From 1fbcdcdf987a28541524e4f23ddc60fc942633ea Mon Sep 17 00:00:00 2001 From: "Ben V. Brown" <5425387+Ralim@users.noreply.github.com> Date: Fri, 19 Aug 2022 15:39:37 +1000 Subject: [PATCH] Pinecil V2 (#1341) * Add SDK * fork * massaging makefile * Drop git module * Bring in sdk as its broken Far, Far to much crap to fix with regex now * Remove bl706 * rf_para_flash_t is missing defs * Remove crapton of junk * Remove yet more * Poking I2C * Update peripheral_config.h * Update pinmux_config.h * Update preRTOS.cpp * Update main.hpp * Setup template * Verbose boot * I2C ish * Update I2C_Wrapper.cpp * Update main.cpp * Turn off I2C reading for now * Display running * Roughing out scheduling timer0 * Starting ADC setup * Working scheduling of ADC :tada: * Format adc headers * Update IRQ.cpp * Buttons working * Slow down I2C * Poking IRQ * Larger stack required * Accel on * Trying to chase down why __libc_init_array isnt working yet * Working c++ * Cleanup * Bump stacks * I2C wake part workaround * Cleanup * Working PWM init * qc draft * Hookup PWM * Stable enough ADC * ADC timing faster + timer without HAL * Silence * Remove boot banner * Tuning in ADC * Wake PID after ADC * Remove unused hal * Draft flash settings * Working settings save & restore * Update to prod model * Cleanup * NTC thermistor * Correct adc gain * Rough tip resistance progress * Scratch out resistance awareness of the tip * better adc settings * Tweaking ADC * ADC tweaking * Make adc range scalable * Update Dockerfile * Update configuration.h * Can read same ADC twice in a row * ADC Setup * Update PIDThread.cpp * Lesser adc backoff * Update USBPD.h * Add device ID * Update BSP_Power.h * Update BSP.cpp * DrawHex dynamicLength * Shorter ID padding * Show validation code * tip measurement * Create access for w0w1 * Expose w0 w1 * Enable debug * crc32 * Device validation * wip starting epr * Logic refactor * Safer PWM Init * PD cleanups * Update bl702_pwm.c * Update power.cpp * Update usb-pd * io * EPR decode * Better gui for showing pd specs * Rough handler for capabilities * EPR * Fix > 25V input * Perform pow step after PPS * Update BSP.cpp * Fix timer output * QC3 * Add tip resistance view * Hold PD negotiation until detection is done for tip res * Get Thermal mass * Tip res =0 protection * Update PIDThread.cpp * Update GUIThread.cpp * Rewrite tip resistance measurement * Update GUIThread.cpp * Fix fallback * Far better tip resistance measurement * Fix QC 0.6V D- * Convert the interpolator to int32 * Correct the NTC lookup * Update BSP.cpp * Update Setup.cpp * . Update configuration #defines More backported functions * Update usb-pd * More missed updates * Refactor BSP Magic BSP -> PinecilV2 Pine64 BSP -> Pinecil Update Makefile * Add Pinecilv2 to CI * Pinecil v2 multi-lang Update push.yml * Update HallSensor.md * Update README.md * Fix wrong prestartcheck default * Fix logo mapping * Update Makefile * Remove unused font block * Style * Style * Remove unused timer funcs * More culling TS80P * Revert "More culling TS80P" This reverts commit 2078b89be7fb244144c4494856f355445e3f8b92. * Revert "Remove unused timer funcs" This reverts commit 0c693a89cc187588ba3525c6b55a656c42781f19. * Make VBus check maskable * Remove DMA half transfer * Drop using brightness and invert icons and go back to text Saves flash space * Refactor settings UI drawing descriptions * Shorten setting function names * Store bin file assets * Fix MHP prestart --- .github/workflows/push.yml | 12 +- .gitignore | 3 +- Documentation/HallSensor.md | 18 +- README.md | 32 +- Translations/make_translation.py | 3 +- Translations/translations_def.js | 824 +- source/Core/BSP/BSP.h | 6 + source/Core/BSP/BSP_Power.h | 4 +- source/Core/BSP/MHP30/BSP.cpp | 10 +- .../Src/stm32f1xx_hal_gpio.c | 16 +- source/Core/BSP/MHP30/configuration.h | 4 + source/Core/BSP/Miniware/BSP.cpp | 8 +- source/Core/BSP/Miniware/ThermoModel.cpp | 4 +- .../Src/stm32f1xx_hal_dma.c | 13 +- .../Src/stm32f1xx_hal_gpio.c | 16 +- source/Core/BSP/Miniware/configuration.h | 341 +- source/Core/BSP/{Pine64 => Pinecil}/BSP.cpp | 8 +- source/Core/BSP/{Pine64 => Pinecil}/Debug.cpp | 0 source/Core/BSP/{Pine64 => Pinecil}/Debug.h | 0 .../BSP/{Pine64 => Pinecil}/FreeRTOSConfig.h | 0 .../BSP/{Pine64 => Pinecil}/I2C_Wrapper.cpp | 0 source/Core/BSP/{Pine64 => Pinecil}/IRQ.cpp | 0 source/Core/BSP/{Pine64 => Pinecil}/IRQ.h | 0 source/Core/BSP/{Pine64 => Pinecil}/NOTES.md | 0 source/Core/BSP/{Pine64 => Pinecil}/Pins.h | 0 source/Core/BSP/{Pine64 => Pinecil}/Power.cpp | 0 .../Core/BSP/{Pine64 => Pinecil}/QC_GPIO.cpp | 0 source/Core/BSP/{Pine64 => Pinecil}/README.md | 0 source/Core/BSP/{Pine64 => Pinecil}/Setup.cpp | 0 source/Core/BSP/{Pine64 => Pinecil}/Setup.h | 0 .../BSP/{Pine64 => Pinecil}/ThermoModel.cpp | 2 +- .../BSP/{Pine64 => Pinecil}/UnitSettings.h | 0 .../NMSIS/Core/Include/core_compatiable.h | 0 .../NMSIS/Core/Include/core_feature_base.h | 0 .../NMSIS/Core/Include/core_feature_cache.h | 0 .../NMSIS/Core/Include/core_feature_dsp.h | 0 .../NMSIS/Core/Include/core_feature_eclic.h | 0 .../NMSIS/Core/Include/core_feature_fpu.h | 0 .../NMSIS/Core/Include/core_feature_pmp.h | 0 .../NMSIS/Core/Include/core_feature_timer.h | 0 .../NMSIS/Core/Include/nmsis_compiler.h | 0 .../Vendor/NMSIS/Core/Include/nmsis_core.h | 0 .../Vendor/NMSIS/Core/Include/nmsis_gcc.h | 0 .../Vendor/NMSIS/Core/Include/nmsis_version.h | 0 .../Vendor/NMSIS/Core/Include/riscv_bits.h | 0 .../NMSIS/Core/Include/riscv_encoding.h | 0 .../OS/FreeRTOS/Source/portable/GCC/port.c | 0 .../OS/FreeRTOS/Source/portable/GCC/portasm.S | 0 .../FreeRTOS/Source/portable/GCC/portmacro.h | 0 .../Source/GCC/gcc_gd32vf103_flashxip.ld | 0 .../Board/pinecil/openocd_gd32vf103.cfg | 0 .../Common/Include/Usb/drv_usb_core.h | 0 .../Common/Include/Usb/drv_usb_dev.h | 0 .../Common/Include/Usb/drv_usb_host.h | 0 .../gd32vf103/Common/Include/Usb/drv_usb_hw.h | 0 .../Common/Include/Usb/drv_usb_regs.h | 0 .../Common/Include/Usb/drv_usbd_int.h | 0 .../Common/Include/Usb/drv_usbh_int.h | 0 .../Common/Include/Usb/usb_ch9_std.h | 0 .../gd32vf103/Common/Include/Usb/usb_conf.h | 0 .../gd32vf103/Common/Include/Usb/usbd_conf.h | 0 .../gd32vf103/Common/Include/Usb/usbd_core.h | 0 .../gd32vf103/Common/Include/Usb/usbd_enum.h | 0 .../Common/Include/Usb/usbd_transc.h | 0 .../gd32vf103/Common/Include/Usb/usbh_conf.h | 0 .../gd32vf103/Common/Include/Usb/usbh_core.h | 0 .../gd32vf103/Common/Include/Usb/usbh_enum.h | 0 .../gd32vf103/Common/Include/Usb/usbh_pipe.h | 0 .../Common/Include/Usb/usbh_transc.h | 0 .../SoC/gd32vf103/Common/Include/gd32vf103.h | 0 .../gd32vf103/Common/Include/gd32vf103_adc.h | 0 .../gd32vf103/Common/Include/gd32vf103_bkp.h | 0 .../gd32vf103/Common/Include/gd32vf103_crc.h | 0 .../gd32vf103/Common/Include/gd32vf103_dac.h | 0 .../gd32vf103/Common/Include/gd32vf103_dbg.h | 0 .../gd32vf103/Common/Include/gd32vf103_dma.h | 0 .../Common/Include/gd32vf103_eclic.h | 0 .../gd32vf103/Common/Include/gd32vf103_exmc.h | 0 .../gd32vf103/Common/Include/gd32vf103_exti.h | 0 .../gd32vf103/Common/Include/gd32vf103_fmc.h | 0 .../Common/Include/gd32vf103_fwdgt.h | 0 .../gd32vf103/Common/Include/gd32vf103_gpio.h | 0 .../gd32vf103/Common/Include/gd32vf103_i2c.h | 0 .../Common/Include/gd32vf103_libopt.h | 0 .../gd32vf103/Common/Include/gd32vf103_pmu.h | 0 .../gd32vf103/Common/Include/gd32vf103_rcu.h | 0 .../gd32vf103/Common/Include/gd32vf103_rtc.h | 0 .../gd32vf103/Common/Include/gd32vf103_spi.h | 0 .../Common/Include/gd32vf103_timer.h | 0 .../Common/Include/gd32vf103_usart.h | 0 .../Common/Include/gd32vf103_wwdgt.h | 0 .../SoC/gd32vf103/Common/Include/n200_func.h | 0 .../gd32vf103/Common/Include/nuclei_sdk_soc.h | 0 .../Common/Include/system_gd32vf103.h | 0 .../Common/Source/Drivers/Usb/drv_usb_core.c | 0 .../Common/Source/Drivers/Usb/drv_usb_dev.c | 0 .../Common/Source/Drivers/Usb/drv_usb_host.c | 0 .../Common/Source/Drivers/Usb/drv_usbd_int.c | 0 .../Common/Source/Drivers/Usb/drv_usbh_int.c | 4 +- .../Source/Drivers/Usb/gd32vf103_usb_hw.c | 0 .../Common/Source/Drivers/Usb/usbd_core.c | 0 .../Common/Source/Drivers/Usb/usbd_enum.c | 0 .../Common/Source/Drivers/Usb/usbd_transc.c | 0 .../Common/Source/Drivers/Usb/usbh_core.c | 0 .../Common/Source/Drivers/Usb/usbh_enum.c | 0 .../Common/Source/Drivers/Usb/usbh_pipe.c | 0 .../Common/Source/Drivers/Usb/usbh_transc.c | 0 .../Common/Source/Drivers/gd32vf103_adc.c | 0 .../Common/Source/Drivers/gd32vf103_bkp.c | 0 .../Common/Source/Drivers/gd32vf103_crc.c | 0 .../Common/Source/Drivers/gd32vf103_dac.c | 0 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| 43 + source/Core/BSP/Pinecilv2/Power.cpp | 40 + source/Core/BSP/Pinecilv2/QC_GPIO.cpp | 61 + source/Core/BSP/Pinecilv2/README.md | 3 + source/Core/BSP/Pinecilv2/Setup.cpp | 157 + source/Core/BSP/Pinecilv2/Setup.h | 35 + source/Core/BSP/Pinecilv2/ThermoModel.cpp | 72 + source/Core/BSP/Pinecilv2/UnitSettings.h | 11 + source/Core/BSP/Pinecilv2/bl702_config.h | 31 + source/Core/BSP/Pinecilv2/bl_mcu_sdk/LICENSE | 202 + .../BSP/Pinecilv2/bl_mcu_sdk/ReleaseNotes | 235 + .../bsp/bsp_common/platform/bflb_platform.c | 267 + .../bsp/bsp_common/platform/bflb_platform.h | 110 + .../bsp/bsp_common/platform/syscalls.c | 219 + .../bsp/bsp_common/usb/uart_interface.c | 194 + .../bsp/bsp_common/usb/uart_interface.h | 44 + .../bl_mcu_sdk/bsp/bsp_common/usb/usb_dc.c | 82 + .../bl_mcu_sdk/common/CMakeLists.txt | 62 + .../common/bl_math/arm_dsp_wrapper.c | 50 + .../common/bl_math/arm_dsp_wrapper.h | 44 + .../bl_mcu_sdk/common/device/drv_device.c | 294 + .../bl_mcu_sdk/common/device/drv_device.h | 135 + .../bl_mcu_sdk/common/list/drv_list.h | 472 + .../bl_mcu_sdk/common/misc/compiler/common.h | 65 + .../bl_mcu_sdk/common/misc/compiler/gcc.h | 112 + .../Pinecilv2/bl_mcu_sdk/common/misc/misc.c | 253 + .../Pinecilv2/bl_mcu_sdk/common/misc/misc.h | 131 + .../bl_mcu_sdk/common/partition/partition.c | 544 + .../bl_mcu_sdk/common/partition/partition.h | 209 + .../BSP/Pinecilv2/bl_mcu_sdk/common/pid/pid.c | 68 + .../BSP/Pinecilv2/bl_mcu_sdk/common/pid/pid.h | 50 + .../common/ring_buffer/ring_buffer.c | 679 + .../common/ring_buffer/ring_buffer.h | 116 + .../bl_mcu_sdk/common/soft_crc/softcrc.c | 194 + .../bl_mcu_sdk/common/soft_crc/softcrc.h | 32 + .../bl_mcu_sdk/common/timestamp/timestamp.c | 136 + .../bl_mcu_sdk/common/timestamp/timestamp.h | 45 + .../gcc/risc-v/bl702/FreeRTOSConfig.h | 112 + ...freertos_risc_v_chip_specific_extensions.h | 67 + .../freertos/portable/gcc/risc-v/bl702/port.c | 195 + .../portable/gcc/risc-v/bl702/portASM.S | 452 + .../portable/gcc/risc-v/bl702/portmacro.h | 164 + .../components/freertos/portable/readme.txt | 20 + .../components/nmsis/CMakeLists.txt | 46 + .../nmsis/core/inc/core_compatiable.h | 226 + .../nmsis/core/inc/core_feature_base.h | 1407 + .../nmsis/core/inc/core_feature_cache.h | 1391 + .../nmsis/core/inc/core_feature_dsp.h | 18667 +++++++++++++ .../nmsis/core/inc/core_feature_eclic.h | 897 + .../nmsis/core/inc/core_feature_fpu.h | 304 + .../nmsis/core/inc/core_feature_pmp.h | 260 + .../nmsis/core/inc/core_feature_timer.h | 364 + .../nmsis/core/inc/nmsis_compiler.h | 37 + .../components/nmsis/core/inc/nmsis_core.h | 87 + .../components/nmsis/core/inc/nmsis_gcc.h | 269 + .../components/nmsis/core/inc/nmsis_version.h | 87 + .../components/nmsis/core/inc/riscv_bits.h | 94 + .../nmsis/core/inc/riscv_encoding.h | 690 + .../components/usb_stack/CMakeLists.txt | 52 + .../usb_stack/class/audio/usbd_audio.c | 114 + .../usb_stack/class/audio/usbd_audio.h | 277 + .../components/usb_stack/class/cdc/usbd_cdc.c | 171 + .../components/usb_stack/class/cdc/usbd_cdc.h | 442 + .../components/usb_stack/class/hid/usbd_hid.c | 286 + .../components/usb_stack/class/hid/usbd_hid.h | 360 + .../components/usb_stack/class/msc/usbd_msc.c | 1004 + .../components/usb_stack/class/msc/usbd_msc.h | 109 + .../usb_stack/class/msc/usbd_scsi.h | 325 + .../usb_stack/class/video/usbd_video.c | 134 + .../usb_stack/class/video/usbd_video.h | 821 + .../usb_stack/class/webusb/usbd_webusb.h | 22 + .../usb_stack/class/winusb/usbd_winusb.h | 26 + .../components/usb_stack/common/usb_dc.h | 197 + .../components/usb_stack/common/usb_def.h | 566 + .../components/usb_stack/common/usb_slist.h | 224 + .../components/usb_stack/common/usb_util.h | 150 + .../components/usb_stack/core/usbd_core.c | 1269 + .../components/usb_stack/core/usbd_core.h | 138 + .../drivers/bl702_driver/CMakeLists.txt | 64 + .../drivers/bl702_driver/bl702_flash.ld | 299 + .../drivers/bl702_driver/cpu_flags.cmake | 11 + .../hal_drv/default_config/adc_config.h | 17 + .../hal_drv/default_config/dac_config.h | 7 + .../hal_drv/default_config/i2s_config.h | 11 + .../hal_drv/default_config/uart_config.h | 16 + .../bl702_driver/hal_drv/inc/hal_adc.h | 185 + .../bl702_driver/hal_drv/inc/hal_boot2.h | 273 + .../bl702_driver/hal_drv/inc/hal_clock.h | 95 + .../bl702_driver/hal_drv/inc/hal_common.h | 46 + .../bl702_driver/hal_drv/inc/hal_dma.h | 190 + .../bl702_driver/hal_drv/inc/hal_flash.h | 50 + .../bl702_driver/hal_drv/inc/hal_gpio.h | 96 + .../bl702_driver/hal_drv/inc/hal_i2c.h | 75 + .../bl702_driver/hal_drv/inc/hal_mtimer.h | 42 + .../drivers/bl702_driver/hal_drv/inc/hal_pm.h | 75 + .../bl702_driver/hal_drv/inc/hal_pm_util.h | 33 + .../bl702_driver/hal_drv/inc/hal_rtc.h | 39 + .../bl702_driver/hal_drv/inc/hal_sec_aes.h | 62 + .../bl702_driver/hal_drv/inc/hal_sec_dsa.h | 63 + .../bl702_driver/hal_drv/inc/hal_sec_ecdsa.h | 69 + .../bl702_driver/hal_drv/inc/hal_sec_hash.h | 72 + .../bl702_driver/hal_drv/inc/hal_uart.h | 136 + .../bl702_driver/hal_drv/inc/hal_usb.h | 236 + .../bl702_driver/hal_drv/inc/hal_wdt.h | 64 + .../bl702_driver/hal_drv/src/hal_boot2.c | 477 + .../bl702_driver/hal_drv/src/hal_clock.c | 660 + .../bl702_driver/hal_drv/src/hal_common.c | 104 + .../bl702_driver/hal_drv/src/hal_dma.c | 431 + .../bl702_driver/hal_drv/src/hal_flash.c | 346 + .../bl702_driver/hal_drv/src/hal_gpio.c | 224 + .../bl702_driver/hal_drv/src/hal_i2c.c | 172 + .../bl702_driver/hal_drv/src/hal_mtimer.c | 143 + .../drivers/bl702_driver/hal_drv/src/hal_pm.c | 1351 + .../bl702_driver/hal_drv/src/hal_pm_util.c | 321 + .../bl702_driver/hal_drv/src/hal_rtc.c | 101 + .../bl702_driver/hal_drv/src/hal_sec_aes.c | 119 + .../bl702_driver/hal_drv/src/hal_sec_dsa.c | 389 + .../bl702_driver/hal_drv/src/hal_sec_ecdsa.c | 1450 + .../bl702_driver/hal_drv/src/hal_sec_hash.c | 387 + .../bl702_driver/hal_drv/src/hal_uart.c | 442 + .../bl702_driver/hal_drv/src/hal_usb.c | 1173 + .../bl702_driver/hal_drv/src/hal_wdt.c | 179 + .../drivers/bl702_driver/regs/aon_reg.h | 1579 ++ .../drivers/bl702_driver/regs/bl702.h | 307 + .../drivers/bl702_driver/regs/bl70x_reg.svc | 4968 ++++ .../drivers/bl702_driver/regs/cam_reg.h | 1203 + .../drivers/bl702_driver/regs/cci_reg.h | 192 + .../drivers/bl702_driver/regs/cks_reg.h | 105 + .../drivers/bl702_driver/regs/dma_reg.h | 2232 ++ .../drivers/bl702_driver/regs/ef_ctrl_reg.h | 812 + .../drivers/bl702_driver/regs/ef_data_0_reg.h | 762 + .../drivers/bl702_driver/regs/emac_reg.h | 601 + .../drivers/bl702_driver/regs/glb_reg.h | 5498 ++++ .../drivers/bl702_driver/regs/gpip_reg.h | 317 + .../drivers/bl702_driver/regs/hbn_reg.h | 814 + .../drivers/bl702_driver/regs/i2c_reg.h | 557 + .../drivers/bl702_driver/regs/i2s_reg.h | 455 + .../drivers/bl702_driver/regs/ir_reg.h | 652 + .../drivers/bl702_driver/regs/kys_reg.h | 194 + .../drivers/bl702_driver/regs/l1c_reg.h | 366 + .../drivers/bl702_driver/regs/mjpeg_reg.h | 1726 ++ .../drivers/bl702_driver/regs/pdm_reg.h | 351 + .../drivers/bl702_driver/regs/pds_reg.h | 1411 + .../drivers/bl702_driver/regs/pwm_reg.h | 993 + .../drivers/bl702_driver/regs/qdec_reg.h | 768 + .../drivers/bl702_driver/regs/sec_dbg_reg.h | 217 + .../drivers/bl702_driver/regs/sec_eng_reg.h | 3529 +++ .../drivers/bl702_driver/regs/sf_ctrl_reg.h | 2735 ++ .../drivers/bl702_driver/regs/soc702_reg.svd | 22548 ++++++++++++++++ .../drivers/bl702_driver/regs/spi_reg.h | 521 + .../drivers/bl702_driver/regs/timer_reg.h | 852 + .../drivers/bl702_driver/regs/tzc_sec_reg.h | 256 + .../drivers/bl702_driver/regs/uart_reg.h | 769 + .../drivers/bl702_driver/regs/usb_reg.h | 2758 ++ .../bl702_driver/risc-v/Core/Include/clic.h | 21 + .../risc-v/Core/Include/riscv_bits.h | 36 + .../risc-v/Core/Include/riscv_const.h | 18 + .../risc-v/Core/Include/riscv_encoding.h | 1360 + .../drivers/bl702_driver/startup/GCC/entry.S | 131 + .../bl702_driver/startup/GCC/start_load.c | 114 + .../drivers/bl702_driver/startup/interrupt.c | 368 + .../bl702_driver/startup/system_bl702.c | 139 + .../bl702_driver/startup/system_bl702.h | 45 + .../bl702_driver/std_drv/inc/bl702_acomp.h | 213 + .../bl702_driver/std_drv/inc/bl702_adc.h | 485 + .../bl702_driver/std_drv/inc/bl702_aon.h | 112 + .../bl702_driver/std_drv/inc/bl702_cam.h | 293 + .../bl702_driver/std_drv/inc/bl702_clock.h | 115 + .../bl702_driver/std_drv/inc/bl702_common.h | 82 + .../bl702_driver/std_drv/inc/bl702_dac.h | 290 + .../bl702_driver/std_drv/inc/bl702_dma.h | 366 + .../bl702_driver/std_drv/inc/bl702_ef_ctrl.h | 310 + .../bl702_driver/std_drv/inc/bl702_emac.h | 306 + .../bl702_driver/std_drv/inc/bl702_glb.h | 822 + .../bl702_driver/std_drv/inc/bl702_gpio.h | 950 + .../bl702_driver/std_drv/inc/bl702_hbn.h | 564 + .../bl702_driver/std_drv/inc/bl702_i2c.h | 199 + .../std_drv/inc/bl702_i2c_gpio_sim.h | 79 + .../bl702_driver/std_drv/inc/bl702_i2s.h | 295 + .../bl702_driver/std_drv/inc/bl702_ir.h | 257 + .../bl702_driver/std_drv/inc/bl702_kys.h | 124 + .../bl702_driver/std_drv/inc/bl702_l1c.h | 203 + .../bl702_driver/std_drv/inc/bl702_mjpeg.h | 229 + .../bl702_driver/std_drv/inc/bl702_nf_cfg.h | 48 + .../bl702_driver/std_drv/inc/bl702_nflash.h | 196 + .../bl702_driver/std_drv/inc/bl702_pds.h | 798 + .../bl702_driver/std_drv/inc/bl702_psram.h | 175 + .../bl702_driver/std_drv/inc/bl702_pwm.h | 197 + .../bl702_driver/std_drv/inc/bl702_qdec.h | 283 + .../std_drv/inc/bl702_romdriver.h | 632 + .../bl702_driver/std_drv/inc/bl702_sec_dbg.h | 82 + .../bl702_driver/std_drv/inc/bl702_sec_eng.h | 580 + .../bl702_driver/std_drv/inc/bl702_sf_cfg.h | 125 + .../std_drv/inc/bl702_sf_cfg_ext.h | 83 + .../bl702_driver/std_drv/inc/bl702_sf_ctrl.h | 410 + .../bl702_driver/std_drv/inc/bl702_sflash.h | 197 + .../std_drv/inc/bl702_sflash_ext.h | 104 + .../bl702_driver/std_drv/inc/bl702_spi.h | 317 + .../bl702_driver/std_drv/inc/bl702_timer.h | 247 + .../bl702_driver/std_drv/inc/bl702_uart.h | 326 + .../bl702_driver/std_drv/inc/bl702_usb.h | 423 + .../std_drv/inc/bl702_xip_sflash.h | 95 + .../std_drv/inc/bl702_xip_sflash_ext.h | 86 + .../bl702_driver/std_drv/src/bl702_acomp.c | 202 + .../bl702_driver/std_drv/src/bl702_adc.c | 1520 ++ .../bl702_driver/std_drv/src/bl702_aon.c | 582 + .../bl702_driver/std_drv/src/bl702_cam.c | 762 + .../bl702_driver/std_drv/src/bl702_clock.c | 166 + .../bl702_driver/std_drv/src/bl702_common.c | 204 + .../bl702_driver/std_drv/src/bl702_dac.c | 518 + .../bl702_driver/std_drv/src/bl702_dma.c | 750 + .../bl702_driver/std_drv/src/bl702_ef_ctrl.c | 1638 ++ .../bl702_driver/std_drv/src/bl702_emac.c | 687 + .../bl702_driver/std_drv/src/bl702_glb.c | 4038 +++ .../bl702_driver/std_drv/src/bl702_hbn.c | 2030 ++ .../bl702_driver/std_drv/src/bl702_i2c.c | 822 + .../std_drv/src/bl702_i2c_gpio_sim.c | 457 + .../bl702_driver/std_drv/src/bl702_i2s.c | 469 + .../bl702_driver/std_drv/src/bl702_ir.c | 1156 + .../bl702_driver/std_drv/src/bl702_kys.c | 274 + .../bl702_driver/std_drv/src/bl702_l1c.c | 665 + .../bl702_driver/std_drv/src/bl702_mjpeg.c | 740 + .../bl702_driver/std_drv/src/bl702_pds.c | 1355 + .../bl702_driver/std_drv/src/bl702_psram.c | 764 + .../bl702_driver/std_drv/src/bl702_pwm.c | 588 + .../bl702_driver/std_drv/src/bl702_qdec.c | 548 + .../bl702_driver/std_drv/src/bl702_romapi.c | 1106 + .../std_drv/src/bl702_romdriver.c | 246 + .../bl702_driver/std_drv/src/bl702_sec_dbg.c | 151 + .../bl702_driver/std_drv/src/bl702_sec_eng.c | 3387 +++ .../bl702_driver/std_drv/src/bl702_sf_cfg.c | 2404 ++ .../std_drv/src/bl702_sf_cfg_ext.c | 705 + .../bl702_driver/std_drv/src/bl702_sf_ctrl.c | 1449 + .../bl702_driver/std_drv/src/bl702_sflash.c | 1489 + .../std_drv/src/bl702_sflash_ext.c | 274 + .../bl702_driver/std_drv/src/bl702_spi.c | 1811 ++ .../bl702_driver/std_drv/src/bl702_timer.c | 894 + .../bl702_driver/std_drv/src/bl702_uart.c | 1226 + .../bl702_driver/std_drv/src/bl702_usb.c | 2491 ++ .../std_drv/src/bl702_xip_sflash.c | 404 + .../std_drv/src/bl702_xip_sflash_ext.c | 139 + source/Core/BSP/Pinecilv2/board.c | 261 + source/Core/BSP/Pinecilv2/clock_config.h | 64 + source/Core/BSP/Pinecilv2/configuration.h | 161 + source/Core/BSP/Pinecilv2/crc32.h | 29 + source/Core/BSP/Pinecilv2/flash.c | 23 + source/Core/BSP/Pinecilv2/fusb_user.cpp | 27 + source/Core/BSP/Pinecilv2/peripheral_config.h | 266 + source/Core/BSP/Pinecilv2/pinmux_config.h | 178 + source/Core/BSP/Pinecilv2/postRTOS.cpp | 29 + source/Core/BSP/Pinecilv2/preRTOS.cpp | 24 + source/Core/Drivers/Font.h | 65 +- source/Core/Drivers/OLED.cpp | 6 +- source/Core/Drivers/OLED.hpp | 2 +- source/Core/Drivers/TipThermoModel.cpp | 9 +- source/Core/Drivers/USBPD.cpp | 4 + source/Core/Drivers/Utils.cpp | 2 +- source/Core/Drivers/Utils.h | 2 +- source/Core/Inc/Translation.h | 1 + source/Core/Inc/expMovingAverage.h | 1 - source/Core/Inc/history.hpp | 2 +- source/Core/Inc/main.hpp | 2 +- source/Core/Inc/settingsGUI.hpp | 4 +- source/Core/Src/FreeRTOSHooks.c | 2 +- source/Core/Src/main.cpp | 13 +- source/Core/Src/power.cpp | 8 +- source/Core/Src/settingsGUI.cpp | 406 +- source/Core/Threads/GUIThread.cpp | 56 +- source/Core/Threads/PIDThread.cpp | 6 +- source/Core/Threads/POWThread.cpp | 10 +- source/Makefile | 178 +- .../FreeRTOS/Source/include/mpu_prototypes.h | 160 - .../FreeRTOS/Source/include/mpu_wrappers.h | 189 - .../FreeRTOS/Source/include/portable.h | 77 +- source/build.sh | 2 +- 428 files changed, 165913 insertions(+), 1380 deletions(-) rename source/Core/BSP/{Pine64 => Pinecil}/BSP.cpp (89%) rename source/Core/BSP/{Pine64 => Pinecil}/Debug.cpp (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Debug.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/FreeRTOSConfig.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/I2C_Wrapper.cpp (100%) rename source/Core/BSP/{Pine64 => Pinecil}/IRQ.cpp (100%) rename source/Core/BSP/{Pine64 => Pinecil}/IRQ.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/NOTES.md (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Pins.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Power.cpp (100%) rename source/Core/BSP/{Pine64 => Pinecil}/QC_GPIO.cpp (100%) rename source/Core/BSP/{Pine64 => Pinecil}/README.md (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Setup.cpp (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Setup.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/ThermoModel.cpp (93%) rename source/Core/BSP/{Pine64 => Pinecil}/UnitSettings.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/NMSIS/Core/Include/core_compatiable.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/NMSIS/Core/Include/core_feature_base.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/NMSIS/Core/Include/core_feature_cache.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/NMSIS/Core/Include/core_feature_dsp.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/NMSIS/Core/Include/core_feature_eclic.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/NMSIS/Core/Include/core_feature_fpu.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/NMSIS/Core/Include/core_feature_pmp.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/NMSIS/Core/Include/core_feature_timer.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/NMSIS/Core/Include/nmsis_compiler.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/NMSIS/Core/Include/nmsis_core.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/NMSIS/Core/Include/nmsis_gcc.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/NMSIS/Core/Include/nmsis_version.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/NMSIS/Core/Include/riscv_bits.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/NMSIS/Core/Include/riscv_encoding.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/OS/FreeRTOS/Source/portable/GCC/port.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/OS/FreeRTOS/Source/portable/GCC/portasm.S (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/OS/FreeRTOS/Source/portable/GCC/portmacro.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Board/pinecil/Source/GCC/gcc_gd32vf103_flashxip.ld (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Board/pinecil/openocd_gd32vf103.cfg (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_core.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_dev.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_host.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_hw.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_regs.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usbd_int.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usbh_int.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/Usb/usb_ch9_std.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/Usb/usb_conf.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_conf.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_core.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_enum.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_transc.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_conf.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_core.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_enum.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_pipe.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_transc.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/gd32vf103.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_adc.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_bkp.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_crc.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_dac.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_dbg.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_dma.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_eclic.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_exmc.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_exti.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_fmc.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_fwdgt.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_gpio.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_i2c.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_libopt.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_pmu.h (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_rcu.h (100%) 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Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usb_dev.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usb_host.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usbd_int.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usbh_int.c (95%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/gd32vf103_usb_hw.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_core.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_enum.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_transc.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_core.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_enum.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_pipe.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_transc.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_adc.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_bkp.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_crc.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_dac.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_dbg.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_dma.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_eclic.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_exmc.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_exti.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_fmc.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_fwdgt.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_gpio.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_i2c.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_pmu.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_rcu.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_rtc.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_spi.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_timer.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_usart.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_wwdgt.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Drivers/n200_func.c (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/GCC/intexc_gd32vf103.S (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/GCC/startup_gd32vf103.S (100%) rename source/Core/BSP/{Pine64 => Pinecil}/Vendor/SoC/gd32vf103/Common/Source/Stubs/close.c (100%) rename source/Core/BSP/{Pine64 => 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source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_pds.h create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_psram.h create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_pwm.h create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_qdec.h create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_romdriver.h create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sec_dbg.h create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sec_eng.h create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sf_cfg.h create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sf_cfg_ext.h create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sf_ctrl.h create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sflash.h create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sflash_ext.h create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_spi.h create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_timer.h create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_uart.h create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_usb.h create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_xip_sflash.h create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_xip_sflash_ext.h create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_acomp.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_adc.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_aon.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_cam.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_clock.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_common.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_dac.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_dma.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_ef_ctrl.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_emac.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_glb.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_hbn.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_i2c.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_i2c_gpio_sim.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_i2s.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_ir.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_kys.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_l1c.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_mjpeg.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_pds.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_psram.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_pwm.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_qdec.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_romapi.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_romdriver.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sec_dbg.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sec_eng.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sf_cfg.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sf_cfg_ext.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sf_ctrl.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sflash.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sflash_ext.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_spi.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_timer.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_uart.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_usb.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_xip_sflash.c create mode 100644 source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_xip_sflash_ext.c create mode 100644 source/Core/BSP/Pinecilv2/board.c create mode 100644 source/Core/BSP/Pinecilv2/clock_config.h create mode 100644 source/Core/BSP/Pinecilv2/configuration.h create mode 100644 source/Core/BSP/Pinecilv2/crc32.h create mode 100644 source/Core/BSP/Pinecilv2/flash.c create mode 100644 source/Core/BSP/Pinecilv2/fusb_user.cpp create mode 100644 source/Core/BSP/Pinecilv2/peripheral_config.h create mode 100644 source/Core/BSP/Pinecilv2/pinmux_config.h create mode 100644 source/Core/BSP/Pinecilv2/postRTOS.cpp create mode 100644 source/Core/BSP/Pinecilv2/preRTOS.cpp delete mode 100644 source/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h delete mode 100644 source/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h diff --git a/.github/workflows/push.yml b/.github/workflows/push.yml index 5720a006..6bda0d65 100644 --- a/.github/workflows/push.yml +++ b/.github/workflows/push.yml @@ -9,7 +9,7 @@ jobs: image: alpine:3.16 strategy: matrix: - model: ["TS100", "TS80", "TS80P", "Pinecil", "MHP30"] + model: ["TS100", "TS80", "TS80P", "Pinecil", "MHP30", "Pinecilv2"] fail-fast: true steps: @@ -41,6 +41,7 @@ jobs: path: | source/Hexfile/${{ matrix.model }}_*.hex source/Hexfile/${{ matrix.model }}_*.dfu + source/Hexfile/${{ matrix.model }}_*.bin source/Hexfile/LICENSE source/Hexfile/LICENSE_RELEASE.md if-no-files-found: error @@ -60,12 +61,12 @@ jobs: image: alpine:3.16 strategy: matrix: - model: ["Pinecil"] + model: ["Pinecil", "Pinecilv2"] fail-fast: true steps: - name: Install dependencies (apk) - run: apk add --no-cache gcc-riscv-none-elf gcc-arm-none-eabi newlib-riscv-none-elf newlib-arm-none-eabi findutils python3 py3-pip make git bash musl-dev + run: apk add --no-cache gcc-riscv-none-elf newlib-riscv-none-elf findutils python3 py3-pip make git bash musl-dev - name: Install dependencies (python) run: python3 -m pip install bdflib @@ -91,18 +92,19 @@ jobs: path: | source/Hexfile/${{ matrix.model }}_*.hex source/Hexfile/${{ matrix.model }}_*.dfu + source/Hexfile/${{ matrix.model }}_*.bin source/Hexfile/LICENSE source/Hexfile/LICENSE_RELEASE.md if-no-files-found: error - name: Generate json index file - run: cd source && python3 metadata.py Pinecil_multi-lang.json + run: cd source && python3 metadata.py ${{ matrix.model }}_multi-lang.json - name: Archive ${{ matrix.model }} index file uses: actions/upload-artifact@v3 with: name: metadata - path: source/Hexfile/Pinecil_multi-lang.json + path: source/Hexfile/${{ matrix.model }}_multi-lang.json tests: runs-on: ubuntu-20.04 diff --git a/.gitignore b/.gitignore index a9a7c21a..c7892f41 100644 --- a/.gitignore +++ b/.gitignore @@ -176,4 +176,5 @@ fabric.properties CoreCompileInputs.cache .vscode/settings.json -source/compile_commands.json +source/compile_commands.json +.idea/ diff --git a/Documentation/HallSensor.md b/Documentation/HallSensor.md index b079e0c4..a6e02ba7 100644 --- a/Documentation/HallSensor.md +++ b/Documentation/HallSensor.md @@ -6,15 +6,15 @@ In Sleep mode, the temperature of the iron automatically lowers to 150 °C (defa Simply moving the iron will wake it back up into soldering mode. You can also press any button and this will also wake-up the iron. -### Optional Hall Effect Feature (Pinecil only): +### Optional Hall Effect Feature (Pinecil v1/v2 only): Inside the Sleep Menu is an additional type of sleep setting. Pinecil has an unpopulated footprint (U14) for a hall effect sensor (Si7210). It is possible with the hall sensor to trigger Pinecil to go to sleep after it enters the stand, and Zzzz will appear on the screen. After installing the hall sensor, a magnet is positioned on the stand close enough to the sensor to activate one of ten user selectable settings. - - 0=off, 1=1000, 2=750, 3=500, 4=250, 5=150, 6=100, 7=75, 8=50, 9=25 (9 has the highest sensitivity to magnets) - - Setting of 1 might be used if you solder on PCBs with magnets and do not wish Pinecil to auto-sleep constantly. A very strong/large magnet would be required on the stand to activate the sleep mode if you use setting 1. - - Setting of 9 would be useful if you only had a small magnet and are not concerned about Pinecil falsely triggering sleep mode near magnetized items/tools. - - Neodymium magnets are recommended. If using small magnets, 2-3 may be required, but too many can also be detrimental. - - Actively watch the hall number change (in [debug menu](/Documentation/DebugMenu.md)) while you slowly move the magnet around to seek the best locations & whether you have too many or too few magnets. Positioning the magnet where you have the highest hall number will ensure consistent sleep mode when you place the iron in the stand. This requires some experimenting. - - Sensor is physically located near the copper contacts for the tip at the front of the handle. Reference [Schematics U14](https://files.pine64.org/doc/Pinecil/Pinecil_schematic_v1.0a_20201120.pdf). - - Positioning/type/quantity of magnets is important for best results. Sometimes too many magnets breaks the effect by distorting the magnetic field as seen [here](https://www.youtube.com/shorts/afkqKwCX00I). Video shows magnets at the top of the stand, and the pinecil goes correctly into Zzzz with only those magnets. Adding more magnets at the side, the Pinecil did not go to sleep, see PDF below for details on magnetic fields. - - Orientation of North and South faces of magnets is important to increase reaction of the hall sensor [SI7210-B-00-IV](https://www.silabs.com/documents/public/application-notes/an1018-si72xx-sensors.pdf). +- 0=off, 1=1000, 2=750, 3=500, 4=250, 5=150, 6=100, 7=75, 8=50, 9=25 (9 has the highest sensitivity to magnets) +- Setting of 1 might be used if you solder on PCBs with magnets and do not wish Pinecil to auto-sleep constantly. And a very strong/large magnet would be required on the stand to activate the sensor sleep mode. +- Setting of 9 would be useful if you only had a small magnet and are not concerned about Pinecil falsely triggering sleep mode near magnetized items/tools. +- Neodymium magnets are recommended. If using small magnets, 2-3 may be required, but too many can also be detrimental. +- Actively watch the hall number change (in [debug menu](/Documentation/DebugMenu.md)) while you slowly move the magnet around to seek the best locations & whether you have too many or too few magnets. Positioning the magnet where you have the highest hall number will ensure consistent sleep mode when you place the iron in the stand. This requires some experimenting. +- Sensor is physically located near the copper contacts for the tip at the front of the handle. Reference [Schematics U14](https://files.pine64.org/doc/Pinecil/Pinecil_schematic_v1.0a_20201120.pdf). +- Positioning/type/quantity of magnets is important for best results. Sometimes [too many magnets](https://www.youtube.com/shorts/afkqKwCX00I) breaks the effect by distorting the magnetic field. +- Orientation of North and South faces of magnets is important to increase reaction of the hall sensor [SI7210-B-00-IV](https://www.silabs.com/documents/public/application-notes/an1018-si72xx-sensors.pdf). diff --git a/README.md b/README.md index eae65460..506bc213 100644 --- a/README.md +++ b/README.md @@ -20,22 +20,17 @@ This project is considered feature complete for use as a soldering iron, _so ple _This firmware does **NOT** support the USB port while running for changing settings. This is done through the onscreen menu only. Logos are edited using the tool or python script and uploaded in DFU mode._ - - -| Device | DC | QC | PD | EPR | BLE | Battery | Recommended | -|----------:|:--:|:--:|:--:|:---:|:---:|:-------:|:-----------:| -| MHP30 |❌ | ❌ | ✔️ | ❌ | ❌ | ❌ | ✔️ | -| Pinecil |✔️ | ✔️ | ✔️ | ❌ | ❌ | ✔️ | ✔️ | -| Pinecil 2 |✔️ | ✔️ | ✔️ | ✔️ | ✔️ | ✔️ | ✔️ | -| TS100 |✔️ | ❌ | ❌ | ❌ | ❌ | ✔️ | ❌ | -| TS80 |❌ | ✔️ | ❌ | ❌ | ❌ | ✔️ | ❌ | -| TS80P |❌ | ✔️ | ✔️ | ❌ | ❌ | ✔️ | ✔️ | - - +| Device | DC | QC | PD | EPR | BLE | Battery | Recommended | +| --------: | :-: | :-: | :-: | :-: | :-: | :-----: | :---------: | +| MHP30 | ❌ | ❌ | ✔️ | ❌ | ❌ | ❌ | ✔️ | +| Pinecil | ✔️ | ✔️ | ✔️ | ❌ | ❌ | ✔️ | ✔️ | +| Pinecil 2 | ✔️ | ✔️ | ✔️ | ✔️ | ✔️ | ✔️ | ✔️ | +| TS100 | ✔️ | ❌ | ❌ | ❌ | ❌ | ✔️ | ❌ | +| TS80 | ❌ | ✔️ | ❌ | ❌ | ❌ | ✔️ | ❌ | +| TS80P | ❌ | ✔️ | ✔️ | ❌ | ❌ | ✔️ | ✔️ | Please note that Miniware started shipping TS100's using cloned STM32 Chips. While these do work with IronOS, their DFU bootloader works terribly, and it is hard to get it to successfully flash larger firmware images like IronOS without timing out. This is the main reason why the TS100 is _no longer recommended_. - ## Getting Started To get started with IronOS firmware, please jump to [Getting Started Guide](Documentation/GettingStarted.md). @@ -56,6 +51,7 @@ For notes on installation for your device, please refer to the [Flashing Guide]( - (TS80) Set 18 W or 24 W settings for your power bank - (TS80P) Automatically negotiates appropriate PD and falls back to QC mode like TS80 - (Pinecil) Supports all 3 power modes (PD, QC, DC In). +- (Pinecilv2) Supports USB-PD EPR for 28V operation. - Improved readability Fonts, supporting multiple languages - Use hardware features to improve reliability - Can disable movement detection if desired @@ -70,17 +66,17 @@ For notes on installation for your device, please refer to the [Flashing Guide]( This new firmware uses a new menu system to allow access to the settings on the device. When on the main screen and having the tip plugged in, the unit shows a pair of prompts for the two most common operations. -- Pressing the button near the tip enters the *soldering mode* -- Pressing the button near the USB end enters the *settings menu* -- When not in *soldering mode*, holding down the button near the tip will enter *soldering temperature adjust mode* (This is the same as the one in the *soldering mode*, but allows to adjust the temperature before heating up), in *soldering mode* however this will activate *boost mode* as long as you hold down the button. -- Holding down the button near the USB end will show the *[debug menu](Documentation/DebugMenu.md).* In *soldering mode* this ends the heating. +- Pressing the button near the tip enters the _soldering mode_ +- Pressing the button near the USB end enters the _settings menu_ +- When not in _soldering mode_, holding down the button near the tip will enter _soldering temperature adjust mode_ (This is the same as the one in the _soldering mode_, but allows to adjust the temperature before heating up), in _soldering mode_ however this will activate _boost mode_ as long as you hold down the button. +- Holding down the button near the USB end will show the _[debug menu](Documentation/DebugMenu.md)._ In _soldering mode_ this ends the heating. Operation details are over in the [Menu information.](Documentation/Menu.md) ## Thanks If you love this firmware and want to continue my caffeine addiction, you can do so [here](https://paypal.me/RalimTek) (or email me for other options). -I also want to give a shout out to all of the [Fantastic Contributors](https://github.com/Ralim/ts100/graphs/contributors). +I also want to give a shout out to all of the [Fantastic Contributors](https://github.com/Ralim/IronOS/graphs/contributors). Especially to the following users, who have helped in various ways that are massively appreciated: diff --git a/Translations/make_translation.py b/Translations/make_translation.py index 5c5478ec..c4237715 100755 --- a/Translations/make_translation.py +++ b/Translations/make_translation.py @@ -128,8 +128,9 @@ def get_debug_menu() -> List[str]: "Vin ", "ACC ", "PWR ", - "ID ", + "ID ", "Max ", + "Tip Res", "HW G ", "HW M ", "HW P ", diff --git a/Translations/translations_def.js b/Translations/translations_def.js index 5cb39e8e..b20f9f79 100644 --- a/Translations/translations_def.js +++ b/Translations/translations_def.js @@ -1,433 +1,433 @@ -var def = -{ - "messages": [ - { - "id": "SettingsCalibrationWarning", - "description": "Confirmation message shown before performing an offset calibration. Should warn the user to make sure tip and handle are at the same temperature." - }, - { - "id": "SettingsResetWarning", - "description": "Confirmation message shown before confirming a settings reset." - }, - { - "id": "UVLOWarningString", - "maxLen": 8, - "description": "Warning text shown when the unit turns off due to undervoltage in simple mode." - }, - { - "id": "UndervoltageString", - "maxLen": 15, - "description": "Warning text shown when the unit turns off due to undervoltage in advanced mode." - }, - { - "id": "InputVoltageString", - "maxLen": 11, - "note": "Preferably end with a space", - "description": "Prefix text for 'Input Voltage' shown before showing the input voltage reading." +var def = /// + { + "messages": [{ + "id": "SettingsCalibrationWarning", + "description": "Confirmation message shown before performing an offset calibration. Should warn the user to make sure tip and handle are at the same temperature." + }, + { + "id": "SettingsResetWarning", + "description": "Confirmation message shown before confirming a settings reset." + }, + { + "id": "UVLOWarningString", + "maxLen": 8, + "description": "Warning text shown when the unit turns off due to undervoltage in simple mode." + }, + { + "id": "UndervoltageString", + "maxLen": 15, + "description": "Warning text shown when the unit turns off due to undervoltage in advanced mode." + }, + { + "id": "InputVoltageString", + "maxLen": 11, + "note": "Preferably end with a space", + "description": "Prefix text for 'Input Voltage' shown before showing the input voltage reading." - }, - { - "id": "SleepingSimpleString", - "maxLen": 4, - "description": "The text shown to indicate the unit is in sleep mode when the advanced view is NOT on." - }, - { - "id": "SleepingAdvancedString", - "maxLen": 15, - "description": "The text shown to indicate the unit is in sleep mode when the advanced view is turned on." - }, - { - "id": "SleepingTipAdvancedString", - "maxLen": 6, - "description": "The prefix text shown before tip temperature when the unit is sleeping with advanced view on." - }, - { - "id": "OffString", - "maxLen": 3, - "description": "Shown when a setting is turned off." - } - ], - "messagesWarn": [ - { - "id": "SettingsResetMessage", - "description": "Shown when the settings are reset to factory defaults either by the user or by incompatible firmware changes." - }, - { - "id": "NoAccelerometerMessage", - "description": "No accelerometer could be communicated with. This means that either the device's accelerometer is broken or unknown to IronOS. All motion-based settings are disabled and motion-based features will not work." - }, - { - "id": "NoPowerDeliveryMessage", - "description": "The IC required for USB-PD could not be communicated with. This is an error warning that USB-PD WILL NOT FUNCTION. Generally indicative of either a hardware or software issues." - }, - { - "id": "LockingKeysString", - "description": "Shown when keys are locked" - }, - { - "id": "UnlockingKeysString", - "description": "Shown when keys are unlocked" - }, - { - "id": "WarningKeysLockedString", - "description": "Warning that is shown when input is ignored due to the key lock being on" - }, - { - "id": "WarningThermalRunaway", - "description": "Warning text shown when the software has disabled the heater as a safety precaution as the temperature reading didn't react as expected." - } - ], - "characters": [ - { - "id": "SettingRightChar", - "len": 1, - "description": "Shown for fixed Right-handed display rotation." - }, - { - "id": "SettingLeftChar", - "len": 1, - "description": "Shown for fixed Left-handed display rotation." - }, - { - "id": "SettingAutoChar", - "len": 1, - "description": "Shown for automatic display rotation." - }, - { - "id": "SettingFastChar", - "len": 1, - "description": "Shown when a setting is set to a fast value i.e. animation speed" - }, - { - "id": "SettingSlowChar", - "len": 1, - "description": "Shown when a setting is set to a slow value i.e. animation speed" - }, - { - "id": "SettingMediumChar", - "len": 1, - "description": "Shown when a setting is set to a medium value i.e. animation speed" - }, - { - "id": "SettingOffChar", - "len": 1, - "description": "Shown when a setting is turned off" - }, - { - "id": "SettingStartSolderingChar", - "len": 1, - "description": "Shown when the auto start mode is set to go straight to soldering." - }, - { - "id": "SettingStartSleepChar", - "len": 1, - "description": "Shown when the auto start mode is set to start in sleep mode." + }, + { + "id": "SleepingSimpleString", + "maxLen": 4, + "description": "The text shown to indicate the unit is in sleep mode when the advanced view is NOT on." + }, + { + "id": "SleepingAdvancedString", + "maxLen": 15, + "description": "The text shown to indicate the unit is in sleep mode when the advanced view is turned on." + }, + { + "id": "SleepingTipAdvancedString", + "maxLen": 6, + "description": "The prefix text shown before tip temperature when the unit is sleeping with advanced view on." + }, + { + "id": "OffString", + "maxLen": 3, + "description": "Shown when a setting is turned off." + }, + { + "id": "DeviceFailedValidationWarning", + "default": "Device may be\ncounterfeit", + "description": "Warning shown if the device may be a clone or counterfeit unit." + } + ], + "messagesWarn": [{ + "id": "SettingsResetMessage", + "description": "Shown when the settings are reset to factory defaults either by the user or by incompatible firmware changes." + }, + { + "id": "NoAccelerometerMessage", + "description": "No accelerometer could be communicated with. This means that either the device's accelerometer is broken or unknown to IronOS. All motion-based settings are disabled and motion-based features will not work." + }, + { + "id": "NoPowerDeliveryMessage", + "description": "The IC required for USB-PD could not be communicated with. This is an error warning that USB-PD WILL NOT FUNCTION. Generally indicative of either a hardware or software issues." + }, + { + "id": "LockingKeysString", + "description": "Shown when keys are locked" + }, + { + "id": "UnlockingKeysString", + "description": "Shown when keys are unlocked" + }, + { + "id": "WarningKeysLockedString", + "description": "Warning that is shown when input is ignored due to the key lock being on" + }, + { + "id": "WarningThermalRunaway", + "description": "Warning text shown when the software has disabled the heater as a safety precaution as the temperature reading didn't react as expected." + } + ], + "characters": [{ + "id": "SettingRightChar", + "len": 1, + "description": "Shown for fixed Right-handed display rotation." + }, + { + "id": "SettingLeftChar", + "len": 1, + "description": "Shown for fixed Left-handed display rotation." + }, + { + "id": "SettingAutoChar", + "len": 1, + "description": "Shown for automatic display rotation." + }, + { + "id": "SettingFastChar", + "len": 1, + "description": "Shown when a setting is set to a fast value i.e. animation speed" + }, + { + "id": "SettingSlowChar", + "len": 1, + "description": "Shown when a setting is set to a slow value i.e. animation speed" + }, + { + "id": "SettingMediumChar", + "len": 1, + "description": "Shown when a setting is set to a medium value i.e. animation speed" + }, + { + "id": "SettingOffChar", + "len": 1, + "description": "Shown when a setting is turned off" + }, + { + "id": "SettingStartSolderingChar", + "len": 1, + "description": "Shown when the auto start mode is set to go straight to soldering." + }, + { + "id": "SettingStartSleepChar", + "len": 1, + "description": "Shown when the auto start mode is set to start in sleep mode." - }, - { - "id": "SettingStartSleepOffChar", - "len": 1, - "description": "Shown when the auto start state is set to go to an off state, but on movement wake into soldering mode." + }, + { + "id": "SettingStartSleepOffChar", + "len": 1, + "description": "Shown when the auto start state is set to go to an off state, but on movement wake into soldering mode." - }, - { - "id": "SettingStartNoneChar", - "len": 1, - "description": "Shown when autostart state is to do nothing and go to a normal boot" - }, - { - "id": "SettingSensitivityOff", - "len": 1, - "description": "Shown when a sensitivity (hall effect sensor) is disabled. Turning off the sensor." + }, + { + "id": "SettingStartNoneChar", + "len": 1, + "description": "Shown when autostart state is to do nothing and go to a normal boot" + }, + { + "id": "SettingSensitivityOff", + "len": 1, + "description": "Shown when a sensitivity (hall effect sensor) is disabled. Turning off the sensor." - }, - { - "id": "SettingSensitivityLow", - "len": 1, - "description": "Shown when a sensitivity (hall effect) is not very sensitive" - }, - { - "id": "SettingSensitivityMedium", - "len": 1, - "description": "Shown when a sensitivity (hall effect) is average sensitive" - }, - { - "id": "SettingSensitivityHigh", - "len": 1, - "description": "Shown when a sensitivity (hall effect) is highly sensitive" - }, - { - "id": "SettingLockDisableChar", - "len": 1, - "default": "D", - "description": "Shown when locking mode is turned off." + }, + { + "id": "SettingSensitivityLow", + "len": 1, + "description": "Shown when a sensitivity (hall effect) is not very sensitive" + }, + { + "id": "SettingSensitivityMedium", + "len": 1, + "description": "Shown when a sensitivity (hall effect) is average sensitive" + }, + { + "id": "SettingSensitivityHigh", + "len": 1, + "description": "Shown when a sensitivity (hall effect) is highly sensitive" + }, + { + "id": "SettingLockDisableChar", + "len": 1, + "default": "D", + "description": "Shown when locking mode is turned off." - }, - { - "id": "SettingLockBoostChar", - "len": 1, - "default": "B", - "description": "Shown when the locking mode is set to lock all buttons except for boost mode." - }, - { - "id": "SettingLockFullChar", - "len": 1, - "default": "F", - "description": "Shown when the locking mode is set to lock all buttons." - } - ], - "menuGroups": [ - { - "id": "PowerMenu", - "maxLen": 5, - "maxLen2": 11, - "description": "Menu for settings related to power. Main settings to do with the input voltage." - }, - { - "id": "SolderingMenu", - "maxLen": 5, - "maxLen2": 11, - "description": "Settings for soldering mode, such as boost temps, the increment used when pressing buttons and if button locking is enabled." - }, - { - "id": "PowerSavingMenu", - "maxLen": 5, - "maxLen2": 11, - "description": "Settings to do with power saving, such as sleep mode, sleep temps, and shutdown modes." - }, - { - "id": "UIMenu", - "maxLen": 5, - "maxLen2": 11, - "description": "User interface related settings, such as units." + }, + { + "id": "SettingLockBoostChar", + "len": 1, + "default": "B", + "description": "Shown when the locking mode is set to lock all buttons except for boost mode." + }, + { + "id": "SettingLockFullChar", + "len": 1, + "default": "F", + "description": "Shown when the locking mode is set to lock all buttons." + } + ], + "menuGroups": [{ + "id": "PowerMenu", + "maxLen": 5, + "maxLen2": 11, + "description": "Menu for settings related to power. Main settings to do with the input voltage." + }, + { + "id": "SolderingMenu", + "maxLen": 5, + "maxLen2": 11, + "description": "Settings for soldering mode, such as boost temps, the increment used when pressing buttons and if button locking is enabled." + }, + { + "id": "PowerSavingMenu", + "maxLen": 5, + "maxLen2": 11, + "description": "Settings to do with power saving, such as sleep mode, sleep temps, and shutdown modes." + }, + { + "id": "UIMenu", + "maxLen": 5, + "maxLen2": 11, + "description": "User interface related settings, such as units." - }, - { - "id": "AdvancedMenu", - "maxLen": 5, - "maxLen2": 11, - "description": "Advanced settings. Misc catchall for settings that don't fit anywhere else or settings that require some thought before use." - } - ], - "menuOptions": [ - { - "id": "DCInCutoff", - "maxLen": 5, - "maxLen2": 11, - "description": "When the device is powered by a battery, this adjusts the low voltage threshold for when the unit should turn off the heater to protect the battery." - }, - { - "id": "SleepTemperature", - "maxLen": 4, - "maxLen2": 9, - "description": "Temperature the device will drop down to while asleep. Typically around halfway between off and soldering temperature." - }, - { - "id": "SleepTimeout", - "maxLen": 4, - "maxLen2": 9, - "description": "How long of a period without movement / button-pressing is required before the device drops down to the sleep temperature." + }, + { + "id": "AdvancedMenu", + "maxLen": 5, + "maxLen2": 11, + "description": "Advanced settings. Misc catchall for settings that don't fit anywhere else or settings that require some thought before use." + } + ], + "menuOptions": [{ + "id": "DCInCutoff", + "maxLen": 5, + "maxLen2": 11, + "description": "When the device is powered by a battery, this adjusts the low voltage threshold for when the unit should turn off the heater to protect the battery." + }, + { + "id": "SleepTemperature", + "maxLen": 4, + "maxLen2": 9, + "description": "Temperature the device will drop down to while asleep. Typically around halfway between off and soldering temperature." + }, + { + "id": "SleepTimeout", + "maxLen": 4, + "maxLen2": 9, + "description": "How long of a period without movement / button-pressing is required before the device drops down to the sleep temperature." - }, - { - "id": "ShutdownTimeout", - "maxLen": 5, - "maxLen2": 11, - "description": "How long of a period without movement / button-pressing is required before the device turns off the tip heater completely and returns to the main idle screen." + }, + { + "id": "ShutdownTimeout", + "maxLen": 5, + "maxLen2": 11, + "description": "How long of a period without movement / button-pressing is required before the device turns off the tip heater completely and returns to the main idle screen." - }, - { - "id": "MotionSensitivity", - "maxLen": 6, - "maxLen2": 13, - "description": "Scale of how sensitive the device is to movement. Higher numbers == more sensitive. 0 == motion detection turned off." - }, - { - "id": "TemperatureUnit", - "maxLen": 6, - "maxLen2": 13, - "description": "If the device shows temperatures in °C or °F." + }, + { + "id": "MotionSensitivity", + "maxLen": 6, + "maxLen2": 13, + "description": "Scale of how sensitive the device is to movement. Higher numbers == more sensitive. 0 == motion detection turned off." + }, + { + "id": "TemperatureUnit", + "maxLen": 6, + "maxLen2": 13, + "description": "If the device shows temperatures in °C or °F." - }, - { - "id": "AdvancedIdle", - "maxLen": 6, - "maxLen2": 13, - "description": "Should the device show an 'advanced' view on the idle screen. The advanced view uses text to show more details than the typical icons." - }, - { - "id": "DisplayRotation", - "maxLen": 6, - "maxLen2": 13, - "description": "If the display should rotate automatically or if it should be fixed for left- or right-handed mode." + }, + { + "id": "AdvancedIdle", + "maxLen": 6, + "maxLen2": 13, + "description": "Should the device show an 'advanced' view on the idle screen. The advanced view uses text to show more details than the typical icons." + }, + { + "id": "DisplayRotation", + "maxLen": 6, + "maxLen2": 13, + "description": "If the display should rotate automatically or if it should be fixed for left- or right-handed mode." - }, - { - "id": "BoostTemperature", - "maxLen": 4, - "maxLen2": 9, - "description": "When the unit is in soldering mode. You can hold down the button at the front of the device to temporarily override the soldering temperature to this value. This SETS the temperature, it does not ADD to it." - }, - { - "id": "AutoStart", - "maxLen": 6, - "maxLen2": 13, - "description": "When the device powers up, should it enter into a special mode. These settings set it to either start into soldering mode, sleeping mode or auto mode (Enters into soldering mode on the first movement)." + }, + { + "id": "BoostTemperature", + "maxLen": 4, + "maxLen2": 9, + "description": "When the unit is in soldering mode. You can hold down the button at the front of the device to temporarily override the soldering temperature to this value. This SETS the temperature, it does not ADD to it." + }, + { + "id": "AutoStart", + "maxLen": 6, + "maxLen2": 13, + "description": "When the device powers up, should it enter into a special mode. These settings set it to either start into soldering mode, sleeping mode or auto mode (Enters into soldering mode on the first movement)." - }, - { - "id": "CooldownBlink", - "maxLen": 6, - "maxLen2": 13, - "description": "If the idle screen should blink the tip temperature for attention while the tip is over 50°C. Intended as a 'tip is still hot' warning." + }, + { + "id": "CooldownBlink", + "maxLen": 6, + "maxLen2": 13, + "description": "If the idle screen should blink the tip temperature for attention while the tip is over 50°C. Intended as a 'tip is still hot' warning." - }, - { - "id": "TemperatureCalibration", - "maxLen": 8, - "maxLen2": 15, - "description": "Used to calibrate the ADC+Op-amp offsets for the tip. This calibration must be performed when the tip temperature and the handle temperature are equal. Generally not required unless your device is reading more than 5°C off target." + }, + { + "id": "TemperatureCalibration", + "maxLen": 8, + "maxLen2": 15, + "description": "Used to calibrate the ADC+Op-amp offsets for the tip. This calibration must be performed when the tip temperature and the handle temperature are equal. Generally not required unless your device is reading more than 5°C off target." - }, - { - "id": "SettingsReset", - "maxLen": 8, - "maxLen2": 15, - "description": "Resets all settings and calibrations to factory defaults. Does NOT erase custom user boot up logo's." - }, - { - "id": "VoltageCalibration", - "maxLen": 8, - "maxLen2": 15, - "description": "Enters an adjustment mode where you can gradually adjust the measured voltage to compensate for any unit-to-unit variance in the voltage sense resistors." - }, - { - "id": "AdvancedSoldering", - "maxLen": 6, - "maxLen2": 13, - "description": "Should the device show an 'advanced' soldering view. This is a text-based view that shows more information at the cost of no nice graphics." - }, - { - "id": "ScrollingSpeed", - "maxLen": 6, - "maxLen2": 11, - "description": "How fast the description text scrolls when hovering on a menu. Faster speeds may induce tearing, but allow reading the whole description faster." + }, + { + "id": "SettingsReset", + "maxLen": 8, + "maxLen2": 15, + "description": "Resets all settings and calibrations to factory defaults. Does NOT erase custom user boot up logo's." + }, + { + "id": "VoltageCalibration", + "maxLen": 8, + "maxLen2": 15, + "description": "Enters an adjustment mode where you can gradually adjust the measured voltage to compensate for any unit-to-unit variance in the voltage sense resistors." + }, + { + "id": "AdvancedSoldering", + "maxLen": 6, + "maxLen2": 13, + "description": "Should the device show an 'advanced' soldering view. This is a text-based view that shows more information at the cost of no nice graphics." + }, + { + "id": "ScrollingSpeed", + "maxLen": 6, + "maxLen2": 11, + "description": "How fast the description text scrolls when hovering on a menu. Faster speeds may induce tearing, but allow reading the whole description faster." - }, - { - "id": "QCMaxVoltage", - "maxLen": 8, - "maxLen2": 15, - "description": "This adjusts the maximum voltage the QC negotiation will adjust to. Does NOT affect USB-PD. Should be set safely based on the current rating of your power supply." - }, - { - "id": "PDNegTimeout", - "maxLen": 8, - "maxLen2": 15, - "description": "How long until firmware stops trying to negotiate for USB-PD and tries QC instead. Longer times may help dodgy / old PD adapters, faster times move onto PD quickly. Units of 100ms. Recommended to keep small values." + }, + { + "id": "QCMaxVoltage", + "maxLen": 8, + "maxLen2": 15, + "description": "This adjusts the maximum voltage the QC negotiation will adjust to. Does NOT affect USB-PD. Should be set safely based on the current rating of your power supply." + }, + { + "id": "PDNegTimeout", + "maxLen": 8, + "maxLen2": 15, + "description": "How long until firmware stops trying to negotiate for USB-PD and tries QC instead. Longer times may help dodgy / old PD adapters, faster times move onto PD quickly. Units of 100ms. Recommended to keep small values." - }, + }, - { - "id": "PowerLimit", - "maxLen": 5, - "maxLen2": 11, - "description": "Allows setting a custom wattage for the device to aim to keep the AVERAGE power below. The unit can't control its peak power no matter how you set this. (Except for MHP30 which will regulate nicely to this). If USB-PD is in use, the limit will be set to the lower of this and the supplies advertised wattage." + { + "id": "PowerLimit", + "maxLen": 5, + "maxLen2": 11, + "description": "Allows setting a custom wattage for the device to aim to keep the AVERAGE power below. The unit can't control its peak power no matter how you set this. (Except for MHP30 which will regulate nicely to this). If USB-PD is in use, the limit will be set to the lower of this and the supplies advertised wattage." - }, - { - "id": "ReverseButtonTempChange", - "maxLen": 6, - "maxLen2": 15, - "description": "Swaps which button increments and decrements on temperature change screens." - }, - { - "id": "TempChangeShortStep", - "maxLen": 8, - "maxLen2": 15, - "description": "Factor by which the temperature is changed with a quick press of the buttons." + }, + { + "id": "ReverseButtonTempChange", + "maxLen": 6, + "maxLen2": 15, + "description": "Swaps which button increments and decrements on temperature change screens." + }, + { + "id": "TempChangeShortStep", + "maxLen": 8, + "maxLen2": 15, + "description": "Factor by which the temperature is changed with a quick press of the buttons." - }, - { - "id": "TempChangeLongStep", - "maxLen": 6, - "maxLen2": 15, - "description": "Factor by which the temperature is changed with a hold of the buttons." + }, + { + "id": "TempChangeLongStep", + "maxLen": 6, + "maxLen2": 15, + "description": "Factor by which the temperature is changed with a hold of the buttons." - }, - { - "id": "PowerPulsePower", - "maxLen": 6, - "maxLen2": 15, - "description": "Enables and sets the wattage of the power pulse. Power pulse causes the device to briefly turn on the heater to draw power to avoid power banks going to sleep." + }, + { + "id": "PowerPulsePower", + "maxLen": 6, + "maxLen2": 15, + "description": "Enables and sets the wattage of the power pulse. Power pulse causes the device to briefly turn on the heater to draw power to avoid power banks going to sleep." - }, - { - "id": "HallEffSensitivity", - "maxLen": 6, - "maxLen2": 8, - "description": "If the unit has a hall effect sensor (Pinecil), this adjusts how sensitive it is at detecting a magnet to put the device into sleep mode." + }, + { + "id": "HallEffSensitivity", + "maxLen": 6, + "maxLen2": 8, + "description": "If the unit has a hall effect sensor (Pinecil), this adjusts how sensitive it is at detecting a magnet to put the device into sleep mode." - }, - { - "id": "LockingMode", - "maxLen": 6, - "maxLen2": 13, - "description": "If locking the buttons against accidental presses is enabled." - }, - { - "id": "MinVolCell", - "maxLen": 4, - "maxLen2": 9, - "description": "When powered by a battery, this adjusts the minimum voltage per cell before shutdown. (This is multiplied by the cell count.)" - }, - { - "id": "AnimLoop", - "maxLen": 6, - "maxLen2": 13, - "description": "Should the menu animations loop. Only visible if the animation speed is not set to \"Off\"" - }, - { - "id": "AnimSpeed", - "maxLen": 6, - "maxLen2": 13, - "description": "How fast should the menu animations loop, or if they should not loop at all." - }, - { - "id": "PowerPulseWait", - "maxLen": 6, - "maxLen2": 13, - "description": "Adjusts the time interval between power pulses. Longer gaps reduce undesired heating of the tip, but needs to be fast enough to keep your power bank awake." - }, - { - "id": "PowerPulseDuration", - "maxLen": 6, - "maxLen2": 13, - "description": "How long should the power pulse go for. Some power banks require seeing the power draw be sustained for a certain duration to keep awake. Should be kept as short as possible to avoid wasting power / undesired heating of the tip." - }, - { - "id": "LanguageSwitch", - "maxLen": 7, - "maxLen2": 15, - "description": "Changes the device language on multi-lingual builds." - }, - { - "id": "Brightness", - "maxLen": 7, - "maxLen2": 15, - "description": "Display brightness. Higher values age the OLED faster due to burn-in. (However, it is notable that most of these screens die from other causes first.)" - }, - { - "id": "ColourInversion", - "maxLen": 7, - "maxLen2": 15, - "description": "Inverts the entire OLED." - }, - { - "id": "LOGOTime", - "maxLen": 7, - "maxLen2": 15, - "description": "Sets the duration for the boot logo (S=seconds)." - } - ] -} + }, + { + "id": "LockingMode", + "maxLen": 6, + "maxLen2": 13, + "description": "If locking the buttons against accidental presses is enabled." + }, + { + "id": "MinVolCell", + "maxLen": 4, + "maxLen2": 9, + "description": "When powered by a battery, this adjusts the minimum voltage per cell before shutdown. (This is multiplied by the cell count.)" + }, + { + "id": "AnimLoop", + "maxLen": 6, + "maxLen2": 13, + "description": "Should the menu animations loop. Only visible if the animation speed is not set to \"Off\"" + }, + { + "id": "AnimSpeed", + "maxLen": 6, + "maxLen2": 13, + "description": "How fast should the menu animations loop, or if they should not loop at all." + }, + { + "id": "PowerPulseWait", + "maxLen": 6, + "maxLen2": 13, + "description": "Adjusts the time interval between power pulses. Longer gaps reduce undesired heating of the tip, but needs to be fast enough to keep your power bank awake." + }, + { + "id": "PowerPulseDuration", + "maxLen": 6, + "maxLen2": 13, + "description": "How long should the power pulse go for. Some power banks require seeing the power draw be sustained for a certain duration to keep awake. Should be kept as short as possible to avoid wasting power / undesired heating of the tip." + }, + { + "id": "LanguageSwitch", + "maxLen": 7, + "maxLen2": 15, + "description": "Changes the device language on multi-lingual builds." + }, + { + "id": "Brightness", + "maxLen": 7, + "maxLen2": 15, + "description": "Display brightness. Higher values age the OLED faster due to burn-in. (However, it is notable that most of these screens die from other causes first.)" + }, + { + "id": "ColourInversion", + "maxLen": 7, + "maxLen2": 15, + "description": "Inverts the entire OLED." + }, + { + "id": "LOGOTime", + "maxLen": 7, + "maxLen2": 15, + "description": "Sets the duration for the boot logo (S=seconds)." + } + ] + } \ No newline at end of file diff --git a/source/Core/BSP/BSP.h b/source/Core/BSP/BSP.h index dd41bc7f..574d98d2 100644 --- a/source/Core/BSP/BSP.h +++ b/source/Core/BSP/BSP.h @@ -77,6 +77,11 @@ bool isTipDisconnected(); // Return hardware unique ID if possible uint64_t getDeviceID(); +// If device has burned in validation code's, return the code +uint32_t getDeviceValidation(); +// If device validation passes returns 0 +uint8_t getDeviceValidationStatus(); + // Status LED controls enum StatusLED { @@ -93,6 +98,7 @@ void setStatusLED(const enum StatusLED state); // By the PID, after each ADC sample comes in // For example, on the MHP30 this is used to figure out the resistance of the hotplate uint8_t preStartChecks(); +uint8_t preStartChecksDone(); #ifdef __cplusplus } #endif diff --git a/source/Core/BSP/BSP_Power.h b/source/Core/BSP/BSP_Power.h index 386ffc74..ef1f4aee 100644 --- a/source/Core/BSP/BSP_Power.h +++ b/source/Core/BSP/BSP_Power.h @@ -16,9 +16,11 @@ extern "C" { // Can be used to check any details for the power system void power_check(); -// Return the tip resistance in x10 ohms (8.5 -> 85) +// Returns the tip resistance in x10 ohms, so 7.5 = 75; 14=140 etc uint8_t getTipResistanceX10(); +uint8_t getTipThermalMass(); + #ifdef __cplusplus } #endif diff --git a/source/Core/BSP/MHP30/BSP.cpp b/source/Core/BSP/MHP30/BSP.cpp index 32c6ffb4..a9e686d9 100644 --- a/source/Core/BSP/MHP30/BSP.cpp +++ b/source/Core/BSP/MHP30/BSP.cpp @@ -26,7 +26,7 @@ void resetWatchdog() { HAL_IWDG_Refresh(&hiwdg); } #ifdef TEMP_NTC // Lookup table for the NTC // Stored as ADCReading,Temp in degC -static const uint16_t NTCHandleLookup[] = { +static const int32_t NTCHandleLookup[] = { // ADC Reading , Temp in Cx10 808, 1600, // 832, 1590, // @@ -425,7 +425,7 @@ bool isTipDisconnected() { uint8_t preStartChecks() { performTipMeasurementStep(false); - return tipMeasurementOccuring ? 1 : 0; + return tipMeasurementOccuring ? 0 : 1; } void setBuzzer(bool on) { if (on) { @@ -474,4 +474,8 @@ void setStatusLED(const enum StatusLED state) { uint64_t getDeviceID() { // return HAL_GetUIDw0() | ((uint64_t)HAL_GetUIDw1() << 32); -} \ No newline at end of file +} + +uint8_t preStartChecksDone() { return 1; } + +uint8_t getTipThermalMass() { return TIP_THERMAL_MASS; } \ No newline at end of file diff --git a/source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c b/source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c index f9616265..fd96debc 100644 --- a/source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c +++ b/source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c @@ -175,11 +175,11 @@ * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { - uint32_t position = 0x00u; - uint32_t ioposition; - uint32_t iocurrent; - uint32_t temp; - uint32_t config = 0x00u; + uint32_t position = 0x00u; + uint32_t ioposition; + uint32_t iocurrent; + uint32_t temp; + uint32_t config = 0x00u; __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ uint32_t registeroffset; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */ @@ -326,9 +326,9 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { * @retval None */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) { - uint32_t position = 0x00u; - uint32_t iocurrent; - uint32_t tmp; + uint32_t position = 0x00u; + uint32_t iocurrent; + uint32_t tmp; __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ uint32_t registeroffset; diff --git a/source/Core/BSP/MHP30/configuration.h b/source/Core/BSP/MHP30/configuration.h index f6775c51..fed535ad 100644 --- a/source/Core/BSP/MHP30/configuration.h +++ b/source/Core/BSP/MHP30/configuration.h @@ -74,6 +74,9 @@ #define POWER_PULSE_WAIT_MAX 9 // 9*2.5s = 22.5 seconds #define POWER_PULSE_DURATION_MAX 9 // 9*250ms = 2.25 seconds +#define ADC_MAX_READING (4096 * 8) // Maximum reading of the adc +#define ADC_VDD_MV 3300 // ADC max reading millivolts + #ifdef MODEL_TS100 #define POWER_PULSE_DEFAULT 0 #else @@ -146,6 +149,7 @@ #define BATTFILTERDEPTH 8 #define OLED_I2CBB #define ACCEL_EXITS_ON_MOVEMENT +#define NEEDS_VBUS_PROBE 0 #define HARDWARE_MAX_WATTAGE_X10 650 #define TIP_THERMAL_MASS 65 // TODO, needs refinement diff --git a/source/Core/BSP/Miniware/BSP.cpp b/source/Core/BSP/Miniware/BSP.cpp index cb7d5248..f09a8ece 100644 --- a/source/Core/BSP/Miniware/BSP.cpp +++ b/source/Core/BSP/Miniware/BSP.cpp @@ -283,10 +283,14 @@ bool isTipDisconnected() { } void setStatusLED(const enum StatusLED state) {} -uint8_t preStartChecks() { return 0; } +uint8_t preStartChecks() { return 1; } uint64_t getDeviceID() { // return HAL_GetUIDw0() | ((uint64_t)HAL_GetUIDw1() << 32); } -uint8_t getTipResistanceX10() { return TIP_RESISTANCE; } \ No newline at end of file +uint8_t getTipResistanceX10() { return TIP_RESISTANCE; } + +uint8_t preStartChecksDone() { return 1; } + +uint8_t getTipThermalMass() { return TIP_THERMAL_MASS; } \ No newline at end of file diff --git a/source/Core/BSP/Miniware/ThermoModel.cpp b/source/Core/BSP/Miniware/ThermoModel.cpp index ae74d49c..1b04bd5f 100644 --- a/source/Core/BSP/Miniware/ThermoModel.cpp +++ b/source/Core/BSP/Miniware/ThermoModel.cpp @@ -9,7 +9,7 @@ #include "configuration.h" #ifdef TEMP_uV_LOOKUP_HAKKO -const uint16_t uVtoDegC[] = { +const int32_t uVtoDegC[] = { // // 0, 0, // @@ -69,7 +69,7 @@ const uint16_t uVtoDegC[] = { #ifdef TEMP_uV_LOOKUP_TS80 -const uint16_t uVtoDegC[] = { +const int32_t uVtoDegC[] = { // // 530, 0, // diff --git a/source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c b/source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c index c12ba6a6..5d46145d 100644 --- a/source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c +++ b/source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c @@ -564,21 +564,10 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { /* Half Transfer Complete Interrupt management ******************************/ if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) { - /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ - if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { - /* Disable the half transfer interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); - } + /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - /* DMA peripheral state is not updated in Half Transfer */ - /* but in Transfer Complete case */ - - if (hdma->XferHalfCpltCallback != NULL) { - /* Half transfer callback */ - hdma->XferHalfCpltCallback(hdma); - } } /* Transfer Complete Interrupt management ***********************************/ diff --git a/source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c b/source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c index 0dd8003c..ec9f7eb1 100644 --- a/source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c +++ b/source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c @@ -191,11 +191,11 @@ * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { - uint32_t position; - uint32_t ioposition = 0x00U; - uint32_t iocurrent = 0x00U; - uint32_t temp = 0x00U; - uint32_t config = 0x00U; + uint32_t position; + uint32_t ioposition = 0x00U; + uint32_t iocurrent = 0x00U; + uint32_t temp = 0x00U; + uint32_t config = 0x00U; __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ uint32_t registeroffset = 0U; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */ @@ -340,9 +340,9 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { * @retval None */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) { - uint32_t position = 0x00U; - uint32_t iocurrent = 0x00U; - uint32_t tmp = 0x00U; + uint32_t position = 0x00U; + uint32_t iocurrent = 0x00U; + uint32_t tmp = 0x00U; __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ uint32_t registeroffset = 0U; diff --git a/source/Core/BSP/Miniware/configuration.h b/source/Core/BSP/Miniware/configuration.h index f33952a0..d3ff9432 100644 --- a/source/Core/BSP/Miniware/configuration.h +++ b/source/Core/BSP/Miniware/configuration.h @@ -1,208 +1,211 @@ #ifndef CONFIGURATION_H_ - #define CONFIGURATION_H_ - #include "Settings.h" - #include - /** - * Configuration.h - * Define here your default pre settings for TS80(P) or TS100 - * - */ +#define CONFIGURATION_H_ +#include "Settings.h" +#include +/** + * Configuration.h + * Define here your default pre settings for TS80(P) or TS100 + * + */ - //=========================================================================== - //============================= Default Settings ============================ - //=========================================================================== - /** - * Default soldering temp is 320.0 C - * Temperature the iron sleeps at - default 150.0 C - */ +//=========================================================================== +//============================= Default Settings ============================ +//=========================================================================== +/** + * Default soldering temp is 320.0 C + * Temperature the iron sleeps at - default 150.0 C + */ - #define SLEEP_TEMP 150 // Default sleep temperature - #define BOOST_TEMP 420 // Default boost temp. - #define BOOST_MODE_ENABLED 1 // 0: Disable 1: Enable +#define SLEEP_TEMP 150 // Default sleep temperature +#define BOOST_TEMP 420 // Default boost temp. +#define BOOST_MODE_ENABLED 1 // 0: Disable 1: Enable - /** - * Blink the temperature on the cooling screen when its > 50C - */ - #define COOLING_TEMP_BLINK 0 // 0: Disable 1: Enable +/** + * Blink the temperature on the cooling screen when its > 50C + */ +#define COOLING_TEMP_BLINK 0 // 0: Disable 1: Enable - /** - * How many seconds/minutes we wait until going to sleep/shutdown. - * Values -> SLEEP_TIME * 10; i.e. 5*10 = 50 Seconds! - */ - #define SLEEP_TIME 5 // x10 Seconds - #define SHUTDOWN_TIME 10 // Minutes +/** + * How many seconds/minutes we wait until going to sleep/shutdown. + * Values -> SLEEP_TIME * 10; i.e. 5*10 = 50 Seconds! + */ +#define SLEEP_TIME 5 // x10 Seconds +#define SHUTDOWN_TIME 10 // Minutes - /** - * Auto start off for safety. - * Pissible values are: - * 0 - none - * 1 - Soldering Temperature - * 2 - Sleep Temperature - * 3 - Sleep Off Temperature - */ - #define AUTO_START_MODE 0 // Default to none +/** + * Auto start off for safety. + * Pissible values are: + * 0 - none + * 1 - Soldering Temperature + * 2 - Sleep Temperature + * 3 - Sleep Off Temperature + */ +#define AUTO_START_MODE 0 // Default to none - /** - * Locking Mode - * When in soldering mode a long press on both keys toggle the lock of the buttons - * Possible values are: - * 0 - Desactivated - * 1 - Lock except boost - * 2 - Full lock - */ - #define LOCKING_MODE 0 // Default to desactivated for safety +/** + * Locking Mode + * When in soldering mode a long press on both keys toggle the lock of the buttons + * Possible values are: + * 0 - Desactivated + * 1 - Lock except boost + * 2 - Full lock + */ +#define LOCKING_MODE 0 // Default to desactivated for safety - /** - * OLED Orientation - * - */ - #define ORIENTATION_MODE 2 // 0: Right 1:Left 2:Automatic - Default Automatic - #define REVERSE_BUTTON_TEMP_CHANGE 0 // 0:Default 1:Reverse - Reverse the plus and minus button assigment for temperature change +/** + * OLED Orientation + * + */ +#define ORIENTATION_MODE 2 // 0: Right 1:Left 2:Automatic - Default Automatic +#define REVERSE_BUTTON_TEMP_CHANGE 0 // 0:Default 1:Reverse - Reverse the plus and minus button assigment for temperature change - /** - * Temp change settings - */ - #define TEMP_CHANGE_SHORT_STEP 1 // Default temp change short step +1 - #define TEMP_CHANGE_LONG_STEP 10 // Default temp change long step +10 - #define TEMP_CHANGE_SHORT_STEP_MAX 50 // Temp change short step MAX value - #define TEMP_CHANGE_LONG_STEP_MAX 90 // Temp change long step MAX value +/** + * Temp change settings + */ +#define TEMP_CHANGE_SHORT_STEP 1 // Default temp change short step +1 +#define TEMP_CHANGE_LONG_STEP 10 // Default temp change long step +10 +#define TEMP_CHANGE_SHORT_STEP_MAX 50 // Temp change short step MAX value +#define TEMP_CHANGE_LONG_STEP_MAX 90 // Temp change long step MAX value - /* Power pulse for keeping power banks awake*/ - #define POWER_PULSE_INCREMENT 1 - #define POWER_PULSE_MAX 100 // x10 max watts - #define POWER_PULSE_WAIT_MAX 9 // 9*2.5s = 22.5 seconds - #define POWER_PULSE_DURATION_MAX 9 // 9*250ms = 2.25 seconds +/* Power pulse for keeping power banks awake*/ +#define POWER_PULSE_INCREMENT 1 +#define POWER_PULSE_MAX 100 // x10 max watts +#define POWER_PULSE_WAIT_MAX 9 // 9*2.5s = 22.5 seconds +#define POWER_PULSE_DURATION_MAX 9 // 9*250ms = 2.25 seconds - #ifdef MODEL_TS100 - #define POWER_PULSE_DEFAULT 0 - #else - #define POWER_PULSE_DEFAULT 5 - #endif - #define POWER_PULSE_WAIT_DEFAULT 4 // Default rate of the power pulse: 4*2500 = 10000 ms = 10 s - #define POWER_PULSE_DURATION_DEFAULT 1 // Default duration of the power pulse: 1*250 = 250 ms +#ifdef MODEL_TS100 +#define POWER_PULSE_DEFAULT 0 +#else +#define POWER_PULSE_DEFAULT 5 +#endif +#define POWER_PULSE_WAIT_DEFAULT 4 // Default rate of the power pulse: 4*2500 = 10000 ms = 10 s +#define POWER_PULSE_DURATION_DEFAULT 1 // Default duration of the power pulse: 1*250 = 250 ms - /** - * OLED Orientation Sensitivity on Automatic mode! - * Motion Sensitivity <0=Off 1=Least Sensitive 9=Most Sensitive> - */ - #define SENSITIVITY 7 // Default 7 +/** + * OLED Orientation Sensitivity on Automatic mode! + * Motion Sensitivity <0=Off 1=Least Sensitive 9=Most Sensitive> + */ +#define SENSITIVITY 7 // Default 7 - /** - * Detailed soldering screen - * Detailed idle screen (off for first time users) - */ - #define DETAILED_SOLDERING 0 // 0: Disable 1: Enable - Default 0 - #define DETAILED_IDLE 0 // 0: Disable 1: Enable - Default 0 +/** + * Detailed soldering screen + * Detailed idle screen (off for first time users) + */ +#define DETAILED_SOLDERING 0 // 0: Disable 1: Enable - Default 0 +#define DETAILED_IDLE 0 // 0: Disable 1: Enable - Default 0 - #define THERMAL_RUNAWAY_TIME_SEC 20 - #define THERMAL_RUNAWAY_TEMP_C 10 +#define THERMAL_RUNAWAY_TIME_SEC 20 +#define THERMAL_RUNAWAY_TEMP_C 10 - #define CUT_OUT_SETTING 0 // default to no cut-off voltage - #define RECOM_VOL_CELL 33 // Minimum voltage per cell (Recommended 3.3V (33)) - #define TEMPERATURE_INF 0 // default to 0 - #define DESCRIPTION_SCROLL_SPEED 0 // 0: Slow 1: Fast - default to slow - #define ANIMATION_LOOP 1 // 0: off 1: on - #define ANIMATION_SPEED settingOffSpeed_t::MEDIUM +#define CUT_OUT_SETTING 0 // default to no cut-off voltage +#define RECOM_VOL_CELL 33 // Minimum voltage per cell (Recommended 3.3V (33)) +#define TEMPERATURE_INF 0 // default to 0 +#define DESCRIPTION_SCROLL_SPEED 0 // 0: Slow 1: Fast - default to slow +#define ANIMATION_LOOP 1 // 0: off 1: on +#define ANIMATION_SPEED settingOffSpeed_t::MEDIUM - #define OP_AMP_Rf_TS100 750 * 1000 // 750 Kilo-ohms -> From schematic, R1 - #define OP_AMP_Rin_TS100 2370 // 2.37 Kilo-ohms -> From schematic, R2 +#define OP_AMP_Rf_TS100 750 * 1000 // 750 Kilo-ohms -> From schematic, R1 +#define OP_AMP_Rin_TS100 2370 // 2.37 Kilo-ohms -> From schematic, R2 - #define OP_AMP_GAIN_STAGE_TS100 (1 + (OP_AMP_Rf_TS100 / OP_AMP_Rin_TS100)) +#define OP_AMP_GAIN_STAGE_TS100 (1 + (OP_AMP_Rf_TS100 / OP_AMP_Rin_TS100)) - #define OP_AMP_Rf_TS80 180 * 1000 // 180 Kilo-ohms -> From schematic, R6 - #define OP_AMP_Rin_TS80 2000 // 2.0 Kilo-ohms -> From schematic, R3 +#define OP_AMP_Rf_TS80 180 * 1000 // 180 Kilo-ohms -> From schematic, R6 +#define OP_AMP_Rin_TS80 2000 // 2.0 Kilo-ohms -> From schematic, R3 - #define OP_AMP_GAIN_STAGE_TS80 (1 + (OP_AMP_Rf_TS80 / OP_AMP_Rin_TS80)) +#define OP_AMP_GAIN_STAGE_TS80 (1 + (OP_AMP_Rf_TS80 / OP_AMP_Rin_TS80)) - // Deriving the Voltage div: - // Vin_max = (3.3*(r1+r2))/(r2) - // vdiv = (32768*4)/(vin_max*10) +#define ADC_MAX_READING (4096 * 8) // Maximum reading of the adc +#define ADC_VDD_MV 3300 // ADC max reading millivolts - #if defined(MODEL_TS100) + defined(MODEL_TS80) + defined(MODEL_TS80P) > 1 - #error "Multiple models defined!" - #elif defined(MODEL_TS100) + defined(MODEL_TS80) + defined(MODEL_TS80P) == 0 - #error "No model defined!" - #endif +// Deriving the Voltage div: +// Vin_max = (3.3*(r1+r2))/(r2) +// vdiv = (32768*4)/(vin_max*10) - // Miniware is swapping IMU's around a bit now, so we turn them all on +#if defined(MODEL_TS100) + defined(MODEL_TS80) + defined(MODEL_TS80P) > 1 +#error "Multiple models defined!" +#elif defined(MODEL_TS100) + defined(MODEL_TS80) + defined(MODEL_TS80P) == 0 +#error "No model defined!" +#endif +#define NEEDS_VBUS_PROBE 0 +// Miniware is swapping IMU's around a bit now, so we turn them all on - #define ACCEL_MMA - #define ACCEL_LIS - #define ACCEL_SC7 - #define ACCEL_MSA - #define ACCEL_BMA +#define ACCEL_MMA +#define ACCEL_LIS +#define ACCEL_SC7 +#define ACCEL_MSA +#define ACCEL_BMA - #define MIN_CALIBRATION_OFFSET 100 // Min value for calibration - #define SOLDERING_TEMP 320 // Default soldering temp is 320.0 °C - #define PID_TIM_HZ (8) // Tick rate of the PID loop - #define MAX_TEMP_C 450 // Max soldering temp selectable °C - #define MAX_TEMP_F 850 // Max soldering temp selectable °F - #define MIN_TEMP_C 10 // Min soldering temp selectable °C - #define MIN_TEMP_F 60 // Min soldering temp selectable °F - #define MIN_BOOST_TEMP_C 250 // The min settable temp for boost mode °C - #define MIN_BOOST_TEMP_F 480 // The min settable temp for boost mode °F +#define MIN_CALIBRATION_OFFSET 100 // Min value for calibration +#define SOLDERING_TEMP 320 // Default soldering temp is 320.0 °C +#define PID_TIM_HZ (8) // Tick rate of the PID loop +#define MAX_TEMP_C 450 // Max soldering temp selectable °C +#define MAX_TEMP_F 850 // Max soldering temp selectable °F +#define MIN_TEMP_C 10 // Min soldering temp selectable °C +#define MIN_TEMP_F 60 // Min soldering temp selectable °F +#define MIN_BOOST_TEMP_C 250 // The min settable temp for boost mode °C +#define MIN_BOOST_TEMP_F 480 // The min settable temp for boost mode °F - #ifdef MODEL_TS100 - #define VOLTAGE_DIV 467 // 467 - Default divider from schematic - #define CALIBRATION_OFFSET 900 // 900 - Default adc offset in uV - #define PID_POWER_LIMIT 70 // Sets the max pwm power limit - #define POWER_LIMIT 0 // 0 watts default limit - #define MAX_POWER_LIMIT 70 - #define POWER_LIMIT_STEPS 5 - #define OP_AMP_GAIN_STAGE OP_AMP_GAIN_STAGE_TS100 - #define TEMP_uV_LOOKUP_HAKKO - #define USB_PD_VMAX 20 // Maximum voltage for PD to negotiate +#ifdef MODEL_TS100 +#define VOLTAGE_DIV 467 // 467 - Default divider from schematic +#define CALIBRATION_OFFSET 900 // 900 - Default adc offset in uV +#define PID_POWER_LIMIT 70 // Sets the max pwm power limit +#define POWER_LIMIT 0 // 0 watts default limit +#define MAX_POWER_LIMIT 70 +#define POWER_LIMIT_STEPS 5 +#define OP_AMP_GAIN_STAGE OP_AMP_GAIN_STAGE_TS100 +#define TEMP_uV_LOOKUP_HAKKO +#define USB_PD_VMAX 20 // Maximum voltage for PD to negotiate - #define HARDWARE_MAX_WATTAGE_X10 750 - #define TIP_THERMAL_MASS 65 // X10 watts to raise 1 deg C in 1 second - #define TIP_RESISTANCE 75 // x10 ohms, 7.5 typical for ts100 tips +#define HARDWARE_MAX_WATTAGE_X10 750 +#define TIP_THERMAL_MASS 65 // X10 watts to raise 1 deg C in 1 second +#define TIP_RESISTANCE 75 // x10 ohms, 7.5 typical for ts100 tips - #define POW_DC - #define POW_PD 0 - #define TEMP_TMP36 - #endif +#define POW_DC +#define POW_PD 0 +#define TEMP_TMP36 +#endif - #if defined(MODEL_TS80) + defined(MODEL_TS80P) > 0 - #define MAX_POWER_LIMIT 40 - #define POWER_LIMIT_STEPS 2 - #define OP_AMP_GAIN_STAGE OP_AMP_GAIN_STAGE_TS80 - #define TEMP_uV_LOOKUP_TS80 - #define USB_PD_VMAX 12 // Maximum voltage for PD to negotiate +#if defined(MODEL_TS80) + defined(MODEL_TS80P) > 0 +#define MAX_POWER_LIMIT 40 +#define POWER_LIMIT_STEPS 2 +#define OP_AMP_GAIN_STAGE OP_AMP_GAIN_STAGE_TS80 +#define TEMP_uV_LOOKUP_TS80 +#define USB_PD_VMAX 12 // Maximum voltage for PD to negotiate - #define TIP_THERMAL_MASS 40 - #define TIP_RESISTANCE 45 // x10 ohms, 4.5 typical for ts80 tips +#define TIP_THERMAL_MASS 40 +#define TIP_RESISTANCE 45 // x10 ohms, 4.5 typical for ts80 tips - #define LIS_ORI_FLIP - #define OLED_FLIP - #endif +#define LIS_ORI_FLIP +#define OLED_FLIP +#endif - #ifdef MODEL_TS80 - #define VOLTAGE_DIV 780 // Default divider from schematic - #define CALIBRATION_OFFSET 900 // the adc offset in uV - #define PID_POWER_LIMIT 24 // Sets the max pwm power limit - #define POWER_LIMIT 24 // 24 watts default power limit +#ifdef MODEL_TS80 +#define VOLTAGE_DIV 780 // Default divider from schematic +#define CALIBRATION_OFFSET 900 // the adc offset in uV +#define PID_POWER_LIMIT 24 // Sets the max pwm power limit +#define POWER_LIMIT 24 // 24 watts default power limit - #define HARDWARE_MAX_WATTAGE_X10 180 +#define HARDWARE_MAX_WATTAGE_X10 180 - #define POW_QC - #define POW_PD 0 - #define TEMP_TMP36 - #endif +#define POW_QC +#define POW_PD 0 +#define TEMP_TMP36 +#endif - #ifdef MODEL_TS80P - #define VOLTAGE_DIV 650 // Default for TS80P with slightly different resistors - #define CALIBRATION_OFFSET 1500 // the adc offset in uV - #define PID_POWER_LIMIT 35 // Sets the max pwm power limit - #define POWER_LIMIT 30 // 30 watts default power limit +#ifdef MODEL_TS80P +#define VOLTAGE_DIV 650 // Default for TS80P with slightly different resistors +#define CALIBRATION_OFFSET 1500 // the adc offset in uV +#define PID_POWER_LIMIT 35 // Sets the max pwm power limit +#define POWER_LIMIT 30 // 30 watts default power limit - #define HARDWARE_MAX_WATTAGE_X10 300 +#define HARDWARE_MAX_WATTAGE_X10 300 - #define POW_PD 1 - #define POW_QC 1 - #define TEMP_NTC - #define I2C_SOFT - #define SC7_ORI_FLIP - #endif +#define POW_PD 1 +#define POW_QC 1 +#define TEMP_NTC +#define I2C_SOFT +#define SC7_ORI_FLIP +#endif #endif #define FLASH_LOGOADDR (0x08000000 + (62 * 1024)) diff --git a/source/Core/BSP/Pine64/BSP.cpp b/source/Core/BSP/Pinecil/BSP.cpp similarity index 89% rename from source/Core/BSP/Pine64/BSP.cpp rename to source/Core/BSP/Pinecil/BSP.cpp index 0b84339e..fa7cb267 100644 --- a/source/Core/BSP/Pine64/BSP.cpp +++ b/source/Core/BSP/Pinecil/BSP.cpp @@ -91,7 +91,11 @@ bool isTipDisconnected() { void setStatusLED(const enum StatusLED state) {} -uint8_t preStartChecks() { return 0; } +uint8_t preStartChecks() { return 1; } uint64_t getDeviceID() { return dbg_id_get(); } -uint8_t getTipResistanceX10() { return TIP_RESISTANCE; } \ No newline at end of file +uint8_t getTipResistanceX10() { return TIP_RESISTANCE; } + +uint8_t preStartChecksDone() { return 1; } + +uint8_t getTipThermalMass() { return TIP_THERMAL_MASS; } \ No newline at end of file diff --git a/source/Core/BSP/Pine64/Debug.cpp b/source/Core/BSP/Pinecil/Debug.cpp similarity index 100% rename from source/Core/BSP/Pine64/Debug.cpp rename to source/Core/BSP/Pinecil/Debug.cpp diff --git a/source/Core/BSP/Pine64/Debug.h b/source/Core/BSP/Pinecil/Debug.h similarity index 100% rename from source/Core/BSP/Pine64/Debug.h rename to source/Core/BSP/Pinecil/Debug.h diff --git a/source/Core/BSP/Pine64/FreeRTOSConfig.h b/source/Core/BSP/Pinecil/FreeRTOSConfig.h similarity index 100% rename from source/Core/BSP/Pine64/FreeRTOSConfig.h rename to source/Core/BSP/Pinecil/FreeRTOSConfig.h diff --git a/source/Core/BSP/Pine64/I2C_Wrapper.cpp b/source/Core/BSP/Pinecil/I2C_Wrapper.cpp similarity index 100% rename from source/Core/BSP/Pine64/I2C_Wrapper.cpp rename to source/Core/BSP/Pinecil/I2C_Wrapper.cpp diff --git a/source/Core/BSP/Pine64/IRQ.cpp b/source/Core/BSP/Pinecil/IRQ.cpp similarity index 100% rename from source/Core/BSP/Pine64/IRQ.cpp rename to source/Core/BSP/Pinecil/IRQ.cpp diff --git a/source/Core/BSP/Pine64/IRQ.h b/source/Core/BSP/Pinecil/IRQ.h similarity index 100% rename from source/Core/BSP/Pine64/IRQ.h rename to source/Core/BSP/Pinecil/IRQ.h diff --git a/source/Core/BSP/Pine64/NOTES.md b/source/Core/BSP/Pinecil/NOTES.md similarity index 100% rename from source/Core/BSP/Pine64/NOTES.md rename to source/Core/BSP/Pinecil/NOTES.md diff --git a/source/Core/BSP/Pine64/Pins.h b/source/Core/BSP/Pinecil/Pins.h similarity index 100% rename from source/Core/BSP/Pine64/Pins.h rename to source/Core/BSP/Pinecil/Pins.h diff --git a/source/Core/BSP/Pine64/Power.cpp b/source/Core/BSP/Pinecil/Power.cpp similarity index 100% rename from source/Core/BSP/Pine64/Power.cpp rename to source/Core/BSP/Pinecil/Power.cpp diff --git a/source/Core/BSP/Pine64/QC_GPIO.cpp b/source/Core/BSP/Pinecil/QC_GPIO.cpp similarity index 100% rename from source/Core/BSP/Pine64/QC_GPIO.cpp rename to source/Core/BSP/Pinecil/QC_GPIO.cpp diff --git a/source/Core/BSP/Pine64/README.md b/source/Core/BSP/Pinecil/README.md similarity index 100% rename from source/Core/BSP/Pine64/README.md rename to source/Core/BSP/Pinecil/README.md diff --git a/source/Core/BSP/Pine64/Setup.cpp b/source/Core/BSP/Pinecil/Setup.cpp similarity index 100% rename from source/Core/BSP/Pine64/Setup.cpp rename to source/Core/BSP/Pinecil/Setup.cpp diff --git a/source/Core/BSP/Pine64/Setup.h b/source/Core/BSP/Pinecil/Setup.h similarity index 100% rename from source/Core/BSP/Pine64/Setup.h rename to source/Core/BSP/Pinecil/Setup.h diff --git a/source/Core/BSP/Pine64/ThermoModel.cpp b/source/Core/BSP/Pinecil/ThermoModel.cpp similarity index 93% rename from source/Core/BSP/Pine64/ThermoModel.cpp rename to source/Core/BSP/Pinecil/ThermoModel.cpp index 1f4da291..846a0a00 100644 --- a/source/Core/BSP/Pine64/ThermoModel.cpp +++ b/source/Core/BSP/Pinecil/ThermoModel.cpp @@ -9,7 +9,7 @@ #include "configuration.h" #ifdef TEMP_uV_LOOKUP_HAKKO -const uint16_t uVtoDegC[] = { +const int32_t uVtoDegC[] = { // // uv -> temp in C 0, 0, // diff --git a/source/Core/BSP/Pine64/UnitSettings.h b/source/Core/BSP/Pinecil/UnitSettings.h similarity index 100% rename from source/Core/BSP/Pine64/UnitSettings.h rename to source/Core/BSP/Pinecil/UnitSettings.h diff --git a/source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_compatiable.h b/source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/core_compatiable.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_compatiable.h rename to source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/core_compatiable.h diff --git a/source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_base.h b/source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/core_feature_base.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_base.h rename to source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/core_feature_base.h diff --git a/source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_cache.h b/source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/core_feature_cache.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_cache.h rename to source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/core_feature_cache.h diff --git a/source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_dsp.h b/source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/core_feature_dsp.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_dsp.h rename to source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/core_feature_dsp.h diff --git a/source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_eclic.h b/source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/core_feature_eclic.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_eclic.h rename to source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/core_feature_eclic.h diff --git a/source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_fpu.h b/source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/core_feature_fpu.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_fpu.h rename to source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/core_feature_fpu.h diff --git a/source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_pmp.h b/source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/core_feature_pmp.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_pmp.h rename to source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/core_feature_pmp.h diff --git a/source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_timer.h b/source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/core_feature_timer.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_timer.h rename to source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/core_feature_timer.h diff --git a/source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/nmsis_compiler.h b/source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/nmsis_compiler.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/nmsis_compiler.h rename to source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/nmsis_compiler.h diff --git a/source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/nmsis_core.h b/source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/nmsis_core.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/nmsis_core.h rename to source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/nmsis_core.h diff --git a/source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/nmsis_gcc.h b/source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/nmsis_gcc.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/nmsis_gcc.h rename to source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/nmsis_gcc.h diff --git a/source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/nmsis_version.h b/source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/nmsis_version.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/nmsis_version.h rename to source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/nmsis_version.h diff --git a/source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/riscv_bits.h b/source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/riscv_bits.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/riscv_bits.h rename to source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/riscv_bits.h diff --git a/source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/riscv_encoding.h b/source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/riscv_encoding.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/riscv_encoding.h rename to source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/riscv_encoding.h diff --git a/source/Core/BSP/Pine64/Vendor/OS/FreeRTOS/Source/portable/GCC/port.c b/source/Core/BSP/Pinecil/Vendor/OS/FreeRTOS/Source/portable/GCC/port.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/OS/FreeRTOS/Source/portable/GCC/port.c rename to source/Core/BSP/Pinecil/Vendor/OS/FreeRTOS/Source/portable/GCC/port.c diff --git a/source/Core/BSP/Pine64/Vendor/OS/FreeRTOS/Source/portable/GCC/portasm.S b/source/Core/BSP/Pinecil/Vendor/OS/FreeRTOS/Source/portable/GCC/portasm.S similarity index 100% rename from source/Core/BSP/Pine64/Vendor/OS/FreeRTOS/Source/portable/GCC/portasm.S rename to source/Core/BSP/Pinecil/Vendor/OS/FreeRTOS/Source/portable/GCC/portasm.S diff --git a/source/Core/BSP/Pine64/Vendor/OS/FreeRTOS/Source/portable/GCC/portmacro.h b/source/Core/BSP/Pinecil/Vendor/OS/FreeRTOS/Source/portable/GCC/portmacro.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/OS/FreeRTOS/Source/portable/GCC/portmacro.h rename to source/Core/BSP/Pinecil/Vendor/OS/FreeRTOS/Source/portable/GCC/portmacro.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Board/pinecil/Source/GCC/gcc_gd32vf103_flashxip.ld b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Board/pinecil/Source/GCC/gcc_gd32vf103_flashxip.ld similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Board/pinecil/Source/GCC/gcc_gd32vf103_flashxip.ld rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Board/pinecil/Source/GCC/gcc_gd32vf103_flashxip.ld diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Board/pinecil/openocd_gd32vf103.cfg b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Board/pinecil/openocd_gd32vf103.cfg similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Board/pinecil/openocd_gd32vf103.cfg rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Board/pinecil/openocd_gd32vf103.cfg diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_core.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_core.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_core.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_core.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_dev.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_dev.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_dev.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_dev.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_host.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_host.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_host.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_host.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_hw.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_hw.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_hw.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_hw.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_regs.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_regs.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_regs.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_regs.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usbd_int.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usbd_int.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usbd_int.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usbd_int.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usbh_int.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usbh_int.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usbh_int.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usbh_int.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usb_ch9_std.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usb_ch9_std.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usb_ch9_std.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usb_ch9_std.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usb_conf.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usb_conf.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usb_conf.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usb_conf.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_conf.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_conf.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_conf.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_conf.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_core.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_core.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_core.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_core.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_enum.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_enum.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_enum.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_enum.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_transc.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_transc.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_transc.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_transc.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_conf.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_conf.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_conf.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_conf.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_core.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_core.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_core.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_core.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_enum.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_enum.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_enum.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_enum.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_pipe.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_pipe.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_pipe.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_pipe.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_transc.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_transc.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_transc.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_transc.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_adc.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_adc.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_adc.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_adc.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_bkp.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_bkp.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_bkp.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_bkp.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_crc.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_crc.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_crc.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_crc.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_dac.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_dac.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_dac.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_dac.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_dbg.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_dbg.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_dbg.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_dbg.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_dma.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_dma.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_dma.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_dma.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_eclic.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_eclic.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_eclic.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_eclic.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_exmc.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_exmc.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_exmc.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_exmc.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_exti.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_exti.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_exti.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_exti.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_fmc.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_fmc.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_fmc.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_fmc.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_fwdgt.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_fwdgt.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_fwdgt.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_fwdgt.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_gpio.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_gpio.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_gpio.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_gpio.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_i2c.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_i2c.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_i2c.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_i2c.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_libopt.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_libopt.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_libopt.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_libopt.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_pmu.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_pmu.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_pmu.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_pmu.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_rcu.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_rcu.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_rcu.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_rcu.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_rtc.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_rtc.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_rtc.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_rtc.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_spi.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_spi.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_spi.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_spi.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_timer.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_timer.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_timer.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_timer.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_usart.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_usart.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_usart.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_usart.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_wwdgt.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_wwdgt.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_wwdgt.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_wwdgt.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/n200_func.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/n200_func.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/n200_func.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/n200_func.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/nuclei_sdk_soc.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/nuclei_sdk_soc.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/nuclei_sdk_soc.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/nuclei_sdk_soc.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/system_gd32vf103.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/system_gd32vf103.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/system_gd32vf103.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/system_gd32vf103.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usb_core.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usb_core.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usb_core.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usb_core.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usb_dev.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usb_dev.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usb_dev.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usb_dev.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usb_host.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usb_host.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usb_host.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usb_host.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usbd_int.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usbd_int.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usbd_int.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usbd_int.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usbh_int.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usbh_int.c similarity index 95% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usbh_int.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usbh_int.c index abbec3cd..3347966e 100644 --- a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usbh_int.c +++ b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usbh_int.c @@ -151,8 +151,8 @@ static uint32_t usbh_int_pipe(usb_core_driver *pudev) { \retval operation status */ static uint32_t usbh_int_txfifoempty(usb_core_driver *pudev, usb_pipe_mode pp_mode) { - uint8_t pp_num = 0U; - uint16_t word_count = 0U, len = 0U; + uint8_t pp_num = 0U; + uint16_t word_count = 0U, len = 0U; __IO uint32_t *txfiforeg = 0U, txfifostate = 0U; if (PIPE_NON_PERIOD == pp_mode) { diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/gd32vf103_usb_hw.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/gd32vf103_usb_hw.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/gd32vf103_usb_hw.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/gd32vf103_usb_hw.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_core.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_core.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_core.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_core.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_enum.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_enum.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_enum.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_enum.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_transc.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_transc.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_transc.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_transc.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_core.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_core.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_core.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_core.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_enum.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_enum.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_enum.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_enum.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_pipe.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_pipe.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_pipe.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_pipe.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_transc.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_transc.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_transc.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_transc.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_adc.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_adc.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_adc.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_adc.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_bkp.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_bkp.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_bkp.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_bkp.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_crc.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_crc.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_crc.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_crc.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_dac.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_dac.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_dac.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_dac.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_dbg.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_dbg.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_dbg.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_dbg.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_dma.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_dma.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_dma.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_dma.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_eclic.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_eclic.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_eclic.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_eclic.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_exmc.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_exmc.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_exmc.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_exmc.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_exti.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_exti.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_exti.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_exti.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_fmc.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_fmc.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_fmc.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_fmc.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_fwdgt.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_fwdgt.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_fwdgt.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_fwdgt.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_gpio.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_gpio.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_gpio.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_gpio.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_i2c.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_i2c.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_i2c.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_i2c.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_pmu.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_pmu.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_pmu.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_pmu.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_rcu.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_rcu.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_rcu.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_rcu.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_rtc.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_rtc.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_rtc.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_rtc.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_spi.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_spi.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_spi.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_spi.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_timer.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_timer.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_timer.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_timer.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_usart.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_usart.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_usart.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_usart.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_wwdgt.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_wwdgt.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_wwdgt.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_wwdgt.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/n200_func.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/n200_func.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/n200_func.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/n200_func.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/GCC/intexc_gd32vf103.S b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/GCC/intexc_gd32vf103.S similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/GCC/intexc_gd32vf103.S rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/GCC/intexc_gd32vf103.S diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/GCC/startup_gd32vf103.S b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/GCC/startup_gd32vf103.S similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/GCC/startup_gd32vf103.S rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/GCC/startup_gd32vf103.S diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Stubs/close.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Stubs/close.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Stubs/close.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Stubs/close.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Stubs/fstat.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Stubs/fstat.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Stubs/fstat.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Stubs/fstat.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Stubs/gettimeofday.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Stubs/gettimeofday.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Stubs/gettimeofday.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Stubs/gettimeofday.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Stubs/isatty.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Stubs/isatty.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Stubs/isatty.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Stubs/isatty.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Stubs/lseek.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Stubs/lseek.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Stubs/lseek.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Stubs/lseek.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Stubs/read.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Stubs/read.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Stubs/read.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Stubs/read.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Stubs/sbrk.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Stubs/sbrk.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Stubs/sbrk.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Stubs/sbrk.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Stubs/stub.h b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Stubs/stub.h similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Stubs/stub.h rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Stubs/stub.h diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/gd32vf103_soc.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/gd32vf103_soc.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/gd32vf103_soc.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/gd32vf103_soc.c diff --git a/source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/system_gd32vf103.c b/source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/system_gd32vf103.c similarity index 100% rename from source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/system_gd32vf103.c rename to source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/system_gd32vf103.c diff --git a/source/Core/BSP/Pine64/configuration.h b/source/Core/BSP/Pinecil/configuration.h similarity index 97% rename from source/Core/BSP/Pine64/configuration.h rename to source/Core/BSP/Pinecil/configuration.h index 27dcd4cc..a6ae918e 100644 --- a/source/Core/BSP/Pine64/configuration.h +++ b/source/Core/BSP/Pinecil/configuration.h @@ -109,6 +109,9 @@ #define OP_AMP_GAIN_STAGE_PINECIL (1 + (OP_AMP_Rf_Pinecil / OP_AMP_Rin_Pinecil)) +#define ADC_MAX_READING (4096 * 8) // Maximum reading of the adc +#define ADC_VDD_MV 3300 // ADC max reading millivolts + #if defined(MODEL_Pinecil) == 0 #error "No model defined!" #endif @@ -145,6 +148,7 @@ #define VBUS_MOD_TEST #define HALL_SI7210 #define DEBUG_UART_OUTPUT +#define NEEDS_VBUS_PROBE 1 #define HARDWARE_MAX_WATTAGE_X10 750 #define TIP_THERMAL_MASS 65 // X10 watts to raise 1 deg C in 1 second diff --git a/source/Core/BSP/Pine64/flash.c b/source/Core/BSP/Pinecil/flash.c similarity index 100% rename from source/Core/BSP/Pine64/flash.c rename to source/Core/BSP/Pinecil/flash.c diff --git a/source/Core/BSP/Pine64/fusb_user.cpp b/source/Core/BSP/Pinecil/fusb_user.cpp similarity index 100% rename from source/Core/BSP/Pine64/fusb_user.cpp rename to source/Core/BSP/Pinecil/fusb_user.cpp diff --git a/source/Core/BSP/Pine64/postRTOS.cpp b/source/Core/BSP/Pinecil/postRTOS.cpp similarity index 100% rename from source/Core/BSP/Pine64/postRTOS.cpp rename to source/Core/BSP/Pinecil/postRTOS.cpp diff --git a/source/Core/BSP/Pine64/preRTOS.cpp b/source/Core/BSP/Pinecil/preRTOS.cpp similarity index 100% rename from source/Core/BSP/Pine64/preRTOS.cpp rename to source/Core/BSP/Pinecil/preRTOS.cpp diff --git a/source/Core/BSP/Pinecilv2/BSP.cpp b/source/Core/BSP/Pinecilv2/BSP.cpp new file mode 100644 index 00000000..3af1b474 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/BSP.cpp @@ -0,0 +1,277 @@ +// BSP mapping functions + +#include "BSP.h" +#include "I2C_Wrapper.hpp" +#include "IRQ.h" +#include "Pins.h" +#include "Setup.h" +#include "TipThermoModel.h" +#include "USBPD.h" +#include "Utils.h" +#include "configuration.h" +#include "crc32.h" +#include "history.hpp" +#include "main.hpp" + +// These control the period's of time used for the PWM +const uint16_t powerPWM = 255; +const uint8_t holdoffTicks = 25; // This is the tick delay before temp measure starts (i.e. time for op-amp recovery) +const uint8_t tempMeasureTicks = 25; + +uint16_t totalPWM = 255; // Total length of the cycle's ticks + +void resetWatchdog() { + //#TODO +} + +#ifdef TEMP_NTC +// Lookup table for the NTC +// Stored as ADCReading,Temp in degC +static const int32_t NTCHandleLookup[] = { + // ADC Reading , Temp in C x10 + + 3221, -400, // + 4144, -350, // + 5271, -300, // + 6622, -250, // + 8219, -200, // + 10075, -150, // + 12190, -100, // + 14554, -50, // + 17151, 0, // + 19937, 50, // + 22867, 100, // + 25886, 150, // + 28944, 200, // + 29546, 210, // + 30159, 220, // + 30769, 230, // + 31373, 240, // + 31969, 250, // + 32566, 260, // + 33159, 270, // + 33749, 280, // + 34334, 290, // + 34916, 300, // + 35491, 310, // + 36062, 320, // + 36628, 330, // + 37186, 340, // + 37739, 350, // + 38286, 360, // + 38825, 370, // + 39358, 380, // + 39884, 390, // + 40400, 400, // + 42879, 450, // + 45160, 500, // + 47235, 550, // + 49111, 600, // + 50792, 650, // + 52292, 700, // + 53621, 750, // + 54797, 800, // + 55836, 850, // + 56748, 900, // + 57550, 950, // + 58257, 1000, // + +}; +#endif +uint16_t getHandleTemperature(uint8_t sample) { + int32_t result = getADCHandleTemp(sample); + // Tip is wired up with an NTC thermistor + // 10K NTC balanced with a 10K pulldown + // NTCG163JF103FTDS + return Utils::InterpolateLookupTable(NTCHandleLookup, sizeof(NTCHandleLookup) / (2 * sizeof(int32_t)), result); +} + +uint16_t getInputVoltageX10(uint16_t divisor, uint8_t sample) { + uint32_t res = getADCVin(sample); + res *= 4; + res /= divisor; + return res; +} + +void unstick_I2C() { + /* configure SDA/SCL for GPIO */ + // GPIO_BC(GPIOB) |= SDA_Pin | SCL_Pin; + // gpio_init(SDA_GPIO_Port, GPIO_MODE_OUT_OD, GPIO_OSPEED_50MHZ, SDA_Pin | SCL_Pin); + // for (int i = 0; i < 8; i++) { + // asm("nop"); + // asm("nop"); + // asm("nop"); + // asm("nop"); + // asm("nop"); + // GPIO_BOP(GPIOB) |= SCL_Pin; + // asm("nop"); + // asm("nop"); + // asm("nop"); + // asm("nop"); + // asm("nop"); + // GPIO_BOP(GPIOB) &= SCL_Pin; + // } + // /* connect PB6 to I2C0_SCL */ + // /* connect PB7 to I2C0_SDA */ + // gpio_init(SDA_GPIO_Port, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, SDA_Pin | SCL_Pin); +} + +uint8_t getButtonA() { + uint8_t val = gpio_read(KEY_A_Pin); + return val; +} +uint8_t getButtonB() { + uint8_t val = gpio_read(KEY_B_Pin); + return val; +} + +void reboot() { + // Spin for watchdog + for (;;) {} +} + +void delay_ms(uint16_t count) { + // delay_1ms(count); + BL702_Delay_MS(count); +} + +uint32_t __get_IPSR(void) { + return 0; // To shut-up CMSIS +} + +bool isTipDisconnected() { + + uint16_t tipDisconnectedThres = TipThermoModel::getTipMaxInC() - 5; + uint32_t tipTemp = TipThermoModel::getTipInC(); + return tipTemp > tipDisconnectedThres; +} + +void setStatusLED(const enum StatusLED state) { + // Dont have one +} + +uint8_t lastTipResistance = 0; // default to unknown +const uint8_t numTipResistanceReadings = 3; +uint32_t tipResistanceReadings[3] = {0, 0, 0}; +uint8_t tipResistanceReadingSlot = 0; +uint8_t getTipResistanceX10() { + // Return tip resistance in x10 ohms + // We can measure this using the op-amp + return lastTipResistance; +} + +uint8_t getTipThermalMass() { + if (lastTipResistance >= 80) { + return TIP_THERMAL_MASS; + } + return (TIP_THERMAL_MASS * 25) / 10; +} +// We want to calculate lastTipResistance +// If tip is connected, and the tip is cold and the tip is not being heated +// We can use the GPIO to inject a small current into the tip and measure this +// The gpio is 5.1k -> diode -> tip -> gnd +// Source is 3.3V-0.5V +// Which is around 0.54mA this will induce: +// 6 ohm tip -> 3.24mV (Real world ~= 3320) +// 8 ohm tip -> 4.32mV (Real world ~= 4500) +// Which is definitely measureable +// Taking shortcuts here as we know we only really have to pick apart 6 and 8 ohm tips +// These are reported as 60 and 75 respectively +void performTipResistanceSampleReading() { + // 0 = read then turn on pullup, 1 = read then turn off pullup, 2 = read then turn on pullup, 3 = final read + turn off pullup + tipResistanceReadings[tipResistanceReadingSlot] = TipThermoModel::convertTipRawADCTouV(getTipRawTemp(0)); + gpio_write(TIP_RESISTANCE_SENSE, tipResistanceReadingSlot == 0); + tipResistanceReadingSlot++; +} + +void FinishMeasureTipResistance() { + + // Otherwise we now have the 4 samples; + // _^_ order, 2 delta's, combine these + + int32_t calculatedSkew = tipResistanceReadings[0] - tipResistanceReadings[2]; // If positive tip is cooling + calculatedSkew /= 2; // divide by two to get offset per time constant + + int32_t reading = (((tipResistanceReadings[1] - tipResistanceReadings[0]) + calculatedSkew) // jump 1 - skew + + // + + ((tipResistanceReadings[1] - tipResistanceReadings[2]) + calculatedSkew) // jump 2 - skew + ) // + / 2; // Take average + // lastTipResistance = reading / 100; + // // As we are only detecting two resistances; we can split the difference for now + uint8_t newRes = 0; + if (reading > 8000) { + // return; // Change nothing as probably disconnected tip + } else if (reading < 5000) { + newRes = 62; + } else { + newRes = 80; + } + lastTipResistance = newRes; +} +volatile bool tipMeasurementOccuring = true; +volatile TickType_t nextTipMeasurement = 100; + +void performTipMeasurementStep() { + + // Wait 100ms for settle time + if (xTaskGetTickCount() < (nextTipMeasurement)) { + return; + } + nextTipMeasurement = xTaskGetTickCount() + TICKS_100MS; + if (tipResistanceReadingSlot < numTipResistanceReadings) { + performTipResistanceSampleReading(); + return; + } + + // We are sensing the resistance + FinishMeasureTipResistance(); + + tipMeasurementOccuring = false; +} + +uint8_t preStartChecks() { + performTipMeasurementStep(); + return preStartChecksDone(); +} +uint8_t preStartChecksDone() { return (lastTipResistance == 0 || tipResistanceReadingSlot < numTipResistanceReadings || tipMeasurementOccuring) ? 0 : 1; } + +// Return hardware unique ID if possible +uint64_t getDeviceID() { + // uint32_t tmp = 0; + // uint32_t tmp2 = 0; + // EF_Ctrl_Read_Sw_Usage(0, &tmp); + // EF_Ctrl_Read_Sw_Usage(1, &tmp2); + + // return tmp | (((uint64_t)tmp2) << 32); + uint64_t tmp = 0; + EF_Ctrl_Read_Chip_ID((uint8_t *)&tmp); + + return __builtin_bswap64(tmp); +} +auto crc32Table = CRC32Table<>(); + +uint32_t gethash() { + static uint32_t computedHash = 0; + if (computedHash != 0) { + return computedHash; + } + + uint32_t deviceKey = EF_Ctrl_Get_Key_Slot_w0(); + const uint32_t crcInitialVector = 0xCAFEF00D; + uint8_t crcPayload[] = {(uint8_t)(deviceKey), (uint8_t)(deviceKey >> 8), (uint8_t)(deviceKey >> 16), (uint8_t)(deviceKey >> 24), 0, 0, 0, 0, 0, 0, 0, 0}; + EF_Ctrl_Read_Chip_ID(crcPayload + sizeof(deviceKey)); // Load device key into second half + + computedHash = crc32Table.computeCRC32(crcInitialVector, crcPayload, sizeof(crcPayload)); + return computedHash; +} +uint32_t getDeviceValidation() { + // 4 byte user data burned in at factory + return EF_Ctrl_Get_Key_Slot_w1(); +} + +uint8_t getDeviceValidationStatus() { + uint32_t programmedHash = EF_Ctrl_Get_Key_Slot_w1(); + uint32_t computedHash = gethash(); + return programmedHash == computedHash ? 0 : 1; +} \ No newline at end of file diff --git a/source/Core/BSP/Pinecilv2/Debug.cpp b/source/Core/BSP/Pinecilv2/Debug.cpp new file mode 100644 index 00000000..79b0a6a0 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/Debug.cpp @@ -0,0 +1,35 @@ +/* + * Debug.cpp + * + * Created on: 26 Jan. 2021 + * Author: Ralim + */ +#include "Debug.h" +#include "FreeRTOS.h" +#include "Pins.h" + +char uartOutputBuffer[uartOutputBufferLength]; +volatile uint32_t currentOutputPos = 0xFF; +volatile uint32_t outputLength = 0; +extern volatile uint8_t pendingPWM; +void log_system_state(int32_t PWMWattsx10) { + if (currentOutputPos == 0xFF) { + + // Want to print a CSV log out the uart + // Tip_Temp_C,Handle_Temp_C,Output_Power_Wattx10,PWM,Tip_Raw\r\n + // 3+1+3+1+3+1+3+1+5+2 = 23, so sizing at 32 for now + + outputLength = snprintf(uartOutputBuffer, uartOutputBufferLength, "%lu,%u,%li,%u,%lu\r\n", // + TipThermoModel::getTipInC(false), // Tip temp in C + getHandleTemperature(0), // Handle temp in C X10 + PWMWattsx10, // Output Wattage + pendingPWM, // PWM + TipThermoModel::convertTipRawADCTouV(getTipRawTemp(0), true) // Tip temp in uV + ); + + // Now print this out the uart via IRQ (DMA cant be used as oled has it) + currentOutputPos = 0; + /* enable USART1 Transmit Buffer Empty interrupt */ + // usart_interrupt_enable(UART_PERIF, USART_INT_TBE); + } +} diff --git a/source/Core/BSP/Pinecilv2/Debug.h b/source/Core/BSP/Pinecilv2/Debug.h new file mode 100644 index 00000000..5c95a132 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/Debug.h @@ -0,0 +1,22 @@ +/* + * Debug.h + * + * Created on: 26 Jan. 2021 + * Author: Ralim + */ + +#ifndef CORE_BSP_PINE64_DEBUG_H_ +#define CORE_BSP_PINE64_DEBUG_H_ + +#include "BSP.h" +#include "TipThermoModel.h" +#include +#include + +const unsigned int uartOutputBufferLength = 32; +extern char uartOutputBuffer[uartOutputBufferLength]; +extern "C" { +ssize_t _write(int fd, const void *ptr, size_t len); +void USART1_IRQHandler(void); +} +#endif /* CORE_BSP_PINE64_DEBUG_H_ */ diff --git a/source/Core/BSP/Pinecilv2/FreeRTOSConfig.h b/source/Core/BSP/Pinecilv2/FreeRTOSConfig.h new file mode 100644 index 00000000..9127e00d --- /dev/null +++ b/source/Core/BSP/Pinecilv2/FreeRTOSConfig.h @@ -0,0 +1,83 @@ +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H +#include + +#define portCHAR char +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 +#define CLINT_CTRL_ADDR (0x02000000UL) +#define configCLINT_BASE_ADDRESS CLINT_CTRL_ADDR +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ (1000000UL) +#define configTICK_RATE_HZ ((TickType_t)1000) +#define configMAX_PRIORITIES (7) +#define configMINIMAL_STACK_SIZE ((unsigned short)160) /* Only needs to be this high as some demo tasks also use this constant. In production only the idle task would use this. */ +#define configTOTAL_HEAP_SIZE ((size_t)0) +#define configMAX_TASK_NAME_LEN (24) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 +#define configUSE_TICKLESS_IDLE 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 + +/* Software timer definitions. */ +#define configUSE_TIMERS 0 + +/* Task priorities. Allow these to be overridden. */ +#ifndef uartPRIMARY_PRIORITY +#define uartPRIMARY_PRIORITY (configMAX_PRIORITIES - 3) +#endif + +#ifdef __cplusplus +extern "C" { +#endif +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +void vAssertCalled(void); + +#define configASSERT(x) \ + if ((x) == 0) \ + vAssertCalled() + +#ifdef __cplusplus +} +#endif +#if (configUSE_TICKLESS_IDLE != 0) +void vApplicationSleep(uint32_t xExpectedIdleTime); +#define portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vApplicationSleep(xExpectedIdleTime) +#endif + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_xResumeFromISR 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetIdleTaskHandle 1 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 1 +#define INCLUDE_xTimerPendFunctionCall 0 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 1 +#define INCLUDE_xTaskResumeFromISR 1 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +#endif /* FREERTOS_CONFIG_H */ diff --git a/source/Core/BSP/Pinecilv2/I2C_Wrapper.cpp b/source/Core/BSP/Pinecilv2/I2C_Wrapper.cpp new file mode 100644 index 00000000..ce80e330 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/I2C_Wrapper.cpp @@ -0,0 +1,127 @@ +/* + * FRToSI2C.cpp + * + * Created on: 14Apr.,2018 + * Author: Ralim + */ +#include "BSP.h" +#include "IRQ.h" +#include "Setup.h" +extern "C" { +#include "bflb_platform.h" +#include "bl702_glb.h" +#include "bl702_i2c.h" +} +#include + +SemaphoreHandle_t FRToSI2C::I2CSemaphore = nullptr; +StaticSemaphore_t FRToSI2C::xSemaphoreBuffer; +#define I2C_TIME_OUT (uint16_t)(12000) +void FRToSI2C::CpltCallback() {} // Not used + +bool FRToSI2C::I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data) { return Mem_Write(address, reg, &data, 1); } + +uint8_t FRToSI2C::I2C_RegisterRead(uint8_t add, uint8_t reg) { + uint8_t temp = 0; + Mem_Read(add, reg, &temp, 1); + return temp; +} + +bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address, uint8_t *p_buffer, uint16_t number_of_byte) { + if (!lock()) { + return false; + } + I2C_Transfer_Cfg i2cCfg = {0, DISABLE, 0, 0, 0, 0}; + BL_Err_Type err = ERROR; + i2cCfg.slaveAddr = DevAddress >> 1; + i2cCfg.stopEveryByte = DISABLE; + i2cCfg.subAddr = read_address; + i2cCfg.dataSize = number_of_byte; + i2cCfg.data = p_buffer; + i2cCfg.subAddrSize = 1; // one byte address + + err = I2C_MasterReceiveBlocking(I2C0_ID, &i2cCfg); + bool res = err == SUCCESS; + if (!res) { + I2C_Unstick(); + } + unlock(); + return res; +} + +bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, uint8_t *p_buffer, uint16_t number_of_byte) { + if (!lock()) { + return false; + } + I2C_Transfer_Cfg i2cCfg = {0, DISABLE, 0, 0, 0, 0}; + BL_Err_Type err = ERROR; + i2cCfg.slaveAddr = DevAddress >> 1; + i2cCfg.stopEveryByte = DISABLE; + i2cCfg.subAddr = MemAddress; + i2cCfg.dataSize = number_of_byte; + i2cCfg.data = p_buffer; + i2cCfg.subAddrSize = 1; // one byte address + + err = I2C_MasterSendBlocking(I2C0_ID, &i2cCfg); + bool res = err == SUCCESS; + if (!res) { + I2C_Unstick(); + } + unlock(); + return res; +} + +bool FRToSI2C::Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size) { return Mem_Write(DevAddress, pData[0], pData + 1, Size - 1); } + +bool FRToSI2C::probe(uint16_t DevAddress) { + uint8_t temp[1]; + return Mem_Read(DevAddress, 0x00, temp, sizeof(temp)); +} + +void FRToSI2C::I2C_Unstick() { unstick_I2C(); } + +bool FRToSI2C::lock() { + if (I2CSemaphore == nullptr) { + return false; + } + return xSemaphoreTake(I2CSemaphore, TICKS_SECOND) == pdTRUE; +} + +void FRToSI2C::unlock() { xSemaphoreGive(I2CSemaphore); } + +bool FRToSI2C::writeRegistersBulk(const uint8_t address, const I2C_REG *registers, const uint8_t registersLength) { + for (int index = 0; index < registersLength; index++) { + if (!I2C_RegisterWrite(address, registers[index].reg, registers[index].val)) { + return false; + } + if (registers[index].pause_ms) { + delay_ms(registers[index].pause_ms); + } + } + return true; +} + +bool FRToSI2C::wakePart(uint16_t DevAddress) { + // wakepart is a special case where only the device address is sent + + if (!lock()) { + return false; + } + uint8_t temp[1] = {0}; + I2C_Transfer_Cfg i2cCfg = {0, DISABLE, 0, 0, 0, 0}; + BL_Err_Type err = ERROR; + i2cCfg.slaveAddr = DevAddress >> 1; + i2cCfg.stopEveryByte = DISABLE; + i2cCfg.subAddr = 0; + i2cCfg.dataSize = 1; + i2cCfg.data = temp; + i2cCfg.subAddrSize = 0; + + err = I2C_MasterReceiveBlocking(I2C0_ID, &i2cCfg); + bool res = err == SUCCESS; + if (!res) { + I2C_Unstick(); + } + unlock(); + return res; +} diff --git a/source/Core/BSP/Pinecilv2/IRQ.cpp b/source/Core/BSP/Pinecilv2/IRQ.cpp new file mode 100644 index 00000000..60a20474 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/IRQ.cpp @@ -0,0 +1,178 @@ +/* + * IRQ.c + * + * Created on: 30 May 2020 + * Author: Ralim + */ + +#include "IRQ.h" +#include "Pins.h" +#include "configuration.h" +#include "history.hpp" + +extern "C" { +#include "bflb_platform.h" +#include "bl702_adc.h" +#include "bl702_glb.h" +#include "bl702_pwm.h" +#include "bl702_timer.h" +} + +#define ADC_Filter_Smooth 4 +history ADC_Vin; +history ADC_Temp; +history ADC_Tip; +void adc_fifo_irq(void) { + if (ADC_GetIntStatus(ADC_INT_FIFO_READY) == SET) { + // Read out all entries in the fifo + while (ADC_Get_FIFO_Count()) { + volatile uint32_t reading = ADC_Read_FIFO(); + // As per manual, 26 bit reading; lowest 16 are the ADC + uint16_t sample = reading & 0xFFFF; + uint8_t source = (reading >> 21) & 0b11111; + switch (source) { + case TMP36_ADC_CHANNEL: + ADC_Temp.update(sample); + break; + case TIP_TEMP_ADC_CHANNEL: + ADC_Tip.update(sample); + break; + case VIN_ADC_CHANNEL: + ADC_Vin.update(sample); + break; + + default: + break; + } + } + + // unblock the PID controller thread + if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + if (pidTaskNotification) { + vTaskNotifyGiveFromISR(pidTaskNotification, &xHigherPriorityTaskWoken); + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + } + } + } + // Clear IRQ + ADC_IntClr(ADC_INT_ALL); +} + +static bool fastPWM = false; +static void switchToFastPWM(void); + +volatile uint16_t PWMSafetyTimer = 0; +volatile uint8_t pendingPWM = 0; +volatile bool lastPeriodWasFast = false; + +// Timer 0 is used to co-ordinate the ADC and the output PWM +void timer0_comp0_callback(void) { ADC_Start(); } +void timer0_comp1_callback(void) { PWM_Channel_Disable(PWM_Channel); } +void timer0_comp2_callback(void) { + + // This occurs at timer rollover, so if we want to turn on the output PWM; we do so + if (PWMSafetyTimer) { + PWMSafetyTimer--; + if (lastPeriodWasFast != fastPWM) { + if (fastPWM) { + switchToFastPWM(); + } else { + switchToSlowPWM(); + } + } + // Update trigger for the end point of the PWM cycle + if (pendingPWM > 0) { + TIMER_SetCompValue(TIMER_CH0, TIMER_COMP_ID_1, pendingPWM - 1); + // Turn on output + PWM_Channel_Enable(PWM_Channel); + } else { + // Leave output off + PWM_Channel_Disable(PWM_Channel); + } + } else { + PWM_Channel_Disable(PWM_Channel); + } +} + +void switchToFastPWM(void) { + fastPWM = true; + totalPWM = powerPWM + tempMeasureTicks + holdoffTicks; + TIMER_SetCompValue(TIMER_CH0, TIMER_COMP_ID_2, totalPWM); + + // ~10Hz + TIMER_SetCompValue(TIMER_CH0, TIMER_COMP_ID_0, powerPWM + holdoffTicks); + // Set divider to 11 + + uint32_t tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_TCDR2, 11); + + BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpVal); +} + +void switchToSlowPWM(void) { + // 5Hz + fastPWM = false; + totalPWM = powerPWM + tempMeasureTicks / 2 + holdoffTicks / 2; + + TIMER_SetCompValue(TIMER_CH0, TIMER_COMP_ID_2, totalPWM); + // Adjust ADC + TIMER_SetCompValue(TIMER_CH0, TIMER_COMP_ID_0, powerPWM + (holdoffTicks / 2)); + + // Set divider to 22 + + uint32_t tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_TCDR2, 22); + + BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpVal); +} +void setTipPWM(const uint8_t pulse, const bool shouldUseFastModePWM) { + PWMSafetyTimer = 10; // This is decremented in the handler for PWM so that the tip pwm is + // disabled if the PID task is not scheduled often enough. + pendingPWM = pulse; + fastPWM = shouldUseFastModePWM; +} +extern osThreadId POWTaskHandle; + +void GPIO_IRQHandler(void) { + if (SET == GLB_Get_GPIO_IntStatus(FUSB302_IRQ_GLB_Pin)) { + GLB_GPIO_IntClear(FUSB302_IRQ_GLB_Pin, SET); +#if POW_PD + if (POWTaskHandle != nullptr) { + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + xTaskNotifyFromISR(POWTaskHandle, 1, eSetBits, &xHigherPriorityTaskWoken); + /* Force a context switch if xHigherPriorityTaskWoken is now set to pdTRUE. + The macro used to do this is dependent on the port and may be called + portEND_SWITCHING_ISR. */ + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + } +#endif + + /* timeout check */ + uint32_t timeOut = 32; + + do { + timeOut--; + } while ((SET == GLB_Get_GPIO_IntStatus(FUSB302_IRQ_GLB_Pin)) && timeOut); + + if (!timeOut) { + // MSG("WARNING: Clear GPIO interrupt status fail.\r\n"); + } + + GLB_GPIO_IntClear(FUSB302_IRQ_GLB_Pin, RESET); + } +} + +bool getFUS302IRQLow() { + // Return true if the IRQ line is still held low + return !gpio_read(FUSB302_IRQ_Pin); +} + +uint16_t getADCHandleTemp(uint8_t sample) { return ADC_Temp.average(); } + +uint16_t getADCVin(uint8_t sample) { return ADC_Vin.average(); } + +// Returns either average or instant value. When sample is set the samples from the injected ADC are copied to the filter and then the raw reading is returned +uint16_t getTipRawTemp(uint8_t sample) { return ADC_Tip.average() >> 1; } diff --git a/source/Core/BSP/Pinecilv2/IRQ.h b/source/Core/BSP/Pinecilv2/IRQ.h new file mode 100644 index 00000000..1e66b904 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/IRQ.h @@ -0,0 +1,28 @@ +/* + * Irqs.h + * + * Created on: 30 May 2020 + * Author: Ralim + */ + +#ifndef BSP_PINE64_IRQ_H_ +#define BSP_PINE64_IRQ_H_ + +#include "BSP.h" +#include "I2C_Wrapper.hpp" +#include "Setup.h" +#include "main.hpp" + +#ifdef __cplusplus +extern "C" { +#endif +void timer0_comp0_callback(void); +void timer0_comp1_callback(void); +void timer0_comp2_callback(void); +void adc_fifo_irq(void); +void GPIO_IRQHandler(void); +void switchToSlowPWM(void); +#ifdef __cplusplus +} +#endif +#endif /* BSP_PINE64_IRQ_H_ */ diff --git a/source/Core/BSP/Pinecilv2/NOTES.md b/source/Core/BSP/Pinecilv2/NOTES.md new file mode 100644 index 00000000..2482821e --- /dev/null +++ b/source/Core/BSP/Pinecilv2/NOTES.md @@ -0,0 +1,38 @@ +# Notes on RISC-V + +## Pinmap + +| Pin Number | Name | Function | Notes | +| ---------- | ---- | ---------------- | ----------- | +| 17 | PB2 | BOOT2 | Pulldown | +| 32 | | IMU INT 1 | N/A | +| 30 | | IMU INT 2 | N/A | +| | PA4 | Handle Temp | ADC Input ? | +| | PA1 | Tip Temp | ADC Input ? | +| | PB1 | B Button | Active High | +| | PB0 | A Button | Active High | +| | PA11 | USB D- | - | +| | PA12 | USB D+ | - | +| | PA6 | Tip PWM Out | - | +| | PA0 | Input DC V Sense | ADC Input ? | +| | PA9 | OLED Reset | | +| | PB7 | SDA | I2C0_SDA | +| | PB6 | SCL | I2C0_SCL | + +## ADC Configuration + +For now running in matching mode for TS100 + +- X channels DMA in background +- Sample tip using "Intereted" channels using TIMER 0,1,3 TRGO or timer0,1,2 channels +- Using just 12 bit mode for now and move to hardware oversampling later +- use DMA for normal samples and 4x16 bit regs for tip temp +- It has dual ADC's so run them in pair mode + +## Timers + +### Timer 2 + +Timer 2 CH0 is tip drive PWM out. +This is fixed at 50% duty cycle and used via the cap to turn on the heater tip. +This should toggle relatively quickly. diff --git a/source/Core/BSP/Pinecilv2/Pins.h b/source/Core/BSP/Pinecilv2/Pins.h new file mode 100644 index 00000000..3baf060c --- /dev/null +++ b/source/Core/BSP/Pinecilv2/Pins.h @@ -0,0 +1,43 @@ +/* + * Pins.h + * + * Created on: 29 May 2020 + * Author: Ralim + */ + +#ifndef BSP_PINE64_PINS_H_ +#define BSP_PINE64_PINS_H_ +#include "bl702_adc.h" +#include "hal_gpio.h" + +#define KEY_B_Pin GPIO_PIN_28 +#define TMP36_INPUT_Pin GPIO_PIN_20 +#define TMP36_ADC_CHANNEL ADC_CHAN10 +#define TIP_TEMP_Pin GPIO_PIN_19 +#define TIP_TEMP_ADC_CHANNEL ADC_CHAN9 + +#define TIP_RESISTANCE_SENSE GPIO_PIN_24 +#define VIN_Pin GPIO_PIN_18 +#define VIN_ADC_CHANNEL ADC_CHAN8 +#define OLED_RESET_Pin GPIO_PIN_3 +#define KEY_A_Pin GPIO_PIN_25 +#define PWM_Out_Pin GPIO_PIN_21 +#define PWM_Channel PWM_CH1 +#define SCL_Pin GPIO_PIN_11 +#define SDA_Pin GPIO_PIN_10 + +#define USB_DM_Pin GPIO_PIN_8 +#define QC_DP_LOW_Pin GPIO_PIN_5 + +// LOW = low resistance, HIGH = high resistance +#define QC_DM_LOW_Pin GPIO_PIN_4 +#define QC_DM_HIGH_Pin GPIO_PIN_6 + +#define FUSB302_IRQ_Pin GPIO_PIN_16 +#define FUSB302_IRQ_GLB_Pin GLB_GPIO_PIN_16 + +// uart +#define UART_TX_Pin GPIO_PIN_22 +#define UART_RX_Pin GPIO_PIN_23 + +#endif /* BSP_PINE64_PINS_H_ */ diff --git a/source/Core/BSP/Pinecilv2/Power.cpp b/source/Core/BSP/Pinecilv2/Power.cpp new file mode 100644 index 00000000..f10dfacd --- /dev/null +++ b/source/Core/BSP/Pinecilv2/Power.cpp @@ -0,0 +1,40 @@ +#include "BSP.h" +#include "BSP_Power.h" +#include "Pins.h" +#include "QC3.h" +#include "Settings.h" +#include "USBPD.h" +#include "configuration.h" + +void power_check() { +#if POW_PD + // Cant start QC until either PD works or fails + if (!USBPowerDelivery::negotiationComplete()) { + return; + } + if (USBPowerDelivery::negotiationHasWorked()) { + return; // We are using PD + } +#endif +#ifdef POW_QC + QC_resync(); +#endif +} + +bool getIsPoweredByDCIN() { +#if POW_PD + if (!USBPowerDelivery::negotiationComplete()) { + return false; // We are assuming not dc while negotiating + } + if (USBPowerDelivery::negotiationHasWorked()) { + return false; // We are using PD + } +#endif + +#ifdef POW_QC + if (hasQCNegotiated()) { + return false; // We are using QC + } +#endif + return true; +} diff --git a/source/Core/BSP/Pinecilv2/QC_GPIO.cpp b/source/Core/BSP/Pinecilv2/QC_GPIO.cpp new file mode 100644 index 00000000..644c5ac6 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/QC_GPIO.cpp @@ -0,0 +1,61 @@ +/* + * QC.c + * + * Created on: 29 May 2020 + * Author: Ralim + */ +#include "BSP.h" +#include "Pins.h" +#include "QC3.h" +#include "Settings.h" + +#ifdef POW_QC +void QC_DPlusZero_Six() { + // pull down D+ + gpio_write(QC_DP_LOW_Pin, 0); +} +void QC_DNegZero_Six() { + gpio_write(QC_DM_HIGH_Pin, 0); + gpio_write(QC_DM_LOW_Pin, 1); +} +void QC_DPlusThree_Three() { + // pull up D+ + gpio_write(QC_DP_LOW_Pin, 1); +} +void QC_DNegThree_Three() { + gpio_write(QC_DM_LOW_Pin, 1); + gpio_write(QC_DM_HIGH_Pin, 1); +} +void QC_DM_PullDown() { + // Turn on pulldown on D- + gpio_set_mode(USB_DM_Pin, GPIO_INPUT_PD_MODE); + gpio_set_mode(QC_DM_LOW_Pin, GPIO_INPUT_PD_MODE); + gpio_set_mode(QC_DM_HIGH_Pin, GPIO_INPUT_PD_MODE); +} +void QC_DM_No_PullDown() { + // Turn off pulldown on d- + gpio_set_mode(USB_DM_Pin, GPIO_INPUT_MODE); +} +void QC_Init_GPIO() { + // Setup any GPIO into the right states for QC + // D+ pulldown as output + gpio_set_mode(QC_DP_LOW_Pin, GPIO_OUTPUT_MODE); + gpio_write(QC_DP_LOW_Pin, 0); + // Make two D- pins floating + gpio_set_mode(USB_DM_Pin, GPIO_INPUT_MODE); + gpio_set_mode(QC_DM_LOW_Pin, GPIO_INPUT_MODE); + gpio_set_mode(QC_DM_HIGH_Pin, GPIO_INPUT_MODE); +} +void QC_Post_Probe_En() { + // Make two D- pins outputs + gpio_set_mode(QC_DM_LOW_Pin, GPIO_OUTPUT_MODE); + gpio_set_mode(QC_DM_HIGH_Pin, GPIO_OUTPUT_MODE); +} + +uint8_t QC_DM_PulledDown() { return gpio_read(USB_DM_Pin) == 0; } +#endif +void QC_resync() { +#ifdef POW_QC + seekQC(getSettingValue(SettingsOptions::QCIdealVoltage), getSettingValue(SettingsOptions::VoltageDiv)); // Run the QC seek again if we have drifted too much +#endif +} diff --git a/source/Core/BSP/Pinecilv2/README.md b/source/Core/BSP/Pinecilv2/README.md new file mode 100644 index 00000000..21b32ac8 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/README.md @@ -0,0 +1,3 @@ +# BSP section for Pinecil v2 + +This folder contains the hardware abstractions required for the Pinecil V2. A RISC-V based soldering iron. diff --git a/source/Core/BSP/Pinecilv2/Setup.cpp b/source/Core/BSP/Pinecilv2/Setup.cpp new file mode 100644 index 00000000..85ffcf63 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/Setup.cpp @@ -0,0 +1,157 @@ +/* + * Setup.c + * + * Created on: 29Aug.,2017 + * Author: Ben V. Brown + */ +#include "Setup.h" +#include "BSP.h" +#include "Debug.h" +#include "FreeRTOSConfig.h" +#include "Pins.h" + +#include "IRQ.h" +#include "history.hpp" +#include +#define ADC_NORM_SAMPLES 16 +#define ADC_FILTER_LEN 4 +uint16_t ADCReadings[ADC_NORM_SAMPLES]; // room for 32 lots of the pair of readings + +// Functions + +void setup_timer_scheduler(void); +void setup_pwm(void); +void setup_adc(void); +void hardware_init() { + gpio_set_mode(OLED_RESET_Pin, GPIO_OUTPUT_MODE); + gpio_set_mode(KEY_A_Pin, GPIO_INPUT_PD_MODE); + gpio_set_mode(KEY_B_Pin, GPIO_INPUT_PD_MODE); + gpio_set_mode(TMP36_INPUT_Pin, GPIO_INPUT_MODE); + gpio_set_mode(TIP_TEMP_Pin, GPIO_INPUT_MODE); + gpio_set_mode(VIN_Pin, GPIO_INPUT_MODE); + + gpio_set_mode(TIP_RESISTANCE_SENSE, GPIO_OUTPUT_MODE); + gpio_write(TIP_RESISTANCE_SENSE, 0); + + MSG((char *)"Pine64 Pinecilv2 Starting\r\n"); + setup_timer_scheduler(); + setup_adc(); + setup_pwm(); + I2C_ClockSet(I2C0_ID, 200000); // Sets clock to around 175kHz + TIMER_SetCompValue(TIMER_CH0, TIMER_COMP_ID_1, 0); +} +void setup_pwm(void) { + // Setup PWM we use for driving the tip + PWM_CH_CFG_Type cfg = { + PWM_Channel, // channel + PWM_CLK_XCLK, // Clock + PWM_STOP_ABRUPT, // Stop mode + PWM_POL_NORMAL, // Normal Polarity + 60, // Clock Div + 100, // Period + 0, // Thres 1 - start at beginng + 50, // Thres 2 - turn off at 50% + 0, // Interrupt pulse count + }; + + PWM_Channel_Init(&cfg); + PWM_Channel_Disable(PWM_Channel); +} + +const ADC_Chan_Type adc_tip_pos_chans[] + = {TIP_TEMP_ADC_CHANNEL, TMP36_ADC_CHANNEL, TIP_TEMP_ADC_CHANNEL, VIN_ADC_CHANNEL, TIP_TEMP_ADC_CHANNEL, TMP36_ADC_CHANNEL, TIP_TEMP_ADC_CHANNEL, VIN_ADC_CHANNEL}; +const ADC_Chan_Type adc_tip_neg_chans[] = {ADC_CHAN_GND, ADC_CHAN_GND, ADC_CHAN_GND, ADC_CHAN_GND, ADC_CHAN_GND, ADC_CHAN_GND, ADC_CHAN_GND, ADC_CHAN_GND}; +static_assert(sizeof(adc_tip_pos_chans) == sizeof(adc_tip_neg_chans)); + +void setup_adc(void) { + // + ADC_CFG_Type adc_cfg = {}; + ADC_FIFO_Cfg_Type adc_fifo_cfg = {}; + + CPU_Interrupt_Disable(GPADC_DMA_IRQn); + + ADC_IntMask(ADC_INT_ALL, MASK); + + adc_cfg.clkDiv = ADC_CLK_DIV_4; + adc_cfg.vref = ADC_VREF_3P2V; + adc_cfg.resWidth = ADC_DATA_WIDTH_14_WITH_64_AVERAGE; + adc_cfg.inputMode = ADC_INPUT_SINGLE_END; + adc_cfg.v18Sel = ADC_V18_SEL_1P72V; + adc_cfg.v11Sel = ADC_V11_SEL_1P1V; + adc_cfg.gain1 = ADC_PGA_GAIN_NONE; + adc_cfg.gain2 = ADC_PGA_GAIN_NONE; + adc_cfg.chopMode = ADC_CHOP_MOD_AZ_ON; + adc_cfg.biasSel = ADC_BIAS_SEL_MAIN_BANDGAP; + adc_cfg.vcm = ADC_PGA_VCM_1P6V; + adc_cfg.offsetCalibEn = ENABLE; + adc_cfg.offsetCalibVal = 0; + + ADC_Disable(); + ADC_Enable(); + ADC_Reset(); + + ADC_Init(&adc_cfg); + adc_fifo_cfg.dmaEn = DISABLE; + adc_fifo_cfg.fifoThreshold = ADC_FIFO_THRESHOLD_8; + ADC_FIFO_Cfg(&adc_fifo_cfg); + ADC_MIC_Bias_Disable(); + ADC_Tsen_Disable(); + + // Enable FiFo IRQ + Interrupt_Handler_Register(GPADC_DMA_IRQn, adc_fifo_irq); + ADC_IntMask(ADC_INT_FIFO_READY, UNMASK); + CPU_Interrupt_Enable(GPADC_DMA_IRQn); + ADC_Stop(); + ADC_FIFO_Clear(); + ADC_Scan_Channel_Config(adc_tip_pos_chans, adc_tip_neg_chans, sizeof(adc_tip_pos_chans) / sizeof(ADC_Chan_Type), DISABLE); +} + +void setup_timer_scheduler() { + TIMER_Disable(TIMER_CH0); + + TIMER_CFG_Type cfg = { + TIMER_CH0, // Channel + TIMER_CLKSRC_32K, // Clock source + TIMER_PRELOAD_TRIG_COMP2, // Trigger + TIMER_COUNT_PRELOAD, // Counter mode + 22, // Clock div + (uint16_t)(powerPWM + holdoffTicks), // CH0 compare (adc) + 0, // CH1 compare (pwm out) + (uint16_t)(powerPWM + tempMeasureTicks + holdoffTicks), // CH2 comapre (total period) + 0, // Preload + }; + TIMER_Init(&cfg); + + Timer_Int_Callback_Install(TIMER_CH0, TIMER_INT_COMP_0, timer0_comp0_callback); + Timer_Int_Callback_Install(TIMER_CH0, TIMER_INT_COMP_1, timer0_comp1_callback); + Timer_Int_Callback_Install(TIMER_CH0, TIMER_INT_COMP_2, timer0_comp2_callback); + + TIMER_ClearIntStatus(TIMER_CH0, TIMER_COMP_ID_0); + TIMER_ClearIntStatus(TIMER_CH0, TIMER_COMP_ID_1); + TIMER_ClearIntStatus(TIMER_CH0, TIMER_COMP_ID_2); + + TIMER_IntMask(TIMER_CH0, TIMER_INT_COMP_0, UNMASK); + TIMER_IntMask(TIMER_CH0, TIMER_INT_COMP_1, UNMASK); + TIMER_IntMask(TIMER_CH0, TIMER_INT_COMP_2, UNMASK); + CPU_Interrupt_Enable(TIMER_CH0_IRQn); + TIMER_Enable(TIMER_CH0); + // switchToSlowPWM(); +} + +void setupFUSBIRQ() { + + gpio_set_mode(FUSB302_IRQ_Pin, GPIO_SYNC_FALLING_TRIGER_INT_MODE); + CPU_Interrupt_Disable(GPIO_INT0_IRQn); + Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO_IRQHandler); + CPU_Interrupt_Enable(GPIO_INT0_IRQn); + gpio_irq_enable(FUSB302_IRQ_Pin, ENABLE); +} + +void vAssertCalled(void) { + MSG((char *)"vAssertCalled\r\n"); + PWM_Channel_Disable(PWM_Channel); + gpio_set_mode(PWM_Out_Pin, GPIO_INPUT_PD_MODE); + + while (1) + ; +} diff --git a/source/Core/BSP/Pinecilv2/Setup.h b/source/Core/BSP/Pinecilv2/Setup.h new file mode 100644 index 00000000..18591d7c --- /dev/null +++ b/source/Core/BSP/Pinecilv2/Setup.h @@ -0,0 +1,35 @@ +/* + * Setup.h + * + * Created on: 29Aug.,2017 + * Author: Ben V. Brown + */ + +#ifndef PINE_SETUP_H_ +#define PINE_SETUP_H_ +#include +extern "C" { +#include "bflb_platform.h" +#include "bl702_adc.h" +#include "bl702_common.h" +#include "bl702_glb.h" +#include "bl702_i2c.h" +#include "bl702_pwm.h" +#include "bl702_timer.h" +#include "hal_adc.h" +} +#ifdef __cplusplus +extern "C" { +#endif + +uint16_t getADC(uint8_t channel); +void hardware_init(); +uint16_t getADCHandleTemp(uint8_t sample); +uint16_t getADCVin(uint8_t sample); +#ifdef __cplusplus +} +#endif +void setupFUSBIRQ(); +extern const uint8_t holdoffTicks; +extern const uint8_t tempMeasureTicks; +#endif /* PINE_SETUP_H_ */ diff --git a/source/Core/BSP/Pinecilv2/ThermoModel.cpp b/source/Core/BSP/Pinecilv2/ThermoModel.cpp new file mode 100644 index 00000000..4515c42f --- /dev/null +++ b/source/Core/BSP/Pinecilv2/ThermoModel.cpp @@ -0,0 +1,72 @@ +/* + * ThermoModel.cpp + * + * Created on: 1 May 2021 + * Author: Ralim + */ +#include "TipThermoModel.h" +#include "Utils.h" +#include "configuration.h" + +#ifdef TEMP_uV_LOOKUP_HAKKO +const int32_t uVtoDegC[] = { + // + // uv -> temp in C + 0, 0, // + 266, 10, // + 522, 20, // + 770, 30, // + 1010, 40, // + 1244, 50, // + 1473, 60, // + 1697, 70, // + 1917, 80, // + 2135, 90, // + 2351, 100, // + 2566, 110, // + 2780, 120, // + 2994, 130, // + 3209, 140, // + 3426, 150, // + 3644, 160, // + 3865, 170, // + 4088, 180, // + 4314, 190, // + 4544, 200, // + 4777, 210, // + 5014, 220, // + 5255, 230, // + 5500, 240, // + 5750, 250, // + 6003, 260, // + 6261, 270, // + 6523, 280, // + 6789, 290, // + 7059, 300, // + 7332, 310, // + 7609, 320, // + 7889, 330, // + 8171, 340, // + 8456, 350, // + 8742, 360, // + 9030, 370, // + 9319, 380, // + 9607, 390, // + 9896, 400, // + 10183, 410, // + 10468, 420, // + 10750, 430, // + 11029, 440, // + 11304, 450, // + 11573, 460, // + 11835, 470, // + 12091, 480, // + 12337, 490, // + 12575, 500, // + +}; +#endif + +const int uVtoDegCItems = sizeof(uVtoDegC) / (2 * sizeof(int32_t)); + +uint32_t TipThermoModel::convertuVToDegC(uint32_t tipuVDelta) { return Utils::InterpolateLookupTable(uVtoDegC, uVtoDegCItems, tipuVDelta); } diff --git a/source/Core/BSP/Pinecilv2/UnitSettings.h b/source/Core/BSP/Pinecilv2/UnitSettings.h new file mode 100644 index 00000000..61fafd30 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/UnitSettings.h @@ -0,0 +1,11 @@ +/* + * UnitSettings.h + * + * Created on: 29 May 2020 + * Author: Ralim + */ + +#ifndef BSP_MAGIC_UNITSETTINGS_H_ +#define BSP_MAGIC_UNITSETTINGS_H_ + +#endif /* BSP_MAGIC_UNITSETTINGS_H_ */ diff --git a/source/Core/BSP/Pinecilv2/bl702_config.h b/source/Core/BSP/Pinecilv2/bl702_config.h new file mode 100644 index 00000000..6a399dd6 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl702_config.h @@ -0,0 +1,31 @@ +/** + * @file bl602_config.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef __BL702_CONFIG_H__ +#define __BL702_CONFIG_H__ + +#include "clock_config.h" +#include "peripheral_config.h" +#include "pinmux_config.h" + +#endif \ No newline at end of file diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/LICENSE b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/LICENSE new file mode 100644 index 00000000..85f48b21 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/LICENSE @@ -0,0 +1,202 @@ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [2020] [BOUFFALO LAB (NANJING) CO., LTD.] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. \ No newline at end of file diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/ReleaseNotes b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/ReleaseNotes new file mode 100644 index 00000000..e55bbfb8 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/ReleaseNotes @@ -0,0 +1,235 @@ +bl mcu sdk Release Notes +---------------------------- +此文件包含 bl mcu sdk 软件开发包的发行说明。 +每个版本的文字说明与发布时的说明保持一致（可能会有错别字的勘误）。 + +bl mcu sdk Release V1.4.2 +---------------------------- + +新增功能说明： + 1. 重构 dac、dma 驱动，更新 dac、dma doc + 2. 新增 arch_ffsll、arch_ctzll、arch_clzll 等函数 + 3. 优化 usb 协议栈 log 信息，msc 新增 sense code for requestSense command + +修复问题说明： + 1. 补充完整 xxx_close 函数，复位相关寄存器 + 2. 删除 drivers 下头文件部分依赖 + 3. 优化 usb 驱动中 端点0 设置 ack 的位置（放置中断中），防止重复设置。 + +bl mcu sdk Release V1.4.1 +---------------------------- + +新增功能说明： + 1. 新增 aes、ble pds31、freertos tickless、audio cube demo + 2. 新增 usb 同步传输中断方式 + 3. 新增 lwip 组件以及对应 emac demo + 4. 新增 pds31 快速唤醒功能 + 5. 文档更新，包含：flash、usb、fatfs、pm、emac、ble + +修复问题说明： + 1. pwm demo 文档中分频值修正 + 2. 修正 mtimer 获取 div 函数 + 3. 修正 dma 链表配置，当传输长度为 4095 时会配置错误，优化 if 判断 + 4. switch 禁用跳表选项 ，C flag 中添加 -fno-jump-tables + 5. 部分 cdk 工程增加 syscall.c，对系统函数重定向，否则会进 M mode 异常 + 6. 修正 gpio func macro value，该值对配置 gpio 为 uart 时会有问题，出现覆盖问题 + 7. 补全 calloc 函数，浮点打印会使用 + 8. 从驱动库文件移除 bflb_platform.h 文件，减少只使用 std drv 时的依赖项 + +bl mcu sdk Release V1.4.0 +---------------------------- + +新增功能说明： + 1. 新增 mbedtls、rt-thread、nmsis 组件,新增 rt-thread msh、mfcc、nn、dsp demo + 2. 新增 flash 模拟u盘升级、 c++、adc 中断读取、boot2 usb iap、prng demo + 3. 修改 makefile 调用 cmake 执行命令 + 4. usb 协议栈新增 usb hs 功能 + 5. freertos 新增 tickless 功能 + 6. 重构芯片驱动的公用头文件包含、删除 flash 的相关 api + 7. cdk 工程源文件更新 + 8. fatfs port接口新增 flash 读写（usb msc中可以使用） + 9. 使能所有外设的 BSP_USING_XXX 宏 + 10. ble 新增 oad 功能，带加密功能 + 11. mmheap 组件更新，链表式的内存管理减少了 ram 的使用，但是会增加 malloc 和 free 时间 + +修复问题说明： + 1. 修复 ble 在 pc上连接失败的问题，修改 capcode 可以解决 + 2. fatfs 中 FS_MAX_SS 参数需要适配其他种类的扇区，修复多个驱动注册到 fatfs 时，参数覆盖的 bug + 3. bl706_avb 文件删除其他 demo 的 pinmux，只留 camera + lcd 的配置，同理 bl706_iot 文件只留 i2s + usb + adc + pwm 配置 + 4. 修正 adc_read 函数，只读取了一个 fifo 数值，影响 adc 采样效率 + 5. 修正 usb_dc_ep_set_stall 在 端点 stall 时没有开启下一次的端点接收的问题 + + +bl mcu sdk Release V1.3.0 +---------------------------- + +新增功能说明： + 1. 新增 acomp、rtc、boot2、wdt、pm hal driver 和 demo + 2. 新增 romfs demo、usb 麦克风和扬声器双声道 demo、带 tinyjpeg 组件的 spi lcd 显示 demo + 3. 重构 boot2_iap demo，统一接口 + 4. 使能 romapi，减少 codesize + 5. 新增 flash 自动识别和配置功能，适配不同的 flash 芯片 + 6. 重构 mcu lcd 驱动层，适配多种 mcu lcd 驱动 + 7. 新增 ssd1306 spi 和 i2c 驱动，新增 ws2812 、wm8978 驱动 + 8. shell 新增颜色显示和自定义打印接口（使用各种终端工具可以查看） + 9. bl602 和 bl702 驱动库相关更新 + 10. 新增外部 cmake 工程编译方式，从而让 sdk 作为 submodule 使用 + 11. ld 文件的更新 + 12. ble lib 文件更新（需要使用最新的 toolchain（sifive）才能编译 ble demo） + +修复问题说明： + 1. 修复 eclipse openocd 调试时，openocd 版本太低导致无法调试 + 2. case 运行异常时，需要添加死循环 + 3. 驱动库的一些 bug fix + 4. 开关外设中断的重名名 + 5. fix 重复定义的宏带来的 warning + +bl mcu sdk Release V1.2.6 +---------------------------- + +新增功能说明： + 1. 重构 board 系统目录结构 + 2. 删除 SUPPORT_XXX 功能，改成 cmake 自动识别组件库并参与编译，识别参数为 TARGET_REQUIRED_LIBS + 3. 删除 device_register 中 flag 选项 + 4. 重构 timer hal 层, clock tree 和 demo + 5. 添加 自动识别内外部 flash 并切换引脚功能 + 6. 添加 2线 flash 下载支持 + 7. 默认使能 cpu 浮点支持（非打印浮点支持） + 8. 添加 bl702 qfn32 的 board 文件 + 9. 添加 boot2 hal 封装层 + 10. 添加 pid 算法 + 11. 添加 qdec hal 和 demo + +修复问题说明： + 1. 修复 开关全局中断嵌套带来的问题 + 2. 修复 使用 shell 功能时编译报错 + 3. memcpy 改用 romapi + 4. 修复 cdk 中编译 ble demo 编译报错，未添加 board 支持 + 5. 修复 pwm demo 相关宏书写错误 + 6. 修复 std 和 hal 中 switch case 返回的一些 bug + 7. cdk 相关 demo 改用 bl706_iot board + 8. 修改 keyscan 默认时钟和分频 + +bl mcu sdk Release V1.2.5 +---------------------------- + +新增功能说明： + 1. 添加 tensorflow lite 支持 + 2. gpio_set_mode 添加高阻模式 + 3. 添加 keyscan hal 驱动 + 4. 新增 shell 文件系统 + 5. 更新 clock tree 宏定义、更新 board.c 中 pinmux 初始化配置 + 6. es8388 驱动增加双通道支持 + 7. il9341 增加字库，支持大字号显示 + +修复问题说明： + 1. 修复 usb msc 中 interface num 为 0 + 2. 修复 uart 和 spi 开关 dma 时未设置 oflag 状态 + 3. 修改 CPU_ID 默认值，当不使用多核时默认为 none + 4. 修复 adc 浮点输出问题 + 5. 修复 hal pwm 相关宏书写错误 + + +bl mcu sdk Release V1.2.4 +---------------------------- + +新增功能说明： + 1. 增加部分 math 库函数对 arm dsp api 的兼容，以及优化 math 库效率 + 2. 增加 bl702 adc、camera 中断，重定义 clock tree 的相关宏， + 3. 删除 GPIO32-GPIO37，更新 GPIO 初始化和读写函数，更新 sf flash 引脚初始化 + 4. 增加 i2s 双通道支持 + 5. 增加 adc、pwm、camera 相关 api + 6. 增加 camera pingpong buffer case + 7. cdk 工程更新 + 8. 更新 openocd cfg 文件，适配 openocd 0.11 版本 + +修复问题说明： + 1. 对 pwm readme 说明修改 + 2. 修复 hal_usb 中对端点 0 状态的判断逻辑 + 3. 修复 flash 擦除扇区时多擦除扇区的问题 + 4. ble、lvgl、usb、boot2iap、adc 相关 demo 的修改 + +bl mcu sdk Release V1.2.3 +---------------------------- + +新增功能说明： + 1. 增加 case 输出成功和失败的 log 提示 + 2. 更新 cdk 工程，使用 minilibc 替代本地 libc + 3. 更新 usb api 及其他文档说明 + +修复问题说明： + 1. 修改 bl702_flash.ld 文件中 ram 的实际大小 + 2. 修复 main 函数返回时一直重入的问题 + 3. 删除 hal driver 中不需要的内容 + 4. 修复 cdk 工程中编译 camera case 存在的问题 + +bl mcu sdk Release V1.2.2 +---------------------------- + +新增功能说明： + 1. 新增 pwm 驱动 dc motor 和 step motor、dht11、custom hid 、shell demo + 2. 为所有的 examples 添加 cdk 工程 + 3. 为 cdk 工程添加 openocd 支持 + 4. 更新文档 + 5. 使用 clang-format 格式化代码 + +修复问题说明： + 1. 修复 __riscv_float_abi_single 未定义带来的 warning + 2. 修改 bl702_flash.ld 中 heap 的 分配方式 + 3. 更新 shell 组件，添加使用时删除中间字符的功能 + +bl mcu sdk Release V1.2.1 +---------------------------- + +新增功能说明： + 1. 新增 readme for demo command line build + 2. 更新 cmake 运行顺序 + 3. 更新 cdk flashloader 和 openocd cfg + 4. 更新文档 + +修复问题说明： + 1. 修复 board.c 中 ADC 的引脚初始化 + 2. 修复 ble 静态库依赖问题 + +bl mcu sdk Release V1.2.0 +---------------------------- + +新增功能说明： + 1. 新增 xz、ble 组件 + 2. usb_stack 中新增 usb video、hid、audio 驱动 + 3. 新增 bl602 driver 和 bl602_iot board + 4. 为 examples 补全 cdk 工程 + 5. 新增 ble、psram、camera、boot2_iap、emac、usb_video、usb_audio、usb_hid、gpio_int、pwm_it、flash读写、lowpower、pka、systick、timer demo + 6. 更新 flash Tools + 7. 更新 cmake 文件 + 8. 更新 mtimer 时钟频率为1M，便于计算 + 9. 文档更新 + +修复问题说明： + 1. 修复若干已知问题 + + +bl mcu sdk Release V1.1.0 +---------------------------- + +新增功能说明： + 1. 新增 lvgl 组件以及基本 demo； + 2. 新增 freertos 702 port 以及基本 demo； + 3. 新增 usb 转串口标准驱动 demo，支持博流自定义 DTR、RTS 流控协议； + 4. 文件系统添加命令行功能； + 5. hal 层添加强转宏，从而用户可以在程序内修改； + +修复问题说明： + 1. 修正 usb 设备描述符初始化宏，添加协议类代码初始化； + 2. 修复 hal 层驱动。 + + + +bl mcu sdk Release V1.0.0 +---------------------------- + +初始化项目。该项目基于 cmake 构建，包含 bl702/bl704/bl706 系列 mcu 底层驱动、基本外设例程、common 驱动以及第三方组件。 +支持 bl706_avb、bl706_iot 开发板的开发工作； +该项目也支持使用 CDK、eclipse 编译、烧写、调试代码； +该项目中还包含烧录工具、调试脚本、flash 算法文件以及构建 cmake 需要的一些工具。 + diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/bsp/bsp_common/platform/bflb_platform.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/bsp/bsp_common/platform/bflb_platform.c new file mode 100644 index 00000000..0923d8ef --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/bsp/bsp_common/platform/bflb_platform.c @@ -0,0 +1,267 @@ +/** + * @file bflb_platform.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "bflb_platform.h" +#include "hal_common.h" +#include "hal_flash.h" +#include "hal_mtimer.h" +#include "hal_uart.h" +#include "ring_buffer.h" + +extern uint32_t __HeapBase; +extern uint32_t __HeapLimit; + +static uint8_t uart_dbg_disable = 0; + +// struct heap_info mmheap_root; + +__WEAK__ void board_init(void) {} + +__WEAK__ enum uart_index_type board_get_debug_uart_index(void) { return 0; } + +void bl_show_flashinfo(void) { + SPI_Flash_Cfg_Type flashCfg; + uint8_t *pFlashCfg = NULL; + uint32_t flashCfgLen = 0; + uint32_t flashJedecId = 0; + + flashJedecId = flash_get_jedecid(); + flash_get_cfg(&pFlashCfg, &flashCfgLen); + arch_memcpy((void *)&flashCfg, pFlashCfg, flashCfgLen); + MSG("show flash cfg:\r\n"); + MSG("jedec id 0x%06X\r\n", flashJedecId); + MSG("mid 0x%02X\r\n", flashCfg.mid); + MSG("iomode 0x%02X\r\n", flashCfg.ioMode); + MSG("clk delay 0x%02X\r\n", flashCfg.clkDelay); + MSG("clk invert 0x%02X\r\n", flashCfg.clkInvert); + MSG("read reg cmd0 0x%02X\r\n", flashCfg.readRegCmd[0]); + MSG("read reg cmd1 0x%02X\r\n", flashCfg.readRegCmd[1]); + MSG("write reg cmd0 0x%02X\r\n", flashCfg.writeRegCmd[0]); + MSG("write reg cmd1 0x%02X\r\n", flashCfg.writeRegCmd[1]); + MSG("qe write len 0x%02X\r\n", flashCfg.qeWriteRegLen); + MSG("cread support 0x%02X\r\n", flashCfg.cReadSupport); + MSG("cread code 0x%02X\r\n", flashCfg.cReadMode); + MSG("burst wrap cmd 0x%02X\r\n", flashCfg.burstWrapCmd); + MSG("-------------------\r\n"); +} + +void bflb_platform_init(uint32_t baudrate) { + // static uint8_t initialized = 0; + BL_Err_Type ret = ERROR; + + cpu_global_irq_disable(); + + ret = flash_init(); + if (ret != SUCCESS) { + MSG("flash init fail!!!\r\n"); + } + board_init(); + + if (!uart_dbg_disable) { + uart_register(board_get_debug_uart_index(), "debug_log"); + struct device *uart = device_find("debug_log"); + + if (uart) { + device_open(uart, DEVICE_OFLAG_STREAM_TX | DEVICE_OFLAG_INT_RX); + device_set_callback(uart, NULL); + device_control(uart, DEVICE_CTRL_CLR_INT, (void *)(UART_RX_FIFO_IT)); + } + } + static bool initialized = false; + if (!initialized) { + // system_mmheap[0].addr = (uint8_t *)&__HeapBase; + // system_mmheap[0].mem_size = ((size_t)&__HeapLimit - (size_t)&__HeapBase); + + // if (system_mmheap[0].mem_size > 0) { + // mmheap_init(&mmheap_root, system_mmheap); + // } + + // MSG("dynamic memory init success,heap size = %d Kbyte \r\n", system_mmheap[0].mem_size / 1024); + initialized = 1; + if (ret != SUCCESS) { + MSG("flash init fail!!!\r\n"); + } + bl_show_flashinfo(); + } + MSG("Enable IRQ's\r\n"); + cpu_global_irq_enable(); +} + +#if ((defined BOOTROM) || (defined BFLB_EFLASH_LOADER)) +static uint8_t eflash_loader_logbuf[1024] __attribute__((section(".system_ram_noinit"))); +static uint32_t log_len = 0; +uint32_t bflb_platform_get_log(uint8_t *data, uint32_t maxlen) { + uint32_t len = log_len; + if (len > maxlen) { + len = maxlen; + } + memcpy(data, eflash_loader_logbuf, len); + return len; +} +#endif + +void bflb_platform_printf(char *fmt, ...) { + struct device *uart; + char print_buf[128]; + va_list ap; + + if (!uart_dbg_disable) { + va_start(ap, fmt); + vsnprintf(print_buf, sizeof(print_buf) - 1, fmt, ap); + va_end(ap); +#if ((defined BOOTROM) || (defined BFLB_EFLASH_LOADER)) + uint32_t len = strlen(print_buf); + if (log_len + len < sizeof(eflash_loader_logbuf)) { + memcpy(eflash_loader_logbuf + log_len, print_buf, len); + log_len += len; + } +#endif + uart = device_find("debug_log"); + device_write(uart, 0, (uint8_t *)print_buf, strlen(print_buf)); + } +} + +void bflb_platform_print_set(uint8_t disable) { uart_dbg_disable = disable; } + +uint8_t bflb_platform_print_get(void) { return uart_dbg_disable; } + +void bflb_platform_deinit(void) { + if (!uart_dbg_disable) { + struct device *uart = device_find("debug_log"); + if (uart) { + device_close(uart); + device_unregister("debug_log"); + } + } +} + +void bflb_platform_dump(uint8_t *data, uint32_t len) { + uint32_t i = 0; + + if (!uart_dbg_disable) { + for (i = 0; i < len; i++) { + if (i % 16 == 0) { + bflb_platform_printf("\r\n"); + } + + bflb_platform_printf("%02x ", data[i]); + } + + bflb_platform_printf("\r\n"); + } +} + +void bflb_platform_reg_dump(uint32_t addr) { bflb_platform_printf("%08x[31:0]=%08x\r\n", addr, *(volatile uint32_t *)(addr)); } + +void bflb_platform_init_time() {} + +void bflb_platform_deinit_time() {} + +void bflb_platform_set_alarm_time(uint64_t time, void (*interruptFun)(void)) { mtimer_set_alarm_time(time, interruptFun); } + +void bflb_platform_clear_time() {} + +void bflb_platform_start_time() {} + +void bflb_platform_stop_time() {} + +uint64_t bflb_platform_get_time_ms() { return mtimer_get_time_ms(); } + +uint64_t bflb_platform_get_time_us() { return mtimer_get_time_us(); } + +void bflb_platform_delay_ms(uint32_t ms) { mtimer_delay_ms(ms); } +void bflb_platform_delay_us(uint32_t us) { mtimer_delay_us(us); } + +void bflb_print_device_list(void) { + struct device *dev; + dlist_t *node; + uint8_t device_index = 0; + + MSG("Device List Print\r\n"); + + dlist_for_each(node, device_get_list_header()) { + dev = dlist_entry(node, struct device, list); + + MSG("Index %d\r\nDevice Name = %s \r\n", device_index, dev->name); + + switch (dev->type) { + case DEVICE_CLASS_GPIO: + MSG("Device Type = %s \r\n", "GPIO"); + break; + + case DEVICE_CLASS_UART: + MSG("Device Type = %s \r\n", "UART"); + break; + + case DEVICE_CLASS_SPI: + MSG("Device Type = %s \r\n", "SPI"); + break; + + case DEVICE_CLASS_I2C: + MSG("Device Type = %s \r\n", "I2C"); + break; + + case DEVICE_CLASS_ADC: + MSG("Device Type = %s \r\n", "ADC"); + break; + + case DEVICE_CLASS_DMA: + MSG("Device Type = %s \r\n", "DMA"); + break; + + case DEVICE_CLASS_TIMER: + MSG("Device Type = %s \r\n", "TIMER"); + break; + + case DEVICE_CLASS_PWM: + MSG("Device Type = %s \r\n", "PWM"); + break; + + case DEVICE_CLASS_SDIO: + MSG("Device Type = %s \r\n", "SDIO"); + break; + + case DEVICE_CLASS_USB: + MSG("Device Type = %s \r\n", "USB"); + break; + + case DEVICE_CLASS_I2S: + MSG("Device Type = %s \r\n", "I2S"); + break; + + case DEVICE_CLASS_CAMERA: + MSG("Device Type = %s \r\n", "CAMERA"); + break; + + case DEVICE_CLASS_NONE: + break; + + default: + break; + } + + MSG("Device Handle = 0x%x \r\n", dev); + MSG("---------------------\r\n", dev); + + device_index++; + } +} diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/bsp/bsp_common/platform/bflb_platform.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/bsp/bsp_common/platform/bflb_platform.h new file mode 100644 index 00000000..eaa1ef8f --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/bsp/bsp_common/platform/bflb_platform.h @@ -0,0 +1,110 @@ +/** + * @file bflb_platform.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef _BFLB_PLATFORM_H +#define _BFLB_PLATFORM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include + +#define MSG(a, ...) bflb_platform_printf(a, ##__VA_ARGS__) +#define MSG_DBG(a, ...) bflb_platform_printf(a, ##__VA_ARGS__) +#define MSG_ERR(a, ...) bflb_platform_printf(a, ##__VA_ARGS__) +#define BL_CASE_FAIL \ + { \ + MSG("case fail\r\n"); \ + } +#define BL_CASE_SUCCESS \ + { \ + MSG("case success\r\n"); \ + } + +/* compatible with old version */ +#ifndef DBG_TAG +#define DBG_TAG "DEBUG" +#endif + +/* + * The color for terminal (foreground) + * BLACK 30 + * RED 31 + * GREEN 32 + * YELLOW 33 + * BLUE 34 + * PURPLE 35 + * CYAN 36 + * WHITE 37 + */ +#define _DBG_COLOR(n) bflb_platform_printf("\033[" #n "m") +#define _DBG_LOG_HDR(lvl_name, color_n) \ + bflb_platform_printf("\033[" #color_n "m[" lvl_name "/" DBG_TAG "] ") +#define _DBG_LOG_X_END \ + bflb_platform_printf("\033[0m\n") + +#define dbg_log_line(lvl, color_n, fmt, ...) \ + do { \ + _DBG_LOG_HDR(lvl, color_n); \ + bflb_platform_printf(fmt, ##__VA_ARGS__); \ + _DBG_LOG_X_END; \ + } while (0) + +#define LOG_D(fmt, ...) dbg_log_line("D", 0, fmt, ##__VA_ARGS__) +#define LOG_I(fmt, ...) dbg_log_line("I", 35, fmt, ##__VA_ARGS__) +#define LOG_W(fmt, ...) dbg_log_line("W", 33, fmt, ##__VA_ARGS__) +#define LOG_E(fmt, ...) dbg_log_line("E", 31, fmt, ##__VA_ARGS__) +#define LOG_RAW(...) bflb_platform_printf(__VA_ARGS__) + +void bflb_platform_init(uint32_t baudrate); +void bflb_platform_printf(char *fmt, ...); +void bflb_platform_print_set(uint8_t disable); +uint8_t bflb_platform_print_get(void); +void bflb_platform_dump(uint8_t *data, uint32_t len); +void bflb_platform_reg_dump(uint32_t addr); +uint32_t bflb_platform_get_log(uint8_t *data, uint32_t maxlen); +void bflb_platform_deinit(void); + +void bflb_platform_init_time(void); +void bflb_platform_clear_time(void); +uint64_t bflb_platform_get_time_ms(void); +uint64_t bflb_platform_get_time_us(void); +void bflb_platform_start_time(void); +void bflb_platform_stop_time(void); +void bflb_platform_set_alarm_time(uint64_t time, void (*interruptFun)(void)); +void bflb_platform_deinit_time(void); +void bflb_platform_delay_ms(uint32_t ms); +void bflb_platform_delay_us(uint32_t us); + +void bflb_print_device_list(void); +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/bsp/bsp_common/platform/syscalls.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/bsp/bsp_common/platform/syscalls.c new file mode 100644 index 00000000..a87c44d5 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/bsp/bsp_common/platform/syscalls.c @@ -0,0 +1,219 @@ +#include +#include +#include +// #include "drv_mmheap.h" +#include "drv_device.h" + +extern struct heap_info mmheap_root; + +#ifdef CONF_VFS_ENABLE +#include +#endif + +/* Reentrant versions of system calls. */ + +/* global errno in RT-Thread */ +static volatile int _sys_errno = 0; + +#ifndef _REENT_ONLY +int *__errno() { + // #if (configUSE_POSIX_ERRNO == 1) + // { + // extern int FreeRTOS_errno; + + // return &FreeRTOS_errno; + // } + // #endif + return (int *)&_sys_errno; +} +#endif + +int _getpid_r(struct _reent *ptr) { return 0; } + +int _execve_r(struct _reent *ptr, const char *name, char *const *argv, char *const *env) { + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +} + +int _fcntl_r(struct _reent *ptr, int fd, int cmd, int arg) { + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +} + +int _fork_r(struct _reent *ptr) { + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +} + +int _fstat_r(struct _reent *ptr, int fd, struct stat *pstat) { + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +} + +int _isatty_r(struct _reent *ptr, int fd) { + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +} + +int _kill_r(struct _reent *ptr, int pid, int sig) { + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +} + +int _link_r(struct _reent *ptr, const char *old, const char *new) { + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +} + +_off_t _lseek_r(struct _reent *ptr, int fd, _off_t pos, int whence) { +#ifndef CONF_VFS_ENABLE + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +#else + _off_t rc; + + rc = aos_lseek(fd, pos, whence); + return rc; +#endif +} + +int _mkdir_r(struct _reent *ptr, const char *name, int mode) { +#ifndef CONF_VFS_ENABLE + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +#else + int rc; + + rc = aos_mkdir(name); + return rc; +#endif +} + +int _open_r(struct _reent *ptr, const char *file, int flags, int mode) { +#ifndef CONF_VFS_ENABLE + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +#else + int rc; + + rc = aos_open(file, flags); + return rc; +#endif +} + +int _close_r(struct _reent *ptr, int fd) { +#ifndef CONF_VFS_ENABLE + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +#else + return aos_close(fd); +#endif +} + +_ssize_t _read_r(struct _reent *ptr, int fd, void *buf, size_t nbytes) { +#ifndef CONF_VFS_ENABLE + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +#else + _ssize_t rc; + + rc = aos_read(fd, buf, nbytes); + return rc; +#endif +} + +int _rename_r(struct _reent *ptr, const char *old, const char *new) { +#ifndef CONF_VFS_ENABLE + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +#else + int rc; + + rc = aos_rename(old, new); + return rc; +#endif +} + +int _stat_r(struct _reent *ptr, const char *file, struct stat *pstat) { +#ifndef CONF_VFS_ENABLE + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +#else + int rc; + + rc = aos_stat(file, pstat); + return rc; +#endif +} + +int _unlink_r(struct _reent *ptr, const char *file) { +#ifndef CONF_VFS_ENABLE + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +#else + return aos_unlink(file); +#endif +} + +int _wait_r(struct _reent *ptr, int *status) { + /* return "not supported" */ + ptr->_errno = -ENOSYS; + return -1; +} + +_ssize_t _write_r(struct _reent *ptr, int fd, const void *buf, size_t nbytes) { +#ifndef CONF_VFS_ENABLE + struct device *uart = device_find("debug_log"); + if ((STDOUT_FILENO == fd) || (STDERR_FILENO == fd)) { + device_write(uart, 0, (uint8_t *)buf, nbytes); + } + return 0; +#else + _ssize_t rc; + + rc = aos_write(fd, buf, nbytes); + return rc; +#endif +} + +// void *_malloc_r(struct _reent *ptr, size_t size) { return NULL; } + +// void *_realloc_r(struct _reent *ptr, void *old, size_t newlen) { return NULL; } + +// void *_calloc_r(struct _reent *ptr, size_t size, size_t len) { return NULL; } + +// void _free_r(struct _reent *ptr, void *addr) {} + +void *_sbrk_r(struct _reent *ptr, ptrdiff_t incr) { return NULL; } + +/* for exit() and abort() */ +void __attribute__((noreturn)) _exit(int status) { + while (1) {} +} + +void _system(const char *s) {} + +mode_t umask(mode_t mask) { return 022; } + +int flock(int fd, int operation) { return 0; } + +/* +These functions are implemented and replaced by the 'common/time.c' file +int _gettimeofday_r(struct _reent *ptr, struct timeval *__tp, void *__tzp); +_CLOCK_T_ _times_r(struct _reent *ptr, struct tms *ptms); +*/ diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/bsp/bsp_common/usb/uart_interface.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/bsp/bsp_common/usb/uart_interface.c new file mode 100644 index 00000000..9fe57a5e --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/bsp/bsp_common/usb/uart_interface.c @@ -0,0 +1,194 @@ +/** + * @file uart_interface.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "bflb_platform.h" +#include "hal_gpio.h" +#include "uart_interface.h" +#include "hal_usb.h" +#include "hal_dma.h" + +#define USB_OUT_RINGBUFFER_SIZE (8 * 1024) +#define UART_RX_RINGBUFFER_SIZE (8 * 1024) +#define UART_TX_DMA_SIZE (4095) + +uint8_t usb_rx_mem[USB_OUT_RINGBUFFER_SIZE] __attribute__((section(".system_ram"))); +uint8_t uart_rx_mem[UART_RX_RINGBUFFER_SIZE] __attribute__((section(".system_ram"))); + +uint8_t src_buffer[UART_TX_DMA_SIZE] __attribute__((section(".tcm_code"))); + +struct device *uart1; +struct device *dma_ch2; + +Ring_Buffer_Type usb_rx_rb; +Ring_Buffer_Type uart1_rx_rb; + +void uart_irq_callback(struct device *dev, void *args, uint32_t size, uint32_t state) +{ + if (state == UART_EVENT_RX_FIFO) { + if (size && size < Ring_Buffer_Get_Empty_Length(&uart1_rx_rb)) { + Ring_Buffer_Write(&uart1_rx_rb, (uint8_t *)args, size); + } else { + MSG("RF OV\r\n"); + } + } else if (state == UART_EVENT_RTO) { + if (size && size < Ring_Buffer_Get_Empty_Length(&uart1_rx_rb)) { + Ring_Buffer_Write(&uart1_rx_rb, (uint8_t *)args, size); + } else { + MSG("RTO OV\r\n"); + } + } else if (state == UART_RX_FER_IT) { + MSG("RX ERR\r\n"); + } +} +void uart1_init(void) +{ +#ifdef UART1_INDEX + uart_register(UART1_INDEX, "uart1"); + uart1 = device_find("uart1"); + + if (uart1) { + // device_open(uart1, DEVICE_OFLAG_DMA_TX | DEVICE_OFLAG_INT_RX); + // device_set_callback(uart1, uart_irq_callback); + // device_control(uart1, DEVICE_CTRL_SET_INT, (void *)(UART_RX_FIFO_IT | UART_RTO_IT)); + } + + dma_register(DMA0_CH2_INDEX, "ch2"); + dma_ch2 = device_find("ch2"); + + if (dma_ch2) { + DMA_DEV(dma_ch2)->direction = DMA_MEMORY_TO_PERIPH; + DMA_DEV(dma_ch2)->transfer_mode = DMA_LLI_ONCE_MODE; + DMA_DEV(dma_ch2)->src_req = DMA_REQUEST_NONE; + DMA_DEV(dma_ch2)->dst_req = DMA_REQUEST_UART1_TX; + DMA_DEV(dma_ch2)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE; + DMA_DEV(dma_ch2)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE; + DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_1BYTE; + DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_1BYTE; + DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_8BIT; + DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_8BIT; + device_open(dma_ch2, 0); + } +#endif +} + +void uart1_config(uint32_t baudrate, uart_databits_t databits, uart_parity_t parity, uart_stopbits_t stopbits) +{ + device_close(uart1); + UART_DEV(uart1)->baudrate = baudrate; + UART_DEV(uart1)->stopbits = stopbits; + UART_DEV(uart1)->parity = parity; + UART_DEV(uart1)->databits = (databits - 5); + device_open(uart1, DEVICE_OFLAG_DMA_TX | DEVICE_OFLAG_INT_RX); + device_set_callback(uart1, uart_irq_callback); + device_control(uart1, DEVICE_CTRL_SET_INT, (void *)(UART_RX_FIFO_IT | UART_RTO_IT)); + Ring_Buffer_Reset(&usb_rx_rb); + Ring_Buffer_Reset(&uart1_rx_rb); +} + +static uint8_t uart1_dtr; +static uint8_t uart1_rts; + +void uart1_set_dtr_rts(uint8_t dtr, uint8_t rts) +{ + uart1_dtr = dtr; + uart1_rts = rts; +} + +void uart1_dtr_init(void) +{ + gpio_set_mode(uart1_dtr, GPIO_OUTPUT_MODE); +} +void uart1_rts_init(void) +{ + gpio_set_mode(uart1_rts, GPIO_OUTPUT_MODE); +} +void uart1_dtr_deinit(void) +{ + gpio_set_mode(uart1_dtr, GPIO_INPUT_MODE); +} +void uart1_rts_deinit(void) +{ + gpio_set_mode(uart1_rts, GPIO_INPUT_MODE); +} +void dtr_pin_set(uint8_t status) +{ + gpio_write(uart1_dtr, status); +} +void rts_pin_set(uint8_t status) +{ + gpio_write(uart1_rts, status); +} +void ringbuffer_lock() +{ + cpu_global_irq_disable(); +} +void ringbuffer_unlock() +{ + cpu_global_irq_enable(); +} + +void uart_ringbuffer_init(void) +{ + /* init mem for ring_buffer */ + memset(usb_rx_mem, 0, USB_OUT_RINGBUFFER_SIZE); + memset(uart_rx_mem, 0, UART_RX_RINGBUFFER_SIZE); + + /* init ring_buffer */ + Ring_Buffer_Init(&usb_rx_rb, usb_rx_mem, USB_OUT_RINGBUFFER_SIZE, ringbuffer_lock, ringbuffer_unlock); + Ring_Buffer_Init(&uart1_rx_rb, uart_rx_mem, UART_RX_RINGBUFFER_SIZE, ringbuffer_lock, ringbuffer_unlock); +} + +static dma_control_data_t uart_dma_ctrl_cfg = { + .bits.fix_cnt = 0, + .bits.dst_min_mode = 0, + .bits.dst_add_mode = 0, + .bits.SI = 1, + .bits.DI = 0, + .bits.SWidth = DMA_TRANSFER_WIDTH_8BIT, + .bits.DWidth = DMA_TRANSFER_WIDTH_8BIT, + .bits.SBSize = 0, + .bits.DBSize = 0, + .bits.I = 0, + .bits.TransferSize = 4095 +}; +static dma_lli_ctrl_t uart_lli_list = { + .src_addr = (uint32_t)src_buffer, + .dst_addr = DMA_ADDR_UART1_TDR, + .nextlli = 0 +}; + +void uart_send_from_ringbuffer(void) +{ + if (Ring_Buffer_Get_Length(&usb_rx_rb)) { + if (!dma_channel_check_busy(dma_ch2)) { + uint32_t avalibleCnt = Ring_Buffer_Read(&usb_rx_rb, src_buffer, UART_TX_DMA_SIZE); + + if (avalibleCnt) { + dma_channel_stop(dma_ch2); + uart_dma_ctrl_cfg.bits.TransferSize = avalibleCnt; + memcpy(&uart_lli_list.cfg, &uart_dma_ctrl_cfg, sizeof(dma_control_data_t)); + dma_channel_update(dma_ch2, (void *)((uint32_t)&uart_lli_list)); + dma_channel_start(dma_ch2); + } + } + } +} \ No newline at end of file diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/bsp/bsp_common/usb/uart_interface.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/bsp/bsp_common/usb/uart_interface.h new file mode 100644 index 00000000..46d5b0c2 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/bsp/bsp_common/usb/uart_interface.h @@ -0,0 +1,44 @@ +/** + * @file uart_interface.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef __UART_IF_H__ +#define __UART_IF_H__ + +#include "hal_uart.h" +#include "ring_buffer.h" + +extern Ring_Buffer_Type usb_rx_rb; +extern Ring_Buffer_Type uart1_rx_rb; + +void uart1_init(void); +void uart1_config(uint32_t baudrate, uart_databits_t databits, uart_parity_t parity, uart_stopbits_t stopbits); +void uart1_set_dtr_rts(uint8_t dtr, uint8_t rts); +void uart1_dtr_init(void); +void uart1_rts_init(void); +void uart1_dtr_deinit(void); +void uart1_rts_deinit(void); +void dtr_pin_set(uint8_t status); +void rts_pin_set(uint8_t status); +void uart_ringbuffer_init(void); +void uart_send_from_ringbuffer(void); +#endif \ No newline at end of file diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/bsp/bsp_common/usb/usb_dc.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/bsp/bsp_common/usb/usb_dc.c new file mode 100644 index 00000000..60dffbd0 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/bsp/bsp_common/usb/usb_dc.c @@ -0,0 +1,82 @@ +/** + * @file usb_dc.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "hal_usb.h" +#include "stdbool.h" +#include "usbd_core.h" + +struct device *usb; + +#ifdef USB_INDEX +static void usb_dc_event_callback(struct device *dev, void *args, uint32_t size, uint32_t state) +{ + usbd_event_notify_handler(state, args); +} +#endif +struct device *usb_dc_init(void) +{ +#ifdef USB_INDEX + usb_dc_register(USB_INDEX, "usb"); + usb = device_find("usb"); + device_set_callback(usb, usb_dc_event_callback); + device_open(usb, 0); + return usb; +#endif + return NULL; +} + +int usbd_set_address(const uint8_t addr) +{ + return usb_dc_set_dev_address(addr); +} + +int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg) +{ + return usb_dc_ep_open(usb, (const struct usb_dc_ep_cfg *)ep_cfg); +} +int usbd_ep_close(const uint8_t ep) +{ + return usb_dc_ep_close(ep); +} +int usbd_ep_set_stall(const uint8_t ep) +{ + return usb_dc_ep_set_stall(ep); +} +int usbd_ep_clear_stall(const uint8_t ep) +{ + return usb_dc_ep_clear_stall(ep); +} +int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled) +{ + return usb_dc_ep_is_stalled(usb, ep, stalled); +} + +int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes) +{ + return usb_dc_ep_write(usb, ep, data, data_len, ret_bytes); +} + +int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t max_data_len, uint32_t *read_bytes) +{ + return usb_dc_ep_read(usb, ep, data, max_data_len, read_bytes); +} diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/CMakeLists.txt b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/CMakeLists.txt new file mode 100644 index 00000000..8f08b7a0 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/CMakeLists.txt @@ -0,0 +1,62 @@ +################# Add global include ################# +list(APPEND ADD_INCLUDE +"${CMAKE_CURRENT_SOURCE_DIR}/ring_buffer" +"${CMAKE_CURRENT_SOURCE_DIR}/soft_crc" +"${CMAKE_CURRENT_SOURCE_DIR}/memheap" +"${CMAKE_CURRENT_SOURCE_DIR}/misc" +"${CMAKE_CURRENT_SOURCE_DIR}/list" +"${CMAKE_CURRENT_SOURCE_DIR}/device" +"${CMAKE_CURRENT_SOURCE_DIR}/partition" +"${CMAKE_CURRENT_SOURCE_DIR}/bl_math" +"${CMAKE_CURRENT_SOURCE_DIR}/pid" +"${CMAKE_CURRENT_SOURCE_DIR}/timestamp" +) +####################################################### + +################# Add private include ################# +# list(APPEND ADD_PRIVATE_INCLUDE +# ) +####################################################### + +############## Add current dir source files ########### +file(GLOB_RECURSE sources +"${CMAKE_CURRENT_SOURCE_DIR}/ring_buffer/*.c" +"${CMAKE_CURRENT_SOURCE_DIR}/soft_crc/*.c" +"${CMAKE_CURRENT_SOURCE_DIR}/memheap/*.c" +"${CMAKE_CURRENT_SOURCE_DIR}/misc/*.c" +"${CMAKE_CURRENT_SOURCE_DIR}/device/*.c" +"${CMAKE_CURRENT_SOURCE_DIR}/partition/*.c" +"${CMAKE_CURRENT_SOURCE_DIR}/bl_math/*.c" +"${CMAKE_CURRENT_SOURCE_DIR}/pid/*.c" +"${CMAKE_CURRENT_SOURCE_DIR}/timestamp/*.c" +) + +#aux_source_directory(. sources) +list(APPEND ADD_SRCS ${sources}) +####################################################### + +########### Add required/dependent components ######### +#list(APPEND ADD_REQUIREMENTS xxx) +####################################################### + +############ Add static libs ########################## +#list(APPEND ADD_STATIC_LIB "libxxx.a") +####################################################### + +############ Add dynamic libs ######################### +# list(APPEND ADD_DYNAMIC_LIB "libxxx.so" +# ) +####################################################### + +############ Add global compile option ################ +#add components denpend on this component +string(TOUPPER ${CHIP} CHIPNAME) +list(APPEND ADD_DEFINITIONS -D${CHIPNAME}) +####################################################### + +############ Add private compile option ################ +#add compile option for this component that won't affect other modules +# list(APPEND ADD_PRIVATE_DEFINITIONS -Dxxx) +####################################################### + +generate_library() diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/bl_math/arm_dsp_wrapper.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/bl_math/arm_dsp_wrapper.c new file mode 100644 index 00000000..05c62792 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/bl_math/arm_dsp_wrapper.c @@ -0,0 +1,50 @@ +/** + * @file arm_dsp_wrapper.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "arm_dsp_wrapper.h" + +void arm_fill_f32(float32_t value, float32_t *pDst, uint32_t blockSize) +{ + uint32_t blkCnt = blockSize >> 2u; + + float32_t in1 = value; + float32_t in2 = value; + float32_t in3 = value; + float32_t in4 = value; + + while (blkCnt > 0u) { + *pDst++ = in1; + *pDst++ = in2; + *pDst++ = in3; + *pDst++ = in4; + + blkCnt--; + } + + blkCnt = blockSize % 0x4u; + + while (blkCnt > 0u) { + *pDst++ = value; + blkCnt--; + } +} diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/bl_math/arm_dsp_wrapper.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/bl_math/arm_dsp_wrapper.h new file mode 100644 index 00000000..445b22a2 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/bl_math/arm_dsp_wrapper.h @@ -0,0 +1,44 @@ +/** + * @file arm_dsp_wrapper.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef __MY_MATH_F_H__ +#define __MY_MATH_F_H__ + +#include "misc.h" +#include "math.h" + +typedef float float32_t; + +__INLINE__ float32_t arm_sqrt_f32(float32_t x) +{ + return sqrtf(x); +} + +__INLINE__ float32_t arm_cos_f32(float32_t x) +{ + return cosf(x); +} + +void arm_fill_f32(float32_t value, float32_t *pDst, uint32_t blockSize); + +#endif \ No newline at end of file diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/device/drv_device.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/device/drv_device.c new file mode 100644 index 00000000..e02a8371 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/device/drv_device.c @@ -0,0 +1,294 @@ +/** + * @file drv_device.c + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "drv_device.h" + +#define DEVICE_CHECK_PARAM + +#define dev_open (dev->open) +#define dev_close (dev->close) +#define dev_read (dev->read) +#define dev_write (dev->write) +#define dev_control (dev->control) + +dlist_t device_head = DLIST_OBJECT_INIT(device_head); + +/** + * This function get device list header + * + * @param None + * + * @return device header + */ +dlist_t *device_get_list_header(void) +{ + return &device_head; +} + +/** + * This function registers a device driver with specified name. + * + * @param dev the pointer of device driver structure + * @param name the device driver's name + * @param flags the capabilities flag of device + * + * @return the error code, DEVICE_EOK on initialization successfully. + */ +int device_register(struct device *dev, const char *name) +{ + dlist_t *node; + + dlist_for_each(node, &device_head) + { + struct device *dev_obj; + dev_obj = dlist_entry(node, struct device, list); + + if (dev_obj == dev) { + return -DEVICE_EEXIST; + } + } + + strcpy(dev->name, name); + + dlist_insert_after(&device_head, &(dev->list)); + dev->status = DEVICE_REGISTERED; + return DEVICE_EOK; +} + +/** + * This function unregisters a device driver with specified name. + * + * @param dev the pointer of device driver structure + * @param name the device driver's name + * @param flags the capabilities flag of device + * + * @return the error code, DEVICE_EOK on initialization successfully. + */ +int device_unregister(const char *name) +{ + struct device *dev = device_find(name); + + if (!dev) { + return -DEVICE_ENODEV; + } + dev->status = DEVICE_UNREGISTER; + /* remove from old list */ + dlist_remove(&(dev->list)); + return DEVICE_EOK; +} + +/** + * This function finds a device driver by specified name. + * + * @param name the device driver's name + * + * @return the registered device driver on successful, or NULL on failure. + */ +struct device *device_find(const char *name) +{ + struct device *dev; + dlist_t *node; + + dlist_for_each(node, &device_head) + { + dev = dlist_entry(node, struct device, list); + + if (strncmp(dev->name, name, DEVICE_NAME_MAX) == 0) { + return dev; + } + } + return NULL; +} + +/** + * This function will open a device + * + * @param dev the pointer of device driver structure + * @param oflag the flags for device open + * + * @return the result + */ +int device_open(struct device *dev, uint16_t oflag) +{ +#ifdef DEVICE_CHECK_PARAM + int retval = DEVICE_EOK; + + if ((dev->status == DEVICE_REGISTERED) || (dev->status == DEVICE_CLOSED)) { + if (dev_open != NULL) { + retval = dev_open(dev, oflag); + dev->status = DEVICE_OPENED; + dev->oflag |= oflag; + } else { + retval = -DEVICE_EFAULT; + } + } else { + retval = -DEVICE_EINVAL; + } + + return retval; +#else + return dev_open(dev, oflag); +#endif +} +/** + * This function will close a device + * + * @param dev the pointer of device driver structure + * + * @return the result + */ +int device_close(struct device *dev) +{ +#ifdef DEVICE_CHECK_PARAM + int retval = DEVICE_EOK; + + if (dev->status == DEVICE_OPENED) { + if (dev_close != NULL) { + retval = dev_close(dev); + dev->status = DEVICE_CLOSED; + dev->oflag = 0; + } else { + retval = -DEVICE_EFAULT; + } + } else { + retval = -DEVICE_EINVAL; + } + + return retval; +#else + return dev_close(dev); +#endif +} +/** + * This function will perform a variety of control functions on devices. + * + * @param dev the pointer of device driver structure + * @param cmd the command sent to device + * @param arg the argument of command + * + * @return the result + */ +int device_control(struct device *dev, int cmd, void *args) +{ +#ifdef DEVICE_CHECK_PARAM + int retval = DEVICE_EOK; + + if (dev->status > DEVICE_UNREGISTER) { + if (dev_control != NULL) { + retval = dev_control(dev, cmd, args); + } else { + retval = -DEVICE_EFAULT; + } + } else { + retval = -DEVICE_EINVAL; + } + + return retval; +#else + return dev_control(dev, cmd, args); +#endif +} +/** + * This function will write some data to a device. + * + * @param dev the pointer of device driver structure + * @param pos the position of written + * @param buffer the data buffer to be written to device + * @param size the size of buffer + * + * @return the actually written size on successful, otherwise negative returned. + */ +int device_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) +{ +#ifdef DEVICE_CHECK_PARAM + int retval = DEVICE_EOK; + + if (dev->status == DEVICE_OPENED) { + if (dev_write != NULL) { + retval = dev_write(dev, pos, buffer, size); + } else { + retval = -DEVICE_EFAULT; + } + } else { + retval = -DEVICE_EINVAL; + } + + return retval; +#else + return dev_write(dev, pos, buffer, size); +#endif +} +/** + * This function will read some data from a device. + * + * @param dev the pointer of device driver structure + * @param pos the position of reading + * @param buffer the data buffer to save read data + * @param size the size of buffer + * + * @return the actually read size on successful, otherwise negative returned. + */ +int device_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) +{ +#ifdef DEVICE_CHECK_PARAM + int retval = DEVICE_EOK; + + if (dev->status == DEVICE_OPENED) { + if (dev_read != NULL) { + retval = dev_read(dev, pos, buffer, size); + } else { + retval = -DEVICE_EFAULT; + } + } else { + retval = -DEVICE_EINVAL; + } + + return retval; +#else + return dev_read(dev, pos, buffer, size); +#endif +} +/** + * This function will read some data from a device. + * + * @param dev the pointer of device driver structure + * @param pos the position of reading + * @param buffer the data buffer to save read data + * @param size the size of buffer + * + * @return the actually read size on successful, otherwise negative returned. + */ +int device_set_callback(struct device *dev, void (*callback)(struct device *dev, void *args, uint32_t size, uint32_t event)) +{ + int retval = DEVICE_EOK; + + if (dev->status > DEVICE_UNREGISTER) { + if (callback != NULL) { + dev->callback = callback; + } else { + retval = -DEVICE_EFAULT; + } + } else { + retval = -DEVICE_EINVAL; + } + + return retval; +} \ No newline at end of file diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/device/drv_device.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/device/drv_device.h new file mode 100644 index 00000000..a7a820f0 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/device/drv_device.h @@ -0,0 +1,135 @@ +/** + * @file drv_device.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __DRV_DEVICE_H__ +#define __DRV_DEVICE_H__ + +#include "drv_list.h" +#include "stdio.h" + +#define DEVICE_NAME_MAX 20 /* max device name*/ + +#define DEVICE_OFLAG_DEFAULT 0x000 /* open with default */ +#define DEVICE_OFLAG_STREAM_TX 0x001 /* open with poll tx */ +#define DEVICE_OFLAG_STREAM_RX 0x002 /* open with poll rx */ +#define DEVICE_OFLAG_INT_TX 0x004 /* open with interrupt tx */ +#define DEVICE_OFLAG_INT_RX 0x008 /* open with interrupt rx */ +#define DEVICE_OFLAG_DMA_TX 0x010 /* open with dma tx */ +#define DEVICE_OFLAG_DMA_RX 0x020 /* open with dma rx */ + +#define DEVICE_CTRL_SET_INT 0x01 /* set interrupt */ +#define DEVICE_CTRL_CLR_INT 0x02 /* clear interrupt */ +#define DEVICE_CTRL_GET_INT 0x03 /* get interrupt status*/ +#define DEVICE_CTRL_RESUME 0x04 /* resume device */ +#define DEVICE_CTRL_SUSPEND 0x05 /* suspend device */ +#define DEVICE_CTRL_CONFIG 0x06 /* config device */ +#define DEVICE_CTRL_GET_CONFIG 0x07 /* get device configuration */ +#define DEVICE_CTRL_ATTACH_TX_DMA 0x08 /* deivce link tx dma */ +#define DEVICE_CTRL_ATTACH_RX_DMA 0x09 /* deivce link rx dma */ +#define DEVICE_CTRL_TX_DMA_SUSPEND 0x0a /* deivce suspend tx dma */ +#define DEVICE_CTRL_RX_DMA_SUSPEND 0x0b /* deivce suspend rx dma */ +#define DEVICE_CTRL_TX_DMA_RESUME 0x0c /* deivce resume tx dma */ +#define DEVICE_CTRL_RX_DMA_RESUME 0x0d /* deivce resume rx dma */ +#define DEVICE_CTRL_RESVD1 0x0E +#define DEVICE_CTRL_RESVD2 0x0F + +/* + * POSIX Error codes + */ + +#define DEVICE_EOK 0 +#define DEVICE_EFAULT 14 /* Bad address */ +#define DEVICE_EEXIST 17 /* device exists */ +#define DEVICE_ENODEV 19 /* No such device */ +#define DEVICE_EINVAL 22 /* Invalid argument */ +#define DEVICE_ENOSPACE 23 /* No more Device for Allocate */ + +#define __ASSERT_PRINT(fmt, ...) printf(fmt, ##__VA_ARGS__) + +#define __ASSERT_LOC(test) \ + __ASSERT_PRINT("ASSERTION FAIL [%s] @ %s:%d\n", \ + #test, \ + __FILE__, __LINE__) + +#define DEVICE_ASSERT(test, fmt, ...) \ + do { \ + if (!(test)) { \ + __ASSERT_LOC(test); \ + __ASSERT_PRINT(fmt, ##__VA_ARGS__); \ + } \ + } while (0) + +enum device_class_type { + DEVICE_CLASS_NONE = 0, + DEVICE_CLASS_GPIO, + DEVICE_CLASS_UART, + DEVICE_CLASS_SPI, + DEVICE_CLASS_I2C, + DEVICE_CLASS_ADC, + DEVICE_CLASS_DAC, + DEVICE_CLASS_DMA, + DEVICE_CLASS_TIMER, + DEVICE_CLASS_PWM, + DEVICE_CLASS_QDEC, + DEVICE_CLASS_SDIO, + DEVICE_CLASS_USB, + DEVICE_CLASS_RMII, + DEVICE_CLASS_I2S, + DEVICE_CLASS_CAMERA, + DEVICE_CLASS_SEC_HASH, + DEVICE_CLASS_KEYSCAN, +}; + +enum device_status_type { + DEVICE_UNREGISTER = 0, + DEVICE_REGISTERED, + DEVICE_OPENED, + DEVICE_CLOSED +}; + +struct device { + char name[DEVICE_NAME_MAX]; /*name of device */ + dlist_t list; /*list node of device */ + enum device_status_type status; /*status of device */ + enum device_class_type type; /*type of device */ + uint16_t oflag; /*oflag of device */ + + int (*open)(struct device *dev, uint16_t oflag); + int (*close)(struct device *dev); + int (*control)(struct device *dev, int cmd, void *args); + int (*write)(struct device *dev, uint32_t pos, const void *buffer, uint32_t size); + int (*read)(struct device *dev, uint32_t pos, void *buffer, uint32_t size); + void (*callback)(struct device *dev, void *args, uint32_t size, uint32_t event); + void *handle; +}; + +int device_register(struct device *dev, const char *name); +int device_unregister(const char *name); +struct device *device_find(const char *name); +int device_open(struct device *dev, uint16_t oflag); +int device_close(struct device *dev); +int device_control(struct device *dev, int cmd, void *args); +int device_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size); +int device_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size); +int device_set_callback(struct device *dev, void (*callback)(struct device *dev, void *args, uint32_t size, uint32_t event)); +dlist_t *device_get_list_header(void); +#endif \ No newline at end of file diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/list/drv_list.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/list/drv_list.h new file mode 100644 index 00000000..5c2beadb --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/list/drv_list.h @@ -0,0 +1,472 @@ +/** + * @file drv_list.h + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __DRV_LIST_H__ +#define __DRV_LIST_H__ + +#include "string.h" +#include "stdint.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * container_of - return the member address of ptr, if the type of ptr is the + * struct type. + */ +#define container_of(ptr, type, member) \ + ((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member))) + +/** + * Double List structure + */ +struct dlist_node { + struct dlist_node *next; /**< point to next node. */ + struct dlist_node *prev; /**< point to prev node. */ +}; +typedef struct dlist_node dlist_t; /**< Type for lists. */ + +/** + * @brief initialize a list + * + * @param l list to be initialized + */ +static inline void dlist_init(dlist_t *l) +{ + l->next = l->prev = l; +} + +/** + * @brief insert a node after a list + * + * @param l list to insert it + * @param n new node to be inserted + */ +static inline void dlist_insert_after(dlist_t *l, dlist_t *n) +{ + l->next->prev = n; + n->next = l->next; + + l->next = n; + n->prev = l; +} + +/** + * @brief insert a node before a list + * + * @param n new node to be inserted + * @param l list to insert it + */ +static inline void dlist_insert_before(dlist_t *l, dlist_t *n) +{ + l->prev->next = n; + n->prev = l->prev; + + l->prev = n; + n->next = l; +} + +/** + * @brief remove node from list. + * @param n the node to remove from the list. + */ +static inline void dlist_remove(dlist_t *n) +{ + n->next->prev = n->prev; + n->prev->next = n->next; + + n->next = n->prev = n; +} + +/** + * @brief move node from list. + * @param n the node to remove from the list. + */ +static inline void dlist_move_head(dlist_t *l, dlist_t *n) +{ + dlist_remove(n); + dlist_insert_after(l, n); +} + +/** + * @brief move node from list. + * @param n the node to remove from the list. + */ +static inline void dlist_move_tail(dlist_t *l, dlist_t *n) +{ + dlist_remove(n); + dlist_insert_before(l, n); +} + +/** + * @brief tests whether a list is empty + * @param l the list to test. + */ +static inline int dlist_isempty(const dlist_t *l) +{ + return l->next == l; +} + +/** + * @brief get the list length + * @param l the list to get. + */ +static inline unsigned int dlist_len(const dlist_t *l) +{ + unsigned int len = 0; + const dlist_t *p = l; + + while (p->next != l) { + p = p->next; + len++; + } + + return len; +} + +/** + * @brief initialize a dlist object + */ +#define DLIST_OBJECT_INIT(object) \ + { \ + &(object), &(object) \ + } +/** + * @brief initialize a dlist object + */ +#define DLIST_DEFINE(list) \ + dlist_t list = { &(list), &(list) } + +/** + * @brief get the struct for this entry + * @param node the entry point + * @param type the type of structure + * @param member the name of list in structure + */ +#define dlist_entry(node, type, member) \ + container_of(node, type, member) + +/** + * dlist_first_entry - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define dlist_first_entry(ptr, type, member) \ + dlist_entry((ptr)->next, type, member) +/** + * dlist_first_entry_or_null - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define dlist_first_entry_or_null(ptr, type, member) \ + (dlist_isempty(ptr) ? NULL : dlist_first_entry(ptr, type, member)) + +/** + * dlist_for_each - iterate over a list + * @pos: the dlist_t * to use as a loop cursor. + * @head: the head for your list. + */ +#define dlist_for_each(pos, head) \ + for (pos = (head)->next; pos != (head); pos = pos->next) + +/** + * dlist_for_each_prev - iterate over a list + * @pos: the dlist_t * to use as a loop cursor. + * @head: the head for your list. + */ +#define dlist_for_each_prev(pos, head) \ + for (pos = (head)->prev; pos != (head); pos = pos->prev) + +/** + * dlist_for_each_safe - iterate over a list safe against removal of list entry + * @pos: the dlist_t * to use as a loop cursor. + * @n: another dlist_t * to use as temporary storage + * @head: the head for your list. + */ +#define dlist_for_each_safe(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) + +#define dlist_for_each_prev_safe(pos, n, head) \ + for (pos = (head)->prev, n = pos->prev; pos != (head); \ + pos = n, n = pos->prev) +/** + * dlist_for_each_entry - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define dlist_for_each_entry(pos, head, member) \ + for (pos = dlist_entry((head)->next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = dlist_entry(pos->member.next, typeof(*pos), member)) + +/** + * dlist_for_each_entry_reverse - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define dlist_for_each_entry_reverse(pos, head, member) \ + for (pos = dlist_entry((head)->prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = dlist_entry(pos->member.prev, typeof(*pos), member)) + +/** + * dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define dlist_for_each_entry_safe(pos, n, head, member) \ + for (pos = dlist_entry((head)->next, typeof(*pos), member), \ + n = dlist_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = dlist_entry(n->member.next, typeof(*n), member)) + +/** + * dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define dlist_for_each_entry_safe_reverse(pos, n, head, member) \ + for (pos = dlist_entry((head)->prev, typeof(*pos), field), \ + n = dlist_entry(pos->member.prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = dlist_entry(pos->member.prev, typeof(*pos), member)) + +/** + * Single List structure + */ +struct slist_node { + struct slist_node *next; /**< point to next node. */ +}; +typedef struct slist_node slist_t; /**< Type for single list. */ + +/** + * @brief initialize a single list + * + * @param l the single list to be initialized + */ +static inline void slist_init(slist_t *l) +{ + l->next = NULL; +} + +static inline void slist_add_head(slist_t *l, slist_t *n) +{ + n->next = l->next; + l->next = n; +} + +static inline void slist_add_tail(slist_t *l, slist_t *n) +{ + while (l->next) { + l = l->next; + } + + /* append the node to the tail */ + l->next = n; + n->next = NULL; +} + +static inline void slist_insert(slist_t *l, slist_t *next, slist_t *n) +{ + if (!next) { + slist_add_tail(next, l); + return; + } + + while (l->next) { + if (l->next == next) { + l->next = n; + n->next = next; + } + + l = l->next; + } +} + +static inline slist_t *slist_remove(slist_t *l, slist_t *n) +{ + /* remove slist head */ + while (l->next && l->next != n) { + l = l->next; + } + + /* remove node */ + if (l->next != (slist_t *)0) { + l->next = l->next->next; + } + + return l; +} + +static inline unsigned int slist_len(const slist_t *l) +{ + unsigned int len = 0; + const slist_t *list = l->next; + + while (list != NULL) { + list = list->next; + len++; + } + + return len; +} + +static inline unsigned int slist_contains(slist_t *l, slist_t *n) +{ + while (l->next) { + if (l->next == n) { + return 0; + } + + l = l->next; + } + + return 1; +} + +static inline slist_t *slist_head(slist_t *l) +{ + return l->next; +} + +static inline slist_t *slist_tail(slist_t *l) +{ + while (l->next) { + l = l->next; + } + + return l; +} + +static inline slist_t *slist_next(slist_t *n) +{ + return n->next; +} + +static inline int slist_isempty(slist_t *l) +{ + return l->next == NULL; +} + +/** + * @brief initialize a slist object + */ +#define SLIST_OBJECT_INIT(object) \ + { \ + NULL \ + } + +/** + * @brief initialize a slist object + */ +#define SLIST_DEFINE(slist) \ + slist_t slist = { NULL } + +/** + * @brief get the struct for this single list node + * @param node the entry point + * @param type the type of structure + * @param member the name of list in structure + */ +#define slist_entry(node, type, member) \ + container_of(node, type, member) + +/** + * slist_first_entry - get the first element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define slist_first_entry(ptr, type, member) \ + slist_entry((ptr)->next, type, member) + +/** + * slist_tail_entry - get the tail element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define slist_tail_entry(ptr, type, member) \ + slist_entry(slist_tail(ptr), type, member) + +/** + * slist_first_entry_or_null - get the first element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define slist_first_entry_or_null(ptr, type, member) \ + (slist_isempty(ptr) ? NULL : slist_first_entry(ptr, type, member)) + +/** + * slist_for_each - iterate over a single list + * @pos: the slist_t * to use as a loop cursor. + * @head: the head for your single list. + */ +#define slist_for_each(pos, head) \ + for (pos = (head)->next; pos != NULL; pos = pos->next) + +#define slist_for_each_safe(pos, next, head) \ + for (pos = (head)->next, next = pos->next; pos; \ + pos = next, next = pos->next) + +/** + * slist_for_each_entry - iterate over single list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your single list. + * @member: the name of the list_struct within the struct. + */ +#define slist_for_each_entry(pos, head, member) \ + for (pos = slist_entry((head)->next, typeof(*pos), member); \ + &pos->member != (NULL); \ + pos = slist_entry(pos->member.next, typeof(*pos), member)) + +#define slist_for_each_entry_safe(pos, n, head, member) \ + for (pos = slist_entry((head)->next, typeof(*pos), member), \ + n = slist_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (NULL); \ + pos = n, n = slist_entry(pos->member.next, typeof(*pos), member)) + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/misc/compiler/common.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/misc/compiler/common.h new file mode 100644 index 00000000..542aafa5 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/misc/compiler/common.h @@ -0,0 +1,65 @@ +#ifndef __COMMON_H +#define __COMMON_H + +/** + * @brief Memory access macro + */ +#define BL_RD_WORD(addr) (*((volatile uint32_t *)(uintptr_t)(addr))) +#define BL_WR_WORD(addr, val) ((*(volatile uint32_t *)(uintptr_t)(addr)) = (val)) +#define BL_RD_SHORT(addr) (*((volatile uint16_t *)(uintptr_t)(addr))) +#define BL_WR_SHORT(addr, val) ((*(volatile uint16_t *)(uintptr_t)(addr)) = (val)) +#define BL_RD_BYTE(addr) (*((volatile uint8_t *)(uintptr_t)(addr))) +#define BL_WR_BYTE(addr, val) ((*(volatile uint8_t *)(uintptr_t)(addr)) = (val)) +#define BL_RDWD_FRM_BYTEP(p) ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0])) + +#define BL_WRWD_TO_BYTEP(p, val) \ + { \ + p[0] = val & 0xff; \ + p[1] = (val >> 8) & 0xff; \ + p[2] = (val >> 16) & 0xff; \ + p[3] = (val >> 24) & 0xff; \ + } +/** + * @brief Register access macro + */ +#define BL_RD_REG16(addr, regname) BL_RD_SHORT(addr + regname##_OFFSET) +#define BL_WR_REG16(addr, regname, val) BL_WR_SHORT(addr + regname##_OFFSET, val) +#define BL_RD_REG(addr, regname) BL_RD_WORD(addr + regname##_OFFSET) +#define BL_WR_REG(addr, regname, val) BL_WR_WORD(addr + regname##_OFFSET, val) +#define BL_SET_REG_BIT(val, bitname) ((val) | (1U << bitname##_POS)) +#define BL_CLR_REG_BIT(val, bitname) ((val)&bitname##_UMSK) +#define BL_GET_REG_BITS_VAL(val, bitname) (((val)&bitname##_MSK) >> bitname##_POS) +#define BL_SET_REG_BITS_VAL(val, bitname, bitval) (((val)&bitname##_UMSK) | ((uint32_t)(bitval) << bitname##_POS)) +#define BL_IS_REG_BIT_SET(val, bitname) (((val) & (1U << (bitname##_POS))) != 0) +#define BL_DRV_DUMMY \ + { \ + __ASM volatile("nop"); \ + __ASM volatile("nop"); \ + __ASM volatile("nop"); \ + __ASM volatile("nop"); \ + } + +/* Std driver attribute macro*/ +#ifndef BFLB_USE_CUSTOM_LD_SECTIONS +//#define ATTR_UNI_SYMBOL +#define ATTR_STRINGIFY(x) #x +#define ATTR_TOSTRING(x) ATTR_STRINGIFY(x) +#define ATTR_UNI_SYMBOL __FILE__ ATTR_TOSTRING(__LINE__) +#define ATTR_CLOCK_SECTION __attribute__((section(".sclock_rlt_code." ATTR_UNI_SYMBOL))) +#define ATTR_CLOCK_CONST_SECTION __attribute__((section(".sclock_rlt_const." ATTR_UNI_SYMBOL))) +#define ATTR_TCM_SECTION __attribute__((section(".tcm_code." ATTR_UNI_SYMBOL))) +#define ATTR_TCM_CONST_SECTION __attribute__((section(".tcm_const." ATTR_UNI_SYMBOL))) +#define ATTR_DTCM_SECTION __attribute__((section(".tcm_data"))) +#define ATTR_HSRAM_SECTION __attribute__((section(".hsram_code"))) +#define ATTR_DMA_RAM_SECTION __attribute__((section(".system_ram"))) +#define ATTR_NOCACHE_RAM_SECTION __attribute__((section(".nocache_ram"))) +#define ATTR_NOCACHE_NOINIT_RAM_SECTION __attribute__((section(".nocache_noinit_ram"))) +#define ATTR_HBN_RAM_SECTION __attribute__((section(".hbn_ram_code"))) +#define ATTR_HBN_RAM_CONST_SECTION __attribute__((section(".hbn_ram_data"))) +#define ATTR_EALIGN(x) __attribute__((aligned(x))) +#define ATTR_FALLTHROUGH() __attribute__((fallthrough)) +#define ATTR_USED __attribute__((__used__)) +#else +#include "bl_ld_sections.h" +#endif /* BFLB_USE_CUSTOM_LD_SECTIONS */ +#endif diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/misc/compiler/gcc.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/misc/compiler/gcc.h new file mode 100644 index 00000000..e8e7ce11 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/misc/compiler/gcc.h @@ -0,0 +1,112 @@ +#ifndef __GCC_H +#define __GCC_H + +#ifndef __ORDER_BIG_ENDIAN__ +#define __ORDER_BIG_ENDIAN__ (1) +#endif + +#ifndef __ORDER_LITTLE_ENDIAN__ +#define __ORDER_LITTLE_ENDIAN__ (2) +#endif + +#define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__ + +/* CPP header guards */ +#ifdef __cplusplus +#define EXTERN_C_BEGIN extern "C" { +#define EXTERN_C_END } +#else +#define EXTERN_C_BEGIN +#define EXTERN_C_END +#endif + +#define __MACRO_BEGIN do { +#define __MACRO_END \ + } \ + while (0) + +#if defined(__GNUC__) +#ifndef __ASM +#define __ASM __asm +#endif +#ifndef __INLINE +#define __INLINE inline +#endif +#ifndef __INLINE__ +#define __INLINE__ inline +#endif +#ifndef __ALWAYS_INLINE +#define __ALWAYS_INLINE inline __attribute__((always_inline)) +#endif +#ifndef __ALWAYS_STATIC_INLINE +#define __ALWAYS_STATIC_INLINE __attribute__((always_inline)) static inline +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif +#ifndef __NO_RETURN +#define __NO_RETURN __attribute__((noreturn)) +#endif +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __UNUSED__ +#define __UNUSED__ __attribute__((__unused__)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __WEAK__ +#define __WEAK__ __attribute__((weak)) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED__ +#define __PACKED__ __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION +#define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __IRQ +#define __IRQ __attribute__((interrupt)) +#endif +#ifndef __IRQ_ALIGN64 +#define __IRQ_ALIGN64 __attribute__((interrupt, aligned(64))) +#endif +#ifndef ALIGN4 +#define ALIGN4 __attribute((aligned(4))) +#endif +#ifndef PACK_START +#define PACK_START +#endif +#ifndef PACK_END +#define PACK_END __attribute__((packed)) +#endif +#ifndef likely +#define likely(x) __builtin_expect(!!(x), 1) +#endif +#ifndef unlikely +#define unlikely(x) __builtin_expect(!!(x), 0) +#endif +#ifndef __ALIGNED__ +#define __ALIGNED__(x) __attribute__((aligned(x))) +#endif +#ifndef SECTION +#define SECTION(x) __attribute__((section(x))) +#endif +#ifndef __CONST__ +#define __CONST__ __attribute__((__const__)) +#endif +#ifndef __NAKED__ +#define __NAKED__ __attribute__((naked)) +#endif +#ifndef __deprecated +#define __deprecated __attribute__((deprecated)) +#endif +#endif + +#endif \ No newline at end of file diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/misc/misc.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/misc/misc.c new file mode 100644 index 00000000..3292a683 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/misc/misc.c @@ -0,0 +1,253 @@ +/** + * @file misc.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "misc.h" + +#ifndef BFLB_USE_ROM_DRIVER +/****************************************************************************/ /** + * @brief Char memcpy + * + * @param dst: Destination + * @param src: Source + * @param n: Count of char + * + * @return Destination pointer + * + *******************************************************************************/ +__WEAK__ void *ATTR_TCM_SECTION arch_memcpy(void *dst, const void *src, uint32_t n) +{ + const uint8_t *p = src; + uint8_t *q = dst; + + while (n--) { + *q++ = *p++; + } + + return dst; +} + +/****************************************************************************/ /** + * @brief Word memcpy + * + * @param dst: Destination + * @param src: Source + * @param n: Count of words + * + * @return Destination pointer + * + *******************************************************************************/ +__WEAK__ uint32_t *ATTR_TCM_SECTION arch_memcpy4(uint32_t *dst, const uint32_t *src, uint32_t n) +{ + const uint32_t *p = src; + uint32_t *q = dst; + + while (n--) { + *q++ = *p++; + } + + return dst; +} + +/****************************************************************************/ /** + * @brief Fast memcpy + * + * @param dst: Destination + * @param src: Source + * @param n: Count of bytes + * + * @return Destination pointer + * + *******************************************************************************/ +__WEAK__ void *ATTR_TCM_SECTION arch_memcpy_fast(void *pdst, const void *psrc, uint32_t n) +{ + uint32_t left, done, i = 0; + uint8_t *dst = (uint8_t *)pdst; + uint8_t *src = (uint8_t *)psrc; + + if (((uint32_t)(uintptr_t)dst & 0x3) == 0 && ((uint32_t)(uintptr_t)src & 0x3) == 0) { + arch_memcpy4((uint32_t *)dst, (const uint32_t *)src, n >> 2); + left = n % 4; + done = n - left; + + while (i < left) { + dst[done + i] = src[done + i]; + i++; + } + } else { + arch_memcpy(dst, src, n); + } + + return dst; +} + +/****************************************************************************/ /** + * @brief char memset + * + * @param dst: Destination + * @param val: Value to set + * @param n: Count of char + * + * @return Destination pointer + * + *******************************************************************************/ +__WEAK__ void *ATTR_TCM_SECTION arch_memset(void *s, uint8_t c, uint32_t n) +{ + uint8_t *p = (uint8_t *)s; + + while (n > 0) { + *p++ = (uint8_t)c; + --n; + } + + return s; +} +/****************************************************************************/ /** + * @brief Word memset + * + * @param dst: Destination + * @param val: Value to set + * @param n: Count of words + * + * @return Destination pointer + * + *******************************************************************************/ +__WEAK__ uint32_t *ATTR_TCM_SECTION arch_memset4(uint32_t *dst, const uint32_t val, uint32_t n) +{ + uint32_t *q = dst; + + while (n--) { + *q++ = val; + } + + return dst; +} + +/****************************************************************************/ /** + * @brief string compare + * + * @param s1: string 1 + * @param s2: string 2 + * @param n: Count of chars + * + * @return compare result + * + *******************************************************************************/ +__WEAK__ int ATTR_TCM_SECTION arch_memcmp(const void *s1, const void *s2, uint32_t n) +{ + const unsigned char *c1 = s1, *c2 = s2; + int d = 0; + + while (n--) { + d = (int)*c1++ - (int)*c2++; + + if (d) { + break; + } + } + + return d; +} +#endif + +void memcopy_to_fifo(void *fifo_addr, uint8_t *data, uint32_t length) +{ + uint8_t *p = (uint8_t *)fifo_addr; + uint8_t *q = data; + + while (length--) { + *p = *q++; + } +} + +void fifocopy_to_mem(void *fifo_addr, uint8_t *data, uint32_t length) +{ + uint8_t *p = (uint8_t *)fifo_addr; + uint8_t *q = data; + + while (length--) { + *q++ = *p; + } +} + +/****************************************************************************/ /** + * @brief get u64 first number 1 from right to left + * + * @param val: target value + * @param bit: first 1 in bit + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +int arch_ffsll(uint64_t *val, uint32_t *bit) +{ + if (!*val) { + return ERROR; + } + + *bit = __builtin_ffsll(*val) - 1; + *val &= ~((1ULL) << (*bit)); + return 0; +} + +int arch_ctzll(uint64_t *val, uint32_t *bit) +{ + if (!*val) + return -1; + + *bit = __builtin_ctzll(*val); + *val &= ~((1ULL) << (*bit)); + return 0; +} + +int arch_clzll(uint64_t *val, uint32_t *bit) +{ + if (!*val) + return -1; + + *bit = __builtin_clzll(*val); + *val &= ~((1ULL) << (*bit)); + return 0; +} + +#ifdef DEBUG +/******************************************************************************* +* @brief Reports the name of the source file and the source line number +* where the CHECK_PARAM error has occurred. + +* @param file: Pointer to the source file name +* @param line: assert_param error line source number + +* @return None +*******************************************************************************/ +void check_failed(uint8_t *file, uint32_t line) +{ + /* Infinite loop */ + while (1) + ; +} +#endif /* DEBUG */ + +/*@} end of group DRIVER_Public_Functions */ + +/*@} end of group DRIVER_COMMON */ + +/*@} end of group BL602_Periph_Driver */ diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/misc/misc.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/misc/misc.h new file mode 100644 index 00000000..50ea5cd0 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/misc/misc.h @@ -0,0 +1,131 @@ +/** + * @file misc.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef _MISC_H +#define _MISC_H + +#include +#include +#include +#include +#include +#include +#include "compiler/gcc.h" +#include "compiler/common.h" + +#ifdef BIT +#undef BIT +#define BIT(n) (1UL << (n)) +#else +#define BIT(n) (1UL << (n)) +#endif + +/** + * @brief Null Type definition + */ +#ifndef NULL +#define NULL 0 +#endif + +/** + * @brief Error type definition + */ +typedef enum { + SUCCESS = 0, + ERROR = 1, + TIMEOUT = 2, + INVALID = 3, /* invalid arguments */ + NORESC = 4 /* no resource or resource temperary unavailable */ +} BL_Err_Type; + +/** + * @brief Functional type definition + */ +typedef enum { + DISABLE = 0, + ENABLE = 1, +} BL_Fun_Type; + +/** + * @brief Status type definition + */ +typedef enum { + RESET = 0, + SET = 1, +} BL_Sts_Type; + +/** + * @brief Mask type definition + */ +typedef enum { + UNMASK = 0, + MASK = 1 +} BL_Mask_Type; + +/** + * @brief Logical status Type definition + */ +typedef enum { + LOGIC_LO = 0, + LOGIC_HI = !LOGIC_LO +} LogicalStatus; + +/** + * @brief Active status Type definition + */ +typedef enum { + DEACTIVE = 0, + ACTIVE = !DEACTIVE +} ActiveStatus; + +/** + * @brief Interrupt callback function type + */ +typedef void(intCallback_Type)(void); +typedef void (*pFunc)(void); + +#define ARCH_MemCpy arch_memcpy +#define ARCH_MemSet arch_memset +#define ARCH_MemCmp arch_memcmp +#define ARCH_MemCpy4 arch_memcpy4 +#define ARCH_MemCpy_Fast arch_memcpy_fast +#define ARCH_MemSet4 arch_memset4 + +#ifdef DEBUG +void check_failed(uint8_t *file, uint32_t line); +#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__)) +#else +#define CHECK_PARAM(expr) ((void)0) +#endif /* DEBUG */ + +void *arch_memcpy(void *dst, const void *src, uint32_t n); +void *arch_memset(void *s, uint8_t c, uint32_t n); +int arch_memcmp(const void *s1, const void *s2, uint32_t n); +uint32_t *arch_memcpy4(uint32_t *dst, const uint32_t *src, uint32_t n); +void *arch_memcpy_fast(void *pdst, const void *psrc, uint32_t n); +uint32_t *arch_memset4(uint32_t *dst, const uint32_t val, uint32_t n); +void memcopy_to_fifo(void *fifo_addr, uint8_t *data, uint32_t length); +void fifocopy_to_mem(void *fifo_addr, uint8_t *data, uint32_t length); +int arch_ctzll(uint64_t *val, uint32_t *bit); +int arch_clzll(uint64_t *val, uint32_t *bit); +int arch_ffsll(uint64_t *val, uint32_t *bit); +#endif diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/partition/partition.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/partition/partition.c new file mode 100644 index 00000000..673dcbe8 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/partition/partition.c @@ -0,0 +1,544 @@ +/** + ****************************************************************************** + * @file partition.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "partition.h" +#include "softcrc.h" +#include "bflb_platform.h" + +/** @addtogroup BFLB_Common_Driver + * @{ + */ + +/** @addtogroup PARTITION + * @{ + */ + +/** @defgroup PARTITION_Private_Macros + * @{ + */ + +/*@} end of group PARTITION_Private_Macros */ + +/** @defgroup PARTITION_Private_Types + * @{ + */ + +/*@} end of group PARTITION_Private_Types */ + +/** @defgroup PARTITION_Private_Variables + * @{ + */ +p_pt_table_flash_erase gp_pt_table_flash_erase = NULL; +p_pt_table_flash_write gp_pt_table_flash_write = NULL; +p_pt_table_flash_read gp_pt_table_flash_read = NULL; +pt_table_iap_param_type p_iap_param; + +/*@} end of group PARTITION_Private_Variables */ + +/** @defgroup PARTITION_Global_Variables + * @{ + */ +extern int main(void); + +/*@} end of group PARTITION_Global_Variables */ + +/** @defgroup PARTITION_Private_Fun_Declaration + * @{ + */ + +/*@} end of group PARTITION_Private_Fun_Declaration */ + +/** @defgroup PARTITION_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Judge partition table valid + * + * @param ptStuff: Partition table stuff pointer + * + * @return 0 for invalid and 1 for valid + * +*******************************************************************************/ +static uint8_t pt_table_valid(pt_table_stuff_config *pt_stuff) +{ + pt_table_config *pt_table = &pt_stuff->pt_table; + pt_table_entry_config *pt_entries = pt_stuff->pt_entries; + uint32_t *p_crc32; + uint32_t entriesLen = sizeof(pt_table_entry_config) * pt_table->entryCnt; + + if (pt_table->magicCode == BFLB_PT_MAGIC_CODE) { + if (pt_table->entryCnt > PT_ENTRY_MAX) { + MSG("PT Entry Count Error\r\n"); + return 0; + } + + if (pt_table->crc32 != + BFLB_Soft_CRC32((uint8_t *)pt_table, sizeof(pt_table_config) - 4)) { + MSG("PT CRC Error\r\n"); + return 0; + } + + /* ToDo it is a trap here, when entryCnt > 8, crc32 will overflow, comment by zhangcheng */ + p_crc32 = (uint32_t *)((uintptr_t)pt_entries + entriesLen); + + if (*p_crc32 != BFLB_Soft_CRC32((uint8_t *)pt_entries, entriesLen)) { + MSG("PT Entry CRC Error\r\n"); + return 0; + } + + return 1; + } + + return 0; +} + +/*@} end of group PARTITION_Private_Functions */ + +/** @defgroup PARTITION_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Register partition flash read write erase fucntion + * + * @param erase: Flash erase function + * @param write: Flash write function + * @param read: Flash read function + * + * @return None + * +*******************************************************************************/ +void pt_table_set_flash_operation(p_pt_table_flash_erase erase, p_pt_table_flash_write write, p_pt_table_flash_read read) +{ + gp_pt_table_flash_erase = erase; + gp_pt_table_flash_write = write; + gp_pt_table_flash_read = read; +} + +/****************************************************************************/ /** + * @brief Get active partition table whole stuff + * + * @param ptStuff[2]: Partition table stuff pointer + * + * @return Active partition table ID + * +*******************************************************************************/ +pt_table_id_type pt_table_get_active_partition_need_lock(pt_table_stuff_config ptStuff[2]) +{ + uint32_t pt_valid[2] = { 0, 0 }; + pt_table_id_type activePtID; + + if (ptStuff == NULL) { + return PT_TABLE_ID_INVALID; + } + + activePtID = PT_TABLE_ID_INVALID; + + gp_pt_table_flash_read(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&ptStuff[0], sizeof(pt_table_stuff_config)); + pt_valid[0] = pt_table_valid(&ptStuff[0]); + + gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&ptStuff[1], sizeof(pt_table_stuff_config)); + pt_valid[1] = pt_table_valid(&ptStuff[1]); + + if (pt_valid[0] == 1 && pt_valid[1] == 1) { + if (ptStuff[0].pt_table.age >= ptStuff[1].pt_table.age) { + activePtID = PT_TABLE_ID_0; + } else { + activePtID = PT_TABLE_ID_1; + } + } else if (pt_valid[0] == 1) { + activePtID = PT_TABLE_ID_0; + } else if (pt_valid[1] == 1) { + activePtID = PT_TABLE_ID_1; + } + + return activePtID; +} + +/****************************************************************************/ /** + * @brief Get partition entry according to entry ID + * + * @param ptStuff: Partition table stuff pointer + * @param type: Type of partition entry + * @param ptEntry: Partition entry pointer to store read data + * + * @return PT_ERROR_SUCCESS or PT_ERROR_ENTRY_NOT_FOUND or PT_ERROR_PARAMETER + * +*******************************************************************************/ +pt_table_error_type pt_table_get_active_entries_by_id(pt_table_stuff_config *pt_stuff, + pt_table_entry_type type, + pt_table_entry_config *pt_entry) +{ + uint32_t i = 0; + + if (pt_stuff == NULL || pt_entry == NULL) { + return PT_ERROR_PARAMETER; + } + + for (i = 0; i < pt_stuff->pt_table.entryCnt; i++) { + if (pt_stuff->pt_entries[i].type == type) { + ARCH_MemCpy_Fast(pt_entry, &pt_stuff->pt_entries[i], sizeof(pt_table_entry_config)); + return PT_ERROR_SUCCESS; + } + } + + return PT_ERROR_ENTRY_NOT_FOUND; +} + +/****************************************************************************/ /** + * @brief Get partition entry according to entry name + * + * @param ptStuff: Partition table stuff pointer + * @param name: Name of partition entry + * @param ptEntry: Partition entry pointer to store read data + * + * @return PT_ERROR_SUCCESS or PT_ERROR_ENTRY_NOT_FOUND or PT_ERROR_PARAMETER + * +*******************************************************************************/ +pt_table_error_type pt_table_get_active_entries_by_name(pt_table_stuff_config *pt_stuff, + uint8_t *name, + pt_table_entry_config *pt_entry) +{ + uint32_t i = 0; + uint32_t len = strlen((char *)name); + + if (pt_stuff == NULL || pt_entry == NULL) { + return PT_ERROR_PARAMETER; + } + + for (i = 0; i < pt_stuff->pt_table.entryCnt; i++) { + if (strlen((char *)pt_stuff->pt_entries[i].name) == len && + memcmp((char *)pt_stuff->pt_entries[i].name, (char *)name, len) == 0) { + ARCH_MemCpy_Fast(pt_entry, &pt_stuff->pt_entries[i], sizeof(pt_table_entry_config)); + return PT_ERROR_SUCCESS; + } + } + + return PT_ERROR_ENTRY_NOT_FOUND; +} + +/****************************************************************************/ /** + * @brief Update partition entry + * + * @param targetTableID: Target partition table to update + * @param ptStuff: Partition table stuff pointer + * @param ptEntry: Partition entry pointer to update + * + * @return Partition update result + * +*******************************************************************************/ +pt_table_error_type pt_table_update_entry(pt_table_id_type target_table_id, + pt_table_stuff_config *pt_stuff, + pt_table_entry_config *pt_entry) +{ + uint32_t i = 0; + BL_Err_Type ret; + uint32_t write_addr; + uint32_t entries_len; + pt_table_config *pt_table; + pt_table_entry_config *pt_entries; + uint32_t *crc32; + + if (pt_entry == NULL || pt_stuff == NULL) { + return PT_ERROR_PARAMETER; + } + + pt_table = &pt_stuff->pt_table; + pt_entries = pt_stuff->pt_entries; + + if (target_table_id == PT_TABLE_ID_INVALID) { + return PT_ERROR_TABLE_NOT_VALID; + } + + if (target_table_id == PT_TABLE_ID_0) { + write_addr = BFLB_PT_TABLE0_ADDRESS; + } else { + write_addr = BFLB_PT_TABLE1_ADDRESS; + } + + for (i = 0; i < pt_table->entryCnt; i++) { + if (pt_entries[i].type == pt_entry->type) { + ARCH_MemCpy_Fast(&pt_entries[i], pt_entry, sizeof(pt_table_entry_config)); + break; + } + } + + if (i == pt_table->entryCnt) { + /* Not found this entry ,add new one */ + if (pt_table->entryCnt < PT_ENTRY_MAX) { + ARCH_MemCpy_Fast(&pt_entries[pt_table->entryCnt], pt_entry, sizeof(pt_table_entry_config)); + pt_table->entryCnt++; + } else { + return PT_ERROR_ENTRY_UPDATE_FAIL; + } + } + + /* Prepare write back to flash */ + /* Update age */ + pt_table->age++; + pt_table->crc32 = BFLB_Soft_CRC32((uint8_t *)pt_table, sizeof(pt_table_config) - 4); + + /* Update entries CRC */ + entries_len = pt_table->entryCnt * sizeof(pt_table_entry_config); + crc32 = (uint32_t *)((uintptr_t)pt_entries + entries_len); + *crc32 = BFLB_Soft_CRC32((uint8_t *)&pt_entries[0], entries_len); + + /* Write back to flash */ + /* Erase flash first */ + //ret = gp_pt_table_flash_erase(write_addr, write_addr + sizeof(pt_table_config) + entries_len + 4 - 1); + ret = gp_pt_table_flash_erase(write_addr, sizeof(pt_table_config) + entries_len + 4); + + if (ret != SUCCESS) { + MSG_ERR("Flash Erase error\r\n"); + return PT_ERROR_FALSH_WRITE; + } + + /* Write flash */ + ret = gp_pt_table_flash_write(write_addr, (uint8_t *)pt_stuff, sizeof(pt_table_stuff_config)); + + if (ret != SUCCESS) { + MSG_ERR("Flash Write error\r\n"); + return PT_ERROR_FALSH_WRITE; + } + + return PT_ERROR_SUCCESS; +} + +/****************************************************************************/ /** + * @brief Create partition entry + * + * @param ptID: Partition table ID + * + * @return Partition create result + * +*******************************************************************************/ +pt_table_error_type pt_table_create(pt_table_id_type pt_id) +{ + uint32_t write_addr; + BL_Err_Type ret; + pt_table_config pt_table; + + if (pt_id == PT_TABLE_ID_INVALID) { + return PT_ERROR_TABLE_NOT_VALID; + } + + if (pt_id == PT_TABLE_ID_0) { + write_addr = BFLB_PT_TABLE0_ADDRESS; + } else { + write_addr = BFLB_PT_TABLE1_ADDRESS; + } + + /* Prepare write back to flash */ + pt_table.magicCode = BFLB_PT_MAGIC_CODE; + pt_table.version = 0; + pt_table.entryCnt = 0; + pt_table.age = 0; + pt_table.crc32 = BFLB_Soft_CRC32((uint8_t *)&pt_table, sizeof(pt_table_config) - 4); + /* Write back to flash */ + //ret = gp_pt_table_flash_erase(write_addr, write_addr + sizeof(pt_table_config) - 1); + ret = gp_pt_table_flash_erase(write_addr,sizeof(pt_table_config)); + + if (ret != SUCCESS) { + MSG_ERR("Flash Erase error\r\n"); + return PT_ERROR_FALSH_ERASE; + } + + ret = gp_pt_table_flash_write(write_addr, (uint8_t *)&pt_table, sizeof(pt_table_config)); + + if (ret != SUCCESS) { + MSG_ERR("Flash Write error\r\n"); + return PT_ERROR_FALSH_WRITE; + } + + return PT_ERROR_SUCCESS; +} + +pt_table_error_type pt_table_dump(void) +{ + uint32_t pt_valid[2] = { 0, 0 }; + pt_table_stuff_config pt_stuff[2]; + + gp_pt_table_flash_read(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&pt_stuff[0], sizeof(pt_table_stuff_config)); + pt_valid[0] = pt_table_valid(&pt_stuff[0]); + + gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff[1], sizeof(pt_table_stuff_config)); + pt_valid[1] = pt_table_valid(&pt_stuff[1]); + + if (pt_valid[0]) { + MSG("PT TABLE0 valid\r\n"); + } else { + MSG("PT TABLE0 invalid\r\n"); + } + + if (pt_valid[1]) { + MSG("PT TABLE1 valid\r\n"); + } else { + MSG("PT TABLE1 invalid\r\n"); + } + + for (int i = 0; i < 2; i++) { + if (pt_valid[i] == 1) { + MSG("ptStuff[%d].pt_table.magicCode 0x%08x\r\n", i, pt_stuff[i].pt_table.magicCode); + MSG("ptStuff[%d].pt_table.version 0x%08x\r\n", i, pt_stuff[i].pt_table.version); + MSG("ptStuff[%d].pt_table.entryCnt 0x%08x\r\n", i, pt_stuff[i].pt_table.entryCnt); + MSG("ptStuff[%d].pt_table.age 0x%08x\r\n", i, pt_stuff[i].pt_table.age); + MSG("ptStuff[%d].pt_table.crc32 0x%08x\r\n", i, pt_stuff[i].pt_table.crc32); + + for (int j = 0; j < pt_stuff[i].pt_table.entryCnt; j++) { + MSG("ptStuff[%d].pt_entries[%d].type 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].type); + MSG("ptStuff[%d].pt_entries[%d].device 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].device); + MSG("ptStuff[%d].pt_entries[%d].active_index 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].active_index); + MSG("ptStuff[%d].pt_entries[%d].Address[0] 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].start_address[0]); + MSG("ptStuff[%d].pt_entries[%d].Address[1] 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].start_address[1]); + MSG("ptStuff[%d].pt_entries[%d].maxLen[0] 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].max_len[0]); + MSG("ptStuff[%d].pt_entries[%d].maxLen[1] 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].max_len[1]); + MSG("ptStuff[%d].pt_entries[%d].len 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].len); + MSG("ptStuff[%d].pt_entries[%d].age 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].age); + } + } + } + + return PT_ERROR_SUCCESS; +} + +pt_table_error_type pt_table_get_iap_para(pt_table_iap_param_type *para) +{ + uint32_t pt_valid[2] = { 0, 0 }; + pt_table_stuff_config pt_stuff[2]; + uint8_t active_index; + + gp_pt_table_flash_read(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&pt_stuff[0], sizeof(pt_table_stuff_config)); + pt_valid[0] = pt_table_valid(&pt_stuff[0]); + + gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff[1], sizeof(pt_table_stuff_config)); + pt_valid[1] = pt_table_valid(&pt_stuff[1]); + + if ((pt_valid[0] == 1) && (pt_valid[1] == 1)) { + if (pt_stuff[0].pt_table.age >= pt_stuff[1].pt_table.age) { + active_index = pt_stuff[0].pt_entries[0].active_index; + para->iap_write_addr = para->iap_start_addr = pt_stuff[0].pt_entries[0].start_address[!(active_index & 0x01)]; + para->inactive_index = !(active_index & 0x01); + para->inactive_table_index = 1; + + } else { + active_index = pt_stuff[1].pt_entries[0].active_index; + para->iap_write_addr = para->iap_start_addr = pt_stuff[1].pt_entries[0].start_address[!(active_index & 0x01)]; + para->inactive_index = !(active_index & 0x01); + para->inactive_table_index = 0; + } + + } else if (pt_valid[1] == 1) { + active_index = pt_stuff[1].pt_entries[0].active_index; + para->iap_write_addr = para->iap_start_addr = pt_stuff[1].pt_entries[0].start_address[!(active_index & 0x01)]; + para->inactive_index = !(active_index & 0x01); + para->inactive_table_index = 0; + } else if (pt_valid[0] == 1) { + active_index = pt_stuff[0].pt_entries[0].active_index; + para->iap_write_addr = para->iap_start_addr = pt_stuff[0].pt_entries[0].start_address[!(active_index & 0x01)]; + para->inactive_index = !(active_index & 0x01); + para->inactive_table_index = 1; + } else { + return PT_ERROR_TABLE_NOT_VALID; + } + + MSG("inactive_table_index %d, inactive index %d , IAP start addr %08x \r\n", para->inactive_table_index, para->inactive_index, para->iap_start_addr); + return PT_ERROR_SUCCESS; +} + +pt_table_error_type pt_table_set_iap_para(pt_table_iap_param_type *para) +{ + pt_table_stuff_config pt_stuff, pt_stuff_write; + int32_t ret; + uint32_t *p_crc32; + uint32_t entries_len; + + if (para->inactive_table_index == 1) { + gp_pt_table_flash_read(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&pt_stuff, sizeof(pt_table_stuff_config)); + } else if (para->inactive_table_index == 0) { + gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff, sizeof(pt_table_stuff_config)); + } + + ARCH_MemCpy_Fast((void *)&pt_stuff_write, (void *)&pt_stuff, sizeof(pt_table_stuff_config)); + pt_stuff_write.pt_table.age += 1; + pt_stuff_write.pt_entries[0].active_index = !(pt_stuff_write.pt_entries[0].active_index & 0x01); + pt_stuff_write.pt_table.crc32 = BFLB_Soft_CRC32((uint8_t *)&pt_stuff_write, sizeof(pt_table_config) - 4); + entries_len = sizeof(pt_table_entry_config) * pt_stuff_write.pt_table.entryCnt; + //pt_stuff_write.crc32 = BFLB_Soft_CRC32((uint8_t*)pt_stuff_write.pt_entries,entries_len); + p_crc32 = (uint32_t *)((uintptr_t)pt_stuff_write.pt_entries + entries_len); + *p_crc32 = BFLB_Soft_CRC32((uint8_t *)pt_stuff_write.pt_entries, entries_len); + + if (para->inactive_table_index == 1) { + //ret = gp_pt_table_flash_erase(BFLB_PT_TABLE1_ADDRESS, BFLB_PT_TABLE1_ADDRESS + sizeof(pt_table_stuff_config) - 1); + ret = gp_pt_table_flash_erase(BFLB_PT_TABLE1_ADDRESS, sizeof(pt_table_stuff_config)); + + if (ret != SUCCESS) { + MSG_ERR("Flash Erase error\r\n"); + return PT_ERROR_FALSH_ERASE; + } + + ret = gp_pt_table_flash_write(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff_write, sizeof(pt_table_stuff_config)); + + if (ret != SUCCESS) { + MSG_ERR("Flash Write error\r\n"); + return PT_ERROR_FALSH_WRITE; + } + } else if (para->inactive_table_index == 0) { + //ret = gp_pt_table_flash_erase(BFLB_PT_TABLE0_ADDRESS, BFLB_PT_TABLE0_ADDRESS + sizeof(pt_table_stuff_config) - 1); + ret = gp_pt_table_flash_erase(BFLB_PT_TABLE0_ADDRESS, sizeof(pt_table_stuff_config)); + + if (ret != SUCCESS) { + MSG_ERR("Flash Erase error\r\n"); + return PT_ERROR_FALSH_ERASE; + } + + ret = gp_pt_table_flash_write(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&pt_stuff_write, sizeof(pt_table_stuff_config)); + + if (ret != SUCCESS) { + MSG_ERR("Flash Write error\r\n"); + return PT_ERROR_FALSH_WRITE; + } + } + + MSG("Update pt_table suss\r\n"); + return PT_ERROR_SUCCESS; +} + +/*@} end of group PARTITION_Public_Functions */ + +/*@} end of group PARTITION */ + +/*@} end of group BFLB_Common_Driver */ diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/partition/partition.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/partition/partition.h new file mode 100644 index 00000000..f20332dc --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/partition/partition.h @@ -0,0 +1,209 @@ +/** + ****************************************************************************** + * @file partition.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __PARTITION_H__ +#define __PARTITION_H__ + +#include "misc.h" + +/** @addtogroup BFLB_Common_Driver + * @{ + */ + +/** @addtogroup PARTITION + * @{ + */ + +/** @defgroup PARTITION_Public_Types + * @{ + */ + +/** + * @brief Partition table error type definition + */ +typedef enum { + PT_ERROR_SUCCESS, /*!< Partition table error type:success */ + PT_ERROR_TABLE_NOT_VALID, /*!< Partition table error type:table not found */ + PT_ERROR_ENTRY_NOT_FOUND, /*!< Partition table error type:entry not found */ + PT_ERROR_ENTRY_UPDATE_FAIL, /*!< Partition table error type:entry update fail */ + PT_ERROR_CRC32, /*!< Partition table error type:crc32 error */ + PT_ERROR_PARAMETER, /*!< Partition table error type:input parameter error */ + PT_ERROR_FALSH_READ, /*!< Partition table error type:flash read error */ + PT_ERROR_FALSH_WRITE, /*!< Partition table error type:flash write error */ + PT_ERROR_FALSH_ERASE, /*!< Partition table error type:flash erase error */ +} pt_table_error_type; + +/** + * @brief Partition id type definition + */ +typedef enum { + PT_TABLE_ID_0, /*!< Partition table ID 0 */ + PT_TABLE_ID_1, /*!< Partition table ID 1 */ + PT_TABLE_ID_INVALID, /*!< Partition table ID invalid */ +} pt_table_id_type; + +/** + * @brief Partition id type definition + */ +typedef enum { + PT_ENTRY_FW_CPU0, /*!< Partition entry type:CPU0 firmware */ + PT_ENTRY_FW_CPU1, /*!< Partition entry type:CPU1 firmware */ + PT_ENTRY_MAX = 16, /*!< Partition entry type:Max */ +} pt_table_entry_type; + +/** + * @brief Partition table config definition + */ +typedef struct +{ + uint32_t magicCode; /*!< Partition table magic code */ + uint16_t version; /*!< Partition table verdion */ + uint16_t entryCnt; /*!< Partition table entry count */ + uint32_t age; /*!< Partition table age */ + uint32_t crc32; /*!< Partition table CRC32 value */ +} pt_table_config; + +/** + * @brief Partition table entry config definition + */ +typedef struct +{ + uint8_t type; /*!< Partition entry type */ + uint8_t device; /*!< Partition entry device */ + uint8_t active_index; /*!< Partition entry active index */ + uint8_t name[9]; /*!< Partition entry name */ + uint32_t start_address[2]; /*!< Partition entry start address */ + uint32_t max_len[2]; /*!< Partition entry max length */ + uint32_t len; /*!< Partition entry length */ + uint32_t age; /*!< Partition entry age */ +} pt_table_entry_config; + +/** + * @brief Partition table stuff config definition + */ +typedef struct +{ + pt_table_config pt_table; /*!< Partition table */ + pt_table_entry_config pt_entries[PT_ENTRY_MAX]; /*!< Partition entries */ + uint32_t crc32; /*!< Partition entries crc32 */ +} pt_table_stuff_config; + +/** + * @brief Partition table iap param definition + */ +typedef struct +{ + uint32_t iap_start_addr; + uint32_t iap_write_addr; + uint32_t iap_img_len; + uint8_t inactive_index; + uint8_t inactive_table_index; +} pt_table_iap_param_type; + +/*@} end of group PARTITION_Public_Types */ + +/** @defgroup PARTITION_Public_Constants + * @{ + */ + +/** @defgroup pt_table_error_type + * @{ + */ +#define IS_PTTABLE_ERROR_TYPE(type) (((type) == PT_ERROR_SUCCESS) || \ + ((type) == PT_ERROR_TABLE_NOT_VALID) || \ + ((type) == PT_ERROR_ENTRY_NOT_FOUND) || \ + ((type) == PT_ERROR_ENTRY_UPDATE_FAIL) || \ + ((type) == PT_ERROR_CRC32) || \ + ((type) == PT_ERROR_PARAMETER) || \ + ((type) == PT_ERROR_FALSH_READ) || \ + ((type) == PT_ERROR_FALSH_WRITE) || \ + ((type) == PT_ERROR_FALSH_ERASE)) + +/** @defgroup pt_table_id_type + * @{ + */ +#define IS_PTTABLE_ID_TYPE(type) (((type) == PT_TABLE_ID_0) || \ + ((type) == PT_TABLE_ID_1) || \ + ((type) == PT_TABLE_ID_INVALID)) + +/** @defgroup pt_table_entry_type + * @{ + */ +#define IS_PTTABLE_ENTRY_TYPE(type) (((type) == PT_ENTRY_FW_CPU0) || \ + ((type) == PT_ENTRY_FW_CPU1) || \ + ((type) == PT_ENTRY_MAX)) + +/*@} end of group PARTITION_Public_Constants */ + +/** @defgroup PARTITION_Public_Macros + * @{ + */ +#define BFLB_PT_TABLE0_ADDRESS 0xE000 +#define BFLB_PT_TABLE1_ADDRESS 0xF000 +#define BFLB_PT_MAGIC_CODE 0x54504642 +typedef BL_Err_Type (*p_pt_table_flash_erase)(uint32_t startaddr, uint32_t endaddr); +typedef BL_Err_Type (*p_pt_table_flash_write)(uint32_t addr, uint8_t *data, uint32_t len); +typedef BL_Err_Type (*p_pt_table_flash_read)(uint32_t addr, uint8_t *data, uint32_t len); + +/*@} end of group PARTITION_Public_Macros */ + +/** @defgroup PARTITION_Public_Functions + * @{ + */ +void pt_table_set_flash_operation(p_pt_table_flash_erase erase, p_pt_table_flash_write write, p_pt_table_flash_read read); +pt_table_id_type pt_table_get_active_partition_need_lock(pt_table_stuff_config ptStuff[2]); +pt_table_error_type pt_table_get_active_entries_by_id(pt_table_stuff_config *pt_stuff, + pt_table_entry_type type, + pt_table_entry_config *pt_entry); +pt_table_error_type pt_table_get_active_entries_by_name(pt_table_stuff_config *pt_stuff, + uint8_t *name, + pt_table_entry_config *pt_entry); +pt_table_error_type pt_table_update_entry(pt_table_id_type target_table_id, + pt_table_stuff_config *pt_stuff, + pt_table_entry_config *pt_entry); +pt_table_error_type pt_table_create(pt_table_id_type pt_id); +pt_table_error_type pt_table_dump(void); +pt_table_error_type pt_table_get_iap_para(pt_table_iap_param_type *para); +pt_table_error_type pt_table_set_iap_para(pt_table_iap_param_type *para); + +/*@} end of group PARTITION_Public_Functions */ + +/*@} end of group PARTITION */ + +/*@} end of group BFLB_Common_Driver */ + +extern pt_table_iap_param_type p_iap_param; + +#endif /* __PARTITION_H__ */ diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/pid/pid.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/pid/pid.c new file mode 100644 index 00000000..dc060200 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/pid/pid.c @@ -0,0 +1,68 @@ +/** + * @file pid.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "pid.h" + +void pid_init(pid_alg_t *pid) +{ + pid->set_val = 0.0f; + pid->out_val = 0.0f; + + pid->last_error = 0.0f; + pid->prev_error = 0.0f; + + pid->kp = 3.0f; + pid->ki = 0.0f; + pid->kd = 0.0f; + + pid->i_error = 0.0f; + pid->sum_error = 0.0f; + + pid->max_val = 32; + pid->min_val = -32; +} + +// standard pid +float standard_pid_cal(pid_alg_t *pid, float next_val) +{ + pid->set_val = next_val; + pid->i_error = pid->set_val - pid->out_val; + pid->sum_error += pid->i_error; + pid->out_val = pid->kp * pid->i_error + pid->ki * pid->sum_error + pid->kd * (pid->i_error - pid->last_error); + pid->last_error = pid->i_error; + + return pid->out_val; +} + +// increment pid +float increment_pid_cal(pid_alg_t *pid, float next_val) +{ + pid->set_val = next_val; + pid->i_error = pid->set_val - pid->out_val; + float increment = pid->kp * (pid->i_error - pid->prev_error) + pid->ki * pid->i_error + pid->kd * (pid->i_error - 2 * pid->prev_error + pid->last_error); + pid->out_val += increment; + pid->last_error = pid->prev_error; + pid->prev_error = pid->i_error; + + return pid->out_val; +} diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/pid/pid.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/pid/pid.h new file mode 100644 index 00000000..eb3b77f0 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/pid/pid.h @@ -0,0 +1,50 @@ +/** + * @file pid.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef __PID_H__ +#define __PID_H__ + +#include "stdint.h" + +typedef struct pid_alg { + float set_val; + float out_val; + + float kp; + float ki; + float kd; + + float i_error; + float last_error; + float prev_error; + float sum_error; + + int max_val; + int min_val; +} pid_alg_t; + +void pid_init(pid_alg_t *pid); +float standard_pid_cal(pid_alg_t *pid, float next_val); +float increment_pid_cal(pid_alg_t *pid, float next_val); + +#endif diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/ring_buffer/ring_buffer.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/ring_buffer/ring_buffer.c new file mode 100644 index 00000000..ec91c715 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/ring_buffer/ring_buffer.c @@ -0,0 +1,679 @@ +/** + * @file ring_buffer.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "ring_buffer.h" + +/** @addtogroup BL_Common_Component + * @{ + */ + +/** @addtogroup RING_BUFFER + * @{ + */ + +/** @defgroup RING_BUFFER_Private_Macros + * @{ + */ + +/*@} end of group RING_BUFFER_Private_Macros */ + +/** @defgroup RING_BUFFER_Private_Types + * @{ + */ + +/*@} end of group RING_BUFFER_Private_Types */ + +/** @defgroup RING_BUFFER_Private_Fun_Declaration + * @{ + */ + +/*@} end of group RING_BUFFER_Private_Fun_Declaration */ + +/** @defgroup RING_BUFFER_Private_Variables + * @{ + */ + +/*@} end of group RING_BUFFER_Private_Variables */ + +/** @defgroup RING_BUFFER_Global_Variables + * @{ + */ + +/*@} end of group RING_BUFFER_Global_Variables */ + +/** @defgroup RING_BUFFER_Private_Functions + * @{ + */ + +/*@} end of group RING_BUFFER_Private_Functions */ + +/** @defgroup RING_BUFFER_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Ring buffer init function + * + * @param rbType: Ring buffer type structure pointer + * @param buffer: Pointer of ring buffer + * @param size: Size of ring buffer + * @param lockCb: Ring buffer lock callback function pointer + * @param unlockCb: Ring buffer unlock callback function pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type Ring_Buffer_Init(Ring_Buffer_Type *rbType, uint8_t *buffer, uint32_t size, ringBuffer_Lock_Callback *lockCb, ringBuffer_Lock_Callback *unlockCb) +{ + /* Init ring buffer pointer */ + rbType->pointer = buffer; + + /* Init read/write mirror and index */ + rbType->readMirror = 0; + rbType->readIndex = 0; + rbType->writeMirror = 0; + rbType->writeIndex = 0; + + /* Set ring buffer size */ + rbType->size = size; + + /* Set lock and unlock callback function */ + rbType->lock = lockCb; + rbType->unlock = unlockCb; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Ring buffer reset function + * + * @param rbType: Ring buffer type structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type Ring_Buffer_Reset(Ring_Buffer_Type *rbType) +{ + if (rbType->lock != NULL) { + rbType->lock(); + } + + /* Clear read/write mirror and index */ + rbType->readMirror = 0; + rbType->readIndex = 0; + rbType->writeMirror = 0; + rbType->writeIndex = 0; + + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Use callback function to write ring buffer function + * + * @param rbType: Ring buffer type structure pointer + * @param length: Length of data want to write + * @param writeCb: Callback function pointer + * @param parameter: Parameter that callback function may use + * + * @return Length of data actually write + * +*******************************************************************************/ +uint32_t Ring_Buffer_Write_Callback(Ring_Buffer_Type *rbType, uint32_t length, ringBuffer_Write_Callback *writeCb, void *parameter) +{ + uint32_t sizeRemained = Ring_Buffer_Get_Empty_Length(rbType); + + if (writeCb == NULL) { + return 0; + } + + if (rbType->lock != NULL) { + rbType->lock(); + } + + /* Ring buffer has no space for new data */ + if (sizeRemained == 0) { + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return 0; + } + + /* Drop part of data when length out of space remained */ + if (length > sizeRemained) { + length = sizeRemained; + } + + /* Get size of space remained in current mirror */ + sizeRemained = rbType->size - rbType->writeIndex; + + if (sizeRemained > length) { + /* Space remained is enough for data in current mirror */ + writeCb(parameter, &rbType->pointer[rbType->writeIndex], length); + rbType->writeIndex += length; + } else { + /* Data is divided to two parts with different mirror */ + writeCb(parameter, &rbType->pointer[rbType->writeIndex], sizeRemained); + writeCb(parameter, &rbType->pointer[0], length - sizeRemained); + rbType->writeIndex = length - sizeRemained; + rbType->writeMirror = ~rbType->writeMirror; + } + + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return length; +} + +/****************************************************************************/ /** + * @brief Copy data from data buffer to ring buffer function + * + * @param parameter: Pointer to source pointer + * @param dest: Ring buffer to write + * @param length: Length of data to write + * + * @return None + * +*******************************************************************************/ +static void Ring_Buffer_Write_Copy(void *parameter, uint8_t *dest, uint32_t length) +{ + uint8_t **src = (uint8_t **)parameter; + + ARCH_MemCpy_Fast(dest, *src, length); + *src += length; +} + +/****************************************************************************/ /** + * @brief Write ring buffer function + * + * @param rbType: Ring buffer type structure pointer + * @param data: Data to write + * @param length: Length of data + * + * @return Length of data writted actually + * +*******************************************************************************/ +uint32_t Ring_Buffer_Write(Ring_Buffer_Type *rbType, const uint8_t *data, uint32_t length) +{ + return Ring_Buffer_Write_Callback(rbType, length, Ring_Buffer_Write_Copy, &data); +} + +/****************************************************************************/ /** + * @brief Write 1 byte to ring buffer function + * + * @param rbType: Ring buffer type structure pointer + * @param data: Data to write + * + * @return Length of data writted actually + * +*******************************************************************************/ +uint32_t Ring_Buffer_Write_Byte(Ring_Buffer_Type *rbType, const uint8_t data) +{ + if (rbType->lock != NULL) { + rbType->lock(); + } + + /* Ring buffer has no space for new data */ + if (!Ring_Buffer_Get_Empty_Length(rbType)) { + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return 0; + } + + rbType->pointer[rbType->writeIndex] = data; + + /* Judge to change index and mirror */ + if (rbType->writeIndex != (rbType->size - 1)) { + rbType->writeIndex++; + } else { + rbType->writeIndex = 0; + rbType->writeMirror = ~rbType->writeMirror; + } + + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return 1; +} + +/****************************************************************************/ /** + * @brief Write ring buffer function, old data will be covered by new data when ring buffer is + * full + * + * @param rbType: Ring buffer type structure pointer + * @param data: Data to write + * @param length: Length of data + * + * @return Length of data writted actually + * +*******************************************************************************/ +uint32_t Ring_Buffer_Write_Force(Ring_Buffer_Type *rbType, const uint8_t *data, uint32_t length) +{ + uint32_t sizeRemained = Ring_Buffer_Get_Empty_Length(rbType); + uint32_t indexRemained = rbType->size - rbType->writeIndex; + + if (rbType->lock != NULL) { + rbType->lock(); + } + + /* Drop extra data when data length is large than size of ring buffer */ + if (length > rbType->size) { + data = &data[length - rbType->size]; + length = rbType->size; + } + + if (indexRemained > length) { + /* Space remained is enough for data in current mirror */ + ARCH_MemCpy_Fast(&rbType->pointer[rbType->writeIndex], data, length); + rbType->writeIndex += length; + + /* Update read index */ + if (length > sizeRemained) { + rbType->readIndex = rbType->writeIndex; + } + } else { + /* Data is divided to two parts with different mirror */ + ARCH_MemCpy_Fast(&rbType->pointer[rbType->writeIndex], data, indexRemained); + ARCH_MemCpy_Fast(&rbType->pointer[0], &data[indexRemained], length - indexRemained); + rbType->writeIndex = length - indexRemained; + rbType->writeMirror = ~rbType->writeMirror; + + /* Update read index and mirror */ + if (length > sizeRemained) { + rbType->readIndex = rbType->writeIndex; + rbType->readMirror = ~rbType->readMirror; + } + } + + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return length; +} + +/****************************************************************************/ /** + * @brief Write 1 byte to ring buffer function, old data will be covered by new data when ring + * buffer is full + * + * @param rbType: Ring buffer type structure pointer + * @param data: Data to write + * + * @return Length of data writted actually + * +*******************************************************************************/ +uint32_t Ring_Buffer_Write_Byte_Force(Ring_Buffer_Type *rbType, const uint8_t data) +{ + Ring_Buffer_Status_Type status = Ring_Buffer_Get_Status(rbType); + + if (rbType->lock != NULL) { + rbType->lock(); + } + + rbType->pointer[rbType->writeIndex] = data; + + /* Judge to change index and mirror */ + if (rbType->writeIndex == rbType->size - 1) { + rbType->writeIndex = 0; + rbType->writeMirror = ~rbType->writeMirror; + + /* Update read index and mirror */ + if (status == RING_BUFFER_FULL) { + rbType->readIndex = rbType->writeIndex; + rbType->readMirror = ~rbType->readMirror; + } + } else { + rbType->writeIndex++; + + /* Update read index */ + if (status == RING_BUFFER_FULL) { + rbType->readIndex = rbType->writeIndex; + } + } + + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return 1; +} + +/****************************************************************************/ /** + * @brief Use callback function to read ring buffer function + * + * @param rbType: Ring buffer type structure pointer + * @param length: Length of data want to read + * @param readCb: Callback function pointer + * @param parameter: Parameter that callback function may use + * + * @return Length of data actually read + * +*******************************************************************************/ +uint32_t Ring_Buffer_Read_Callback(Ring_Buffer_Type *rbType, uint32_t length, ringBuffer_Read_Callback *readCb, void *parameter) +{ + uint32_t size = Ring_Buffer_Get_Length(rbType); + + if (readCb == NULL) { + return 0; + } + + if (rbType->lock != NULL) { + rbType->lock(); + } + + /* Ring buffer has no data */ + if (!size) { + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return 0; + } + + /* Ring buffer do not have enough data */ + if (size < length) { + length = size; + } + + /* Get size of space remained in current mirror */ + size = rbType->size - rbType->readIndex; + + if (size > length) { + /* Read all data needed */ + readCb(parameter, &rbType->pointer[rbType->readIndex], length); + rbType->readIndex += length; + } else { + /* Read two part of data in different mirror */ + readCb(parameter, &rbType->pointer[rbType->readIndex], size); + readCb(parameter, &rbType->pointer[0], length - size); + rbType->readIndex = length - size; + rbType->readMirror = ~rbType->readMirror; + } + + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return length; +} + +/****************************************************************************/ /** + * @brief Copy data from ring buffer to data buffer function + * + * @param parameter: Pointer to destination pointer + * @param data: Data buffer to copy + * @param length: Length of data to copy + * + * @return None + * +*******************************************************************************/ +static void Ring_Buffer_Read_Copy(void *parameter, uint8_t *data, uint32_t length) +{ + uint8_t **dest = (uint8_t **)parameter; + + ARCH_MemCpy_Fast(*dest, data, length); + *dest += length; +} + +/****************************************************************************/ /** + * @brief Read ring buffer function + * + * @param rbType: Ring buffer type structure pointer + * @param data: Buffer for data read + * @param length: Length of data to read + * + * @return Length of data read actually + * +*******************************************************************************/ +uint32_t Ring_Buffer_Read(Ring_Buffer_Type *rbType, uint8_t *data, uint32_t length) +{ + return Ring_Buffer_Read_Callback(rbType, length, Ring_Buffer_Read_Copy, &data); +} + +/****************************************************************************/ /** + * @brief Read 1 byte from ring buffer function + * + * @param rbType: Ring buffer type structure pointer + * @param data: Data read + * + * @return Length of data actually read + * +*******************************************************************************/ +uint32_t Ring_Buffer_Read_Byte(Ring_Buffer_Type *rbType, uint8_t *data) +{ + if (rbType->lock != NULL) { + rbType->lock(); + } + + /* Ring buffer has no data */ + if (!Ring_Buffer_Get_Length(rbType)) { + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return 0; + } + + /* Read data */ + *data = rbType->pointer[rbType->readIndex]; + + /* Update read index and mirror */ + if (rbType->readIndex == rbType->size - 1) { + rbType->readIndex = 0; + rbType->readMirror = ~rbType->readMirror; + } else { + rbType->readIndex++; + } + + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return 1; +} + +/****************************************************************************/ /** + * @brief Read ring buffer function, do not remove from buffer actually + * + * @param rbType: Ring buffer type structure pointer + * @param data: Buffer for data read + * @param length: Length of data to read + * + * @return Length of data read actually + * +*******************************************************************************/ +uint32_t Ring_Buffer_Peek(Ring_Buffer_Type *rbType, uint8_t *data, uint32_t length) +{ + uint32_t size = Ring_Buffer_Get_Length(rbType); + + if (rbType->lock != NULL) { + rbType->lock(); + } + + /* Ring buffer has no data */ + if (!size) { + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return 0; + } + + /* Ring buffer do not have enough data */ + if (size < length) { + length = size; + } + + /* Get size of space remained in current mirror */ + size = rbType->size - rbType->readIndex; + + if (size > length) { + /* Read all data needed */ + ARCH_MemCpy_Fast(data, &rbType->pointer[rbType->readIndex], length); + } else { + /* Read two part of data in different mirror */ + ARCH_MemCpy_Fast(data, &rbType->pointer[rbType->readIndex], size); + ARCH_MemCpy_Fast(&data[size], &rbType->pointer[0], length - size); + } + + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return length; +} + +/****************************************************************************/ /** + * @brief Read 1 byte from ring buffer function, do not remove from buffer actually + * + * @param rbType: Ring buffer type structure pointer + * @param data: Data read + * + * @return Length of data actually read + * +*******************************************************************************/ +uint32_t Ring_Buffer_Peek_Byte(Ring_Buffer_Type *rbType, uint8_t *data) +{ + if (rbType->lock != NULL) { + rbType->lock(); + } + + /* Ring buffer has no data */ + if (!Ring_Buffer_Get_Length(rbType)) { + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return 0; + } + + /* Read data */ + *data = rbType->pointer[rbType->readIndex]; + + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return 1; +} + +/****************************************************************************/ /** + * @brief Get length of data in ring buffer function + * + * @param rbType: Ring buffer type structure pointer + * + * @return Length of data + * +*******************************************************************************/ +uint32_t Ring_Buffer_Get_Length(Ring_Buffer_Type *rbType) +{ + uint32_t readMirror = 0; + uint32_t writeMirror = 0; + uint32_t readIndex = 0; + uint32_t writeIndex = 0; + uint32_t size = 0; + + if (rbType->lock != NULL) { + rbType->lock(); + } + + readMirror = rbType->readMirror; + writeMirror = rbType->writeMirror; + readIndex = rbType->readIndex; + writeIndex = rbType->writeIndex; + size = rbType->size; + + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + if (readMirror == writeMirror) { + return writeIndex - readIndex; + } else { + return size - (readIndex - writeIndex); + } +} + +/****************************************************************************/ /** + * @brief Get space remained in ring buffer function + * + * @param rbType: Ring buffer type structure pointer + * + * @return Length of space remained + * +*******************************************************************************/ +uint32_t Ring_Buffer_Get_Empty_Length(Ring_Buffer_Type *rbType) +{ + return (rbType->size - Ring_Buffer_Get_Length(rbType)); +} + +/****************************************************************************/ /** + * @brief Get ring buffer status function + * + * @param rbType: Ring buffer type structure pointer + * + * @return Status of ring buffer + * +*******************************************************************************/ +Ring_Buffer_Status_Type Ring_Buffer_Get_Status(Ring_Buffer_Type *rbType) +{ + if (rbType->lock != NULL) { + rbType->lock(); + } + + /* Judge empty or full */ + if (rbType->readIndex == rbType->writeIndex) { + if (rbType->readMirror == rbType->writeMirror) { + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return RING_BUFFER_EMPTY; + } else { + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return RING_BUFFER_FULL; + } + } + + if (rbType->unlock != NULL) { + rbType->unlock(); + } + + return RING_BUFFER_PARTIAL; +} + +/*@} end of group RING_BUFFER_Public_Functions */ + +/*@} end of group RING_BUFFER */ + +/*@} end of group BL_Common_Component */ diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/ring_buffer/ring_buffer.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/ring_buffer/ring_buffer.h new file mode 100644 index 00000000..dbc66819 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/ring_buffer/ring_buffer.h @@ -0,0 +1,116 @@ +/** + * @file ring_buffer.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __RING_BUFFER_H__ +#define __RING_BUFFER_H__ + +#include "misc.h" + +/** @addtogroup BL_Common_Component + * @{ + */ + +/** @addtogroup RING_BUFFER + * @{ + */ + +/** @defgroup RING_BUFFER_Public_Types + * @{ + */ + +/** + * @brief Ring buffer status type definition + */ +typedef enum { + RING_BUFFER_EMPTY, /*!< Ring buffer is empty */ + RING_BUFFER_PARTIAL, /*!< Ring buffer has partial data */ + RING_BUFFER_FULL, /*!< Ring buffer is full */ +} Ring_Buffer_Status_Type; + +/** + * @brief Ring buffer structure definition + */ +typedef struct +{ + uint8_t *pointer; /*!< Pointer of ring buffer */ + uint8_t readMirror; /*!< Read mirror,used to judge empty or full */ + uint32_t readIndex; /*!< Index of read address */ + uint8_t writeMirror; /*!< Write mirror,used to judge empty or full */ + uint32_t writeIndex; /*!< Index of write address */ + uint32_t size; /*!< Size of ring buffer */ + void (*lock)(void); /*!< Lock ring buffer */ + void (*unlock)(void); /*!< Unlock ring buffer */ +} Ring_Buffer_Type; + +/*@} end of group RING_BUFFER_Public_Types */ + +/** @defgroup RING_BUFFER_Public_Constants + * @{ + */ + +/** @defgroup RING_BUFFER_STATUS_TYPE + * @{ + */ +#define IS_RING_BUFFER_STATUS_TYPE(type) (((type) == RING_BUFFER_EMPTY) || \ + ((type) == RING_BUFFER_PARTIAL) || \ + ((type) == RING_BUFFER_FULL)) + +/*@} end of group RING_BUFFER_Public_Constants */ + +/** @defgroup RING_BUFFER_Public_Macros + * @{ + */ +typedef void(ringBuffer_Lock_Callback)(void); +typedef void(ringBuffer_Read_Callback)(void *, uint8_t *, uint32_t); +typedef void(ringBuffer_Write_Callback)(void *, uint8_t *, uint32_t); + +/*@} end of group RING_BUFFER_Public_Macros */ + +/** @defgroup RING_BUFFER_Public_Functions + * @{ + */ +BL_Err_Type Ring_Buffer_Init(Ring_Buffer_Type *rbType, uint8_t *buffer, uint32_t size, ringBuffer_Lock_Callback *lockCb, + ringBuffer_Lock_Callback *unlockCb); +BL_Err_Type Ring_Buffer_Reset(Ring_Buffer_Type *rbType); +uint32_t Ring_Buffer_Write_Callback(Ring_Buffer_Type *rbType, uint32_t length, ringBuffer_Write_Callback *writeCb, + void *parameter); +uint32_t Ring_Buffer_Write(Ring_Buffer_Type *rbType, const uint8_t *data, uint32_t length); +uint32_t Ring_Buffer_Write_Byte(Ring_Buffer_Type *rbType, const uint8_t data); +uint32_t Ring_Buffer_Write_Force(Ring_Buffer_Type *rbType, const uint8_t *data, uint32_t length); +uint32_t Ring_Buffer_Write_Byte_Force(Ring_Buffer_Type *rbType, const uint8_t data); +uint32_t Ring_Buffer_Read_Callback(Ring_Buffer_Type *rbType, uint32_t length, ringBuffer_Read_Callback *readCb, + void *parameter); +uint32_t Ring_Buffer_Read(Ring_Buffer_Type *rbType, uint8_t *data, uint32_t length); +uint32_t Ring_Buffer_Read_Byte(Ring_Buffer_Type *rbType, uint8_t *data); +uint32_t Ring_Buffer_Peek(Ring_Buffer_Type *rbType, uint8_t *data, uint32_t length); +uint32_t Ring_Buffer_Peek_Byte(Ring_Buffer_Type *rbType, uint8_t *data); +uint32_t Ring_Buffer_Get_Length(Ring_Buffer_Type *rbType); +uint32_t Ring_Buffer_Get_Empty_Length(Ring_Buffer_Type *rbType); +Ring_Buffer_Status_Type Ring_Buffer_Get_Status(Ring_Buffer_Type *rbType); + +/*@} end of group RING_BUFFER_Public_Functions */ + +/*@} end of group RING_BUFFER */ + +/*@} end of group BL_Common_Component */ + +#endif /* __RING_BUFFER_H__ */ diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/soft_crc/softcrc.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/soft_crc/softcrc.c new file mode 100644 index 00000000..4c4cbe55 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/soft_crc/softcrc.c @@ -0,0 +1,194 @@ +/** + * @file softcrc.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "softcrc.h" +#include "misc.h" +// ---------------- POPULAR POLYNOMIALS ---------------- +// CCITT: x^16 + x^12 + x^5 + x^0 (0x1021,init 0x0000) +// CRC-16: x^16 + x^15 + x^2 + x^0 (0x8005,init 0xFFFF) +// we use 0x8005 here and + +const uint8_t chCRCHTalbe[] = { + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, + 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, + 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40 +}; + +const uint8_t chCRCLTalbe[] = { + 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7, + 0x05, 0xC5, 0xC4, 0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E, + 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9, + 0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC, + 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, 0x12, 0x13, 0xD3, + 0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32, + 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D, + 0xFF, 0x3F, 0x3E, 0xFE, 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38, + 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA, 0xEE, 0x2E, 0x2F, 0xEF, + 0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26, + 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1, + 0x63, 0xA3, 0xA2, 0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4, + 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB, + 0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA, + 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, 0x74, 0x75, 0xB5, + 0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0, + 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97, + 0x55, 0x95, 0x94, 0x54, 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E, + 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98, 0x88, 0x48, 0x49, 0x89, + 0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C, + 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83, + 0x41, 0x81, 0x80, 0x40 +}; + +uint16_t BFLB_Soft_CRC16(void *dataIn, uint32_t len) +{ + uint8_t chCRCHi = 0xFF; + uint8_t chCRCLo = 0xFF; + uint16_t wIndex; + uint8_t *data = (uint8_t *)dataIn; + + while (len--) { + wIndex = chCRCLo ^ *data++; + chCRCLo = chCRCHi ^ chCRCHTalbe[wIndex]; + chCRCHi = chCRCLTalbe[wIndex]; + } + + return ((chCRCHi << 8) | chCRCLo); +} + +/* +x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 +*/ +const uint32_t crc32Tab[256] = { + 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, + 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, + 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2, + 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, + 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, + 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, + 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c, + 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, + 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, + 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, + 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106, + 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, + 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, + 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, + 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950, + 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, + 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, + 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, + 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, + 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, + 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, + 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84, + 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, + 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, + 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, + 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e, + 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, + 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, + 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, + 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28, + 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, + 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f, + 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, + 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242, + 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, + 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, + 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, + 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, + 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, + 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, + 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d +}; + +uint32_t BFLB_Soft_CRC32_Table(void *dataIn, uint32_t len) +{ + uint32_t crc = 0; + uint8_t *data = (uint8_t *)dataIn; + + crc = crc ^ 0xffffffff; + + while (len--) { + crc = crc32Tab[(crc ^ *data++) & 0xFF] ^ (crc >> 8); + } + + return crc ^ 0xffffffff; +} + +/****************************************************************************** +* Name: CRC-32 x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1 +* Poly: 0x4C11DB7 +* Init: 0xFFFFFFF +* Refin: True +* Refout: True +* Xorout: 0xFFFFFFF +* Alias: CRC_32/ADCCP +* Use: WinRAR,ect. +*****************************************************************************/ +uint32_t ATTR_TCM_SECTION BFLB_Soft_CRC32_Ex(uint32_t initial, void *dataIn, uint32_t len) +{ + uint8_t i; + uint32_t crc = ~initial; // Initial value + uint8_t *data=(uint8_t *)dataIn; + + while(len--){ + crc ^= *data++; // crc ^= *data; data++; + for (i = 0; i < 8; ++i){ + if (crc & 1){ + crc = (crc >> 1) ^ 0xEDB88320;// 0xEDB88320= reverse 0x04C11DB7 + }else{ + crc = (crc >> 1); + } + } + } + return ~crc; +} + +#ifndef BFLB_USE_ROM_DRIVER +__WEAK__ +uint32_t ATTR_TCM_SECTION BFLB_Soft_CRC32(void *dataIn, uint32_t len) +{ + return BFLB_Soft_CRC32_Ex(0,dataIn,len); +} +#endif diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/soft_crc/softcrc.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/soft_crc/softcrc.h new file mode 100644 index 00000000..c56ab26d --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/soft_crc/softcrc.h @@ -0,0 +1,32 @@ +/** + * @file softcrc.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __SOFTCRC_H__ +#define __SOFTCRC_H__ + +#include "stdint.h" + +uint16_t BFLB_Soft_CRC16(void *dataIn, uint32_t len); +uint32_t BFLB_Soft_CRC32_Ex(uint32_t initial, void *dataIn, uint32_t len); +uint32_t BFLB_Soft_CRC32(void *dataIn, uint32_t len); + +#endif diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/timestamp/timestamp.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/timestamp/timestamp.c new file mode 100644 index 00000000..3454ff47 --- /dev/null +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/timestamp/timestamp.c @@ -0,0 +1,136 @@ +/** + * @file timestamp.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "timestamp.h" + +#define FOUR_YEAR_DAY ((365 << 2) + 1) //The total number of days in a 4-year cycle +#define TIMEZONE (8) //Beijing time Zone adjustment + +#define SEC_NUM_PER_DAY (24 * 60 * 60) +#define SEC_NUM_PER_HOUR (60 * 60) +#define SEC_NUM_PER_MINUTE (60) + +static uint8_t month_day[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; //平年 +static uint8_t Leap_month_day[12] = { 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; //闰年 + +/** +* @bref judge if it is a leap year +* @para year to be judge +* @return 1：leap year 0： nonleap year +*/ +bool check_leap_year(uint16_t year) +{ + if (year % 4) { + return false; + } else { + if ((year % 100 == 0) && (year % 400 != 0)) { + return false; + } else { + return true; + } + } +} + +void cal_weekday(rtc_time *beijing_time) +{ + uint32_t y,m,d,w; + + y=beijing_time->year; + m=beijing_time->month; + d=beijing_time->day; + + if((m==1)||(m==2)) + { + m+=12; + y--; + } + /* + 把一月和二月看成是上一年的十三月和十四月，例：如果是2004-1-10则换算成：2003-13-10来代入公式计算。 + 以公元元年为参考，公元元年1月1日为星期一
程序如下：
+	利用基姆拉尔森计算日期公式  w=(d+2*m+3*(m+1)/5+y+y/4-y/100+y/400)
+	*/
+	w=(d+2*m+3*(m+1)/5+y+y/4-y/100+y/400+1)%7;
+
+	beijing_time->week=(uint8_t)w;
+}
+
+void unixtime2bejingtime(uint32_t unixtime, rtc_time *beijing_time)
+{
+    uint32_t totle_day_num;
+    uint32_t current_sec_num;
+
+    uint16_t remain_day;
+
+    uint16_t temp_year;
+
+    uint8_t *p = NULL;
+
+    totle_day_num = unixtime / SEC_NUM_PER_DAY;   //The total number of days
+    current_sec_num = unixtime % SEC_NUM_PER_DAY; //The number of seconds this day
+
+    /* use the number of seconds this day, To calculate hour\minute\second */
+    beijing_time->hour = current_sec_num / SEC_NUM_PER_HOUR;
+    beijing_time->minute = (current_sec_num % SEC_NUM_PER_HOUR) / SEC_NUM_PER_MINUTE;
+    beijing_time->second = (current_sec_num % SEC_NUM_PER_HOUR) % SEC_NUM_PER_MINUTE;
+
+    /* Adjust the time zone and check whether the date is +1 */
+    beijing_time->hour += 8;
+    if (beijing_time->hour > 23) {
+        beijing_time->hour -= 24;
+        totle_day_num++;
+    }
+
+
+    /* calculate year */
+    beijing_time->year = 1970 + (totle_day_num / FOUR_YEAR_DAY) * 4; // 4-year as a cycle
+    remain_day = totle_day_num % FOUR_YEAR_DAY;                      //remaining day nym( < 4 year )
+
+    /* calculate year & day */
+    temp_year = check_leap_year(beijing_time->year) ? 366 : 365;
+    while (remain_day >= temp_year) {
+        beijing_time->year++;
+        remain_day -= temp_year;
+        temp_year = check_leap_year(beijing_time->year) ? 366 : 365;
+    }
+
+    /* Calculate specific dates(month\day)*/
+    p = check_leap_year(beijing_time->year) ? Leap_month_day : month_day;
+    remain_day++; //The actual day starts at 1
+    beijing_time->month = 0;
+    while (remain_day > *(p + beijing_time->month)) {
+        remain_day -= *(p + beijing_time->month);
+        beijing_time->month++;
+    }
+
+    beijing_time->month++; //The actual month starts at 1
+    beijing_time->day = remain_day;
+
+
+
+	/*利用基姆拉尔森计算日期公式  w=(d+2*m+3*(m+1)/5+y+y/4-y/100+y/400)*/
+
+	beijing_time->week = beijing_time->day + 2*beijing_time->month + 3*(beijing_time->month+1)/5 + \
+	beijing_time->year + beijing_time->year/4 - beijing_time->year/100 +beijing_time->year/400 ;
+
+	cal_weekday(beijing_time);
+}
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/timestamp/timestamp.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/timestamp/timestamp.h
new file mode 100644
index 00000000..dfa95e2d
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/timestamp/timestamp.h
@@ -0,0 +1,45 @@
+/**
+ * @file timestamp.h
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef _TIMESTAMP_
+#define _TIMESTAMP_
+
+#include "stdint.h"
+#include "stddef.h"
+#include "stdbool.h"
+
+typedef struct _rtc_time_t
+{
+	uint16_t year;
+	uint8_t month;
+	uint8_t day;
+	uint8_t week;
+	uint8_t hour;
+	uint8_t minute;
+	uint8_t second;
+}rtc_time;
+
+void unixtime2bejingtime(uint32_t unixtime,rtc_time* beijing_time);
+
+#endif
+
+
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/freertos/portable/gcc/risc-v/bl702/FreeRTOSConfig.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/freertos/portable/gcc/risc-v/bl702/FreeRTOSConfig.h
new file mode 100644
index 00000000..1ad79327
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/freertos/portable/gcc/risc-v/bl702/FreeRTOSConfig.h
@@ -0,0 +1,112 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define CLINT_CTRL_ADDR                         (0x02000000UL)
+#define configCLINT_BASE_ADDRESS                CLINT_CTRL_ADDR
+#define configUSE_PREEMPTION                    1
+#define configUSE_IDLE_HOOK                     0
+#define configUSE_TICK_HOOK                     0
+#define configCPU_CLOCK_HZ                      (1000000UL)
+#define configTICK_RATE_HZ                      ((TickType_t)1000)
+#define configMAX_PRIORITIES                    (7)
+#define configMINIMAL_STACK_SIZE                ((unsigned short)512) /* Only needs to be this high as some demo tasks also use this constant.  In production only the idle task would use this. */
+#define configTOTAL_HEAP_SIZE                   ((size_t)48 * 1024)
+#define configMAX_TASK_NAME_LEN                 (16)
+#define configUSE_TRACE_FACILITY                1
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 0
+#define configUSE_MUTEXES                       1
+#define configQUEUE_REGISTRY_SIZE               8
+#define configCHECK_FOR_STACK_OVERFLOW          2
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_MALLOC_FAILED_HOOK            1
+#define configUSE_APPLICATION_TASK_TAG          0
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configGENERATE_RUN_TIME_STATS           0
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#define configUSE_STATS_FORMATTING_FUNCTIONS    2
+#define configUSE_TICKLESS_IDLE                 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES           0
+#define configMAX_CO_ROUTINE_PRIORITIES (2)
+
+/* Software timer definitions. */
+#define configUSE_TIMERS             1
+#define configTIMER_TASK_PRIORITY    (configMAX_PRIORITIES - 1)
+#define configTIMER_QUEUE_LENGTH     8
+#define configTIMER_TASK_STACK_DEPTH (160)
+
+/* Task priorities.  Allow these to be overridden. */
+#ifndef uartPRIMARY_PRIORITY
+#define uartPRIMARY_PRIORITY (configMAX_PRIORITIES - 3)
+#endif
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet         1
+#define INCLUDE_uxTaskPriorityGet        1
+#define INCLUDE_vTaskDelete              1
+#define INCLUDE_vTaskCleanUpResources    1
+#define INCLUDE_vTaskSuspend             1
+#define INCLUDE_vTaskDelayUntil          1
+#define INCLUDE_vTaskDelay               1
+#define INCLUDE_eTaskGetState            1
+#define INCLUDE_xTimerPendFunctionCall   1
+#define INCLUDE_xTaskAbortDelay          1
+#define INCLUDE_xTaskGetHandle           1
+#define INCLUDE_xSemaphoreGetMutexHolder 1
+
+/* Normal assert() semantics without relying on the provision of an assert.h
+header file. */
+void vAssertCalled(void);
+#define configASSERT(x) \
+    if ((x) == 0)       \
+    vAssertCalled()
+
+#if (configUSE_TICKLESS_IDLE != 0)
+void vApplicationSleep(uint32_t xExpectedIdleTime);
+#define portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vApplicationSleep(xExpectedIdleTime)
+#endif
+
+#define portUSING_MPU_WRAPPERS 0
+#endif /* FREERTOS_CONFIG_H */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/freertos/portable/gcc/risc-v/bl702/freertos_risc_v_chip_specific_extensions.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/freertos/portable/gcc/risc-v/bl702/freertos_risc_v_chip_specific_extensions.h
new file mode 100644
index 00000000..1b695c8c
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/freertos/portable/gcc/risc-v/bl702/freertos_risc_v_chip_specific_extensions.h
@@ -0,0 +1,67 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
+ *
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ *   is common to all currently supported RISC-V chips.  There is only one
+ *   portASM.S file because the same file is built for all RISC-V target chips.
+ *
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
+ *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
+ *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
+ *   as there are multiple RISC-V chip implementations.
+ *
+ * !!!NOTE!!!
+ * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
+ * HEADER FILE FOR THE CHIP IN USE.  This is done using the assembler's (not the
+ * compiler's!) include path.  For example, if the chip in use includes a core
+ * local interrupter (CLINT) and does not include any chip specific register
+ * extensions then add the path below to the assembler's include path:
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ *
+ */
+
+#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
+#define __FREERTOS_RISC_V_EXTENSIONS_H__
+
+#define portasmHAS_CLINT               1
+#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
+
+.macro portasmSAVE_ADDITIONAL_REGISTERS
+    /* No additional registers to save, so this macro does nothing. */
+    .endm
+
+    /* Restore the additional registers found on the Pulpino. */
+    .macro portasmRESTORE_ADDITIONAL_REGISTERS
+    /* No additional registers to restore, so this macro does nothing. */
+    .endm
+
+#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/freertos/portable/gcc/risc-v/bl702/port.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/freertos/portable/gcc/risc-v/bl702/port.c
new file mode 100644
index 00000000..36ec1514
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/freertos/portable/gcc/risc-v/bl702/port.c
@@ -0,0 +1,195 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the RISC-V RV32 port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "portmacro.h"
+
+#ifndef configCLINT_BASE_ADDRESS
+#warning configCLINT_BASE_ADDRESS must be defined in FreeRTOSConfig.h.  If the target chip includes a Core Local Interrupter (CLINT) then set configCLINT_BASE_ADDRESS to the CLINT base address.  Otherwise set configCLINT_BASE_ADDRESS to 0.
+#endif
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+#define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/* The stack used by interrupt service routines.  Set configISR_STACK_SIZE_WORDS
+to use a statically allocated array as the interrupt stack.  Alternative leave
+configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
+linker variable names __freertos_irq_stack_top has the same value as the top
+of the stack used by main.  Using the linker script method will repurpose the
+stack that was used by main before the scheduler was started for use as the
+interrupt stack after the scheduler has started. */
+#ifdef configISR_STACK_SIZE_WORDS
+static __attribute__((aligned(16))) StackType_t xISRStack[configISR_STACK_SIZE_WORDS] = { 0 };
+const StackType_t xISRStackTop = (StackType_t) & (xISRStack[configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK]);
+#else
+extern const uint32_t __freertos_irq_stack_top[];
+const StackType_t xISRStackTop = (StackType_t)__freertos_irq_stack_top;
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt(void) __attribute__((weak));
+
+/*-----------------------------------------------------------*/
+
+/* Used to program the machine timer compare register. */
+uint64_t ullNextTime = 0ULL;
+const uint64_t *pullNextTime = &ullNextTime;
+const size_t uxTimerIncrementsForOneTick = (size_t)(configCPU_CLOCK_HZ / configTICK_RATE_HZ); /* Assumes increment won't go over 32-bits. */
+volatile uint64_t *const pullMachineTimerCompareRegisterBase = (volatile uint64_t *const)(configCLINT_BASE_ADDRESS + 0x4000);
+volatile uint64_t *pullMachineTimerCompareRegister = 0;
+BaseType_t TrapNetCounter = 0;
+const BaseType_t *pTrapNetCounter = &TrapNetCounter;
+
+/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
+stack checking.  A problem in the ISR stack will trigger an assert, not call the
+stack overflow hook function (because the stack overflow hook is specific to a
+task stack, not the ISR stack). */
+#if (configCHECK_FOR_STACK_OVERFLOW > 2)
+#warning This path not tested, or even compiled yet.
+/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
+the task stacks, and so will legitimately appear in many positions within
+the ISR stack. */
+#define portISR_STACK_FILL_BYTE 0xee
+
+static const uint8_t ucExpectedStackBytes[] = {
+    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,
+    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,
+    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,
+    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,
+    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE
+};
+
+#define portCHECK_ISR_STACK() configASSERT((memcmp((void *)xISRStack, (void *)ucExpectedStackBytes, sizeof(ucExpectedStackBytes)) == 0))
+#else
+/* Define the function away. */
+#define portCHECK_ISR_STACK()
+#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
+
+/*-----------------------------------------------------------*/
+
+#if (configCLINT_BASE_ADDRESS != 0)
+
+void vPortSetupTimerInterrupt(void)
+{
+    uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
+    volatile uint32_t *const pulTimeHigh = (volatile uint32_t *const)(configCLINT_BASE_ADDRESS + 0xBFFC);
+    volatile uint32_t *const pulTimeLow = (volatile uint32_t *const)(configCLINT_BASE_ADDRESS + 0xBFF8);
+    volatile uint32_t ulHartId = 0;
+
+    __asm volatile("csrr %0, mhartid"
+                   : "=r"(ulHartId));
+    pullMachineTimerCompareRegister = &(pullMachineTimerCompareRegisterBase[ulHartId]);
+
+    do {
+        ulCurrentTimeHigh = *pulTimeHigh;
+        ulCurrentTimeLow = *pulTimeLow;
+    } while (ulCurrentTimeHigh != *pulTimeHigh);
+
+    ullNextTime = (uint64_t)ulCurrentTimeHigh;
+    ullNextTime <<= 32ULL;
+    ullNextTime |= (uint64_t)ulCurrentTimeLow;
+    ullNextTime += (uint64_t)uxTimerIncrementsForOneTick;
+    *pullMachineTimerCompareRegister = ullNextTime;
+
+    /* Prepare the time to use after the next tick interrupt. */
+    ullNextTime += (uint64_t)uxTimerIncrementsForOneTick;
+}
+
+#endif /* ( configCLINT_BASE_ADDRESS != 0 ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler(void)
+{
+    extern void xPortStartFirstTask(void);
+
+#if (configASSERT_DEFINED == 1)
+    {
+        volatile uint32_t mtvec = 0;
+
+        /* Check the least significant two bits of mtvec are 00 - indicating
+        single vector mode. */
+        __asm volatile("csrr %0, mtvec"
+                       : "=r"(mtvec));
+        //configASSERT( ( mtvec & 0x03UL ) == 0 );
+
+        /* Check alignment of the interrupt stack - which is the same as the
+        stack that was being used by main() prior to the scheduler being
+        started. */
+        configASSERT((xISRStackTop & portBYTE_ALIGNMENT_MASK) == 0);
+    }
+#endif /* configASSERT_DEFINED */
+
+    /* If there is a CLINT then it is ok to use the default implementation
+    in this file, otherwise vPortSetupTimerInterrupt() must be implemented to
+    configure whichever clock is to be used to generate the tick interrupt. */
+    vPortSetupTimerInterrupt();
+
+#if (configCLINT_BASE_ADDRESS != 0)
+    {
+        /* Enable mtime and external interrupts.  1<<7 for timer interrupt, 1<<11
+        for external interrupt.  _RB_ What happens here when mtime is not present as
+        with pulpino? */
+        __asm volatile("csrs mie, %0" ::"r"(0x880));
+    }
+#else
+    {
+        /* Enable external interrupts. */
+        __asm volatile("csrs mie, %0" ::"r"(0x800));
+    }
+#endif /* configCLINT_BASE_ADDRESS */
+
+    *(uint8_t *)(0x02800400 + 7) = 1;
+    xPortStartFirstTask();
+
+    /* Should not get here as after calling xPortStartFirstTask() only tasks
+    should be executing. */
+    return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler(void)
+{
+    /* Not implemented. */
+    for (;;)
+        ;
+}
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/freertos/portable/gcc/risc-v/bl702/portASM.S b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/freertos/portable/gcc/risc-v/bl702/portASM.S
new file mode 100644
index 00000000..74f50f2b
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/freertos/portable/gcc/risc-v/bl702/portASM.S
@@ -0,0 +1,452 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
+ *
+ * + The code that is common to all RISC-V chips is implemented in
+ *   FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S.  There is only one
+ *   portASM.S file because the same file is used no matter which RISC-V chip is
+ *   in use.
+ *
+ * + The code that tailors the kernel's RISC-V port to a specific RISC-V
+ *   chip is implemented in freertos_risc_v_chip_specific_extensions.h.  There
+ *   is one freertos_risc_v_chip_specific_extensions.h that can be used with any
+ *   RISC-V chip that both includes a standard CLINT and does not add to the
+ *   base set of RISC-V registers.  There are additional
+ *   freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
+ *   that do not include a standard CLINT or do add to the base set of RISC-V
+ *   registers.
+ *
+ * CARE MUST BE TAKEN TO INCLDUE THE CORRECT
+ * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
+ * IN USE.  To include the correct freertos_risc_v_chip_specific_extensions.h
+ * header file ensure the path to the correct header file is in the assembler's
+ * include path.
+ *
+ * This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
+ * that include a standard CLINT and do not add to the base set of RISC-V
+ * registers.
+ *
+ */
+#if __riscv_xlen == 64
+	#define portWORD_SIZE 8
+	#define store_x sd
+	#define load_x ld
+#elif __riscv_xlen == 32
+	#define store_x sw
+	#define load_x lw
+	#define portWORD_SIZE 4
+#else
+	#error Assembler did not define __riscv_xlen
+#endif
+
+#include "freertos_risc_v_chip_specific_extensions.h"
+
+/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line
+definitions. */
+#ifndef portasmHAS_CLINT
+	#error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_CLINT to either 1 (CLINT present) or 0 (clint not present).
+#endif
+
+#ifndef portasmHANDLE_INTERRUPT
+	#error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts.  portasmHANDLE_INTERRUPT can be defined on the assmbler command line or in the appropriate freertos_risc_v_chip_specific_extensions.h header file.
+#endif
+
+/* Only the standard core registers are stored by default.  Any additional
+registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and
+portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
+specific version of freertos_risc_v_chip_specific_extensions.h.  See the notes
+at the top of this file. */
+#define portCONTEXT_SIZE ( 30 * portWORD_SIZE )
+
+.global xPortStartFirstTask
+.global freertos_risc_v_trap_handler
+.global pxPortInitialiseStack
+.extern pxCurrentTCB
+.extern ulPortTrapHandler
+.extern vTaskSwitchContext
+.extern xTaskIncrementTick
+.extern Timer_IRQHandler
+.extern pullMachineTimerCompareRegister
+.extern pullNextTime
+ .extern pTrapNetCounter
+.extern uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */
+.extern xISRStackTop
+.extern portasmHANDLE_INTERRUPT
+.extern Trap_Handler
+
+/*-----------------------------------------------------------*/
+
+.align 8
+.func
+freertos_risc_v_trap_handler:
+	addi sp, sp, -portCONTEXT_SIZE
+	store_x x1, 1 * portWORD_SIZE( sp )
+	store_x x5, 2 * portWORD_SIZE( sp )
+	store_x x6, 3 * portWORD_SIZE( sp )
+	store_x x7, 4 * portWORD_SIZE( sp )
+	store_x x8, 5 * portWORD_SIZE( sp )
+	store_x x9, 6 * portWORD_SIZE( sp )
+	store_x x10, 7 * portWORD_SIZE( sp )
+	store_x x11, 8 * portWORD_SIZE( sp )
+	store_x x12, 9 * portWORD_SIZE( sp )
+	store_x x13, 10 * portWORD_SIZE( sp )
+	store_x x14, 11 * portWORD_SIZE( sp )
+	store_x x15, 12 * portWORD_SIZE( sp )
+	store_x x16, 13 * portWORD_SIZE( sp )
+	store_x x17, 14 * portWORD_SIZE( sp )
+	store_x x18, 15 * portWORD_SIZE( sp )
+	store_x x19, 16 * portWORD_SIZE( sp )
+	store_x x20, 17 * portWORD_SIZE( sp )
+	store_x x21, 18 * portWORD_SIZE( sp )
+	store_x x22, 19 * portWORD_SIZE( sp )
+	store_x x23, 20 * portWORD_SIZE( sp )
+	store_x x24, 21 * portWORD_SIZE( sp )
+	store_x x25, 22 * portWORD_SIZE( sp )
+	store_x x26, 23 * portWORD_SIZE( sp )
+	store_x x27, 24 * portWORD_SIZE( sp )
+	store_x x28, 25 * portWORD_SIZE( sp )
+	store_x x29, 26 * portWORD_SIZE( sp )
+	store_x x30, 27 * portWORD_SIZE( sp )
+	store_x x31, 28 * portWORD_SIZE( sp )
+
+	csrr t0, mstatus					/* Required for MPIE bit. */
+	store_x t0, 29 * portWORD_SIZE( sp )
+
+	portasmSAVE_ADDITIONAL_REGISTERS	/* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
+
+         load_x  t0, pTrapNetCounter
+         lw   t1, 0( t0 )
+         addi   t1, t1, 1
+         store_x t1, 0( t0 )
+
+	load_x  t0, pxCurrentTCB			/* Load pxCurrentTCB. */
+	store_x  sp, 0( t0 )				/* Write sp to first TCB member. */
+
+	csrr a0, mcause
+	csrr a1, mepc
+
+	li t0, 0x80000FFF
+	and a0, a0, t0
+test_if_asynchronous:
+	srli a2, a0, __riscv_xlen - 1		/* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */
+	beq a2, x0, handle_synchronous		/* Branch past interrupt handing if not asynchronous. */
+	store_x a1, 0( sp )					/* Asynch so save unmodified exception return address. */
+
+handle_asynchronous:
+
+#if( portasmHAS_CLINT != 0 )
+
+	test_if_mtimer:						/* If there is a CLINT then the mtimer is used to generate the tick interrupt. */
+
+		addi t0, x0, 1
+
+		slli t0, t0, __riscv_xlen - 1   /* LSB is already set, shift into MSB.  Shift 31 on 32-bit or 63 on 64-bit cores. */
+		addi t1, t0, 7					/* 0x8000[]0007 == machine timer interrupt. */
+		bne a0, t1, test_if_external_interrupt
+
+		load_x t0, pullMachineTimerCompareRegister  /* Load address of compare register into t0. */
+		load_x t1, pullNextTime  		/* Load the address of ullNextTime into t1. */
+
+		#if( __riscv_xlen == 32 )
+
+			/* Update the 64-bit mtimer compare match value in two 32-bit writes. */
+			li t4, -1
+			lw t2, 0(t1)				/* Load the low word of ullNextTime into t2. */
+			lw t3, 4(t1)				/* Load the high word of ullNextTime into t3. */
+			sw t4, 0(t0)				/* Low word no smaller than old value to start with - will be overwritten below. */
+			sw t3, 4(t0)				/* Store high word of ullNextTime into compare register.  No smaller than new value. */
+			sw t2, 0(t0)				/* Store low word of ullNextTime into compare register. */
+			lw t0, uxTimerIncrementsForOneTick	/* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
+			add t4, t0, t2				/* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */
+			sltu t5, t4, t2				/* See if the sum of low words overflowed (what about the zero case?). */
+			add t6, t3, t5				/* Add overflow to high word of ullNextTime. */
+			sw t4, 0(t1)				/* Store new low word of ullNextTime. */
+			sw t6, 4(t1)				/* Store new high word of ullNextTime. */
+
+		#endif /* __riscv_xlen == 32 */
+
+		#if( __riscv_xlen == 64 )
+
+			/* Update the 64-bit mtimer compare match value. */
+			ld t2, 0(t1)			 	/* Load ullNextTime into t2. */
+			sd t2, 0(t0)				/* Store ullNextTime into compare register. */
+			ld t0, uxTimerIncrementsForOneTick  /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
+			add t4, t0, t2				/* Add ullNextTime to the timer increments for one tick. */
+			sd t4, 0(t1)				/* Store ullNextTime. */
+
+		#endif /* __riscv_xlen == 64 */
+
+		load_x sp, xISRStackTop			/* Switch to ISR stack before function call. */
+		jal xTaskIncrementTick
+		beqz a0, processed_source		/* Don't switch context if incrementing tick didn't unblock a task. */
+		jal vTaskSwitchContext
+		j processed_source
+
+	test_if_external_interrupt:			/* If there is a CLINT and the mtimer interrupt is not pending then check to see if an external interrupt is pending. */
+		//addi t1, t1, 4					/* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */
+		//bne a0, t1, as_yet_unhandled	/* Something as yet unhandled. */
+
+#endif /* portasmHAS_CLINT */
+
+	load_x sp, xISRStackTop				/* Switch to ISR stack before function call. */
+	jal portasmHANDLE_INTERRUPT			/* Jump to the interrupt handler if there is no CLINT or if there is a CLINT and it has been determined that an external interrupt is pending. */
+	j processed_source
+
+handle_synchronous:
+	addi a1, a1, 4						/* Synchronous so updated exception return address to the instruction after the instruction that generated the exeption. */
+	store_x a1, 0( sp )					/* Save updated exception return address. */
+
+test_if_environment_call:
+	li t0, 11 							/* 11 == environment call. */
+	bne a0, t0, is_exception			/* Not an M environment call, so some other exception. */
+	load_x sp, xISRStackTop				/* Switch to ISR stack before function call. */
+	jal vTaskSwitchContext
+	j processed_source
+
+is_exception:
+	csrr t0, mcause						/* For viewing in the debugger only. */
+	csrr t1, mepc						/* For viewing in the debugger only */
+	csrr t2, mstatus
+	load_x sp, xISRStackTop
+	jal Trap_Handler
+	j is_exception
+
+as_yet_unhandled:
+	csrr t0, mcause						/* For viewing in the debugger only. */
+	j as_yet_unhandled
+
+processed_source:
+
+         load_x  t0, pTrapNetCounter
+         lw   t1, 0 ( t0 )
+         addi   t1, t1, -1
+         store_x t1, 0( t0 )
+         
+	load_x  t1, pxCurrentTCB			/* Load pxCurrentTCB. */
+	load_x  sp, 0( t1 )				 	/* Read sp from first TCB member. */
+
+	/* Load mret with the address of the next instruction in the task to run next. */
+	load_x t0, 0( sp )
+	csrw mepc, t0
+
+	portasmRESTORE_ADDITIONAL_REGISTERS	/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
+
+	/* Load mstatus with the interrupt enable bits used by the task. */
+	load_x  t0, 29 * portWORD_SIZE( sp )
+	csrw mstatus, t0						/* Required for MPIE bit. */
+
+	load_x  x1, 1 * portWORD_SIZE( sp )
+	load_x  x5, 2 * portWORD_SIZE( sp )		/* t0 */
+	load_x  x6, 3 * portWORD_SIZE( sp )		/* t1 */
+	load_x  x7, 4 * portWORD_SIZE( sp )		/* t2 */
+	load_x  x8, 5 * portWORD_SIZE( sp )		/* s0/fp */
+	load_x  x9, 6 * portWORD_SIZE( sp )		/* s1 */
+	load_x  x10, 7 * portWORD_SIZE( sp )	/* a0 */
+	load_x  x11, 8 * portWORD_SIZE( sp )	/* a1 */
+	load_x  x12, 9 * portWORD_SIZE( sp )	/* a2 */
+	load_x  x13, 10 * portWORD_SIZE( sp )	/* a3 */
+	load_x  x14, 11 * portWORD_SIZE( sp )	/* a4 */
+	load_x  x15, 12 * portWORD_SIZE( sp )	/* a5 */
+	load_x  x16, 13 * portWORD_SIZE( sp )	/* a6 */
+	load_x  x17, 14 * portWORD_SIZE( sp )	/* a7 */
+	load_x  x18, 15 * portWORD_SIZE( sp )	/* s2 */
+	load_x  x19, 16 * portWORD_SIZE( sp )	/* s3 */
+	load_x  x20, 17 * portWORD_SIZE( sp )	/* s4 */
+	load_x  x21, 18 * portWORD_SIZE( sp )	/* s5 */
+	load_x  x22, 19 * portWORD_SIZE( sp )	/* s6 */
+	load_x  x23, 20 * portWORD_SIZE( sp )	/* s7 */
+	load_x  x24, 21 * portWORD_SIZE( sp )	/* s8 */
+	load_x  x25, 22 * portWORD_SIZE( sp )	/* s9 */
+	load_x  x26, 23 * portWORD_SIZE( sp )	/* s10 */
+	load_x  x27, 24 * portWORD_SIZE( sp )	/* s11 */
+	load_x  x28, 25 * portWORD_SIZE( sp )	/* t3 */
+	load_x  x29, 26 * portWORD_SIZE( sp )	/* t4 */
+	load_x  x30, 27 * portWORD_SIZE( sp )	/* t5 */
+	load_x  x31, 28 * portWORD_SIZE( sp )	/* t6 */
+	addi sp, sp, portCONTEXT_SIZE
+
+	mret
+	.endfunc
+/*-----------------------------------------------------------*/
+
+.align 8
+.func
+xPortStartFirstTask:
+
+#if( portasmHAS_CLINT != 0 )
+	/* If there is a clint then interrupts can branch directly to the FreeRTOS
+	trap handler.  Otherwise the interrupt controller will need to be configured
+	outside of this file. */
+	la t0, freertos_risc_v_trap_handler
+	ori t0, t0, 2
+	csrw mtvec, t0
+#endif /* portasmHAS_CLILNT */
+
+	load_x  sp, pxCurrentTCB			/* Load pxCurrentTCB. */
+	load_x  sp, 0( sp )				 	/* Read sp from first TCB member. */
+
+	load_x  x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
+
+	portasmRESTORE_ADDITIONAL_REGISTERS	/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
+
+	load_x  t0, 29 * portWORD_SIZE( sp )	/* mstatus */
+	addi t0, t0, 0x08						/* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
+	csrrw  x0, mstatus, t0					/* Interrupts enabled from here! */
+
+	load_x  x5, 2 * portWORD_SIZE( sp )		/* t0 */
+	load_x  x6, 3 * portWORD_SIZE( sp )		/* t1 */
+	load_x  x7, 4 * portWORD_SIZE( sp )		/* t2 */
+	load_x  x8, 5 * portWORD_SIZE( sp )		/* s0/fp */
+	load_x  x9, 6 * portWORD_SIZE( sp )		/* s1 */
+	load_x  x10, 7 * portWORD_SIZE( sp )	/* a0 */
+	load_x  x11, 8 * portWORD_SIZE( sp )	/* a1 */
+	load_x  x12, 9 * portWORD_SIZE( sp )	/* a2 */
+	load_x  x13, 10 * portWORD_SIZE( sp )	/* a3 */
+	load_x  x14, 11 * portWORD_SIZE( sp )	/* a4 */
+	load_x  x15, 12 * portWORD_SIZE( sp )	/* a5 */
+	load_x  x16, 13 * portWORD_SIZE( sp )	/* a6 */
+	load_x  x17, 14 * portWORD_SIZE( sp )	/* a7 */
+	load_x  x18, 15 * portWORD_SIZE( sp )	/* s2 */
+	load_x  x19, 16 * portWORD_SIZE( sp )	/* s3 */
+	load_x  x20, 17 * portWORD_SIZE( sp )	/* s4 */
+	load_x  x21, 18 * portWORD_SIZE( sp )	/* s5 */
+	load_x  x22, 19 * portWORD_SIZE( sp )	/* s6 */
+	load_x  x23, 20 * portWORD_SIZE( sp )	/* s7 */
+	load_x  x24, 21 * portWORD_SIZE( sp )	/* s8 */
+	load_x  x25, 22 * portWORD_SIZE( sp )	/* s9 */
+	load_x  x26, 23 * portWORD_SIZE( sp )	/* s10 */
+	load_x  x27, 24 * portWORD_SIZE( sp )	/* s11 */
+	load_x  x28, 25 * portWORD_SIZE( sp )	/* t3 */
+	load_x  x29, 26 * portWORD_SIZE( sp )	/* t4 */
+	load_x  x30, 27 * portWORD_SIZE( sp )	/* t5 */
+	load_x  x31, 28 * portWORD_SIZE( sp )	/* t6 */
+	addi	sp, sp, portCONTEXT_SIZE
+	ret
+	.endfunc
+/*-----------------------------------------------------------*/
+
+/*
+ * Unlike other ports pxPortInitialiseStack() is written in assembly code as it
+ * needs access to the portasmADDITIONAL_CONTEXT_SIZE constant.  The prototype
+ * for the function is as per the other ports:
+ * StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters );
+ *
+ * As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in
+ * a1, and pvParameters in a2.  The new top of stack is passed out in a0.
+ *
+ * RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
+ * for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
+ *
+ * Register		ABI Name	Description						Saver
+ * x0			zero		Hard-wired zero					-
+ * x1			ra			Return address					Caller
+ * x2			sp			Stack pointer					Callee
+ * x3			gp			Global pointer					-
+ * x4			tp			Thread pointer					-
+ * x5-7			t0-2		Temporaries						Caller
+ * x8			s0/fp		Saved register/Frame pointer	Callee
+ * x9			s1			Saved register					Callee
+ * x10-11		a0-1		Function Arguments/return values Caller
+ * x12-17		a2-7		Function arguments				Caller
+ * x18-27		s2-11		Saved registers					Callee
+ * x28-31		t3-6		Temporaries						Caller
+ *
+ * The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
+ * where the global and thread pointers are currently assumed to be constant so
+ * are not saved:
+ *
+ * mstatus
+ * x31
+ * x30
+ * x29
+ * x28
+ * x27
+ * x26
+ * x25
+ * x24
+ * x23
+ * x22
+ * x21
+ * x20
+ * x19
+ * x18
+ * x17
+ * x16
+ * x15
+ * x14
+ * x13
+ * x12
+ * x11
+ * pvParameters
+ * x9
+ * x8
+ * x7
+ * x6
+ * x5
+ * portTASK_RETURN_ADDRESS
+ * [chip specific registers go here]
+ * pxCode
+ */
+.align 8
+.func
+pxPortInitialiseStack:
+
+	csrr t0, mstatus					/* Obtain current mstatus value. */
+
+#if 1
+    li   t1, 0x1880
+    or   t0, t0, t1                     /* MPP = 0b11, MPIE = 1 */
+    andi t0, t0, 0xFFFFFFF7             /* !!! MIE = 0 !!! */
+#else
+	addi t1, x0, 0x188					/* Generate the value 0x1888, which are the MIE, MPIE and privilege bits to set in mstatus. */
+	slli t1, t1, 4
+	or t0, t0, t1						/* Set MPIE and MPP bits in mstatus value. */
+#endif
+
+	addi a0, a0, -portWORD_SIZE
+	store_x t0, 0(a0)					/* mstatus onto the stack. */
+	addi a0, a0, -(22 * portWORD_SIZE)	/* Space for registers x11-x31. */
+	store_x a2, 0(a0)					/* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
+	addi a0, a0, -(6 * portWORD_SIZE)	/* Space for registers x5-x9. */
+	store_x x0, 0(a0)					/* Return address onto the stack, could be portTASK_RETURN_ADDRESS */
+	addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
+chip_specific_stack_frame:				/* First add any chip specific registers to the stack frame being created. */
+	beq t0, x0, 1f						/* No more chip specific registers to save. */
+	addi a0, a0, -portWORD_SIZE			/* Make space for chip specific register. */
+	store_x x0, 0(a0)					/* Give the chip specific register an initial value of zero. */
+	addi t0, t0, -1						/* Decrement the count of chip specific registers remaining. */
+	j chip_specific_stack_frame			/* Until no more chip specific registers. */
+1:
+	addi a0, a0, -portWORD_SIZE
+	store_x a1, 0(a0)					/* mret value (pxCode parameter) onto the stack. */
+	ret
+	.endfunc
+/*-----------------------------------------------------------*/
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/freertos/portable/gcc/risc-v/bl702/portmacro.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/freertos/portable/gcc/risc-v/bl702/portmacro.h
new file mode 100644
index 00000000..2f331e48
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/freertos/portable/gcc/risc-v/bl702/portmacro.h
@@ -0,0 +1,164 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+#include 
+#include 
+
+/* Type definitions. */
+#if __riscv_xlen == 64
+#define portSTACK_TYPE        uint64_t
+#define portBASE_TYPE         int64_t
+#define portUBASE_TYPE        uint64_t
+#define portMAX_DELAY         (TickType_t)0xffffffffffffffffUL
+#define portPOINTER_SIZE_TYPE uint64_t
+#elif __riscv_xlen == 32
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE  int /* int32_t */
+#define portUBASE_TYPE uint32_t
+#define portMAX_DELAY  (TickType_t)0xffffffffUL
+#ifdef __riscv_float_abi_single
+/* better to use float replace double here,
+ * so that it will generates floating point instructions
+ */
+#define portDOUBLE float /* double */
+#else
+#define portDOUBLE double
+#endif
+#else
+#error Assembler did not define __riscv_xlen
+#endif
+
+typedef portSTACK_TYPE StackType_t;
+typedef portBASE_TYPE  BaseType_t;
+typedef portUBASE_TYPE UBaseType_t;
+typedef portUBASE_TYPE TickType_t;
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH   (-1)
+#define portTICK_PERIOD_MS ((TickType_t)1000 / configTICK_RATE_HZ)
+#ifdef __riscv64
+#error This is the RV32 port that has not yet been adapted for 64.
+#define portBYTE_ALIGNMENT 16
+#else
+#define portBYTE_ALIGNMENT 16
+#endif
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+extern BaseType_t TrapNetCounter;
+extern void       vTaskSwitchContext(void);
+#define portYIELD() __asm volatile("ecall");
+#define portEND_SWITCHING_ISR(xSwitchRequired) \
+  if (xSwitchRequired)                         \
+  vTaskSwitchContext()
+#define portYIELD_FROM_ISR(x) portEND_SWITCHING_ISR(x)
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#define portCRITICAL_NESTING_IN_TCB 1
+extern void vTaskEnterCritical(void);
+extern void vTaskExitCritical(void);
+
+#define portSET_INTERRUPT_MASK_FROM_ISR()                     0
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(uxSavedStatusValue) (void)uxSavedStatusValue
+#define portDISABLE_INTERRUPTS()                              __asm volatile("csrc mstatus, 8")
+#define portENABLE_INTERRUPTS()                               __asm volatile("csrs mstatus, 8")
+#define portENTER_CRITICAL()                                  vTaskEnterCritical()
+#define portEXIT_CRITICAL()                                   vTaskExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if (configUSE_PORT_OPTIMISED_TASK_SELECTION == 1)
+
+/* Check the configuration. */
+#if (configMAX_PRIORITIES > 32)
+#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+#endif
+
+/* Store/clear the ready priorities in a bit map. */
+#define portRECORD_READY_PRIORITY(uxPriority, uxReadyPriorities) (uxReadyPriorities) |= (1UL << (uxPriority))
+#define portRESET_READY_PRIORITY(uxPriority, uxReadyPriorities)  (uxReadyPriorities) &= ~(1UL << (uxPriority))
+
+/*-----------------------------------------------------------*/
+
+#define portGET_HIGHEST_PRIORITY(uxTopPriority, uxReadyPriorities) uxTopPriority = (31UL - __builtin_clz(uxReadyPriorities))
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters)
+#define portTASK_FUNCTION(vFunction, pvParameters)       void vFunction(void *pvParameters)
+
+/*-----------------------------------------------------------*/
+
+#define portNOP() __asm volatile(" nop ")
+
+#define portINLINE __inline
+
+#ifndef portFORCE_INLINE
+#define portFORCE_INLINE inline __attribute__((always_inline))
+#endif
+
+#define portMEMORY_BARRIER() __asm volatile("" ::: "memory")
+
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt(void) { return TrapNetCounter ? 1 : 0; }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/freertos/portable/readme.txt b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/freertos/portable/readme.txt
new file mode 100644
index 00000000..b68d2d57
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/freertos/portable/readme.txt
@@ -0,0 +1,20 @@
+Each real time kernel port consists of three files that contain the core kernel
+components and are common to every port, and one or more files that are
+specific to a particular microcontroller and/or compiler.
+
+
++ The FreeRTOS/Source/Portable/MemMang directory contains the five sample
+memory allocators as described on the http://www.FreeRTOS.org WEB site.
+
++ The other directories each contain files specific to a particular
+microcontroller or compiler, where the directory name denotes the compiler
+specific files the directory contains.
+
+
+
+For example, if you are interested in the [compiler] port for the [architecture]
+microcontroller, then the port specific files are contained in
+FreeRTOS/Source/Portable/[compiler]/[architecture] directory.  If this is the
+only port you are interested in then all the other directories can be
+ignored.
+
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/CMakeLists.txt b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/CMakeLists.txt
new file mode 100644
index 00000000..f067f2bc
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/CMakeLists.txt
@@ -0,0 +1,46 @@
+################# Add global include #################
+list(APPEND ADD_INCLUDE
+"${CMAKE_CURRENT_SOURCE_DIR}/core/inc"
+"${CMAKE_CURRENT_SOURCE_DIR}/dsp/inc"
+"${CMAKE_CURRENT_SOURCE_DIR}/nn/inc"
+)
+#######################################################
+
+################# Add private include #################
+list(APPEND ADD_PRIVATE_INCLUDE
+"${CMAKE_CURRENT_SOURCE_DIR}/dsp/privateInc"
+)
+#######################################################
+
+############## Add current dir source files ###########
+file(GLOB_RECURSE sources "${CMAKE_CURRENT_SOURCE_DIR}/dsp/*.c"
+"${CMAKE_CURRENT_SOURCE_DIR}/nn/*.c"
+)
+list(APPEND ADD_SRCS  ${sources})
+# aux_source_directory(src ADD_SRCS)
+# list(REMOVE_ITEM ADD_SRCS "${CMAKE_CURRENT_SOURCE_DIR}")
+#######################################################
+
+########### Add required/dependent components #########
+# list(APPEND ADD_REQUIREMENTS common)
+#######################################################
+
+############ Add static libs ##########################
+#list(APPEND ADD_STATIC_LIB "libxxx.a")
+#######################################################
+
+############ Add dynamic libs #########################
+# list(APPEND ADD_DYNAMIC_LIB "libxxx.so")
+#######################################################
+
+############ Add global compile option ################
+#add components denpend on this component
+list(APPEND ADD_DEFINITIONS -D__RISCV_FEATURE_MVE=0 -Wno-incompatible-pointer-types -Wno-parentheses)
+#######################################################
+
+############ Add private compile option ################
+#add compile option for this component that won't affect other modules
+# list(APPEND ADD_PRIVATE_DEFINITIONS )
+#######################################################
+
+generate_library()
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_compatiable.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_compatiable.h
new file mode 100644
index 00000000..efd7ea85
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_compatiable.h
@@ -0,0 +1,226 @@
+/*
+ * Copyright (c) 2019 Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __CORE_COMPATIABLE_H__
+#define __CORE_COMPATIABLE_H__
+/*!
+ * @file     core_compatiable.h
+ * @brief    ARM compatiable function definitions header file
+ */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ===== ARM Compatiable Functions ===== */
+/**
+ * \defgroup NMSIS_Core_ARMCompatiable_Functions   ARM Compatiable Functions
+ * \ingroup  NMSIS_Core
+ * \brief    A few functions that compatiable with ARM CMSIS-Core.
+ * \details
+ *
+ * Here we provided a few functions that compatiable with ARM CMSIS-Core,
+ * mostly used in the DSP and NN library.
+ * @{
+ */
+/** \brief Instruction Synchronization Barrier, compatiable with ARM */
+#define __ISB() __RWMB()
+
+/** \brief Data Synchronization Barrier, compatiable with ARM */
+#define __DSB() __RWMB()
+
+/** \brief Data Memory Barrier, compatiable with ARM */
+#define __DMB() __RWMB()
+
+/** \brief LDRT Unprivileged (8 bit), ARM Compatiable */
+#define __LDRBT(ptr) __LB((ptr))
+/** \brief LDRT Unprivileged (16 bit), ARM Compatiable */
+#define __LDRHT(ptr) __LH((ptr))
+/** \brief LDRT Unprivileged (32 bit), ARM Compatiable */
+#define __LDRT(ptr) __LW((ptr))
+
+/** \brief STRT Unprivileged (8 bit), ARM Compatiable */
+#define __STRBT(val, ptr) __SB((ptr), (val))
+/** \brief STRT Unprivileged (16 bit), ARM Compatiable */
+#define __STRHT(val, ptr) __SH((ptr), (val))
+/** \brief STRT Unprivileged (32 bit), ARM Compatiable */
+#define __STRT(val, ptr) __SW((ptr), (val))
+
+/* ===== Saturation Operations ===== */
+/**
+ * \brief   Signed Saturate
+ * \details Saturates a signed value.
+ * \param [in]  value  Value to be saturated
+ * \param [in]    sat  Bit position to saturate to (1..32)
+ * \return             Saturated value
+ */
+#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
+#define __SSAT(val, sat) __RV_SCLIP32((val), (sat - 1))
+#else
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+    if ((sat >= 1U) && (sat <= 32U)) {
+        const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+        const int32_t min = -1 - max;
+        if (val > max) {
+            return max;
+        } else if (val < min) {
+            return min;
+        }
+    }
+    return val;
+}
+#endif
+
+/**
+ * \brief   Unsigned Saturate
+ * \details Saturates an unsigned value.
+ * \param [in]  value  Value to be saturated
+ * \param [in]    sat  Bit position to saturate to (0..31)
+ * \return             Saturated value
+ */
+#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
+#define __USAT(val, sat) __RV_UCLIP32((val), (sat))
+#else
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+    if (sat <= 31U) {
+        const uint32_t max = ((1U << sat) - 1U);
+        if (val > (int32_t)max) {
+            return max;
+        } else if (val < 0) {
+            return 0U;
+        }
+    }
+    return (uint32_t)val;
+}
+#endif
+#if 0
+/* ===== Data Processing Operations ===== */
+/**
+ * \brief   Reverse byte order (32 bit)
+ * \details Reverses the byte order in unsigned integer value.
+ * For example, 0x12345678 becomes 0x78563412.
+ * \param [in]    value  Value to reverse
+ * \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+    uint32_t result;
+
+    result = ((value & 0xff000000) >> 24) | ((value & 0x00ff0000) >> 8) | ((value & 0x0000ff00) << 8) | ((value & 0x000000ff) << 24);
+    return result;
+}
+
+/**
+ * \brief   Reverse byte order (16 bit)
+ * \details Reverses the byte order within each halfword of a word.
+ * For example, 0x12345678 becomes 0x34127856.
+ * \param [in]    value  Value to reverse
+ * \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+    uint32_t result;
+    result = ((value & 0xff000000) >> 8) | ((value & 0x00ff00000) << 8) | ((value & 0x0000ff00) >> 8) | ((value & 0x000000ff) << 8);
+
+    return result;
+}
+
+/**
+ * \brief   Reverse byte order (16 bit)
+ * \details Reverses the byte order in a 16-bit value
+ * and returns the signed 16-bit result.
+ * For example, 0x0080 becomes 0x8000.
+ * \param [in]    value  Value to reverse
+ * \return               Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+    int16_t result;
+    result = ((value & 0xff00) >> 8) | ((value & 0x00ff) << 8);
+    return result;
+}
+#endif
+/**
+ * \brief   Rotate Right in unsigned value (32 bit)
+ * \details Rotate Right (immediate) provides the value of
+ * the contents of a register rotated by a variable number of bits.
+ * \param [in]    op1  Value to rotate
+ * \param [in]    op2  Number of Bits to rotate(0-31)
+ * \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+    op2 = op2 & 0x1F;
+    if (op2 == 0U) {
+        return op1;
+    }
+    return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+/**
+ * \brief   Reverse bit order of value
+ * \details Reverses the bit order of the given value.
+ * \param [in]    value  Value to reverse
+ * \return               Reversed value
+ */
+#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
+#define __RBIT(value) __RV_BITREVI((value), 31)
+#else
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+    uint32_t result;
+    uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+    result = value; /* r will be reversed bits of v; first get LSB of v */
+    for (value >>= 1U; value != 0U; value >>= 1U) {
+        result <<= 1U;
+        result |= value & 1U;
+        s--;
+    }
+    result <<= s; /* shift when v's highest bits are zero */
+    return result;
+}
+#endif /* defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) */
+
+/**
+ * \brief   Count leading zeros
+ * \details Counts the number of leading zeros of a data value.
+ * \param [in]  data  Value to count the leading zeros
+ * \return             number of leading zeros in value
+ */
+#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
+#define __CLZ(data) __RV_CLZ32(data)
+#else
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data)
+{
+    uint8_t ret = 0;
+    uint32_t temp = ~data;
+    while (temp & 0x80000000) {
+        temp <<= 1;
+        ret++;
+    }
+    return ret;
+}
+#endif /* defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) */
+
+/** @} */ /* End of Doxygen Group NMSIS_Core_ARMCompatiable_Functions */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __CORE_COMPATIABLE_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_base.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_base.h
new file mode 100644
index 00000000..7bf1ad10
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_base.h
@@ -0,0 +1,1407 @@
+/*
+ * Copyright (c) 2019 Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CORE_FEATURE_BASE__
+#define __CORE_FEATURE_BASE__
+/*!
+ * @file     core_feature_base.h
+ * @brief    Base core feature API for Nuclei N/NX Core
+ */
+#include 
+#include "riscv_encoding.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup NMSIS_Core_Registers     Register Define and Type Definitions
+ * \brief   Type definitions and defines for core registers.
+ *
+ * @{
+ */
+#ifndef __RISCV_XLEN
+/** \brief Refer to the width of an integer register in bits(either 32 or 64) */
+#ifndef __riscv_xlen
+#define __RISCV_XLEN 32
+#else
+#define __RISCV_XLEN __riscv_xlen
+#endif
+#endif /* __RISCV_XLEN */
+
+/** \brief Type of Control and Status Register(CSR), depends on the XLEN defined in RISC-V */
+#if __RISCV_XLEN == 32
+typedef uint32_t rv_csr_t;
+#elif __RISCV_XLEN == 64
+typedef uint64_t rv_csr_t;
+#else
+typedef uint32_t rv_csr_t;
+#endif
+/** @} */ /* End of Doxygen Group NMSIS_Core_Registers */
+/**
+ * \defgroup NMSIS_Core_Base_Registers     Base Register Define and Type Definitions
+ * \ingroup NMSIS_Core_Registers
+ * \brief   Type definitions and defines for base core registers.
+ *
+ * @{
+ */
+/**
+ * \brief  Union type to access MISA CSR register.
+ */
+typedef union {
+    struct {
+        rv_csr_t a          : 1; /*!< bit:     0  Atomic extension */
+        rv_csr_t b          : 1; /*!< bit:     1  Tentatively reserved for Bit-Manipulation extension */
+        rv_csr_t c          : 1; /*!< bit:     2  Compressed extension */
+        rv_csr_t d          : 1; /*!< bit:     3  Double-precision floating-point extension */
+        rv_csr_t e          : 1; /*!< bit:     4  RV32E base ISA */
+        rv_csr_t f          : 1; /*!< bit:     5  Single-precision floating-point extension */
+        rv_csr_t g          : 1; /*!< bit:     6  Additional standard extensions present */
+        rv_csr_t h          : 1; /*!< bit:     7  Hypervisor extension */
+        rv_csr_t i          : 1; /*!< bit:     8  RV32I/64I/128I base ISA */
+        rv_csr_t j          : 1; /*!< bit:     9  Tentatively reserved for Dynamically Translated Languages extension */
+        rv_csr_t _reserved1 : 1; /*!< bit:     10 Reserved  */
+        rv_csr_t l          : 1; /*!< bit:     11 Tentatively reserved for Decimal Floating-Point extension  */
+        rv_csr_t m          : 1; /*!< bit:     12 Integer Multiply/Divide extension */
+        rv_csr_t n          : 1; /*!< bit:     13 User-level interrupts supported  */
+        rv_csr_t _reserved2 : 1; /*!< bit:     14 Reserved  */
+        rv_csr_t p          : 1; /*!< bit:     15 Tentatively reserved for Packed-SIMD extension  */
+        rv_csr_t q          : 1; /*!< bit:     16 Quad-precision floating-point extension  */
+        rv_csr_t _resreved3 : 1; /*!< bit:     17 Reserved  */
+        rv_csr_t s          : 1; /*!< bit:     18 Supervisor mode implemented  */
+        rv_csr_t t          : 1; /*!< bit:     19 Tentatively reserved for Transactional Memory extension  */
+        rv_csr_t u          : 1; /*!< bit:     20 User mode implemented  */
+        rv_csr_t v          : 1; /*!< bit:     21 Tentatively reserved for Vector extension  */
+        rv_csr_t _reserved4 : 1; /*!< bit:     22 Reserved  */
+        rv_csr_t x          : 1; /*!< bit:     23 Non-standard extensions present  */
+#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
+        rv_csr_t _reserved5 : 38; /*!< bit:     24..61 Reserved  */
+        rv_csr_t mxl        : 2;  /*!< bit:     62..63 Machine XLEN  */
+#else
+        rv_csr_t _reserved5 : 6; /*!< bit:     24..29 Reserved  */
+        rv_csr_t mxl        : 2; /*!< bit:     30..31 Machine XLEN  */
+#endif
+    } b;        /*!< Structure used for bit  access */
+    rv_csr_t d; /*!< Type      used for csr data access */
+} CSR_MISA_Type;
+
+/**
+ * \brief  Union type to access MSTATUS CSR register.
+ */
+typedef union {
+    struct {
+#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
+        rv_csr_t _reserved0 : 3;  /*!< bit:     0..2  Reserved */
+        rv_csr_t mie        : 1;  /*!< bit:     3  Machine mode interrupt enable flag */
+        rv_csr_t _reserved1 : 3;  /*!< bit:     4..6  Reserved */
+        rv_csr_t mpie       : 1;  /*!< bit:     7  mirror of MIE flag */
+        rv_csr_t _reserved2 : 3;  /*!< bit:     8..10  Reserved */
+        rv_csr_t mpp        : 2;  /*!< bit:     11..12 mirror of Privilege Mode */
+        rv_csr_t fs         : 2;  /*!< bit:     13..14 FS status flag */
+        rv_csr_t xs         : 2;  /*!< bit:     15..16 XS status flag */
+        rv_csr_t mprv       : 1;  /*!< bit:     Machine mode PMP */
+        rv_csr_t _reserved3 : 14; /*!< bit:     18..31 Reserved */
+        rv_csr_t uxl        : 2;  /*!< bit:     32..33 user mode xlen */
+        rv_csr_t _reserved6 : 29; /*!< bit:     34..62 Reserved  */
+        rv_csr_t sd         : 1;  /*!< bit:     Dirty status for XS or FS */
+#else
+        rv_csr_t _reserved0 : 1;  /*!< bit:     0  Reserved */
+        rv_csr_t sie        : 1;  /*!< bit:     1  supervisor interrupt enable flag */
+        rv_csr_t _reserved1 : 1;  /*!< bit:     2  Reserved */
+        rv_csr_t mie        : 1;  /*!< bit:     3  Machine mode interrupt enable flag */
+        rv_csr_t _reserved2 : 1;  /*!< bit:     4  Reserved */
+        rv_csr_t spie       : 1;  /*!< bit:     3  Supervisor Privilede mode interrupt enable flag */
+        rv_csr_t _reserved3 : 1;  /*!< bit:     Reserved */
+        rv_csr_t mpie       : 1;  /*!< bit:     mirror of MIE flag */
+        rv_csr_t _reserved4 : 3;  /*!< bit:     Reserved */
+        rv_csr_t mpp        : 2;  /*!< bit:     mirror of Privilege Mode */
+        rv_csr_t fs         : 2;  /*!< bit:     FS status flag */
+        rv_csr_t xs         : 2;  /*!< bit:     XS status flag */
+        rv_csr_t mprv       : 1;  /*!< bit:     Machine mode PMP */
+        rv_csr_t sum        : 1;  /*!< bit:     Supervisor Mode load and store protection */
+        rv_csr_t _reserved6 : 12; /*!< bit:     19..30 Reserved  */
+        rv_csr_t sd         : 1;  /*!< bit:     Dirty status for XS or FS */
+#endif
+    } b;        /*!< Structure used for bit  access */
+    rv_csr_t d; /*!< Type      used for csr data access */
+} CSR_MSTATUS_Type;
+
+/**
+ * \brief  Union type to access MTVEC CSR register.
+ */
+typedef union {
+    struct {
+        rv_csr_t mode : 6; /*!< bit:     0..5   interrupt mode control */
+#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
+        rv_csr_t addr : 58; /*!< bit:     6..63  mtvec address */
+#else
+        rv_csr_t addr : 26; /*!< bit:     6..31  mtvec address */
+#endif
+    } b;        /*!< Structure used for bit  access */
+    rv_csr_t d; /*!< Type      used for csr data access */
+} CSR_MTVEC_Type;
+
+/**
+ * \brief  Union type to access MCAUSE CSR register.
+ */
+typedef union {
+    struct {
+        rv_csr_t exccode    : 12; /*!< bit:     11..0  exception or interrupt code */
+        rv_csr_t _reserved0 : 4;  /*!< bit:     15..12  Reserved */
+        rv_csr_t mpil       : 8;  /*!< bit:     23..16  Previous interrupt level */
+        rv_csr_t _reserved1 : 3;  /*!< bit:     26..24  Reserved */
+        rv_csr_t mpie       : 1;  /*!< bit:     27  Interrupt enable flag before enter interrupt */
+        rv_csr_t mpp        : 2;  /*!< bit:     29..28  Privilede mode flag before enter interrupt */
+        rv_csr_t minhv      : 1;  /*!< bit:     30  Machine interrupt vector table */
+#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
+        rv_csr_t _reserved2 : 32; /*!< bit:     31..62  Reserved */
+        rv_csr_t interrupt  : 1;  /*!< bit:     63  trap type. 0 means exception and 1 means interrupt */
+#else
+        rv_csr_t interrupt : 1; /*!< bit:     31  trap type. 0 means exception and 1 means interrupt */
+#endif
+    } b;        /*!< Structure used for bit  access */
+    rv_csr_t d; /*!< Type      used for csr data access */
+} CSR_MCAUSE_Type;
+
+/**
+ * \brief  Union type to access MCOUNTINHIBIT CSR register.
+ */
+typedef union {
+    struct {
+        rv_csr_t cy         : 1; /*!< bit:     0     1 means disable mcycle counter */
+        rv_csr_t _reserved0 : 1; /*!< bit:     1     Reserved */
+        rv_csr_t ir         : 1; /*!< bit:     2     1 means disable minstret counter */
+#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
+        rv_csr_t _reserved1 : 61; /*!< bit:     3..63 Reserved */
+#else
+        rv_csr_t _reserved1 : 29; /*!< bit:     3..31 Reserved */
+#endif
+    } b;        /*!< Structure used for bit  access */
+    rv_csr_t d; /*!< Type      used for csr data access */
+} CSR_MCOUNTINHIBIT_Type;
+
+/**
+ * \brief  Union type to access MSUBM CSR register.
+ */
+typedef union {
+    struct {
+        rv_csr_t _reserved0 : 6; /*!< bit:     0..5   Reserved */
+        rv_csr_t typ        : 2; /*!< bit:     6..7   current trap type */
+        rv_csr_t ptyp       : 2; /*!< bit:     8..9   previous trap type */
+#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
+        rv_csr_t _reserved1 : 54; /*!< bit:     10..63 Reserved */
+#else
+        rv_csr_t _reserved1 : 22; /*!< bit:     10..31 Reserved */
+#endif
+    } b;        /*!< Structure used for bit  access */
+    rv_csr_t d; /*!< Type      used for csr data access */
+} CSR_MSUBM_Type;
+
+/**
+ * \brief  Union type to access MDCAUSE CSR register.
+ */
+typedef union {
+    struct {
+        rv_csr_t mdcause : 2;                   /*!< bit:     0..1   More detailed exception information as MCAUSE supplement */
+        rv_csr_t _reserved0 : __RISCV_XLEN - 2; /*!< bit:     2..XLEN-1 Reserved */
+    } b;                                        /*!< Structure used for bit  access */
+    rv_csr_t d;                                 /*!< Type      used for csr data access */
+} CSR_MDCAUSE_Type;
+
+/**
+ * \brief  Union type to access MMISC_CTRL CSR register.
+ */
+typedef union {
+    struct {
+        rv_csr_t _reserved0 : 3; /*!< bit:     0..2  Reserved */
+        rv_csr_t bpu        : 1; /*!< bit:     3     dynamic prediction enable flag */
+        rv_csr_t _reserved1 : 2; /*!< bit:     4..5  Reserved */
+        rv_csr_t misalign   : 1; /*!< bit:     6     misaligned access support flag */
+        rv_csr_t _reserved2 : 2; /*!< bit:     7..8  Reserved */
+        rv_csr_t nmi_cause  : 1; /*!< bit:     9     mnvec control and nmi mcase exccode */
+#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
+        rv_csr_t _reserved3 : 54; /*!< bit:     10..63 Reserved */
+#else
+        rv_csr_t _reserved3 : 22; /*!< bit:     10..31 Reserved */
+#endif
+    } b;        /*!< Structure used for bit  access */
+    rv_csr_t d; /*!< Type      used for csr data access */
+} CSR_MMISCCTRL_Type;
+
+typedef CSR_MMISCCTRL_Type CSR_MMISCCTL_Type;
+
+/**
+ * \brief  Union type to access MCACHE_CTL CSR register.
+ */
+typedef union {
+    struct {
+        rv_csr_t ic_en          : 1; /*!< I-Cache enable */
+        rv_csr_t ic_scpd_mod    : 1; /*!< Scratchpad mode, 0: Scratchpad as ICache Data RAM, 1: Scratchpad as ILM SRAM */
+        rv_csr_t ic_ecc_en      : 1; /*!< I-Cache ECC enable */
+        rv_csr_t ic_ecc_excp_en : 1; /*!< I-Cache 2bit ECC error exception enable */
+        rv_csr_t ic_rwtecc      : 1; /*!< Control I-Cache Tag Ram ECC code injection */
+        rv_csr_t ic_rwdecc      : 1; /*!< Control I-Cache Data Ram ECC code injection */
+        rv_csr_t _reserved0     : 10;
+        rv_csr_t dc_en          : 1; /*!< DCache enable */
+        rv_csr_t dc_ecc_en      : 1; /*!< D-Cache ECC enable */
+        rv_csr_t dc_ecc_excp_en : 1; /*!< D-Cache 2bit ECC error exception enable */
+        rv_csr_t dc_rwtecc      : 1; /*!< Control D-Cache Tag Ram ECC code injection */
+        rv_csr_t dc_rwdecc      : 1; /*!< Control D-Cache Data Ram ECC code injection */
+        rv_csr_t _reserved1 : __RISCV_XLEN - 21;
+    } b;        /*!< Structure used for bit  access */
+    rv_csr_t d; /*!< Type      used for csr data access */
+} CSR_MCACHECTL_Type;
+
+/**
+ * \brief  Union type to access MSAVESTATUS CSR register.
+ */
+typedef union {
+    struct {
+        rv_csr_t mpie1      : 1; /*!< bit:     0     interrupt enable flag of fisrt level NMI/exception nestting */
+        rv_csr_t mpp1       : 2; /*!< bit:     1..2  privilede mode of fisrt level NMI/exception nestting */
+        rv_csr_t _reserved0 : 3; /*!< bit:     3..5  Reserved */
+        rv_csr_t ptyp1      : 2; /*!< bit:     6..7  NMI/exception type of before first nestting */
+        rv_csr_t mpie2      : 1; /*!< bit:     8     interrupt enable flag of second level NMI/exception nestting */
+        rv_csr_t mpp2       : 2; /*!< bit:     9..10 privilede mode of second level NMI/exception nestting */
+        rv_csr_t _reserved1 : 3; /*!< bit:     11..13     Reserved */
+        rv_csr_t ptyp2      : 2; /*!< bit:     14..15     NMI/exception type of before second nestting */
+#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
+        rv_csr_t _reserved2 : 48; /*!< bit:     16..63 Reserved*/
+#else
+        rv_csr_t _reserved2 : 16; /*!< bit:     16..31 Reserved*/
+#endif
+    } b;        /*!< Structure used for bit  access */
+    rv_csr_t w; /*!< Type      used for csr data access */
+} CSR_MSAVESTATUS_Type;
+
+/**
+ * \brief  Union type to access MILM_CTL CSR register.
+ */
+typedef union {
+    struct {
+        rv_csr_t ilm_en          : 1;         /*!< ILM enable */
+        rv_csr_t ilm_ecc_en      : 1;         /*!< ILM ECC eanble */
+        rv_csr_t ilm_ecc_excp_en : 1;         /*!< ILM ECC exception enable */
+        rv_csr_t ilm_rwecc       : 1;         /*!< Control mecc_code write to ilm, simulate error injection */
+        rv_csr_t _reserved0      : 6;         /*!< Reserved */
+        rv_csr_t ilm_bpa : __RISCV_XLEN - 10; /*!< ILM base address */
+    } b;                                      /*!< Structure used for bit  access */
+    rv_csr_t d;                               /*!< Type      used for csr data access */
+} CSR_MILMCTL_Type;
+
+/**
+ * \brief  Union type to access MDLM_CTL CSR register.
+ */
+typedef union {
+    struct {
+        rv_csr_t dlm_en          : 1;         /*!< DLM enable */
+        rv_csr_t dlm_ecc_en      : 1;         /*!< DLM ECC eanble */
+        rv_csr_t dlm_ecc_excp_en : 1;         /*!< DLM ECC exception enable */
+        rv_csr_t dlm_rwecc       : 1;         /*!< Control mecc_code write to dlm, simulate error injection */
+        rv_csr_t _reserved0      : 6;         /*!< Reserved */
+        rv_csr_t dlm_bpa : __RISCV_XLEN - 10; /*!< DLM base address */
+    } b;                                      /*!< Structure used for bit  access */
+    rv_csr_t d;                               /*!< Type      used for csr data access */
+} CSR_MDLMCTL_Type;
+
+/**
+ * \brief  Union type to access MCFG_INFO CSR register.
+ */
+typedef union {
+    struct {
+        rv_csr_t tee    : 1; /*!< TEE present */
+        rv_csr_t ecc    : 1; /*!< ECC present */
+        rv_csr_t clic   : 1; /*!< CLIC present */
+        rv_csr_t plic   : 1; /*!< PLIC present */
+        rv_csr_t fio    : 1; /*!< FIO present */
+        rv_csr_t ppi    : 1; /*!< PPI present */
+        rv_csr_t nice   : 1; /*!< NICE present */
+        rv_csr_t ilm    : 1; /*!< ILM present */
+        rv_csr_t dlm    : 1; /*!< DLM present */
+        rv_csr_t icache : 1; /*!< ICache present */
+        rv_csr_t dcache : 1; /*!< DCache present */
+        rv_csr_t _reserved0 : __RISCV_XLEN - 11;
+    } b;        /*!< Structure used for bit  access */
+    rv_csr_t d; /*!< Type      used for csr data access */
+} CSR_MCFGINFO_Type;
+
+/**
+ * \brief  Union type to access MICFG_INFO CSR register.
+ */
+typedef union {
+    struct {
+        rv_csr_t set        : 4; /*!< I-Cache sets per way */
+        rv_csr_t way        : 3; /*!< I-Cache way */
+        rv_csr_t lsize      : 3; /*!< I-Cache line size */
+        rv_csr_t cache_ecc  : 1; /*!< I-Cache ECC present */
+        rv_csr_t _reserved0 : 5;
+        rv_csr_t lm_size    : 5; /*!< ILM size, need to be 2^n size */
+        rv_csr_t lm_xonly   : 1; /*!< ILM Execute only permission */
+        rv_csr_t lm_ecc     : 1; /*!< ILM ECC present */
+        rv_csr_t _reserved1 : __RISCV_XLEN - 23;
+    } b;        /*!< Structure used for bit  access */
+    rv_csr_t d; /*!< Type      used for csr data access */
+} CSR_MICFGINFO_Type;
+
+/**
+ * \brief  Union type to access MDCFG_INFO CSR register.
+ */
+typedef union {
+    struct {
+        rv_csr_t set        : 4; /*!< D-Cache sets per way */
+        rv_csr_t way        : 3; /*!< D-Cache way */
+        rv_csr_t lsize      : 3; /*!< D-Cache line size */
+        rv_csr_t cache_ecc  : 1; /*!< D-Cache ECC present */
+        rv_csr_t _reserved0 : 5;
+        rv_csr_t lm_size    : 5; /*!< DLM size, need to be 2^n size */
+        rv_csr_t lm_xonly   : 1; /*!< DLM Execute only permission */
+        rv_csr_t lm_ecc     : 1; /*!< DLM ECC present */
+        rv_csr_t _reserved1 : __RISCV_XLEN - 23;
+    } b;        /*!< Structure used for bit  access */
+    rv_csr_t d; /*!< Type      used for csr data access */
+} CSR_MDCFGINFO_Type;
+
+/**
+ * \brief  Union type to access MPPICFG_INFO CSR register.
+ */
+typedef union {
+    struct {
+        rv_csr_t _reserved0 : 1;              /*!< Reserved */
+        rv_csr_t ppi_size   : 5;              /*!< PPI size, need to be 2^n size */
+        rv_csr_t _reserved1 : 4;              /*!< Reserved */
+        rv_csr_t ppi_bpa : __RISCV_XLEN - 10; /*!< PPI base address */
+    } b;                                      /*!< Structure used for bit  access */
+    rv_csr_t d;                               /*!< Type      used for csr data access */
+} CSR_MPPICFGINFO_Type;
+
+/**
+ * \brief  Union type to access MFIOCFG_INFO CSR register.
+ */
+typedef union {
+    struct {
+        rv_csr_t _reserved0 : 1;              /*!< Reserved */
+        rv_csr_t fio_size   : 5;              /*!< FIO size, need to be 2^n size */
+        rv_csr_t _reserved1 : 4;              /*!< Reserved */
+        rv_csr_t fio_bpa : __RISCV_XLEN - 10; /*!< FIO base address */
+    } b;                                      /*!< Structure used for bit  access */
+    rv_csr_t d;                               /*!< Type      used for csr data access */
+} CSR_MFIOCFGINFO_Type;
+
+/**
+ * \brief  Union type to access MECC_LOCK CSR register.
+ */
+typedef union {
+    struct {
+        rv_csr_t ecc_lock : 1;                  /*!< RW permission, ECC Lock configure */
+        rv_csr_t _reserved0 : __RISCV_XLEN - 1; /*!< Reserved */
+    } b;                                        /*!< Structure used for bit  access */
+    rv_csr_t d;                                 /*!< Type      used for csr data access */
+} CSR_MECCLOCK_Type;
+
+/**
+ * \brief  Union type to access MECC_CODE CSR register.
+ */
+typedef union {
+    struct {
+        rv_csr_t code       : 9;                 /*!< Used to inject ECC check code */
+        rv_csr_t _reserved0 : 7;                 /*!< Reserved */
+        rv_csr_t ramid      : 5;                 /*!< Indicate 2bit ECC error, software can clear these bits */
+        rv_csr_t _reserved1 : 3;                 /*!< Reserved */
+        rv_csr_t sramid     : 5;                 /*!< Indicate 1bit ECC error, software can clear these bits */
+        rv_csr_t _reserved2 : __RISCV_XLEN - 29; /*!< Reserved */
+    } b;                                         /*!< Structure used for bit  access */
+    rv_csr_t d;                                  /*!< Type      used for csr data access */
+} CSR_MECCCODE_Type;
+
+/** @} */ /* End of Doxygen Group NMSIS_Core_Base_Registers */
+
+/* ###########################  Core Function Access  ########################### */
+/**
+ * \defgroup NMSIS_Core_CSR_Register_Access    Core CSR Register Access
+ * \ingroup  NMSIS_Core
+ * \brief    Functions to access the Core CSR Registers
+ * \details
+ *
+ * The following functions or macros provide access to Core CSR registers.
+ * - \ref NMSIS_Core_CSR_Encoding
+ * - \ref NMSIS_Core_CSR_Registers
+ *   @{
+ */
+
+#ifndef __ASSEMBLY__
+
+/**
+ * \brief CSR operation Macro for csrrw instruction.
+ * \details
+ * Read the content of csr register to __v,
+ * then write content of val into csr register, then return __v
+ * \param csr   CSR macro definition defined in
+ *              \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS
+ * \param val   value to store into the CSR register
+ * \return the CSR register value before written
+ */
+#define __RV_CSR_SWAP(csr, val)                           \
+    ({                                                    \
+        register rv_csr_t __v = (unsigned long)(val);     \
+        __ASM volatile("csrrw %0, " STRINGIFY(csr) ", %1" \
+                       : "=r"(__v)                        \
+                       : "rK"(__v)                        \
+                       : "memory");                       \
+        __v;                                              \
+    })
+
+/**
+ * \brief CSR operation Macro for csrr instruction.
+ * \details
+ * Read the content of csr register to __v and return it
+ * \param csr   CSR macro definition defined in
+ *              \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS
+ * \return the CSR register value
+ */
+#define __RV_CSR_READ(csr)                        \
+    ({                                            \
+        register rv_csr_t __v;                    \
+        __ASM volatile("csrr %0, " STRINGIFY(csr) \
+                       : "=r"(__v)                \
+                       :                          \
+                       : "memory");               \
+        __v;                                      \
+    })
+
+/**
+ * \brief CSR operation Macro for csrw instruction.
+ * \details
+ * Write the content of val to csr register
+ * \param csr   CSR macro definition defined in
+ *              \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS
+ * \param val   value to store into the CSR register
+ */
+#define __RV_CSR_WRITE(csr, val)                     \
+    ({                                               \
+        register rv_csr_t __v = (rv_csr_t)(val);     \
+        __ASM volatile("csrw " STRINGIFY(csr) ", %0" \
+                       :                             \
+                       : "rK"(__v)                   \
+                       : "memory");                  \
+    })
+
+/**
+ * \brief CSR operation Macro for csrrs instruction.
+ * \details
+ * Read the content of csr register to __v,
+ * then set csr register to be __v | val, then return __v
+ * \param csr   CSR macro definition defined in
+ *              \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS
+ * \param val   Mask value to be used wih csrrs instruction
+ * \return the CSR register value before written
+ */
+#define __RV_CSR_READ_SET(csr, val)                       \
+    ({                                                    \
+        register rv_csr_t __v = (rv_csr_t)(val);          \
+        __ASM volatile("csrrs %0, " STRINGIFY(csr) ", %1" \
+                       : "=r"(__v)                        \
+                       : "rK"(__v)                        \
+                       : "memory");                       \
+        __v;                                              \
+    })
+
+/**
+ * \brief CSR operation Macro for csrs instruction.
+ * \details
+ * Set csr register to be csr_content | val
+ * \param csr   CSR macro definition defined in
+ *              \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS
+ * \param val   Mask value to be used wih csrs instruction
+ */
+#define __RV_CSR_SET(csr, val)                       \
+    ({                                               \
+        register rv_csr_t __v = (rv_csr_t)(val);     \
+        __ASM volatile("csrs " STRINGIFY(csr) ", %0" \
+                       :                             \
+                       : "rK"(__v)                   \
+                       : "memory");                  \
+    })
+
+/**
+ * \brief CSR operation Macro for csrrc instruction.
+ * \details
+ * Read the content of csr register to __v,
+ * then set csr register to be __v & ~val, then return __v
+ * \param csr   CSR macro definition defined in
+ *              \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS
+ * \param val   Mask value to be used wih csrrc instruction
+ * \return the CSR register value before written
+ */
+#define __RV_CSR_READ_CLEAR(csr, val)                     \
+    ({                                                    \
+        register rv_csr_t __v = (rv_csr_t)(val);          \
+        __ASM volatile("csrrc %0, " STRINGIFY(csr) ", %1" \
+                       : "=r"(__v)                        \
+                       : "rK"(__v)                        \
+                       : "memory");                       \
+        __v;                                              \
+    })
+
+/**
+ * \brief CSR operation Macro for csrc instruction.
+ * \details
+ * Set csr register to be csr_content & ~val
+ * \param csr   CSR macro definition defined in
+ *              \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS
+ * \param val   Mask value to be used wih csrc instruction
+ */
+#define __RV_CSR_CLEAR(csr, val)                     \
+    ({                                               \
+        register rv_csr_t __v = (rv_csr_t)(val);     \
+        __ASM volatile("csrc " STRINGIFY(csr) ", %0" \
+                       :                             \
+                       : "rK"(__v)                   \
+                       : "memory");                  \
+    })
+#endif /* __ASSEMBLY__ */
+#if 0
+/**
+ * \brief   Enable IRQ Interrupts
+ * \details Enables IRQ interrupts by setting the MIE-bit in the MSTATUS Register.
+ * \remarks
+ *          Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+    __RV_CSR_SET(CSR_MSTATUS, MSTATUS_MIE);
+}
+
+/**
+ * \brief   Disable IRQ Interrupts
+ * \details Disables IRQ interrupts by clearing the MIE-bit in the MSTATUS Register.
+ * \remarks
+ *          Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+    __RV_CSR_CLEAR(CSR_MSTATUS, MSTATUS_MIE);
+}
+#endif
+/**
+ * \brief   Read whole 64 bits value of mcycle counter
+ * \details This function will read the whole 64 bits of MCYCLE register
+ * \return  The whole 64 bits value of MCYCLE
+ * \remarks It will work for both RV32 and RV64 to get full 64bits value of MCYCLE
+ */
+__STATIC_FORCEINLINE uint64_t __get_rv_cycle(void)
+{
+#if __RISCV_XLEN == 32
+    volatile uint32_t high0, low, high;
+    uint64_t full;
+
+    high0 = __RV_CSR_READ(CSR_MCYCLEH);
+    low = __RV_CSR_READ(CSR_MCYCLE);
+    high = __RV_CSR_READ(CSR_MCYCLEH);
+    if (high0 != high) {
+        low = __RV_CSR_READ(CSR_MCYCLE);
+    }
+    full = (((uint64_t)high) << 32) | low;
+    return full;
+#elif __RISCV_XLEN == 64
+    return (uint64_t)__RV_CSR_READ(CSR_MCYCLE);
+#else // TODO Need cover for XLEN=128 case in future
+    return (uint64_t)__RV_CSR_READ(CSR_MCYCLE);
+#endif
+}
+
+/**
+ * \brief   Read whole 64 bits value of machine instruction-retired counter
+ * \details This function will read the whole 64 bits of MINSTRET register
+ * \return  The whole 64 bits value of MINSTRET
+ * \remarks It will work for both RV32 and RV64 to get full 64bits value of MINSTRET
+ */
+__STATIC_FORCEINLINE uint64_t __get_rv_instret(void)
+{
+#if __RISCV_XLEN == 32
+    volatile uint32_t high0, low, high;
+    uint64_t full;
+
+    high0 = __RV_CSR_READ(CSR_MINSTRETH);
+    low = __RV_CSR_READ(CSR_MINSTRET);
+    high = __RV_CSR_READ(CSR_MINSTRETH);
+    if (high0 != high) {
+        low = __RV_CSR_READ(CSR_MINSTRET);
+    }
+    full = (((uint64_t)high) << 32) | low;
+    return full;
+#elif __RISCV_XLEN == 64
+    return (uint64_t)__RV_CSR_READ(CSR_MINSTRET);
+#else // TODO Need cover for XLEN=128 case in future
+    return (uint64_t)__RV_CSR_READ(CSR_MINSTRET);
+#endif
+}
+
+/**
+ * \brief   Read whole 64 bits value of real-time clock
+ * \details This function will read the whole 64 bits of TIME register
+ * \return  The whole 64 bits value of TIME CSR
+ * \remarks It will work for both RV32 and RV64 to get full 64bits value of TIME
+ * \attention only available when user mode available
+ */
+__STATIC_FORCEINLINE uint64_t __get_rv_time(void)
+{
+#if __RISCV_XLEN == 32
+    volatile uint32_t high0, low, high;
+    uint64_t full;
+
+    high0 = __RV_CSR_READ(CSR_TIMEH);
+    low = __RV_CSR_READ(CSR_TIME);
+    high = __RV_CSR_READ(CSR_TIMEH);
+    if (high0 != high) {
+        low = __RV_CSR_READ(CSR_TIME);
+    }
+    full = (((uint64_t)high) << 32) | low;
+    return full;
+#elif __RISCV_XLEN == 64
+    return (uint64_t)__RV_CSR_READ(CSR_TIME);
+#else // TODO Need cover for XLEN=128 case in future
+    return (uint64_t)__RV_CSR_READ(CSR_TIME);
+#endif
+}
+
+/** @} */ /* End of Doxygen Group NMSIS_Core_CSR_Register_Access */
+
+/* ###########################  CPU Intrinsic Functions ########################### */
+/**
+ * \defgroup NMSIS_Core_CPU_Intrinsic   Intrinsic Functions for CPU Intructions
+ * \ingroup  NMSIS_Core
+ * \brief    Functions that generate RISC-V CPU instructions.
+ * \details
+ *
+ * The following functions generate specified RISC-V instructions that cannot be directly accessed by compiler.
+ *   @{
+ */
+#if 0
+/**
+ * \brief   NOP Instruction
+ * \details
+ * No Operation does nothing.
+ * This instruction can be used for code alignment purposes.
+ */
+__STATIC_FORCEINLINE void __NOP(void)
+{
+    __ASM volatile("nop");
+}
+
+/**
+ * \brief   Wait For Interrupt
+ * \details
+ * Wait For Interrupt is is executed using CSR_WFE.WFE=0 and WFI instruction.
+ * It will suspends execution until interrupt, NMI or Debug happened.
+ * When Core is waked up by interrupt, if
+ * 1. mstatus.MIE == 1(interrupt enabled), Core will enter ISR code
+ * 2. mstatus.MIE == 0(interrupt disabled), Core will resume previous execution
+ */
+__STATIC_FORCEINLINE void __WFI(void)
+{
+    __RV_CSR_CLEAR(CSR_WFE, WFE_WFE);
+    __ASM volatile("wfi");
+}
+
+/**
+ * \brief   Wait For Event
+ * \details
+ * Wait For Event is executed using CSR_WFE.WFE=1 and WFI instruction.
+ * It will suspends execution until event, NMI or Debug happened.
+ * When Core is waked up, Core will resume previous execution
+ */
+__STATIC_FORCEINLINE void __WFE(void)
+{
+    __RV_CSR_SET(CSR_WFE, WFE_WFE);
+    __ASM volatile("wfi");
+    __RV_CSR_CLEAR(CSR_WFE, WFE_WFE);
+}
+
+/**
+ * \brief   Breakpoint Instruction
+ * \details
+ * Causes the processor to enter Debug state.
+ * Debug tools can use this to investigate system state
+ * when the instruction at a particular address is reached.
+ */
+__STATIC_FORCEINLINE void __EBREAK(void)
+{
+    __ASM volatile("ebreak");
+}
+
+/**
+ * \brief   Environment Call Instruction
+ * \details
+ * The ECALL instruction is used to make a service request to
+ * the execution environment.
+ */
+__STATIC_FORCEINLINE void __ECALL(void)
+{
+    __ASM volatile("ecall");
+}
+#endif
+/**
+ * \brief WFI Sleep Mode enumeration
+ */
+typedef enum WFI_SleepMode {
+    WFI_SHALLOW_SLEEP = 0, /*!< Shallow sleep mode, the core_clk will poweroff */
+    WFI_DEEP_SLEEP = 1     /*!< Deep sleep mode, the core_clk and core_ano_clk will poweroff */
+} WFI_SleepMode_Type;
+
+/**
+ * \brief   Set Sleep mode of WFI
+ * \details
+ * Set the SLEEPVALUE CSR register to control the
+ * WFI Sleep mode.
+ * \param[in] mode      The sleep mode to be set
+ */
+__STATIC_FORCEINLINE void __set_wfi_sleepmode(WFI_SleepMode_Type mode)
+{
+    __RV_CSR_WRITE(CSR_SLEEPVALUE, mode);
+}
+
+/**
+ * \brief   Send TX Event
+ * \details
+ * Set the CSR TXEVT to control send a TX Event.
+ * The Core will output signal tx_evt as output event signal.
+ */
+__STATIC_FORCEINLINE void __TXEVT(void)
+{
+    __RV_CSR_SET(CSR_TXEVT, 0x1);
+}
+
+/**
+ * \brief   Enable MCYCLE counter
+ * \details
+ * Clear the CY bit of MCOUNTINHIBIT to 0 to enable MCYCLE Counter
+ */
+__STATIC_FORCEINLINE void __enable_mcycle_counter(void)
+{
+    __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_CY);
+}
+
+/**
+ * \brief   Disable MCYCLE counter
+ * \details
+ * Set the CY bit of MCOUNTINHIBIT to 1 to disable MCYCLE Counter
+ */
+__STATIC_FORCEINLINE void __disable_mcycle_counter(void)
+{
+    __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_CY);
+}
+
+/**
+ * \brief   Enable MINSTRET counter
+ * \details
+ * Clear the IR bit of MCOUNTINHIBIT to 0 to enable MINSTRET Counter
+ */
+__STATIC_FORCEINLINE void __enable_minstret_counter(void)
+{
+    __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR);
+}
+
+/**
+ * \brief   Disable MINSTRET counter
+ * \details
+ * Set the IR bit of MCOUNTINHIBIT to 1 to disable MINSTRET Counter
+ */
+__STATIC_FORCEINLINE void __disable_minstret_counter(void)
+{
+    __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR);
+}
+
+/**
+ * \brief   Enable MCYCLE & MINSTRET counter
+ * \details
+ * Clear the IR and CY bit of MCOUNTINHIBIT to 1 to enable MINSTRET & MCYCLE Counter
+ */
+__STATIC_FORCEINLINE void __enable_all_counter(void)
+{
+    __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR | MCOUNTINHIBIT_CY);
+}
+
+/**
+ * \brief   Disable MCYCLE & MINSTRET counter
+ * \details
+ * Set the IR and CY bit of MCOUNTINHIBIT to 1 to disable MINSTRET & MCYCLE Counter
+ */
+__STATIC_FORCEINLINE void __disable_all_counter(void)
+{
+    __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR | MCOUNTINHIBIT_CY);
+}
+
+/**
+ * \brief Execute fence instruction, p -> pred, s -> succ
+ * \details
+ * the FENCE instruction ensures that all memory accesses from instructions preceding
+ * the fence in program order (the `predecessor set`) appear earlier in the global memory order than
+ * memory accesses from instructions appearing after the fence in program order (the `successor set`).
+ * For details, please refer to The RISC-V Instruction Set Manual
+ * \param p     predecessor set, such as iorw, rw, r, w
+ * \param s     successor set, such as iorw, rw, r, w
+ **/
+#define __FENCE(p, s) __ASM volatile("fence " #p "," #s \
+                                     :                  \
+                                     :                  \
+                                     : "memory")
+
+/**
+ * \brief   Fence.i Instruction
+ * \details
+ * The FENCE.I instruction is used to synchronize the instruction
+ * and data streams.
+ */
+__STATIC_FORCEINLINE void __FENCE_I(void)
+{
+    __ASM volatile("fence.i");
+}
+
+/** \brief Read & Write Memory barrier */
+#define __RWMB() __FENCE(iorw, iorw)
+
+/** \brief Read Memory barrier */
+#define __RMB() __FENCE(ir, ir)
+
+/** \brief Write Memory barrier */
+#define __WMB() __FENCE(ow, ow)
+
+/** \brief SMP Read & Write Memory barrier */
+#define __SMP_RWMB() __FENCE(rw, rw)
+
+/** \brief SMP Read Memory barrier */
+#define __SMP_RMB() __FENCE(r, r)
+
+/** \brief SMP Write Memory barrier */
+#define __SMP_WMB() __FENCE(w, w)
+
+/** \brief CPU relax for busy loop */
+#define __CPU_RELAX() __ASM volatile("" \
+                                     :  \
+                                     :  \
+                                     : "memory")
+
+/* ===== Load/Store Operations ===== */
+/**
+ * \brief  Load 8bit value from address (8 bit)
+ * \details Load 8 bit value.
+ * \param [in]    addr  Address pointer to data
+ * \return              value of type uint8_t at (*addr)
+ */
+__STATIC_FORCEINLINE uint8_t __LB(volatile void *addr)
+{
+    uint8_t result;
+
+    __ASM volatile("lb %0, 0(%1)"
+                   : "=r"(result)
+                   : "r"(addr));
+    return result;
+}
+
+/**
+ * \brief  Load 16bit value from address (16 bit)
+ * \details Load 16 bit value.
+ * \param [in]    addr  Address pointer to data
+ * \return              value of type uint16_t at (*addr)
+ */
+__STATIC_FORCEINLINE uint16_t __LH(volatile void *addr)
+{
+    uint16_t result;
+
+    __ASM volatile("lh %0, 0(%1)"
+                   : "=r"(result)
+                   : "r"(addr));
+    return result;
+}
+
+/**
+ * \brief  Load 32bit value from address (32 bit)
+ * \details Load 32 bit value.
+ * \param [in]    addr  Address pointer to data
+ * \return              value of type uint32_t at (*addr)
+ */
+__STATIC_FORCEINLINE uint32_t __LW(volatile void *addr)
+{
+    uint32_t result;
+
+    __ASM volatile("lw %0, 0(%1)"
+                   : "=r"(result)
+                   : "r"(addr));
+    return result;
+}
+
+#if __RISCV_XLEN != 32
+/**
+ * \brief  Load 64bit value from address (64 bit)
+ * \details Load 64 bit value.
+ * \param [in]    addr  Address pointer to data
+ * \return              value of type uint64_t at (*addr)
+ * \remarks RV64 only macro
+ */
+__STATIC_FORCEINLINE uint64_t __LD(volatile void *addr)
+{
+    uint64_t result;
+    __ASM volatile("ld %0, 0(%1)"
+                   : "=r"(result)
+                   : "r"(addr));
+    return result;
+}
+#endif
+
+/**
+ * \brief  Write 8bit value to address (8 bit)
+ * \details Write 8 bit value.
+ * \param [in]    addr  Address pointer to data
+ * \param [in]    val   Value to set
+ */
+__STATIC_FORCEINLINE void __SB(volatile void *addr, uint8_t val)
+{
+    __ASM volatile("sb %0, 0(%1)"
+                   :
+                   : "r"(val), "r"(addr));
+}
+
+/**
+ * \brief  Write 16bit value to address (16 bit)
+ * \details Write 16 bit value.
+ * \param [in]    addr  Address pointer to data
+ * \param [in]    val   Value to set
+ */
+__STATIC_FORCEINLINE void __SH(volatile void *addr, uint16_t val)
+{
+    __ASM volatile("sh %0, 0(%1)"
+                   :
+                   : "r"(val), "r"(addr));
+}
+
+/**
+ * \brief  Write 32bit value to address (32 bit)
+ * \details Write 32 bit value.
+ * \param [in]    addr  Address pointer to data
+ * \param [in]    val   Value to set
+ */
+__STATIC_FORCEINLINE void __SW(volatile void *addr, uint32_t val)
+{
+    __ASM volatile("sw %0, 0(%1)"
+                   :
+                   : "r"(val), "r"(addr));
+}
+
+#if __RISCV_XLEN != 32
+/**
+ * \brief  Write 64bit value to address (64 bit)
+ * \details Write 64 bit value.
+ * \param [in]    addr  Address pointer to data
+ * \param [in]    val   Value to set
+ */
+__STATIC_FORCEINLINE void __SD(volatile void *addr, uint64_t val)
+{
+    __ASM volatile("sd %0, 0(%1)"
+                   :
+                   : "r"(val), "r"(addr));
+}
+#endif
+
+/**
+ * \brief  Compare and Swap 32bit value using LR and SC
+ * \details Compare old value with memory, if identical,
+ * store new value in memory. Return the initial value in memory.
+ * Success is indicated by comparing return value with OLD.
+ * memory address, return 0 if successful, otherwise return !0
+ * \param [in]    addr      Address pointer to data, address need to be 4byte aligned
+ * \param [in]    oldval    Old value of the data in address
+ * \param [in]    newval    New value to be stored into the address
+ * \return  return the initial value in memory
+ */
+__STATIC_FORCEINLINE uint32_t __CAS_W(volatile uint32_t *addr, uint32_t oldval, uint32_t newval)
+{
+    register uint32_t result;
+    register uint32_t rc;
+
+    __ASM volatile(
+        "0:     lr.w %0, %2      \n"
+        "       bne  %0, %z3, 1f \n"
+        "       sc.w %1, %z4, %2 \n"
+        "       bnez %1, 0b      \n"
+        "1:\n"
+        : "=&r"(result), "=&r"(rc), "+A"(*addr)
+        : "r"(oldval), "r"(newval)
+        : "memory");
+    return result;
+}
+
+/**
+ * \brief  Atomic Swap 32bit value into memory
+ * \details Atomically swap new 32bit value into memory using amoswap.d.
+ * \param [in]    addr      Address pointer to data, address need to be 4byte aligned
+ * \param [in]    newval    New value to be stored into the address
+ * \return  return the original value in memory
+ */
+__STATIC_FORCEINLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval)
+{
+    register uint32_t result;
+
+    __ASM volatile("amoswap.w %0, %2, %1"
+                   : "=r"(result), "+A"(*addr)
+                   : "r"(newval)
+                   : "memory");
+    return result;
+}
+
+/**
+ * \brief  Atomic Add with 32bit value
+ * \details Atomically ADD 32bit value with value in memory using amoadd.d.
+ * \param [in]    addr   Address pointer to data, address need to be 4byte aligned
+ * \param [in]    value  value to be ADDed
+ * \return  return memory value + add value
+ */
+__STATIC_FORCEINLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value)
+{
+    register int32_t result;
+
+    __ASM volatile("amoadd.w %0, %2, %1"
+                   : "=r"(result), "+A"(*addr)
+                   : "r"(value)
+                   : "memory");
+    return *addr;
+}
+
+/**
+ * \brief  Atomic And with 32bit value
+ * \details Atomically AND 32bit value with value in memory using amoand.d.
+ * \param [in]    addr   Address pointer to data, address need to be 4byte aligned
+ * \param [in]    value  value to be ANDed
+ * \return  return memory value & and value
+ */
+__STATIC_FORCEINLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value)
+{
+    register int32_t result;
+
+    __ASM volatile("amoand.w %0, %2, %1"
+                   : "=r"(result), "+A"(*addr)
+                   : "r"(value)
+                   : "memory");
+    return *addr;
+}
+
+/**
+ * \brief  Atomic OR with 32bit value
+ * \details Atomically OR 32bit value with value in memory using amoor.d.
+ * \param [in]    addr   Address pointer to data, address need to be 4byte aligned
+ * \param [in]    value  value to be ORed
+ * \return  return memory value | and value
+ */
+__STATIC_FORCEINLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value)
+{
+    register int32_t result;
+
+    __ASM volatile("amoor.w %0, %2, %1"
+                   : "=r"(result), "+A"(*addr)
+                   : "r"(value)
+                   : "memory");
+    return *addr;
+}
+
+/**
+ * \brief  Atomic XOR with 32bit value
+ * \details Atomically XOR 32bit value with value in memory using amoxor.d.
+ * \param [in]    addr   Address pointer to data, address need to be 4byte aligned
+ * \param [in]    value  value to be XORed
+ * \return  return memory value ^ and value
+ */
+__STATIC_FORCEINLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value)
+{
+    register int32_t result;
+
+    __ASM volatile("amoxor.w %0, %2, %1"
+                   : "=r"(result), "+A"(*addr)
+                   : "r"(value)
+                   : "memory");
+    return *addr;
+}
+
+/**
+ * \brief  Atomic unsigned MAX with 32bit value
+ * \details Atomically unsigned max compare 32bit value with value in memory using amomaxu.d.
+ * \param [in]    addr   Address pointer to data, address need to be 4byte aligned
+ * \param [in]    value  value to be compared
+ * \return  return the bigger value
+ */
+__STATIC_FORCEINLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value)
+{
+    register uint32_t result;
+
+    __ASM volatile("amomaxu.w %0, %2, %1"
+                   : "=r"(result), "+A"(*addr)
+                   : "r"(value)
+                   : "memory");
+    return *addr;
+}
+
+/**
+ * \brief  Atomic signed MAX with 32bit value
+ * \details Atomically signed max compare 32bit value with value in memory using amomax.d.
+ * \param [in]    addr   Address pointer to data, address need to be 4byte aligned
+ * \param [in]    value  value to be compared
+ * \return the bigger value
+ */
+__STATIC_FORCEINLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value)
+{
+    register int32_t result;
+
+    __ASM volatile("amomax.w %0, %2, %1"
+                   : "=r"(result), "+A"(*addr)
+                   : "r"(value)
+                   : "memory");
+    return *addr;
+}
+
+/**
+ * \brief  Atomic unsigned MIN with 32bit value
+ * \details Atomically unsigned min compare 32bit value with value in memory using amominu.d.
+ * \param [in]    addr   Address pointer to data, address need to be 4byte aligned
+ * \param [in]    value  value to be compared
+ * \return the smaller value
+ */
+__STATIC_FORCEINLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value)
+{
+    register uint32_t result;
+
+    __ASM volatile("amominu.w %0, %2, %1"
+                   : "=r"(result), "+A"(*addr)
+                   : "r"(value)
+                   : "memory");
+    return *addr;
+}
+
+/**
+ * \brief  Atomic signed MIN with 32bit value
+ * \details Atomically signed min compare 32bit value with value in memory using amomin.d.
+ * \param [in]    addr   Address pointer to data, address need to be 4byte aligned
+ * \param [in]    value  value to be compared
+ * \return  the smaller value
+ */
+__STATIC_FORCEINLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value)
+{
+    register int32_t result;
+
+    __ASM volatile("amomin.w %0, %2, %1"
+                   : "=r"(result), "+A"(*addr)
+                   : "r"(value)
+                   : "memory");
+    return *addr;
+}
+
+#if __RISCV_XLEN == 64
+/**
+ * \brief  Compare and Swap 64bit value using LR and SC
+ * \details Compare old value with memory, if identical,
+ * store new value in memory. Return the initial value in memory.
+ * Success is indicated by comparing return value with OLD.
+ * memory address, return 0 if successful, otherwise return !0
+ * \param [in]    addr      Address pointer to data, address need to be 8byte aligned
+ * \param [in]    oldval    Old value of the data in address
+ * \param [in]    newval    New value to be stored into the address
+ * \return  return the initial value in memory
+ */
+__STATIC_FORCEINLINE uint64_t __CAS_D(volatile uint64_t *addr, uint64_t oldval, uint64_t newval)
+{
+    register uint64_t result;
+    register uint64_t rc;
+
+    __ASM volatile(
+        "0:     lr.d %0, %2      \n"
+        "       bne  %0, %z3, 1f \n"
+        "       sc.d %1, %z4, %2 \n"
+        "       bnez %1, 0b      \n"
+        "1:\n"
+        : "=&r"(result), "=&r"(rc), "+A"(*addr)
+        : "r"(oldval), "r"(newval)
+        : "memory");
+    return result;
+}
+
+/**
+ * \brief  Atomic Swap 64bit value into memory
+ * \details Atomically swap new 64bit value into memory using amoswap.d.
+ * \param [in]    addr      Address pointer to data, address need to be 8byte aligned
+ * \param [in]    newval    New value to be stored into the address
+ * \return  return the original value in memory
+ */
+__STATIC_FORCEINLINE uint64_t __AMOSWAP_D(volatile uint64_t *addr, uint64_t newval)
+{
+    register uint64_t result;
+
+    __ASM volatile("amoswap.d %0, %2, %1"
+                   : "=r"(result), "+A"(*addr)
+                   : "r"(newval)
+                   : "memory");
+    return result;
+}
+
+/**
+ * \brief  Atomic Add with 64bit value
+ * \details Atomically ADD 64bit value with value in memory using amoadd.d.
+ * \param [in]    addr   Address pointer to data, address need to be 8byte aligned
+ * \param [in]    value  value to be ADDed
+ * \return  return memory value + add value
+ */
+__STATIC_FORCEINLINE int64_t __AMOADD_D(volatile int64_t *addr, int64_t value)
+{
+    register int64_t result;
+
+    __ASM volatile("amoadd.d %0, %2, %1"
+                   : "=r"(result), "+A"(*addr)
+                   : "r"(value)
+                   : "memory");
+    return *addr;
+}
+
+/**
+ * \brief  Atomic And with 64bit value
+ * \details Atomically AND 64bit value with value in memory using amoand.d.
+ * \param [in]    addr   Address pointer to data, address need to be 8byte aligned
+ * \param [in]    value  value to be ANDed
+ * \return  return memory value & and value
+ */
+__STATIC_FORCEINLINE int64_t __AMOAND_D(volatile int64_t *addr, int64_t value)
+{
+    register int64_t result;
+
+    __ASM volatile("amoand.d %0, %2, %1"
+                   : "=r"(result), "+A"(*addr)
+                   : "r"(value)
+                   : "memory");
+    return *addr;
+}
+
+/**
+ * \brief  Atomic OR with 64bit value
+ * \details Atomically OR 64bit value with value in memory using amoor.d.
+ * \param [in]    addr   Address pointer to data, address need to be 8byte aligned
+ * \param [in]    value  value to be ORed
+ * \return  return memory value | and value
+ */
+__STATIC_FORCEINLINE int64_t __AMOOR_D(volatile int64_t *addr, int64_t value)
+{
+    register int64_t result;
+
+    __ASM volatile("amoor.d %0, %2, %1"
+                   : "=r"(result), "+A"(*addr)
+                   : "r"(value)
+                   : "memory");
+    return *addr;
+}
+
+/**
+ * \brief  Atomic XOR with 64bit value
+ * \details Atomically XOR 64bit value with value in memory using amoxor.d.
+ * \param [in]    addr   Address pointer to data, address need to be 8byte aligned
+ * \param [in]    value  value to be XORed
+ * \return  return memory value ^ and value
+ */
+__STATIC_FORCEINLINE int64_t __AMOXOR_D(volatile int64_t *addr, int64_t value)
+{
+    register int64_t result;
+
+    __ASM volatile("amoxor.d %0, %2, %1"
+                   : "=r"(result), "+A"(*addr)
+                   : "r"(value)
+                   : "memory");
+    return *addr;
+}
+
+/**
+ * \brief  Atomic unsigned MAX with 64bit value
+ * \details Atomically unsigned max compare 64bit value with value in memory using amomaxu.d.
+ * \param [in]    addr   Address pointer to data, address need to be 8byte aligned
+ * \param [in]    value  value to be compared
+ * \return  return the bigger value
+ */
+__STATIC_FORCEINLINE uint64_t __AMOMAXU_D(volatile uint64_t *addr, uint64_t value)
+{
+    register uint64_t result;
+
+    __ASM volatile("amomaxu.d %0, %2, %1"
+                   : "=r"(result), "+A"(*addr)
+                   : "r"(value)
+                   : "memory");
+    return *addr;
+}
+
+/**
+ * \brief  Atomic signed MAX with 64bit value
+ * \details Atomically signed max compare 64bit value with value in memory using amomax.d.
+ * \param [in]    addr   Address pointer to data, address need to be 8byte aligned
+ * \param [in]    value  value to be compared
+ * \return the bigger value
+ */
+__STATIC_FORCEINLINE int64_t __AMOMAX_D(volatile int64_t *addr, int64_t value)
+{
+    register int64_t result;
+
+    __ASM volatile("amomax.d %0, %2, %1"
+                   : "=r"(result), "+A"(*addr)
+                   : "r"(value)
+                   : "memory");
+    return *addr;
+}
+
+/**
+ * \brief  Atomic unsigned MIN with 64bit value
+ * \details Atomically unsigned min compare 64bit value with value in memory using amominu.d.
+ * \param [in]    addr   Address pointer to data, address need to be 8byte aligned
+ * \param [in]    value  value to be compared
+ * \return the smaller value
+ */
+__STATIC_FORCEINLINE uint64_t __AMOMINU_D(volatile uint64_t *addr, uint64_t value)
+{
+    register uint64_t result;
+
+    __ASM volatile("amominu.d %0, %2, %1"
+                   : "=r"(result), "+A"(*addr)
+                   : "r"(value)
+                   : "memory");
+    return *addr;
+}
+
+/**
+ * \brief  Atomic signed MIN with 64bit value
+ * \details Atomically signed min compare 64bit value with value in memory using amomin.d.
+ * \param [in]    addr   Address pointer to data, address need to be 8byte aligned
+ * \param [in]    value  value to be compared
+ * \return  the smaller value
+ */
+__STATIC_FORCEINLINE int64_t __AMOMIN_D(volatile int64_t *addr, int64_t value)
+{
+    register int64_t result;
+
+    __ASM volatile("amomin.d %0, %2, %1"
+                   : "=r"(result), "+A"(*addr)
+                   : "r"(value)
+                   : "memory");
+    return *addr;
+}
+#endif /* __RISCV_XLEN == 64  */
+
+/** @} */ /* End of Doxygen Group NMSIS_Core_CPU_Intrinsic */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __CORE_FEATURE_BASE__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_cache.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_cache.h
new file mode 100644
index 00000000..8652337d
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_cache.h
@@ -0,0 +1,1391 @@
+/*
+ * Copyright (c) 2019 Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __CORE_FEATURE_CACHE_H__
+#define __CORE_FEATURE_CACHE_H__
+/*!
+ * @file     core_feature_cache.h
+ * @brief    Cache feature API header file for Nuclei N/NX Core
+ */
+/*
+ * Cache Feature Configuration Macro:
+ * 1. __ICACHE_PRESENT:  Define whether I-Cache Unit is present or not.
+ *   * 0: Not present
+ *   * 1: Present
+ * 1. __DCACHE_PRESENT:  Define whether D-Cache Unit is present or not.
+ *   * 0: Not present
+ *   * 1: Present
+ */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if (defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1)) \
+    || (defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1))
+
+/* ##########################  Cache functions  #################################### */
+/**
+ * \defgroup NMSIS_Core_Cache       Cache Functions
+ * \brief    Functions that configure Instruction and Data Cache.
+ * @{
+ *
+ * Nuclei provide Cache Control and Maintainence(CCM) for software to control and maintain
+ * the internal L1 I/D Cache of the RISC-V Core, software can manage the cache flexibly to
+ * meet the actual application scenarios.
+ *
+ * The CCM operations have 3 types: by single address, by all and flush pipeline.
+ * The CCM operations are done via CSR registers, M/S/U mode has its own CSR registers to
+ * do CCM operations. By default, CCM operations are not allowed in S/U mode, you can execute
+ * \ref EnableSUCCM in M-Mode to enable it.
+ *
+ * * API names started with M, such as \ref MInvalICacheLine must be called in M-Mode only.
+ * * API names started with S, such as \ref SInvalICacheLine should be called in S-Mode.
+ * * API names started with U, such as \ref UInvalICacheLine should be called in U-Mode.
+ *
+ */
+
+
+/**
+ * \brief Cache CCM Operation Fail Info
+ */
+typedef enum CCM_OP_FINFO {
+    CCM_OP_SUCCESS = 0x0,               /*!< Lock Succeed */
+    CCM_OP_EXCEED_ERR = 0x1,            /*!< Exceed the the number of lockable ways(N-Way I/D-Cache, lockable is N-1) */
+    CCM_OP_PERM_CHECK_ERR = 0x2,        /*!< PMP/sPMP/Page-Table X(I-Cache)/R(D-Cache) permission check failed, or belong to Device/Non-Cacheable address range */
+    CCM_OP_REFILL_BUS_ERR = 0x3,        /*!< Refill has Bus Error */
+    CCM_OP_ECC_ERR = 0x4                /*!< ECC Error */
+} CCM_OP_FINFO_Type;
+
+/**
+ * \brief Cache CCM Command Types
+ */
+typedef enum CCM_CMD {
+    CCM_DC_INVAL = 0x0,                 /*!< Unlock and invalidate D-Cache line specified by CSR CCM_XBEGINADDR */
+    CCM_DC_WB = 0x1,                    /*!< Flush the specific D-Cache line specified by CSR CCM_XBEGINADDR */
+    CCM_DC_WBINVAL = 0x2,               /*!< Unlock, flush and invalidate the specific D-Cache line specified by CSR CCM_XBEGINADDR */
+    CCM_DC_LOCK = 0x3,                  /*!< Lock the specific D-Cache line specified by CSR CCM_XBEGINADDR */
+    CCM_DC_UNLOCK = 0x4,                /*!< Unlock the specific D-Cache line specified by CSR CCM_XBEGINADDR */
+    CCM_DC_WBINVAL_ALL = 0x6,           /*!< Unlock and flush and invalidate all the valid and dirty D-Cache lines */
+    CCM_DC_WB_ALL = 0x7,                /*!< Flush all the valid and dirty D-Cache lines */
+    CCM_DC_INVAL_ALL = 0x17,            /*!< Unlock and invalidate all the D-Cache lines */
+    CCM_IC_INVAL = 0x8,                 /*!< Unlock and invalidate I-Cache line specified by CSR CCM_XBEGINADDR */
+    CCM_IC_LOCK = 0xb,                  /*!< Lock the specific I-Cache line specified by CSR CCM_XBEGINADDR */
+    CCM_IC_UNLOCK = 0xc,                /*!< Unlock the specific I-Cache line specified by CSR CCM_XBEGINADDR */
+    CCM_IC_INVAL_ALL = 0xd              /*!< Unlock and invalidate all the I-Cache lines */
+} CCM_CMD_Type;
+
+/**
+ * \brief Cache Information Type
+ */
+typedef struct CacheInfo {
+    uint32_t linesize;                  /*!< Cache Line size in bytes */
+    uint32_t ways;                      /*!< Cache ways */
+    uint32_t setperway;                 /*!< Cache set per way */
+    uint32_t size;                      /*!< Cache total size in bytes */
+} CacheInfo_Type;
+
+#define CCM_SUEN_SUEN_Pos               0U                              /*!< CSR CCM_SUEN: SUEN bit Position */
+#define CCM_SUEN_SUEN_Msk               (1UL << CCM_SUEN_SUEN_Pos)      /*!< CSR CCM_SUEN: SUEN Mask */
+
+/**
+ * \brief  Enable CCM operation in Supervisor/User Mode
+ * \details
+ * This function enable CCM operation in Supervisor/User Mode.
+ * If enabled, CCM operations in supervisor/user mode will
+ * be allowed.
+ * \remarks
+ * - This function can be called in M-Mode only.
+ * \sa
+ * - \ref DisableSUCCM
+*/
+__STATIC_FORCEINLINE void EnableSUCCM(void)
+{
+    __RV_CSR_SET(CSR_CCM_SUEN, CCM_SUEN_SUEN_Msk);
+}
+
+/**
+ * \brief  Disable CCM operation in Supervisor/User Mode
+ * \details
+ * This function disable CCM operation in Supervisor/User Mode.
+ * If not enabled, CCM operations in supervisor/user mode will
+ * trigger a *illegal intruction* exception.
+ * \remarks
+ * - This function can be called in M-Mode only.
+ * \sa
+ * - \ref EnableSUCCM
+*/
+__STATIC_FORCEINLINE void DisableSUCCM(void)
+{
+    __RV_CSR_CLEAR(CSR_CCM_SUEN, CCM_SUEN_SUEN_Msk);
+}
+
+/**
+ * \brief  Flush pipeline after CCM operation
+ * \details
+ * This function is used to flush pipeline after CCM operations
+ * on Cache, it will ensure latest instructions or data can be
+ * seen by pipeline.
+ * \remarks
+ * - This function can be called in M/S/U-Mode only.
+*/
+__STATIC_FORCEINLINE void FlushPipeCCM(void)
+{
+    __RV_CSR_WRITE(CSR_CCM_FPIPE, 0x1);
+}
+/** @} */ /* End of Doxygen Group NMSIS_Core_Cache */
+#endif
+
+#if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1)
+
+/**
+ * \defgroup NMSIS_Core_ICache      I-Cache Functions
+ * \ingroup  NMSIS_Core_Cache
+ * \brief    Functions that configure Instruction Cache.
+ * @{
+ */
+
+/**
+ * \brief  Enable ICache
+ * \details
+ * This function enable I-Cache
+ * \remarks
+ * - This function can be called in M-Mode only.
+ * - This \ref CSR_MCACHE_CTL register control I Cache enable.
+ * \sa
+ * - \ref DisableICache
+*/
+__STATIC_FORCEINLINE void EnableICache(void)
+{
+    __RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE);
+}
+
+/**
+ * \brief  Disable ICache
+ * \details
+ * This function Disable I-Cache
+ * \remarks
+ * - This function can be called in M-Mode only.
+ * - This \ref CSR_MCACHE_CTL register control I Cache enable.
+ * \sa
+ * - \ref EnableICache
+ */
+__STATIC_FORCEINLINE void DisableICache(void)
+{
+    __RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE);
+}
+
+/**
+ * \brief  Get I-Cache Information
+ * \details
+ * This function get I-Cache Information
+ * \remarks
+ * - This function can be called in M-Mode only.
+ * - You can use this function in combination with cache lines operations
+ * \sa
+ * - \ref GetDCacheInfo
+ */
+__STATIC_FORCEINLINE int32_t GetICacheInfo(CacheInfo_Type *info)
+{
+    if (info == NULL) {
+        return -1;
+    }
+    CSR_MICFGINFO_Type csr_ccfg = (CSR_MICFGINFO_Type)__RV_CSR_READ(CSR_MICFG_INFO);
+    uint32_t info->setperway = (1 << csr_ccfg.b.set) << 3;
+    uint32_t info->ways = (1 + csr_ccfg.b.way);
+    if (csr_ccfg.b.lsize == 0) {
+        info->linesize = 0;
+    } else {
+        info->linesize = (1 << (csr_ccfg.b.lsize - 1)) << 3;
+    }
+    info->size = info->setperway * info->ways * info->linesize;
+    return 0;
+}
+
+/**
+ * \brief  Get D-Cache Information
+ * \details
+ * This function get D-Cache Information
+ * \remarks
+ * - This function can be called in M-Mode only.
+ * - You can use this function in combination with cache lines operations
+ * \sa
+ * - \ref GetICacheInfo
+ */
+__STATIC_FORCEINLINE int32_t GetDCacheInfo(CacheInfo_Type *info)
+{
+    if (info == NULL) {
+        return -1;
+    }
+    CSR_MDCFGINFO_Type csr_ccfg = (CSR_MDCFGINFO_Type)__RV_CSR_READ(CSR_MDCFG_INFO);
+    uint32_t info->setperway = (1 << csr_ccfg.b.set) << 3;
+    uint32_t info->ways = (1 + csr_ccfg.b.way);
+    if (csr_ccfg.b.lsize == 0) {
+        info->linesize = 0;
+    } else {
+        info->linesize = (1 << (csr_ccfg.b.lsize - 1)) << 3;
+    }
+    info->size = info->setperway * info->ways * info->linesize;
+    return 0;
+}
+
+/**
+ * \brief  Invalidate one I-Cache line specified by address in M-Mode
+ * \details
+ * This function unlock and invalidate one I-Cache line specified
+ * by the address.
+ * Command \ref CCM_IC_INVAL is written to CSR \ref CSR_CCM_MCOMMAND.
+ * \remarks
+ * This function must be executed in M-Mode only.
+ * \param [in]    addr    start address to be invalidated
+ */
+__STATIC_FORCEINLINE void MInvalICacheLine(unsigned long addr)
+{
+    __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
+    __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_IC_INVAL);
+}
+
+/**
+ * \brief  Invalidate several I-Cache lines specified by address in M-Mode
+ * \details
+ * This function unlock and invalidate several I-Cache lines specified
+ * by the address and line count.
+ * Command \ref CCM_IC_INVAL is written to CSR \ref CSR_CCM_MCOMMAND.
+ * \remarks
+ * This function must be executed in M-Mode only.
+ * \param [in]    addr    start address to be invalidated
+ * \param [in]    cnt     count of cache lines to be invalidated
+ */
+__STATIC_FORCEINLINE void MInvalICacheLines(unsigned long addr, unsigned long cnt)
+{
+    if (cnt > 0) {
+        unsigned long i;
+        __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
+        for (i = 0; i < cnt; i++) {
+            __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_IC_INVAL);
+        }
+    }
+}
+
+/**
+ * \brief  Invalidate one I-Cache line specified by address in S-Mode
+ * \details
+ * This function unlock and invalidate one I-Cache line specified
+ * by the address.
+ * Command \ref CCM_IC_INVAL is written to CSR \ref CSR_CCM_SCOMMAND.
+ * \remarks
+ * This function must be executed in M/S-Mode only.
+ * \param [in]    addr    start address to be invalidated
+ */
+__STATIC_FORCEINLINE void SInvalICacheLine(unsigned long addr)
+{
+    __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
+    __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_IC_INVAL);
+}
+
+/**
+ * \brief  Invalidate several I-Cache lines specified by address in S-Mode
+ * \details
+ * This function unlock and invalidate several I-Cache lines specified
+ * by the address and line count.
+ * Command \ref CCM_IC_INVAL is written to CSR \ref CSR_CCM_SCOMMAND.
+ * \remarks
+ * This function must be executed in M/S-Mode only.
+ * \param [in]    addr    start address to be invalidated
+ * \param [in]    cnt     count of cache lines to be invalidated
+ */
+__STATIC_FORCEINLINE void SInvalICacheLines(unsigned long addr, unsigned long cnt)
+{
+    if (cnt > 0) {
+        unsigned long i;
+        __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
+        for (i = 0; i < cnt; i++) {
+            __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_IC_INVAL);
+        }
+    }
+}
+
+/**
+ * \brief  Invalidate one I-Cache line specified by address in U-Mode
+ * \details
+ * This function unlock and invalidate one I-Cache line specified
+ * by the address.
+ * Command \ref CCM_IC_INVAL is written to CSR \ref CSR_CCM_UCOMMAND.
+ * \remarks
+ * This function must be executed in M/S/U-Mode only.
+ * \param [in]    addr    start address to be invalidated
+ */
+__STATIC_FORCEINLINE void UInvalICacheLine(unsigned long addr)
+{
+    __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
+    __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_IC_INVAL);
+}
+
+/**
+ * \brief  Invalidate several I-Cache lines specified by address in U-Mode
+ * \details
+ * This function unlock and invalidate several I-Cache lines specified
+ * by the address and line count.
+ * Command \ref CCM_IC_INVAL is written to CSR \ref CSR_CCM_UCOMMAND.
+ * \remarks
+ * This function must be executed in M/S/U-Mode only.
+ * \param [in]    addr    start address to be invalidated
+ * \param [in]    cnt     count of cache lines to be invalidated
+ */
+__STATIC_FORCEINLINE void UInvalICacheLines(unsigned long addr, unsigned long cnt)
+{
+    if (cnt > 0) {
+        unsigned long i;
+        __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
+        for (i = 0; i < cnt; i++) {
+            __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_IC_INVAL);
+        }
+    }
+}
+
+/**
+ * \brief  Lock one I-Cache line specified by address in M-Mode
+ * \details
+ * This function lock one I-Cache line specified by the address.
+ * Command \ref CCM_IC_LOCK is written to CSR \ref CSR_CCM_MCOMMAND.
+ * \remarks
+ * This function must be executed in M-Mode only.
+ * \param [in]    addr    start address to be locked
+ * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO
+ */
+__STATIC_FORCEINLINE unsigned long MLockICacheLine(unsigned long addr)
+{
+    __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
+    __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_IC_LOCK);
+    return __RV_CSR_READ(CSR_CCM_MDATA);
+}
+
+/**
+ * \brief  Lock several I-Cache lines specified by address in M-Mode
+ * \details
+ * This function lock several I-Cache lines specified by the address
+ * and line count.
+ * Command \ref CCM_IC_LOCK is written to CSR \ref CSR_CCM_MCOMMAND.
+ * \remarks
+ * This function must be executed in M-Mode only.
+ * \param [in]    addr    start address to be locked
+ * \param [in]    cnt     count of cache lines to be locked
+ * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO
+ */
+__STATIC_FORCEINLINE unsigned long MLockICacheLines(unsigned long addr, unsigned long cnt)
+{
+    if (cnt > 0) {
+        unsigned long i;
+        __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
+        for (i = 0; i < cnt; i++) {
+            __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_IC_LOCK);
+        }
+        return __RV_CSR_READ(CSR_CCM_MDATA);
+    } else {
+        return 0;
+    }
+}
+
+/**
+ * \brief  Lock one I-Cache line specified by address in S-Mode
+ * \details
+ * This function lock one I-Cache line specified by the address.
+ * Command \ref CCM_IC_LOCK is written to CSR \ref CSR_CCM_SCOMMAND.
+ * \remarks
+ * This function must be executed in M/S-Mode only.
+ * \param [in]    addr    start address to be locked
+ * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO
+ */
+__STATIC_FORCEINLINE unsigned long SLockICacheLine(unsigned long addr)
+{
+    __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
+    __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_IC_LOCK);
+    return __RV_CSR_READ(CSR_CCM_SDATA);
+}
+
+/**
+ * \brief  Lock several I-Cache lines specified by address in S-Mode
+ * \details
+ * This function lock several I-Cache lines specified by the address
+ * and line count.
+ * Command \ref CCM_IC_LOCK is written to CSR \ref CSR_CCM_SCOMMAND.
+ * \remarks
+ * This function must be executed in M/S-Mode only.
+ * \param [in]    addr    start address to be locked
+ * \param [in]    cnt     count of cache lines to be locked
+ * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO
+ */
+__STATIC_FORCEINLINE unsigned long SLockICacheLines(unsigned long addr, unsigned long cnt)
+{
+    if (cnt > 0) {
+        unsigned long i;
+        __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
+        for (i = 0; i < cnt; i++) {
+            __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_IC_LOCK);
+        }
+        return __RV_CSR_READ(CSR_CCM_SDATA);
+    } else {
+        return 0;
+    }
+}
+
+/**
+ * \brief  Lock one I-Cache line specified by address in U-Mode
+ * \details
+ * This function lock one I-Cache line specified by the address.
+ * Command \ref CCM_IC_LOCK is written to CSR \ref CSR_CCM_UCOMMAND.
+ * \remarks
+ * This function must be executed in M/S/U-Mode only.
+ * \param [in]    addr    start address to be locked
+ * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO
+ */
+__STATIC_FORCEINLINE unsigned long ULockICacheLine(unsigned long addr)
+{
+    __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
+    __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_IC_LOCK);
+    return __RV_CSR_READ(CSR_CCM_UDATA);
+}
+
+/**
+ * \brief  Lock several I-Cache lines specified by address in U-Mode
+ * \details
+ * This function lock several I-Cache lines specified by the address
+ * and line count.
+ * Command \ref CCM_IC_LOCK is written to CSR \ref CSR_CCM_UCOMMAND.
+ * \remarks
+ * This function must be executed in M/S/U-Mode only.
+ * \param [in]    addr    start address to be locked
+ * \param [in]    cnt     count of cache lines to be locked
+ * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO
+ */
+__STATIC_FORCEINLINE unsigned long ULockICacheLines(unsigned long addr, unsigned long cnt)
+{
+    if (cnt > 0) {
+        unsigned long i;
+        __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
+        for (i = 0; i < cnt; i++) {
+            __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_IC_LOCK);
+        }
+        return __RV_CSR_READ(CSR_CCM_UDATA);
+    } else {
+        return 0;
+    }
+}
+
+/**
+ * \brief  Unlock one I-Cache line specified by address in M-Mode
+ * \details
+ * This function unlock one I-Cache line specified by the address.
+ * Command \ref CCM_IC_UNLOCK is written to CSR \ref CSR_CCM_MCOMMAND.
+ * \remarks
+ * This function must be executed in M-Mode only.
+ * \param [in]    addr    start address to be unlocked
+ */
+__STATIC_FORCEINLINE void MUnlockICacheLine(unsigned long addr)
+{
+    __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
+    __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_IC_UNLOCK);
+}
+
+/**
+ * \brief  Unlock several I-Cache lines specified by address in M-Mode
+ * \details
+ * This function unlock several I-Cache lines specified
+ * by the address and line count.
+ * Command \ref CCM_IC_UNLOCK is written to CSR \ref CSR_CCM_MCOMMAND.
+ * \remarks
+ * This function must be executed in M-Mode only.
+ * \param [in]    addr    start address to be unlocked
+ * \param [in]    cnt     count of cache lines to be unlocked
+ */
+__STATIC_FORCEINLINE void MUnlockICacheLines(unsigned long addr, unsigned long cnt)
+{
+    if (cnt > 0) {
+        unsigned long i;
+        __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
+        for (i = 0; i < cnt; i++) {
+            __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_IC_UNLOCK);
+        }
+    }
+}
+
+/**
+ * \brief  Unlock one I-Cache line specified by address in S-Mode
+ * \details
+ * This function unlock one I-Cache line specified by the address.
+ * Command \ref CCM_IC_UNLOCK is written to CSR \ref CSR_CCM_SCOMMAND.
+ * \remarks
+ * This function must be executed in M/S-Mode only.
+ * \param [in]    addr    start address to be unlocked
+ */
+__STATIC_FORCEINLINE void SUnlockICacheLine(unsigned long addr)
+{
+    __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
+    __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_IC_UNLOCK);
+}
+
+/**
+ * \brief  Unlock several I-Cache lines specified by address in S-Mode
+ * \details
+ * This function unlock several I-Cache lines specified
+ * by the address and line count.
+ * Command \ref CCM_IC_UNLOCK is written to CSR \ref CSR_CCM_SCOMMAND.
+ * \remarks
+ * This function must be executed in M/S-Mode only.
+ * \param [in]    addr    start address to be unlocked
+ * \param [in]    cnt     count of cache lines to be unlocked
+ */
+__STATIC_FORCEINLINE void SUnlockICacheLines(unsigned long addr, unsigned long cnt)
+{
+    if (cnt > 0) {
+        unsigned long i;
+        __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
+        for (i = 0; i < cnt; i++) {
+            __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_IC_UNLOCK);
+        }
+    }
+}
+
+/**
+ * \brief  Unlock one I-Cache line specified by address in U-Mode
+ * \details
+ * This function unlock one I-Cache line specified by the address.
+ * Command \ref CCM_IC_UNLOCK is written to CSR \ref CSR_CCM_UCOMMAND.
+ * \remarks
+ * This function must be executed in M/S/U-Mode only.
+ * \param [in]    addr    start address to be unlocked
+ */
+__STATIC_FORCEINLINE void UUnlockICacheLine(unsigned long addr)
+{
+    __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
+    __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_IC_UNLOCK);
+}
+
+/**
+ * \brief  Unlock several I-Cache lines specified by address in U-Mode
+ * \details
+ * This function unlock several I-Cache lines specified
+ * by the address and line count.
+ * Command \ref CCM_IC_UNLOCK is written to CSR \ref CSR_CCM_UCOMMAND.
+ * \remarks
+ * This function must be executed in M/S/U-Mode only.
+ * \param [in]    addr    start address to be unlocked
+ * \param [in]    cnt     count of cache lines to be unlocked
+ */
+__STATIC_FORCEINLINE void UUnlockICacheLines(unsigned long addr, unsigned long cnt)
+{
+    if (cnt > 0) {
+        unsigned long i;
+        __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
+        for (i = 0; i < cnt; i++) {
+            __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_IC_UNLOCK);
+        }
+    }
+}
+
+/**
+ * \brief  Invalidate all I-Cache lines in M-Mode
+ * \details
+ * This function invalidate all I-Cache lines.
+ * Command \ref CCM_IC_INVAL_ALL is written to CSR \ref CSR_CCM_MCOMMAND.
+ * \remarks
+ * This function must be executed in M-Mode only.
+ * \param [in]    addr    start address to be invalidated
+ */
+__STATIC_FORCEINLINE void MInvalICache(void)
+{
+    __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_IC_INVAL_ALL);
+}
+
+/**
+ * \brief  Invalidate all I-Cache lines in S-Mode
+ * \details
+ * This function invalidate all I-Cache lines.
+ * Command \ref CCM_IC_INVAL_ALL is written to CSR \ref CSR_CCM_SCOMMAND.
+ * \remarks
+ * This function must be executed in M/S-Mode only.
+ * \param [in]    addr    start address to be invalidated
+ */
+__STATIC_FORCEINLINE void SInvalICache(void)
+{
+    __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_IC_INVAL_ALL);
+}
+
+/**
+ * \brief  Invalidate all I-Cache lines in U-Mode
+ * \details
+ * This function invalidate all I-Cache lines.
+ * Command \ref CCM_IC_INVAL_ALL is written to CSR \ref CSR_CCM_UCOMMAND.
+ * \remarks
+ * This function must be executed in M/S/U-Mode only.
+ * \param [in]    addr    start address to be invalidated
+ */
+__STATIC_FORCEINLINE void UInvalICache(void)
+{
+    __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_IC_INVAL_ALL);
+}
+
+/** @} */ /* End of Doxygen Group NMSIS_Core_ICache */
+#endif /* defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1) */
+
+#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1)
+/**
+ * \defgroup NMSIS_Core_DCache      D-Cache Functions
+ * \ingroup  NMSIS_Core_Cache
+ * \brief    Functions that configure Data Cache.
+ * @{
+ */
+/**
+ * \brief  Enable DCache
+ * \details
+ * This function enable D-Cache
+ * \remarks
+ * - This function can be called in M-Mode only.
+ * - This \ref CSR_MCACHE_CTL register control D Cache enable.
+ * \sa
+ * - \ref DisableDCache
+*/
+__STATIC_FORCEINLINE void EnableDCache(void)
+{
+    __RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE);
+}
+
+/**
+ * \brief  Disable DCache
+ * \details
+ * This function Disable D-Cache
+ * \remarks
+ * - This function can be called in M-Mode only.
+ * - This \ref CSR_MCACHE_CTL register control D Cache enable.
+ * \sa
+ * - \ref EnableDCache
+ */
+__STATIC_FORCEINLINE void DisableDCache(void)
+{
+    __RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE);
+}
+
+/**
+ * \brief  Invalidate one D-Cache line specified by address in M-Mode
+ * \details
+ * This function unlock and invalidate one D-Cache line specified
+ * by the address.
+ * Command \ref CCM_DC_INVAL is written to CSR \ref CSR_CCM_MCOMMAND.
+ * \remarks
+ * This function must be executed in M-Mode only.
+ * \param [in]    addr    start address to be invalidated
+ */
+__STATIC_FORCEINLINE void MInvalDCacheLine(unsigned long addr)
+{
+    __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
+    __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_INVAL);
+}
+
+/**
+ * \brief  Invalidate several D-Cache lines specified by address in M-Mode
+ * \details
+ * This function unlock and invalidate several D-Cache lines specified
+ * by the address and line count.
+ * Command \ref CCM_DC_INVAL is written to CSR \ref CSR_CCM_MCOMMAND.
+ * \remarks
+ * This function must be executed in M-Mode only.
+ * \param [in]    addr    start address to be invalidated
+ * \param [in]    cnt     count of cache lines to be invalidated
+ */
+__STATIC_FORCEINLINE void MInvalDCacheLines(unsigned long addr, unsigned long cnt)
+{
+    if (cnt > 0) {
+        unsigned long i;
+        __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
+        for (i = 0; i < cnt; i++) {
+            __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_INVAL);
+        }
+    }
+}
+
+/**
+ * \brief  Invalidate one D-Cache line specified by address in S-Mode
+ * \details
+ * This function unlock and invalidate one D-Cache line specified
+ * by the address.
+ * Command \ref CCM_DC_INVAL is written to CSR \ref CSR_CCM_MCOMMAND.
+ * \remarks
+ * This function must be executed in M/S-Mode only.
+ * \param [in]    addr    start address to be invalidated
+ */
+__STATIC_FORCEINLINE void SInvalDCacheLine(unsigned long addr)
+{
+    __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
+    __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_INVAL);
+}
+
+/**
+ * \brief  Invalidate several D-Cache lines specified by address in S-Mode
+ * \details
+ * This function unlock and invalidate several D-Cache lines specified
+ * by the address and line count.
+ * Command \ref CCM_DC_INVAL is written to CSR \ref CSR_CCM_SCOMMAND.
+ * \remarks
+ * This function must be executed in M/S-Mode only.
+ * \param [in]    addr    start address to be invalidated
+ * \param [in]    cnt     count of cache lines to be invalidated
+ */
+__STATIC_FORCEINLINE void SInvalDCacheLines(unsigned long addr, unsigned long cnt)
+{
+    if (cnt > 0) {
+        unsigned long i;
+        __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
+        for (i = 0; i < cnt; i++) {
+            __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_INVAL);
+        }
+    }
+}
+
+/**
+ * \brief  Invalidate one D-Cache line specified by address in U-Mode
+ * \details
+ * This function unlock and invalidate one D-Cache line specified
+ * by the address.
+ * Command \ref CCM_DC_INVAL is written to CSR \ref CSR_CCM_UCOMMAND.
+ * \remarks
+ * This function must be executed in M/S/U-Mode only.
+ * \param [in]    addr    start address to be invalidated
+ */
+__STATIC_FORCEINLINE void UInvalDCacheLine(unsigned long addr)
+{
+    __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
+    __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_INVAL);
+}
+
+/**
+ * \brief  Invalidate several D-Cache lines specified by address in U-Mode
+ * \details
+ * This function unlock and invalidate several D-Cache lines specified
+ * by the address and line count.
+ * Command \ref CCM_DC_INVAL is written to CSR \ref CSR_CCM_UCOMMAND.
+ * \remarks
+ * This function must be executed in M/S/U-Mode only.
+ * \param [in]    addr    start address to be invalidated
+ * \param [in]    cnt     count of cache lines to be invalidated
+ */
+__STATIC_FORCEINLINE void UInvalDCacheLines(unsigned long addr, unsigned long cnt)
+{
+    if (cnt > 0) {
+        unsigned long i;
+        __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
+        for (i = 0; i < cnt; i++) {
+            __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_INVAL);
+        }
+    }
+}
+
+/**
+ * \brief  Flush one D-Cache line specified by address in M-Mode
+ * \details
+ * This function flush one D-Cache line specified by the address.
+ * Command \ref CCM_DC_WB is written to CSR \ref CSR_CCM_MCOMMAND.
+ * \remarks
+ * This function must be executed in M-Mode only.
+ * \param [in]    addr    start address to be flushed
+ */
+__STATIC_FORCEINLINE void MFlushDCacheLine(unsigned long addr)
+{
+    __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
+    __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_WB);
+}
+
+/**
+ * \brief  Flush several D-Cache lines specified by address in M-Mode
+ * \details
+ * This function flush several D-Cache lines specified
+ * by the address and line count.
+ * Command \ref CCM_DC_WB is written to CSR \ref CSR_CCM_MCOMMAND.
+ * \remarks
+ * This function must be executed in M-Mode only.
+ * \param [in]    addr    start address to be flushed
+ * \param [in]    cnt     count of cache lines to be flushed
+ */
+__STATIC_FORCEINLINE void MFlushDCacheLines(unsigned long addr, unsigned long cnt)
+{
+    if (cnt > 0) {
+        unsigned long i;
+        __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
+        for (i = 0; i < cnt; i++) {
+            __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_WB);
+        }
+    }
+}
+
+/**
+ * \brief  Flush one D-Cache line specified by address in S-Mode
+ * \details
+ * This function flush one D-Cache line specified by the address.
+ * Command \ref CCM_DC_WB is written to CSR \ref CSR_CCM_SCOMMAND.
+ * \remarks
+ * This function must be executed in M/S-Mode only.
+ * \param [in]    addr    start address to be flushed
+ */
+__STATIC_FORCEINLINE void SFlushDCacheLine(unsigned long addr)
+{
+    __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
+    __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_WB);
+}
+
+/**
+ * \brief  Flush several D-Cache lines specified by address in S-Mode
+ * \details
+ * This function flush several D-Cache lines specified
+ * by the address and line count.
+ * Command \ref CCM_DC_WB is written to CSR \ref CSR_CCM_SCOMMAND.
+ * \remarks
+ * This function must be executed in M/S-Mode only.
+ * \param [in]    addr    start address to be flushed
+ * \param [in]    cnt     count of cache lines to be flushed
+ */
+__STATIC_FORCEINLINE void SFlushDCacheLines(unsigned long addr, unsigned long cnt)
+{
+    if (cnt > 0) {
+        unsigned long i;
+        __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
+        for (i = 0; i < cnt; i++) {
+            __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_WB);
+        }
+    }
+}
+
+/**
+ * \brief  Flush one D-Cache line specified by address in U-Mode
+ * \details
+ * This function flush one D-Cache line specified by the address.
+ * Command \ref CCM_DC_WB is written to CSR \ref CSR_CCM_UCOMMAND.
+ * \remarks
+ * This function must be executed in M/S/U-Mode only.
+ * \param [in]    addr    start address to be flushed
+ */
+__STATIC_FORCEINLINE void UFlushDCacheLine(unsigned long addr)
+{
+    __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
+    __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_WB);
+}
+
+/**
+ * \brief  Flush several D-Cache lines specified by address in U-Mode
+ * \details
+ * This function flush several D-Cache lines specified
+ * by the address and line count.
+ * Command \ref CCM_DC_WB is written to CSR \ref CSR_CCM_UCOMMAND.
+ * \remarks
+ * This function must be executed in M/S/U-Mode only.
+ * \param [in]    addr    start address to be flushed
+ * \param [in]    cnt     count of cache lines to be flushed
+ */
+__STATIC_FORCEINLINE void UFlushDCacheLines(unsigned long addr, unsigned long cnt)
+{
+    if (cnt > 0) {
+        unsigned long i;
+        __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
+        for (i = 0; i < cnt; i++) {
+            __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_WB);
+        }
+    }
+}
+
+/**
+ * \brief  Flush and invalidate one D-Cache line specified by address in M-Mode
+ * \details
+ * This function flush and invalidate one D-Cache line specified by the address.
+ * Command \ref CCM_DC_WBINVAL is written to CSR \ref CSR_CCM_MCOMMAND.
+ * \remarks
+ * This function must be executed in M-Mode only.
+ * \param [in]    addr    start address to be flushed and invalidated
+ */
+__STATIC_FORCEINLINE void MFlushInvalDCacheLine(unsigned long addr)
+{
+    __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
+    __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_WBINVAL);
+}
+
+/**
+ * \brief  Flush and invalidate several D-Cache lines specified by address in M-Mode
+ * \details
+ * This function flush and invalidate several D-Cache lines specified
+ * by the address and line count.
+ * Command \ref CCM_DC_WBINVAL is written to CSR \ref CSR_CCM_MCOMMAND.
+ * \remarks
+ * This function must be executed in M-Mode only.
+ * \param [in]    addr    start address to be flushed and invalidated
+ * \param [in]    cnt     count of cache lines to be flushed and invalidated
+ */
+__STATIC_FORCEINLINE void MFlushInvalDCacheLines(unsigned long addr, unsigned long cnt)
+{
+    if (cnt > 0) {
+        unsigned long i;
+        __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
+        for (i = 0; i < cnt; i++) {
+            __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_WBINVAL);
+        }
+    }
+}
+
+/**
+ * \brief  Flush and invalidate one D-Cache line specified by address in S-Mode
+ * \details
+ * This function flush and invalidate one D-Cache line specified by the address.
+ * Command \ref CCM_DC_WBINVAL is written to CSR \ref CSR_CCM_SCOMMAND.
+ * \remarks
+ * This function must be executed in M/S-Mode only.
+ * \param [in]    addr    start address to be flushed and invalidated
+ */
+__STATIC_FORCEINLINE void SFlushInvalDCacheLine(unsigned long addr)
+{
+    __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
+    __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_WBINVAL);
+}
+
+/**
+ * \brief  Flush and invalidate several D-Cache lines specified by address in S-Mode
+ * \details
+ * This function flush and invalidate several D-Cache lines specified
+ * by the address and line count.
+ * Command \ref CCM_DC_WBINVAL is written to CSR \ref CSR_CCM_SCOMMAND.
+ * \remarks
+ * This function must be executed in M/S-Mode only.
+ * \param [in]    addr    start address to be flushed and invalidated
+ * \param [in]    cnt     count of cache lines to be flushed and invalidated
+ */
+__STATIC_FORCEINLINE void SFlushInvalDCacheLines(unsigned long addr, unsigned long cnt)
+{
+    if (cnt > 0) {
+        unsigned long i;
+        __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
+        for (i = 0; i < cnt; i++) {
+            __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_WBINVAL);
+        }
+    }
+}
+
+/**
+ * \brief  Flush and invalidate one D-Cache line specified by address in U-Mode
+ * \details
+ * This function flush and invalidate one D-Cache line specified by the address.
+ * Command \ref CCM_DC_WBINVAL is written to CSR \ref CSR_CCM_UCOMMAND.
+ * \remarks
+ * This function must be executed in M/S/U-Mode only.
+ * \param [in]    addr    start address to be flushed and invalidated
+ */
+__STATIC_FORCEINLINE void UFlushInvalDCacheLine(unsigned long addr)
+{
+    __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
+    __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_WBINVAL);
+}
+
+/**
+ * \brief  Flush and invalidate several D-Cache lines specified by address in U-Mode
+ * \details
+ * This function flush and invalidate several D-Cache lines specified
+ * by the address and line count.
+ * Command \ref CCM_DC_WBINVAL is written to CSR \ref CSR_CCM_UCOMMAND.
+ * \remarks
+ * This function must be executed in M/S/U-Mode only.
+ * \param [in]    addr    start address to be flushed and invalidated
+ * \param [in]    cnt     count of cache lines to be flushed and invalidated
+ */
+__STATIC_FORCEINLINE void UFlushInvalDCacheLines(unsigned long addr, unsigned long cnt)
+{
+    if (cnt > 0) {
+        unsigned long i;
+        __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
+        for (i = 0; i < cnt; i++) {
+            __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_WBINVAL);
+        }
+    }
+}
+
+/**
+ * \brief  Lock one D-Cache line specified by address in M-Mode
+ * \details
+ * This function lock one D-Cache line specified by the address.
+ * Command \ref CCM_DC_LOCK is written to CSR \ref CSR_CCM_MCOMMAND.
+ * \remarks
+ * This function must be executed in M-Mode only.
+ * \param [in]    addr    start address to be locked
+ * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO
+ */
+__STATIC_FORCEINLINE unsigned long MLockDCacheLine(unsigned long addr)
+{
+    __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
+    __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_LOCK);
+    return __RV_CSR_READ(CSR_CCM_MDATA);
+}
+
+/**
+ * \brief  Lock several D-Cache lines specified by address in M-Mode
+ * \details
+ * This function lock several D-Cache lines specified by the address
+ * and line count.
+ * Command \ref CCM_DC_LOCK is written to CSR \ref CSR_CCM_MCOMMAND.
+ * \remarks
+ * This function must be executed in M-Mode only.
+ * \param [in]    addr    start address to be locked
+ * \param [in]    cnt     count of cache lines to be locked
+ * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO
+ */
+__STATIC_FORCEINLINE unsigned long MLockDCacheLines(unsigned long addr, unsigned long cnt)
+{
+    if (cnt > 0) {
+        unsigned long i;
+        __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
+        for (i = 0; i < cnt; i++) {
+            __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_LOCK);
+        }
+        return __RV_CSR_READ(CSR_CCM_MDATA);
+    } else {
+        return 0;
+    }
+}
+
+/**
+ * \brief  Lock one D-Cache line specified by address in S-Mode
+ * \details
+ * This function lock one D-Cache line specified by the address.
+ * Command \ref CCM_DC_LOCK is written to CSR \ref CSR_CCM_SCOMMAND.
+ * \remarks
+ * This function must be executed in M/S-Mode only.
+ * \param [in]    addr    start address to be locked
+ * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO
+ */
+__STATIC_FORCEINLINE unsigned long SLockDCacheLine(unsigned long addr)
+{
+    __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
+    __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_LOCK);
+    return __RV_CSR_READ(CSR_CCM_SDATA);
+}
+
+/**
+ * \brief  Lock several D-Cache lines specified by address in S-Mode
+ * \details
+ * This function lock several D-Cache lines specified by the address
+ * and line count.
+ * Command \ref CCM_DC_LOCK is written to CSR \ref CSR_CCM_SCOMMAND.
+ * \remarks
+ * This function must be executed in M/S-Mode only.
+ * \param [in]    addr    start address to be locked
+ * \param [in]    cnt     count of cache lines to be locked
+ * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO
+ */
+__STATIC_FORCEINLINE unsigned long SLockDCacheLines(unsigned long addr, unsigned long cnt)
+{
+    if (cnt > 0) {
+        unsigned long i;
+        __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
+        for (i = 0; i < cnt; i++) {
+            __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_LOCK);
+        }
+        return __RV_CSR_READ(CSR_CCM_SDATA);
+    } else {
+        return 0;
+    }
+}
+
+/**
+ * \brief  Lock one D-Cache line specified by address in U-Mode
+ * \details
+ * This function lock one D-Cache line specified by the address.
+ * Command \ref CCM_DC_LOCK is written to CSR \ref CSR_CCM_UCOMMAND.
+ * \remarks
+ * This function must be executed in M/S/U-Mode only.
+ * \param [in]    addr    start address to be locked
+ * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO
+ */
+__STATIC_FORCEINLINE unsigned long ULockDCacheLine(unsigned long addr)
+{
+    __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
+    __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_LOCK);
+    return __RV_CSR_READ(CSR_CCM_UDATA);
+}
+
+/**
+ * \brief  Lock several D-Cache lines specified by address in U-Mode
+ * \details
+ * This function lock several D-Cache lines specified by the address
+ * and line count.
+ * Command \ref CCM_DC_LOCK is written to CSR \ref CSR_CCM_UCOMMAND.
+ * \remarks
+ * This function must be executed in M/S/U-Mode only.
+ * \param [in]    addr    start address to be locked
+ * \param [in]    cnt     count of cache lines to be locked
+ * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO
+ */
+__STATIC_FORCEINLINE unsigned long ULockDCacheLines(unsigned long addr, unsigned long cnt)
+{
+    if (cnt > 0) {
+        unsigned long i;
+        __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
+        for (i = 0; i < cnt; i++) {
+            __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_LOCK);
+        }
+        return __RV_CSR_READ(CSR_CCM_UDATA);
+    } else {
+        return 0;
+    }
+}
+
+/**
+ * \brief  Unlock one D-Cache line specified by address in M-Mode
+ * \details
+ * This function unlock one D-Cache line specified by the address.
+ * Command \ref CCM_DC_UNLOCK is written to CSR \ref CSR_CCM_MCOMMAND.
+ * \remarks
+ * This function must be executed in M-Mode only.
+ * \param [in]    addr    start address to be unlocked
+ */
+__STATIC_FORCEINLINE void MUnlockDCacheLine(unsigned long addr)
+{
+    __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
+    __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_UNLOCK);
+}
+
+/**
+ * \brief  Unlock several D-Cache lines specified by address in M-Mode
+ * \details
+ * This function unlock several D-Cache lines specified
+ * by the address and line count.
+ * Command \ref CCM_DC_UNLOCK is written to CSR \ref CSR_CCM_MCOMMAND.
+ * \remarks
+ * This function must be executed in M-Mode only.
+ * \param [in]    addr    start address to be unlocked
+ * \param [in]    cnt     count of cache lines to be unlocked
+ */
+__STATIC_FORCEINLINE void MUnlockDCacheLines(unsigned long addr, unsigned long cnt)
+{
+    if (cnt > 0) {
+        unsigned long i;
+        __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
+        for (i = 0; i < cnt; i++) {
+            __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_UNLOCK);
+        }
+    }
+}
+
+/**
+ * \brief  Unlock one D-Cache line specified by address in S-Mode
+ * \details
+ * This function unlock one D-Cache line specified by the address.
+ * Command \ref CCM_DC_UNLOCK is written to CSR \ref CSR_CCM_SCOMMAND.
+ * \remarks
+ * This function must be executed in M/S-Mode only.
+ * \param [in]    addr    start address to be unlocked
+ */
+__STATIC_FORCEINLINE void SUnlockDCacheLine(unsigned long addr)
+{
+    __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
+    __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_UNLOCK);
+}
+
+/**
+ * \brief  Unlock several D-Cache lines specified by address in S-Mode
+ * \details
+ * This function unlock several D-Cache lines specified
+ * by the address and line count.
+ * Command \ref CCM_DC_UNLOCK is written to CSR \ref CSR_CCM_SCOMMAND.
+ * \remarks
+ * This function must be executed in M/S-Mode only.
+ * \param [in]    addr    start address to be unlocked
+ * \param [in]    cnt     count of cache lines to be unlocked
+ */
+__STATIC_FORCEINLINE void SUnlockDCacheLines(unsigned long addr, unsigned long cnt)
+{
+    if (cnt > 0) {
+        unsigned long i;
+        __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
+        for (i = 0; i < cnt; i++) {
+            __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_UNLOCK);
+        }
+    }
+}
+
+/**
+ * \brief  Unlock one D-Cache line specified by address in U-Mode
+ * \details
+ * This function unlock one D-Cache line specified by the address.
+ * Command \ref CCM_DC_UNLOCK is written to CSR \ref CSR_CCM_UCOMMAND.
+ * \remarks
+ * This function must be executed in M/S/U-Mode only.
+ * \param [in]    addr    start address to be unlocked
+ */
+__STATIC_FORCEINLINE void UUnlockDCacheLine(unsigned long addr)
+{
+    __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
+    __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_UNLOCK);
+}
+
+/**
+ * \brief  Unlock several D-Cache lines specified by address in U-Mode
+ * \details
+ * This function unlock several D-Cache lines specified
+ * by the address and line count.
+ * Command \ref CCM_DC_UNLOCK is written to CSR \ref CSR_CCM_UCOMMAND.
+ * \remarks
+ * This function must be executed in M/S/U-Mode only.
+ * \param [in]    addr    start address to be unlocked
+ * \param [in]    cnt     count of cache lines to be unlocked
+ */
+__STATIC_FORCEINLINE void UUnlockDCacheLines(unsigned long addr, unsigned long cnt)
+{
+    if (cnt > 0) {
+        unsigned long i;
+        __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
+        for (i = 0; i < cnt; i++) {
+            __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_UNLOCK);
+        }
+    }
+}
+
+/**
+ * \brief  Invalidate all D-Cache lines in M-Mode
+ * \details
+ * This function invalidate all D-Cache lines.
+ * Command \ref CCM_DC_INVAL_ALL is written to CSR \ref CSR_CCM_MCOMMAND.
+ * \remarks
+ * This function must be executed in M-Mode only.
+ * \param [in]    addr    start address to be invalidated
+ */
+__STATIC_FORCEINLINE void MInvalDCache(void)
+{
+    __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_INVAL_ALL);
+}
+
+/**
+ * \brief  Invalidate all D-Cache lines in S-Mode
+ * \details
+ * This function invalidate all D-Cache lines.
+ * Command \ref CCM_DC_INVAL_ALL is written to CSR \ref CSR_CCM_SCOMMAND.
+ * \remarks
+ * This function must be executed in M/S-Mode only.
+ * \param [in]    addr    start address to be invalidated
+ */
+__STATIC_FORCEINLINE void SInvalDCache(void)
+{
+    __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_INVAL_ALL);
+}
+
+/**
+ * \brief  Invalidate all D-Cache lines in U-Mode
+ * \details
+ * This function invalidate all D-Cache lines.
+ * In U-Mode, this operation will be automatically
+ * translated to flush and invalidate operations by hardware.
+ * Command \ref CCM_DC_INVAL_ALL is written to CSR \ref CSR_CCM_UCOMMAND.
+ * \remarks
+ * This function must be executed in M/S/U-Mode only.
+ * \param [in]    addr    start address to be invalidated
+ */
+__STATIC_FORCEINLINE void UInvalDCache(void)
+{
+    __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_INVAL_ALL);
+}
+
+/**
+ * \brief  Flush all D-Cache lines in M-Mode
+ * \details
+ * This function flush all D-Cache lines.
+ * Command \ref CCM_DC_WB_ALL is written to CSR \ref CSR_CCM_MCOMMAND.
+ * \remarks
+ * This function must be executed in M-Mode only.
+ * \param [in]    addr    start address to be flushed
+ */
+__STATIC_FORCEINLINE void MFlushDCache(void)
+{
+    __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_WB_ALL);
+}
+
+/**
+ * \brief  Flush all D-Cache lines in S-Mode
+ * \details
+ * This function flush all D-Cache lines.
+ * Command \ref CCM_DC_WB_ALL is written to CSR \ref CSR_CCM_SCOMMAND.
+ * \remarks
+ * This function must be executed in M/S-Mode only.
+ * \param [in]    addr    start address to be flushed
+ */
+__STATIC_FORCEINLINE void SFlushDCache(void)
+{
+    __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_WB_ALL);
+}
+
+/**
+ * \brief  Flush all D-Cache lines in U-Mode
+ * \details
+ * This function flush all D-Cache lines.
+ * Command \ref CCM_DC_WB_ALL is written to CSR \ref CSR_CCM_UCOMMAND.
+ * \remarks
+ * This function must be executed in M/S/U-Mode only.
+ * \param [in]    addr    start address to be flushed
+ */
+__STATIC_FORCEINLINE void UFlushDCache(void)
+{
+    __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_WB_ALL);
+}
+
+/**
+ * \brief  Flush and invalidate all D-Cache lines in M-Mode
+ * \details
+ * This function flush and invalidate all D-Cache lines.
+ * Command \ref CCM_DC_WBINVAL_ALL is written to CSR \ref CSR_CCM_MCOMMAND.
+ * \remarks
+ * This function must be executed in M-Mode only.
+ * \param [in]    addr    start address to be flushed and locked
+ */
+__STATIC_FORCEINLINE void MFlushInvalDCache(void)
+{
+    __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_WBINVAL_ALL);
+}
+
+/**
+ * \brief  Flush and invalidate all D-Cache lines in S-Mode
+ * \details
+ * This function flush and invalidate all D-Cache lines.
+ * Command \ref CCM_DC_WBINVAL_ALL is written to CSR \ref CSR_CCM_SCOMMAND.
+ * \remarks
+ * This function must be executed in M/S-Mode only.
+ * \param [in]    addr    start address to be flushed and locked
+ */
+__STATIC_FORCEINLINE void SFlushInvalDCache(void)
+{
+    __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_WBINVAL_ALL);
+}
+
+/**
+ * \brief  Flush and invalidate all D-Cache lines in U-Mode
+ * \details
+ * This function flush and invalidate all D-Cache lines.
+ * Command \ref CCM_DC_WBINVAL_ALL is written to CSR \ref CSR_CCM_UCOMMAND.
+ * \remarks
+ * This function must be executed in M/S/U-Mode only.
+ * \param [in]    addr    start address to be flushed and locked
+ */
+__STATIC_FORCEINLINE void UFlushInvalDCache(void)
+{
+    __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_WBINVAL_ALL);
+}
+
+/** @} */ /* End of Doxygen Group NMSIS_Core_DCache */
+#endif /* defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1) */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /** __CORE_FEATURE_CACHE_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_dsp.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_dsp.h
new file mode 100644
index 00000000..42df123c
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_dsp.h
@@ -0,0 +1,18667 @@
+/*
+ * Copyright (c) 2019 Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __CORE_FEATURE_DSP__
+#define __CORE_FEATURE_DSP__
+
+/*!
+ * @file     core_feature_dsp.h
+ * @brief    DSP feature API header file for Nuclei N/NX Core
+ */
+/*
+ * DSP Feature Configuration Macro:
+ * 1. __DSP_PRESENT:  Define whether Digital Signal Processing Unit(DSP) is present or not
+ *   * 0: Not present
+ *   * 1: Present
+ */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
+
+/* ###########################  CPU SIMD DSP Intrinsic Functions ########################### */
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic   Intrinsic Functions for SIMD Instructions
+ * \ingroup  NMSIS_Core
+ * \brief    Functions that generate RISC-V DSP SIMD instructions.
+ * \details
+ *
+ * The following functions generate specified RISC-V SIMD instructions that cannot be directly accessed by compiler.
+ * * **DSP ISA Extension Instruction Summary**
+ *   + **Shorthand Definitions**
+ *     - r.H == rH1: r[31:16], r.L == r.H0: r[15:0]
+ *     - r.B3: r[31:24], r.B2: r[23:16], r.B1: r[15:8], r.B0: r[7:0]
+ *     - r.B[x]: r[(x*8+7):(x*8+0)]
+ *     - r.H[x]: r[(x*16+7):(x*16+0)]
+ *     - r.W[x]: r[(x*32+31):(x*32+0)]
+ *     - r[xU]: the upper 32-bit of a 64-bit number; xU represents the GPR number that contains this upper part 32-bit value.
+ *     - r[xL]: the lower 32-bit of a 64-bit number; xL represents the GPR number that contains this lower part 32-bit value.
+ *     - r[xU].r[xL]: a 64-bit number that is formed from a pair of GPRs.
+ *     - s>>: signed arithmetic right shift:
+ *     - u>>: unsigned logical right shift
+ *     - SAT.Qn(): Saturate to the range of [-2^n, 2^n-1], if saturation happens, set PSW.OV.
+ *     - SAT.Um(): Saturate to the range of [0, 2^m-1], if saturation happens, set PSW.OV.
+ *     - RUND(): Indicate `rounding`, i.e., add 1 to the most significant discarded bit for right shift or MSW-type multiplication instructions.
+ *     - Sign or Zero Extending functions:
+ *       - SEm(data): Sign-Extend data to m-bit.:
+ *       - ZEm(data): Zero-Extend data to m-bit.
+ *     - ABS(x): Calculate the absolute value of `x`.
+ *     - CONCAT(x,y): Concatinate `x` and `y` to form a value.
+ *     - u<: Unsinged less than comparison.
+ *     - u<=: Unsinged less than & equal comparison.
+ *     - u>: Unsinged greater than comparison.
+ *     - s*: Signed multiplication.
+ *     - u*: Unsigned multiplication.
+ *
+ *   @{
+ */
+/** @} */ /* End of Doxygen Group NMSIS_Core_DSP_Intrinsic */
+
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS      SIMD Data Processing Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic
+ * \brief    SIMD Data Processing Instructions
+ * \details
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB      SIMD 16-bit Add/Subtract Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS
+ * \brief    SIMD 16-bit Add/Subtract Instructions
+ * \details
+ * Based on the combination of the types of the two 16-bit arithmetic operations, the SIMD 16-bit
+ * add/subtract instructions can be classified into 6 main categories: Addition (two 16-bit addition),
+ * Subtraction (two 16-bit subtraction), Crossed Add & Sub (one addition and one subtraction), and
+ * Crossed Sub & Add (one subtraction and one addition), Straight Add & Sub (one addition and one
+ * subtraction), and Straight Sub & Add (one subtraction and one addition).
+ * Based on the way of how an overflow condition is handled, the SIMD 16-bit add/subtract
+ * instructions can be classified into 5 groups: Wrap-around (dropping overflow), Signed Halving
+ * (keeping overflow by dropping 1 LSB bit), Unsigned Halving, Signed Saturation (clipping overflow),
+ * and Unsigned Saturation.
+ * Together, there are 30 SIMD 16-bit add/subtract instructions.
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB      SIMD 8-bit Addition & Subtraction Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS
+ * \brief    SIMD 8-bit Addition & Subtraction Instructions
+ * \details
+ * Based on the types of the four 8-bit arithmetic operations, the SIMD 8-bit add/subtract instructions
+ * can be classified into 2 main categories: Addition (four 8-bit addition), and Subtraction (four 8-bit
+ * subtraction).
+ * Based on the way of how an overflow condition is handled for singed or unsigned operation, the
+ * SIMD 8-bit add/subtract instructions can be classified into 5 groups: Wrap-around (dropping
+ * overflow), Signed Halving (keeping overflow by dropping 1 LSB bit), Unsigned Halving, Signed
+ * Saturation (clipping overflow), and Unsigned Saturation.
+ * Together, there are 10 SIMD 8-bit add/subtract instructions.
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT      SIMD 16-bit Shift Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS
+ * \brief    SIMD 16-bit Shift Instructions
+ * \details
+ * there are 14 SIMD 16-bit shift instructions.
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT      SIMD 8-bit Shift Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS
+ * \brief    SIMD 8-bit Shift Instructions
+ * \details
+ *  there are 14 SIMD 8-bit shift instructions.
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_CMP      SIMD 16-bit Compare Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS
+ * \brief    SIMD 16-bit Compare Instructions
+ * \details
+ *  there are 5 SIMD 16-bit Compare instructions.
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_CMP      SIMD 8-bit Compare Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS
+ * \brief    SIMD 8-bit Compare Instructions
+ * \details
+ *  there are 5  SIMD 8-bit Compare instructions.
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MULTIPLY      SIMD 16-bit Multiply Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS
+ * \brief    SIMD 16-bit Multiply Instructions
+ * \details
+ * there are 6 SIMD 16-bit Multiply instructions.
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MULTIPLY      SIMD 8-bit Multiply Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS
+ * \brief    SIMD 8-bit Multiply Instructions
+ * \details
+ *  there are 6 SIMD 8-bit Multiply instructions.
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC      SIMD 16-bit Miscellaneous Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS
+ * \brief    SIMD 16-bit Miscellaneous Instructions
+ * \details
+ *  there are 10 SIMD 16-bit Misc instructions.
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC      SIMD 8-bit Miscellaneous Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS
+ * \brief    SIMD 8-bit Miscellaneous Instructions
+ * \details
+ *  there are 10 SIMD 8-bit Miscellaneous instructions.
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK      SIMD 8-bit Unpacking Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS
+ * \brief    SIMD 8-bit Unpacking Instructions
+ * \details
+ *  there are 8 SIMD 8-bit Unpacking instructions.
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_NON_SIMD      Non-SIMD Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic
+ * \brief    Non-SIMD Instructions
+ * \details
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU      Non-SIMD Q15 saturation ALU Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_NON_SIMD
+ * \brief    Non-SIMD Q15 saturation ALU Instructions
+ * \details
+ * there are 7 Non-SIMD Q15 saturation ALU Instructions
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU      Non-SIMD Q31 saturation ALU Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_NON_SIMD
+ * \brief    Non-SIMD Q31 saturation ALU Instructions
+ * \details
+ *  there are Non-SIMD Q31 saturation ALU Instructions
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION      32-bit Computation Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_NON_SIMD
+ * \brief    32-bit Computation Instructions
+ * \details
+ * there are 8 32-bit Computation Instructions
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_OV_FLAG_SC      OV (Overflow) flag Set/Clear Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_NON_SIMD
+ * \brief    OV (Overflow) flag Set/Clear Instructions
+ * \details
+ * The following table lists the user instructions related to Overflow (OV) flag manipulation. there are 2 OV (Overflow) flag Set/Clear Instructions
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC      Non-SIMD Miscellaneous Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_NON_SIMD
+ * \brief    Non-SIMD Miscellaneous Instructions
+ * \details
+ * There are 13 Miscellaneous Instructions here.
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS      Partial-SIMD Data Processing Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic
+ * \brief    Partial-SIMD Data Processing Instructions
+ * \details
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_PACK      SIMD 16-bit Packing Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS
+ * \brief    SIMD 16-bit Packing Instructions
+ * \details
+ * there are 4 SIMD16-bit Packing Instructions.
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC      Signed MSW 32x32 Multiply and Add Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS
+ * \brief    Signed MSW 32x32 Multiply and Add Instructions
+ * \details
+ *  there are 8 Signed MSW 32x32 Multiply and Add Instructions
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC      Signed MSW 32x16 Multiply and Add Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS
+ * \brief    Signed MSW 32x16 Multiply and Add Instructions
+ * \details
+ * there are 15 Signed MSW 32x16 Multiply and Add Instructions
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB      Signed 16-bit Multiply 32-bit Add/Subtract Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS
+ * \brief    Signed 16-bit Multiply 32-bit Add/Subtract Instructions
+ * \details
+ *  there are 18 Signed 16-bit Multiply 32-bit Add/Subtract Instructions
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB      Signed 16-bit Multiply 64-bit Add/Subtract Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS
+ * \brief    Signed 16-bit Multiply 64-bit Add/Subtract Instructions
+ * \details
+ *  there is Signed 16-bit Multiply 64-bit Add/Subtract Instructions
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC      Partial-SIMD Miscellaneous Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS
+ * \brief    Partial-SIMD Miscellaneous Instructions
+ * \details
+ *  there are  7 Partial-SIMD Miscellaneous Instructions
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_8B_MULT_32B_ADD      8-bit Multiply with 32-bit Add Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS
+ * \brief    8-bit Multiply with 32-bit Add Instructions
+ * \details
+ * there are  3 8-bit Multiply with 32-bit Add Instructions
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_64B_PROFILE      64-bit Profile Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic
+ * \brief    64-bit Profile Instructions
+ * \details
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB      64-bit Addition & Subtraction Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_64B_PROFILE
+ * \brief    64-bit Addition & Subtraction Instructions
+ * \details
+ * there are 10 64-bit Addition & Subtraction Instructions.
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB      32-bit Multiply with 64-bit Add/Subtract Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_64B_PROFILE
+ * \brief    32-bit Multiply with 64-bit Add/Subtract Instructions
+ * \details
+ *  there are 32-bit Multiply 64-bit Add/Subtract Instructions
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB      Signed 16-bit Multiply with 64-bit Add/Subtract Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_64B_PROFILE
+ * \brief    Signed 16-bit Multiply with 64-bit Add/Subtract Instructions
+ * \details
+ * there are 10 Signed 16-bit Multiply with 64-bit Add/Subtract Instructions
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_ONLY      RV64 Only Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic
+ * \brief    RV64 Only Instructions
+ * \details
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB      (RV64 Only) SIMD 32-bit Add/Subtract Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_RV64_ONLY
+ * \brief    (RV64 Only) SIMD 32-bit Add/Subtract Instructions
+ * \details
+ * The following tables list instructions that are only present in RV64.
+ * There are 30 SIMD 32-bit addition or subtraction instructions.there are 4 SIMD16-bit Packing Instructions.
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT      (RV64 Only) SIMD 32-bit Shift Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_RV64_ONLY
+ * \brief    (RV64 Only) SIMD 32-bit Shift Instructions
+ * \details
+ *  there are 14 (RV64 Only) SIMD 32-bit Shift Instructions
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_MISC      (RV64 Only) SIMD 32-bit Miscellaneous Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_RV64_ONLY
+ * \brief    (RV64 Only) SIMD 32-bit Miscellaneous Instructions
+ * \details
+ * there are 5  (RV64 Only) SIMD 32-bit Miscellaneous Instructions
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT      (RV64 Only) SIMD Q15 Saturating Multiply Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_RV64_ONLY
+ * \brief    (RV64 Only) SIMD Q15 Saturating Multiply Instructions
+ * \details
+ *  there are 9 (RV64 Only) SIMD Q15 saturating Multiply Instructions
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT      (RV64 Only) 32-bit Multiply Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_RV64_ONLY
+ * \brief    (RV64 Only) 32-bit Multiply Instructions
+ * \details
+ *  there is 3 RV64 Only) 32-bit Multiply Instructions
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT_ADD      (RV64 Only) 32-bit Multiply & Add Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_RV64_ONLY
+ * \brief    (RV64 Only) 32-bit Multiply & Add Instructions
+ * \details
+ *  there are  3 (RV64 Only) 32-bit Multiply & Add Instructions
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC      (RV64 Only) 32-bit Parallel Multiply & Add Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_RV64_ONLY
+ * \brief    (RV64 Only) 32-bit Parallel Multiply & Add Instructions
+ * \details
+ * there are 12 (RV64 Only) 32-bit Parallel Multiply & Add Instructions
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_NON_SIMD_32B_SHIFT      (RV64 Only) Non-SIMD 32-bit Shift Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_RV64_ONLY
+ * \brief    (RV64 Only) Non-SIMD 32-bit Shift Instructions
+ * \details
+ *  there are 1  (RV64 Only) Non-SIMD 32-bit Shift Instructions
+ */
+
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PACK      32-bit Packing Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_RV64_ONLY
+ * \brief    32-bit Packing Instructions
+ * \details
+ *  There are four 32-bit packing instructions here
+ */
+
+/* ===== Inline Function Start for 3.1. ADD8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB
+ * \brief ADD8 (SIMD 8-bit Addition)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * ADD8 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit integer element additions simultaneously.
+ *
+ * **Description**:\n
+ * This instruction adds the 8-bit integer elements in Rs1 with the 8-bit integer elements
+ * in Rs2, and then writes the 8-bit element results to Rd.
+ *
+ * **Note**:\n
+ * This instruction can be used for either signed or unsigned addition.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.B[x] = Rs1.B[x] + Rs2.B[x];
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_ADD8(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("add8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.1. ADD8 ===== */
+
+/* ===== Inline Function Start for 3.2. ADD16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief ADD16 (SIMD 16-bit Addition)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * ADD16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit integer element additions simultaneously.
+ *
+ * **Description**:\n
+ * This instruction adds the 16-bit integer elements in Rs1 with the 16-bit integer
+ * elements in Rs2, and then writes the 16-bit element results to Rd.
+ *
+ * **Note**:\n
+ * This instruction can be used for either signed or unsigned addition.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.H[x] = Rs1.H[x] + Rs2.H[x];
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_ADD16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("add16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.2. ADD16 ===== */
+
+/* ===== Inline Function Start for 3.3. ADD64 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB
+ * \brief ADD64 (64-bit Addition)
+ * \details
+ * **Type**: 64-bit Profile
+ *
+ * **Syntax**:\n
+ * ~~~
+ * ADD64 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Add two 64-bit signed or unsigned integers.
+ *
+ * **RV32 Description**:\n
+ * This instruction adds the 64-bit integer of an even/odd pair of registers specified
+ * by Rs1(4,1) with the 64-bit integer of an even/odd pair of registers specified by Rs2(4,1), and then
+ * writes the 64-bit result to an even/odd pair of registers specified by Rd(4,1).
+ * Rx(4,1), i.e., value d, determines the even/odd pair group of two registers. Specifically, the register
+ * pair includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
+ * of the pair contains the low 32-bit of the result.
+ *
+ * **RV64 Description**:\n
+ * This instruction has the same behavior as the ADD instruction in RV64I.
+ *
+ * **Note**:\n
+ * This instruction can be used for either signed or unsigned addition.
+ *
+ * **Operations**:\n
+ * ~~~
+ * RV32:
+ *  t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
+ *  a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1);
+ *  b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1);
+ *  R[t_H].R[t_L] = R[a_H].R[a_L] + R[b_H].R[b_L];
+ * RV64:
+ *  Rd = Rs1 + Rs2;
+ * ~~~
+ *
+ * \param [in]  a    unsigned long long type of value stored in a
+ * \param [in]  b    unsigned long long type of value stored in b
+ * \return value stored in unsigned long long type
+ */
+__STATIC_FORCEINLINE unsigned long long __RV_ADD64(unsigned long long a, unsigned long long b)
+{
+    register unsigned long long result;
+    __ASM volatile("add64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.3. ADD64 ===== */
+
+/* ===== Inline Function Start for 3.4. AVE ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
+ * \brief AVE (Average with Rounding)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * AVE Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Calculate the average of the contents of two general registers.
+ *
+ * **Description**:\n
+ * This instruction calculates the average value of two signed integers stored in Rs1 and
+ * Rs2, rounds up a half-integer result to the nearest integer, and writes the result to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Sum = CONCAT(Rs1[MSB],Rs1[MSB:0]) + CONCAT(Rs2[MSB],Rs2[MSB:0]) + 1;
+ * Rd = Sum[(MSB+1):1];
+ * for RV32: MSB=31,
+ * for RV64: MSB=63
+ * ~~~
+ *
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_AVE(long a, long b)
+{
+    register long result;
+    __ASM volatile("ave %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.4. AVE ===== */
+
+/* ===== Inline Function Start for 3.5. BITREV ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
+ * \brief BITREV (Bit Reverse)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * BITREV Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Reverse the bit positions of the source operand within a specified width starting from bit
+ * 0. The reversed width is a variable from a GPR.
+ *
+ * **Description**:\n
+ * This instruction reverses the bit positions of the content of Rs1. The reversed bit width
+ * is calculated as Rs2[4:0]+1 (RV32) or Rs2[5:0]+1 (RV64). The upper bits beyond the reversed width
+ * are filled with zeros. After the bit reverse operation, the result is written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * msb = Rs2[4:0]; (for RV32)
+ * msb = Rs2[5:0]; (for RV64)
+ * rev[0:msb] = Rs1[msb:0];
+ * Rd = ZE(rev[msb:0]);
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_BITREV(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("bitrev %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.5. BITREV ===== */
+
+/* ===== Inline Function Start for 3.6. BITREVI ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
+ * \brief BITREVI (Bit Reverse Immediate)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * (RV32) BITREVI Rd, Rs1, imm[4:0]
+ * (RV64) BITREVI Rd, Rs1, imm[5:0]
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Reverse the bit positions of the source operand within a specified width starting from bit
+ * 0. The reversed width is an immediate value.
+ *
+ * **Description**:\n
+ * This instruction reverses the bit positions of the content of Rs1. The reversed bit width
+ * is calculated as imm[4:0]+1 (RV32) or imm[5:0]+1 (RV64). The upper bits beyond the reversed width
+ * are filled with zeros. After the bit reverse operation, the result is written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * msb = imm[4:0]; (RV32)
+ * msb = imm[5:0]; (RV64)
+ * rev[0:msb] = Rs1[msb:0];
+ * Rd = ZE(rev[msb:0]);
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+#define __RV_BITREVI(a, b)    \
+    ({    \
+        register unsigned long result;    \
+        register unsigned long __a = (unsigned long)(a);    \
+        __ASM volatile("bitrevi %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
+        result;    \
+    })
+/* ===== Inline Function End for 3.6. BITREVI ===== */
+
+/* ===== Inline Function Start for 3.7. BPICK ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
+ * \brief BPICK (Bit-wise Pick)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * BPICK Rd, Rs1, Rs2, Rc
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Select from two source operands based on a bit mask in the third operand.
+ *
+ * **Description**:\n
+ * This instruction selects individual bits from Rs1 or Rs2, based on the bit mask value in
+ * Rc. If a bit in Rc is 1, the corresponding bit is from Rs1; otherwise, the corresponding bit is from Rs2.
+ * The selection results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd[x] = Rc[x]? Rs1[x] : Rs2[x];
+ * for RV32, x=31...0
+ * for RV64, x=63...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \param [in]  c    unsigned long type of value stored in c
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_BPICK(unsigned long a, unsigned long b, unsigned long c)
+{
+    register unsigned long result;
+    __ASM volatile("bpick %0, %1, %2, %3" : "=r"(result) : "r"(a), "r"(b), "r"(c));
+    return result;
+}
+/* ===== Inline Function End for 3.7. BPICK ===== */
+
+/* ===== Inline Function Start for 3.8. CLROV ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_OV_FLAG_SC
+ * \brief CLROV (Clear OV flag)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * CLROV # pseudo mnemonic
+ * ~~~
+ *
+ * **Purpose**:\n
+ * This pseudo instruction is an alias to `CSRRCI x0, ucode, 1` instruction.
+ *
+ *
+ */
+__STATIC_FORCEINLINE void __RV_CLROV(void)
+{
+    __ASM volatile("clrov ");
+}
+/* ===== Inline Function End for 3.8. CLROV ===== */
+
+/* ===== Inline Function Start for 3.9. CLRS8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC
+ * \brief CLRS8 (SIMD 8-bit Count Leading Redundant Sign)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * CLRS8 Rd, Rs1
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Count the number of redundant sign bits of the 8-bit elements of a general register.
+ *
+ * **Description**:\n
+ * Starting from the bits next to the sign bits of the 8-bit elements of Rs1, this instruction
+ * counts the number of redundant sign bits and writes the result to the corresponding 8-bit elements
+ * of Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * snum[x] = Rs1.B[x];
+ * cnt[x] = 0;
+ * for (i = 6 to 0) {
+ *   if (snum[x](i) == snum[x](7)) {
+ *     cnt[x] = cnt[x] + 1;
+ *   } else {
+ *     break;
+ *   }
+ * }
+ * Rd.B[x] = cnt[x];
+ * for RV32: x=3...0
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_CLRS8(unsigned long a)
+{
+    register unsigned long result;
+    __ASM volatile("clrs8 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 3.9. CLRS8 ===== */
+
+/* ===== Inline Function Start for 3.10. CLRS16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC
+ * \brief CLRS16 (SIMD 16-bit Count Leading Redundant Sign)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * CLRS16 Rd, Rs1
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Count the number of redundant sign bits of the 16-bit elements of a general register.
+ *
+ * **Description**:\n
+ * Starting from the bits next to the sign bits of the 16-bit elements of Rs1, this
+ * instruction counts the number of redundant sign bits and writes the result to the corresponding 16-
+ * bit elements of Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * snum[x] = Rs1.H[x];
+ * cnt[x] = 0;
+ * for (i = 14 to 0) {
+ *   if (snum[x](i) == snum[x](15)) {
+ *     cnt[x] = cnt[x] + 1;
+ *   } else {
+ *     break;
+ *   }
+ * }
+ * Rd.H[x] = cnt[x];
+ * for RV32: x=1...0
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_CLRS16(unsigned long a)
+{
+    register unsigned long result;
+    __ASM volatile("clrs16 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 3.10. CLRS16 ===== */
+
+/* ===== Inline Function Start for 3.11. CLRS32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC
+ * \brief CLRS32 (SIMD 32-bit Count Leading Redundant Sign)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * CLRS32 Rd, Rs1
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Count the number of redundant sign bits of the 32-bit elements of a general register.
+ *
+ * **Description**:\n
+ * Starting from the bits next to the sign bits of the 32-bit elements of Rs1, this
+ * instruction counts the number of redundant sign bits and writes the result to the corresponding 32-
+ * bit elements of Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * snum[x] = Rs1.W[x];
+ * cnt[x] = 0;
+ * for (i = 30 to 0) {
+ *   if (snum[x](i) == snum[x](31)) {
+ *     cnt[x] = cnt[x] + 1;
+ *   } else {
+ *     break;
+ *   }
+ * }
+ * Rd.W[x] = cnt[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_CLRS32(unsigned long a)
+{
+    register unsigned long result;
+    __ASM volatile("clrs32 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 3.11. CLRS32 ===== */
+
+/* ===== Inline Function Start for 3.12. CLO8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC
+ * \brief CLO8 (SIMD 8-bit Count Leading One)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * CLO8 Rd, Rs1
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Count the number of leading one bits of the 8-bit elements of a general register.
+ *
+ * **Description**:\n
+ * Starting from the most significant bits of the 8-bit elements of Rs1, this instruction
+ * counts the number of leading one bits and writes the results to the corresponding 8-bit elements of
+ * Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * snum[x] = Rs1.B[x];
+ * cnt[x] = 0;
+ *   for (i = 7 to 0) {
+ *   if (snum[x](i) == 1) {
+ *     cnt[x] = cnt[x] + 1;
+ *   } else {
+ *     break;
+ *   }
+ * }
+ * Rd.B[x] = cnt[x];
+ * for RV32: x=3...0
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_CLO8(unsigned long a)
+{
+    register unsigned long result;
+    __ASM volatile("clo8 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 3.12. CLO8 ===== */
+
+/* ===== Inline Function Start for 3.13. CLO16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC
+ * \brief CLO16 (SIMD 16-bit Count Leading One)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * CLO16 Rd, Rs1
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Count the number of leading one bits of the 16-bit elements of a general register.
+ *
+ * **Description**:\n
+ * Starting from the most significant bits of the 16-bit elements of Rs1, this instruction
+ * counts the number of leading one bits and writes the results to the corresponding 16-bit elements
+ * of Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * snum[x] = Rs1.H[x];
+ * cnt[x] = 0;
+ * for (i = 15 to 0) {
+ *   if (snum[x](i) == 1) {
+ *     cnt[x] = cnt[x] + 1;
+ *   } else {
+ *     break;
+ *   }
+ * }
+ * Rd.H[x] = cnt[x];
+ * for RV32: x=1...0
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_CLO16(unsigned long a)
+{
+    register unsigned long result;
+    __ASM volatile("clo16 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 3.13. CLO16 ===== */
+
+/* ===== Inline Function Start for 3.14. CLO32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC
+ * \brief CLO32 (SIMD 32-bit Count Leading One)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * CLO32 Rd, Rs1
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Count the number of leading one bits of the 32-bit elements of a general register.
+ *
+ * **Description**:\n
+ * Starting from the most significant bits of the 32-bit elements of Rs1, this instruction
+ * counts the number of leading one bits and writes the results to the corresponding 32-bit elements
+ * of Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * snum[x] = Rs1.W[x];
+ * cnt[x] = 0;
+ * for (i = 31 to 0) {
+ *   if (snum[x](i) == 1) {
+ *     cnt[x] = cnt[x] + 1;
+ *   } else {
+ *     break;
+ *   }
+ * }
+ * Rd.W[x] = cnt[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_CLO32(unsigned long a)
+{
+    register unsigned long result;
+    __ASM volatile("clo32 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 3.14. CLO32 ===== */
+
+/* ===== Inline Function Start for 3.15. CLZ8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC
+ * \brief CLZ8 (SIMD 8-bit Count Leading Zero)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * CLZ8 Rd, Rs1
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Count the number of leading zero bits of the 8-bit elements of a general register.
+ *
+ * **Description**:\n
+ * Starting from the most significant bits of the 8-bit elements of Rs1, this instruction
+ * counts the number of leading zero bits and writes the results to the corresponding 8-bit elements of
+ * Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * snum[x] = Rs1.B[x];
+ * cnt[x] = 0;
+ * for (i = 7 to 0) {
+ *   if (snum[x](i) == 0) {
+ *     cnt[x] = cnt[x] + 1;
+ *   } else {
+ *     break;
+ *   }
+ * }
+ * Rd.B[x] = cnt[x];
+ * for RV32: x=3...0
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_CLZ8(unsigned long a)
+{
+    register unsigned long result;
+    __ASM volatile("clz8 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 3.15. CLZ8 ===== */
+
+/* ===== Inline Function Start for 3.16. CLZ16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC
+ * \brief CLZ16 (SIMD 16-bit Count Leading Zero)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * CLZ16 Rd, Rs1
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Count the number of leading zero bits of the 16-bit elements of a general register.
+ *
+ * **Description**:\n
+ * Starting from the most significant bits of the 16-bit elements of Rs1, this instruction
+ * counts the number of leading zero bits and writes the results to the corresponding 16-bit elements
+ * of Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * snum[x] = Rs1.H[x];
+ * cnt[x] = 0;
+ * for (i = 15 to 0) {
+ *   if (snum[x](i) == 0) {
+ *     cnt[x] = cnt[x] + 1;
+ *   } else {
+ *     break;
+ *   }
+ * }
+ * Rd.H[x] = cnt[x];
+ * for RV32: x=1...0
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_CLZ16(unsigned long a)
+{
+    register unsigned long result;
+    __ASM volatile("clz16 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 3.16. CLZ16 ===== */
+
+/* ===== Inline Function Start for 3.17. CLZ32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC
+ * \brief CLZ32 (SIMD 32-bit Count Leading Zero)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * CLZ32 Rd, Rs1
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Count the number of leading zero bits of the 32-bit elements of a general register.
+ *
+ * **Description**:\n
+ * Starting from the most significant bits of the 32-bit elements of Rs1, this instruction
+ * counts the number of leading zero bits and writes the results to the corresponding 32-bit elements
+ * of Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * snum[x] = Rs1.W[x];
+ * cnt[x] = 0;
+ * for (i = 31 to 0) {
+ *   if (snum[x](i) == 0) {
+ *     cnt[x] = cnt[x] + 1;
+ *   } else {
+ *     break;
+ *   }
+ * }
+ * Rd.W[x] = cnt[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_CLZ32(unsigned long a)
+{
+    register unsigned long result;
+    __ASM volatile("clz32 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 3.17. CLZ32 ===== */
+
+/* ===== Inline Function Start for 3.18. CMPEQ8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_CMP
+ * \brief CMPEQ8 (SIMD 8-bit Integer Compare Equal)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * CMPEQ8 Rs, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit integer elements equal comparisons simultaneously.
+ *
+ * **Description**:\n
+ * This instruction compares the 8-bit integer elements in Rs1 with the 8-bit integer
+ * elements in Rs2 to see if they are equal. If they are equal, the result is 0xFF; otherwise, the result is
+ * 0x0. The 8-bit element comparison results are written to Rd.
+ *
+ * **Note**:\n
+ * This instruction can be used for either signed or unsigned numbers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.B[x] = (Rs1.B[x] == Rs2.B[x])? 0xff : 0x0;
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_CMPEQ8(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("cmpeq8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.18. CMPEQ8 ===== */
+
+/* ===== Inline Function Start for 3.19. CMPEQ16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_CMP
+ * \brief CMPEQ16 (SIMD 16-bit Integer Compare Equal)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * CMPEQ16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit integer elements equal comparisons simultaneously.
+ *
+ * **Description**:\n
+ * This instruction compares the 16-bit integer elements in Rs1 with the 16-bit integer
+ * elements in Rs2 to see if they are equal. If they are equal, the result is 0xFFFF; otherwise, the result
+ * is 0x0. The 16-bit element comparison results are written to Rt.
+ *
+ * **Note**:\n
+ * This instruction can be used for either signed or unsigned numbers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.H[x] = (Rs1.H[x] == Rs2.H[x])? 0xffff : 0x0;
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_CMPEQ16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("cmpeq16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.19. CMPEQ16 ===== */
+
+/* ===== Inline Function Start for 3.20. CRAS16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief CRAS16 (SIMD 16-bit Cross Addition & Subtraction)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * CRAS16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit integer element addition and 16-bit integer element subtraction in a 32-bit
+ * chunk simultaneously. Operands are from crossed positions in 32-bit chunks.
+ *
+ * **Description**:\n
+ * This instruction adds the 16-bit integer element in [31:16] of 32-bit chunks in Rs1 with
+ * the 16-bit integer element in [15:0] of 32-bit chunks in Rs2, and writes the result to [31:16] of 32-bit
+ * chunks in Rd; at the same time, it subtracts the 16-bit integer element in [31:16] of 32-bit chunks in
+ * Rs2 from the 16-bit integer element in [15:0] of 32-bit chunks, and writes the result to [15:0] of 32-
+ * bit chunks in Rd.
+ *
+ * **Note**:\n
+ * This instruction can be used for either signed or unsigned operations.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x][31:16] = Rs1.W[x][31:16] + Rs2.W[x][15:0];
+ * Rd.W[x][15:0] = Rs1.W[x][15:0] - Rs2.W[x][31:16];
+ * for RV32, x=0
+ * for RV64, x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_CRAS16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("cras16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.20. CRAS16 ===== */
+
+/* ===== Inline Function Start for 3.21. CRSA16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief CRSA16 (SIMD 16-bit Cross Subtraction & Addition)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * CRSA16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit integer element subtraction and 16-bit integer element addition in a 32-bit
+ * chunk simultaneously. Operands are from crossed positions in 32-bit chunks.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 16-bit integer element in [15:0] of 32-bit chunks in Rs2
+ * from the 16-bit integer element in [31:16] of 32-bit chunks in Rs1, and writes the result to [31:16] of
+ * 32-bit chunks in Rd; at the same time, it adds the 16-bit integer element in [31:16] of 32-bit chunks
+ * in Rs2 with the 16-bit integer element in [15:0] of 32-bit chunks in Rs1, and writes the result to
+ * [15:0] of 32-bit chunks in Rd.
+ *
+ * **Note**:\n
+ * This instruction can be used for either signed or unsigned operations.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x][31:16] = Rs1.W[x][31:16] - Rs2.W[x][15:0];
+ * Rd.W[x][15:0] = Rs1.W[x][15:0] + Rs2.W[x][31:16];
+ * for RV32, x=0
+ * for RV64, x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_CRSA16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("crsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.21. CRSA16 ===== */
+
+/* ===== Inline Function Start for 3.22. INSB ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
+ * \brief INSB (Insert Byte)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * (RV32) INSB Rd, Rs1, imm[1:0]
+ * (RV64) INSB Rd, Rs1, imm[2:0]
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Insert byte 0 of a 32-bit or 64-bit register into one of the byte elements of another register.
+ *
+ * **Description**:\n
+ * This instruction inserts byte 0 of Rs1 into byte `imm[1:0]` (RV32) or `imm[2:0]` (RV64)
+ * of Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * bpos = imm[1:0]; (RV32)
+ * bpos = imm[2:0]; (RV64)
+ * Rd.B[bpos] = Rs1.B[0]
+ * ~~~
+ *
+ * \param [in]  t    unsigned long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+#define __RV_INSB(t, a, b)    \
+    ({    \
+        register unsigned long __t = (unsigned long)(t);    \
+        register unsigned long __a = (unsigned long)(a);    \
+        __ASM volatile("insb %0, %1, %2" : "+r"(__t) : "r"(__a), "K"(b));    \
+        __t;    \
+    })
+/* ===== Inline Function End for 3.22. INSB ===== */
+
+/* ===== Inline Function Start for 3.23. KABS8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC
+ * \brief KABS8 (SIMD 8-bit Saturating Absolute)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KABS8 Rd, Rs1
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Get the absolute value of 8-bit signed integer elements simultaneously.
+ *
+ * **Description**:\n
+ * This instruction calculates the absolute value of 8-bit signed integer elements stored
+ * in Rs1 and writes the element results to Rd. If the input number is 0x80, this instruction generates
+ * 0x7f as the output and sets the OV bit to 1.
+ *
+ * **Operations**:\n
+ * ~~~
+ * src = Rs1.B[x];
+ * if (src == 0x80) {
+ *   src = 0x7f;
+ *   OV = 1;
+ * } else if (src[7] == 1)
+ *   src = -src;
+ * }
+ * Rd.B[x] = src;
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KABS8(unsigned long a)
+{
+    register unsigned long result;
+    __ASM volatile("kabs8 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 3.23. KABS8 ===== */
+
+/* ===== Inline Function Start for 3.24. KABS16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC
+ * \brief KABS16 (SIMD 16-bit Saturating Absolute)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KABS16 Rd, Rs1
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Get the absolute value of 16-bit signed integer elements simultaneously.
+ *
+ * **Description**:\n
+ * This instruction calculates the absolute value of 16-bit signed integer elements stored
+ * in Rs1 and writes the element results to Rd. If the input number is 0x8000, this instruction
+ * generates 0x7fff as the output and sets the OV bit to 1.
+ *
+ * **Operations**:\n
+ * ~~~
+ * src = Rs1.H[x];
+ * if (src == 0x8000) {
+ *   src = 0x7fff;
+ *   OV = 1;
+ * } else if (src[15] == 1)
+ *   src = -src;
+ * }
+ * Rd.H[x] = src;
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KABS16(unsigned long a)
+{
+    register unsigned long result;
+    __ASM volatile("kabs16 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 3.24. KABS16 ===== */
+
+/* ===== Inline Function Start for 3.25. KABSW ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
+ * \brief KABSW (Scalar 32-bit Absolute Value with Saturation)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KABSW Rd, Rs1
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Get the absolute value of a signed 32-bit integer in a general register.
+ *
+ * **Description**:\n
+ * This instruction calculates the absolute value of a signed 32-bit integer stored in Rs1.
+ * The result is sign-extended (for RV64) and written to Rd. This instruction with the minimum
+ * negative integer input of 0x80000000 will produce a saturated output of maximum positive integer
+ * of 0x7fffffff and the OV flag will be set to 1.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if (Rs1.W[0] >= 0) {
+ *   res = Rs1.W[0];
+ * } else {
+ *   If (Rs1.W[0] == 0x80000000) {
+ *     res = 0x7fffffff;
+ *     OV = 1;
+ *   } else {
+ *     res = -Rs1.W[0];
+ *   }
+ * }
+ * Rd = SE32(res);
+ * ~~~
+ *
+ * \param [in]  a    signed long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KABSW(signed long a)
+{
+    register unsigned long result;
+    __ASM volatile("kabsw %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 3.25. KABSW ===== */
+
+/* ===== Inline Function Start for 3.26. KADD8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB
+ * \brief KADD8 (SIMD 8-bit Signed Saturating Addition)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KADD8 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit signed integer element saturating additions simultaneously.
+ *
+ * **Description**:\n
+ * This instruction adds the 8-bit signed integer elements in Rs1 with the 8-bit signed
+ * integer elements in Rs2. If any of the results are beyond the Q7 number range (-2^7 <= Q7 <= 2^7-1), they
+ * are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[x] = Rs1.B[x] + Rs2.B[x];
+ * if (res[x] > 127) {
+ *   res[x] = 127;
+ *   OV = 1;
+ * } else if (res[x] < -128) {
+ *   res[x] = -128;
+ *   OV = 1;
+ * }
+ * Rd.B[x] = res[x];
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KADD8(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("kadd8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.26. KADD8 ===== */
+
+/* ===== Inline Function Start for 3.27. KADD16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief KADD16 (SIMD 16-bit Signed Saturating Addition)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KADD16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit signed integer element saturating additions simultaneously.
+ *
+ * **Description**:\n
+ * This instruction adds the 16-bit signed integer elements in Rs1 with the 16-bit signed
+ * integer elements in Rs2. If any of the results are beyond the Q15 number range (-2^15 <= Q15 <= 2^15-1),
+ * they are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[x] = Rs1.H[x] + Rs2.H[x];
+ * if (res[x] > 32767) {
+ *   res[x] = 32767;
+ *   OV = 1;
+ * } else if (res[x] < -32768) {
+ *   res[x] = -32768;
+ *   OV = 1;
+ * }
+ * Rd.H[x] = res[x];
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KADD16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("kadd16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.27. KADD16 ===== */
+
+/* ===== Inline Function Start for 3.28. KADD64 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB
+ * \brief KADD64 (64-bit Signed Saturating Addition)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KADD64 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Add two 64-bit signed integers. The result is saturated to the Q63 range.
+ *
+ * **RV32 Description**:\n
+ * This instruction adds the 64-bit signed integer of an even/odd pair of registers
+ * specified by Rs1(4,1) with the 64-bit signed integer of an even/odd pair of registers specified by
+ * Rs2(4,1). If the 64-bit result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the
+ * range and the OV bit is set to 1. The saturated result is written to an even/odd pair of registers
+ * specified by Rd(4,1).
+ * Rx(4,1), i.e., value d, determines the even/odd pair group of two registers. Specifically, the register
+ * pair includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
+ * of the pair contains the low 32-bit of the result.
+ *
+ * **RV64 Description**:\n
+ * This instruction adds the 64-bit signed integer in Rs1 with the 64-bit signed
+ * integer in Rs2. If the result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the
+ * range and the OV bit is set to 1. The saturated result is written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * RV32:
+ *  t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
+ *  a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1);
+ *  b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1);
+ *  result = R[a_H].R[a_L] + R[b_H].R[b_L];
+ *  if (result > (2^63)-1) {
+ *    result = (2^63)-1; OV = 1;
+ *  } else if (result < -2^63) {
+ *    result = -2^63; OV = 1;
+ *  }
+ *  R[t_H].R[t_L] = result;
+ * RV64:
+ *  result = Rs1 + Rs2;
+ *  if (result > (2^63)-1) {
+ *    result = (2^63)-1; OV = 1;
+ *  } else if (result < -2^63) {
+ *    result = -2^63; OV = 1;
+ *  }
+ *  Rd = result;
+ * ~~~
+ *
+ * \param [in]  a    long long type of value stored in a
+ * \param [in]  b    long long type of value stored in b
+ * \return value stored in long long type
+ */
+__STATIC_FORCEINLINE long long __RV_KADD64(long long a, long long b)
+{
+    register long long result;
+    __ASM volatile("kadd64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.28. KADD64 ===== */
+
+/* ===== Inline Function Start for 3.29. KADDH ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU
+ * \brief KADDH (Signed Addition with Q15 Saturation)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KADDH Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Add the signed lower 32-bit content of two registers with Q15 saturation.
+ *
+ * **Description**:\n
+ * The signed lower 32-bit content of Rs1 is added with the signed lower 32-bit content of
+ * Rs2. And the result is saturated to the 16-bit signed integer range of [-2^15, 2^15-1] and then sign-
+ * extended and written to Rd. If saturation happens, this instruction sets the OV flag.
+ *
+ * **Operations**:\n
+ * ~~~
+ * tmp = Rs1.W[0] + Rs2.W[0];
+ * if (tmp > 32767) {
+ *   res = 32767;
+ *   OV = 1;
+ * } else if (tmp < -32768) {
+ *   res = -32768;
+ *   OV = 1
+ * } else {
+ *   res = tmp;
+ * }
+ * Rd = SE(tmp[15:0]);
+ * ~~~
+ *
+ * \param [in]  a    int type of value stored in a
+ * \param [in]  b    int type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KADDH(int a, int b)
+{
+    register long result;
+    __ASM volatile("kaddh %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.29. KADDH ===== */
+
+/* ===== Inline Function Start for 3.30. KADDW ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
+ * \brief KADDW (Signed Addition with Q31 Saturation)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KADDW Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Add the lower 32-bit signed content of two registers with Q31 saturation.
+ *
+ * **Description**:\n
+ * The lower 32-bit signed content of Rs1 is added with the lower 32-bit signed content of
+ * Rs2. And the result is saturated to the 32-bit signed integer range of [-2^31, 2^31-1] and then sign-
+ * extended and written to Rd. If saturation happens, this instruction sets the OV flag.
+ *
+ * **Operations**:\n
+ * ~~~
+ * tmp = Rs1.W[0] + Rs2.W[0];
+ * if (tmp > (2^31)-1) {
+ *   res = (2^31)-1;
+ *   OV = 1;
+ * } else if (tmp < -2^31) {
+ *   res = -2^31;
+ *   OV = 1
+ * } else {
+ *   res = tmp;
+ * }
+ * Rd = res[31:0]; // RV32
+ * Rd = SE(res[31:0]) // RV64
+ * ~~~
+ *
+ * \param [in]  a    int type of value stored in a
+ * \param [in]  b    int type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KADDW(int a, int b)
+{
+    register long result;
+    __ASM volatile("kaddw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.30. KADDW ===== */
+
+/* ===== Inline Function Start for 3.31. KCRAS16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief KCRAS16 (SIMD 16-bit Signed Saturating Cross Addition & Subtraction)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KCRAS16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit signed integer element saturating addition and 16-bit signed integer element
+ * saturating subtraction in a 32-bit chunk simultaneously. Operands are from crossed positions in 32-
+ * bit chunks.
+ *
+ * **Description**:\n
+ * This instruction adds the 16-bit signed integer element in [31:16] of 32-bit chunks in
+ * Rs1 with the 16-bit signed integer element in [15:0] of 32-bit chunks in Rs2; at the same time, it
+ * subtracts the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs2 from the 16-bit signed
+ * integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the Q15 number
+ * range (-2^15 <= Q15 <= 2^15-1), they are saturated to the range and the OV bit is set to 1. The saturated
+ * results are written to [31:16] of 32-bit chunks in Rd for addition and [15:0] of 32-bit chunks in Rd for
+ * subtraction.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res1 = Rs1.W[x][31:16] + Rs2.W[x][15:0];
+ * res2 = Rs1.W[x][15:0] - Rs2.W[x][31:16];
+ * for (res in [res1, res2]) {
+ *   if (res > (2^15)-1) {
+ *     res = (2^15)-1;
+ *     OV = 1;
+ *   } else if (res < -2^15) {
+ *     res = -2^15;
+ *     OV = 1;
+ *   }
+ * }
+ * Rd.W[x][31:16] = res1;
+ * Rd.W[x][15:0] = res2;
+ * for RV32, x=0
+ * for RV64, x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KCRAS16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("kcras16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.31. KCRAS16 ===== */
+
+/* ===== Inline Function Start for 3.32. KCRSA16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief KCRSA16 (SIMD 16-bit Signed Saturating Cross Subtraction & Addition)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KCRSA16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit signed integer element saturating subtraction and 16-bit signed integer element
+ * saturating addition in a 32-bit chunk simultaneously. Operands are from crossed positions in 32-bit
+ * chunks.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 16-bit signed integer element in [15:0] of 32-bit chunks
+ * in Rs2 from the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs1; at the same time, it
+ * adds the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs2 with the 16-bit signed
+ * integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the Q15 number
+ * range (-2^15 <= Q15 <= 2^15-1), they are saturated to the range and the OV bit is set to 1. The saturated
+ * results are written to [31:16] of 32-bit chunks in Rd for subtraction and [15:0] of 32-bit chunks in Rd
+ * for addition.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res1 = Rs1.W[x][31:16] - Rs2.W[x][15:0];
+ * res2 = Rs1.W[x][15:0] + Rs2.W[x][31:16];
+ * for (res in [res1, res2]) {
+ *   if (res > (2^15)-1) {
+ *     res = (2^15)-1;
+ *     OV = 1;
+ *   } else if (res < -2^15) {
+ *     res = -2^15;
+ *     OV = 1;
+ *   }
+ * }
+ * Rd.W[x][31:16] = res1;
+ * Rd.W[x][15:0] = res2;
+ * for RV32, x=0
+ * for RV64, x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KCRSA16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("kcrsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.32. KCRSA16 ===== */
+
+/* ===== Inline Function Start for 3.33.1. KDMBB ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
+ * \brief KDMBB (Signed Saturating Double Multiply B16 x B16)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KDMxy Rd, Rs1, Rs2 (xy = BB, BT, TT)
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
+ * of the lower 32-bit chunk in registers and then double and saturate the Q31 result. The result is
+ * written into the destination register for RV32 or sign-extended to 64-bits and written into the
+ * destination register for RV64. If saturation happens, an overflow flag OV will be set.
+ *
+ * **Description**:\n
+ * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with
+ * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then
+ * doubled and saturated into a Q31 value. The Q31 value is then written into Rd (sign-extended in
+ * RV64). When both the two Q15 inputs are 0x8000, saturation will happen. The result will be
+ * saturated to 0x7FFFFFFF and the overflow flag OV will be set.
+ *
+ * **Operations**:\n
+ * ~~~
+ * aop = Rs1.H[0]; bop = Rs2.H[0]; // KDMBB
+ * aop = Rs1.H[0]; bop = Rs2.H[1]; // KDMBT
+ * aop = Rs1.H[1]; bop = Rs2.H[1]; // KDMTT
+ * If (0x8000 != aop | 0x8000 != bop) {
+ *   Mresult = aop * bop;
+ *   resQ31 = Mresult << 1;
+ *   Rd = resQ31; // RV32
+ *   Rd = SE(resQ31); // RV64
+ * } else {
+ *   resQ31 = 0x7FFFFFFF;
+ *   Rd = resQ31; // RV32
+ *   Rd = SE(resQ31); // RV64
+ *   OV = 1;
+ * }
+ * ~~~
+ *
+ * \param [in]  a    unsigned int type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KDMBB(unsigned int a, unsigned int b)
+{
+    register long result;
+    __ASM volatile("kdmbb %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.33.1. KDMBB ===== */
+
+/* ===== Inline Function Start for 3.33.2. KDMBT ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
+ * \brief KDMBT (Signed Saturating Double Multiply B16 x T16)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KDMxy Rd, Rs1, Rs2 (xy = BB, BT, TT)
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
+ * of the lower 32-bit chunk in registers and then double and saturate the Q31 result. The result is
+ * written into the destination register for RV32 or sign-extended to 64-bits and written into the
+ * destination register for RV64. If saturation happens, an overflow flag OV will be set.
+ *
+ * **Description**:\n
+ * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with
+ * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then
+ * doubled and saturated into a Q31 value. The Q31 value is then written into Rd (sign-extended in
+ * RV64). When both the two Q15 inputs are 0x8000, saturation will happen. The result will be
+ * saturated to 0x7FFFFFFF and the overflow flag OV will be set.
+ *
+ * **Operations**:\n
+ * ~~~
+ * aop = Rs1.H[0]; bop = Rs2.H[0]; // KDMBB
+ * aop = Rs1.H[0]; bop = Rs2.H[1]; // KDMBT
+ * aop = Rs1.H[1]; bop = Rs2.H[1]; // KDMTT
+ * If (0x8000 != aop | 0x8000 != bop) {
+ *   Mresult = aop * bop;
+ *   resQ31 = Mresult << 1;
+ *   Rd = resQ31; // RV32
+ *   Rd = SE(resQ31); // RV64
+ * } else {
+ *   resQ31 = 0x7FFFFFFF;
+ *   Rd = resQ31; // RV32
+ *   Rd = SE(resQ31); // RV64
+ *   OV = 1;
+ * }
+ * ~~~
+ *
+ * \param [in]  a    unsigned int type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KDMBT(unsigned int a, unsigned int b)
+{
+    register long result;
+    __ASM volatile("kdmbt %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.33.2. KDMBT ===== */
+
+/* ===== Inline Function Start for 3.33.3. KDMTT ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
+ * \brief KDMTT (Signed Saturating Double Multiply T16 x T16)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KDMxy Rd, Rs1, Rs2 (xy = BB, BT, TT)
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
+ * of the lower 32-bit chunk in registers and then double and saturate the Q31 result. The result is
+ * written into the destination register for RV32 or sign-extended to 64-bits and written into the
+ * destination register for RV64. If saturation happens, an overflow flag OV will be set.
+ *
+ * **Description**:\n
+ * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with
+ * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then
+ * doubled and saturated into a Q31 value. The Q31 value is then written into Rd (sign-extended in
+ * RV64). When both the two Q15 inputs are 0x8000, saturation will happen. The result will be
+ * saturated to 0x7FFFFFFF and the overflow flag OV will be set.
+ *
+ * **Operations**:\n
+ * ~~~
+ * aop = Rs1.H[0]; bop = Rs2.H[0]; // KDMBB
+ * aop = Rs1.H[0]; bop = Rs2.H[1]; // KDMBT
+ * aop = Rs1.H[1]; bop = Rs2.H[1]; // KDMTT
+ * If (0x8000 != aop | 0x8000 != bop) {
+ *   Mresult = aop * bop;
+ *   resQ31 = Mresult << 1;
+ *   Rd = resQ31; // RV32
+ *   Rd = SE(resQ31); // RV64
+ * } else {
+ *   resQ31 = 0x7FFFFFFF;
+ *   Rd = resQ31; // RV32
+ *   Rd = SE(resQ31); // RV64
+ *   OV = 1;
+ * }
+ * ~~~
+ *
+ * \param [in]  a    unsigned int type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KDMTT(unsigned int a, unsigned int b)
+{
+    register long result;
+    __ASM volatile("kdmtt %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.33.3. KDMTT ===== */
+
+/* ===== Inline Function Start for 3.34.1. KDMABB ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
+ * \brief KDMABB (Signed Saturating Double Multiply Addition B16 x B16)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KDMAxy Rd, Rs1, Rs2 (xy = BB, BT, TT)
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
+ * of the lower 32-bit chunk in registers and then double and saturate the Q31 result, add the result
+ * with the sign-extended lower 32-bit chunk destination register and write the saturated addition
+ * result into the destination register. If saturation happens, an overflow flag OV will be set.
+ *
+ * **Description**:\n
+ * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with
+ * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then
+ * doubled and saturated into a Q31 value. The Q31 value is then added with the content of Rd. If the
+ * addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and
+ * the OV flag is set to 1. The result after saturation is written to Rd.
+ * When both the two Q15 inputs are 0x8000, saturation will happen and the overflow flag OV will be
+ * set.
+ *
+ * **Operations**:\n
+ * ~~~
+ * aop = Rs1.H[0]; bop = Rs2.H[0]; // KDMABB
+ * aop = Rs1.H[0]; bop = Rs2.H[1]; // KDMABT
+ * aop = Rs1.H[1]; bop = Rs2.H[1]; // KDMATT
+ * If (0x8000 != aop | 0x8000 != bop) {
+ *   Mresult = aop * bop;
+ *   resQ31 = Mresult << 1;
+ * } else {
+ *   resQ31 = 0x7FFFFFFF;
+ *   OV = 1;
+ * }
+ * resadd = Rd + resQ31; // RV32
+ * resadd = Rd.W[0] + resQ31; // RV64
+ * if (resadd > (2^31)-1) {
+ *   resadd = (2^31)-1;
+ *   OV = 1;
+ * } else if (resadd < -2^31) {
+ *   resadd = -2^31;
+ *   OV = 1;
+ * }
+ * Rd = resadd; // RV32
+ * Rd = SE(resadd); // RV64
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned int type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KDMABB(long t, unsigned int a, unsigned int b)
+{
+    __ASM volatile("kdmabb %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.34.1. KDMABB ===== */
+
+/* ===== Inline Function Start for 3.34.2. KDMABT ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
+ * \brief KDMABT (Signed Saturating Double Multiply Addition B16 x T16)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KDMAxy Rd, Rs1, Rs2 (xy = BB, BT, TT)
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
+ * of the lower 32-bit chunk in registers and then double and saturate the Q31 result, add the result
+ * with the sign-extended lower 32-bit chunk destination register and write the saturated addition
+ * result into the destination register. If saturation happens, an overflow flag OV will be set.
+ *
+ * **Description**:\n
+ * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with
+ * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then
+ * doubled and saturated into a Q31 value. The Q31 value is then added with the content of Rd. If the
+ * addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and
+ * the OV flag is set to 1. The result after saturation is written to Rd.
+ * When both the two Q15 inputs are 0x8000, saturation will happen and the overflow flag OV will be
+ * set.
+ *
+ * **Operations**:\n
+ * ~~~
+ * aop = Rs1.H[0]; bop = Rs2.H[0]; // KDMABB
+ * aop = Rs1.H[0]; bop = Rs2.H[1]; // KDMABT
+ * aop = Rs1.H[1]; bop = Rs2.H[1]; // KDMATT
+ * If (0x8000 != aop | 0x8000 != bop) {
+ *   Mresult = aop * bop;
+ *   resQ31 = Mresult << 1;
+ * } else {
+ *   resQ31 = 0x7FFFFFFF;
+ *   OV = 1;
+ * }
+ * resadd = Rd + resQ31; // RV32
+ * resadd = Rd.W[0] + resQ31; // RV64
+ * if (resadd > (2^31)-1) {
+ *   resadd = (2^31)-1;
+ *   OV = 1;
+ * } else if (resadd < -2^31) {
+ *   resadd = -2^31;
+ *   OV = 1;
+ * }
+ * Rd = resadd; // RV32
+ * Rd = SE(resadd); // RV64
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned int type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KDMABT(long t, unsigned int a, unsigned int b)
+{
+    __ASM volatile("kdmabt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.34.2. KDMABT ===== */
+
+/* ===== Inline Function Start for 3.34.3. KDMATT ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
+ * \brief KDMATT (Signed Saturating Double Multiply Addition T16 x T16)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KDMAxy Rd, Rs1, Rs2 (xy = BB, BT, TT)
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
+ * of the lower 32-bit chunk in registers and then double and saturate the Q31 result, add the result
+ * with the sign-extended lower 32-bit chunk destination register and write the saturated addition
+ * result into the destination register. If saturation happens, an overflow flag OV will be set.
+ *
+ * **Description**:\n
+ * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with
+ * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then
+ * doubled and saturated into a Q31 value. The Q31 value is then added with the content of Rd. If the
+ * addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and
+ * the OV flag is set to 1. The result after saturation is written to Rd.
+ * When both the two Q15 inputs are 0x8000, saturation will happen and the overflow flag OV will be
+ * set.
+ *
+ * **Operations**:\n
+ * ~~~
+ * aop = Rs1.H[0]; bop = Rs2.H[0]; // KDMABB
+ * aop = Rs1.H[0]; bop = Rs2.H[1]; // KDMABT
+ * aop = Rs1.H[1]; bop = Rs2.H[1]; // KDMATT
+ * If (0x8000 != aop | 0x8000 != bop) {
+ *   Mresult = aop * bop;
+ *   resQ31 = Mresult << 1;
+ * } else {
+ *   resQ31 = 0x7FFFFFFF;
+ *   OV = 1;
+ * }
+ * resadd = Rd + resQ31; // RV32
+ * resadd = Rd.W[0] + resQ31; // RV64
+ * if (resadd > (2^31)-1) {
+ *   resadd = (2^31)-1;
+ *   OV = 1;
+ * } else if (resadd < -2^31) {
+ *   resadd = -2^31;
+ *   OV = 1;
+ * }
+ * Rd = resadd; // RV32
+ * Rd = SE(resadd); // RV64
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned int type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KDMATT(long t, unsigned int a, unsigned int b)
+{
+    __ASM volatile("kdmatt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.34.3. KDMATT ===== */
+
+/* ===== Inline Function Start for 3.35.1. KHM8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MULTIPLY
+ * \brief KHM8 (SIMD Signed Saturating Q7 Multiply)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KHM8 Rd, Rs1, Rs2
+ * KHMX8 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do Q7xQ7 element multiplications simultaneously. The Q14 results are then reduced to Q7
+ * numbers again.
+ *
+ * **Description**:\n
+ * For the `KHM8` instruction, multiply the top 8-bit Q7 content of 16-bit chunks in Rs1
+ * with the top 8-bit Q7 content of 16-bit chunks in Rs2. At the same time, multiply the bottom 8-bit Q7
+ * content of 16-bit chunks in Rs1 with the bottom 8-bit Q7 content of 16-bit chunks in Rs2.
+ * For the `KHMX16` instruction, multiply the top 8-bit Q7 content of 16-bit chunks in Rs1 with the
+ * bottom 8-bit Q7 content of 16-bit chunks in Rs2. At the same time, multiply the bottom 8-bit Q7
+ * content of 16-bit chunks in Rs1 with the top 8-bit Q7 content of 16-bit chunks in Rs2.
+ * The Q14 results are then right-shifted 7-bits and saturated into Q7 values. The Q7 results are then
+ * written into Rd. When both the two Q7 inputs of a multiplication are 0x80, saturation will happen.
+ * The result will be saturated to 0x7F and the overflow flag OV will be set.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if (is `KHM8`) {
+ *   op1t = Rs1.B[x+1]; op2t = Rs2.B[x+1]; // top
+ *   op1b = Rs1.B[x]; op2b = Rs2.B[x]; // bottom
+ * } else if (is `KHMX8`) {
+ *   op1t = Rs1.H[x+1]; op2t = Rs2.H[x]; // Rs1 top
+ *   op1b = Rs1.H[x]; op2b = Rs2.H[x+1]; // Rs1 bottom
+ * }
+ * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) {
+ *   if (0x80 != aop | 0x80 != bop) {
+ *     res = (aop s* bop) >> 7;
+ *   } else {
+ *     res= 0x7F;
+ *     OV = 1;
+ *   }
+ * }
+ * Rd.H[x/2] = concat(rest, resb);
+ * for RV32, x=0,2
+ * for RV64, x=0,2,4,6
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KHM8(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("khm8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.35.1. KHM8 ===== */
+
+/* ===== Inline Function Start for 3.35.2. KHMX8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MULTIPLY
+ * \brief KHMX8 (SIMD Signed Saturating Crossed Q7 Multiply)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KHM8 Rd, Rs1, Rs2
+ * KHMX8 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do Q7xQ7 element multiplications simultaneously. The Q14 results are then reduced to Q7
+ * numbers again.
+ *
+ * **Description**:\n
+ * For the `KHM8` instruction, multiply the top 8-bit Q7 content of 16-bit chunks in Rs1
+ * with the top 8-bit Q7 content of 16-bit chunks in Rs2. At the same time, multiply the bottom 8-bit Q7
+ * content of 16-bit chunks in Rs1 with the bottom 8-bit Q7 content of 16-bit chunks in Rs2.
+ * For the `KHMX16` instruction, multiply the top 8-bit Q7 content of 16-bit chunks in Rs1 with the
+ * bottom 8-bit Q7 content of 16-bit chunks in Rs2. At the same time, multiply the bottom 8-bit Q7
+ * content of 16-bit chunks in Rs1 with the top 8-bit Q7 content of 16-bit chunks in Rs2.
+ * The Q14 results are then right-shifted 7-bits and saturated into Q7 values. The Q7 results are then
+ * written into Rd. When both the two Q7 inputs of a multiplication are 0x80, saturation will happen.
+ * The result will be saturated to 0x7F and the overflow flag OV will be set.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if (is `KHM8`) {
+ *   op1t = Rs1.B[x+1]; op2t = Rs2.B[x+1]; // top
+ *   op1b = Rs1.B[x]; op2b = Rs2.B[x]; // bottom
+ * } else if (is `KHMX8`) {
+ *   op1t = Rs1.H[x+1]; op2t = Rs2.H[x]; // Rs1 top
+ *   op1b = Rs1.H[x]; op2b = Rs2.H[x+1]; // Rs1 bottom
+ * }
+ * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) {
+ *   if (0x80 != aop | 0x80 != bop) {
+ *     res = (aop s* bop) >> 7;
+ *   } else {
+ *     res= 0x7F;
+ *     OV = 1;
+ *   }
+ * }
+ * Rd.H[x/2] = concat(rest, resb);
+ * for RV32, x=0,2
+ * for RV64, x=0,2,4,6
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KHMX8(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("khmx8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.35.2. KHMX8 ===== */
+
+/* ===== Inline Function Start for 3.36.1. KHM16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MULTIPLY
+ * \brief KHM16 (SIMD Signed Saturating Q15 Multiply)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KHM16 Rd, Rs1, Rs2
+ * KHMX16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do Q15xQ15 element multiplications simultaneously. The Q30 results are then reduced to
+ * Q15 numbers again.
+ *
+ * **Description**:\n
+ * For the `KHM16` instruction, multiply the top 16-bit Q15 content of 32-bit chunks in
+ * Rs1 with the top 16-bit Q15 content of 32-bit chunks in Rs2. At the same time, multiply the bottom
+ * 16-bit Q15 content of 32-bit chunks in Rs1 with the bottom 16-bit Q15 content of 32-bit chunks in
+ * Rs2.
+ * For the `KHMX16` instruction, multiply the top 16-bit Q15 content of 32-bit chunks in Rs1 with the
+ * bottom 16-bit Q15 content of 32-bit chunks in Rs2. At the same time, multiply the bottom 16-bit Q15
+ * content of 32-bit chunks in Rs1 with the top 16-bit Q15 content of 32-bit chunks in Rs2.
+ * The Q30 results are then right-shifted 15-bits and saturated into Q15 values. The Q15 results are
+ * then written into Rd. When both the two Q15 inputs of a multiplication are 0x8000, saturation will
+ * happen. The result will be saturated to 0x7FFF and the overflow flag OV will be set.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if (is `KHM16`) {
+ *   op1t = Rs1.H[x+1]; op2t = Rs2.H[x+1]; // top
+ *   op1b = Rs1.H[x]; op2b = Rs2.H[x]; // bottom
+ * } else if (is `KHMX16`) {
+ *   op1t = Rs1.H[x+1]; op2t = Rs2.H[x]; // Rs1 top
+ *   op1b = Rs1.H[x]; op2b = Rs2.H[x+1]; // Rs1 bottom
+ * }
+ * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) {
+ *   if (0x8000 != aop | 0x8000 != bop) {
+ *     res = (aop s* bop) >> 15;
+ *   } else {
+ *     res= 0x7FFF;
+ *     OV = 1;
+ *   }
+ * }
+ * Rd.W[x/2] = concat(rest, resb);
+ * for RV32: x=0
+ * for RV64: x=0,2
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KHM16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("khm16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.36.1. KHM16 ===== */
+
+/* ===== Inline Function Start for 3.36.2. KHMX16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MULTIPLY
+ * \brief KHMX16 (SIMD Signed Saturating Crossed Q15 Multiply)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KHM16 Rd, Rs1, Rs2
+ * KHMX16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do Q15xQ15 element multiplications simultaneously. The Q30 results are then reduced to
+ * Q15 numbers again.
+ *
+ * **Description**:\n
+ * For the `KHM16` instruction, multiply the top 16-bit Q15 content of 32-bit chunks in
+ * Rs1 with the top 16-bit Q15 content of 32-bit chunks in Rs2. At the same time, multiply the bottom
+ * 16-bit Q15 content of 32-bit chunks in Rs1 with the bottom 16-bit Q15 content of 32-bit chunks in
+ * Rs2.
+ * For the `KHMX16` instruction, multiply the top 16-bit Q15 content of 32-bit chunks in Rs1 with the
+ * bottom 16-bit Q15 content of 32-bit chunks in Rs2. At the same time, multiply the bottom 16-bit Q15
+ * content of 32-bit chunks in Rs1 with the top 16-bit Q15 content of 32-bit chunks in Rs2.
+ * The Q30 results are then right-shifted 15-bits and saturated into Q15 values. The Q15 results are
+ * then written into Rd. When both the two Q15 inputs of a multiplication are 0x8000, saturation will
+ * happen. The result will be saturated to 0x7FFF and the overflow flag OV will be set.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if (is `KHM16`) {
+ *   op1t = Rs1.H[x+1]; op2t = Rs2.H[x+1]; // top
+ *   op1b = Rs1.H[x]; op2b = Rs2.H[x]; // bottom
+ * } else if (is `KHMX16`) {
+ *   op1t = Rs1.H[x+1]; op2t = Rs2.H[x]; // Rs1 top
+ *   op1b = Rs1.H[x]; op2b = Rs2.H[x+1]; // Rs1 bottom
+ * }
+ * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) {
+ *   if (0x8000 != aop | 0x8000 != bop) {
+ *     res = (aop s* bop) >> 15;
+ *   } else {
+ *     res= 0x7FFF;
+ *     OV = 1;
+ *   }
+ * }
+ * Rd.W[x/2] = concat(rest, resb);
+ * for RV32: x=0
+ * for RV64: x=0,2
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KHMX16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("khmx16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.36.2. KHMX16 ===== */
+
+/* ===== Inline Function Start for 3.37.1. KHMBB ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU
+ * \brief KHMBB (Signed Saturating Half Multiply B16 x B16)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KHMxy Rd, Rs1, Rs2 (xy = BB, BT, TT)
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed Q15 number contents of two 16-bit data in the corresponding portion
+ * of the lower 32-bit chunk in registers and then right-shift 15 bits to turn the Q30 result into a Q15
+ * number again and saturate the Q15 result into the destination register. If saturation happens, an
+ * overflow flag OV will be set.
+ *
+ * **Description**:\n
+ * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with
+ * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then right-
+ * shifted 15-bits and saturated into a Q15 value. The Q15 value is then sing-extended and written into
+ * Rd. When both the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated
+ * to 0x7FFF and the overflow flag OV will be set.
+ *
+ * **Operations**:\n
+ * ~~~
+ * aop = Rs1.H[0]; bop = Rs2.H[0]; // KHMBB
+ * aop = Rs1.H[0]; bop = Rs2.H[1]; // KHMBT
+ * aop = Rs1.H[1]; bop = Rs2.H[1]; // KHMTT
+ * If (0x8000 != aop | 0x8000 != bop) {
+ *   Mresult[31:0] = aop * bop;
+ *   res[15:0] = Mresult[30:15];
+ * } else {
+ *   res[15:0] = 0x7FFF;
+ *   OV = 1;
+ * }
+ * Rd = SE32(res[15:0]); // Rv32
+ * Rd = SE64(res[15:0]); // RV64
+ * ~~~
+ *
+ * \param [in]  a    unsigned int type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KHMBB(unsigned int a, unsigned int b)
+{
+    register long result;
+    __ASM volatile("khmbb %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.37.1. KHMBB ===== */
+
+/* ===== Inline Function Start for 3.37.2. KHMBT ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU
+ * \brief KHMBT (Signed Saturating Half Multiply B16 x T16)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KHMxy Rd, Rs1, Rs2 (xy = BB, BT, TT)
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed Q15 number contents of two 16-bit data in the corresponding portion
+ * of the lower 32-bit chunk in registers and then right-shift 15 bits to turn the Q30 result into a Q15
+ * number again and saturate the Q15 result into the destination register. If saturation happens, an
+ * overflow flag OV will be set.
+ *
+ * **Description**:\n
+ * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with
+ * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then right-
+ * shifted 15-bits and saturated into a Q15 value. The Q15 value is then sing-extended and written into
+ * Rd. When both the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated
+ * to 0x7FFF and the overflow flag OV will be set.
+ *
+ * **Operations**:\n
+ * ~~~
+ * aop = Rs1.H[0]; bop = Rs2.H[0]; // KHMBB
+ * aop = Rs1.H[0]; bop = Rs2.H[1]; // KHMBT
+ * aop = Rs1.H[1]; bop = Rs2.H[1]; // KHMTT
+ * If (0x8000 != aop | 0x8000 != bop) {
+ *   Mresult[31:0] = aop * bop;
+ *   res[15:0] = Mresult[30:15];
+ * } else {
+ *   res[15:0] = 0x7FFF;
+ *   OV = 1;
+ * }
+ * Rd = SE32(res[15:0]); // Rv32
+ * Rd = SE64(res[15:0]); // RV64
+ * ~~~
+ *
+ * \param [in]  a    unsigned int type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KHMBT(unsigned int a, unsigned int b)
+{
+    register long result;
+    __ASM volatile("khmbt %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.37.2. KHMBT ===== */
+
+/* ===== Inline Function Start for 3.37.3. KHMTT ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU
+ * \brief KHMTT (Signed Saturating Half Multiply T16 x T16)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KHMxy Rd, Rs1, Rs2 (xy = BB, BT, TT)
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed Q15 number contents of two 16-bit data in the corresponding portion
+ * of the lower 32-bit chunk in registers and then right-shift 15 bits to turn the Q30 result into a Q15
+ * number again and saturate the Q15 result into the destination register. If saturation happens, an
+ * overflow flag OV will be set.
+ *
+ * **Description**:\n
+ * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with
+ * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then right-
+ * shifted 15-bits and saturated into a Q15 value. The Q15 value is then sing-extended and written into
+ * Rd. When both the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated
+ * to 0x7FFF and the overflow flag OV will be set.
+ *
+ * **Operations**:\n
+ * ~~~
+ * aop = Rs1.H[0]; bop = Rs2.H[0]; // KHMBB
+ * aop = Rs1.H[0]; bop = Rs2.H[1]; // KHMBT
+ * aop = Rs1.H[1]; bop = Rs2.H[1]; // KHMTT
+ * If (0x8000 != aop | 0x8000 != bop) {
+ *   Mresult[31:0] = aop * bop;
+ *   res[15:0] = Mresult[30:15];
+ * } else {
+ *   res[15:0] = 0x7FFF;
+ *   OV = 1;
+ * }
+ * Rd = SE32(res[15:0]); // Rv32
+ * Rd = SE64(res[15:0]); // RV64
+ * ~~~
+ *
+ * \param [in]  a    unsigned int type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KHMTT(unsigned int a, unsigned int b)
+{
+    register long result;
+    __ASM volatile("khmtt %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.37.3. KHMTT ===== */
+
+/* ===== Inline Function Start for 3.38.1. KMABB ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
+ * \brief KMABB (SIMD Saturating Signed Multiply Bottom Halfs & Add)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMABB Rd, Rs1, Rs2
+ * KMABT Rd, Rs1, Rs2
+ * KMATT Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 16-bit content of 32-bit elements in a register with the 16-bit content
+ * of 32-bit elements in another register and add the result to the content of 32-bit elements in the
+ * third register. The addition result may be saturated and is written to the third register.
+ * * KMABB: rd.W[x] + bottom*bottom (per 32-bit element)
+ * * KMABT rd.W[x] + bottom*top (per 32-bit element)
+ * * KMATT rd.W[x] + top*top (per 32-bit element)
+ *
+ * **Description**:\n
+ * For the `KMABB` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
+ * the bottom 16-bit content of 32-bit elements in Rs2.
+ * For the `KMABT` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
+ * the top 16-bit content of 32-bit elements in Rs2.
+ * For the `KMATT` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the
+ * top 16-bit content of 32-bit elements in Rs2.
+ * The multiplication result is added to the content of 32-bit elements in Rd. If the addition result is
+ * beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to
+ * 1. The results after saturation are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as
+ * signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[0]); // KMABB
+ * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[1]); // KMABT
+ * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]); // KMATT
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMABB(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmabb %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.38.1. KMABB ===== */
+
+/* ===== Inline Function Start for 3.38.2. KMABT ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
+ * \brief KMABT (SIMD Saturating Signed Multiply Bottom & Top Halfs & Add)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMABB Rd, Rs1, Rs2
+ * KMABT Rd, Rs1, Rs2
+ * KMATT Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 16-bit content of 32-bit elements in a register with the 16-bit content
+ * of 32-bit elements in another register and add the result to the content of 32-bit elements in the
+ * third register. The addition result may be saturated and is written to the third register.
+ * * KMABB: rd.W[x] + bottom*bottom (per 32-bit element)
+ * * KMABT rd.W[x] + bottom*top (per 32-bit element)
+ * * KMATT rd.W[x] + top*top (per 32-bit element)
+ *
+ * **Description**:\n
+ * For the `KMABB` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
+ * the bottom 16-bit content of 32-bit elements in Rs2.
+ * For the `KMABT` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
+ * the top 16-bit content of 32-bit elements in Rs2.
+ * For the `KMATT` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the
+ * top 16-bit content of 32-bit elements in Rs2.
+ * The multiplication result is added to the content of 32-bit elements in Rd. If the addition result is
+ * beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to
+ * 1. The results after saturation are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as
+ * signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[0]); // KMABB
+ * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[1]); // KMABT
+ * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]); // KMATT
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMABT(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmabt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.38.2. KMABT ===== */
+
+/* ===== Inline Function Start for 3.38.3. KMATT ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
+ * \brief KMATT (SIMD Saturating Signed Multiply Top Halfs & Add)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMABB Rd, Rs1, Rs2
+ * KMABT Rd, Rs1, Rs2
+ * KMATT Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 16-bit content of 32-bit elements in a register with the 16-bit content
+ * of 32-bit elements in another register and add the result to the content of 32-bit elements in the
+ * third register. The addition result may be saturated and is written to the third register.
+ * * KMABB: rd.W[x] + bottom*bottom (per 32-bit element)
+ * * KMABT rd.W[x] + bottom*top (per 32-bit element)
+ * * KMATT rd.W[x] + top*top (per 32-bit element)
+ *
+ * **Description**:\n
+ * For the `KMABB` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
+ * the bottom 16-bit content of 32-bit elements in Rs2.
+ * For the `KMABT` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
+ * the top 16-bit content of 32-bit elements in Rs2.
+ * For the `KMATT` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the
+ * top 16-bit content of 32-bit elements in Rs2.
+ * The multiplication result is added to the content of 32-bit elements in Rd. If the addition result is
+ * beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to
+ * 1. The results after saturation are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as
+ * signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[0]); // KMABB
+ * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[1]); // KMABT
+ * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]); // KMATT
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMATT(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmatt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.38.3. KMATT ===== */
+
+/* ===== Inline Function Start for 3.39.1. KMADA ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
+ * \brief KMADA (SIMD Saturating Signed Multiply Two Halfs and Two Adds)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMADA Rd, Rs1, Rs2
+ * KMAXDA Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 16-bit multiplications from 32-bit elements in two registers; and then adds
+ * the two 32-bit results and 32-bit elements in a third register together. The addition result may be
+ * saturated.
+ * * KMADA: rd.W[x] + top*top + bottom*bottom (per 32-bit element)
+ * * KMAXDA: rd.W[x] + top*bottom + bottom*top (per 32-bit element)
+ *
+ * **Description**:\n
+ * For the `KMADA instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
+ * the bottom 16-bit content of 32-bit elements in Rs2 and then adds the result to the result of
+ * multiplying the top 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit
+ * elements in Rs2.
+ * For the `KMAXDA` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the
+ * bottom 16-bit content of 32-bit elements in Rs2 and then adds the result to the result of multiplying
+ * the bottom 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit elements in
+ * Rs2.
+ * The result is added to the content of 32-bit elements in Rd. If the addition result is beyond the Q31
+ * number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The 32-bit
+ * results after saturation are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as signed
+ * integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * // KMADA
+ * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]) + (Rs1.W[x].H[0] * Rs2.W[x].H[0]);
+ * // KMAXDA
+ * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[0]) + (Rs1.W[x].H[0] * Rs2.W[x].H[1]);
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^31) {
+ *   res[x] = -2^31;
+ * OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMADA(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmada %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.39.1. KMADA ===== */
+
+/* ===== Inline Function Start for 3.39.2. KMAXDA ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
+ * \brief KMAXDA (SIMD Saturating Signed Crossed Multiply Two Halfs and Two Adds)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMADA Rd, Rs1, Rs2
+ * KMAXDA Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 16-bit multiplications from 32-bit elements in two registers; and then adds
+ * the two 32-bit results and 32-bit elements in a third register together. The addition result may be
+ * saturated.
+ * * KMADA: rd.W[x] + top*top + bottom*bottom (per 32-bit element)
+ * * KMAXDA: rd.W[x] + top*bottom + bottom*top (per 32-bit element)
+ *
+ * **Description**:\n
+ * For the `KMADA instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
+ * the bottom 16-bit content of 32-bit elements in Rs2 and then adds the result to the result of
+ * multiplying the top 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit
+ * elements in Rs2.
+ * For the `KMAXDA` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the
+ * bottom 16-bit content of 32-bit elements in Rs2 and then adds the result to the result of multiplying
+ * the bottom 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit elements in
+ * Rs2.
+ * The result is added to the content of 32-bit elements in Rd. If the addition result is beyond the Q31
+ * number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The 32-bit
+ * results after saturation are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as signed
+ * integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * // KMADA
+ * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]) + (Rs1.W[x].H[0] * Rs2.W[x].H[0]);
+ * // KMAXDA
+ * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[0]) + (Rs1.W[x].H[0] * Rs2.W[x].H[1]);
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^31) {
+ *   res[x] = -2^31;
+ * OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMAXDA(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmaxda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.39.2. KMAXDA ===== */
+
+/* ===== Inline Function Start for 3.40.1. KMADS ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
+ * \brief KMADS (SIMD Saturating Signed Multiply Two Halfs & Subtract & Add)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMADS Rd, Rs1, Rs2
+ * KMADRS Rd, Rs1, Rs2
+ * KMAXDS Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 16-bit multiplications from 32-bit elements in two registers; and then
+ * perform a subtraction operation between the two 32-bit results. Then add the subtraction result to
+ * the corresponding 32-bit elements in a third register. The addition result may be saturated.
+ * * KMADS: rd.W[x] + (top*top - bottom*bottom) (per 32-bit element)
+ * * KMADRS: rd.W[x] + (bottom*bottom - top*top) (per 32-bit element)
+ * * KMAXDS: rd.W[x] + (top*bottom - bottom*top) (per 32-bit element)
+ *
+ * **Description**:\n
+ * For the `KMADS` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
+ * the bottom 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of
+ * multiplying the top 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit
+ * elements in Rs2.
+ * For the `KMADRS` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the
+ * top 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of
+ * multiplying the bottom 16-bit content of 32-bit elements in Rs1 with the bottom 16-bit content of 32-
+ * bit elements in Rs2.
+ * For the `KMAXDS` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
+ * the top 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of
+ * multiplying the top 16-bit content of 32-bit elements in Rs1 with the bottom 16-bit content of 32-bit
+ * elements in Rs2.
+ * The subtraction result is then added to the content of the corresponding 32-bit elements in Rd. If the
+ * addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and
+ * the OV bit is set to 1. The 32-bit results after saturation are written to Rd. The 16-bit contents of Rs1
+ * and Rs2 are treated as signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * // KMADS
+ * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]);
+ * // KMADRS
+ * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[0]) - (Rs1.W[x].H[1] * Rs2.W[x].H[1]);
+ * // KMAXDS
+ * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]);
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMADS(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmads %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.40.1. KMADS ===== */
+
+/* ===== Inline Function Start for 3.40.2. KMADRS ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
+ * \brief KMADRS (SIMD Saturating Signed Multiply Two Halfs & Reverse Subtract & Add)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMADS Rd, Rs1, Rs2
+ * KMADRS Rd, Rs1, Rs2
+ * KMAXDS Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 16-bit multiplications from 32-bit elements in two registers; and then
+ * perform a subtraction operation between the two 32-bit results. Then add the subtraction result to
+ * the corresponding 32-bit elements in a third register. The addition result may be saturated.
+ * * KMADS: rd.W[x] + (top*top - bottom*bottom) (per 32-bit element)
+ * * KMADRS: rd.W[x] + (bottom*bottom - top*top) (per 32-bit element)
+ * * KMAXDS: rd.W[x] + (top*bottom - bottom*top) (per 32-bit element)
+ *
+ * **Description**:\n
+ * For the `KMADS` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
+ * the bottom 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of
+ * multiplying the top 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit
+ * elements in Rs2.
+ * For the `KMADRS` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the
+ * top 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of
+ * multiplying the bottom 16-bit content of 32-bit elements in Rs1 with the bottom 16-bit content of 32-
+ * bit elements in Rs2.
+ * For the `KMAXDS` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
+ * the top 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of
+ * multiplying the top 16-bit content of 32-bit elements in Rs1 with the bottom 16-bit content of 32-bit
+ * elements in Rs2.
+ * The subtraction result is then added to the content of the corresponding 32-bit elements in Rd. If the
+ * addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and
+ * the OV bit is set to 1. The 32-bit results after saturation are written to Rd. The 16-bit contents of Rs1
+ * and Rs2 are treated as signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * // KMADS
+ * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]);
+ * // KMADRS
+ * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[0]) - (Rs1.W[x].H[1] * Rs2.W[x].H[1]);
+ * // KMAXDS
+ * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]);
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMADRS(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmadrs %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.40.2. KMADRS ===== */
+
+/* ===== Inline Function Start for 3.40.3. KMAXDS ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
+ * \brief KMAXDS (SIMD Saturating Signed Crossed Multiply Two Halfs & Subtract & Add)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMADS Rd, Rs1, Rs2
+ * KMADRS Rd, Rs1, Rs2
+ * KMAXDS Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 16-bit multiplications from 32-bit elements in two registers; and then
+ * perform a subtraction operation between the two 32-bit results. Then add the subtraction result to
+ * the corresponding 32-bit elements in a third register. The addition result may be saturated.
+ * * KMADS: rd.W[x] + (top*top - bottom*bottom) (per 32-bit element)
+ * * KMADRS: rd.W[x] + (bottom*bottom - top*top) (per 32-bit element)
+ * * KMAXDS: rd.W[x] + (top*bottom - bottom*top) (per 32-bit element)
+ *
+ * **Description**:\n
+ * For the `KMADS` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
+ * the bottom 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of
+ * multiplying the top 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit
+ * elements in Rs2.
+ * For the `KMADRS` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the
+ * top 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of
+ * multiplying the bottom 16-bit content of 32-bit elements in Rs1 with the bottom 16-bit content of 32-
+ * bit elements in Rs2.
+ * For the `KMAXDS` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
+ * the top 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of
+ * multiplying the top 16-bit content of 32-bit elements in Rs1 with the bottom 16-bit content of 32-bit
+ * elements in Rs2.
+ * The subtraction result is then added to the content of the corresponding 32-bit elements in Rd. If the
+ * addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and
+ * the OV bit is set to 1. The 32-bit results after saturation are written to Rd. The 16-bit contents of Rs1
+ * and Rs2 are treated as signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * // KMADS
+ * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]);
+ * // KMADRS
+ * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[0]) - (Rs1.W[x].H[1] * Rs2.W[x].H[1]);
+ * // KMAXDS
+ * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]);
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMAXDS(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmaxds %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.40.3. KMAXDS ===== */
+
+/* ===== Inline Function Start for 3.41. KMAR64 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB
+ * \brief KMAR64 (Signed Multiply and Saturating Add to 64-Bit Data)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMAR64 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the 32-bit signed elements in two registers and add the 64-bit multiplication
+ * results to the 64-bit signed data of a pair of registers (RV32) or a register (RV64). The result is
+ * saturated to the Q63 range and written back to the pair of registers (RV32) or the register (RV64).
+ *
+ * **RV32 Description**:\n
+ * This instruction multiplies the 32-bit signed data of Rs1 with that of Rs2. It adds
+ * the 64-bit multiplication result to the 64-bit signed data of an even/odd pair of registers specified by
+ * Rd(4,1) with unlimited precision. If the 64-bit addition result is beyond the Q63 number range (-2^63 <=
+ * Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The saturated result is written back
+ * to the even/odd pair of registers specified by Rd(4,1).
+ * Rx(4,1), i.e., value d, determines the even/odd pair group of two registers. Specifically, the register
+ * pair includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
+ * of the pair contains the low 32-bit of the result.
+ *
+ * **RV64 Description**:\n
+ * This instruction multiplies the 32-bit signed elements of Rs1 with that of Rs2. It
+ * adds the 64-bit multiplication results to the 64-bit signed data of Rd with unlimited precision. If the
+ * 64-bit addition result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range
+ * and the OV bit is set to 1. The saturated result is written back to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * RV32:
+ * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
+ * result = R[t_H].R[t_L] + (Rs1 * Rs2);
+ * if (result > (2^63)-1) {
+ *   result = (2^63)-1; OV = 1;
+ * } else if (result < -2^63) {
+ *   result = -2^63; OV = 1;
+ * }
+ * R[t_H].R[t_L] = result;
+ * RV64:
+ * // `result` has unlimited precision
+ * result = Rd + (Rs1.W[0] * Rs2.W[0]) + (Rs1.W[1] * Rs2.W[1]);
+ * if (result > (2^63)-1) {
+ *   result = (2^63)-1; OV = 1;
+ * } else if (result < -2^63) {
+ *   result = -2^63; OV = 1;
+ * }
+ * Rd = result;
+ * ~~~
+ *
+ * \param [in]  t    long long type of value stored in t
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    long type of value stored in b
+ * \return value stored in long long type
+ */
+__STATIC_FORCEINLINE long long __RV_KMAR64(long long t, long a, long b)
+{
+    __ASM volatile("kmar64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.41. KMAR64 ===== */
+
+/* ===== Inline Function Start for 3.42.1. KMDA ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
+ * \brief KMDA (SIMD Signed Multiply Two Halfs and Add)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMDA Rd, Rs1, Rs2
+ * KMXDA Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
+ * adds the two 32-bit results together. The addition result may be saturated.
+ * * KMDA: top*top + bottom*bottom (per 32-bit element)
+ * * KMXDA: top*bottom + bottom*top (per 32-bit element)
+ *
+ * **Description**:\n
+ * For the `KMDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of
+ * multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-
+ * bit elements of Rs2.
+ * For the `KMXDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the top 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of
+ * multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the
+ * 32-bit elements of Rs2.
+ * The addition result is checked for saturation. If saturation happens, the result is saturated to 2^31-1.
+ * The final results are written to Rd. The 16-bit contents are treated as signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if  Rs1.W[x]  !=  0x80008000)  or  (Rs2.W[x]  !=  0x80008000  {  //  KMDA  Rd.W[x]  =  Rs1.W[x].H[1]  *
+ * Rs2.W[x].H[1]) + (Rs1.W[x].H[0] * Rs2.W[x].H[0]; // KMXDA Rd.W[x] = Rs1.W[x].H[1] * Rs2.W[x].H[0])
+ * +  (Rs1.W[x].H[0]  *  Rs2.W[x].H[1];  }  else  {  Rd.W[x]  =  0x7fffffff;  OV  =  1;  }  for  RV32:  x=0  for  RV64:
+ * x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMDA(unsigned long a, unsigned long b)
+{
+    register long result;
+    __ASM volatile("kmda %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.42.1. KMDA ===== */
+
+/* ===== Inline Function Start for 3.42.2. KMXDA ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
+ * \brief KMXDA (SIMD Signed Crossed Multiply Two Halfs and Add)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMDA Rd, Rs1, Rs2
+ * KMXDA Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
+ * adds the two 32-bit results together. The addition result may be saturated.
+ * * KMDA: top*top + bottom*bottom (per 32-bit element)
+ * * KMXDA: top*bottom + bottom*top (per 32-bit element)
+ *
+ * **Description**:\n
+ * For the `KMDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of
+ * multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-
+ * bit elements of Rs2.
+ * For the `KMXDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the top 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of
+ * multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the
+ * 32-bit elements of Rs2.
+ * The addition result is checked for saturation. If saturation happens, the result is saturated to 2^31-1.
+ * The final results are written to Rd. The 16-bit contents are treated as signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if  Rs1.W[x]  !=  0x80008000)  or  (Rs2.W[x]  !=  0x80008000  {  //  KMDA  Rd.W[x]  =  Rs1.W[x].H[1]  *
+ * Rs2.W[x].H[1]) + (Rs1.W[x].H[0] * Rs2.W[x].H[0]; // KMXDA Rd.W[x] = Rs1.W[x].H[1] * Rs2.W[x].H[0])
+ * +  (Rs1.W[x].H[0]  *  Rs2.W[x].H[1];  }  else  {  Rd.W[x]  =  0x7fffffff;  OV  =  1;  }  for  RV32:  x=0  for  RV64:
+ * x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMXDA(unsigned long a, unsigned long b)
+{
+    register long result;
+    __ASM volatile("kmxda %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.42.2. KMXDA ===== */
+
+/* ===== Inline Function Start for 3.43.1. KMMAC ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC
+ * \brief KMMAC (SIMD Saturating MSW Signed Multiply Word and Add)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMMAC Rd, Rs1, Rs2
+ * KMMAC.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit integer elements of two registers and add the most significant
+ * 32-bit results with the signed 32-bit integer elements of a third register. The addition results are
+ * saturated first and then written back to the third register. The `.u` form performs an additional
+ * rounding up operation on the multiplication results before adding the most significant 32-bit part
+ * of the results.
+ *
+ * **Description**:\n
+ * This instruction multiplies the signed 32-bit elements of Rs1 with the signed 32-bit elements of Rs2
+ * and adds the most significant 32-bit multiplication results with the signed 32-bit elements of Rd. If
+ * the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range
+ * and the OV bit is set to 1. The results after saturation are written to Rd. The `.u` form of the
+ * instruction additionally rounds up the most significant 32-bit of the 64-bit multiplication results by
+ * adding a 1 to bit 31 of the results.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x];
+ * if (`.u` form) {
+ *   Round[x][32:0] = Mres[x][63:31] + 1;
+ *   res[x] = Rd.W[x] + Round[x][32:1];
+ * } else {
+ *   res[x] = Rd.W[x] + Mres[x][63:32];
+ * }
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMMAC(long t, long a, long b)
+{
+    __ASM volatile("kmmac %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.43.1. KMMAC ===== */
+
+/* ===== Inline Function Start for 3.43.2. KMMAC.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC
+ * \brief KMMAC.u (SIMD Saturating MSW Signed Multiply Word and Add with Rounding)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMMAC Rd, Rs1, Rs2
+ * KMMAC.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit integer elements of two registers and add the most significant
+ * 32-bit results with the signed 32-bit integer elements of a third register. The addition results are
+ * saturated first and then written back to the third register. The `.u` form performs an additional
+ * rounding up operation on the multiplication results before adding the most significant 32-bit part
+ * of the results.
+ *
+ * **Description**:\n
+ * This instruction multiplies the signed 32-bit elements of Rs1 with the signed 32-bit elements of Rs2
+ * and adds the most significant 32-bit multiplication results with the signed 32-bit elements of Rd. If
+ * the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range
+ * and the OV bit is set to 1. The results after saturation are written to Rd. The `.u` form of the
+ * instruction additionally rounds up the most significant 32-bit of the 64-bit multiplication results by
+ * adding a 1 to bit 31 of the results.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x];
+ * if (`.u` form) {
+ *   Round[x][32:0] = Mres[x][63:31] + 1;
+ *   res[x] = Rd.W[x] + Round[x][32:1];
+ * } else {
+ *   res[x] = Rd.W[x] + Mres[x][63:32];
+ * }
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMMAC_U(long t, long a, long b)
+{
+    __ASM volatile("kmmac.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.43.2. KMMAC.u ===== */
+
+/* ===== Inline Function Start for 3.44.1. KMMAWB ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
+ * \brief KMMAWB (SIMD Saturating MSW Signed Multiply Word and Bottom Half and Add)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMMAWB Rd, Rs1, Rs2
+ * KMMAWB.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit integer elements of one register and the bottom 16-bit of the
+ * corresponding 32-bit elements of another register and add the most significant 32-bit results with
+ * the corresponding signed 32-bit elements of a third register. The addition result is written to the
+ * corresponding 32-bit elements of the third register. The `.u` form rounds up the multiplication
+ * results from the most significant discarded bit before the addition operations.
+ *
+ * **Description**:\n
+ * This instruction multiplies the signed 32-bit elements of Rs1 with the signed bottom 16-bit content
+ * of the corresponding 32-bit elements of Rs2 and adds the most significant 32-bit multiplication
+ * results with the corresponding signed 32-bit elements of Rd. If the addition result is beyond the Q31
+ * number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The results
+ * after saturation are written to the corresponding 32-bit elements of Rd. The `.u` form of the
+ * instruction rounds up the most significant 32-bit of the 48-bit multiplication results by adding a 1 to
+ * bit 15 of the result before the addition operations.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[0];
+ * if (`.u` form) {
+ *   Round[x][32:0] = Mres[x][47:15] + 1;
+ *   res[x] = Rd.W[x] + Round[x][32:1];
+ * } else {
+ *   res[x] = Rd.W[x] + Mres[x][47:16];
+ * }
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMMAWB(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmmawb %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.44.1. KMMAWB ===== */
+
+/* ===== Inline Function Start for 3.44.2. KMMAWB.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
+ * \brief KMMAWB.u (SIMD Saturating MSW Signed Multiply Word and Bottom Half and Add with Rounding)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMMAWB Rd, Rs1, Rs2
+ * KMMAWB.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit integer elements of one register and the bottom 16-bit of the
+ * corresponding 32-bit elements of another register and add the most significant 32-bit results with
+ * the corresponding signed 32-bit elements of a third register. The addition result is written to the
+ * corresponding 32-bit elements of the third register. The `.u` form rounds up the multiplication
+ * results from the most significant discarded bit before the addition operations.
+ *
+ * **Description**:\n
+ * This instruction multiplies the signed 32-bit elements of Rs1 with the signed bottom 16-bit content
+ * of the corresponding 32-bit elements of Rs2 and adds the most significant 32-bit multiplication
+ * results with the corresponding signed 32-bit elements of Rd. If the addition result is beyond the Q31
+ * number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The results
+ * after saturation are written to the corresponding 32-bit elements of Rd. The `.u` form of the
+ * instruction rounds up the most significant 32-bit of the 48-bit multiplication results by adding a 1 to
+ * bit 15 of the result before the addition operations.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[0];
+ * if (`.u` form) {
+ *   Round[x][32:0] = Mres[x][47:15] + 1;
+ *   res[x] = Rd.W[x] + Round[x][32:1];
+ * } else {
+ *   res[x] = Rd.W[x] + Mres[x][47:16];
+ * }
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMMAWB_U(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmmawb.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.44.2. KMMAWB.u ===== */
+
+/* ===== Inline Function Start for 3.45.1. KMMAWB2 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
+ * \brief KMMAWB2 (SIMD Saturating MSW Signed Multiply Word and Bottom Half & 2 and Add)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMMAWB2 Rd, Rs1, Rs2
+ * KMMAWB2.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit elements of one register and the bottom 16-bit of the
+ * corresponding 32-bit elements of another register, double the multiplication results and add the
+ * saturated most significant 32-bit results with the corresponding signed 32-bit elements of a third
+ * register. The saturated addition result is written to the corresponding 32-bit elements of the third
+ * register. The `.u` form rounds up the multiplication results from the most significant discarded bit
+ * before the addition operations.
+ *
+ * **Description**:\n
+ * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed bottom 16-bit Q15
+ * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and
+ * adds the saturated most significant 32-bit Q31 multiplication results with the corresponding signed
+ * 32-bit elements of Rd. If the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is
+ * saturated to the range and the OV bit is set to 1. The results after saturation are written to the
+ * corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the most significant
+ * 32-bit of the 48-bit Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of
+ * the result before the addition operations.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[0] == 0x8000)) {
+ *   addop.W[x] = 0x7fffffff;
+ *   OV = 1;
+ * } else {
+ *   Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[0];
+ *   if (`.u` form) {
+ *     Mres[x][47:14] = Mres[x][47:14] + 1;
+ *   }
+ *   addop.W[x] = Mres[x][46:15]; // doubling
+ * }
+ * res[x] = Rd.W[x] + addop.W[x];
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMMAWB2(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmmawb2 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.45.1. KMMAWB2 ===== */
+
+/* ===== Inline Function Start for 3.45.2. KMMAWB2.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
+ * \brief KMMAWB2.u (SIMD Saturating MSW Signed Multiply Word and Bottom Half & 2 and Add with Rounding)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMMAWB2 Rd, Rs1, Rs2
+ * KMMAWB2.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit elements of one register and the bottom 16-bit of the
+ * corresponding 32-bit elements of another register, double the multiplication results and add the
+ * saturated most significant 32-bit results with the corresponding signed 32-bit elements of a third
+ * register. The saturated addition result is written to the corresponding 32-bit elements of the third
+ * register. The `.u` form rounds up the multiplication results from the most significant discarded bit
+ * before the addition operations.
+ *
+ * **Description**:\n
+ * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed bottom 16-bit Q15
+ * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and
+ * adds the saturated most significant 32-bit Q31 multiplication results with the corresponding signed
+ * 32-bit elements of Rd. If the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is
+ * saturated to the range and the OV bit is set to 1. The results after saturation are written to the
+ * corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the most significant
+ * 32-bit of the 48-bit Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of
+ * the result before the addition operations.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[0] == 0x8000)) {
+ *   addop.W[x] = 0x7fffffff;
+ *   OV = 1;
+ * } else {
+ *   Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[0];
+ *   if (`.u` form) {
+ *     Mres[x][47:14] = Mres[x][47:14] + 1;
+ *   }
+ *   addop.W[x] = Mres[x][46:15]; // doubling
+ * }
+ * res[x] = Rd.W[x] + addop.W[x];
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMMAWB2_U(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmmawb2.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.45.2. KMMAWB2.u ===== */
+
+/* ===== Inline Function Start for 3.46.1. KMMAWT ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
+ * \brief KMMAWT (SIMD Saturating MSW Signed Multiply Word and Top Half and Add)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMMAWT Rd, Rs1, Rs2
+ * KMMAWT.u Rd Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit integer elements of one register and the signed top 16-bit of the
+ * corresponding 32-bit elements of another register and add the most significant 32-bit results with
+ * the corresponding signed 32-bit elements of a third register. The addition results are written to the
+ * corresponding 32-bit elements of the third register. The `.u` form rounds up the multiplication
+ * results from the most significant discarded bit before the addition operations.
+ *
+ * **Description**:\n
+ * This instruction multiplies the signed 32-bit elements of Rs1 with the signed top 16-bit of the
+ * corresponding 32-bit elements of Rs2 and adds the most significant 32-bit multiplication results
+ * with the corresponding signed 32-bit elements of Rd. If the addition result is beyond the Q31
+ * number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The results
+ * after saturation are written to the corresponding 32-bit elements of Rd. The `.u` form of the
+ * instruction rounds up the most significant 32-bit of the 48-bit multiplication results by adding a 1 to
+ * bit 15 of the result before the addition operations.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[1];
+ * if (`.u` form) {
+ *   Round[x][32:0] = Mres[x][47:15] + 1;
+ *   res[x] = Rd.W[x] + Round[x][32:1];
+ * } else {
+ *   res[x] = Rd.W[x] + Mres[x][47:16];
+ * }
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMMAWT(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmmawt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.46.1. KMMAWT ===== */
+
+/* ===== Inline Function Start for 3.46.2. KMMAWT.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
+ * \brief KMMAWT.u (SIMD Saturating MSW Signed Multiply Word and Top Half and Add with Rounding)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMMAWT Rd, Rs1, Rs2
+ * KMMAWT.u Rd Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit integer elements of one register and the signed top 16-bit of the
+ * corresponding 32-bit elements of another register and add the most significant 32-bit results with
+ * the corresponding signed 32-bit elements of a third register. The addition results are written to the
+ * corresponding 32-bit elements of the third register. The `.u` form rounds up the multiplication
+ * results from the most significant discarded bit before the addition operations.
+ *
+ * **Description**:\n
+ * This instruction multiplies the signed 32-bit elements of Rs1 with the signed top 16-bit of the
+ * corresponding 32-bit elements of Rs2 and adds the most significant 32-bit multiplication results
+ * with the corresponding signed 32-bit elements of Rd. If the addition result is beyond the Q31
+ * number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The results
+ * after saturation are written to the corresponding 32-bit elements of Rd. The `.u` form of the
+ * instruction rounds up the most significant 32-bit of the 48-bit multiplication results by adding a 1 to
+ * bit 15 of the result before the addition operations.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[1];
+ * if (`.u` form) {
+ *   Round[x][32:0] = Mres[x][47:15] + 1;
+ *   res[x] = Rd.W[x] + Round[x][32:1];
+ * } else {
+ *   res[x] = Rd.W[x] + Mres[x][47:16];
+ * }
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMMAWT_U(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmmawt.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.46.2. KMMAWT.u ===== */
+
+/* ===== Inline Function Start for 3.47.1. KMMAWT2 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
+ * \brief KMMAWT2 (SIMD Saturating MSW Signed Multiply Word and Top Half & 2 and Add)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMMAWT2 Rd, Rs1, Rs2
+ * KMMAWT2.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit elements of one register and the top 16-bit of the
+ * corresponding 32-bit elements of another register, double the multiplication results and add the
+ * saturated most significant 32-bit results with the corresponding signed 32-bit elements of a third
+ * register. The saturated addition result is written to the corresponding 32-bit elements of the third
+ * register. The `.u` form rounds up the multiplication results from the most significant discarded bit
+ * before the addition operations.
+ *
+ * **Description**:\n
+ * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed top 16-bit Q15
+ * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and
+ * adds the saturated most significant 32-bit Q31 multiplication results with the corresponding signed
+ * 32-bit elements of Rd. If the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is
+ * saturated to the range and the OV bit is set to 1. The results after saturation are written to the
+ * corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the most significant
+ * 32-bit of the 48-bit Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of
+ * the result before the addition operations.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[1] == 0x8000)) {
+ *   addop.W[x] = 0x7fffffff;
+ *   OV = 1;
+ * } else {
+ *   Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[1];
+ *   if (`.u` form) {
+ *     Mres[x][47:14] = Mres[x][47:14] + 1;
+ *   }
+ *   addop.W[x] = Mres[x][46:15]; // doubling
+ * }
+ * res[x] = Rd.W[x] + addop.W[x];
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMMAWT2(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmmawt2 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.47.1. KMMAWT2 ===== */
+
+/* ===== Inline Function Start for 3.47.2. KMMAWT2.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
+ * \brief KMMAWT2.u (SIMD Saturating MSW Signed Multiply Word and Top Half & 2 and Add with Rounding)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMMAWT2 Rd, Rs1, Rs2
+ * KMMAWT2.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit elements of one register and the top 16-bit of the
+ * corresponding 32-bit elements of another register, double the multiplication results and add the
+ * saturated most significant 32-bit results with the corresponding signed 32-bit elements of a third
+ * register. The saturated addition result is written to the corresponding 32-bit elements of the third
+ * register. The `.u` form rounds up the multiplication results from the most significant discarded bit
+ * before the addition operations.
+ *
+ * **Description**:\n
+ * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed top 16-bit Q15
+ * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and
+ * adds the saturated most significant 32-bit Q31 multiplication results with the corresponding signed
+ * 32-bit elements of Rd. If the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is
+ * saturated to the range and the OV bit is set to 1. The results after saturation are written to the
+ * corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the most significant
+ * 32-bit of the 48-bit Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of
+ * the result before the addition operations.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[1] == 0x8000)) {
+ *   addop.W[x] = 0x7fffffff;
+ *   OV = 1;
+ * } else {
+ *   Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[1];
+ *   if (`.u` form) {
+ *     Mres[x][47:14] = Mres[x][47:14] + 1;
+ *   }
+ *   addop.W[x] = Mres[x][46:15]; // doubling
+ * }
+ * res[x] = Rd.W[x] + addop.W[x];
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMMAWT2_U(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmmawt2.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.47.2. KMMAWT2.u ===== */
+
+/* ===== Inline Function Start for 3.48.1. KMMSB ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC
+ * \brief KMMSB (SIMD Saturating MSW Signed Multiply Word and Subtract)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMMSB Rd, Rs1, Rs2
+ * KMMSB.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit integer elements of two registers and subtract the most
+ * significant 32-bit results from the signed 32-bit elements of a third register. The subtraction results
+ * are written to the third register. The `.u` form performs an additional rounding up operation on
+ * the multiplication results before subtracting the most significant 32-bit part of the results.
+ *
+ * **Description**:\n
+ * This instruction multiplies the signed 32-bit elements of Rs1 with the signed 32-bit elements of Rs2
+ * and subtracts the most significant 32-bit multiplication results from the signed 32-bit elements of
+ * Rd. If the subtraction result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the
+ * range and the OV bit is set to 1. The results after saturation are written to Rd. The `.u` form of the
+ * instruction additionally rounds up the most significant 32-bit of the 64-bit multiplication results by
+ * adding a 1 to bit 31 of the results.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x];
+ * if (`.u` form) {
+ *   Round[x][32:0] = Mres[x][63:31] + 1;
+ *   res[x] = Rd.W[x] - Round[x][32:1];
+ * } else {
+ *   res[x] = Rd.W[x] - Mres[x][63:32];
+ * }
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMMSB(long t, long a, long b)
+{
+    __ASM volatile("kmmsb %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.48.1. KMMSB ===== */
+
+/* ===== Inline Function Start for 3.48.2. KMMSB.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC
+ * \brief KMMSB.u (SIMD Saturating MSW Signed Multiply Word and Subtraction with Rounding)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMMSB Rd, Rs1, Rs2
+ * KMMSB.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit integer elements of two registers and subtract the most
+ * significant 32-bit results from the signed 32-bit elements of a third register. The subtraction results
+ * are written to the third register. The `.u` form performs an additional rounding up operation on
+ * the multiplication results before subtracting the most significant 32-bit part of the results.
+ *
+ * **Description**:\n
+ * This instruction multiplies the signed 32-bit elements of Rs1 with the signed 32-bit elements of Rs2
+ * and subtracts the most significant 32-bit multiplication results from the signed 32-bit elements of
+ * Rd. If the subtraction result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the
+ * range and the OV bit is set to 1. The results after saturation are written to Rd. The `.u` form of the
+ * instruction additionally rounds up the most significant 32-bit of the 64-bit multiplication results by
+ * adding a 1 to bit 31 of the results.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x];
+ * if (`.u` form) {
+ *   Round[x][32:0] = Mres[x][63:31] + 1;
+ *   res[x] = Rd.W[x] - Round[x][32:1];
+ * } else {
+ *   res[x] = Rd.W[x] - Mres[x][63:32];
+ * }
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMMSB_U(long t, long a, long b)
+{
+    __ASM volatile("kmmsb.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.48.2. KMMSB.u ===== */
+
+/* ===== Inline Function Start for 3.49.1. KMMWB2 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
+ * \brief KMMWB2 (SIMD Saturating MSW Signed Multiply Word and Bottom Half & 2)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMMWB2 Rd, Rs1, Rs2
+ * KMMWB2.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit integer elements of one register and the bottom 16-bit of the
+ * corresponding 32-bit elements of another register, double the multiplication results and write the
+ * saturated most significant 32-bit results to the corresponding 32-bit elements of a register. The `.u`
+ * form rounds up the results from the most significant discarded bit.
+ *
+ * **Description**:\n
+ * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed bottom 16-bit Q15
+ * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and
+ * writes the saturated most significant 32-bit Q31 multiplication results to the corresponding 32-bit
+ * elements of Rd. The `.u` form of the instruction rounds up the most significant 32-bit of the 48-bit
+ * Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of the results.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[0] == 0x8000)) {
+ *   Rd.W[x] = 0x7fffffff;
+ *   OV = 1;
+ * } else {
+ *   Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[0];
+ *   if (`.u` form) {
+ *     Round[x][32:0] = Mres[x][46:14] + 1;
+ *     Rd.W[x] = Round[x][32:1];
+ *   } else {
+ *     Rd.W[x] = Mres[x][46:15];
+ *   }
+ * }
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMMWB2(long a, unsigned long b)
+{
+    register long result;
+    __ASM volatile("kmmwb2 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.49.1. KMMWB2 ===== */
+
+/* ===== Inline Function Start for 3.49.2. KMMWB2.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
+ * \brief KMMWB2.u (SIMD Saturating MSW Signed Multiply Word and Bottom Half & 2 with Rounding)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMMWB2 Rd, Rs1, Rs2
+ * KMMWB2.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit integer elements of one register and the bottom 16-bit of the
+ * corresponding 32-bit elements of another register, double the multiplication results and write the
+ * saturated most significant 32-bit results to the corresponding 32-bit elements of a register. The `.u`
+ * form rounds up the results from the most significant discarded bit.
+ *
+ * **Description**:\n
+ * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed bottom 16-bit Q15
+ * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and
+ * writes the saturated most significant 32-bit Q31 multiplication results to the corresponding 32-bit
+ * elements of Rd. The `.u` form of the instruction rounds up the most significant 32-bit of the 48-bit
+ * Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of the results.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[0] == 0x8000)) {
+ *   Rd.W[x] = 0x7fffffff;
+ *   OV = 1;
+ * } else {
+ *   Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[0];
+ *   if (`.u` form) {
+ *     Round[x][32:0] = Mres[x][46:14] + 1;
+ *     Rd.W[x] = Round[x][32:1];
+ *   } else {
+ *     Rd.W[x] = Mres[x][46:15];
+ *   }
+ * }
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMMWB2_U(long a, unsigned long b)
+{
+    register long result;
+    __ASM volatile("kmmwb2.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.49.2. KMMWB2.u ===== */
+
+/* ===== Inline Function Start for 3.50.1. KMMWT2 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
+ * \brief KMMWT2 (SIMD Saturating MSW Signed Multiply Word and Top Half & 2)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMMWT2 Rd, Rs1, Rs2
+ * KMMWT2.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit integer elements of one register and the top 16-bit of the
+ * corresponding 32-bit elements of another register, double the multiplication results and write the
+ * saturated most significant 32-bit results to the corresponding 32-bit elements of a register. The `.u`
+ * form rounds up the results from the most significant discarded bit.
+ *
+ * **Description**:\n
+ * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed top 16-bit Q15
+ * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and
+ * writes the saturated most significant 32-bit Q31 multiplication results to the corresponding 32-bit
+ * elements of Rd. The `.u` form of the instruction rounds up the most significant 32-bit of the 48-bit
+ * Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of the results.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[1] == 0x8000)) {
+ *   Rd.W[x] = 0x7fffffff;
+ *   OV = 1;
+ * } else {
+ *   Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[1];
+ *   if (`.u` form) {
+ *     Round[x][32:0] = Mres[x][46:14] + 1;
+ *     Rd.W[x] = Round[x][32:1];
+ *   } else {
+ *     Rd.W[x] = Mres[x][46:15];
+ *   }
+ * }
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMMWT2(long a, unsigned long b)
+{
+    register long result;
+    __ASM volatile("kmmwt2 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.50.1. KMMWT2 ===== */
+
+/* ===== Inline Function Start for 3.50.2. KMMWT2.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
+ * \brief KMMWT2.u (SIMD Saturating MSW Signed Multiply Word and Top Half & 2 with Rounding)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMMWT2 Rd, Rs1, Rs2
+ * KMMWT2.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit integer elements of one register and the top 16-bit of the
+ * corresponding 32-bit elements of another register, double the multiplication results and write the
+ * saturated most significant 32-bit results to the corresponding 32-bit elements of a register. The `.u`
+ * form rounds up the results from the most significant discarded bit.
+ *
+ * **Description**:\n
+ * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed top 16-bit Q15
+ * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and
+ * writes the saturated most significant 32-bit Q31 multiplication results to the corresponding 32-bit
+ * elements of Rd. The `.u` form of the instruction rounds up the most significant 32-bit of the 48-bit
+ * Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of the results.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[1] == 0x8000)) {
+ *   Rd.W[x] = 0x7fffffff;
+ *   OV = 1;
+ * } else {
+ *   Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[1];
+ *   if (`.u` form) {
+ *     Round[x][32:0] = Mres[x][46:14] + 1;
+ *     Rd.W[x] = Round[x][32:1];
+ *   } else {
+ *     Rd.W[x] = Mres[x][46:15];
+ *   }
+ * }
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMMWT2_U(long a, unsigned long b)
+{
+    register long result;
+    __ASM volatile("kmmwt2.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.50.2. KMMWT2.u ===== */
+
+/* ===== Inline Function Start for 3.51.1. KMSDA ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
+ * \brief KMSDA (SIMD Saturating Signed Multiply Two Halfs & Add & Subtract)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMSDA Rd, Rs1, Rs2
+ * KMSXDA Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
+ * subtracts the two 32-bit results from the corresponding 32-bit elements of a third register. The
+ * subtraction result may be saturated.
+ * * KMSDA: rd.W[x] - top*top - bottom*bottom (per 32-bit element)
+ * * KMSXDA: rd.W[x] - top*bottom - bottom*top (per 32-bit element)
+ *
+ * **Description**:\n
+ * For the `KMSDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of
+ * the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2.
+ * For the `KMSXDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the top 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of the
+ * 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2.
+ * The two 32-bit multiplication results are then subtracted from the content of the corresponding 32-
+ * bit elements of Rd. If the subtraction result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is
+ * saturated to the range and the OV bit is set to 1. The results after saturation are written to Rd. The
+ * 16-bit contents are treated as signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * // KMSDA
+ * res[x] = Rd.W[x] - (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]);
+ * // KMSXDA
+ * res[x] = Rd.W[x] - (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]);
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMSDA(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmsda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.51.1. KMSDA ===== */
+
+/* ===== Inline Function Start for 3.51.2. KMSXDA ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
+ * \brief KMSXDA (SIMD Saturating Signed Crossed Multiply Two Halfs & Add & Subtract)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMSDA Rd, Rs1, Rs2
+ * KMSXDA Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
+ * subtracts the two 32-bit results from the corresponding 32-bit elements of a third register. The
+ * subtraction result may be saturated.
+ * * KMSDA: rd.W[x] - top*top - bottom*bottom (per 32-bit element)
+ * * KMSXDA: rd.W[x] - top*bottom - bottom*top (per 32-bit element)
+ *
+ * **Description**:\n
+ * For the `KMSDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of
+ * the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2.
+ * For the `KMSXDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the top 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of the
+ * 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2.
+ * The two 32-bit multiplication results are then subtracted from the content of the corresponding 32-
+ * bit elements of Rd. If the subtraction result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is
+ * saturated to the range and the OV bit is set to 1. The results after saturation are written to Rd. The
+ * 16-bit contents are treated as signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * // KMSDA
+ * res[x] = Rd.W[x] - (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]);
+ * // KMSXDA
+ * res[x] = Rd.W[x] - (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]);
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMSXDA(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmsxda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.51.2. KMSXDA ===== */
+
+/* ===== Inline Function Start for 3.52. KMSR64 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB
+ * \brief KMSR64 (Signed Multiply and Saturating Subtract from 64-Bit Data)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMSR64 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the 32-bit signed elements in two registers and subtract the 64-bit multiplication
+ * results from the 64-bit signed data of a pair of registers (RV32) or a register (RV64). The result is
+ * saturated to the Q63 range and written back to the pair of registers (RV32) or the register (RV64).
+ *
+ * **RV32 Description**:\n
+ * This instruction multiplies the 32-bit signed data of Rs1 with that of Rs2. It
+ * subtracts the 64-bit multiplication result from the 64-bit signed data of an even/odd pair of registers
+ * specified by Rd(4,1) with unlimited precision. If the 64-bit subtraction result is beyond the Q63
+ * number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The saturated
+ * result is written back to the even/odd pair of registers specified by Rd(4,1).
+ * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
+ * of the pair contains the low 32-bit of the result.
+ *
+ * **RV64 Description**:\n
+ * This instruction multiplies the 32-bit signed elements of Rs1 with that of Rs2. It
+ * subtracts the 64-bit multiplication results from the 64-bit signed data in Rd with unlimited
+ * precision. If the 64-bit subtraction result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is
+ * saturated to the range and the OV bit is set to 1. The saturated result is written back to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * RV32:
+ * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
+ * result = R[t_H].R[t_L] - (Rs1 * Rs2);
+ * if (result > (2^63)-1) {
+ *   result = (2^63)-1; OV = 1;
+ * } else if (result < -2^63) {
+ *   result = -2^63; OV = 1;
+ * }
+ * R[t_H].R[t_L] = result;
+ * RV64:
+ * // `result` has unlimited precision
+ * result = Rd - (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]);
+ * if (result > (2^63)-1) {
+ *   result = (2^63)-1; OV = 1;
+ * } else if (result < -2^63) {
+ *   result = -2^63; OV = 1;
+ * }
+ * Rd = result;
+ * ~~~
+ *
+ * \param [in]  t    long long type of value stored in t
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    long type of value stored in b
+ * \return value stored in long long type
+ */
+__STATIC_FORCEINLINE long long __RV_KMSR64(long long t, long a, long b)
+{
+    __ASM volatile("kmsr64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.52. KMSR64 ===== */
+
+/* ===== Inline Function Start for 3.53. KSLLW ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
+ * \brief KSLLW (Saturating Shift Left Logical for Word)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSLLW Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do logical left shift operation with saturation on a 32-bit word. The shift amount is a
+ * variable from a GPR.
+ *
+ * **Description**:\n
+ * The first word data in Rs1 is left-shifted logically. The shifted out bits are filled with
+ * zero and the shift amount is specified by the low-order 5-bits of the value in the Rs2 register. Any
+ * shifted value greater than 2^31-1 is saturated to 2^31-1. Any shifted value smaller than -2^31 is saturated
+ * to -2^31. And the saturated result is sign-extended and written to Rd. If any saturation is performed,
+ * set OV bit to 1.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = Rs2[4:0];
+ * res[(31+sa):0] = Rs1.W[0] << sa;
+ * if (res > (2^31)-1) {
+ *   res = 0x7fffffff; OV = 1;
+ * } else if (res < -2^31) {
+ *   res = 0x80000000; OV = 1;
+ * }
+ * Rd[31:0] = res[31:0]; // RV32
+ * Rd[63:0] = SE(res[31:0]); // RV64
+ * ~~~
+ *
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KSLLW(long a, unsigned int b)
+{
+    register long result;
+    __ASM volatile("ksllw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.53. KSLLW ===== */
+
+/* ===== Inline Function Start for 3.54. KSLLIW ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
+ * \brief KSLLIW (Saturating Shift Left Logical Immediate for Word)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSLLIW Rd, Rs1, imm5u
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do logical left shift operation with saturation on a 32-bit word. The shift amount is an
+ * immediate value.
+ *
+ * **Description**:\n
+ * The first word data in Rs1 is left-shifted logically. The shifted out bits are filled with
+ * zero and the shift amount is specified by the imm5u constant. Any shifted value greater than 2^31-1 is
+ * saturated to 2^31-1. Any shifted value smaller than -2^31 is saturated to -2^31. And the saturated result is
+ * sign-extended and written to Rd. If any saturation is performed, set OV bit to 1.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = imm5u;
+ * res[(31+sa):0] = Rs1.W[0] << sa;
+ * if (res > (2^31)-1) {
+ *   res = 0x7fffffff; OV = 1;
+ * } else if (res < -2^31) {
+ *   res = 0x80000000; OV = 1;
+ * }
+ * Rd[31:0] = res[31:0]; // RV32
+ * Rd[63:0] = SE(res[31:0]); // RV64
+ * ~~~
+ *
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in long type
+ */
+#define __RV_KSLLIW(a, b)    \
+    ({    \
+        register long result;    \
+        register long __a = (long)(a);    \
+        __ASM volatile("kslliw %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
+        result;    \
+    })
+/* ===== Inline Function End for 3.54. KSLLIW ===== */
+
+/* ===== Inline Function Start for 3.55. KSLL8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
+ * \brief KSLL8 (SIMD 8-bit Saturating Shift Left Logical)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSLL8 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit elements logical left shift operations with saturation simultaneously. The shift
+ * amount is a variable from a GPR.
+ *
+ * **Description**:\n
+ * The 8-bit data elements in Rs1 are left-shifted logically. The shifted out bits are filled
+ * with zero and the shift amount is specified by the low-order 3-bits of the value in the Rs2 register.
+ * Any shifted value greater than 2^7-1 is saturated to 2^7-1. Any shifted value smaller than -2^7 is
+ * saturated to -2^7. And the saturated results are written to Rd. If any saturation is performed, set OV
+ * bit to 1.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = Rs2[2:0];
+ * if (sa != 0) {
+ *   res[(7+sa):0] = Rs1.B[x] << sa;
+ *   if (res > (2^7)-1) {
+ *     res = 0x7f; OV = 1;
+ *   } else if (res < -2^7) {
+ *     res = 0x80; OV = 1;
+ *   }
+ *   Rd.B[x] = res[7:0];
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KSLL8(unsigned long a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("ksll8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.55. KSLL8 ===== */
+
+/* ===== Inline Function Start for 3.56. KSLLI8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
+ * \brief KSLLI8 (SIMD 8-bit Saturating Shift Left Logical Immediate)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSLLI8 Rd, Rs1, imm3u
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit elements logical left shift operations with saturation simultaneously. The shift
+ * amount is an immediate value.
+ *
+ * **Description**:\n
+ * The 8-bit data elements in Rs1 are left-shifted logically. The shifted out bits are filled
+ * with zero and the shift amount is specified by the imm3u constant. Any shifted value greater than
+ * 2^7-1 is saturated to 2^7-1. Any shifted value smaller than -2^7 is saturated to -2^7. And the saturated
+ * results are written to Rd. If any saturation is performed, set OV bit to 1.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = imm3u[2:0];
+ * if (sa != 0) {
+ *   res[(7+sa):0] = Rs1.B[x] << sa;
+ *   if (res > (2^7)-1) {
+ *     res = 0x7f; OV = 1;
+ *   } else if (res < -2^7) {
+ *     res = 0x80; OV = 1;
+ *   }
+ *   Rd.B[x] = res[7:0];
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+#define __RV_KSLLI8(a, b)    \
+    ({    \
+        register unsigned long result;    \
+        register unsigned long __a = (unsigned long)(a);    \
+        __ASM volatile("kslli8 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
+        result;    \
+    })
+/* ===== Inline Function End for 3.56. KSLLI8 ===== */
+
+/* ===== Inline Function Start for 3.57. KSLL16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
+ * \brief KSLL16 (SIMD 16-bit Saturating Shift Left Logical)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSLL16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit elements logical left shift operations with saturation simultaneously. The shift
+ * amount is a variable from a GPR.
+ *
+ * **Description**:\n
+ * The 16-bit data elements in Rs1 are left-shifted logically. The shifted out bits are filled
+ * with zero and the shift amount is specified by the low-order 4-bits of the value in the Rs2 register.
+ * Any shifted value greater than 2^15-1 is saturated to 2^15-1. Any shifted value smaller than -2^15 is
+ * saturated to -2^15. And the saturated results are written to Rd. If any saturation is performed, set OV
+ * bit to 1.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = Rs2[3:0];
+ * if (sa != 0) {
+ *   res[(15+sa):0] = Rs1.H[x] << sa;
+ *   if (res > (2^15)-1) {
+ *     res = 0x7fff; OV = 1;
+ *   } else if (res < -2^15) {
+ *     res = 0x8000; OV = 1;
+ *   }
+ *   Rd.H[x] = res[15:0];
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KSLL16(unsigned long a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("ksll16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.57. KSLL16 ===== */
+
+/* ===== Inline Function Start for 3.58. KSLLI16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
+ * \brief KSLLI16 (SIMD 16-bit Saturating Shift Left Logical Immediate)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSLLI16 Rd, Rs1, imm4u
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit elements logical left shift operations with saturation simultaneously. The shift
+ * amount is an immediate value.
+ *
+ * **Description**:\n
+ * The 16-bit data elements in Rs1 are left-shifted logically. The shifted out bits are filled
+ * with zero and the shift amount is specified by the imm4u constant. Any shifted value greater than
+ * 2^15-1 is saturated to 2^15-1. Any shifted value smaller than -2^15 is saturated to -2^15. And the saturated
+ * results are written to Rd. If any saturation is performed, set OV bit to 1.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = imm4u[3:0];
+ * if (sa != 0) {
+ *   res[(15+sa):0] = Rs1.H[x] << sa;
+ *   if (res > (2^15)-1) {
+ *     res = 0x7fff; OV = 1;
+ *   } else if (res < -2^15) {
+ *     res = 0x8000; OV = 1;
+ *   }
+ *   Rd.H[x] = res[15:0];
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+#define __RV_KSLLI16(a, b)    \
+    ({    \
+        register unsigned long result;    \
+        register unsigned long __a = (unsigned long)(a);    \
+        __ASM volatile("kslli16 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
+        result;    \
+    })
+/* ===== Inline Function End for 3.58. KSLLI16 ===== */
+
+/* ===== Inline Function Start for 3.59.1. KSLRA8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
+ * \brief KSLRA8 (SIMD 8-bit Shift Left Logical with Saturation or Shift Right Arithmetic)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSLRA8 Rd, Rs1, Rs2
+ * KSLRA8.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit elements logical left (positive) or arithmetic right (negative) shift operation with
+ * Q7 saturation for the left shift. The `.u` form performs additional rounding up operations for the
+ * right shift.
+ *
+ * **Description**:\n
+ * The 8-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically
+ * based on the value of Rs2[3:0]. Rs2[3:0] is in the signed range of [-2^3, 2^3-1]. A positive Rs2[3:0] means
+ * logical left shift and a negative Rs2[3:0] means arithmetic right shift. The shift amount is the
+ * absolute value of Rs2[3:0]. However, the behavior of `Rs2[3:0]==-2^3 (0x8)` is defined to be
+ * equivalent to the behavior of `Rs2[3:0]==-(2^3-1) (0x9)`.
+ * The left-shifted results are saturated to the 8-bit signed integer range of [-2^7, 2^7-1]. For the `.u` form
+ * of the instruction, the right-shifted results are added a 1 to the most significant discarded bit
+ * position for rounding effect. After the shift, saturation, or rounding, the final results are written to
+ * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:4] will not affect
+ * this instruction.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if (Rs2[3:0] < 0) {
+ *   sa = -Rs2[3:0];
+ *   sa = (sa == 8)? 7 : sa;
+ *   if (`.u` form) {
+ *     res[7:-1] = SE9(Rs1.B[x][7:sa-1]) + 1;
+ *     Rd.B[x] = res[7:0];
+ *   } else {
+ *     Rd.B[x] = SE8(Rs1.B[x][7:sa]);
+ *   }
+ * } else {
+ *   sa = Rs2[2:0];
+ *   res[(7+sa):0] = Rs1.B[x] <<(logic) sa;
+ *   if (res > (2^7)-1) {
+ *     res[7:0] = 0x7f; OV = 1;
+ *   } else if (res < -2^7) {
+ *     res[7:0] = 0x80; OV = 1;
+ *   }
+ *   Rd.B[x] = res[7:0];
+ * }
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KSLRA8(unsigned long a, int b)
+{
+    register unsigned long result;
+    __ASM volatile("kslra8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.59.1. KSLRA8 ===== */
+
+/* ===== Inline Function Start for 3.59.2. KSLRA8.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
+ * \brief KSLRA8.u (SIMD 8-bit Shift Left Logical with Saturation or Rounding Shift Right Arithmetic)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSLRA8 Rd, Rs1, Rs2
+ * KSLRA8.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit elements logical left (positive) or arithmetic right (negative) shift operation with
+ * Q7 saturation for the left shift. The `.u` form performs additional rounding up operations for the
+ * right shift.
+ *
+ * **Description**:\n
+ * The 8-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically
+ * based on the value of Rs2[3:0]. Rs2[3:0] is in the signed range of [-2^3, 2^3-1]. A positive Rs2[3:0] means
+ * logical left shift and a negative Rs2[3:0] means arithmetic right shift. The shift amount is the
+ * absolute value of Rs2[3:0]. However, the behavior of `Rs2[3:0]==-2^3 (0x8)` is defined to be
+ * equivalent to the behavior of `Rs2[3:0]==-(2^3-1) (0x9)`.
+ * The left-shifted results are saturated to the 8-bit signed integer range of [-2^7, 2^7-1]. For the `.u` form
+ * of the instruction, the right-shifted results are added a 1 to the most significant discarded bit
+ * position for rounding effect. After the shift, saturation, or rounding, the final results are written to
+ * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:4] will not affect
+ * this instruction.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if (Rs2[3:0] < 0) {
+ *   sa = -Rs2[3:0];
+ *   sa = (sa == 8)? 7 : sa;
+ *   if (`.u` form) {
+ *     res[7:-1] = SE9(Rs1.B[x][7:sa-1]) + 1;
+ *     Rd.B[x] = res[7:0];
+ *   } else {
+ *     Rd.B[x] = SE8(Rs1.B[x][7:sa]);
+ *   }
+ * } else {
+ *   sa = Rs2[2:0];
+ *   res[(7+sa):0] = Rs1.B[x] <<(logic) sa;
+ *   if (res > (2^7)-1) {
+ *     res[7:0] = 0x7f; OV = 1;
+ *   } else if (res < -2^7) {
+ *     res[7:0] = 0x80; OV = 1;
+ *   }
+ *   Rd.B[x] = res[7:0];
+ * }
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KSLRA8_U(unsigned long a, int b)
+{
+    register unsigned long result;
+    __ASM volatile("kslra8.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.59.2. KSLRA8.u ===== */
+
+/* ===== Inline Function Start for 3.60.1. KSLRA16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
+ * \brief KSLRA16 (SIMD 16-bit Shift Left Logical with Saturation or Shift Right Arithmetic)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSLRA16 Rd, Rs1, Rs2
+ * KSLRA16.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit elements logical left (positive) or arithmetic right (negative) shift operation with
+ * Q15 saturation for the left shift. The `.u` form performs additional rounding up operations for the
+ * right shift.
+ *
+ * **Description**:\n
+ * The 16-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically
+ * based on the value of Rs2[4:0]. Rs2[4:0] is in the signed range of [-2^4, 2^4-1]. A positive Rs2[4:0] means
+ * logical left shift and a negative Rs2[4:0] means arithmetic right shift. The shift amount is the
+ * absolute value of Rs2[4:0]. However, the behavior of `Rs2[4:0]==-2^4 (0x10)` is defined to be
+ * equivalent to the behavior of `Rs2[4:0]==-(2^4-1) (0x11)`.
+ * The left-shifted results are saturated to the 16-bit signed integer range of [-2^15, 2^15-1]. For the `.u`
+ * form of the instruction, the right-shifted results are added a 1 to the most significant discarded bit
+ * position for rounding effect. After the shift, saturation, or rounding, the final results are written to
+ * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:5] will not affect
+ * this instruction.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if (Rs2[4:0] < 0) {
+ *   sa = -Rs2[4:0];
+ *   sa = (sa == 16)? 15 : sa;
+ *   if (`.u` form) {
+ *     res[15:-1] = SE17(Rs1.H[x][15:sa-1]) + 1;
+ *     Rd.H[x] = res[15:0];
+ *   } else {
+ *     Rd.H[x] = SE16(Rs1.H[x][15:sa]);
+ *   }
+ * } else {
+ *   sa = Rs2[3:0];
+ *   res[(15+sa):0] = Rs1.H[x] <<(logic) sa;
+ *   if (res > (2^15)-1) {
+ *     res[15:0] = 0x7fff; OV = 1;
+ *   } else if (res < -2^15) {
+ *     res[15:0] = 0x8000; OV = 1;
+ *   }
+ *   d.H[x] = res[15:0];
+ * }
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KSLRA16(unsigned long a, int b)
+{
+    register unsigned long result;
+    __ASM volatile("kslra16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.60.1. KSLRA16 ===== */
+
+/* ===== Inline Function Start for 3.60.2. KSLRA16.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
+ * \brief KSLRA16.u (SIMD 16-bit Shift Left Logical with Saturation or Rounding Shift Right Arithmetic)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSLRA16 Rd, Rs1, Rs2
+ * KSLRA16.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit elements logical left (positive) or arithmetic right (negative) shift operation with
+ * Q15 saturation for the left shift. The `.u` form performs additional rounding up operations for the
+ * right shift.
+ *
+ * **Description**:\n
+ * The 16-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically
+ * based on the value of Rs2[4:0]. Rs2[4:0] is in the signed range of [-2^4, 2^4-1]. A positive Rs2[4:0] means
+ * logical left shift and a negative Rs2[4:0] means arithmetic right shift. The shift amount is the
+ * absolute value of Rs2[4:0]. However, the behavior of `Rs2[4:0]==-2^4 (0x10)` is defined to be
+ * equivalent to the behavior of `Rs2[4:0]==-(2^4-1) (0x11)`.
+ * The left-shifted results are saturated to the 16-bit signed integer range of [-2^15, 2^15-1]. For the `.u`
+ * form of the instruction, the right-shifted results are added a 1 to the most significant discarded bit
+ * position for rounding effect. After the shift, saturation, or rounding, the final results are written to
+ * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:5] will not affect
+ * this instruction.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if (Rs2[4:0] < 0) {
+ *   sa = -Rs2[4:0];
+ *   sa = (sa == 16)? 15 : sa;
+ *   if (`.u` form) {
+ *     res[15:-1] = SE17(Rs1.H[x][15:sa-1]) + 1;
+ *     Rd.H[x] = res[15:0];
+ *   } else {
+ *     Rd.H[x] = SE16(Rs1.H[x][15:sa]);
+ *   }
+ * } else {
+ *   sa = Rs2[3:0];
+ *   res[(15+sa):0] = Rs1.H[x] <<(logic) sa;
+ *   if (res > (2^15)-1) {
+ *     res[15:0] = 0x7fff; OV = 1;
+ *   } else if (res < -2^15) {
+ *     res[15:0] = 0x8000; OV = 1;
+ *   }
+ *   d.H[x] = res[15:0];
+ * }
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KSLRA16_U(unsigned long a, int b)
+{
+    register unsigned long result;
+    __ASM volatile("kslra16.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.60.2. KSLRA16.u ===== */
+
+/* ===== Inline Function Start for 3.61. KSLRAW ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
+ * \brief KSLRAW (Shift Left Logical with Q31 Saturation or Shift Right Arithmetic)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSLRAW Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Perform a logical left (positive) or arithmetic right (negative) shift operation with Q31
+ * saturation for the left shift on a 32-bit data.
+ *
+ * **Description**:\n
+ * The lower 32-bit content of Rs1 is left-shifted logically or right-shifted arithmetically
+ * based on the value of Rs2[5:0]. Rs2[5:0] is in the signed range of [-25, 25-1]. A positive Rs2[5:0] means
+ * logical left shift and a negative Rs2[5:0] means arithmetic right shift. The shift amount is the
+ * absolute value of Rs2[5:0] clamped to the actual shift range of [0, 31].
+ * The left-shifted result is saturated to the 32-bit signed integer range of [-2^31, 2^31-1]. After the shift
+ * operation, the final result is bit-31 sign-extended and written to Rd. If any saturation happens, this
+ * instruction sets the OV flag. The value of Rs2[31:6] will not affected the operation of this instruction.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if (Rs2[5:0] < 0) {
+ *   sa = -Rs2[5:0];
+ *   sa = (sa == 32)? 31 : sa;
+ *   res[31:0] = Rs1.W[0] >>(arith) sa;
+ * } else {
+ *   sa = Rs2[5:0];
+ *   tmp = Rs1.W[0] <<(logic) sa;
+ *   if (tmp > (2^31)-1) {
+ *     res[31:0] = (2^31)-1;
+ *     OV = 1;
+ *   } else if (tmp < -2^31) {
+ *     res[31:0] = -2^31;
+ *     OV = 1
+ *   } else {
+ *     res[31:0] = tmp[31:0];
+ *   }
+ * }
+ * Rd = res[31:0]; // RV32
+ * Rd = SE64(res[31:0]); // RV64
+ * ~~~
+ *
+ * \param [in]  a    int type of value stored in a
+ * \param [in]  b    int type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KSLRAW(int a, int b)
+{
+    register long result;
+    __ASM volatile("kslraw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.61. KSLRAW ===== */
+
+/* ===== Inline Function Start for 3.62. KSLRAW.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
+ * \brief KSLRAW.u (Shift Left Logical with Q31 Saturation or Rounding Shift Right Arithmetic)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSLRAW.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Perform a logical left (positive) or arithmetic right (negative) shift operation with Q31
+ * saturation for the left shift and a rounding up operation for the right shift on a 32-bit data.
+ *
+ * **Description**:\n
+ * The lower 32-bit content of Rs1 is left-shifted logically or right-shifted arithmetically
+ * based on the value of Rs2[5:0]. Rs2[5:0] is in the signed range of [-25, 25-1]. A positive Rs2[5:0] means
+ * logical left shift and a negative Rs2[5:0] means arithmetic right shift. The shift amount is the
+ * absolute value of Rs2[5:0] clamped to the actual shift range of [0, 31].
+ * The left-shifted result is saturated to the 32-bit signed integer range of [-2^31, 2^31-1]. The right-shifted
+ * result is added a 1 to the most significant discarded bit position for rounding effect. After the shift,
+ * saturation, or rounding, the final result is bit-31 sign-extended and written to Rd. If any saturation
+ * happens, this instruction sets the OV flag. The value of Rs2[31:6] will not affect the operation of this
+ * instruction.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if (Rs2[5:0] < 0) {
+ *   sa = -Rs2[5:0];
+ *   sa = (sa == 32)? 31 : sa;
+ *   res[31:-1] = SE33(Rs1[31:(sa-1)]) + 1;
+ *   rst[31:0] = res[31:0];
+ * } else {
+ *   sa = Rs2[5:0];
+ *   tmp = Rs1.W[0] <<(logic) sa;
+ *   if (tmp > (2^31)-1) {
+ *     rst[31:0] = (2^31)-1;
+ *     OV = 1;
+ *   } else if (tmp < -2^31) {
+ *     rst[31:0] = -2^31;
+ *     OV = 1
+ *   } else {
+ *     rst[31:0] = tmp[31:0];
+ *   }
+ * }
+ * Rd = rst[31:0]; // RV32
+ * Rd = SE64(rst[31:0]); // RV64
+ * ~~~
+ *
+ * \param [in]  a    int type of value stored in a
+ * \param [in]  b    int type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KSLRAW_U(int a, int b)
+{
+    register long result;
+    __ASM volatile("kslraw.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.62. KSLRAW.u ===== */
+
+/* ===== Inline Function Start for 3.63. KSTAS16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief KSTAS16 (SIMD 16-bit Signed Saturating Straight Addition & Subtraction)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSTAS16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit signed integer element saturating addition and 16-bit signed integer element
+ * saturating subtraction in a 32-bit chunk simultaneously. Operands are from corresponding
+ * positions in 32-bit chunks.
+ *
+ * **Description**:\n
+ * This instruction adds the 16-bit signed integer element in [31:16] of 32-bit chunks in
+ * Rs1 with the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs2; at the same time, it
+ * subtracts the 16-bit signed integer element in [15:0] of 32-bit chunks in Rs2 from the 16-bit signed
+ * integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the Q15 number
+ * range (-2^15 <= Q15 <= 2^15-1), they are saturated to the range and the OV bit is set to 1. The saturated
+ * results are written to [31:16] of 32-bit chunks in Rd for addition and [15:0] of 32-bit chunks in Rd for
+ * subtraction.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res1 = Rs1.W[x][31:16] + Rs2.W[x][31:16];
+ * res2 = Rs1.W[x][15:0] - Rs2.W[x][15:0];
+ * for (res in [res1, res2]) {
+ *   if (res > (2^15)-1) {
+ *     res = (2^15)-1;
+ *     OV = 1;
+ *   } else if (res < -2^15) {
+ *     res = -2^15;
+ *     OV = 1;
+ *   }
+ * }
+ * Rd.W[x][31:16] = res1;
+ * Rd.W[x][15:0] = res2;
+ * for RV32, x=0
+ * for RV64, x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KSTAS16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("kstas16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.63. KSTAS16 ===== */
+
+/* ===== Inline Function Start for 3.64. KSTSA16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief KSTSA16 (SIMD 16-bit Signed Saturating Straight Subtraction & Addition)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSTSA16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit signed integer element saturating subtraction and 16-bit signed integer element
+ * saturating addition in a 32-bit chunk simultaneously. Operands are from corresponding positions in
+ * 32-bit chunks.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 16-bit signed integer element in [31:16] of 32-bit chunks
+ * in Rs2 from the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs1; at the same time, it
+ * adds the 16-bit signed integer element in [15:0] of 32-bit chunks in Rs2 with the 16-bit signed integer
+ * element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the Q15 number range (-2^15
+ * <= Q15 <= 2^15-1), they are saturated to the range and the OV bit is set to 1. The saturated results are
+ * written to [31:16] of 32-bit chunks in Rd for subtraction and [15:0] of 32-bit chunks in Rd for
+ * addition.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res1 = Rs1.W[x][31:16] - Rs2.W[x][31:16];
+ * res2 = Rs1.W[x][15:0] + Rs2.W[x][15:0];
+ * for (res in [res1, res2]) {
+ *   if (res > (2^15)-1) {
+ *     res = (2^15)-1;
+ *     OV = 1;
+ *   } else if (res < -2^15) {
+ *     res = -2^15;
+ *     OV = 1;
+ *   }
+ * }
+ * Rd.W[x][31:16] = res1;
+ * Rd.W[x][15:0] = res2;
+ * for RV32, x=0
+ * for RV64, x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KSTSA16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("kstsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.64. KSTSA16 ===== */
+
+/* ===== Inline Function Start for 3.65. KSUB8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB
+ * \brief KSUB8 (SIMD 8-bit Signed Saturating Subtraction)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSUB8 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit signed elements saturating subtractions simultaneously.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 8-bit signed integer elements in Rs2 from the 8-bit
+ * signed integer elements in Rs1. If any of the results are beyond the Q7 number range (-2^7 <= Q7 <= 27
+ * -1), they are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[x] = Rs1.B[x] - Rs2.B[x];
+ * if (res[x] > (2^7)-1) {
+ *   res[x] = (2^7)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^7) {
+ *   res[x] = -2^7;
+ *   OV = 1;
+ * }
+ * Rd.B[x] = res[x];
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KSUB8(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("ksub8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.65. KSUB8 ===== */
+
+/* ===== Inline Function Start for 3.66. KSUB16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief KSUB16 (SIMD 16-bit Signed Saturating Subtraction)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSUB16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit signed integer elements saturating subtractions simultaneously.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 16-bit signed integer elements in Rs2 from the 16-bit
+ * signed integer elements in Rs1. If any of the results are beyond the Q15 number range (-2^15 <= Q15 <=
+ * 2^15-1), they are saturated to the range and the OV bit is set to 1. The saturated results are written to
+ * Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[x] = Rs1.H[x] - Rs2.H[x];
+ * if (res[x] > (2^15)-1) {
+ *   res[x] = (2^15)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^15) {
+ *   res[x] = -2^15;
+ *   OV = 1;
+ * }
+ * Rd.H[x] = res[x];
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KSUB16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("ksub16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.66. KSUB16 ===== */
+
+/* ===== Inline Function Start for 3.67. KSUB64 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB
+ * \brief KSUB64 (64-bit Signed Saturating Subtraction)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSUB64 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Perform a 64-bit signed integer subtraction. The result is saturated to the Q63 range.
+ *
+ * **RV32 Description**:\n
+ * This instruction subtracts the 64-bit signed integer of an even/odd pair of
+ * registers specified by Rs2(4,1) from the 64-bit signed integer of an even/odd pair of registers
+ * specified by Rs1(4,1). If the 64-bit result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is
+ * saturated to the range and the OV bit is set to 1. The saturated result is then written to an even/odd
+ * pair of registers specified by Rd(4,1).
+ * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d`
+ * register of the pair contains the low 32-bit of the operand.
+ *
+ * **RV64 Description**:\n
+ * This instruction subtracts the 64-bit signed integer of Rs2 from the 64-bit signed
+ * integer of Rs1. If the 64-bit result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated
+ * to the range and the OV bit is set to 1. The saturated result is then written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * RV32:
+ * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
+ * a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1);
+ * b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1);
+ * result = R[a_H].R[a_L] - R[b_H].R[b_L];
+ * if (result > (2^63)-1) {
+ *   result = (2^63)-1; OV = 1;
+ * } else if (result < -2^63) {
+ *   result = -2^63; OV = 1;
+ * }
+ * R[t_H].R[t_L] = result;
+ * RV64:
+ * result = Rs1 - Rs2;
+ * if (result > (2^63)-1) {
+ *   result = (2^63)-1; OV = 1;
+ * } else if (result < -2^63) {
+ *   result = -2^63; OV = 1;
+ * }
+ * Rd = result;
+ * ~~~
+ *
+ * \param [in]  a    long long type of value stored in a
+ * \param [in]  b    long long type of value stored in b
+ * \return value stored in long long type
+ */
+__STATIC_FORCEINLINE long long __RV_KSUB64(long long a, long long b)
+{
+    register long long result;
+    __ASM volatile("ksub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.67. KSUB64 ===== */
+
+/* ===== Inline Function Start for 3.68. KSUBH ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU
+ * \brief KSUBH (Signed Subtraction with Q15 Saturation)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSUBH Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Subtract the signed lower 32-bit content of two registers with Q15 saturation.
+ *
+ * **Description**:\n
+ * The signed lower 32-bit content of Rs2 is subtracted from the signed lower 32-bit
+ * content of Rs1. And the result is saturated to the 16-bit signed integer range of [-2^15, 2^15-1] and then
+ * sign-extended and written to Rd. If saturation happens, this instruction sets the OV flag.
+ *
+ * **Operations**:\n
+ * ~~~
+ * tmp = Rs1.W[0] - Rs2.W[0];
+ * if (tmp > (2^15)-1) {
+ *   res = (2^15)-1;
+ *   OV = 1;
+ * } else if (tmp < -2^15) {
+ *   res = -2^15;
+ *   OV = 1
+ * } else {
+ *   res = tmp;
+ * }
+ * Rd = SE(res[15:0]);
+ * ~~~
+ *
+ * \param [in]  a    int type of value stored in a
+ * \param [in]  b    int type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KSUBH(int a, int b)
+{
+    register long result;
+    __ASM volatile("ksubh %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.68. KSUBH ===== */
+
+/* ===== Inline Function Start for 3.69. KSUBW ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
+ * \brief KSUBW (Signed Subtraction with Q31 Saturation)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSUBW Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Subtract the signed lower 32-bit content of two registers with Q31 saturation.
+ *
+ * **Description**:\n
+ * The signed lower 32-bit content of Rs2 is subtracted from the signed lower 32-bit
+ * content of Rs1. And the result is saturated to the 32-bit signed integer range of [-2^31, 2^31-1] and then
+ * sign-extened and written to Rd. If saturation happens, this instruction sets the OV flag.
+ *
+ * **Operations**:\n
+ * ~~~
+ * tmp = Rs1.W[0] - Rs2.W[0];
+ * if (tmp > (2^31)-1) {
+ *   res = (2^31)-1;
+ *   OV = 1;
+ * } else if (tmp < -2^31) {
+ * res = -2^31;
+ *   OV = 1
+ * } else {
+ *   res = tmp;
+ * }
+ * Rd = res[31:0]; // RV32
+ * Rd = SE(res[31:0]); // RV64
+ * ~~~
+ *
+ * \param [in]  a    int type of value stored in a
+ * \param [in]  b    int type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KSUBW(int a, int b)
+{
+    register long result;
+    __ASM volatile("ksubw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.69. KSUBW ===== */
+
+/* ===== Inline Function Start for 3.70.1. KWMMUL ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC
+ * \brief KWMMUL (SIMD Saturating MSW Signed Multiply Word & Double)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KWMMUL Rd, Rs1, Rs2
+ * KWMMUL.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit integer elements of two registers, shift the results left 1-bit,
+ * saturate, and write the most significant 32-bit results to a register. The `.u` form additionally
+ * rounds up the multiplication results from the most signification discarded bit.
+ *
+ * **Description**:\n
+ * This instruction multiplies the 32-bit elements of Rs1 with the 32-bit elements of Rs2. It then shifts
+ * the multiplication results one bit to the left and takes the most significant 32-bit results. If the
+ * shifted result is greater than 2^31-1, it is saturated to 2^31-1 and the OV flag is set to 1. The final element
+ * result is written to Rd. The 32-bit elements of Rs1 and Rs2 are treated as signed integers. The `.u`
+ * form of the instruction additionally rounds up the 64-bit multiplication results by adding a 1 to bit
+ * 30 before the shift and saturation operations.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if ((0x80000000 != Rs1.W[x]) | (0x80000000 != Rs2.W[x])) {
+ *   Mres[x][63:0] = Rs1.W[x] * Rs2.W[x];
+ *   if (`.u` form) {
+ *     Round[x][33:0] = Mres[x][63:30] + 1;
+ *     Rd.W[x] = Round[x][32:1];
+ *   } else {
+ *     Rd.W[x] = Mres[x][62:31];
+ *   }
+ * } else {
+ *   Rd.W[x] = 0x7fffffff;
+ *   OV = 1;
+ * }
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KWMMUL(long a, long b)
+{
+    register long result;
+    __ASM volatile("kwmmul %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.70.1. KWMMUL ===== */
+
+/* ===== Inline Function Start for 3.70.2. KWMMUL.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC
+ * \brief KWMMUL.u (SIMD Saturating MSW Signed Multiply Word & Double with Rounding)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KWMMUL Rd, Rs1, Rs2
+ * KWMMUL.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit integer elements of two registers, shift the results left 1-bit,
+ * saturate, and write the most significant 32-bit results to a register. The `.u` form additionally
+ * rounds up the multiplication results from the most signification discarded bit.
+ *
+ * **Description**:\n
+ * This instruction multiplies the 32-bit elements of Rs1 with the 32-bit elements of Rs2. It then shifts
+ * the multiplication results one bit to the left and takes the most significant 32-bit results. If the
+ * shifted result is greater than 2^31-1, it is saturated to 2^31-1 and the OV flag is set to 1. The final element
+ * result is written to Rd. The 32-bit elements of Rs1 and Rs2 are treated as signed integers. The `.u`
+ * form of the instruction additionally rounds up the 64-bit multiplication results by adding a 1 to bit
+ * 30 before the shift and saturation operations.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if ((0x80000000 != Rs1.W[x]) | (0x80000000 != Rs2.W[x])) {
+ *   Mres[x][63:0] = Rs1.W[x] * Rs2.W[x];
+ *   if (`.u` form) {
+ *     Round[x][33:0] = Mres[x][63:30] + 1;
+ *     Rd.W[x] = Round[x][32:1];
+ *   } else {
+ *     Rd.W[x] = Mres[x][62:31];
+ *   }
+ * } else {
+ *   Rd.W[x] = 0x7fffffff;
+ *   OV = 1;
+ * }
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KWMMUL_U(long a, long b)
+{
+    register long result;
+    __ASM volatile("kwmmul.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.70.2. KWMMUL.u ===== */
+
+/* ===== Inline Function Start for 3.71. MADDR32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
+ * \brief MADDR32 (Multiply and Add to 32-Bit Word)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * MADDR32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the 32-bit contents of two registers and add the lower 32-bit multiplication result
+ * to the 32-bit content of a destination register. Write the final result back to the destination register.
+ *
+ * **Description**:\n
+ * This instruction multiplies the lower 32-bit content of Rs1 with that of Rs2. It adds the
+ * lower 32-bit multiplication result to the lower 32-bit content of Rd and writes the final result (RV32)
+ * or sign-extended result (RV64) back to Rd. The contents of Rs1 and Rs2 can be either signed or
+ * unsigned integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * RV32:
+ * Mresult = Rs1 * Rs2;
+ * Rd = Rd + Mresult.W[0];
+ * RV64:
+ * Mresult = Rs1.W[0] * Rs2.W[0];
+ * tres[31:0] = Rd.W[0] + Mresult.W[0];
+ * Rd = SE64(tres[31:0]);
+ * ~~~
+ *
+ * \param [in]  t    unsigned long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_MADDR32(unsigned long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("maddr32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.71. MADDR32 ===== */
+
+/* ===== Inline Function Start for 3.72. MAXW ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION
+ * \brief MAXW (32-bit Signed Word Maximum)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * MAXW Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Get the larger value from the 32-bit contents of two general registers.
+ *
+ * **Description**:\n
+ * This instruction compares two signed 32-bit integers stored in Rs1 and Rs2, picks the
+ * larger value as the result, and writes the result to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if (Rs1.W[0] >= Rs2.W[0]) {
+ *   Rd = SE(Rs1.W[0]);
+ * } else {
+ *   Rd = SE(Rs2.W[0]);
+ * }
+ * ~~~
+ *
+ * \param [in]  a    int type of value stored in a
+ * \param [in]  b    int type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_MAXW(int a, int b)
+{
+    register long result;
+    __ASM volatile("maxw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.72. MAXW ===== */
+
+/* ===== Inline Function Start for 3.73. MINW ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION
+ * \brief MINW (32-bit Signed Word Minimum)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * MINW Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Get the smaller value from the 32-bit contents of two general registers.
+ *
+ * **Description**:\n
+ * This instruction compares two signed 32-bit integers stored in Rs1 and Rs2, picks the
+ * smaller value as the result, and writes the result to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if (Rs1.W[0] >= Rs2.W[0]) { Rd = SE(Rs2.W[0]); } else { Rd = SE(Rs1.W[0]); }
+ * ~~~
+ *
+ * \param [in]  a    int type of value stored in a
+ * \param [in]  b    int type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_MINW(int a, int b)
+{
+    register long result;
+    __ASM volatile("minw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.73. MINW ===== */
+
+/* ===== Inline Function Start for 3.74. MSUBR32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
+ * \brief MSUBR32 (Multiply and Subtract from 32-Bit Word)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * MSUBR32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the 32-bit contents of two registers and subtract the lower 32-bit multiplication
+ * result from the 32-bit content of a destination register. Write the final result back to the destination
+ * register.
+ *
+ * **Description**:\n
+ * This instruction multiplies the lower 32-bit content of Rs1 with that of Rs2, subtracts
+ * the lower 32-bit multiplication result from the lower 32-bit content of Rd, then writes the final
+ * result (RV32) or sign-extended result (RV64) back to Rd. The contents of Rs1 and Rs2 can be either
+ * signed or unsigned integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * RV32:
+ * Mresult = Rs1 * Rs2;
+ * Rd = Rd - Mresult.W[0];
+ * RV64:
+ * Mresult = Rs1.W[0] * Rs2.W[0];
+ * tres[31:0] = Rd.W[0] - Mresult.W[0];
+ * Rd = SE64(tres[31:0]);
+ * ~~~
+ *
+ * \param [in]  t    unsigned long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_MSUBR32(unsigned long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("msubr32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.74. MSUBR32 ===== */
+
+/* ===== Inline Function Start for 3.75. MULR64 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION
+ * \brief MULR64 (Multiply Word Unsigned to 64-bit Data)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * MULR64 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the 32-bit unsigned integer contents of two registers and write the 64-bit result.
+ *
+ * **RV32 Description**:\n
+ * This instruction multiplies the 32-bit content of Rs1 with that of Rs2 and writes the 64-bit
+ * multiplication result to an even/odd pair of registers containing Rd. Rd(4,1) index d determines the
+ * even/odd pair group of the two registers. Specifically, the register pair includes register 2d and
+ * 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
+ * of the pair contains the low 32-bit of the result.
+ * The lower 32-bit contents of Rs1 and Rs2 are treated as unsigned integers.
+ *
+ * **RV64 Description**:\n
+ * This instruction multiplies the lower 32-bit content of Rs1 with that of Rs2 and writes the 64-bit
+ * multiplication result to Rd.
+ * The lower 32-bit contents of Rs1 and Rs2 are treated as unsigned integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * RV32:
+ * Mresult = CONCAT(1`b0,Rs1) u* CONCAT(1`b0,Rs2);
+ * R[Rd(4,1).1(0)][31:0] = Mresult[63:32];
+ * R[Rd(4,1).0(0)][31:0] = Mresult[31:0];
+ * RV64:
+ * Rd = Mresult[63:0];
+ * Mresult = CONCAT(1`b0,Rs1.W[0]) u* CONCAT(1`b0,Rs2.W[0]);
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long long type
+ */
+__STATIC_FORCEINLINE unsigned long long __RV_MULR64(unsigned long a, unsigned long b)
+{
+    register unsigned long long result;
+    __ASM volatile("mulr64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.75. MULR64 ===== */
+
+/* ===== Inline Function Start for 3.76. MULSR64 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION
+ * \brief MULSR64 (Multiply Word Signed to 64-bit Data)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * MULSR64 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the 32-bit signed integer contents of two registers and write the 64-bit result.
+ *
+ * **RV32 Description**:\n
+ * This instruction multiplies the lower 32-bit content of Rs1 with the lower 32-bit content of Rs2 and
+ * writes the 64-bit multiplication result to an even/odd pair of registers containing Rd. Rd(4,1) index d
+ * determines the even/odd pair group of the two registers. Specifically, the register pair includes
+ * register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
+ * of the pair contains the low 32-bit of the result.
+ * The lower 32-bit contents of Rs1 and Rs2 are treated as signed integers.
+ *
+ * **RV64 Description**:\n
+ * This instruction multiplies the lower 32-bit content of Rs1 with the lower 32-bit content of Rs2 and
+ * writes the 64-bit multiplication result to Rd.
+ * The lower 32-bit contents of Rs1 and Rs2 are treated as signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * RV32:
+ * Mresult = Ra s* Rb;
+ * R[Rd(4,1).1(0)][31:0] = Mresult[63:32];
+ * R[Rd(4,1).0(0)][31:0] = Mresult[31:0];
+ * RV64:
+ * Mresult = Ra.W[0] s* Rb.W[0];
+ * Rd = Mresult[63:0];
+ * ~~~
+ *
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    long type of value stored in b
+ * \return value stored in long long type
+ */
+__STATIC_FORCEINLINE long long __RV_MULSR64(long a, long b)
+{
+    register long long result;
+    __ASM volatile("mulsr64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.76. MULSR64 ===== */
+
+/* ===== Inline Function Start for 3.77. PBSAD ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC
+ * \brief PBSAD (Parallel Byte Sum of Absolute Difference)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * PBSAD Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Calculate the sum of absolute difference of unsigned 8-bit data elements.
+ *
+ * **Description**:\n
+ * This instruction subtracts the un-signed 8-bit elements of Rs2 from those of Rs1. Then
+ * it adds the absolute value of each difference together and writes the result to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * absdiff[x] = ABS(Rs1.B[x] - Rs2.B[x]);
+ * Rd = SUM(absdiff[x]);
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_PBSAD(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("pbsad %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.77. PBSAD ===== */
+
+/* ===== Inline Function Start for 3.78. PBSADA ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC
+ * \brief PBSADA (Parallel Byte Sum of Absolute Difference Accum)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * PBSADA Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Calculate the sum of absolute difference of four unsigned 8-bit data elements and
+ * accumulate it into a register.
+ *
+ * **Description**:\n
+ * This instruction subtracts the un-signed 8-bit elements of Rs2 from those of Rs1. It
+ * then adds the absolute value of each difference together along with the content of Rd and writes the
+ * accumulated result back to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * absdiff[x] = ABS(Rs1.B[x] - Rs2.B[x]);
+ * Rd = Rd + SUM(absdiff[x]);
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  t    unsigned long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_PBSADA(unsigned long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("pbsada %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.78. PBSADA ===== */
+
+/* ===== Inline Function Start for 3.79.1. PKBB16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_PACK
+ * \brief PKBB16 (Pack Two 16-bit Data from Both Bottom Half)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * PKBB16 Rd, Rs1, Rs2
+ * PKBT16 Rd, Rs1, Rs2
+ * PKTT16 Rd, Rs1, Rs2
+ * PKTB16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Pack 16-bit data from 32-bit chunks in two registers.
+ * * PKBB16: bottom.bottom
+ * * PKBT16 bottom.top
+ * * PKTT16 top.top
+ * * PKTB16 top.bottom
+ *
+ * **Description**:\n
+ * (PKBB16) moves Rs1.W[x][15:0] to Rd.W[x][31:16] and moves Rs2.W[x] [15:0] to
+ * Rd.W[x] [15:0].
+ * (PKBT16) moves Rs1.W[x] [15:0] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0].
+ * (PKTT16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0].
+ * (PKTB16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [15:0] to Rd.W[x] [15:0].
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][15:0]); // PKBB16
+ * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][31:16]); // PKBT16
+ * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][15:0]); // PKTB16
+ * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][31:16]); // PKTT16
+ * for RV32: x=0,
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_PKBB16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("pkbb16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.79.1. PKBB16 ===== */
+
+/* ===== Inline Function Start for 3.79.2. PKBT16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_PACK
+ * \brief PKBT16 (Pack Two 16-bit Data from Bottom and Top Half)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * PKBB16 Rd, Rs1, Rs2
+ * PKBT16 Rd, Rs1, Rs2
+ * PKTT16 Rd, Rs1, Rs2
+ * PKTB16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Pack 16-bit data from 32-bit chunks in two registers.
+ * * PKBB16: bottom.bottom
+ * * PKBT16 bottom.top
+ * * PKTT16 top.top
+ * * PKTB16 top.bottom
+ *
+ * **Description**:\n
+ * (PKBB16) moves Rs1.W[x][15:0] to Rd.W[x][31:16] and moves Rs2.W[x] [15:0] to
+ * Rd.W[x] [15:0].
+ * (PKBT16) moves Rs1.W[x] [15:0] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0].
+ * (PKTT16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0].
+ * (PKTB16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [15:0] to Rd.W[x] [15:0].
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][15:0]); // PKBB16
+ * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][31:16]); // PKBT16
+ * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][15:0]); // PKTB16
+ * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][31:16]); // PKTT16
+ * for RV32: x=0,
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_PKBT16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("pkbt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.79.2. PKBT16 ===== */
+
+/* ===== Inline Function Start for 3.79.3. PKTT16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_PACK
+ * \brief PKTT16 (Pack Two 16-bit Data from Both Top Half)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * PKBB16 Rd, Rs1, Rs2
+ * PKBT16 Rd, Rs1, Rs2
+ * PKTT16 Rd, Rs1, Rs2
+ * PKTB16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Pack 16-bit data from 32-bit chunks in two registers.
+ * * PKBB16: bottom.bottom
+ * * PKBT16 bottom.top
+ * * PKTT16 top.top
+ * * PKTB16 top.bottom
+ *
+ * **Description**:\n
+ * (PKBB16) moves Rs1.W[x][15:0] to Rd.W[x][31:16] and moves Rs2.W[x] [15:0] to
+ * Rd.W[x] [15:0].
+ * (PKBT16) moves Rs1.W[x] [15:0] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0].
+ * (PKTT16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0].
+ * (PKTB16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [15:0] to Rd.W[x] [15:0].
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][15:0]); // PKBB16
+ * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][31:16]); // PKBT16
+ * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][15:0]); // PKTB16
+ * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][31:16]); // PKTT16
+ * for RV32: x=0,
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_PKTT16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("pktt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.79.3. PKTT16 ===== */
+
+/* ===== Inline Function Start for 3.79.4. PKTB16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_PACK
+ * \brief PKTB16 (Pack Two 16-bit Data from Top and Bottom Half)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * PKBB16 Rd, Rs1, Rs2
+ * PKBT16 Rd, Rs1, Rs2
+ * PKTT16 Rd, Rs1, Rs2
+ * PKTB16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Pack 16-bit data from 32-bit chunks in two registers.
+ * * PKBB16: bottom.bottom
+ * * PKBT16 bottom.top
+ * * PKTT16 top.top
+ * * PKTB16 top.bottom
+ *
+ * **Description**:\n
+ * (PKBB16) moves Rs1.W[x][15:0] to Rd.W[x][31:16] and moves Rs2.W[x] [15:0] to
+ * Rd.W[x] [15:0].
+ * (PKBT16) moves Rs1.W[x] [15:0] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0].
+ * (PKTT16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0].
+ * (PKTB16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [15:0] to Rd.W[x] [15:0].
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][15:0]); // PKBB16
+ * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][31:16]); // PKBT16
+ * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][15:0]); // PKTB16
+ * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][31:16]); // PKTT16
+ * for RV32: x=0,
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_PKTB16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("pktb16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.79.4. PKTB16 ===== */
+
+/* ===== Inline Function Start for 3.80. RADD8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB
+ * \brief RADD8 (SIMD 8-bit Signed Halving Addition)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * RADD8 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit signed integer element additions simultaneously. The element results are halved
+ * to avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction adds the 8-bit signed integer elements in Rs1 with the 8-bit signed
+ * integer elements in Rs2. The results are first arithmetically right-shifted by 1 bit and then written to
+ * Rd.
+ *
+ * **Examples**:\n
+ * ~~~
+ * * Rs1 = 0x7F, Rs2 = 0x7F, Rd = 0x7F
+ * * Rs1 = 0x80, Rs2 = 0x80, Rd = 0x80
+ * * Rs1 = 0x40, Rs2 = 0x80, Rd = 0xE0
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.B[x] = (Rs1.B[x] + Rs2.B[x]) s>> 1; for RV32: x=3...0, for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_RADD8(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("radd8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.80. RADD8 ===== */
+
+/* ===== Inline Function Start for 3.81. RADD16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief RADD16 (SIMD 16-bit Signed Halving Addition)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * RADD16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit signed integer element additions simultaneously. The results are halved to avoid
+ * overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction adds the 16-bit signed integer elements in Rs1 with the 16-bit signed
+ * integer elements in Rs2. The results are first arithmetically right-shifted by 1 bit and then written to
+ * Rd.
+ *
+ * **Examples**:\n
+ * ~~~
+ * * Rs1 = 0x7FFF, Rs2 = 0x7FFF, Rd = 0x7FFF
+ * * Rs1 = 0x8000, Rs2 = 0x8000, Rd = 0x8000
+ * * Rs1 = 0x4000, Rs2 = 0x8000, Rd = 0xE000
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.H[x] = (Rs1.H[x] + Rs2.H[x]) s>> 1; for RV32: x=1...0, for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_RADD16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("radd16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.81. RADD16 ===== */
+
+/* ===== Inline Function Start for 3.82. RADD64 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB
+ * \brief RADD64 (64-bit Signed Halving Addition)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * RADD64 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Add two 64-bit signed integers. The result is halved to avoid overflow or saturation.
+ *
+ * **RV32 Description**:\n
+ * This instruction adds the 64-bit signed integer of an even/odd pair of registers
+ * specified by Rs1(4,1) with the 64-bit signed integer of an even/odd pair of registers specified by
+ * Rs2(4,1). The 64-bit addition result is first arithmetically right-shifted by 1 bit and then written to an
+ * even/odd pair of registers specified by Rd(4,1).
+ * Rx(4,1), i.e., value d, determines the even/odd pair group of two registers. Specifically, the register
+ * pair includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
+ * of the pair contains the low 32-bit of the result.
+ *
+ * **RV64 Description**:\n
+ * This instruction adds the 64-bit signed integer in Rs1 with the 64-bit signed
+ * integer in Rs2. The 64-bit addition result is first arithmetically right-shifted by 1 bit and then
+ * written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * RV32:
+ * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
+ * a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1);
+ * b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1);
+ * R[t_H].R[t_L] = (R[a_H].R[a_L] + R[b_H].R[b_L]) s>> 1;
+ * RV64:
+ * Rd = (Rs1 + Rs2) s>> 1;
+ * ~~~
+ *
+ * \param [in]  a    long long type of value stored in a
+ * \param [in]  b    long long type of value stored in b
+ * \return value stored in long long type
+ */
+__STATIC_FORCEINLINE long long __RV_RADD64(long long a, long long b)
+{
+    register long long result;
+    __ASM volatile("radd64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.82. RADD64 ===== */
+
+/* ===== Inline Function Start for 3.83. RADDW ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION
+ * \brief RADDW (32-bit Signed Halving Addition)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * RADDW Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Add 32-bit signed integers and the results are halved to avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction adds the first 32-bit signed integer in Rs1 with the first 32-bit signed
+ * integer in Rs2. The result is first arithmetically right-shifted by 1 bit and then sign-extended and
+ * written to Rd.
+ *
+ * **Examples**:\n
+ * ~~~
+ * * Rs1 = 0x7FFFFFFF, Rs2 = 0x7FFFFFFF, Rd = 0x7FFFFFFF
+ * * Rs1 = 0x80000000, Rs2 = 0x80000000, Rd = 0x80000000
+ * * Rs1 = 0x40000000, Rs2 = 0x80000000, Rd = 0xE0000000
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * RV32:
+ * Rd[31:0] = (Rs1[31:0] + Rs2[31:0]) s>> 1;
+ * RV64:
+ * resw[31:0] = (Rs1[31:0] + Rs2[31:0]) s>> 1;
+ * Rd[63:0] = SE(resw[31:0]);
+ * ~~~
+ *
+ * \param [in]  a    int type of value stored in a
+ * \param [in]  b    int type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_RADDW(int a, int b)
+{
+    register long result;
+    __ASM volatile("raddw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.83. RADDW ===== */
+
+/* ===== Inline Function Start for 3.84. RCRAS16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief RCRAS16 (SIMD 16-bit Signed Halving Cross Addition & Subtraction)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * RCRAS16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit signed integer element addition and 16-bit signed integer element subtraction in
+ * a 32-bit chunk simultaneously. Operands are from crossed positions in 32-bit chunks. The results
+ * are halved to avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction adds the 16-bit signed integer element in [31:16] of 32-bit chunks in
+ * Rs1 with the 16-bit signed integer element in [15:0] of 32-bit chunks in Rs2, and subtracts the 16-bit
+ * signed integer element in [31:16] of 32-bit chunks in Rs2 from the 16-bit signed integer element in
+ * [15:0] of 32-bit chunks in Rs1. The element results are first arithmetically right-shifted by 1 bit and
+ * then written to [31:16] of 32-bit chunks in Rd and [15:0] of 32-bit chunks in Rd.
+ *
+ * **Examples**:\n
+ * ~~~
+ * Please see `RADD16` and `RSUB16` instructions.
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x][31:16] = (Rs1.W[x][31:16] + Rs2.W[x][15:0]) s>> 1;
+ * Rd.W[x][15:0] = (Rs1.W[x][15:0] - Rs2.W[x][31:16]) s>> 1;
+ * for RV32, x=0
+ * for RV64, x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_RCRAS16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("rcras16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.84. RCRAS16 ===== */
+
+/* ===== Inline Function Start for 3.85. RCRSA16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief RCRSA16 (SIMD 16-bit Signed Halving Cross Subtraction & Addition)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * RCRSA16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit signed integer element subtraction and 16-bit signed integer element addition in
+ * a 32-bit chunk simultaneously. Operands are from crossed positions in 32-bit chunks. The results
+ * are halved to avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 16-bit signed integer element in [15:0] of 32-bit chunks
+ * in Rs2 from the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs1, and adds the 16-bit
+ * signed element integer in [15:0] of 32-bit chunks in Rs1 with the 16-bit signed integer element in
+ * [31:16] of 32-bit chunks in Rs2. The two results are first arithmetically right-shifted by 1 bit and
+ * then written to [31:16] of 32-bit chunks in Rd and [15:0] of 32-bit chunks in Rd.
+ *
+ * **Examples**:\n
+ * ~~~
+ * Please see `RADD16` and `RSUB16` instructions.
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x][31:16] = (Rs1.W[x][31:16] - Rs2.W[x][15:0]) s>> 1;
+ * Rd.W[x][15:0] = (Rs1.W[x][15:0] + Rs2.W[x][31:16]) s>> 1;
+ * for RV32, x=0
+ * for RV64, x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_RCRSA16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("rcrsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.85. RCRSA16 ===== */
+
+/* ===== Inline Function Start for 3.86. RDOV ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_OV_FLAG_SC
+ * \brief RDOV (Read OV flag)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * RDOV Rd  # pseudo mnemonic
+ * ~~~
+ *
+ * **Purpose**:\n
+ * This pseudo instruction is an alias to `CSRR Rd, ucode` instruction which maps to the real
+ * instruction of `CSRRS Rd, ucode, x0`.
+ *
+ *
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_RDOV(void)
+{
+    register unsigned long result;
+    __ASM volatile("rdov %0" : "=r"(result));
+    return result;
+}
+/* ===== Inline Function End for 3.86. RDOV ===== */
+
+/* ===== Inline Function Start for 3.87. RSTAS16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief RSTAS16 (SIMD 16-bit Signed Halving Straight Addition & Subtraction)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * RSTAS16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit signed integer element addition and 16-bit signed integer element subtraction in
+ * a 32-bit chunk simultaneously. Operands are from corresponding positions in 32-bit chunks. The
+ * results are halved to avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction adds the 16-bit signed integer element in [31:16] of 32-bit chunks in
+ * Rs1 with the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs2, and subtracts the 16-bit
+ * signed integer element in [15:0] of 32-bit chunks in Rs2 from the 16-bit signed integer element in
+ * [15:0] of 32-bit chunks in Rs1. The element results are first arithmetically right-shifted by 1 bit and
+ * then written to [31:16] of 32-bit chunks in Rd and [15:0] of 32-bit chunks in Rd.
+ *
+ * **Examples**:\n
+ * ~~~
+ * Please see `RADD16` and `RSUB16` instructions.
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x][31:16] = (Rs1.W[x][31:16] + Rs2.W[x][31:16]) s>> 1;
+ * Rd.W[x][15:0] = (Rs1.W[x][15:0] - Rs2.W[x][15:0]) s>> 1;
+ * for RV32, x=0
+ * for RV64, x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_RSTAS16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("rstas16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.87. RSTAS16 ===== */
+
+/* ===== Inline Function Start for 3.88. RSTSA16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief RSTSA16 (SIMD 16-bit Signed Halving Straight Subtraction & Addition)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * RSTSA16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit signed integer element subtraction and 16-bit signed integer element addition in
+ * a 32-bit chunk simultaneously. Operands are from corresponding positions in 32-bit chunks. The
+ * results are halved to avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 16-bit signed integer element in [31:16] of 32-bit chunks
+ * in Rs2 from the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs1, and adds the 16-bit
+ * signed element integer in [15:0] of 32-bit chunks in Rs1 with the 16-bit signed integer element in
+ * [15:0] of 32-bit chunks in Rs2. The two results are first arithmetically right-shifted by 1 bit and then
+ * written to [31:16] of 32-bit chunks in Rd and [15:0] of 32-bit chunks in Rd.
+ *
+ * **Examples**:\n
+ * ~~~
+ * Please see `RADD16` and `RSUB16` instructions.
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x][31:16] = (Rs1.W[x][31:16] - Rs2.W[x][31:16]) s>> 1;
+ * Rd.W[x][15:0] = (Rs1.W[x][15:0] + Rs2.W[x][15:0]) s>> 1;
+ * for RV32, x=0
+ * for RV64, x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_RSTSA16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("rstsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.88. RSTSA16 ===== */
+
+/* ===== Inline Function Start for 3.89. RSUB8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB
+ * \brief RSUB8 (SIMD 8-bit Signed Halving Subtraction)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * RSUB8 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit signed integer element subtractions simultaneously. The results are halved to
+ * avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 8-bit signed integer elements in Rs2 from the 8-bit
+ * signed integer elements in Rs1. The results are first arithmetically right-shifted by 1 bit and then
+ * written to Rd.
+ *
+ * **Examples**:\n
+ * ~~~
+ * * Rs1 = 0x7F, Rs2 = 0x80, Rd = 0x7F
+ * * Rs1 = 0x80, Rs2 = 0x7F, Rd = 0x80
+ * * Rs1= 0x80, Rs2 = 0x40, Rd = 0xA0
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.B[x] = (Rs1.B[x] - Rs2.B[x]) s>> 1;
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_RSUB8(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("rsub8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.89. RSUB8 ===== */
+
+/* ===== Inline Function Start for 3.90. RSUB16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief RSUB16 (SIMD 16-bit Signed Halving Subtraction)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * RSUB16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit signed integer element subtractions simultaneously. The results are halved to
+ * avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 16-bit signed integer elements in Rs2 from the 16-bit
+ * signed integer elements in Rs1. The results are first arithmetically right-shifted by 1 bit and then
+ * written to Rd.
+ *
+ * **Examples**:\n
+ * ~~~
+ * * Ra = 0x7FFF, Rb = 0x8000, Rt = 0x7FFF
+ * * Ra = 0x8000, Rb = 0x7FFF, Rt = 0x8000
+ * * Ra = 0x8000, Rb = 0x4000, Rt = 0xA000
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.H[x] = (Rs1.H[x] - Rs2.H[x]) s>> 1;
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_RSUB16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("rsub16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.90. RSUB16 ===== */
+
+/* ===== Inline Function Start for 3.91. RSUB64 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB
+ * \brief RSUB64 (64-bit Signed Halving Subtraction)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * RSUB64 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Perform a 64-bit signed integer subtraction. The result is halved to avoid overflow or
+ * saturation.
+ *
+ * **RV32 Description**:\n
+ * This instruction subtracts the 64-bit signed integer of an even/odd pair of
+ * registers specified by Rb(4,1) from the 64-bit signed integer of an even/odd pair of registers
+ * specified by Ra(4,1). The subtraction result is first arithmetically right-shifted by 1 bit and then
+ * written to an even/odd pair of registers specified by Rt(4,1).
+ * Rx(4,1), i.e., value d, determines the even/odd pair group of two registers. Specifically, the register
+ * pair includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
+ * of the pair contains the low 32-bit of the result.
+ *
+ * **RV64 Description**:\n
+ * This instruction subtracts the 64-bit signed integer in Rs2 from the 64-bit signed
+ * integer in Rs1. The 64-bit subtraction result is first arithmetically right-shifted by 1 bit and then
+ * written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * RV32:
+ * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
+ * a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1);
+ * b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1);
+ * R[t_H].R[t_L] = (R[a_H].R[a_L] - R[b_H].R[b_L]) s>> 1;
+ * RV64:
+ * Rd = (Rs1 - Rs2) s>> 1;
+ * ~~~
+ *
+ * \param [in]  a    long long type of value stored in a
+ * \param [in]  b    long long type of value stored in b
+ * \return value stored in long long type
+ */
+__STATIC_FORCEINLINE long long __RV_RSUB64(long long a, long long b)
+{
+    register long long result;
+    __ASM volatile("rsub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.91. RSUB64 ===== */
+
+/* ===== Inline Function Start for 3.92. RSUBW ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION
+ * \brief RSUBW (32-bit Signed Halving Subtraction)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * RSUBW Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Subtract 32-bit signed integers and the result is halved to avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction subtracts the first 32-bit signed integer in Rs2 from the first 32-bit
+ * signed integer in Rs1. The result is first arithmetically right-shifted by 1 bit and then sign-extended
+ * and written to Rd.
+ *
+ * **Examples**:\n
+ * ~~~
+ * * Rs1 = 0x7FFFFFFF, Rs2 = 0x80000000, Rd = 0x7FFFFFFF
+ * * Rs1 = 0x80000000, Rs2 = 0x7FFFFFFF, Rd = 0x80000000
+ * * Rs1 = 0x80000000, Rs2 = 0x40000000, Rd = 0xA0000000
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * RV32:
+ * Rd[31:0] = (Rs1[31:0] - Rs2[31:0]) s>> 1;
+ * RV64:
+ * resw[31:0] = (Rs1[31:0] - Rs2[31:0]) s>> 1;
+ * Rd[63:0] = SE(resw[31:0]);
+ * ~~~
+ *
+ * \param [in]  a    int type of value stored in a
+ * \param [in]  b    int type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_RSUBW(int a, int b)
+{
+    register long result;
+    __ASM volatile("rsubw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.92. RSUBW ===== */
+
+/* ===== Inline Function Start for 3.93. SCLIP8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC
+ * \brief SCLIP8 (SIMD 8-bit Signed Clip Value)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SCLIP8 Rd, Rs1, imm3u[2:0]
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Limit the 8-bit signed integer elements of a register into a signed range simultaneously.
+ *
+ * **Description**:\n
+ * This instruction limits the 8-bit signed integer elements stored in Rs1 into a signed
+ * integer range between 2^imm3u-1 and -2^imm3u, and writes the limited results to Rd. For example, if
+ * imm3u is 3, the 8-bit input values should be saturated between 7 and -8. If saturation is performed,
+ * set OV bit to 1.
+ *
+ * **Operations**:\n
+ * ~~~
+ * src = Rs1.B[x];
+ * if (src > (2^imm3u)-1) {
+ *   src = (2^imm3u)-1;
+ *   OV = 1;
+ * } else if (src < -2^imm3u) {
+ *   src = -2^imm3u;
+ *   OV = 1;
+ * }
+ * Rd.B[x] = src
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+#define __RV_SCLIP8(a, b)    \
+    ({    \
+        register unsigned long result;    \
+        register unsigned long __a = (unsigned long)(a);    \
+        __ASM volatile("sclip8 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
+        result;    \
+    })
+/* ===== Inline Function End for 3.93. SCLIP8 ===== */
+
+/* ===== Inline Function Start for 3.94. SCLIP16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC
+ * \brief SCLIP16 (SIMD 16-bit Signed Clip Value)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SCLIP16 Rd, Rs1, imm4u[3:0]
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Limit the 16-bit signed integer elements of a register into a signed range simultaneously.
+ *
+ * **Description**:\n
+ * This instruction limits the 16-bit signed integer elements stored in Rs1 into a signed
+ * integer range between 2imm4u-1 and -2imm4u, and writes the limited results to Rd. For example, if
+ * imm4u is 3, the 16-bit input values should be saturated between 7 and -8. If saturation is performed,
+ * set OV bit to 1.
+ *
+ * **Operations**:\n
+ * ~~~
+ * src = Rs1.H[x];
+ * if (src > (2^imm4u)-1) {
+ *   src = (2^imm4u)-1;
+ *   OV = 1;
+ * } else if (src < -2^imm4u) {
+ *   src = -2^imm4u;
+ *   OV = 1;
+ * }
+ * Rd.H[x] = src
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+#define __RV_SCLIP16(a, b)    \
+    ({    \
+        register unsigned long result;    \
+        register unsigned long __a = (unsigned long)(a);    \
+        __ASM volatile("sclip16 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
+        result;    \
+    })
+/* ===== Inline Function End for 3.94. SCLIP16 ===== */
+
+/* ===== Inline Function Start for 3.95. SCLIP32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC
+ * \brief SCLIP32 (SIMD 32-bit Signed Clip Value)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SCLIP32 Rd, Rs1, imm5u[4:0]
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Limit the 32-bit signed integer elements of a register into a signed range simultaneously.
+ *
+ * **Description**:\n
+ * This instruction limits the 32-bit signed integer elements stored in Rs1 into a signed
+ * integer range between 2imm5u-1 and -2imm5u, and writes the limited results to Rd. For example, if
+ * imm5u is 3, the 32-bit input values should be saturated between 7 and -8. If saturation is performed,
+ * set OV bit to 1.
+ *
+ * **Operations**:\n
+ * ~~~
+ * src = Rs1.W[x];
+ * if (src > (2^imm5u)-1) {
+ *   src = (2^imm5u)-1;
+ *   OV = 1;
+ * } else if (src < -2^imm5u) {
+ *   src = -2^imm5u;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = src
+ * for RV32: x=0,
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in long type
+ */
+#define __RV_SCLIP32(a, b)    \
+    ({    \
+        register long result;    \
+        register long __a = (long)(a);    \
+        __ASM volatile("sclip32 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
+        result;    \
+    })
+/* ===== Inline Function End for 3.95. SCLIP32 ===== */
+
+/* ===== Inline Function Start for 3.96. SCMPLE8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_CMP
+ * \brief SCMPLE8 (SIMD 8-bit Signed Compare Less Than & Equal)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SCMPLE8 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit signed integer elements less than & equal comparisons simultaneously.
+ *
+ * **Description**:\n
+ * This instruction compares the 8-bit signed integer elements in Rs1 with the 8-bit
+ * signed integer elements in Rs2 to see if the one in Rs1 is less than or equal to the one in Rs2. If it is
+ * true, the result is 0xFF; otherwise, the result is 0x0. The element comparison results are written to
+ * Rd
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.B[x] = (Rs1.B[x] {le} Rs2.B[x])? 0xff : 0x0;
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SCMPLE8(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("scmple8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.96. SCMPLE8 ===== */
+
+/* ===== Inline Function Start for 3.97. SCMPLE16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_CMP
+ * \brief SCMPLE16 (SIMD 16-bit Signed Compare Less Than & Equal)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SCMPLE16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit signed integer elements less than & equal comparisons simultaneously.
+ *
+ * **Description**:\n
+ * This instruction compares the 16-bit signed integer elements in Rs1 with the 16-bit
+ * signed integer elements in Rs2 to see if the one in Rs1 is less than or equal to the one in Rs2. If it is
+ * true, the result is 0xFFFF; otherwise, the result is 0x0. The element comparison results are written
+ * to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.H[x] = (Rs1.H[x] {le} Rs2.H[x])? 0xffff : 0x0;
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SCMPLE16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("scmple16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.97. SCMPLE16 ===== */
+
+/* ===== Inline Function Start for 3.98. SCMPLT8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_CMP
+ * \brief SCMPLT8 (SIMD 8-bit Signed Compare Less Than)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SCMPLT8 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit signed integer elements less than comparisons simultaneously.
+ *
+ * **Description**:\n
+ * This instruction compares the 8-bit signed integer elements in Rs1 with the 8-bit
+ * signed integer elements in Rs2 to see if the one in Rs1 is less than the one in Rs2. If it is true, the
+ * result is 0xFF; otherwise, the result is 0x0. The element comparison results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.B[x] = (Rs1.B[x] < Rs2.B[x])? 0xff : 0x0;
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SCMPLT8(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("scmplt8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.98. SCMPLT8 ===== */
+
+/* ===== Inline Function Start for 3.99. SCMPLT16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_CMP
+ * \brief SCMPLT16 (SIMD 16-bit Signed Compare Less Than)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SCMPLT16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit signed integer elements less than comparisons simultaneously.
+ *
+ * **Description**:\n
+ * This instruction compares the 16-bit signed integer elements in Rs1 with the two 16-
+ * bit signed integer elements in Rs2 to see if the one in Rs1 is less than the one in Rs2. If it is true, the
+ * result is 0xFFFF; otherwise, the result is 0x0. The element comparison results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.H[x] = (Rs1.H[x] < Rs2.H[x])? 0xffff : 0x0;
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SCMPLT16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("scmplt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.99. SCMPLT16 ===== */
+
+/* ===== Inline Function Start for 3.100. SLL8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
+ * \brief SLL8 (SIMD 8-bit Shift Left Logical)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SLL8 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit elements logical left shift operations simultaneously. The shift amount is a
+ * variable from a GPR.
+ *
+ * **Description**:\n
+ * The 8-bit elements in Rs1 are left-shifted logically. And the results are written to Rd.
+ * The shifted out bits are filled with zero and the shift amount is specified by the low-order 3-bits of
+ * the value in the Rs2 register.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = Rs2[2:0];
+ * Rd.B[x] = Rs1.B[x] << sa;
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SLL8(unsigned long a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("sll8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.100. SLL8 ===== */
+
+/* ===== Inline Function Start for 3.101. SLLI8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
+ * \brief SLLI8 (SIMD 8-bit Shift Left Logical Immediate)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SLLI8 Rd, Rs1, imm3u
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit elements logical left shift operations simultaneously. The shift amount is an
+ * immediate value.
+ *
+ * **Description**:\n
+ * The 8-bit elements in Rs1 are left-shifted logically. And the results are written to Rd.
+ * The shifted out bits are filled with zero and the shift amount is specified by the imm3u constant.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = imm3u[2:0];
+ * Rd.B[x] = Rs1.B[x] << sa;
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+#define __RV_SLLI8(a, b)    \
+    ({    \
+        register unsigned long result;    \
+        register unsigned long __a = (unsigned long)(a);    \
+        __ASM volatile("slli8 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
+        result;    \
+    })
+/* ===== Inline Function End for 3.101. SLLI8 ===== */
+
+/* ===== Inline Function Start for 3.102. SLL16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
+ * \brief SLL16 (SIMD 16-bit Shift Left Logical)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SLL16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit elements logical left shift operations simultaneously. The shift amount is a
+ * variable from a GPR.
+ *
+ * **Description**:\n
+ * The 16-bit elements in Rs1 are left-shifted logically. And the results are written to Rd.
+ * The shifted out bits are filled with zero and the shift amount is specified by the low-order 4-bits of
+ * the value in the Rs2 register.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = Rs2[3:0];
+ * Rd.H[x] = Rs1.H[x] << sa;
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SLL16(unsigned long a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("sll16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.102. SLL16 ===== */
+
+/* ===== Inline Function Start for 3.103. SLLI16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
+ * \brief SLLI16 (SIMD 16-bit Shift Left Logical Immediate)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SLLI16 Rd, Rs1, imm4[3:0]
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit element logical left shift operations simultaneously. The shift amount is an
+ * immediate value.
+ *
+ * **Description**:\n
+ * The 16-bit elements in Rs1 are left-shifted logically. The shifted out bits are filled with
+ * zero and the shift amount is specified by the imm4[3:0] constant. And the results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = imm4[3:0];
+ * Rd.H[x] = Rs1.H[x] << sa;
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+#define __RV_SLLI16(a, b)    \
+    ({    \
+        register unsigned long result;    \
+        register unsigned long __a = (unsigned long)(a);    \
+        __ASM volatile("slli16 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
+        result;    \
+    })
+/* ===== Inline Function End for 3.103. SLLI16 ===== */
+
+/* ===== Inline Function Start for 3.104. SMAL ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB
+ * \brief SMAL (Signed Multiply Halfs & Add 64-bit)
+ * \details
+ * **Type**: Partial-SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMAL Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed bottom 16-bit content of the 32-bit elements of a register with the top
+ * 16-bit content of the same 32-bit elements of the same register, and add the results with a 64-bit
+ * value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back
+ * to another even/odd pair of registers (RV32) or a register (RV64).
+ *
+ * **RV32 Description**:\n
+ * This instruction multiplies the bottom 16-bit content of the lower 32-bit of Rs2 with the top 16-bit
+ * content of the lower 32-bit of Rs2 and adds the result with the 64-bit value of an even/odd pair of
+ * registers specified by Rs1(4,1). The 64-bit addition result is written back to an even/odd pair of
+ * registers specified by Rd(4,1). The 16-bit values of Rs2, and the 64-bit value of the Rs1(4,1) register-
+ * pair are treated as signed integers.
+ * Rx(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d`
+ * register of the pair contains the low 32-bit of the operand.
+ *
+ * **RV64 Description**:\n
+ * This instruction multiplies the bottom 16-bit content of the 32-bit elements of Rs2 with the top 16-bit
+ * content of the same 32-bit elements of Rs2 and adds the results with the 64-bit value of Rs1. The 64-
+ * bit addition result is written back to Rd. The 16-bit values of Rs2, and the 64-bit value of Rs1 are
+ * treated as signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * RV32:
+ * Mres[31:0] = Rs2.H[1] * Rs2.H[0];
+ * Idx0 = CONCAT(Rs1(4,1),1'b0); Idx1 = CONCAT(Rs1(4,1),1'b1); +
+ * Idx2 = CONCAT(Rd(4,1),1'b0); Idx3 = CONCAT(Rd(4,1),1'b1);
+ * R[Idx3].R[Idx2] = R[Idx1].R[Idx0] + SE64(Mres[31:0]);
+ * RV64:
+ * Mres[0][31:0] = Rs2.W[0].H[1] * Rs2.W[0].H[0];
+ * Mres[1][31:0] = Rs2.W[1].H[1] * Rs2.W[1].H[0];
+ * Rd = Rs1 + SE64(Mres[1][31:0]) + SE64(Mres[0][31:0]);
+ * ~~~
+ *
+ * \param [in]  a    long long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long long type
+ */
+__STATIC_FORCEINLINE long long __RV_SMAL(long long a, unsigned long b)
+{
+    register long long result;
+    __ASM volatile("smal %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.104. SMAL ===== */
+
+/* ===== Inline Function Start for 3.105.1. SMALBB ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB
+ * \brief SMALBB (Signed Multiply Bottom Halfs & Add 64-bit)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMALBB Rd, Rs1, Rs2
+ * SMALBT Rd, Rs1, Rs2
+ * SMALTT Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 16-bit content of the 32-bit elements of a register with the 16-bit
+ * content of the corresponding 32-bit elements of another register and add the results with a 64-bit
+ * value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back
+ * to the register-pair (RV32) or the register (RV64).
+ * * SMALBB: rt pair + bottom*bottom (all 32-bit elements)
+ * * SMALBT rt pair + bottom*top (all 32-bit elements)
+ * * SMALTT rt pair + top*top (all 32-bit elements)
+ *
+ * **RV32 Description**:\n
+ * For the `SMALBB` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit
+ * content of Rs2.
+ * For the `SMALBT` instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit
+ * content of Rs2.
+ * For the `SMALTT` instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content
+ * of Rs2.
+ * The multiplication result is added with the 64-bit value of an even/odd pair of registers specified by
+ * Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and
+ * Rs2, and the 64-bit value of the register-pair are treated as signed integers.
+ * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d`
+ * register of the pair contains the low 32-bit of the operand.
+ *
+ * **RV64 Description**:\n
+ * For the `SMALBB` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the bottom 16-bit content of the 32-bit elements of Rs2.
+ * For the `SMALBT` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the top 16-bit content of the 32-bit elements of Rs2.
+ * For the `SMALTT` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
+ * the top 16-bit content of the 32-bit elements of Rs2.
+ * The multiplication results are added with the 64-bit value of Rd. The 64-bit addition result is written
+ * back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed
+ * integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * RV32:
+ * Mres[31:0] = Rs1.H[0] * Rs2.H[0]; // SMALBB
+ * Mres[31:0] = Rs1.H[0] * Rs2.H[1]; // SMALBT
+ * Mres[31:0] = Rs1.H[1] * Rs2.H[1]; // SMALTT
+ * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1);
+ * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]);
+ * RV64:
+ * // SMALBB
+ * Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[0];
+ * Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[0];
+ * // SMALBT
+ * Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[1];
+ * Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[1];
+ * // SMALTT
+ * Mres[0][31:0] = Rs1.W[0].H[1] * Rs2.W[0].H[1];
+ * Mres[1][31:0] = Rs1.W[1].H[1] * Rs2.W[1].H[1];
+ * Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]);
+ * ~~~
+ *
+ * \param [in]  t    long long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long long type
+ */
+__STATIC_FORCEINLINE long long __RV_SMALBB(long long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("smalbb %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.105.1. SMALBB ===== */
+
+/* ===== Inline Function Start for 3.105.2. SMALBT ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB
+ * \brief SMALBT (Signed Multiply Bottom Half & Top Half & Add 64-bit)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMALBB Rd, Rs1, Rs2
+ * SMALBT Rd, Rs1, Rs2
+ * SMALTT Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 16-bit content of the 32-bit elements of a register with the 16-bit
+ * content of the corresponding 32-bit elements of another register and add the results with a 64-bit
+ * value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back
+ * to the register-pair (RV32) or the register (RV64).
+ * * SMALBB: rt pair + bottom*bottom (all 32-bit elements)
+ * * SMALBT rt pair + bottom*top (all 32-bit elements)
+ * * SMALTT rt pair + top*top (all 32-bit elements)
+ *
+ * **RV32 Description**:\n
+ * For the `SMALBB` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit
+ * content of Rs2.
+ * For the `SMALBT` instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit
+ * content of Rs2.
+ * For the `SMALTT` instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content
+ * of Rs2.
+ * The multiplication result is added with the 64-bit value of an even/odd pair of registers specified by
+ * Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and
+ * Rs2, and the 64-bit value of the register-pair are treated as signed integers.
+ * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d`
+ * register of the pair contains the low 32-bit of the operand.
+ *
+ * **RV64 Description**:\n
+ * For the `SMALBB` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the bottom 16-bit content of the 32-bit elements of Rs2.
+ * For the `SMALBT` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the top 16-bit content of the 32-bit elements of Rs2.
+ * For the `SMALTT` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
+ * the top 16-bit content of the 32-bit elements of Rs2.
+ * The multiplication results are added with the 64-bit value of Rd. The 64-bit addition result is written
+ * back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed
+ * integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * RV32:
+ * Mres[31:0] = Rs1.H[0] * Rs2.H[0]; // SMALBB
+ * Mres[31:0] = Rs1.H[0] * Rs2.H[1]; // SMALBT
+ * Mres[31:0] = Rs1.H[1] * Rs2.H[1]; // SMALTT
+ * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1);
+ * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]);
+ * RV64:
+ * // SMALBB
+ * Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[0];
+ * Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[0];
+ * // SMALBT
+ * Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[1];
+ * Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[1];
+ * // SMALTT
+ * Mres[0][31:0] = Rs1.W[0].H[1] * Rs2.W[0].H[1];
+ * Mres[1][31:0] = Rs1.W[1].H[1] * Rs2.W[1].H[1];
+ * Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]);
+ * ~~~
+ *
+ * \param [in]  t    long long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long long type
+ */
+__STATIC_FORCEINLINE long long __RV_SMALBT(long long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("smalbt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.105.2. SMALBT ===== */
+
+/* ===== Inline Function Start for 3.105.3. SMALTT ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB
+ * \brief SMALTT (Signed Multiply Top Halfs & Add 64-bit)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMALBB Rd, Rs1, Rs2
+ * SMALBT Rd, Rs1, Rs2
+ * SMALTT Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 16-bit content of the 32-bit elements of a register with the 16-bit
+ * content of the corresponding 32-bit elements of another register and add the results with a 64-bit
+ * value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back
+ * to the register-pair (RV32) or the register (RV64).
+ * * SMALBB: rt pair + bottom*bottom (all 32-bit elements)
+ * * SMALBT rt pair + bottom*top (all 32-bit elements)
+ * * SMALTT rt pair + top*top (all 32-bit elements)
+ *
+ * **RV32 Description**:\n
+ * For the `SMALBB` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit
+ * content of Rs2.
+ * For the `SMALBT` instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit
+ * content of Rs2.
+ * For the `SMALTT` instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content
+ * of Rs2.
+ * The multiplication result is added with the 64-bit value of an even/odd pair of registers specified by
+ * Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and
+ * Rs2, and the 64-bit value of the register-pair are treated as signed integers.
+ * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d`
+ * register of the pair contains the low 32-bit of the operand.
+ *
+ * **RV64 Description**:\n
+ * For the `SMALBB` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the bottom 16-bit content of the 32-bit elements of Rs2.
+ * For the `SMALBT` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the top 16-bit content of the 32-bit elements of Rs2.
+ * For the `SMALTT` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
+ * the top 16-bit content of the 32-bit elements of Rs2.
+ * The multiplication results are added with the 64-bit value of Rd. The 64-bit addition result is written
+ * back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed
+ * integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * RV32:
+ * Mres[31:0] = Rs1.H[0] * Rs2.H[0]; // SMALBB
+ * Mres[31:0] = Rs1.H[0] * Rs2.H[1]; // SMALBT
+ * Mres[31:0] = Rs1.H[1] * Rs2.H[1]; // SMALTT
+ * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1);
+ * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]);
+ * RV64:
+ * // SMALBB
+ * Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[0];
+ * Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[0];
+ * // SMALBT
+ * Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[1];
+ * Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[1];
+ * // SMALTT
+ * Mres[0][31:0] = Rs1.W[0].H[1] * Rs2.W[0].H[1];
+ * Mres[1][31:0] = Rs1.W[1].H[1] * Rs2.W[1].H[1];
+ * Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]);
+ * ~~~
+ *
+ * \param [in]  t    long long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long long type
+ */
+__STATIC_FORCEINLINE long long __RV_SMALTT(long long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("smaltt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.105.3. SMALTT ===== */
+
+/* ===== Inline Function Start for 3.106.1. SMALDA ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB
+ * \brief SMALDA (Signed Multiply Two Halfs and Two Adds 64-bit)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMALDA Rd, Rs1, Rs2
+ * SMALXDA Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
+ * adds the two 32-bit results and the 64-bit value of an even/odd pair of registers together.
+ * * SMALDA: rt pair+ top*top + bottom*bottom (all 32-bit elements)
+ * * SMALXDA: rt pair+ top*bottom + bottom*top (all 32-bit elements)
+ *
+ * **RV32 Description**:\n
+ * For the `SMALDA` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit
+ * content of Rs2 and then adds the result to the result of multiplying the top 16-bit content of Rs1 with
+ * the top 16-bit content of Rs2 with unlimited precision.
+ * For the `SMALXDA` instruction, it multiplies the top 16-bit content of Rs1 with the bottom 16-bit
+ * content of Rs2 and then adds the result to the result of multiplying the bottom 16-bit content of Rs1
+ * with the top 16-bit content of Rs2 with unlimited precision.
+ * The result is added to the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64-
+ * bit addition result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64-
+ * bit value of the register-pair are treated as signed integers.
+ * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d`
+ * register of the pair contains the low 32-bit of the operand.
+ *
+ * **RV64 Description**:\n
+ * For the `SMALDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of
+ * multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-
+ * bit elements of Rs2 with unlimited precision.
+ * For the `SMALXDA` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1
+ * with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of
+ * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the
+ * 32-bit elements of Rs2 with unlimited precision.
+ * The results are added to the 64-bit value of Rd. The 64-bit addition result is written back to Rd. The
+ * 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * RV32:
+ * // SMALDA
+ * Mres0[31:0] = (Rs1.H[0] * Rs2.H[0]);
+ * Mres1[31:0] = (Rs1.H[1] * Rs2.H[1]);
+ * // SMALXDA
+ * Mres0[31:0] = (Rs1.H[0] * Rs2.H[1]);
+ * Mres1[31:0] = (Rs1.H[1] * Rs2.H[0]);
+ * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1);
+ * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres0[31:0]) + SE64(Mres1[31:0]);
+ * RV64:
+ * // SMALDA
+ * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]);
+ * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]);
+ * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[0]);
+ * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[1]);
+ * // SMALXDA
+ * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[1]);
+ * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]);
+ * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[1]);
+ * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[0]);
+ * Rd = Rd + SE64(Mres0[0][31:0]) + SE64(Mres1[0][31:0]) + SE64(Mres0[1][31:0]) +
+ * SE64(Mres1[1][31:0]);
+ * ~~~
+ *
+ * \param [in]  t    long long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long long type
+ */
+__STATIC_FORCEINLINE long long __RV_SMALDA(long long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("smalda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.106.1. SMALDA ===== */
+
+/* ===== Inline Function Start for 3.106.2. SMALXDA ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB
+ * \brief SMALXDA (Signed Crossed Multiply Two Halfs and Two Adds 64-bit)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMALDA Rd, Rs1, Rs2
+ * SMALXDA Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
+ * adds the two 32-bit results and the 64-bit value of an even/odd pair of registers together.
+ * * SMALDA: rt pair+ top*top + bottom*bottom (all 32-bit elements)
+ * * SMALXDA: rt pair+ top*bottom + bottom*top (all 32-bit elements)
+ *
+ * **RV32 Description**:\n
+ * For the `SMALDA` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit
+ * content of Rs2 and then adds the result to the result of multiplying the top 16-bit content of Rs1 with
+ * the top 16-bit content of Rs2 with unlimited precision.
+ * For the `SMALXDA` instruction, it multiplies the top 16-bit content of Rs1 with the bottom 16-bit
+ * content of Rs2 and then adds the result to the result of multiplying the bottom 16-bit content of Rs1
+ * with the top 16-bit content of Rs2 with unlimited precision.
+ * The result is added to the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64-
+ * bit addition result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64-
+ * bit value of the register-pair are treated as signed integers.
+ * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d`
+ * register of the pair contains the low 32-bit of the operand.
+ *
+ * **RV64 Description**:\n
+ * For the `SMALDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of
+ * multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-
+ * bit elements of Rs2 with unlimited precision.
+ * For the `SMALXDA` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1
+ * with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of
+ * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the
+ * 32-bit elements of Rs2 with unlimited precision.
+ * The results are added to the 64-bit value of Rd. The 64-bit addition result is written back to Rd. The
+ * 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * RV32:
+ * // SMALDA
+ * Mres0[31:0] = (Rs1.H[0] * Rs2.H[0]);
+ * Mres1[31:0] = (Rs1.H[1] * Rs2.H[1]);
+ * // SMALXDA
+ * Mres0[31:0] = (Rs1.H[0] * Rs2.H[1]);
+ * Mres1[31:0] = (Rs1.H[1] * Rs2.H[0]);
+ * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1);
+ * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres0[31:0]) + SE64(Mres1[31:0]);
+ * RV64:
+ * // SMALDA
+ * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]);
+ * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]);
+ * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[0]);
+ * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[1]);
+ * // SMALXDA
+ * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[1]);
+ * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]);
+ * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[1]);
+ * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[0]);
+ * Rd = Rd + SE64(Mres0[0][31:0]) + SE64(Mres1[0][31:0]) + SE64(Mres0[1][31:0]) +
+ * SE64(Mres1[1][31:0]);
+ * ~~~
+ *
+ * \param [in]  t    long long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long long type
+ */
+__STATIC_FORCEINLINE long long __RV_SMALXDA(long long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("smalxda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.106.2. SMALXDA ===== */
+
+/* ===== Inline Function Start for 3.107.1. SMALDS ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB
+ * \brief SMALDS (Signed Multiply Two Halfs & Subtract & Add 64-bit)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMALDS Rd, Rs1, Rs2
+ * SMALDRS Rd, Rs1, Rs2
+ * SMALXDS Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
+ * perform a subtraction operation between the two 32-bit results. Then add the subtraction result to
+ * the 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is
+ * written back to the register-pair.
+ * * SMALDS: rt pair + (top*top - bottom*bottom) (all 32-bit elements)
+ * * SMALDRS: rt pair + (bottom*bottom - top*top) (all 32-bit elements)
+ * * SMALXDS: rt pair + (top*bottom - bottom*top) (all 32-bit elements)
+ *
+ * **RV32 Description**:\n
+ * For the `SMALDS` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit
+ * content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of
+ * Rs1 with the top 16-bit content of Rs2.
+ * For the `SMALDRS` instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content
+ * of Rs2 and then subtracts the result from the result of multiplying the bottom 16-bit content of Rs1
+ * with the bottom 16-bit content of Rs2.
+ * For the `SMALXDS` instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit
+ * content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of
+ * Rs1 with the bottom 16-bit content of Rs2.
+ * The subtraction result is then added to the 64-bit value of an even/odd pair of registers specified by
+ * Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and
+ * Rs2, and the 64-bit value of the register-pair are treated as signed integers.
+ * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d`
+ * register of the pair contains the low 32-bit of the operand.
+ *
+ * **RV64 Description**:\n
+ * For the `SMALDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the
+ * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content
+ * of the 32-bit elements of Rs2.
+ * For the `SMALDRS` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
+ * the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of
+ * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of
+ * the 32-bit elements of Rs2.
+ * For the `SMALXDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the
+ * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit
+ * content of the 32-bit elements of Rs2.
+ * The subtraction results are then added to the 64-bit value of Rd. The 64-bit addition result is written
+ * back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed
+ * integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * Mres[31:0] = (Rs1.H[1] * Rs2.H[1]) - (Rs1.H[0] * Rs2.H[0]); // SMALDS
+ * Mres[31:0] = (Rs1.H[0] * Rs2.H[0]) - (Rs1.H[1] * Rs2.H[1]); // SMALDRS
+ * Mres[31:0] = (Rs1.H[1] * Rs2.H[0]) - (Rs1.H[0] * Rs2.H[1]); // SMALXDS
+ * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1);
+ * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]);
+ * * RV64:
+ * // SMALDS
+ * Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]) - (Rs1.W[0].H[0] * Rs2.W[0].H[0]);
+ * Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[1]) - (Rs1.W[1].H[0] * Rs2.W[1].H[0]);
+ * // SMALDRS
+ * Mres[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]) - (Rs1.W[0].H[1] * Rs2.W[0].H[1]);
+ * Mres[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[0].H[0]) - (Rs1.W[1].H[1] * Rs2.W[1].H[1]);
+ * // SMALXDS
+ * Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]) - (Rs1.W[0].H[0] * Rs2.W[0].H[1]);
+ * Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[0]) - (Rs1.W[1].H[0] * Rs2.W[1].H[1]);
+ * Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]);
+ * ~~~
+ *
+ * \param [in]  t    long long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long long type
+ */
+__STATIC_FORCEINLINE long long __RV_SMALDS(long long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("smalds %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.107.1. SMALDS ===== */
+
+/* ===== Inline Function Start for 3.107.2. SMALDRS ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB
+ * \brief SMALDRS (Signed Multiply Two Halfs & Reverse Subtract & Add 64- bit)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMALDS Rd, Rs1, Rs2
+ * SMALDRS Rd, Rs1, Rs2
+ * SMALXDS Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
+ * perform a subtraction operation between the two 32-bit results. Then add the subtraction result to
+ * the 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is
+ * written back to the register-pair.
+ * * SMALDS: rt pair + (top*top - bottom*bottom) (all 32-bit elements)
+ * * SMALDRS: rt pair + (bottom*bottom - top*top) (all 32-bit elements)
+ * * SMALXDS: rt pair + (top*bottom - bottom*top) (all 32-bit elements)
+ *
+ * **RV32 Description**:\n
+ * For the `SMALDS` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit
+ * content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of
+ * Rs1 with the top 16-bit content of Rs2.
+ * For the `SMALDRS` instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content
+ * of Rs2 and then subtracts the result from the result of multiplying the bottom 16-bit content of Rs1
+ * with the bottom 16-bit content of Rs2.
+ * For the `SMALXDS` instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit
+ * content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of
+ * Rs1 with the bottom 16-bit content of Rs2.
+ * The subtraction result is then added to the 64-bit value of an even/odd pair of registers specified by
+ * Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and
+ * Rs2, and the 64-bit value of the register-pair are treated as signed integers.
+ * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d`
+ * register of the pair contains the low 32-bit of the operand.
+ *
+ * **RV64 Description**:\n
+ * For the `SMALDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the
+ * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content
+ * of the 32-bit elements of Rs2.
+ * For the `SMALDRS` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
+ * the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of
+ * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of
+ * the 32-bit elements of Rs2.
+ * For the `SMALXDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the
+ * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit
+ * content of the 32-bit elements of Rs2.
+ * The subtraction results are then added to the 64-bit value of Rd. The 64-bit addition result is written
+ * back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed
+ * integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * Mres[31:0] = (Rs1.H[1] * Rs2.H[1]) - (Rs1.H[0] * Rs2.H[0]); // SMALDS
+ * Mres[31:0] = (Rs1.H[0] * Rs2.H[0]) - (Rs1.H[1] * Rs2.H[1]); // SMALDRS
+ * Mres[31:0] = (Rs1.H[1] * Rs2.H[0]) - (Rs1.H[0] * Rs2.H[1]); // SMALXDS
+ * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1);
+ * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]);
+ * * RV64:
+ * // SMALDS
+ * Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]) - (Rs1.W[0].H[0] * Rs2.W[0].H[0]);
+ * Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[1]) - (Rs1.W[1].H[0] * Rs2.W[1].H[0]);
+ * // SMALDRS
+ * Mres[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]) - (Rs1.W[0].H[1] * Rs2.W[0].H[1]);
+ * Mres[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[0].H[0]) - (Rs1.W[1].H[1] * Rs2.W[1].H[1]);
+ * // SMALXDS
+ * Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]) - (Rs1.W[0].H[0] * Rs2.W[0].H[1]);
+ * Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[0]) - (Rs1.W[1].H[0] * Rs2.W[1].H[1]);
+ * Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]);
+ * ~~~
+ *
+ * \param [in]  t    long long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long long type
+ */
+__STATIC_FORCEINLINE long long __RV_SMALDRS(long long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("smaldrs %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.107.2. SMALDRS ===== */
+
+/* ===== Inline Function Start for 3.107.3. SMALXDS ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB
+ * \brief SMALXDS (Signed Crossed Multiply Two Halfs & Subtract & Add 64- bit)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMALDS Rd, Rs1, Rs2
+ * SMALDRS Rd, Rs1, Rs2
+ * SMALXDS Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
+ * perform a subtraction operation between the two 32-bit results. Then add the subtraction result to
+ * the 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is
+ * written back to the register-pair.
+ * * SMALDS: rt pair + (top*top - bottom*bottom) (all 32-bit elements)
+ * * SMALDRS: rt pair + (bottom*bottom - top*top) (all 32-bit elements)
+ * * SMALXDS: rt pair + (top*bottom - bottom*top) (all 32-bit elements)
+ *
+ * **RV32 Description**:\n
+ * For the `SMALDS` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit
+ * content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of
+ * Rs1 with the top 16-bit content of Rs2.
+ * For the `SMALDRS` instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content
+ * of Rs2 and then subtracts the result from the result of multiplying the bottom 16-bit content of Rs1
+ * with the bottom 16-bit content of Rs2.
+ * For the `SMALXDS` instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit
+ * content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of
+ * Rs1 with the bottom 16-bit content of Rs2.
+ * The subtraction result is then added to the 64-bit value of an even/odd pair of registers specified by
+ * Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and
+ * Rs2, and the 64-bit value of the register-pair are treated as signed integers.
+ * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d`
+ * register of the pair contains the low 32-bit of the operand.
+ *
+ * **RV64 Description**:\n
+ * For the `SMALDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the
+ * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content
+ * of the 32-bit elements of Rs2.
+ * For the `SMALDRS` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
+ * the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of
+ * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of
+ * the 32-bit elements of Rs2.
+ * For the `SMALXDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the
+ * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit
+ * content of the 32-bit elements of Rs2.
+ * The subtraction results are then added to the 64-bit value of Rd. The 64-bit addition result is written
+ * back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed
+ * integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * Mres[31:0] = (Rs1.H[1] * Rs2.H[1]) - (Rs1.H[0] * Rs2.H[0]); // SMALDS
+ * Mres[31:0] = (Rs1.H[0] * Rs2.H[0]) - (Rs1.H[1] * Rs2.H[1]); // SMALDRS
+ * Mres[31:0] = (Rs1.H[1] * Rs2.H[0]) - (Rs1.H[0] * Rs2.H[1]); // SMALXDS
+ * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1);
+ * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]);
+ * * RV64:
+ * // SMALDS
+ * Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]) - (Rs1.W[0].H[0] * Rs2.W[0].H[0]);
+ * Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[1]) - (Rs1.W[1].H[0] * Rs2.W[1].H[0]);
+ * // SMALDRS
+ * Mres[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]) - (Rs1.W[0].H[1] * Rs2.W[0].H[1]);
+ * Mres[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[0].H[0]) - (Rs1.W[1].H[1] * Rs2.W[1].H[1]);
+ * // SMALXDS
+ * Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]) - (Rs1.W[0].H[0] * Rs2.W[0].H[1]);
+ * Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[0]) - (Rs1.W[1].H[0] * Rs2.W[1].H[1]);
+ * Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]);
+ * ~~~
+ *
+ * \param [in]  t    long long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long long type
+ */
+__STATIC_FORCEINLINE long long __RV_SMALXDS(long long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("smalxds %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.107.3. SMALXDS ===== */
+
+/* ===== Inline Function Start for 3.108. SMAR64 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB
+ * \brief SMAR64 (Signed Multiply and Add to 64-Bit Data)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMAR64 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the 32-bit signed elements in two registers and add the 64-bit multiplication
+ * result to the 64-bit signed data of a pair of registers (RV32) or a register (RV64). The result is written
+ * back to the pair of registers (RV32) or a register (RV64).
+ *
+ * **RV32 Description**:\n
+ * This instruction multiplies the 32-bit signed data of Rs1 with that of Rs2. It adds
+ * the 64-bit multiplication result to the 64-bit signed data of an even/odd pair of registers specified by
+ * Rd(4,1). The addition result is written back to the even/odd pair of registers specified by Rd(4,1).
+ * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
+ * of the pair contains the low 32-bit of the result.
+ *
+ * **RV64 Description**:\n
+ * This instruction multiplies the 32-bit signed elements of Rs1 with that of Rs2. It
+ * adds the 64-bit multiplication results to the 64-bit signed data of Rd. The addition result is written
+ * back to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
+ * R[t_H].R[t_L] = R[t_H].R[t_L] + (Rs1 * Rs2);
+ * * RV64:
+ * Rd = Rd + (Rs1.W[0] * Rs2.W[0]) + (Rs1.W[1] * Rs2.W[1]);
+ * ~~~
+ *
+ * \param [in]  t    long long type of value stored in t
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    long type of value stored in b
+ * \return value stored in long long type
+ */
+__STATIC_FORCEINLINE long long __RV_SMAR64(long long t, long a, long b)
+{
+    __ASM volatile("smar64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.108. SMAR64 ===== */
+
+/* ===== Inline Function Start for 3.109. SMAQA ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_8B_MULT_32B_ADD
+ * \brief SMAQA (Signed Multiply Four Bytes with 32-bit Adds)
+ * \details
+ * **Type**: Partial-SIMD (Reduction)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMAQA Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do four signed 8-bit multiplications from 32-bit chunks of two registers; and then adds
+ * the four 16-bit results and the content of corresponding 32-bit chunks of a third register together.
+ *
+ * **Description**:\n
+ * This instruction multiplies the four signed 8-bit elements of 32-bit chunks of Rs1 with the four
+ * signed 8-bit elements of 32-bit chunks of Rs2 and then adds the four results together with the signed
+ * content of the corresponding 32-bit chunks of Rd. The final results are written back to the
+ * corresponding 32-bit chunks in Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[x] = Rd.W[x] +
+ *    (Rs1.W[x].B[3] s* Rs2.W[x].B[3]) + (Rs1.W[x].B[2] s* Rs2.W[x].B[2]) +
+ *    (Rs1.W[x].B[1] s* Rs2.W[x].B[1]) + (Rs1.W[x].B[0] s* Rs2.W[x].B[0]);
+ * Rd.W[x] = res[x];
+ * for RV32: x=0,
+ * for RV64: x=1,0
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_SMAQA(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("smaqa %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.109. SMAQA ===== */
+
+/* ===== Inline Function Start for 3.110. SMAQA.SU ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_8B_MULT_32B_ADD
+ * \brief SMAQA.SU (Signed and Unsigned Multiply Four Bytes with 32-bit Adds)
+ * \details
+ * **Type**: Partial-SIMD (Reduction)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMAQA.SU Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do four `signed x unsigned` 8-bit multiplications from 32-bit chunks of two registers; and
+ * then adds the four 16-bit results and the content of corresponding 32-bit chunks of a third register
+ * together.
+ *
+ * **Description**:\n
+ * This instruction multiplies the four signed 8-bit elements of 32-bit chunks of Rs1 with the four
+ * unsigned 8-bit elements of 32-bit chunks of Rs2 and then adds the four results together with the
+ * signed content of the corresponding 32-bit chunks of Rd. The final results are written back to the
+ * corresponding 32-bit chunks in Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[x] = Rd.W[x] +
+ *    (Rs1.W[x].B[3] su* Rs2.W[x].B[3]) + (Rs1.W[x].B[2] su* Rs2.W[x].B[2]) +
+ *    (Rs1.W[x].B[1] su* Rs2.W[x].B[1]) + (Rs1.W[x].B[0] su* Rs2.W[x].B[0]);
+ * Rd.W[x] = res[x];
+ * for RV32: x=0,
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_SMAQA_SU(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("smaqa.su %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.110. SMAQA.SU ===== */
+
+/* ===== Inline Function Start for 3.111. SMAX8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC
+ * \brief SMAX8 (SIMD 8-bit Signed Maximum)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMAX8 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit signed integer elements finding maximum operations simultaneously.
+ *
+ * **Description**:\n
+ * This instruction compares the 8-bit signed integer elements in Rs1 with the 8-bit
+ * signed integer elements in Rs2 and selects the numbers that is greater than the other one. The
+ * selected results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.B[x] = (Rs1.B[x] > Rs2.B[x])? Rs1.B[x] : Rs2.B[x];
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SMAX8(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("smax8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.111. SMAX8 ===== */
+
+/* ===== Inline Function Start for 3.112. SMAX16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC
+ * \brief SMAX16 (SIMD 16-bit Signed Maximum)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMAX16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit signed integer elements finding maximum operations simultaneously.
+ *
+ * **Description**:\n
+ * This instruction compares the 16-bit signed integer elements in Rs1 with the 16-bit
+ * signed integer elements in Rs2 and selects the numbers that is greater than the other one. The
+ * selected results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.H[x] = (Rs1.H[x] > Rs2.H[x])? Rs1.H[x] : Rs2.H[x];
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SMAX16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("smax16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.112. SMAX16 ===== */
+
+/* ===== Inline Function Start for 3.113.1. SMBB16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
+ * \brief SMBB16 (SIMD Signed Multiply Bottom Half & Bottom Half)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMBB16 Rd, Rs1, Rs2
+ * SMBT16 Rd, Rs1, Rs2
+ * SMTT16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 16-bit content of the 32-bit elements of a register with the signed 16-
+ * bit content of the 32-bit elements of another register and write the result to a third register.
+ * * SMBB16: W[x].bottom*W[x].bottom
+ * * SMBT16: W[x].bottom *W[x].top
+ * * SMTT16: W[x].top * W[x].top
+ *
+ * **Description**:\n
+ * For the `SMBB16` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the bottom 16-bit content of the 32-bit elements of Rs2.
+ * For the `SMBT16` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the top 16-bit content of the 32-bit elements of Rs2.
+ * For the `SMTT16` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
+ * the top 16-bit content of the 32-bit elements of Rs2.
+ * The multiplication results are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as signed
+ * integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x] = Rs1.W[x].H[0] * Rs2.W[x].H[0]; // SMBB16
+ * Rd.W[x] = Rs1.W[x].H[0] * Rs2.W[x].H[1]; // SMBT16
+ * Rd.W[x] = Rs1.W[x].H[1] * Rs2.W[x].H[1]; // SMTT16
+ * for RV32: x=0,
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_SMBB16(unsigned long a, unsigned long b)
+{
+    register long result;
+    __ASM volatile("smbb16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.113.1. SMBB16 ===== */
+
+/* ===== Inline Function Start for 3.113.2. SMBT16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
+ * \brief SMBT16 (SIMD Signed Multiply Bottom Half & Top Half)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMBB16 Rd, Rs1, Rs2
+ * SMBT16 Rd, Rs1, Rs2
+ * SMTT16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 16-bit content of the 32-bit elements of a register with the signed 16-
+ * bit content of the 32-bit elements of another register and write the result to a third register.
+ * * SMBB16: W[x].bottom*W[x].bottom
+ * * SMBT16: W[x].bottom *W[x].top
+ * * SMTT16: W[x].top * W[x].top
+ *
+ * **Description**:\n
+ * For the `SMBB16` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the bottom 16-bit content of the 32-bit elements of Rs2.
+ * For the `SMBT16` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the top 16-bit content of the 32-bit elements of Rs2.
+ * For the `SMTT16` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
+ * the top 16-bit content of the 32-bit elements of Rs2.
+ * The multiplication results are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as signed
+ * integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x] = Rs1.W[x].H[0] * Rs2.W[x].H[0]; // SMBB16
+ * Rd.W[x] = Rs1.W[x].H[0] * Rs2.W[x].H[1]; // SMBT16
+ * Rd.W[x] = Rs1.W[x].H[1] * Rs2.W[x].H[1]; // SMTT16
+ * for RV32: x=0,
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_SMBT16(unsigned long a, unsigned long b)
+{
+    register long result;
+    __ASM volatile("smbt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.113.2. SMBT16 ===== */
+
+/* ===== Inline Function Start for 3.113.3. SMTT16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
+ * \brief SMTT16 (SIMD Signed Multiply Top Half & Top Half)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMBB16 Rd, Rs1, Rs2
+ * SMBT16 Rd, Rs1, Rs2
+ * SMTT16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 16-bit content of the 32-bit elements of a register with the signed 16-
+ * bit content of the 32-bit elements of another register and write the result to a third register.
+ * * SMBB16: W[x].bottom*W[x].bottom
+ * * SMBT16: W[x].bottom *W[x].top
+ * * SMTT16: W[x].top * W[x].top
+ *
+ * **Description**:\n
+ * For the `SMBB16` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the bottom 16-bit content of the 32-bit elements of Rs2.
+ * For the `SMBT16` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the top 16-bit content of the 32-bit elements of Rs2.
+ * For the `SMTT16` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
+ * the top 16-bit content of the 32-bit elements of Rs2.
+ * The multiplication results are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as signed
+ * integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x] = Rs1.W[x].H[0] * Rs2.W[x].H[0]; // SMBB16
+ * Rd.W[x] = Rs1.W[x].H[0] * Rs2.W[x].H[1]; // SMBT16
+ * Rd.W[x] = Rs1.W[x].H[1] * Rs2.W[x].H[1]; // SMTT16
+ * for RV32: x=0,
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_SMTT16(unsigned long a, unsigned long b)
+{
+    register long result;
+    __ASM volatile("smtt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.113.3. SMTT16 ===== */
+
+/* ===== Inline Function Start for 3.114.1. SMDS ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
+ * \brief SMDS (SIMD Signed Multiply Two Halfs and Subtract)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMDS Rd, Rs1, Rs2
+ * SMDRS Rd, Rs1, Rs2
+ * SMXDS Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
+ * perform a subtraction operation between the two 32-bit results.
+ * * SMDS: top*top - bottom*bottom (per 32-bit element)
+ * * SMDRS: bottom*bottom - top*top (per 32-bit element)
+ * * SMXDS: top*bottom - bottom*top (per 32-bit element)
+ *
+ * **Description**:\n
+ * For the `SMDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with
+ * the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result
+ * of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the
+ * 32-bit elements of Rs2.
+ * For the `SMDRS` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
+ * the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of
+ * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of
+ * the 32-bit elements of Rs2.
+ * For the `SMXDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the
+ * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit
+ * content of the 32-bit elements of Rs2.
+ * The subtraction result is written to the corresponding 32-bit element of Rd. The 16-bit contents of
+ * multiplication are treated as signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * * SMDS:
+ * Rd.W[x] = (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]);
+ * * SMDRS:
+ * Rd.W[x] = (Rs1.W[x].H[0] * Rs2.W[x].H[0]) - (Rs1.W[x].H[1] * Rs2.W[x].H[1]);
+ * * SMXDS:
+ * Rd.W[x] = (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]);
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_SMDS(unsigned long a, unsigned long b)
+{
+    register long result;
+    __ASM volatile("smds %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.114.1. SMDS ===== */
+
+/* ===== Inline Function Start for 3.114.2. SMDRS ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
+ * \brief SMDRS (SIMD Signed Multiply Two Halfs and Reverse Subtract)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMDS Rd, Rs1, Rs2
+ * SMDRS Rd, Rs1, Rs2
+ * SMXDS Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
+ * perform a subtraction operation between the two 32-bit results.
+ * * SMDS: top*top - bottom*bottom (per 32-bit element)
+ * * SMDRS: bottom*bottom - top*top (per 32-bit element)
+ * * SMXDS: top*bottom - bottom*top (per 32-bit element)
+ *
+ * **Description**:\n
+ * For the `SMDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with
+ * the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result
+ * of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the
+ * 32-bit elements of Rs2.
+ * For the `SMDRS` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
+ * the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of
+ * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of
+ * the 32-bit elements of Rs2.
+ * For the `SMXDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the
+ * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit
+ * content of the 32-bit elements of Rs2.
+ * The subtraction result is written to the corresponding 32-bit element of Rd. The 16-bit contents of
+ * multiplication are treated as signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * * SMDS:
+ * Rd.W[x] = (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]);
+ * * SMDRS:
+ * Rd.W[x] = (Rs1.W[x].H[0] * Rs2.W[x].H[0]) - (Rs1.W[x].H[1] * Rs2.W[x].H[1]);
+ * * SMXDS:
+ * Rd.W[x] = (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]);
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_SMDRS(unsigned long a, unsigned long b)
+{
+    register long result;
+    __ASM volatile("smdrs %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.114.2. SMDRS ===== */
+
+/* ===== Inline Function Start for 3.114.3. SMXDS ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
+ * \brief SMXDS (SIMD Signed Crossed Multiply Two Halfs and Subtract)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMDS Rd, Rs1, Rs2
+ * SMDRS Rd, Rs1, Rs2
+ * SMXDS Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
+ * perform a subtraction operation between the two 32-bit results.
+ * * SMDS: top*top - bottom*bottom (per 32-bit element)
+ * * SMDRS: bottom*bottom - top*top (per 32-bit element)
+ * * SMXDS: top*bottom - bottom*top (per 32-bit element)
+ *
+ * **Description**:\n
+ * For the `SMDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with
+ * the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result
+ * of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the
+ * 32-bit elements of Rs2.
+ * For the `SMDRS` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
+ * the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of
+ * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of
+ * the 32-bit elements of Rs2.
+ * For the `SMXDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the
+ * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit
+ * content of the 32-bit elements of Rs2.
+ * The subtraction result is written to the corresponding 32-bit element of Rd. The 16-bit contents of
+ * multiplication are treated as signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * * SMDS:
+ * Rd.W[x] = (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]);
+ * * SMDRS:
+ * Rd.W[x] = (Rs1.W[x].H[0] * Rs2.W[x].H[0]) - (Rs1.W[x].H[1] * Rs2.W[x].H[1]);
+ * * SMXDS:
+ * Rd.W[x] = (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]);
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_SMXDS(unsigned long a, unsigned long b)
+{
+    register long result;
+    __ASM volatile("smxds %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.114.3. SMXDS ===== */
+
+/* ===== Inline Function Start for 3.115. SMIN8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC
+ * \brief SMIN8 (SIMD 8-bit Signed Minimum)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMIN8 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit signed integer elements finding minimum operations simultaneously.
+ *
+ * **Description**:\n
+ * This instruction compares the 8-bit signed integer elements in Rs1 with the 8-bit
+ * signed integer elements in Rs2 and selects the numbers that is less than the other one. The selected
+ * results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.B[x] = (Rs1.B[x] < Rs2.B[x])? Rs1.B[x] : Rs2.B[x];
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SMIN8(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("smin8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.115. SMIN8 ===== */
+
+/* ===== Inline Function Start for 3.116. SMIN16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC
+ * \brief SMIN16 (SIMD 16-bit Signed Minimum)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMIN16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit signed integer elements finding minimum operations simultaneously.
+ *
+ * **Description**:\n
+ * This instruction compares the 16-bit signed integer elements in Rs1 with the 16-bit
+ * signed integer elements in Rs2 and selects the numbers that is less than the other one. The selected
+ * results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.H[x] = (Rs1.H[x] < Rs2.H[x])? Rs1.H[x] : Rs2.H[x];
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SMIN16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("smin16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.116. SMIN16 ===== */
+
+/* ===== Inline Function Start for 3.117.1. SMMUL ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC
+ * \brief SMMUL (SIMD MSW Signed Multiply Word)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMMUL Rd, Rs1, Rs2
+ * SMMUL.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the 32-bit signed integer elements of two registers and write the most significant
+ * 32-bit results to the corresponding 32-bit elements of a register. The `.u` form performs an
+ * additional rounding up operation on the multiplication results before taking the most significant
+ * 32-bit part of the results.
+ *
+ * **Description**:\n
+ * This instruction multiplies the 32-bit elements of Rs1 with the 32-bit elements of Rs2 and writes the
+ * most significant 32-bit multiplication results to the corresponding 32-bit elements of Rd. The 32-bit
+ * elements of Rs1 and Rs2 are treated as signed integers. The `.u` form of the instruction rounds up
+ * the most significant 32-bit of the 64-bit multiplication results by adding a 1 to bit 31 of the results.
+ * * For `smmul/RV32` instruction, it is an alias to `mulh/RV32` instruction.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x];
+ * if (`.u` form) {
+ *   Round[x][32:0] = Mres[x][63:31] + 1;
+ *   Rd.W[x] = Round[x][32:1];
+ * } else {
+ *   Rd.W[x] = Mres[x][63:32];
+ * }
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_SMMUL(long a, long b)
+{
+    register long result;
+    __ASM volatile("smmul %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.117.1. SMMUL ===== */
+
+/* ===== Inline Function Start for 3.117.2. SMMUL.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC
+ * \brief SMMUL.u (SIMD MSW Signed Multiply Word with Rounding)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMMUL Rd, Rs1, Rs2
+ * SMMUL.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the 32-bit signed integer elements of two registers and write the most significant
+ * 32-bit results to the corresponding 32-bit elements of a register. The `.u` form performs an
+ * additional rounding up operation on the multiplication results before taking the most significant
+ * 32-bit part of the results.
+ *
+ * **Description**:\n
+ * This instruction multiplies the 32-bit elements of Rs1 with the 32-bit elements of Rs2 and writes the
+ * most significant 32-bit multiplication results to the corresponding 32-bit elements of Rd. The 32-bit
+ * elements of Rs1 and Rs2 are treated as signed integers. The `.u` form of the instruction rounds up
+ * the most significant 32-bit of the 64-bit multiplication results by adding a 1 to bit 31 of the results.
+ * * For `smmul/RV32` instruction, it is an alias to `mulh/RV32` instruction.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x];
+ * if (`.u` form) {
+ *   Round[x][32:0] = Mres[x][63:31] + 1;
+ *   Rd.W[x] = Round[x][32:1];
+ * } else {
+ *   Rd.W[x] = Mres[x][63:32];
+ * }
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_SMMUL_U(long a, long b)
+{
+    register long result;
+    __ASM volatile("smmul.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.117.2. SMMUL.u ===== */
+
+/* ===== Inline Function Start for 3.118.1. SMMWB ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
+ * \brief SMMWB (SIMD MSW Signed Multiply Word and Bottom Half)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMMWB Rd, Rs1, Rs2
+ * SMMWB.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit integer elements of one register and the bottom 16-bit of the
+ * corresponding 32-bit elements of another register, and write the most significant 32-bit results to
+ * the corresponding 32-bit elements of a register. The `.u` form rounds up the results from the most
+ * significant discarded bit.
+ *
+ * **Description**:\n
+ * This instruction multiplies the signed 32-bit elements of Rs1 with the signed bottom 16-bit content
+ * of the corresponding 32-bit elements of Rs2 and writes the most significant 32-bit multiplication
+ * results to the corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the
+ * most significant 32-bit of the 48-bit multiplication results by adding a 1 to bit 15 of the results.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[0];
+ * if (`.u` form) {
+ *   Round[x][32:0] = Mres[x][47:15] + 1;
+ *   Rd.W[x] = Round[x][32:1];
+ * } else {
+ *   Rd.W[x] = Mres[x][47:16];
+ * }
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_SMMWB(long a, unsigned long b)
+{
+    register long result;
+    __ASM volatile("smmwb %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.118.1. SMMWB ===== */
+
+/* ===== Inline Function Start for 3.118.2. SMMWB.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
+ * \brief SMMWB.u (SIMD MSW Signed Multiply Word and Bottom Half with Rounding)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMMWB Rd, Rs1, Rs2
+ * SMMWB.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit integer elements of one register and the bottom 16-bit of the
+ * corresponding 32-bit elements of another register, and write the most significant 32-bit results to
+ * the corresponding 32-bit elements of a register. The `.u` form rounds up the results from the most
+ * significant discarded bit.
+ *
+ * **Description**:\n
+ * This instruction multiplies the signed 32-bit elements of Rs1 with the signed bottom 16-bit content
+ * of the corresponding 32-bit elements of Rs2 and writes the most significant 32-bit multiplication
+ * results to the corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the
+ * most significant 32-bit of the 48-bit multiplication results by adding a 1 to bit 15 of the results.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[0];
+ * if (`.u` form) {
+ *   Round[x][32:0] = Mres[x][47:15] + 1;
+ *   Rd.W[x] = Round[x][32:1];
+ * } else {
+ *   Rd.W[x] = Mres[x][47:16];
+ * }
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_SMMWB_U(long a, unsigned long b)
+{
+    register long result;
+    __ASM volatile("smmwb.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.118.2. SMMWB.u ===== */
+
+/* ===== Inline Function Start for 3.119.1. SMMWT ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
+ * \brief SMMWT (SIMD MSW Signed Multiply Word and Top Half)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMMWT Rd, Rs1, Rs2
+ * SMMWT.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit integer elements of one register and the top 16-bit of the
+ * corresponding 32-bit elements of another register, and write the most significant 32-bit results to
+ * the corresponding 32-bit elements of a register. The `.u` form rounds up the results from the most
+ * significant discarded bit.
+ *
+ * **Description**:\n
+ * This instruction multiplies the signed 32-bit elements of Rs1 with the top signed 16-bit content of
+ * the corresponding 32-bit elements of Rs2 and writes the most significant 32-bit multiplication
+ * results to the corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the
+ * most significant 32-bit of the 48-bit multiplication results by adding a 1 to bit 15 of the results.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[1];
+ * if (`.u` form) {
+ *   Round[x][32:0] = Mres[x][47:15] + 1;
+ *   Rd.W[x] = Round[x][32:1];
+ * } else {
+ *   Rd.W[x] = Mres[x][47:16];
+ * }
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_SMMWT(long a, unsigned long b)
+{
+    register long result;
+    __ASM volatile("smmwt %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.119.1. SMMWT ===== */
+
+/* ===== Inline Function Start for 3.119.2. SMMWT.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
+ * \brief SMMWT.u (SIMD MSW Signed Multiply Word and Top Half with Rounding)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMMWT Rd, Rs1, Rs2
+ * SMMWT.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit integer elements of one register and the top 16-bit of the
+ * corresponding 32-bit elements of another register, and write the most significant 32-bit results to
+ * the corresponding 32-bit elements of a register. The `.u` form rounds up the results from the most
+ * significant discarded bit.
+ *
+ * **Description**:\n
+ * This instruction multiplies the signed 32-bit elements of Rs1 with the top signed 16-bit content of
+ * the corresponding 32-bit elements of Rs2 and writes the most significant 32-bit multiplication
+ * results to the corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the
+ * most significant 32-bit of the 48-bit multiplication results by adding a 1 to bit 15 of the results.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[1];
+ * if (`.u` form) {
+ *   Round[x][32:0] = Mres[x][47:15] + 1;
+ *   Rd.W[x] = Round[x][32:1];
+ * } else {
+ *   Rd.W[x] = Mres[x][47:16];
+ * }
+ * for RV32: x=0
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_SMMWT_U(long a, unsigned long b)
+{
+    register long result;
+    __ASM volatile("smmwt.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.119.2. SMMWT.u ===== */
+
+/* ===== Inline Function Start for 3.120.1. SMSLDA ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB
+ * \brief SMSLDA (Signed Multiply Two Halfs & Add & Subtract 64-bit)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMSLDA Rd, Rs1, Rs2
+ * SMSLXDA Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
+ * subtracts the two 32-bit results from the 64-bit value of an even/odd pair of registers (RV32) or a
+ * register (RV64). The subtraction result is written back to the register-pair.
+ * * SMSLDA: rd pair - top*top - bottom*bottom (all 32-bit elements)
+ * * SMSLXDA: rd pair - top*bottom - bottom*top (all 32-bit elements)
+ *
+ * **RV32 Description**:\n
+ * For the `SMSLDA` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit
+ * content Rs2 and multiplies the top 16-bit content of Rs1 with the top 16-bit content of Rs2.
+ * For the `SMSLXDA` instruction, it multiplies the top 16-bit content of Rs1 with the bottom 16-bit
+ * content of Rs2 and multiplies the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2.
+ * The two multiplication results are subtracted from the 64-bit value of an even/odd pair of registers
+ * specified by Rd(4,1). The 64-bit subtraction result is written back to the register-pair. The 16-bit
+ * values of Rs1 and Rs2, and the 64-bit value of the register-pair are treated as signed integers.
+ * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
+ * of the pair contains the low 32-bit of the result.
+ *
+ * **RV64 Description**:\n
+ * For the `SMSLDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of
+ * the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2.
+ * For the `SMSLXDA` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
+ * the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the bottom 16-bit content of
+ * the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2.
+ * The four multiplication results are subtracted from the 64-bit value of Rd. The 64-bit subtraction
+ * result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated
+ * as signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * // SMSLDA
+ * Mres0[31:0] = (Rs1.H[0] * Rs2.H[0]);
+ * Mres1[31:0] = (Rs1.H[1] * Rs2.H[1]);
+ * // SMSLXDA
+ * Mres0[31:0] = (Rs1.H[0] * Rs2.H[1]);
+ * Mres1[31:0] = (Rs1.H[1] * Rs2.H[0]);
+ * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1);
+ * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] - SE64(Mres0[31:0]) - SE64(Mres1[31:0]);
+ * * RV64:
+ * // SMSLDA
+ * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]);
+ * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]);
+ * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[0]);
+ * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[1]);
+ * // SMSLXDA
+ * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[1]);
+ * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]);
+ * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[1]);
+ * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[0]);
+ * Rd = Rd - SE64(Mres0[0][31:0]) - SE64(Mres1[0][31:0]) - SE64(Mres0[1][31:0]) -
+ * SE64(Mres1[1][31:0]);
+ * ~~~
+ *
+ * \param [in]  t    long long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long long type
+ */
+__STATIC_FORCEINLINE long long __RV_SMSLDA(long long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("smslda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.120.1. SMSLDA ===== */
+
+/* ===== Inline Function Start for 3.120.2. SMSLXDA ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB
+ * \brief SMSLXDA (Signed Crossed Multiply Two Halfs & Add & Subtract 64- bit)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMSLDA Rd, Rs1, Rs2
+ * SMSLXDA Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
+ * subtracts the two 32-bit results from the 64-bit value of an even/odd pair of registers (RV32) or a
+ * register (RV64). The subtraction result is written back to the register-pair.
+ * * SMSLDA: rd pair - top*top - bottom*bottom (all 32-bit elements)
+ * * SMSLXDA: rd pair - top*bottom - bottom*top (all 32-bit elements)
+ *
+ * **RV32 Description**:\n
+ * For the `SMSLDA` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit
+ * content Rs2 and multiplies the top 16-bit content of Rs1 with the top 16-bit content of Rs2.
+ * For the `SMSLXDA` instruction, it multiplies the top 16-bit content of Rs1 with the bottom 16-bit
+ * content of Rs2 and multiplies the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2.
+ * The two multiplication results are subtracted from the 64-bit value of an even/odd pair of registers
+ * specified by Rd(4,1). The 64-bit subtraction result is written back to the register-pair. The 16-bit
+ * values of Rs1 and Rs2, and the 64-bit value of the register-pair are treated as signed integers.
+ * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
+ * of the pair contains the low 32-bit of the result.
+ *
+ * **RV64 Description**:\n
+ * For the `SMSLDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
+ * with the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of
+ * the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2.
+ * For the `SMSLXDA` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
+ * the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the bottom 16-bit content of
+ * the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2.
+ * The four multiplication results are subtracted from the 64-bit value of Rd. The 64-bit subtraction
+ * result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated
+ * as signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * // SMSLDA
+ * Mres0[31:0] = (Rs1.H[0] * Rs2.H[0]);
+ * Mres1[31:0] = (Rs1.H[1] * Rs2.H[1]);
+ * // SMSLXDA
+ * Mres0[31:0] = (Rs1.H[0] * Rs2.H[1]);
+ * Mres1[31:0] = (Rs1.H[1] * Rs2.H[0]);
+ * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1);
+ * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] - SE64(Mres0[31:0]) - SE64(Mres1[31:0]);
+ * * RV64:
+ * // SMSLDA
+ * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]);
+ * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]);
+ * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[0]);
+ * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[1]);
+ * // SMSLXDA
+ * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[1]);
+ * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]);
+ * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[1]);
+ * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[0]);
+ * Rd = Rd - SE64(Mres0[0][31:0]) - SE64(Mres1[0][31:0]) - SE64(Mres0[1][31:0]) -
+ * SE64(Mres1[1][31:0]);
+ * ~~~
+ *
+ * \param [in]  t    long long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long long type
+ */
+__STATIC_FORCEINLINE long long __RV_SMSLXDA(long long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("smslxda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.120.2. SMSLXDA ===== */
+
+/* ===== Inline Function Start for 3.121. SMSR64 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB
+ * \brief SMSR64 (Signed Multiply and Subtract from 64- Bit Data)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMSR64 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the 32-bit signed elements in two registers and subtract the 64-bit multiplication
+ * results from the 64-bit signed data of a pair of registers (RV32) or a register (RV64). The result is
+ * written back to the pair of registers (RV32) or a register (RV64).
+ *
+ * **RV32 Description**:\n
+ * This instruction multiplies the 32-bit signed data of Rs1 with that of Rs2. It
+ * subtracts the 64-bit multiplication result from the 64-bit signed data of an even/odd pair of registers
+ * specified by Rd(4,1). The subtraction result is written back to the even/odd pair of registers
+ * specified by Rd(4,1).
+ * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
+ * of the pair contains the low 32-bit of the result.
+ *
+ * **RV64 Description**:\n
+ * This instruction multiplies the 32-bit signed elements of Rs1 with that of Rs2. It
+ * subtracts the 64-bit multiplication results from the 64-bit signed data of Rd. The subtraction result is
+ * written back to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
+ * R[t_H].R[t_L] = R[t_H].R[t_L] - (Rs1 * Rs2);
+ * * RV64:
+ * Rd = Rd - (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]);
+ * ~~~
+ *
+ * \param [in]  t    long long type of value stored in t
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    long type of value stored in b
+ * \return value stored in long long type
+ */
+__STATIC_FORCEINLINE long long __RV_SMSR64(long long t, long a, long b)
+{
+    __ASM volatile("smsr64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.121. SMSR64 ===== */
+
+/* ===== Inline Function Start for 3.122.1. SMUL8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MULTIPLY
+ * \brief SMUL8 (SIMD Signed 8-bit Multiply)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMUL8 Rd, Rs1, Rs2
+ * SMULX8 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do signed 8-bit multiplications and generate four 16-bit results simultaneously.
+ *
+ * **RV32 Description**:\n
+ * For the `SMUL8` instruction, multiply the 8-bit data elements of Rs1 with the
+ * corresponding 8-bit data elements of Rs2.
+ * For the `SMULX8` instruction, multiply the first and second 8-bit data elements of Rs1 with the
+ * second and first 8-bit data elements of Rs2. At the same time, multiply the third and fourth 8-bit data
+ * elements of Rs1 with the fourth and third 8-bit data elements of Rs2.
+ * The four 16-bit results are then written into an even/odd pair of registers specified by Rd(4,1).
+ * Rd(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the two 16-bit results calculated from the top part of
+ * Rs1 and the even `2d` register of the pair contains the two 16-bit results calculated from the bottom
+ * part of Rs1.
+ *
+ * **RV64 Description**:\n
+ * For the `SMUL8` instruction, multiply the 8-bit data elements of Rs1 with the
+ * corresponding 8-bit data elements of Rs2.
+ * For the `SMULX8` instruction, multiply the first and second 8-bit data elements of Rs1 with the
+ * second and first 8-bit data elements of Rs2. At the same time, multiply the third and fourth 8-bit data
+ * elements of Rs1 with the fourth and third 8-bit data elements of Rs2.
+ * The four 16-bit results are then written into Rd. The Rd.W[1] contains the two 16-bit results
+ * calculated from the top part of Rs1 and the Rd.W[0] contains the two 16-bit results calculated from
+ * the bottom part of Rs1.
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * if (is `SMUL8`) {
+ *   op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x+1]; // top
+ *   op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x]; // bottom
+ * } else if (is `SMULX8`) {
+ *   op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x]; // Rs1 top
+ *   op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x+1]; // Rs1 bottom
+ * }
+ * rest[x/2] = op1t[x/2] s* op2t[x/2];
+ * resb[x/2] = op1b[x/2] s* op2b[x/2];
+ * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
+ * R[t_H].H[1] = rest[1]; R[t_H].H[0] = resb[1];
+ * R[t_L].H[1] = rest[0]; R[t_L].H[0] = resb[0];
+ * x = 0 and 2
+ * * RV64:
+ * if (is `SMUL8`) {
+ *   op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x+1]; // top
+ *   op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x]; // bottom
+ * } else if (is `SMULX8`) {
+ *   op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x]; // Rs1 top
+ *   op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x+1]; // Rs1 bottom
+ * }
+ * rest[x/2] = op1t[x/2] s* op2t[x/2];
+ * resb[x/2] = op1b[x/2] s* op2b[x/2];
+ * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
+ * Rd.W[1].H[1] = rest[1]; Rd.W[1].H[0] = resb[1];
+ * Rd.W[0].H[1] = rest[0]; Rd.W[0].H[0] = resb[0];
+ * x = 0 and 2
+ * ~~~
+ *
+ * \param [in]  a    unsigned int type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long long type
+ */
+__STATIC_FORCEINLINE unsigned long long __RV_SMUL8(unsigned int a, unsigned int b)
+{
+    register unsigned long long result;
+    __ASM volatile("smul8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.122.1. SMUL8 ===== */
+
+/* ===== Inline Function Start for 3.122.2. SMULX8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MULTIPLY
+ * \brief SMULX8 (SIMD Signed Crossed 8-bit Multiply)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMUL8 Rd, Rs1, Rs2
+ * SMULX8 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do signed 8-bit multiplications and generate four 16-bit results simultaneously.
+ *
+ * **RV32 Description**:\n
+ * For the `SMUL8` instruction, multiply the 8-bit data elements of Rs1 with the
+ * corresponding 8-bit data elements of Rs2.
+ * For the `SMULX8` instruction, multiply the first and second 8-bit data elements of Rs1 with the
+ * second and first 8-bit data elements of Rs2. At the same time, multiply the third and fourth 8-bit data
+ * elements of Rs1 with the fourth and third 8-bit data elements of Rs2.
+ * The four 16-bit results are then written into an even/odd pair of registers specified by Rd(4,1).
+ * Rd(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the two 16-bit results calculated from the top part of
+ * Rs1 and the even `2d` register of the pair contains the two 16-bit results calculated from the bottom
+ * part of Rs1.
+ *
+ * **RV64 Description**:\n
+ * For the `SMUL8` instruction, multiply the 8-bit data elements of Rs1 with the
+ * corresponding 8-bit data elements of Rs2.
+ * For the `SMULX8` instruction, multiply the first and second 8-bit data elements of Rs1 with the
+ * second and first 8-bit data elements of Rs2. At the same time, multiply the third and fourth 8-bit data
+ * elements of Rs1 with the fourth and third 8-bit data elements of Rs2.
+ * The four 16-bit results are then written into Rd. The Rd.W[1] contains the two 16-bit results
+ * calculated from the top part of Rs1 and the Rd.W[0] contains the two 16-bit results calculated from
+ * the bottom part of Rs1.
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * if (is `SMUL8`) {
+ *   op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x+1]; // top
+ *   op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x]; // bottom
+ * } else if (is `SMULX8`) {
+ *   op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x]; // Rs1 top
+ *   op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x+1]; // Rs1 bottom
+ * }
+ * rest[x/2] = op1t[x/2] s* op2t[x/2];
+ * resb[x/2] = op1b[x/2] s* op2b[x/2];
+ * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
+ * R[t_H].H[1] = rest[1]; R[t_H].H[0] = resb[1];
+ * R[t_L].H[1] = rest[0]; R[t_L].H[0] = resb[0];
+ * x = 0 and 2
+ * * RV64:
+ * if (is `SMUL8`) {
+ *   op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x+1]; // top
+ *   op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x]; // bottom
+ * } else if (is `SMULX8`) {
+ *   op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x]; // Rs1 top
+ *   op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x+1]; // Rs1 bottom
+ * }
+ * rest[x/2] = op1t[x/2] s* op2t[x/2];
+ * resb[x/2] = op1b[x/2] s* op2b[x/2];
+ * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
+ * Rd.W[1].H[1] = rest[1]; Rd.W[1].H[0] = resb[1];
+ * Rd.W[0].H[1] = rest[0]; Rd.W[0].H[0] = resb[0];
+ * x = 0 and 2
+ * ~~~
+ *
+ * \param [in]  a    unsigned int type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long long type
+ */
+__STATIC_FORCEINLINE unsigned long long __RV_SMULX8(unsigned int a, unsigned int b)
+{
+    register unsigned long long result;
+    __ASM volatile("smulx8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.122.2. SMULX8 ===== */
+
+/* ===== Inline Function Start for 3.123.1. SMUL16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MULTIPLY
+ * \brief SMUL16 (SIMD Signed 16-bit Multiply)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMUL16 Rd, Rs1, Rs2
+ * SMULX16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do signed 16-bit multiplications and generate two 32-bit results simultaneously.
+ *
+ * **RV32 Description**:\n
+ * For the `SMUL16` instruction, multiply the top 16-bit Q15 content of Rs1 with
+ * the top 16-bit Q15 content of Rs2. At the same time, multiply the bottom 16-bit Q15 content of Rs1
+ * with the bottom 16-bit Q15 content of Rs2.
+ * For the `SMULX16` instruction, multiply the top 16-bit Q15 content of Rs1 with the bottom 16-bit
+ * Q15 content of Rs2. At the same time, multiply the bottom 16-bit Q15 content of Rs1 with the top 16-
+ * bit Q15 content of Rs2.
+ * The two Q30 results are then written into an even/odd pair of registers specified by Rd(4,1). Rd(4,1),
+ * i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair includes
+ * register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the 32-bit result calculated from the top part of Rs1 and
+ * the even `2d` register of the pair contains the 32-bit result calculated from the bottom part of Rs1.
+ *
+ * **RV64 Description**:\n
+ * For the `SMUL16` instruction, multiply the top 16-bit Q15 content of the lower
+ * 32-bit word in Rs1 with the top 16-bit Q15 content of the lower 32-bit word in Rs2. At the same time,
+ * multiply the bottom 16-bit Q15 content of the lower 32-bit word in Rs1 with the bottom 16-bit Q15
+ * content of the lower 32-bit word in Rs2.
+ * For the `SMULX16` instruction, multiply the top 16-bit Q15 content of the lower 32-bit word in Rs1
+ * with the bottom 16-bit Q15 content of the lower 32-bit word in Rs2. At the same time, multiply the
+ * bottom 16-bit Q15 content of the lower 32-bit word in Rs1 with the top 16-bit Q15 content of the
+ * lower 32-bit word in Rs2.
+ * The two 32-bit Q30 results are then written into Rd. The result calculated from the top 16-bit of the
+ * lower 32-bit word in Rs1 is written to Rd.W[1]. And the result calculated from the bottom 16-bit of
+ * the lower 32-bit word in Rs1 is written to Rd.W[0]
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * if (is `SMUL16`) {
+ *   op1t = Rs1.H[1]; op2t = Rs2.H[1]; // top
+ *   op1b = Rs1.H[0]; op2b = Rs2.H[0]; // bottom
+ * } else if (is `SMULX16`) {
+ *   op1t = Rs1.H[1]; op2t = Rs2.H[0]; // Rs1 top
+ *   op1b = Rs1.H[0]; op2b = Rs2.H[1]; // Rs1 bottom
+ * }
+ * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) {
+ *   res = aop s* bop;
+ * }
+ * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
+ * R[t_H] = rest;
+ * R[t_L] = resb;
+ * * RV64:
+ * if (is `SMUL16`) {
+ *   op1t = Rs1.H[1]; op2t = Rs2.H[1]; // top
+ *   op1b = Rs1.H[0]; op2b = Rs2.H[0]; // bottom
+ * } else if (is `SMULX16`) {
+ *   op1t = Rs1.H[1]; op2t = Rs2.H[0]; // Rs1 top
+ *   op1b = Rs1.H[0]; op2b = Rs2.H[1]; // Rs1 bottom
+ * }
+ * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) {
+ *   res = aop s* bop;
+ * }
+ * Rd.W[1] = rest;
+ * Rd.W[0] = resb;
+ * ~~~
+ *
+ * \param [in]  a    unsigned int type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long long type
+ */
+__STATIC_FORCEINLINE unsigned long long __RV_SMUL16(unsigned int a, unsigned int b)
+{
+    register unsigned long long result;
+    __ASM volatile("smul16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.123.1. SMUL16 ===== */
+
+/* ===== Inline Function Start for 3.123.2. SMULX16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MULTIPLY
+ * \brief SMULX16 (SIMD Signed Crossed 16-bit Multiply)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMUL16 Rd, Rs1, Rs2
+ * SMULX16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do signed 16-bit multiplications and generate two 32-bit results simultaneously.
+ *
+ * **RV32 Description**:\n
+ * For the `SMUL16` instruction, multiply the top 16-bit Q15 content of Rs1 with
+ * the top 16-bit Q15 content of Rs2. At the same time, multiply the bottom 16-bit Q15 content of Rs1
+ * with the bottom 16-bit Q15 content of Rs2.
+ * For the `SMULX16` instruction, multiply the top 16-bit Q15 content of Rs1 with the bottom 16-bit
+ * Q15 content of Rs2. At the same time, multiply the bottom 16-bit Q15 content of Rs1 with the top 16-
+ * bit Q15 content of Rs2.
+ * The two Q30 results are then written into an even/odd pair of registers specified by Rd(4,1). Rd(4,1),
+ * i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair includes
+ * register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the 32-bit result calculated from the top part of Rs1 and
+ * the even `2d` register of the pair contains the 32-bit result calculated from the bottom part of Rs1.
+ *
+ * **RV64 Description**:\n
+ * For the `SMUL16` instruction, multiply the top 16-bit Q15 content of the lower
+ * 32-bit word in Rs1 with the top 16-bit Q15 content of the lower 32-bit word in Rs2. At the same time,
+ * multiply the bottom 16-bit Q15 content of the lower 32-bit word in Rs1 with the bottom 16-bit Q15
+ * content of the lower 32-bit word in Rs2.
+ * For the `SMULX16` instruction, multiply the top 16-bit Q15 content of the lower 32-bit word in Rs1
+ * with the bottom 16-bit Q15 content of the lower 32-bit word in Rs2. At the same time, multiply the
+ * bottom 16-bit Q15 content of the lower 32-bit word in Rs1 with the top 16-bit Q15 content of the
+ * lower 32-bit word in Rs2.
+ * The two 32-bit Q30 results are then written into Rd. The result calculated from the top 16-bit of the
+ * lower 32-bit word in Rs1 is written to Rd.W[1]. And the result calculated from the bottom 16-bit of
+ * the lower 32-bit word in Rs1 is written to Rd.W[0]
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * if (is `SMUL16`) {
+ *   op1t = Rs1.H[1]; op2t = Rs2.H[1]; // top
+ *   op1b = Rs1.H[0]; op2b = Rs2.H[0]; // bottom
+ * } else if (is `SMULX16`) {
+ *   op1t = Rs1.H[1]; op2t = Rs2.H[0]; // Rs1 top
+ *   op1b = Rs1.H[0]; op2b = Rs2.H[1]; // Rs1 bottom
+ * }
+ * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) {
+ *   res = aop s* bop;
+ * }
+ * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
+ * R[t_H] = rest;
+ * R[t_L] = resb;
+ * * RV64:
+ * if (is `SMUL16`) {
+ *   op1t = Rs1.H[1]; op2t = Rs2.H[1]; // top
+ *   op1b = Rs1.H[0]; op2b = Rs2.H[0]; // bottom
+ * } else if (is `SMULX16`) {
+ *   op1t = Rs1.H[1]; op2t = Rs2.H[0]; // Rs1 top
+ *   op1b = Rs1.H[0]; op2b = Rs2.H[1]; // Rs1 bottom
+ * }
+ * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) {
+ *   res = aop s* bop;
+ * }
+ * Rd.W[1] = rest;
+ * Rd.W[0] = resb;
+ * ~~~
+ *
+ * \param [in]  a    unsigned int type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long long type
+ */
+__STATIC_FORCEINLINE unsigned long long __RV_SMULX16(unsigned int a, unsigned int b)
+{
+    register unsigned long long result;
+    __ASM volatile("smulx16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.123.2. SMULX16 ===== */
+
+/* ===== Inline Function Start for 3.124. SRA.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
+ * \brief SRA.u (Rounding Shift Right Arithmetic)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRA.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Perform an arithmetic right shift operation with rounding. The shift amount is a variable
+ * from a GPR.
+ *
+ * **Description**:\n
+ * This instruction right-shifts the content of Rs1 arithmetically. The shifted out bits are
+ * filled with the sign-bit and the shift amount is specified by the low-order 5-bits (RV32) or 6-bits
+ * (RV64) of the Rs2 register. For the rounding operation, a value of 1 is added to the most significant
+ * discarded bit of the data to calculate the final result. And the result is written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * sa = Rs2[4:0];
+ * if (sa > 0) {
+ *   res[31:-1] = SE33(Rs1[31:(sa-1)]) + 1;
+ *   Rd = res[31:0];
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * * RV64:
+ * sa = Rs2[5:0];
+ * if (sa > 0) {
+ *   res[63:-1] = SE65(Rs1[63:(sa-1)]) + 1;
+ *   Rd = res[63:0];
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * ~~~
+ *
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_SRA_U(long a, unsigned int b)
+{
+    register long result;
+    __ASM volatile("sra.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.124. SRA.u ===== */
+
+/* ===== Inline Function Start for 3.125. SRAI.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
+ * \brief SRAI.u (Rounding Shift Right Arithmetic Immediate)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRAI.u Rd, Rs1, imm6u[4:0] (RV32)
+ * SRAI.u Rd, Rs1, imm6u[5:0] (RV64)
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Perform an arithmetic right shift operation with rounding. The shift amount is an
+ * immediate value.
+ *
+ * **Description**:\n
+ * This instruction right-shifts the content of Rs1 arithmetically. The shifted out bits are
+ * filled with the sign-bit and the shift amount is specified by the imm6u[4:0] (RV32) or imm6u[5:0]
+ * (RV64) constant . For the rounding operation, a value of 1 is added to the most significant discarded
+ * bit of the data to calculate the final result. And the result is written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * sa = imm6u[4:0];
+ * if (sa > 0) {
+ *   res[31:-1] = SE33(Rs1[31:(sa-1)]) + 1;
+ *   Rd = res[31:0];
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * * RV64:
+ * sa = imm6u[5:0];
+ * if (sa > 0) {
+ *   res[63:-1] = SE65(Rs1[63:(sa-1)]) + 1;
+ *   Rd = res[63:0];
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * ~~~
+ *
+ * \param [in]  a    long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in long type
+ */
+#define __RV_SRAI_U(a, b)    \
+    ({    \
+        register long result;    \
+        register long __a = (long)(a);    \
+        __ASM volatile("srai.u %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
+        result;    \
+    })
+/* ===== Inline Function End for 3.125. SRAI.u ===== */
+
+/* ===== Inline Function Start for 3.126.1. SRA8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
+ * \brief SRA8 (SIMD 8-bit Shift Right Arithmetic)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRA8 Rd, Rs1, Rs2
+ * SRA8.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit element arithmetic right shift operations simultaneously. The shift amount is a
+ * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted
+ * results.
+ *
+ * **Description**:\n
+ * The 8-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out
+ * bits are filled with the sign-bit of the data elements. The shift amount is specified by the low-order
+ * 3-bits of the value in the Rs2 register. For the rounding operation of the `.u` form, a value of 1 is
+ * added to the most significant discarded bit of each 8-bit data element to calculate the final results.
+ * And the results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = Rs2[2:0];
+ * if (sa > 0) {
+ *   if (`.u` form) { // SRA8.u
+ *     res[7:-1] = SE9(Rs1.B[x][7:sa-1]) + 1;
+ *     Rd.B[x] = res[7:0];
+ *   } else { // SRA8
+ *     Rd.B[x] = SE8(Rd.B[x][7:sa])
+ *   }
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SRA8(unsigned long a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("sra8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.126.1. SRA8 ===== */
+
+/* ===== Inline Function Start for 3.126.2. SRA8.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
+ * \brief SRA8.u (SIMD 8-bit Rounding Shift Right Arithmetic)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRA8 Rd, Rs1, Rs2
+ * SRA8.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit element arithmetic right shift operations simultaneously. The shift amount is a
+ * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted
+ * results.
+ *
+ * **Description**:\n
+ * The 8-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out
+ * bits are filled with the sign-bit of the data elements. The shift amount is specified by the low-order
+ * 3-bits of the value in the Rs2 register. For the rounding operation of the `.u` form, a value of 1 is
+ * added to the most significant discarded bit of each 8-bit data element to calculate the final results.
+ * And the results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = Rs2[2:0];
+ * if (sa > 0) {
+ *   if (`.u` form) { // SRA8.u
+ *     res[7:-1] = SE9(Rs1.B[x][7:sa-1]) + 1;
+ *     Rd.B[x] = res[7:0];
+ *   } else { // SRA8
+ *     Rd.B[x] = SE8(Rd.B[x][7:sa])
+ *   }
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SRA8_U(unsigned long a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("sra8.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.126.2. SRA8.u ===== */
+
+/* ===== Inline Function Start for 3.127.1. SRAI8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
+ * \brief SRAI8 (SIMD 8-bit Shift Right Arithmetic Immediate)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRAI8 Rd, Rs1, imm3u
+ * SRAI8.u Rd, Rs1, imm3u
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit element arithmetic right shift operations simultaneously. The shift amount is an
+ * immediate value. The `.u` form performs additional rounding up operations on the shifted results.
+ *
+ * **Description**:\n
+ * The 8-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out
+ * bits are filled with the sign-bit of the data elements. The shift amount is specified by the imm3u
+ * constant. For the rounding operation of the `.u` form, a value of 1 is added to the most significant
+ * discarded bit of each 8-bit data element to calculate the final results. And the results are written to
+ * Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = imm3u[2:0];
+ * if (sa > 0) {
+ *   if (`.u` form) { // SRA8.u
+ *     res[7:-1] = SE9(Rs1.B[x][7:sa-1]) + 1;
+ *     Rd.B[x] = res[7:0];
+ *   } else { // SRA8
+ *     Rd.B[x] = SE8(Rd.B[x][7:sa])
+ *   }
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+#define __RV_SRAI8(a, b)    \
+    ({    \
+        register unsigned long result;    \
+        register unsigned long __a = (unsigned long)(a);    \
+        __ASM volatile("srai8 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
+        result;    \
+    })
+/* ===== Inline Function End for 3.127.1. SRAI8 ===== */
+
+/* ===== Inline Function Start for 3.127.2. SRAI8.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
+ * \brief SRAI8.u (SIMD 8-bit Rounding Shift Right Arithmetic Immediate)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRAI8 Rd, Rs1, imm3u
+ * SRAI8.u Rd, Rs1, imm3u
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit element arithmetic right shift operations simultaneously. The shift amount is an
+ * immediate value. The `.u` form performs additional rounding up operations on the shifted results.
+ *
+ * **Description**:\n
+ * The 8-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out
+ * bits are filled with the sign-bit of the data elements. The shift amount is specified by the imm3u
+ * constant. For the rounding operation of the `.u` form, a value of 1 is added to the most significant
+ * discarded bit of each 8-bit data element to calculate the final results. And the results are written to
+ * Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = imm3u[2:0];
+ * if (sa > 0) {
+ *   if (`.u` form) { // SRA8.u
+ *     res[7:-1] = SE9(Rs1.B[x][7:sa-1]) + 1;
+ *     Rd.B[x] = res[7:0];
+ *   } else { // SRA8
+ *     Rd.B[x] = SE8(Rd.B[x][7:sa])
+ *   }
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+#define __RV_SRAI8_U(a, b)    \
+    ({    \
+        register unsigned long result;    \
+        register unsigned long __a = (unsigned long)(a);    \
+        __ASM volatile("srai8.u %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
+        result;    \
+    })
+/* ===== Inline Function End for 3.127.2. SRAI8.u ===== */
+
+/* ===== Inline Function Start for 3.128.1. SRA16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
+ * \brief SRA16 (SIMD 16-bit Shift Right Arithmetic)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRA16 Rd, Rs1, Rs2
+ * SRA16.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit element arithmetic right shift operations simultaneously. The shift amount is a
+ * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted
+ * results.
+ *
+ * **Description**:\n
+ * The 16-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out
+ * bits are filled with the sign-bit of the data elements. The shift amount is specified by the low-order
+ * 4-bits of the value in the Rs2 register. For the rounding operation of the `.u` form, a value of 1 is
+ * added to the most significant discarded bit of each 16-bit data element to calculate the final results.
+ * And the results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = Rs2[3:0];
+ * if (sa != 0) {
+ *   if (`.u` form) { // SRA16.u
+ *     res[15:-1] = SE17(Rs1.H[x][15:sa-1]) + 1;
+ *     Rd.H[x] = res[15:0];
+ *   } else { // SRA16
+ *     Rd.H[x] = SE16(Rs1.H[x][15:sa])
+ *   }
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SRA16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("sra16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.128.1. SRA16 ===== */
+
+/* ===== Inline Function Start for 3.128.2. SRA16.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
+ * \brief SRA16.u (SIMD 16-bit Rounding Shift Right Arithmetic)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRA16 Rd, Rs1, Rs2
+ * SRA16.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit element arithmetic right shift operations simultaneously. The shift amount is a
+ * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted
+ * results.
+ *
+ * **Description**:\n
+ * The 16-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out
+ * bits are filled with the sign-bit of the data elements. The shift amount is specified by the low-order
+ * 4-bits of the value in the Rs2 register. For the rounding operation of the `.u` form, a value of 1 is
+ * added to the most significant discarded bit of each 16-bit data element to calculate the final results.
+ * And the results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = Rs2[3:0];
+ * if (sa != 0) {
+ *   if (`.u` form) { // SRA16.u
+ *     res[15:-1] = SE17(Rs1.H[x][15:sa-1]) + 1;
+ *     Rd.H[x] = res[15:0];
+ *   } else { // SRA16
+ *     Rd.H[x] = SE16(Rs1.H[x][15:sa])
+ *   }
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SRA16_U(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("sra16.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.128.2. SRA16.u ===== */
+
+/* ===== Inline Function Start for 3.129.1. SRAI16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
+ * \brief SRAI16 (SIMD 16-bit Shift Right Arithmetic Immediate)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRAI16 Rd, Rs1, imm4u
+ * SRAI16.u Rd, Rs1, imm4u
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit elements arithmetic right shift operations simultaneously. The shift amount is
+ * an immediate value. The `.u` form performs additional rounding up operations on the shifted
+ * results.
+ *
+ * **Description**:\n
+ * The 16-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out
+ * bits are filled with the sign-bit of the 16-bit data elements. The shift amount is specified by the
+ * imm4u constant. For the rounding operation of the `.u` form, a value of 1 is added to the most
+ * significant discarded bit of each 16-bit data to calculate the final results. And the results are written
+ * to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = imm4u[3:0];
+ * if (sa > 0) {
+ *   if (`.u` form) { // SRAI16.u
+ *     res[15:-1] = SE17(Rs1.H[x][15:sa-1]) + 1;
+ *     Rd.H[x] = res[15:0];
+ *   } else { // SRAI16
+ *     Rd.H[x] = SE16(Rs1.H[x][15:sa]);
+ *   }
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+#define __RV_SRAI16(a, b)    \
+    ({    \
+        register unsigned long result;    \
+        register unsigned long __a = (unsigned long)(a);    \
+        __ASM volatile("srai16 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
+        result;    \
+    })
+/* ===== Inline Function End for 3.129.1. SRAI16 ===== */
+
+/* ===== Inline Function Start for 3.129.2. SRAI16.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
+ * \brief SRAI16.u (SIMD 16-bit Rounding Shift Right Arithmetic Immediate)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRAI16 Rd, Rs1, imm4u
+ * SRAI16.u Rd, Rs1, imm4u
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit elements arithmetic right shift operations simultaneously. The shift amount is
+ * an immediate value. The `.u` form performs additional rounding up operations on the shifted
+ * results.
+ *
+ * **Description**:\n
+ * The 16-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out
+ * bits are filled with the sign-bit of the 16-bit data elements. The shift amount is specified by the
+ * imm4u constant. For the rounding operation of the `.u` form, a value of 1 is added to the most
+ * significant discarded bit of each 16-bit data to calculate the final results. And the results are written
+ * to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = imm4u[3:0];
+ * if (sa > 0) {
+ *   if (`.u` form) { // SRAI16.u
+ *     res[15:-1] = SE17(Rs1.H[x][15:sa-1]) + 1;
+ *     Rd.H[x] = res[15:0];
+ *   } else { // SRAI16
+ *     Rd.H[x] = SE16(Rs1.H[x][15:sa]);
+ *   }
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+#define __RV_SRAI16_U(a, b)    \
+    ({    \
+        register unsigned long result;    \
+        register unsigned long __a = (unsigned long)(a);    \
+        __ASM volatile("srai16.u %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
+        result;    \
+    })
+/* ===== Inline Function End for 3.129.2. SRAI16.u ===== */
+
+/* ===== Inline Function Start for 3.130.1. SRL8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
+ * \brief SRL8 (SIMD 8-bit Shift Right Logical)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRL8 Rt, Ra, Rb
+ * SRL8.u Rt, Ra, Rb
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit elements logical right shift operations simultaneously. The shift amount is a
+ * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted
+ * results.
+ *
+ * **Description**:\n
+ * The 8-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits are
+ * filled with zero. The shift amount is specified by the low-order 3-bits of the value in the Rs2 register.
+ * For the rounding operation of the `.u` form, a value of 1 is added to the most significant discarded
+ * bit of each 8-bit data element to calculate the final results. And the results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = Rs2[2:0];
+ * if (sa > 0) {
+ *   if (`.u` form) { // SRL8.u
+ *     res[8:0] = ZE9(Rs1.B[x][7:sa-1]) + 1;
+ *     Rd.B[x] = res[8:1];
+ *   } else { // SRL8
+ *     Rd.B[x] = ZE8(Rs1.B[x][7:sa]);
+ *   }
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SRL8(unsigned long a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("srl8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.130.1. SRL8 ===== */
+
+/* ===== Inline Function Start for 3.130.2. SRL8.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
+ * \brief SRL8.u (SIMD 8-bit Rounding Shift Right Logical)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRL8 Rt, Ra, Rb
+ * SRL8.u Rt, Ra, Rb
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit elements logical right shift operations simultaneously. The shift amount is a
+ * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted
+ * results.
+ *
+ * **Description**:\n
+ * The 8-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits are
+ * filled with zero. The shift amount is specified by the low-order 3-bits of the value in the Rs2 register.
+ * For the rounding operation of the `.u` form, a value of 1 is added to the most significant discarded
+ * bit of each 8-bit data element to calculate the final results. And the results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = Rs2[2:0];
+ * if (sa > 0) {
+ *   if (`.u` form) { // SRL8.u
+ *     res[8:0] = ZE9(Rs1.B[x][7:sa-1]) + 1;
+ *     Rd.B[x] = res[8:1];
+ *   } else { // SRL8
+ *     Rd.B[x] = ZE8(Rs1.B[x][7:sa]);
+ *   }
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SRL8_U(unsigned long a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("srl8.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.130.2. SRL8.u ===== */
+
+/* ===== Inline Function Start for 3.131.1. SRLI8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
+ * \brief SRLI8 (SIMD 8-bit Shift Right Logical Immediate)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRLI8 Rt, Ra, imm3u
+ * SRLI8.u Rt, Ra, imm3u
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit elements logical right shift operations simultaneously. The shift amount is an
+ * immediate value. The `.u` form performs additional rounding up operations on the shifted results.
+ *
+ * **Description**:\n
+ * The 8-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits are
+ * filled with zero. The shift amount is specified by the imm3u constant. For the rounding operation of
+ * the `.u` form, a value of 1 is added to the most significant discarded bit of each 8-bit data element to
+ * calculate the final results. And the results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = imm3u[2:0];
+ * if (sa > 0) {
+ *   if (`.u` form) { // SRLI8.u
+ *     res[8:0] = ZE9(Rs1.B[x][7:sa-1]) + 1;
+ *     Rd.B[x] = res[8:1];
+ *   } else { // SRLI8
+ *     Rd.B[x] = ZE8(Rs1.B[x][7:sa]);
+ *   }
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+#define __RV_SRLI8(a, b)    \
+    ({    \
+        register unsigned long result;    \
+        register unsigned long __a = (unsigned long)(a);    \
+        __ASM volatile("srli8 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
+        result;    \
+    })
+/* ===== Inline Function End for 3.131.1. SRLI8 ===== */
+
+/* ===== Inline Function Start for 3.131.2. SRLI8.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
+ * \brief SRLI8.u (SIMD 8-bit Rounding Shift Right Logical Immediate)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRLI8 Rt, Ra, imm3u
+ * SRLI8.u Rt, Ra, imm3u
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit elements logical right shift operations simultaneously. The shift amount is an
+ * immediate value. The `.u` form performs additional rounding up operations on the shifted results.
+ *
+ * **Description**:\n
+ * The 8-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits are
+ * filled with zero. The shift amount is specified by the imm3u constant. For the rounding operation of
+ * the `.u` form, a value of 1 is added to the most significant discarded bit of each 8-bit data element to
+ * calculate the final results. And the results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = imm3u[2:0];
+ * if (sa > 0) {
+ *   if (`.u` form) { // SRLI8.u
+ *     res[8:0] = ZE9(Rs1.B[x][7:sa-1]) + 1;
+ *     Rd.B[x] = res[8:1];
+ *   } else { // SRLI8
+ *     Rd.B[x] = ZE8(Rs1.B[x][7:sa]);
+ *   }
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+#define __RV_SRLI8_U(a, b)    \
+    ({    \
+        register unsigned long result;    \
+        register unsigned long __a = (unsigned long)(a);    \
+        __ASM volatile("srli8.u %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
+        result;    \
+    })
+/* ===== Inline Function End for 3.131.2. SRLI8.u ===== */
+
+/* ===== Inline Function Start for 3.132.1. SRL16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
+ * \brief SRL16 (SIMD 16-bit Shift Right Logical)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRL16 Rt, Ra, Rb
+ *  SRL16.u Rt, Ra, Rb
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit elements logical right shift operations simultaneously. The shift amount is a variable from a GPR. The `.u` form performs additional rounding upoperations on the shifted results.
+ *
+ * **Description**:\n
+ * The 16-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits
+ * are filled with zero. The shift amount is specified by the low-order 4-bits of the value in the Rs2
+ * register. For the rounding operation of the `.u` form, a value of 1 is added to the most significant
+ * discarded bit of each 16-bit data element to calculate the final results. And the results are written to
+ * Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = Rs2[3:0];
+ * if (sa > 0) {
+ *   if (`.u` form) { // SRL16.u
+ *     res[16:0] = ZE17(Rs1.H[x][15:sa-1]) + 1;
+ *     Rd.H[x] = res[16:1];
+ *   } else { // SRL16
+ *     Rd.H[x] = ZE16(Rs1.H[x][15:sa]);
+ *   }
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SRL16(unsigned long a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("srl16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.132.1. SRL16 ===== */
+
+/* ===== Inline Function Start for 3.132.2. SRL16.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
+ * \brief SRL16.u (SIMD 16-bit Rounding Shift Right Logical)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRL16 Rt, Ra, Rb
+ *  SRL16.u Rt, Ra, Rb
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit elements logical right shift operations simultaneously. The shift amount is a variable from a GPR. The `.u` form performs additional rounding upoperations on the shifted results.
+ *
+ * **Description**:\n
+ * The 16-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits
+ * are filled with zero. The shift amount is specified by the low-order 4-bits of the value in the Rs2
+ * register. For the rounding operation of the `.u` form, a value of 1 is added to the most significant
+ * discarded bit of each 16-bit data element to calculate the final results. And the results are written to
+ * Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = Rs2[3:0];
+ * if (sa > 0) {
+ *   if (`.u` form) { // SRL16.u
+ *     res[16:0] = ZE17(Rs1.H[x][15:sa-1]) + 1;
+ *     Rd.H[x] = res[16:1];
+ *   } else { // SRL16
+ *     Rd.H[x] = ZE16(Rs1.H[x][15:sa]);
+ *   }
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SRL16_U(unsigned long a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("srl16.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.132.2. SRL16.u ===== */
+
+/* ===== Inline Function Start for 3.133.1. SRLI16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
+ * \brief SRLI16 (SIMD 16-bit Shift Right Logical Immediate)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRLI16 Rt, Ra, imm4u
+ * SRLI16.u Rt, Ra, imm4u
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit elements logical right shift operations simultaneously. The shift amount is an
+ * immediate value. The `.u` form performs additional rounding up operations on the shifted results.
+ *
+ * **Description**:\n
+ * The 16-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits
+ * are filled with zero. The shift amount is specified by the imm4u constant. For the rounding
+ * operation of the `.u` form, a value of 1 is added to the most significant discarded bit of each 16-bit
+ * data element to calculate the final results. And the results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = imm4u;
+ * if (sa > 0) {
+ *   if (`.u` form) { // SRLI16.u
+ *     res[16:0] = ZE17(Rs1.H[x][15:sa-1]) + 1;
+ *     Rd.H[x] = res[16:1];
+ *   } else { // SRLI16
+ *     Rd.H[x] = ZE16(Rs1.H[x][15:sa]);
+ *   }
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+#define __RV_SRLI16(a, b)    \
+    ({    \
+        register unsigned long result;    \
+        register unsigned long __a = (unsigned long)(a);    \
+        __ASM volatile("srli16 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
+        result;    \
+    })
+/* ===== Inline Function End for 3.133.1. SRLI16 ===== */
+
+/* ===== Inline Function Start for 3.133.2. SRLI16.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
+ * \brief SRLI16.u (SIMD 16-bit Rounding Shift Right Logical Immediate)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRLI16 Rt, Ra, imm4u
+ * SRLI16.u Rt, Ra, imm4u
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit elements logical right shift operations simultaneously. The shift amount is an
+ * immediate value. The `.u` form performs additional rounding up operations on the shifted results.
+ *
+ * **Description**:\n
+ * The 16-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits
+ * are filled with zero. The shift amount is specified by the imm4u constant. For the rounding
+ * operation of the `.u` form, a value of 1 is added to the most significant discarded bit of each 16-bit
+ * data element to calculate the final results. And the results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = imm4u;
+ * if (sa > 0) {
+ *   if (`.u` form) { // SRLI16.u
+ *     res[16:0] = ZE17(Rs1.H[x][15:sa-1]) + 1;
+ *     Rd.H[x] = res[16:1];
+ *   } else { // SRLI16
+ *     Rd.H[x] = ZE16(Rs1.H[x][15:sa]);
+ *   }
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+#define __RV_SRLI16_U(a, b)    \
+    ({    \
+        register unsigned long result;    \
+        register unsigned long __a = (unsigned long)(a);    \
+        __ASM volatile("srli16.u %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
+        result;    \
+    })
+/* ===== Inline Function End for 3.133.2. SRLI16.u ===== */
+
+/* ===== Inline Function Start for 3.134. STAS16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief STAS16 (SIMD 16-bit Straight Addition & Subtraction)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * STAS16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit integer element addition and 16-bit integer element subtraction in a 32-bit
+ * chunk simultaneously. Operands are from corresponding positions in 32-bit chunks.
+ *
+ * **Description**:\n
+ * This instruction adds the 16-bit integer element in [31:16] of 32-bit chunks in Rs1 with
+ * the 16-bit integer element in [31:16] of 32-bit chunks in Rs2, and writes the result to [31:16] of 32-bit
+ * chunks in Rd; at the same time, it subtracts the 16-bit integer element in [15:0] of 32-bit chunks in
+ * Rs2 from the 16-bit integer element in [15:0] of 32-bit chunks, and writes the result to [15:0] of 32-
+ * bit chunks in Rd.
+ *
+ * **Note**:\n
+ * This instruction can be used for either signed or unsigned operations.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x][31:16] = Rs1.W[x][31:16] + Rs2.W[x][31:16];
+ * Rd.W[x][15:0] = Rs1.W[x][15:0] - Rs2.W[x][15:0];
+ * for RV32, x=0
+ * for RV64, x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_STAS16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("stas16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.134. STAS16 ===== */
+
+/* ===== Inline Function Start for 3.135. STSA16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief STSA16 (SIMD 16-bit Straight Subtraction & Addition)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * STSA16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit integer element subtraction and 16-bit integer element addition in a 32-bit
+ * chunk simultaneously. Operands are from corresponding positions in 32-bit chunks.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 16-bit integer element in [31:16] of 32-bit chunks in Rs2
+ * from the 16-bit integer element in [31:16] of 32-bit chunks in Rs1, and writes the result to [31:16] of
+ * 32-bit chunks in Rd; at the same time, it adds the 16-bit integer element in [15:0] of 32-bit chunks in
+ * Rs2 with the 16-bit integer element in [15:0] of 32-bit chunks in Rs1, and writes the result to [15:0] of
+ * 32-bit chunks in Rd.
+ *
+ * **Note**:\n
+ * This instruction can be used for either signed or unsigned operations.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x][31:16] = Rs1.W[x][31:16] - Rs2.W[x][31:16];
+ * Rd.W[x][15:0] = Rs1.W[x][15:0] + Rs2.W[x][15:0];
+ * for RV32, x=0
+ * for RV64, x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_STSA16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("stsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.135. STSA16 ===== */
+
+/* ===== Inline Function Start for 3.136. SUB8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB
+ * \brief SUB8 (SIMD 8-bit Subtraction)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SUB8 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit integer element subtractions simultaneously.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 8-bit integer elements in Rs2 from the 8-bit integer
+ * elements in Rs1, and then writes the result to Rd.
+ *
+ * **Note**:\n
+ * This instruction can be used for either signed or unsigned subtraction.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.B[x] = Rs1.B[x] - Rs2.B[x];
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SUB8(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("sub8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.136. SUB8 ===== */
+
+/* ===== Inline Function Start for 3.137. SUB16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief SUB16 (SIMD 16-bit Subtraction)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SUB16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit integer element subtractions simultaneously.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 16-bit integer elements in Rs2 from the 16-bit integer
+ * elements in Rs1, and then writes the result to Rd.
+ *
+ * **Note**:\n
+ * This instruction can be used for either signed or unsigned subtraction.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.H[x] = Rs1.H[x] - Rs2.H[x];
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SUB16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("sub16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.137. SUB16 ===== */
+
+/* ===== Inline Function Start for 3.138. SUB64 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB
+ * \brief SUB64 (64-bit Subtraction)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SUB64 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Perform a 64-bit signed or unsigned integer subtraction.
+ *
+ * **RV32 Description**:\n
+ * This instruction subtracts the 64-bit integer of an even/odd pair of registers
+ * specified by Rs2(4,1) from the 64-bit integer of an even/odd pair of registers specified by Rs1(4,1),
+ * and then writes the 64-bit result to an even/odd pair of registers specified by Rd(4,1).
+ * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d`
+ * register of the pair contains the low 32-bit of the operand.
+ *
+ * **RV64 Description**:\n
+ * This instruction subtracts the 64-bit integer of Rs2 from the 64-bit integer of Rs1,
+ * and then writes the 64-bit result to Rd.
+ *
+ * **Note**:\n
+ * This instruction can be used for either signed or unsigned subtraction.
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
+ * a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1);
+ * b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1);
+ * R[t_H].R[t_L] = R[a_H].R[a_L] - R[b_H].R[b_L];
+ * * RV64:
+ * Rd = Rs1 - Rs2;
+ * ~~~
+ *
+ * \param [in]  a    unsigned long long type of value stored in a
+ * \param [in]  b    unsigned long long type of value stored in b
+ * \return value stored in unsigned long long type
+ */
+__STATIC_FORCEINLINE unsigned long long __RV_SUB64(unsigned long long a, unsigned long long b)
+{
+    register unsigned long long result;
+    __ASM volatile("sub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.138. SUB64 ===== */
+
+/* ===== Inline Function Start for 3.139.1. SUNPKD810 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK
+ * \brief SUNPKD810 (Signed Unpacking Bytes 1 & 0)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SUNPKD8xy Rd, Rs1
+ * xy = {10, 20, 30, 31, 32}
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Unpack byte *x and byte y* of 32-bit chunks in a register into two 16-bit signed halfwords
+ * of 32-bit chunks in a register.
+ *
+ * **Description**:\n
+ * For the `SUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into
+ * two 16-bit signed halfwords and writes the results to the top part and the bottom part of 32-bit
+ * chunks in Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[m].H[1] = SE16(Rs1.W[m].B[x])
+ * Rd.W[m].H[0] = SE16(Rs1.W[m].B[y])
+ * // SUNPKD810, x=1,y=0
+ * // SUNPKD820, x=2,y=0
+ * // SUNPKD830, x=3,y=0
+ * // SUNPKD831, x=3,y=1
+ * // SUNPKD832, x=3,y=2
+ * for RV32: m=0,
+ * for RV64: m=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SUNPKD810(unsigned long a)
+{
+    register unsigned long result;
+    __ASM volatile("sunpkd810 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 3.139.1. SUNPKD810 ===== */
+
+/* ===== Inline Function Start for 3.139.2. SUNPKD820 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK
+ * \brief SUNPKD820 (Signed Unpacking Bytes 2 & 0)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SUNPKD8xy Rd, Rs1
+ * xy = {10, 20, 30, 31, 32}
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Unpack byte *x and byte y* of 32-bit chunks in a register into two 16-bit signed halfwords
+ * of 32-bit chunks in a register.
+ *
+ * **Description**:\n
+ * For the `SUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into
+ * two 16-bit signed halfwords and writes the results to the top part and the bottom part of 32-bit
+ * chunks in Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[m].H[1] = SE16(Rs1.W[m].B[x])
+ * Rd.W[m].H[0] = SE16(Rs1.W[m].B[y])
+ * // SUNPKD810, x=1,y=0
+ * // SUNPKD820, x=2,y=0
+ * // SUNPKD830, x=3,y=0
+ * // SUNPKD831, x=3,y=1
+ * // SUNPKD832, x=3,y=2
+ * for RV32: m=0,
+ * for RV64: m=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SUNPKD820(unsigned long a)
+{
+    register unsigned long result;
+    __ASM volatile("sunpkd820 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 3.139.2. SUNPKD820 ===== */
+
+/* ===== Inline Function Start for 3.139.3. SUNPKD830 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK
+ * \brief SUNPKD830 (Signed Unpacking Bytes 3 & 0)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SUNPKD8xy Rd, Rs1
+ * xy = {10, 20, 30, 31, 32}
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Unpack byte *x and byte y* of 32-bit chunks in a register into two 16-bit signed halfwords
+ * of 32-bit chunks in a register.
+ *
+ * **Description**:\n
+ * For the `SUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into
+ * two 16-bit signed halfwords and writes the results to the top part and the bottom part of 32-bit
+ * chunks in Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[m].H[1] = SE16(Rs1.W[m].B[x])
+ * Rd.W[m].H[0] = SE16(Rs1.W[m].B[y])
+ * // SUNPKD810, x=1,y=0
+ * // SUNPKD820, x=2,y=0
+ * // SUNPKD830, x=3,y=0
+ * // SUNPKD831, x=3,y=1
+ * // SUNPKD832, x=3,y=2
+ * for RV32: m=0,
+ * for RV64: m=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SUNPKD830(unsigned long a)
+{
+    register unsigned long result;
+    __ASM volatile("sunpkd830 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 3.139.3. SUNPKD830 ===== */
+
+/* ===== Inline Function Start for 3.139.4. SUNPKD831 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK
+ * \brief SUNPKD831 (Signed Unpacking Bytes 3 & 1)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SUNPKD8xy Rd, Rs1
+ * xy = {10, 20, 30, 31, 32}
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Unpack byte *x and byte y* of 32-bit chunks in a register into two 16-bit signed halfwords
+ * of 32-bit chunks in a register.
+ *
+ * **Description**:\n
+ * For the `SUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into
+ * two 16-bit signed halfwords and writes the results to the top part and the bottom part of 32-bit
+ * chunks in Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[m].H[1] = SE16(Rs1.W[m].B[x])
+ * Rd.W[m].H[0] = SE16(Rs1.W[m].B[y])
+ * // SUNPKD810, x=1,y=0
+ * // SUNPKD820, x=2,y=0
+ * // SUNPKD830, x=3,y=0
+ * // SUNPKD831, x=3,y=1
+ * // SUNPKD832, x=3,y=2
+ * for RV32: m=0,
+ * for RV64: m=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SUNPKD831(unsigned long a)
+{
+    register unsigned long result;
+    __ASM volatile("sunpkd831 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 3.139.4. SUNPKD831 ===== */
+
+/* ===== Inline Function Start for 3.139.5. SUNPKD832 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK
+ * \brief SUNPKD832 (Signed Unpacking Bytes 3 & 2)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SUNPKD8xy Rd, Rs1
+ * xy = {10, 20, 30, 31, 32}
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Unpack byte *x and byte y* of 32-bit chunks in a register into two 16-bit signed halfwords
+ * of 32-bit chunks in a register.
+ *
+ * **Description**:\n
+ * For the `SUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into
+ * two 16-bit signed halfwords and writes the results to the top part and the bottom part of 32-bit
+ * chunks in Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[m].H[1] = SE16(Rs1.W[m].B[x])
+ * Rd.W[m].H[0] = SE16(Rs1.W[m].B[y])
+ * // SUNPKD810, x=1,y=0
+ * // SUNPKD820, x=2,y=0
+ * // SUNPKD830, x=3,y=0
+ * // SUNPKD831, x=3,y=1
+ * // SUNPKD832, x=3,y=2
+ * for RV32: m=0,
+ * for RV64: m=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SUNPKD832(unsigned long a)
+{
+    register unsigned long result;
+    __ASM volatile("sunpkd832 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 3.139.5. SUNPKD832 ===== */
+
+/* ===== Inline Function Start for 3.140. SWAP8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
+ * \brief SWAP8 (Swap Byte within Halfword)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SWAP8 Rd, Rs1
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Swap the bytes within each halfword of a register.
+ *
+ * **Description**:\n
+ * This instruction swaps the bytes within each halfword of Rs1 and writes the result to
+ * Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.H[x] = CONCAT(Rs1.H[x][7:0],Rs1.H[x][15:8]);
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SWAP8(unsigned long a)
+{
+    register unsigned long result;
+    __ASM volatile("swap8 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 3.140. SWAP8 ===== */
+
+/* ===== Inline Function Start for 3.141. SWAP16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
+ * \brief SWAP16 (Swap Halfword within Word)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SWAP16 Rd, Rs1
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Swap the 16-bit halfwords within each word of a register.
+ *
+ * **Description**:\n
+ * This instruction swaps the 16-bit halfwords within each word of Rs1 and writes the
+ * result to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x] = CONCAT(Rs1.W[x][15:0],Rs1.H[x][31:16]);
+ * for RV32: x=0,
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SWAP16(unsigned long a)
+{
+    register unsigned long result;
+    __ASM volatile("swap16 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 3.141. SWAP16 ===== */
+
+/* ===== Inline Function Start for 3.142. UCLIP8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC
+ * \brief UCLIP8 (SIMD 8-bit Unsigned Clip Value)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UCLIP8 Rt, Ra, imm3u
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Limit the 8-bit signed elements of a register into an unsigned range simultaneously.
+ *
+ * **Description**:\n
+ * This instruction limits the 8-bit signed elements stored in Rs1 into an unsigned integer
+ * range between 2^imm3u-1 and 0, and writes the limited results to Rd. For example, if imm3u is 3, the 8-
+ * bit input values should be saturated between 7 and 0. If saturation is performed, set OV bit to 1.
+ *
+ * **Operations**:\n
+ * ~~~
+ * src = Rs1.H[x];
+ * if (src > (2^imm3u)-1) {
+ *   src = (2^imm3u)-1;
+ *   OV = 1;
+ * } else if (src < 0) {
+ *   src = 0;
+ *   OV = 1;
+ * }
+ * Rd.H[x] = src;
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+#define __RV_UCLIP8(a, b)    \
+    ({    \
+        register unsigned long result;    \
+        register unsigned long __a = (unsigned long)(a);    \
+        __ASM volatile("uclip8 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
+        result;    \
+    })
+/* ===== Inline Function End for 3.142. UCLIP8 ===== */
+
+/* ===== Inline Function Start for 3.143. UCLIP16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC
+ * \brief UCLIP16 (SIMD 16-bit Unsigned Clip Value)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UCLIP16 Rt, Ra, imm4u
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Limit the 16-bit signed elements of a register into an unsigned range simultaneously.
+ *
+ * **Description**:\n
+ * This instruction limits the 16-bit signed elements stored in Rs1 into an unsigned
+ * integer range between 2imm4u-1 and 0, and writes the limited results to Rd. For example, if imm4u is
+ * 3, the 16-bit input values should be saturated between 7 and 0. If saturation is performed, set OV bit
+ * to 1.
+ *
+ * **Operations**:\n
+ * ~~~
+ * src = Rs1.H[x];
+ * if (src > (2^imm4u)-1) {
+ *   src = (2^imm4u)-1;
+ *   OV = 1;
+ * } else if (src < 0) {
+ *   src = 0;
+ *   OV = 1;
+ * }
+ * Rd.H[x] = src;
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+#define __RV_UCLIP16(a, b)    \
+    ({    \
+        register unsigned long result;    \
+        register unsigned long __a = (unsigned long)(a);    \
+        __ASM volatile("uclip16 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
+        result;    \
+    })
+/* ===== Inline Function End for 3.143. UCLIP16 ===== */
+
+/* ===== Inline Function Start for 3.144. UCLIP32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC
+ * \brief UCLIP32 (SIMD 32-bit Unsigned Clip Value)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UCLIP32 Rd, Rs1, imm5u[4:0]
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Limit the 32-bit signed integer elements of a register into an unsigned range
+ * simultaneously.
+ *
+ * **Description**:\n
+ * This instruction limits the 32-bit signed integer elements stored in Rs1 into an
+ * unsigned integer range between 2imm5u-1 and 0, and writes the limited results to Rd. For example, if
+ * imm5u is 3, the 32-bit input values should be saturated between 7 and 0. If saturation is performed,
+ * set OV bit to 1.
+ *
+ * **Operations**:\n
+ * ~~~
+ * src = Rs1.W[x];
+ * if (src > (2^imm5u)-1) {
+ *   src = (2^imm5u)-1;
+ *   OV = 1;
+ * } else if (src < 0) {
+ *   src = 0;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = src
+ * for RV32: x=0,
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+#define __RV_UCLIP32(a, b)    \
+    ({    \
+        register unsigned long result;    \
+        register unsigned long __a = (unsigned long)(a);    \
+        __ASM volatile("uclip32 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
+        result;    \
+    })
+/* ===== Inline Function End for 3.144. UCLIP32 ===== */
+
+/* ===== Inline Function Start for 3.145. UCMPLE8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_CMP
+ * \brief UCMPLE8 (SIMD 8-bit Unsigned Compare Less Than & Equal)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UCMPLE8 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit unsigned integer elements less than & equal comparisons simultaneously.
+ *
+ * **Description**:\n
+ * This instruction compares the 8-bit unsigned integer elements in Rs1 with the 8-bit
+ * unsigned integer elements in Rs2 to see if the one in Rs1 is less than or equal to the one in Rs2. If it
+ * is true, the result is 0xFF; otherwise, the result is 0x0. The four comparison results are written to
+ * Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.B[x] = (Rs1.B[x] <=u Rs2.B[x])? 0xff : 0x0;
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_UCMPLE8(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("ucmple8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.145. UCMPLE8 ===== */
+
+/* ===== Inline Function Start for 3.146. UCMPLE16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_CMP
+ * \brief UCMPLE16 (SIMD 16-bit Unsigned Compare Less Than & Equal)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UCMPLE16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit unsigned integer elements less than & equal comparisons simultaneously.
+ *
+ * **Description**:\n
+ * This instruction compares the 16-bit unsigned integer elements in Rs1 with the 16-bit
+ * unsigned integer elements in Rs2 to see if the one in Rs1 is less than or equal to the one in Rs2. If it
+ * is true, the result is 0xFFFF; otherwise, the result is 0x0. The element comparison results are
+ * written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.H[x] = (Rs1.H[x] <=u Rs2.H[x])? 0xffff : 0x0;
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_UCMPLE16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("ucmple16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.146. UCMPLE16 ===== */
+
+/* ===== Inline Function Start for 3.147. UCMPLT8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_CMP
+ * \brief UCMPLT8 (SIMD 8-bit Unsigned Compare Less Than)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UCMPLT8 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit unsigned integer elements less than comparisons simultaneously.
+ *
+ * **Description**:\n
+ * This instruction compares the 8-bit unsigned integer elements in Rs1 with the 8-bit
+ * unsigned integer elements in Rs2 to see if the one in Rs1 is less than the one in Rs2. If it is true, the
+ * result is 0xFF; otherwise, the result is 0x0. The element comparison results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.B[x] = (Rs1.B[x]  (2^8)-1) {
+ *   res[x] = (2^8)-1;
+ *   OV = 1;
+ * }
+ * Rd.B[x] = res[x];
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_UKADD8(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("ukadd8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.149. UKADD8 ===== */
+
+/* ===== Inline Function Start for 3.150. UKADD16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief UKADD16 (SIMD 16-bit Unsigned Saturating Addition)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UKADD16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit unsigned integer element saturating additions simultaneously.
+ *
+ * **Description**:\n
+ * This instruction adds the 16-bit unsigned integer elements in Rs1 with the 16-bit
+ * unsigned integer elements in Rs2. If any of the results are beyond the 16-bit unsigned number
+ * range (0 <= RES <= 2^16-1), they are saturated to the range and the OV bit is set to 1. The saturated
+ * results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[x] = Rs1.H[x] + Rs2.H[x];
+ * if (res[x] > (2^16)-1) {
+ *   res[x] = (2^16)-1;
+ *   OV = 1;
+ * }
+ * Rd.H[x] = res[x];
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_UKADD16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("ukadd16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.150. UKADD16 ===== */
+
+/* ===== Inline Function Start for 3.151. UKADD64 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB
+ * \brief UKADD64 (64-bit Unsigned Saturating Addition)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UKADD64 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Add two 64-bit unsigned integers. The result is saturated to the U64 range.
+ *
+ * **RV32 Description**:\n
+ * This instruction adds the 64-bit unsigned integer of an even/odd pair of registers
+ * specified by Rs1(4,1) with the 64-bit unsigned integer of an even/odd pair of registers specified by
+ * Rs2(4,1). If the 64-bit result is beyond the U64 number range (0 <= U64 <= 2^64-1), it is saturated to the
+ * range and the OV bit is set to 1. The saturated result is written to an even/odd pair of registers
+ * specified by Rd(4,1).
+ * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
+ * of the pair contains the low 32-bit of the result.
+ *
+ * **RV64 Description**:\n
+ * This instruction adds the 64-bit unsigned integer in Rs1 with the 64-bit unsigned
+ * integer in Rs2. If the 64-bit result is beyond the U64 number range (0 <= U64 <= 2^64-1), it is saturated to
+ * the range and the OV bit is set to 1. The saturated result is written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * t_L = CONCAT(Rt(4,1),1'b0); t_H = CONCAT(Rt(4,1),1'b1);
+ * a_L = CONCAT(Ra(4,1),1'b0); a_H = CONCAT(Ra(4,1),1'b1);
+ * b_L = CONCAT(Rb(4,1),1'b0); b_H = CONCAT(Rb(4,1),1'b1);
+ * result = R[a_H].R[a_L] + R[b_H].R[b_L];
+ * if (result > (2^64)-1) {
+ *   result = (2^64)-1; OV = 1;
+ * }
+ * R[t_H].R[t_L] = result;
+ * * RV64:
+ * result = Rs1 + Rs2;
+ * if (result > (2^64)-1) {
+ *   result = (2^64)-1; OV = 1;
+ * }
+ * Rd = result;
+ * ~~~
+ *
+ * \param [in]  a    unsigned long long type of value stored in a
+ * \param [in]  b    unsigned long long type of value stored in b
+ * \return value stored in unsigned long long type
+ */
+__STATIC_FORCEINLINE unsigned long long __RV_UKADD64(unsigned long long a, unsigned long long b)
+{
+    register unsigned long long result;
+    __ASM volatile("ukadd64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.151. UKADD64 ===== */
+
+/* ===== Inline Function Start for 3.152. UKADDH ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU
+ * \brief UKADDH (Unsigned Addition with U16 Saturation)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UKADDH Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Add the unsigned lower 32-bit content of two registers with U16 saturation.
+ *
+ * **Description**:\n
+ * The unsigned lower 32-bit content of Rs1 is added with the unsigned lower 32-bit
+ * content of Rs2. And the result is saturated to the 16-bit unsigned integer range of [0, 2^16-1] and then
+ * sign-extended and written to Rd. If saturation happens, this instruction sets the OV flag.
+ *
+ * **Operations**:\n
+ * ~~~
+ * tmp = Rs1.W[0] + Rs2.W[0];
+ * if (tmp > (2^16)-1) {
+ *   tmp = (2^16)-1;
+ *   OV = 1;
+ * }
+ * Rd = SE(tmp[15:0]);
+ * ~~~
+ *
+ * \param [in]  a    unsigned int type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_UKADDH(unsigned int a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("ukaddh %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.152. UKADDH ===== */
+
+/* ===== Inline Function Start for 3.153. UKADDW ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
+ * \brief UKADDW (Unsigned Addition with U32 Saturation)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UKADDW Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Add the unsigned lower 32-bit content of two registers with U32 saturation.
+ *
+ * **Description**:\n
+ * The unsigned lower 32-bit content of Rs1 is added with the unsigned lower 32-bit
+ * content of Rs2. And the result is saturated to the 32-bit unsigned integer range of [0, 2^32-1] and then
+ * sign-extended and written to Rd. If saturation happens, this instruction sets the OV flag.
+ *
+ * **Operations**:\n
+ * ~~~
+ * tmp = Rs1.W[0] + Rs2.W[0];
+ * if (tmp > (2^32)-1) {
+ *   tmp[31:0] = (2^32)-1;
+ *   OV = 1;
+ * }
+ * Rd = tmp[31:0]; // RV32
+ * Rd = SE(tmp[31:0]); // RV64
+ * ~~~
+ *
+ * \param [in]  a    unsigned int type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_UKADDW(unsigned int a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("ukaddw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.153. UKADDW ===== */
+
+/* ===== Inline Function Start for 3.154. UKCRAS16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief UKCRAS16 (SIMD 16-bit Unsigned Saturating Cross Addition & Subtraction)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UKCRAS16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do one 16-bit unsigned integer element saturating addition and one 16-bit unsigned
+ * integer element saturating subtraction in a 32-bit chunk simultaneously. Operands are from crossed
+ * positions in 32-bit chunks.
+ *
+ * **Description**:\n
+ * This instruction adds the 16-bit unsigned integer element in [31:16] of 32-bit chunks in
+ * Rs1 with the 16-bit unsigned integer element in [15:0] of 32-bit chunks in Rs2; at the same time, it
+ * subtracts the 16-bit unsigned integer element in [31:16] of 32-bit chunks in Rs2 from the 16-bit
+ * unsigned integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the 16-bit
+ * unsigned number range (0 <= RES <= 2^16-1), they are saturated to the range and the OV bit is set to 1.
+ * The saturated results are written to [31:16] of 32-bit chunks in Rd for addition and [15:0] of 32-bit
+ * chunks in Rd for subtraction.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res1 = Rs1.W[x][31:16] + Rs2.W[x][15:0];
+ * res2 = Rs1.W[x][15:0] - Rs2.W[x][31:16];
+ * if (res1 > (2^16)-1) {
+ *   res1 = (2^16)-1;
+ *   OV = 1;
+ * }
+ * if (res2 < 0) {
+ *   res2 = 0;
+ *   OV = 1;
+ * }
+ * Rd.W[x][31:16] = res1;
+ * Rd.W[x][15:0] = res2;
+ * for RV32, x=0
+ * for RV64, x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_UKCRAS16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("ukcras16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.154. UKCRAS16 ===== */
+
+/* ===== Inline Function Start for 3.155. UKCRSA16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief UKCRSA16 (SIMD 16-bit Unsigned Saturating Cross Subtraction & Addition)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UKCRSA16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do one 16-bit unsigned integer element saturating subtraction and one 16-bit unsigned
+ * integer element saturating addition in a 32-bit chunk simultaneously. Operands are from crossed
+ * positions in 32-bit chunks.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 16-bit unsigned integer element in [15:0] of 32-bit
+ * chunks in Rs2 from the 16-bit unsigned integer element in [31:16] of 32-bit chunks in Rs1; at the
+ * same time, it adds the 16-bit unsigned integer element in [31:16] of 32-bit chunks in Rs2 with the 16-
+ * bit unsigned integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the
+ * 16-bit unsigned number range (0 <= RES <= 2^16-1), they are saturated to the range and the OV bit is set
+ * to 1. The saturated results are written to [31:16] of 32-bit chunks in Rd for subtraction and [15:0] of
+ * 32-bit chunks in Rd for addition.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res1 = Rs1.W[x][31:16] - Rs2.W[x][15:0];
+ * res2 = Rs1.W[x][15:0] + Rs2.W[x][31:16];
+ * if (res1 < 0) {
+ *   res1 = 0;
+ *   OV = 1;
+ * } else if (res2 > (2^16)-1) {
+ *   res2 = (2^16)-1;
+ *   OV = 1;
+ * }
+ * Rd.W[x][31:16] = res1;
+ * Rd.W[x][15:0] = res2;
+ * for RV32, x=0
+ * for RV64, x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_UKCRSA16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("ukcrsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.155. UKCRSA16 ===== */
+
+/* ===== Inline Function Start for 3.156. UKMAR64 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB
+ * \brief UKMAR64 (Unsigned Multiply and Saturating Add to 64-Bit Data)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UKMAR64 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the 32-bit unsigned elements in two registers and add the 64-bit multiplication
+ * results to the 64-bit unsigned data of a pair of registers (RV32) or a register (RV64). The result is
+ * saturated to the U64 range and written back to the pair of registers (RV32) or the register (RV64).
+ *
+ * **RV32 Description**:\n
+ * This instruction multiplies the 32-bit unsigned data of Rs1 with that of Rs2. It
+ * adds the 64-bit multiplication result to the 64-bit unsigned data of an even/odd pair of registers
+ * specified by Rd(4,1) with unlimited precision. If the 64-bit addition result is beyond the U64 number
+ * range (0 <= U64 <= 2^64-1), it is saturated to the range and the OV bit is set to 1. The saturated result is
+ * written back to the even/odd pair of registers specified by Rd(4,1).
+ * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
+ * of the pair contains the low 32-bit of the result.
+ *
+ * **RV64 Description**:\n
+ * This instruction multiplies the 32-bit unsigned elements of Rs1 with that of Rs2.
+ * It adds the 64-bit multiplication results to the 64-bit unsigned data in Rd with unlimited precision. If
+ * the 64-bit addition result is beyond the U64 number range (0 <= U64 <= 2^64-1), it is saturated to the
+ * range and the OV bit is set to 1. The saturated result is written back to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
+ * result = R[t_H].R[t_L] + (Rs1 * Rs2);
+ * if (result > (2^64)-1) {
+ *   result = (2^64)-1; OV = 1;
+ * }
+ * R[t_H].R[t_L] = result;
+ * * RV64:
+ * // `result` has unlimited precision
+ * result = Rd + (Rs1.W[0] u* Rs2.W[0]) + (Rs1.W[1] u* Rs2.W[1]);
+ * if (result > (2^64)-1) {
+ *   result = (2^64)-1; OV = 1;
+ * }
+ * Rd = result;
+ * ~~~
+ *
+ * \param [in]  t    unsigned long long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long long type
+ */
+__STATIC_FORCEINLINE unsigned long long __RV_UKMAR64(unsigned long long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("ukmar64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.156. UKMAR64 ===== */
+
+/* ===== Inline Function Start for 3.157. UKMSR64 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB
+ * \brief UKMSR64 (Unsigned Multiply and Saturating Subtract from 64-Bit Data)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UKMSR64 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the 32-bit unsigned elements in two registers and subtract the 64-bit
+ * multiplication results from the 64-bit unsigned data of a pair of registers (RV32) or a register (RV64).
+ * The result is saturated to the U64 range and written back to the pair of registers (RV32) or a register
+ * (RV64).
+ *
+ * **RV32 Description**:\n
+ * This instruction multiplies the 32-bit unsigned data of Rs1 with that of Rs2. It
+ * subtracts the 64-bit multiplication result from the 64-bit unsigned data of an even/odd pair of
+ * registers specified by Rd(4,1) with unlimited precision. If the 64-bit subtraction result is beyond the
+ * U64 number range (0 <= U64 <= 2^64-1), it is saturated to the range and the OV bit is set to 1. The
+ * saturated result is written back to the even/odd pair of registers specified by Rd(4,1).
+ * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
+ * of the pair contains the low 32-bit of the result.
+ *
+ * **RV64 Description**:\n
+ * This instruction multiplies the 32-bit unsigned elements of Rs1 with that of Rs2.
+ * It subtracts the 64-bit multiplication results from the 64-bit unsigned data of Rd with unlimited
+ * precision. If the 64-bit subtraction result is beyond the U64 number range (0 <= U64 <= 2^64-1), it is
+ * saturated to the range and the OV bit is set to 1. The saturated result is written back to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
+ * result = R[t_H].R[t_L] - (Rs1 u* Rs2);
+ * if (result < 0) {
+ *   result = 0; OV = 1;
+ * }
+ * R[t_H].R[t_L] = result;
+ * * RV64:
+ * // `result` has unlimited precision
+ * result = Rd - (Rs1.W[0] u* Rs2.W[0]) - (Rs1.W[1] u* Rs2.W[1]);
+ * if (result < 0) {
+ *   result = 0; OV = 1;
+ * }
+ * Rd = result;
+ * ~~~
+ *
+ * \param [in]  t    unsigned long long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long long type
+ */
+__STATIC_FORCEINLINE unsigned long long __RV_UKMSR64(unsigned long long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("ukmsr64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.157. UKMSR64 ===== */
+
+/* ===== Inline Function Start for 3.158. UKSTAS16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief UKSTAS16 (SIMD 16-bit Unsigned Saturating Straight Addition & Subtraction)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UKSTAS16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do one 16-bit unsigned integer element saturating addition and one 16-bit unsigned
+ * integer element saturating subtraction in a 32-bit chunk simultaneously. Operands are from
+ * corresponding positions in 32-bit chunks.
+ *
+ * **Description**:\n
+ * This instruction adds the 16-bit unsigned integer element in [31:16] of 32-bit chunks in
+ * Rs1 with the 16-bit unsigned integer element in [31:16] of 32-bit chunks in Rs2; at the same time, it
+ * subtracts the 16-bit unsigned integer element in [15:0] of 32-bit chunks in Rs2 from the 16-bit
+ * unsigned integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the 16-bit
+ * unsigned number range (0 <= RES <= 2^16-1), they are saturated to the range and the OV bit is set to 1.
+ * The saturated results are written to [31:16] of 32-bit chunks in Rd for addition and [15:0] of 32-bit
+ * chunks in Rd for subtraction.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res1 = Rs1.W[x][31:16] + Rs2.W[x][31:16];
+ * res2 = Rs1.W[x][15:0] - Rs2.W[x][15:0];
+ * if (res1 > (2^16)-1) {
+ *   res1 = (2^16)-1;
+ *   OV = 1;
+ * }
+ * if (res2 < 0) {
+ *   res2 = 0;
+ *   OV = 1;
+ * }
+ * Rd.W[x][31:16] = res1;
+ * Rd.W[x][15:0] = res2;
+ * for RV32, x=0
+ * for RV64, x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_UKSTAS16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("ukstas16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.158. UKSTAS16 ===== */
+
+/* ===== Inline Function Start for 3.159. UKSTSA16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief UKSTSA16 (SIMD 16-bit Unsigned Saturating Straight Subtraction & Addition)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UKSTSA16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do one 16-bit unsigned integer element saturating subtraction and one 16-bit unsigned
+ * integer element saturating addition in a 32-bit chunk simultaneously. Operands are from
+ * corresponding positions in 32-bit chunks.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 16-bit unsigned integer element in [31:16] of 32-bit
+ * chunks in Rs2 from the 16-bit unsigned integer element in [31:16] of 32-bit chunks in Rs1; at the
+ * same time, it adds the 16-bit unsigned integer element in [15:0] of 32-bit chunks in Rs2 with the 16-
+ * bit unsigned integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the
+ * 16-bit unsigned number range (0 <= RES <= 2^16-1), they are saturated to the range and the OV bit is set
+ * to 1. The saturated results are written to [31:16] of 32-bit chunks in Rd for subtraction and [15:0] of
+ * 32-bit chunks in Rd for addition.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res1 = Rs1.W[x][31:16] - Rs2.W[x][31:16];
+ * res2 = Rs1.W[x][15:0] + Rs2.W[x][15:0];
+ * if (res1 < 0) {
+ *   res1 = 0;
+ *   OV = 1;
+ * } else if (res2 > (2^16)-1) {
+ *   res2 = (2^16)-1;
+ *   OV = 1;
+ * }
+ * Rd.W[x][31:16] = res1;
+ * Rd.W[x][15:0] = res2;
+ * for RV32, x=0
+ * for RV64, x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_UKSTSA16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("ukstsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.159. UKSTSA16 ===== */
+
+/* ===== Inline Function Start for 3.160. UKSUB8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB
+ * \brief UKSUB8 (SIMD 8-bit Unsigned Saturating Subtraction)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UKSUB8 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit unsigned integer elements saturating subtractions simultaneously.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 8-bit unsigned integer elements in Rs2 from the 8-bit
+ * unsigned integer elements in Rs1. If any of the results are beyond the 8-bit unsigned number range
+ * (0 <= RES <= 28-1), they are saturated to the range and the OV bit is set to 1. The saturated results are
+ * written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[x] = Rs1.B[x] - Rs2.B[x];
+ * if (res[x] < 0) {
+ *   res[x] = 0;
+ *   OV = 1;
+ * }
+ * Rd.B[x] = res[x];
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_UKSUB8(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("uksub8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.160. UKSUB8 ===== */
+
+/* ===== Inline Function Start for 3.161. UKSUB16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief UKSUB16 (SIMD 16-bit Unsigned Saturating Subtraction)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UKSUB16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit unsigned integer elements saturating subtractions simultaneously.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 16-bit unsigned integer elements in Rs2 from the 16-bit
+ * unsigned integer elements in Rs1. If any of the results are beyond the 16-bit unsigned number
+ * range (0 <= RES <= 2^16-1), they are saturated to the range and the OV bit is set to 1. The saturated
+ * results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[x] = Rs1.H[x] - Rs2.H[x];
+ * if (res[x] < 0) {
+ *   res[x] = 0;
+ *   OV = 1;
+ * }
+ * Rd.H[x] = res[x];
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_UKSUB16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("uksub16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.161. UKSUB16 ===== */
+
+/* ===== Inline Function Start for 3.162. UKSUB64 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB
+ * \brief UKSUB64 (64-bit Unsigned Saturating Subtraction)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UKSUB64 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Perform a 64-bit signed integer subtraction. The result is saturated to the U64 range.
+ *
+ * **RV32 Description**:\n
+ * This instruction subtracts the 64-bit unsigned integer of an even/odd pair of
+ * registers specified by Rs2(4,1) from the 64-bit unsigned integer of an even/odd pair of registers
+ * specified by Rs1(4,1). If the 64-bit result is beyond the U64 number range (0 <= U64 <= 2^64-1), it is
+ * saturated to the range and the OV bit is set to 1. The saturated result is then written to an even/odd
+ * pair of registers specified by Rd(4,1).
+ * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d`
+ * register of the pair contains the low 32-bit of the operand.
+ *
+ * **RV64 Description**:\n
+ * This instruction subtracts the 64-bit unsigned integer of Rs2 from the 64-bit
+ * unsigned integer of an even/odd pair of Rs1. If the 64-bit result is beyond the U64 number range (0 <=
+ * U64 <= 2^64-1), it is saturated to the range and the OV bit is set to 1. The saturated result is then written
+ * to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
+ * a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1);
+ * b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1);
+ * result = R[a_H].R[a_L] - R[b_H].R[b_L];
+ * if (result < 0) {
+ *   result = 0; OV = 1;
+ * }
+ * R[t_H].R[t_L] = result;
+ * * RV64
+ * result = Rs1 - Rs2;
+ * if (result < 0) {
+ *   result = 0; OV = 1;
+ * }
+ * Rd = result;
+ * ~~~
+ *
+ * \param [in]  a    unsigned long long type of value stored in a
+ * \param [in]  b    unsigned long long type of value stored in b
+ * \return value stored in unsigned long long type
+ */
+__STATIC_FORCEINLINE unsigned long long __RV_UKSUB64(unsigned long long a, unsigned long long b)
+{
+    register unsigned long long result;
+    __ASM volatile("uksub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.162. UKSUB64 ===== */
+
+/* ===== Inline Function Start for 3.163. UKSUBH ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU
+ * \brief UKSUBH (Unsigned Subtraction with U16 Saturation)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UKSUBH Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Subtract the unsigned lower 32-bit content of two registers with U16 saturation.
+ *
+ * **Description**:\n
+ * The unsigned lower 32-bit content of Rs2 is subtracted from the unsigned lower 32-bit
+ * content of Rs1. And the result is saturated to the 16-bit unsigned integer range of [0, 2^16-1] and then
+ * sign-extended and written to Rd. If saturation happens, this instruction sets the OV flag.
+ *
+ * **Operations**:\n
+ * ~~~
+ * tmp = Rs1.W[0] - Rs2.W[0];
+ * if (tmp > (2^16)-1) {
+ *   tmp = (2^16)-1;
+ *   OV = 1;
+ * }
+ * else if (tmp < 0) {
+ *   tmp = 0;
+ *   OV = 1;
+ * }
+ * Rd = SE(tmp[15:0]);
+ * ~~~
+ *
+ * \param [in]  a    unsigned int type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_UKSUBH(unsigned int a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("uksubh %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.163. UKSUBH ===== */
+
+/* ===== Inline Function Start for 3.164. UKSUBW ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
+ * \brief UKSUBW (Unsigned Subtraction with U32 Saturation)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UKSUBW Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Subtract the unsigned lower 32-bit content of two registers with unsigned 32-bit
+ * saturation.
+ *
+ * **Description**:\n
+ * The unsigned lower 32-bit content of Rs2 is subtracted from the unsigned lower 32-bit
+ * content of Rs1. And the result is saturated to the 32-bit unsigned integer range of [0, 2^32-1] and then
+ * sign-extended and written to Rd. If saturation happens, this instruction sets the OV flag.
+ *
+ * **Operations**:\n
+ * ~~~
+ * tmp = Rs1.W[0] - Rs2.W[0];
+ * if (tmp < 0) {
+ *   tmp[31:0] = 0;
+ *   OV = 1;
+ * }
+ * Rd = tmp[31:0]; // RV32
+ * Rd = SE(tmp[31:0]); // RV64
+ * ~~~
+ *
+ * \param [in]  a    unsigned int type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_UKSUBW(unsigned int a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("uksubw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.164. UKSUBW ===== */
+
+/* ===== Inline Function Start for 3.165. UMAR64 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB
+ * \brief UMAR64 (Unsigned Multiply and Add to 64-Bit Data)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UMAR64 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the 32-bit unsigned elements in two registers and add the 64-bit multiplication
+ * results to the 64-bit unsigned data of a pair of registers (RV32) or a register (RV64). The result is
+ * written back to the pair of registers (RV32) or a register (RV64).
+ *
+ * **RV32 Description**:\n
+ * This instruction multiplies the 32-bit unsigned data of Rs1 with that of Rs2. It
+ * adds the 64-bit multiplication result to the 64-bit unsigned data of an even/odd pair of registers
+ * specified by Rd(4,1). The addition result is written back to the even/odd pair of registers specified by
+ * Rd(4,1).
+ * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
+ * of the pair contains the low 32-bit of the result.
+ *
+ * **RV64 Description**:\n
+ * This instruction multiplies the 32-bit unsigned elements of Rs1 with that of Rs2.
+ * It adds the 64-bit multiplication results to the 64-bit unsigned data of Rd. The addition result is
+ * written back to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
+ * R[t_H].R[t_L] = R[t_H].R[t_L] + (Rs1 * Rs2);
+ * * RV64:
+ * Rd = Rd + (Rs1.W[0] u* Rs2.W[0]) + (Rs1.W[1] u* Rs2.W[1]);
+ * ~~~
+ *
+ * \param [in]  t    unsigned long long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long long type
+ */
+__STATIC_FORCEINLINE unsigned long long __RV_UMAR64(unsigned long long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("umar64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.165. UMAR64 ===== */
+
+/* ===== Inline Function Start for 3.166. UMAQA ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_8B_MULT_32B_ADD
+ * \brief UMAQA (Unsigned Multiply Four Bytes with 32- bit Adds)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UMAQA Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do four unsigned 8-bit multiplications from 32-bit chunks of two registers; and then adds
+ * the four 16-bit results and the content of corresponding 32-bit chunks of a third register together.
+ *
+ * **Description**:\n
+ * This instruction multiplies the four unsigned 8-bit elements of 32-bit chunks of Rs1 with the four
+ * unsigned 8-bit elements of 32-bit chunks of Rs2 and then adds the four results together with the
+ * unsigned content of the corresponding 32-bit chunks of Rd. The final results are written back to the
+ * corresponding 32-bit chunks in Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[x] = Rd.W[x] + (Rs1.W[x].B[3] u* Rs2.W[x].B[3]) +
+ *          (Rs1.W[x].B[2] u* Rs2.W[x].B[2]) + (Rs1.W[x].B[1] u* Rs2.W[x].B[1]) +
+ *          (Rs1.W[x].B[0] u* Rs2.W[x].B[0]);
+ * Rd.W[x] = res[x];
+ * for RV32: x=0,
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  t    unsigned long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_UMAQA(unsigned long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("umaqa %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 3.166. UMAQA ===== */
+
+/* ===== Inline Function Start for 3.167. UMAX8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC
+ * \brief UMAX8 (SIMD 8-bit Unsigned Maximum)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UMAX8 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit unsigned integer elements finding maximum operations simultaneously.
+ *
+ * **Description**:\n
+ * This instruction compares the 8-bit unsigned integer elements in Rs1 with the four 8-
+ * bit unsigned integer elements in Rs2 and selects the numbers that is greater than the other one. The
+ * two selected results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.B[x] = (Rs1.B[x] >u Rs2.B[x])? Rs1.B[x] : Rs2.B[x];
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_UMAX8(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("umax8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.167. UMAX8 ===== */
+
+/* ===== Inline Function Start for 3.168. UMAX16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC
+ * \brief UMAX16 (SIMD 16-bit Unsigned Maximum)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UMAX16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit unsigned integer elements finding maximum operations simultaneously.
+ *
+ * **Description**:\n
+ * This instruction compares the 16-bit unsigned integer elements in Rs1 with the 16-bit
+ * unsigned integer elements in Rs2 and selects the numbers that is greater than the other one. The
+ * selected results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.H[x] = (Rs1.H[x] >u Rs2.H[x])? Rs1.H[x] : Rs2.H[x];
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_UMAX16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("umax16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.168. UMAX16 ===== */
+
+/* ===== Inline Function Start for 3.169. UMIN8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC
+ * \brief UMIN8 (SIMD 8-bit Unsigned Minimum)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UMIN8 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit unsigned integer elements finding minimum operations simultaneously.
+ *
+ * **Description**:\n
+ * This instruction compares the 8-bit unsigned integer elements in Rs1 with the 8-bit
+ * unsigned integer elements in Rs2 and selects the numbers that is less than the other one. The
+ * selected results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.B[x] = (Rs1.B[x] > 1;
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_URADD8(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("uradd8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.174. URADD8 ===== */
+
+/* ===== Inline Function Start for 3.175. URADD16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief URADD16 (SIMD 16-bit Unsigned Halving Addition)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * URADD16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit unsigned integer element additions simultaneously. The results are halved to
+ * avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction adds the 16-bit unsigned integer elements in Rs1 with the 16-bit
+ * unsigned integer elements in Rs2. The results are first logically right-shifted by 1 bit and then
+ * written to Rd.
+ *
+ * **Examples**:\n
+ * ~~~
+ * * Ra = 0x7FFF, Rb = 0x7FFF Rt = 0x7FFF
+ * * Ra = 0x8000, Rb = 0x8000 Rt = 0x8000
+ * * Ra = 0x4000, Rb = 0x8000 Rt = 0x6000
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.H[x] = (Rs1.H[x] + Rs2.H[x]) u>> 1;
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_URADD16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("uradd16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.175. URADD16 ===== */
+
+/* ===== Inline Function Start for 3.176. URADD64 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB
+ * \brief URADD64 (64-bit Unsigned Halving Addition)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * URADD64 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Add two 64-bit unsigned integers. The result is halved to avoid overflow or saturation.
+ *
+ * **RV32 Description**:\n
+ * This instruction adds the 64-bit unsigned integer of an even/odd pair of registers
+ * specified by Rs1(4,1) with the 64-bit unsigned integer of an even/odd pair of registers specified by
+ * Rs2(4,1). The 64-bit addition result is first logically right-shifted by 1 bit and then written to an
+ * even/odd pair of registers specified by Rd(4,1).
+ * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
+ * of the pair contains the low 32-bit of the result.
+ *
+ * **RV64 Description**:\n
+ * This instruction adds the 64-bit unsigned integer in Rs1 with the 64-bit unsigned
+ * integer Rs2. The 64-bit addition result is first logically right-shifted by 1 bit and then written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * t_L = CONCAT(Rt(4,1),1'b0); t_H = CONCAT(Rt(4,1),1'b1);
+ * a_L = CONCAT(Ra(4,1),1'b0); a_H = CONCAT(Ra(4,1),1'b1);
+ * b_L = CONCAT(Rb(4,1),1'b0); b_H = CONCAT(Rb(4,1),1'b1);
+ * R[t_H].R[t_L] = (R[a_H].R[a_L] + R[b_H].R[b_L]) u>> 1;
+ * * RV64:
+ * Rd = (Rs1 + Rs2) u>> 1;
+ * ~~~
+ *
+ * \param [in]  a    unsigned long long type of value stored in a
+ * \param [in]  b    unsigned long long type of value stored in b
+ * \return value stored in unsigned long long type
+ */
+__STATIC_FORCEINLINE unsigned long long __RV_URADD64(unsigned long long a, unsigned long long b)
+{
+    register unsigned long long result;
+    __ASM volatile("uradd64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.176. URADD64 ===== */
+
+/* ===== Inline Function Start for 3.177. URADDW ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION
+ * \brief URADDW (32-bit Unsigned Halving Addition)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * URADDW Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Add 32-bit unsigned integers and the results are halved to avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction adds the first 32-bit unsigned integer in Rs1 with the first 32-bit
+ * unsigned integer in Rs2. The result is first logically right-shifted by 1 bit and then sign-extended and
+ * written to Rd.
+ *
+ * **Examples**:\n
+ * ~~~
+ * * Ra = 0x7FFFFFFF, Rb = 0x7FFFFFFF Rt = 0x7FFFFFFF
+ * * Ra = 0x80000000, Rb = 0x80000000 Rt = 0x80000000
+ * * Ra = 0x40000000, Rb = 0x80000000 Rt = 0x60000000
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * Rd[31:0] = (Rs1[31:0] + Rs2[31:0]) u>> 1;
+ * * RV64:
+ * resw[31:0] = (Rs1[31:0] + Rs2[31:0]) u>> 1;
+ * Rd[63:0] = SE(resw[31:0]);
+ * ~~~
+ *
+ * \param [in]  a    unsigned int type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_URADDW(unsigned int a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("uraddw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.177. URADDW ===== */
+
+/* ===== Inline Function Start for 3.178. URCRAS16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief URCRAS16 (SIMD 16-bit Unsigned Halving Cross Addition & Subtraction)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * URCRAS16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit unsigned integer element addition and 16-bit unsigned integer element
+ * subtraction in a 32-bit chunk simultaneously. Operands are from crossed positions in 32-bit chunks.
+ * The results are halved to avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction adds the 16-bit unsigned integer in [31:16] of 32-bit chunks in Rs1
+ * with the 16-bit unsigned integer in [15:0] of 32-bit chunks in Rs2, and subtracts the 16-bit unsigned
+ * integer in [31:16] of 32-bit chunks in Rs2 from the 16-bit unsigned integer in [15:0] of 32-bit chunks
+ * in Rs1. The element results are first logically right-shifted by 1 bit and then written to [31:16] of 32-
+ * bit chunks in Rd and [15:0] of 32-bit chunks in Rd.
+ *
+ * **Examples**:\n
+ * ~~~
+ * Please see `URADD16` and `URSUB16` instructions.
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x][31:16] = (Rs1.W[x][31:16] + Rs2.W[x][15:0]) u>> 1;
+ * Rd.W[x][15:0] = (Rs1.W[x][15:0] - Rs2.W[x][31:16]) u>> 1;
+ * for RV32, x=0
+ * for RV64, x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_URCRAS16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("urcras16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.178. URCRAS16 ===== */
+
+/* ===== Inline Function Start for 3.179. URCRSA16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief URCRSA16 (SIMD 16-bit Unsigned Halving Cross Subtraction & Addition)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * URCRSA16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit unsigned integer element subtraction and 16-bit unsigned integer element
+ * addition in a 32-bit chunk simultaneously. Operands are from crossed positions in 32-bit chunks.
+ * The results are halved to avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 16-bit unsigned integer in [15:0] of 32-bit chunks in Rs2
+ * from the 16-bit unsigned integer in [31:16] of 32-bit chunks in Rs1, and adds the 16-bit unsigned
+ * integer in [15:0] of 32-bit chunks in Rs1 with the 16-bit unsigned integer in [31:16] of 32-bit chunks
+ * in Rs2. The two results are first logically right-shifted by 1 bit and then written to [31:16] of 32-bit
+ * chunks in Rd and [15:0] of 32-bit chunks in Rd.
+ *
+ * **Examples**:\n
+ * ~~~
+ * Please see `URADD16` and `URSUB16` instructions.
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x][31:16] = (Rs1.W[x][31:16] - Rs2.W[x][15:0]) u>> 1;
+ * Rd.W[x][15:0] = (Rs1.W[x][15:0] + Rs2.W[x][31:16]) u>> 1;
+ * for RV32, x=0
+ * for RV64, x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_URCRSA16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("urcrsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.179. URCRSA16 ===== */
+
+/* ===== Inline Function Start for 3.180. URSTAS16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief URSTAS16 (SIMD 16-bit Unsigned Halving Straight Addition & Subtraction)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * URSTAS16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit unsigned integer element addition and 16-bit unsigned integer element
+ * subtraction in a 32-bit chunk simultaneously. Operands are from corresponding positions in 32-bit
+ * chunks. The results are halved to avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction adds the 16-bit unsigned integer in [31:16] of 32-bit chunks in Rs1
+ * with the 16-bit unsigned integer in [31:16] of 32-bit chunks in Rs2, and subtracts the 16-bit unsigned
+ * integer in [15:0] of 32-bit chunks in Rs2 from the 16-bit unsigned integer in [15:0] of 32-bit chunks
+ * in Rs1. The element results are first logically right-shifted by 1 bit and then written to [31:16] of 32-
+ * bit chunks in Rd and [15:0] of 32-bit chunks in Rd.
+ *
+ * **Examples**:\n
+ * ~~~
+ * Please see `URADD16` and `URSUB16` instructions.
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x][31:16] = (Rs1.W[x][31:16] + Rs2.W[x][31:16]) u>> 1;
+ * Rd.W[x][15:0] = (Rs1.W[x][15:0] - Rs2.W[x][15:0]) u>> 1;
+ * for RV32, x=0
+ * for RV64, x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_URSTAS16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("urstas16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.180. URSTAS16 ===== */
+
+/* ===== Inline Function Start for 3.181. URSTSA16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief URSTSA16 (SIMD 16-bit Unsigned Halving Straight Subtraction & Addition)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * URCRSA16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit unsigned integer element subtraction and 16-bit unsigned integer element
+ * addition in a 32-bit chunk simultaneously. Operands are from corresponding positions in 32-bit
+ * chunks. The results are halved to avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 16-bit unsigned integer in [31:16] of 32-bit chunks in Rs2
+ * from the 16-bit unsigned integer in [31:16] of 32-bit chunks in Rs1, and adds the 16-bit unsigned
+ * integer in [15:0] of 32-bit chunks in Rs1 with the 16-bit unsigned integer in [15:0] of 32-bit chunks in
+ * Rs2. The two results are first logically right-shifted by 1 bit and then written to [31:16] of 32-bit
+ * chunks in Rd and [15:0] of 32-bit chunks in Rd.
+ *
+ * **Examples**:\n
+ * ~~~
+ * Please see `URADD16` and `URSUB16` instructions.
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x][31:16] = (Rs1.W[x][31:16] - Rs2.W[x][31:16]) u>> 1;
+ * Rd.W[x][15:0] = (Rs1.W[x][15:0] + Rs2.W[x][15:0]) u>> 1;
+ * for RV32, x=0
+ * for RV64, x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_URSTSA16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("urstsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.181. URSTSA16 ===== */
+
+/* ===== Inline Function Start for 3.182. URSUB8 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB
+ * \brief URSUB8 (SIMD 8-bit Unsigned Halving Subtraction)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * URSUB8 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit unsigned integer element subtractions simultaneously. The results are halved to
+ * avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 8-bit unsigned integer elements in Rs2 from the 8-bit
+ * unsigned integer elements in Rs1. The results are first logically right-shifted by 1 bit and then
+ * written to Rd.
+ *
+ * **Examples**:\n
+ * ~~~
+ * * Ra = 0x7F, Rb = 0x80 Rt = 0xFF
+ * * Ra = 0x80, Rb = 0x7F Rt = 0x00
+ * * Ra = 0x80, Rb = 0x40 Rt = 0x20
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.B[x] = (Rs1.B[x] - Rs2.B[x]) u>> 1;
+ * for RV32: x=3...0,
+ * for RV64: x=7...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_URSUB8(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("ursub8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.182. URSUB8 ===== */
+
+/* ===== Inline Function Start for 3.183. URSUB16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
+ * \brief URSUB16 (SIMD 16-bit Unsigned Halving Subtraction)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * URSUB16 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit unsigned integer element subtractions simultaneously. The results are halved to
+ * avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 16-bit unsigned integer elements in Rs2 from the 16-bit
+ * unsigned integer elements in Rs1. The results are first logically right-shifted by 1 bit and then
+ * written to Rd.
+ *
+ * **Examples**:\n
+ * ~~~
+ * * Ra = 0x7FFF, Rb = 0x8000 Rt = 0xFFFF
+ * * Ra = 0x8000, Rb = 0x7FFF Rt = 0x0000
+ * * Ra = 0x8000, Rb = 0x4000 Rt = 0x2000
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.H[x] = (Rs1.H[x] - Rs2.H[x]) u>> 1;
+ * for RV32: x=1...0,
+ * for RV64: x=3...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_URSUB16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("ursub16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.183. URSUB16 ===== */
+
+/* ===== Inline Function Start for 3.184. URSUB64 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB
+ * \brief URSUB64 (64-bit Unsigned Halving Subtraction)
+ * \details
+ * **Type**: DSP (64-bit Profile)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * URSUB64 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Perform a 64-bit unsigned integer subtraction. The result is halved to avoid overflow or
+ * saturation.
+ *
+ * **RV32 Description**:\n
+ * This instruction subtracts the 64-bit unsigned integer of an even/odd pair of
+ * registers specified by Rs2(4,1) from the 64-bit unsigned integer of an even/odd pair of registers
+ * specified by Rs1(4,1). The subtraction result is first logically right-shifted by 1 bit and then written
+ * to an even/odd pair of registers specified by Rd(4,1).
+ * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
+ * includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
+ * of the pair contains the low 32-bit of the result.
+ *
+ * **RV64 Description**:\n
+ * This instruction subtracts the 64-bit unsigned integer in Rs2 from the 64-bit
+ * unsigned integer in Rs1. The subtraction result is first logically right-shifted by 1 bit and then
+ * written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * t_L = CONCAT(Rt(4,1),1'b0); t_H = CONCAT(Rt(4,1),1'b1);
+ * a_L = CONCAT(Ra(4,1),1'b0); a_H = CONCAT(Ra(4,1),1'b1);
+ * b_L = CONCAT(Rb(4,1),1'b0); b_H = CONCAT(Rb(4,1),1'b1);
+ * R[t_H].R[t_L] = (R[a_H].R[a_L] - R[b_H].R[b_L]) u>> 1;
+ * * RV64:
+ * Rd = (Rs1 - Rs2) u>> 1;
+ * ~~~
+ *
+ * \param [in]  a    unsigned long long type of value stored in a
+ * \param [in]  b    unsigned long long type of value stored in b
+ * \return value stored in unsigned long long type
+ */
+__STATIC_FORCEINLINE unsigned long long __RV_URSUB64(unsigned long long a, unsigned long long b)
+{
+    register unsigned long long result;
+    __ASM volatile("ursub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.184. URSUB64 ===== */
+
+/* ===== Inline Function Start for 3.185. URSUBW ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION
+ * \brief URSUBW (32-bit Unsigned Halving Subtraction)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * URSUBW Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Subtract 32-bit unsigned integers and the result is halved to avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction subtracts the first 32-bit signed integer in Rs2 from the first 32-bit
+ * signed integer in Rs1. The result is first logically right-shifted by 1 bit and then sign-extended and
+ * written to Rd.
+ *
+ * **Examples**:\n
+ * ~~~
+ * * Ra = 0x7FFFFFFF, Rb = 0x80000000 Rt = 0xFFFFFFFF
+ * * Ra = 0x80000000, Rb = 0x7FFFFFFF Rt = 0x00000000
+ * * Ra = 0x80000000, Rb = 0x40000000 Rt = 0x20000000
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * Rd[31:0] = (Rs1[31:0] - Rs2[31:0]) u>> 1;
+ * * RV64:
+ * resw[31:0] = (Rs1[31:0] - Rs2[31:0]) u>> 1;
+ * Rd[63:0] = SE(resw[31:0]);
+ * ~~~
+ *
+ * \param [in]  a    unsigned int type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_URSUBW(unsigned int a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("ursubw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.185. URSUBW ===== */
+
+/* ===== Inline Function Start for 3.186. WEXTI ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
+ * \brief WEXTI (Extract Word from 64-bit Immediate)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * WEXTI Rd, Rs1, #LSBloc
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Extract a 32-bit word from a 64-bit value stored in an even/odd pair of registers (RV32) or
+ * a register (RV64) starting from a specified immediate LSB bit position.
+ *
+ * **RV32 Description**:\n
+ * This instruction extracts a 32-bit word from a 64-bit value of an even/odd pair of registers specified
+ * by Rs1(4,1) starting from a specified immediate LSB bit position, #LSBloc. The extracted word is
+ * written to Rd.
+ * Rs1(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register
+ * pair includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the 64-bit value and the even `2d`
+ * register of the pair contains the low 32-bit of the 64-bit value.
+ *
+ * **RV64 Description**:\n
+ * This instruction extracts a 32-bit word from a 64-bit value in Rs1 starting from a specified
+ * immediate LSB bit position, #LSBloc. The extracted word is sign-extended and written to lower 32-
+ * bit of Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * Idx0 = CONCAT(Rs1(4,1),1'b0); Idx1 = CONCAT(Rs2(4,1),1'b1);
+ * src[63:0] = Concat(R[Idx1], R[Idx0]);
+ * Rd = src[31+LSBloc:LSBloc];
+ * * RV64:
+ * ExtractW = Rs1[31+LSBloc:LSBloc];
+ * Rd = SE(ExtractW)
+ * ~~~
+ *
+ * \param [in]  a    long long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+#define __RV_WEXTI(a, b)    \
+    ({    \
+        register unsigned long result;    \
+        register long long __a = (long long)(a);    \
+        __ASM volatile("wexti %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
+        result;    \
+    })
+/* ===== Inline Function End for 3.186. WEXTI ===== */
+
+/* ===== Inline Function Start for 3.187. WEXT ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
+ * \brief WEXT (Extract Word from 64-bit)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * WEXT Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Extract a 32-bit word from a 64-bit value stored in an even/odd pair of registers (RV32) or
+ * a register (RV64) starting from a specified LSB bit position in a register.
+ *
+ * **RV32 Description**:\n
+ * This instruction extracts a 32-bit word from a 64-bit value of an even/odd pair of registers specified
+ * by Rs1(4,1) starting from a specified LSB bit position, specified in Rs2[4:0]. The extracted word is
+ * written to Rd.
+ * Rs1(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register
+ * pair includes register 2d and 2d+1.
+ * The odd `2d+1` register of the pair contains the high 32-bit of the 64-bit value and the even `2d`
+ * register of the pair contains the low 32-bit of the 64-bit value.
+ *
+ * **Operations**:\n
+ * ~~~
+ * * RV32:
+ * Idx0 = CONCAT(Rs1(4,1),1'b0); Idx1 = CONCAT(Rs1(4,1),1'b1);
+ * src[63:0] = Concat(R[Idx1], R[Idx0]);
+ * LSBloc = Rs2[4:0];
+ * Rd = src[31+LSBloc:LSBloc];
+ * * RV64:
+ * LSBloc = Rs2[4:0];
+ * ExtractW = Rs1[31+LSBloc:LSBloc];
+ * Rd = SE(ExtractW)
+ * ~~~
+ *
+ * \param [in]  a    long long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_WEXT(long long a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("wext %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 3.187. WEXT ===== */
+
+/* ===== Inline Function Start for 3.188.1. ZUNPKD810 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK
+ * \brief ZUNPKD810 (Unsigned Unpacking Bytes 1 & 0)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * ZUNPKD8xy Rd, Rs1
+ * xy = {10, 20, 30, 31, 32}
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Unpack byte x and byte y of 32-bit chunks in a register into two 16-bit unsigned
+ * halfwords of 32-bit chunks in a register.
+ *
+ * **Description**:\n
+ * For the `ZUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into
+ * two 16-bit unsigned halfwords and writes the results to the top part and the bottom part of 32-bit
+ * chunks in Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[m].H[1] = ZE16(Rs1.W[m].B[x])
+ * Rd.W[m].H[0] = ZE16(Rs1.W[m].B[y])
+ * // ZUNPKD810, x=1,y=0
+ * // ZUNPKD820, x=2,y=0
+ * // ZUNPKD830, x=3,y=0
+ * // ZUNPKD831, x=3,y=1
+ * // ZUNPKD832, x=3,y=2
+ * for RV32: m=0,
+ * for RV64: m=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_ZUNPKD810(unsigned long a)
+{
+    register unsigned long result;
+    __ASM volatile("zunpkd810 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 3.188.1. ZUNPKD810 ===== */
+
+/* ===== Inline Function Start for 3.188.2. ZUNPKD820 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK
+ * \brief ZUNPKD820 (Unsigned Unpacking Bytes 2 & 0)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * ZUNPKD8xy Rd, Rs1
+ * xy = {10, 20, 30, 31, 32}
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Unpack byte x and byte y of 32-bit chunks in a register into two 16-bit unsigned
+ * halfwords of 32-bit chunks in a register.
+ *
+ * **Description**:\n
+ * For the `ZUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into
+ * two 16-bit unsigned halfwords and writes the results to the top part and the bottom part of 32-bit
+ * chunks in Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[m].H[1] = ZE16(Rs1.W[m].B[x])
+ * Rd.W[m].H[0] = ZE16(Rs1.W[m].B[y])
+ * // ZUNPKD810, x=1,y=0
+ * // ZUNPKD820, x=2,y=0
+ * // ZUNPKD830, x=3,y=0
+ * // ZUNPKD831, x=3,y=1
+ * // ZUNPKD832, x=3,y=2
+ * for RV32: m=0,
+ * for RV64: m=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_ZUNPKD820(unsigned long a)
+{
+    register unsigned long result;
+    __ASM volatile("zunpkd820 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 3.188.2. ZUNPKD820 ===== */
+
+/* ===== Inline Function Start for 3.188.3. ZUNPKD830 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK
+ * \brief ZUNPKD830 (Unsigned Unpacking Bytes 3 & 0)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * ZUNPKD8xy Rd, Rs1
+ * xy = {10, 20, 30, 31, 32}
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Unpack byte x and byte y of 32-bit chunks in a register into two 16-bit unsigned
+ * halfwords of 32-bit chunks in a register.
+ *
+ * **Description**:\n
+ * For the `ZUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into
+ * two 16-bit unsigned halfwords and writes the results to the top part and the bottom part of 32-bit
+ * chunks in Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[m].H[1] = ZE16(Rs1.W[m].B[x])
+ * Rd.W[m].H[0] = ZE16(Rs1.W[m].B[y])
+ * // ZUNPKD810, x=1,y=0
+ * // ZUNPKD820, x=2,y=0
+ * // ZUNPKD830, x=3,y=0
+ * // ZUNPKD831, x=3,y=1
+ * // ZUNPKD832, x=3,y=2
+ * for RV32: m=0,
+ * for RV64: m=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_ZUNPKD830(unsigned long a)
+{
+    register unsigned long result;
+    __ASM volatile("zunpkd830 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 3.188.3. ZUNPKD830 ===== */
+
+/* ===== Inline Function Start for 3.188.4. ZUNPKD831 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK
+ * \brief ZUNPKD831 (Unsigned Unpacking Bytes 3 & 1)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * ZUNPKD8xy Rd, Rs1
+ * xy = {10, 20, 30, 31, 32}
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Unpack byte x and byte y of 32-bit chunks in a register into two 16-bit unsigned
+ * halfwords of 32-bit chunks in a register.
+ *
+ * **Description**:\n
+ * For the `ZUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into
+ * two 16-bit unsigned halfwords and writes the results to the top part and the bottom part of 32-bit
+ * chunks in Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[m].H[1] = ZE16(Rs1.W[m].B[x])
+ * Rd.W[m].H[0] = ZE16(Rs1.W[m].B[y])
+ * // ZUNPKD810, x=1,y=0
+ * // ZUNPKD820, x=2,y=0
+ * // ZUNPKD830, x=3,y=0
+ * // ZUNPKD831, x=3,y=1
+ * // ZUNPKD832, x=3,y=2
+ * for RV32: m=0,
+ * for RV64: m=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_ZUNPKD831(unsigned long a)
+{
+    register unsigned long result;
+    __ASM volatile("zunpkd831 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 3.188.4. ZUNPKD831 ===== */
+
+/* ===== Inline Function Start for 3.188.5. ZUNPKD832 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK
+ * \brief ZUNPKD832 (Unsigned Unpacking Bytes 3 & 2)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * ZUNPKD8xy Rd, Rs1
+ * xy = {10, 20, 30, 31, 32}
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Unpack byte x and byte y of 32-bit chunks in a register into two 16-bit unsigned
+ * halfwords of 32-bit chunks in a register.
+ *
+ * **Description**:\n
+ * For the `ZUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into
+ * two 16-bit unsigned halfwords and writes the results to the top part and the bottom part of 32-bit
+ * chunks in Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[m].H[1] = ZE16(Rs1.W[m].B[x])
+ * Rd.W[m].H[0] = ZE16(Rs1.W[m].B[y])
+ * // ZUNPKD810, x=1,y=0
+ * // ZUNPKD820, x=2,y=0
+ * // ZUNPKD830, x=3,y=0
+ * // ZUNPKD831, x=3,y=1
+ * // ZUNPKD832, x=3,y=2
+ * for RV32: m=0,
+ * for RV64: m=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_ZUNPKD832(unsigned long a)
+{
+    register unsigned long result;
+    __ASM volatile("zunpkd832 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 3.188.5. ZUNPKD832 ===== */
+
+#if (__RISCV_XLEN == 64) || defined(__ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__)
+
+/* ===== Inline Function Start for 4.1. ADD32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief ADD32 (SIMD 32-bit Addition)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * ADD32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit integer element additions simultaneously.
+ *
+ * **Description**:\n
+ * This instruction adds the 32-bit integer elements in Rs1 with the 32-bit integer
+ * elements in Rs2, and then writes the 32-bit element results to Rd.
+ *
+ * **Note**:\n
+ * This instruction can be used for either signed or unsigned addition.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x] = Rs1.W[x] + Rs2.W[x];
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_ADD32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("add32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.1. ADD32 ===== */
+
+/* ===== Inline Function Start for 4.2. CRAS32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief CRAS32 (SIMD 32-bit Cross Addition & Subtraction)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * CRAS32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit integer element addition and 32-bit integer element subtraction in a 64-bit
+ * chunk simultaneously. Operands are from crossed 32-bit elements.
+ *
+ * **Description**:\n
+ * This instruction adds the 32-bit integer element in [63:32] of Rs1 with the 32-bit
+ * integer element in [31:0] of Rs2, and writes the result to [63:32] of Rd; at the same time, it subtracts
+ * the 32-bit integer element in [63:32] of Rs2 from the 32-bit integer element in [31:0] of Rs1, and
+ * writes the result to [31:0] of Rd.
+ *
+ * **Note**:\n
+ * This instruction can be used for either signed or unsigned operations.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[1] = Rs1.W[1] + Rs2.W[0];
+ * Rd.W[0] = Rs1.W[0] - Rs2.W[1];
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_CRAS32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("cras32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.2. CRAS32 ===== */
+
+/* ===== Inline Function Start for 4.3. CRSA32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief CRSA32 (SIMD 32-bit Cross Subtraction & Addition)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * CRSA32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit integer element subtraction and 32-bit integer element addition in a 64-bit
+ * chunk simultaneously. Operands are from crossed 32-bit elements.
+ * *Description: *
+ * This instruction subtracts the 32-bit integer element in [31:0] of Rs2 from the 32-bit integer element
+ * in [63:32] of Rs1, and writes the result to [63:32] of Rd; at the same time, it adds the 32-bit integer
+ * element in [31:0] of Rs1 with the 32-bit integer element in [63:32] of Rs2, and writes the result to
+ * [31:0] of Rd
+ *
+ * **Note**:\n
+ * This instruction can be used for either signed or unsigned operations.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[1] = Rs1.W[1] - Rs2.W[0];
+ * Rd.W[0] = Rs1.W[0] + Rs2.W[1];
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_CRSA32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("crsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.3. CRSA32 ===== */
+
+/* ===== Inline Function Start for 4.4. KABS32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_MISC
+ * \brief KABS32 (Scalar 32-bit Absolute Value with Saturation)
+ * \details
+ * **Type**: DSP (RV64 Only)
+24    20
+19    15
+14    12
+11    7
+KABS32
+10010
+Rs1
+000
+Rd
+6    0
+GE80B
+1111111
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KABS32 Rd, Rs1
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Get the absolute value of signed 32-bit integer elements in a general register.
+ *
+ * **Description**:\n
+ * This instruction calculates the absolute value of signed 32-bit integer elements stored
+ * in Rs1. The results are written to Rd. This instruction with the minimum negative integer input of
+ * 0x80000000 will produce a saturated output of maximum positive integer of 0x7fffffff and the OV
+ * flag will be set to 1.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if (Rs1.W[x] >= 0) {
+ *   res[x] = Rs1.W[x];
+ * } else {
+ *   If (Rs1.W[x] == 0x80000000) {
+ *     res[x] = 0x7fffffff;
+ *     OV = 1;
+ *   } else {
+ *     res[x] = -Rs1.W[x];
+ *   }
+ * }
+ * Rd.W[x] = res[x];
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KABS32(unsigned long a)
+{
+    register unsigned long result;
+    __ASM volatile("kabs32 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for 4.4. KABS32 ===== */
+
+/* ===== Inline Function Start for 4.5. KADD32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief KADD32 (SIMD 32-bit Signed Saturating Addition)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KADD32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit signed integer element saturating additions simultaneously.
+ *
+ * **Description**:\n
+ * This instruction adds the 32-bit signed integer elements in Rs1 with the 32-bit signed
+ * integer elements in Rs2. If any of the results are beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1),
+ * they are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[x] = Rs1.W[x] + Rs2.W[x];
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KADD32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("kadd32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.5. KADD32 ===== */
+
+/* ===== Inline Function Start for 4.6. KCRAS32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief KCRAS32 (SIMD 32-bit Signed Saturating Cross Addition & Subtraction)
+ * \details
+ * **Type**: SIM (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KCRAS32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit signed integer element saturating addition and 32-bit signed integer element
+ * saturating subtraction in a 64-bit chunk simultaneously. Operands are from crossed 32-bit elements.
+ *
+ * **Description**:\n
+ * This instruction adds the 32-bit integer element in [63:32] of Rs1 with the 32-bit
+ * integer element in [31:0] of Rs2; at the same time, it subtracts the 32-bit integer element in [63:32] of
+ * Rs2 from the 32-bit integer element in [31:0] of Rs1. If any of the results are beyond the Q31 number
+ * range (-2^31 <= Q31 <= 2^31-1), they are saturated to the range and the OV bit is set to 1. The saturated
+ * results are written to [63:32] of Rd for addition and [31:0] of Rd for subtraction.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[1] = Rs1.W[1] + Rs2.W[0];
+ * res[0] = Rs1.W[0] - Rs2.W[1];
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[1] = res[1];
+ * Rd.W[0] = res[0];
+ * for RV64, x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KCRAS32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("kcras32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.6. KCRAS32 ===== */
+
+/* ===== Inline Function Start for 4.7. KCRSA32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief KCRSA32 (SIMD 32-bit Signed Saturating Cross Subtraction & Addition)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KCRSA32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit signed integer element saturating subtraction and 32-bit signed integer element
+ * saturating addition in a 64-bit chunk simultaneously. Operands are from crossed 32-bit elements.
+ * *Description: *
+ * This instruction subtracts the 32-bit integer element in [31:0] of Rs2 from the 32-bit integer element
+ * in [63:32] of Rs1; at the same time, it adds the 32-bit integer element in [31:0] of Rs1 with the 32-bit
+ * integer element in [63:32] of Rs2. If any of the results are beyond the Q31 number range (-2^31 <= Q31
+ * <= 2^31-1), they are saturated to the range and the OV bit is set to 1. The saturated results are written to
+ * [63:32] of Rd for subtraction and [31:0] of Rd for addition.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[1] = Rs1.W[1] - Rs2.W[0];
+ * res[0] = Rs1.W[0] + Rs2.W[1];
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[1] = res[1];
+ * Rd.W[0] = res[0];
+ * for RV64, x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KCRSA32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("kcrsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.7. KCRSA32 ===== */
+
+/* ===== Inline Function Start for 4.8.1. KDMBB16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT
+ * \brief KDMBB16 (SIMD Signed Saturating Double Multiply B16 x B16)
+ * \details
+ * **Type**: SIMD (RV64 only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KDMxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT)
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
+ * of the 32-bit chunks in registers and then double and saturate the Q31 results into the 32-bit chunks
+ * in the destination register. If saturation happens, an overflow flag OV will be set.
+ *
+ * **Description**:\n
+ * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top
+ * or bottom 16-bit Q15 content of the 32-bit portions in Rs2. The Q30 results are then doubled and
+ * saturated into Q31 values. The Q31 values are then written into the 32-bit chunks in Rd. When both
+ * the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated to 0x7FFFFFFF
+ * and the overflow flag OV will be set.
+ *
+ * **Operations**:\n
+ * ~~~
+ * // KDMBB16: (x,y,z)=(0,0,0),(2,2,1)
+ * // KDMBT16: (x,y,z)=(0,1,0),(2,3,1)
+ * // KDMTT16: (x,y,z)=(1,1,0),(3,3,1)
+ * aop[z] = Rs1.H[x]; bop[z] = Rs2.H[y];
+ * If (0x8000 != aop[z] | 0x8000 != bop[z]) {
+ *   Mresult[z] = aop[z] * bop[z];
+ *   resQ31[z] = Mresult[z] << 1;
+ * } else {
+ *   resQ31[z] = 0x7FFFFFFF;
+ *   OV = 1;
+ * }
+ * Rd.W[z] = resQ31[z];
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KDMBB16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("kdmbb16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.8.1. KDMBB16 ===== */
+
+/* ===== Inline Function Start for 4.8.2. KDMBT16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT
+ * \brief KDMBT16 (SIMD Signed Saturating Double Multiply B16 x T16)
+ * \details
+ * **Type**: SIMD (RV64 only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KDMxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT)
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
+ * of the 32-bit chunks in registers and then double and saturate the Q31 results into the 32-bit chunks
+ * in the destination register. If saturation happens, an overflow flag OV will be set.
+ *
+ * **Description**:\n
+ * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top
+ * or bottom 16-bit Q15 content of the 32-bit portions in Rs2. The Q30 results are then doubled and
+ * saturated into Q31 values. The Q31 values are then written into the 32-bit chunks in Rd. When both
+ * the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated to 0x7FFFFFFF
+ * and the overflow flag OV will be set.
+ *
+ * **Operations**:\n
+ * ~~~
+ * // KDMBB16: (x,y,z)=(0,0,0),(2,2,1)
+ * // KDMBT16: (x,y,z)=(0,1,0),(2,3,1)
+ * // KDMTT16: (x,y,z)=(1,1,0),(3,3,1)
+ * aop[z] = Rs1.H[x]; bop[z] = Rs2.H[y];
+ * If (0x8000 != aop[z] | 0x8000 != bop[z]) {
+ *   Mresult[z] = aop[z] * bop[z];
+ *   resQ31[z] = Mresult[z] << 1;
+ * } else {
+ *   resQ31[z] = 0x7FFFFFFF;
+ *   OV = 1;
+ * }
+ * Rd.W[z] = resQ31[z];
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KDMBT16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("kdmbt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.8.2. KDMBT16 ===== */
+
+/* ===== Inline Function Start for 4.8.3. KDMTT16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT
+ * \brief KDMTT16 (SIMD Signed Saturating Double Multiply T16 x T16)
+ * \details
+ * **Type**: SIMD (RV64 only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KDMxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT)
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
+ * of the 32-bit chunks in registers and then double and saturate the Q31 results into the 32-bit chunks
+ * in the destination register. If saturation happens, an overflow flag OV will be set.
+ *
+ * **Description**:\n
+ * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top
+ * or bottom 16-bit Q15 content of the 32-bit portions in Rs2. The Q30 results are then doubled and
+ * saturated into Q31 values. The Q31 values are then written into the 32-bit chunks in Rd. When both
+ * the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated to 0x7FFFFFFF
+ * and the overflow flag OV will be set.
+ *
+ * **Operations**:\n
+ * ~~~
+ * // KDMBB16: (x,y,z)=(0,0,0),(2,2,1)
+ * // KDMBT16: (x,y,z)=(0,1,0),(2,3,1)
+ * // KDMTT16: (x,y,z)=(1,1,0),(3,3,1)
+ * aop[z] = Rs1.H[x]; bop[z] = Rs2.H[y];
+ * If (0x8000 != aop[z] | 0x8000 != bop[z]) {
+ *   Mresult[z] = aop[z] * bop[z];
+ *   resQ31[z] = Mresult[z] << 1;
+ * } else {
+ *   resQ31[z] = 0x7FFFFFFF;
+ *   OV = 1;
+ * }
+ * Rd.W[z] = resQ31[z];
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KDMTT16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("kdmtt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.8.3. KDMTT16 ===== */
+
+/* ===== Inline Function Start for 4.9.1. KDMABB16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT
+ * \brief KDMABB16 (SIMD Signed Saturating Double Multiply Addition B16 x B16)
+ * \details
+ * **Type**: SIMD (RV64 only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KDMAxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT)
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
+ * of the 32-bit chunks in registers and then double and saturate the Q31 results, add the results with
+ * the values of the corresponding 32-bit chunks from the destination register and write the saturated
+ * addition results back into the corresponding 32-bit chunks of the destination register. If saturation
+ * happens, an overflow flag OV will be set.
+ *
+ * **Description**:\n
+ * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top
+ * or bottom 16-bit Q15 content of the corresponding 32-bit portions in Rs2. The Q30 results are then
+ * doubled and saturated into Q31 values. The Q31 values are then added with the content of the
+ * corresponding 32-bit portions of Rd. If the addition results are beyond the Q31 number range (-2^31 <=
+ * Q31 <= 2^31-1), they are saturated to the range and the OV flag is set to 1. The results after saturation
+ * are written back to Rd.
+ * When both the two Q15 inputs are 0x8000, saturation will happen and the overflow flag OV will be
+ * set.
+ *
+ * **Operations**:\n
+ * ~~~
+ * // KDMABB16: (x,y,z)=(0,0,0),(2,2,1)
+ * // KDMABT16: (x,y,z)=(0,1,0),(2,3,1)
+ * // KDMATT16: (x,y,z)=(1,1,0),(3,3,1)
+ * aop[z] = Rs1.H[x]; bop[z] = Rs2.H[y];
+ * If (0x8000 != aop[z] | 0x8000 != bop[z]) {
+ *   Mresult[z] = aop[z] * bop[z];
+ *   resQ31[z] = Mresult[z] << 1;
+ * } else {
+ *   resQ31[z] = 0x7FFFFFFF;
+ *   OV = 1;
+ * }
+ * resadd[z] = Rd.W[z] + resQ31[z];
+ * if (resadd[z] > (2^31)-1) {
+ *   resadd[z] = (2^31)-1;
+ *   OV = 1;
+ * } else if (resadd[z] < -2^31) {
+ *   resadd[z] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[z] = resadd[z];
+ * ~~~
+ *
+ * \param [in]  t    unsigned long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KDMABB16(unsigned long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kdmabb16 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 4.9.1. KDMABB16 ===== */
+
+/* ===== Inline Function Start for 4.9.2. KDMABT16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT
+ * \brief KDMABT16 (SIMD Signed Saturating Double Multiply Addition B16 x T16)
+ * \details
+ * **Type**: SIMD (RV64 only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KDMAxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT)
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
+ * of the 32-bit chunks in registers and then double and saturate the Q31 results, add the results with
+ * the values of the corresponding 32-bit chunks from the destination register and write the saturated
+ * addition results back into the corresponding 32-bit chunks of the destination register. If saturation
+ * happens, an overflow flag OV will be set.
+ *
+ * **Description**:\n
+ * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top
+ * or bottom 16-bit Q15 content of the corresponding 32-bit portions in Rs2. The Q30 results are then
+ * doubled and saturated into Q31 values. The Q31 values are then added with the content of the
+ * corresponding 32-bit portions of Rd. If the addition results are beyond the Q31 number range (-2^31 <=
+ * Q31 <= 2^31-1), they are saturated to the range and the OV flag is set to 1. The results after saturation
+ * are written back to Rd.
+ * When both the two Q15 inputs are 0x8000, saturation will happen and the overflow flag OV will be
+ * set.
+ *
+ * **Operations**:\n
+ * ~~~
+ * // KDMABB16: (x,y,z)=(0,0,0),(2,2,1)
+ * // KDMABT16: (x,y,z)=(0,1,0),(2,3,1)
+ * // KDMATT16: (x,y,z)=(1,1,0),(3,3,1)
+ * aop[z] = Rs1.H[x]; bop[z] = Rs2.H[y];
+ * If (0x8000 != aop[z] | 0x8000 != bop[z]) {
+ *   Mresult[z] = aop[z] * bop[z];
+ *   resQ31[z] = Mresult[z] << 1;
+ * } else {
+ *   resQ31[z] = 0x7FFFFFFF;
+ *   OV = 1;
+ * }
+ * resadd[z] = Rd.W[z] + resQ31[z];
+ * if (resadd[z] > (2^31)-1) {
+ *   resadd[z] = (2^31)-1;
+ *   OV = 1;
+ * } else if (resadd[z] < -2^31) {
+ *   resadd[z] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[z] = resadd[z];
+ * ~~~
+ *
+ * \param [in]  t    unsigned long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KDMABT16(unsigned long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kdmabt16 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 4.9.2. KDMABT16 ===== */
+
+/* ===== Inline Function Start for 4.9.3. KDMATT16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT
+ * \brief KDMATT16 (SIMD Signed Saturating Double Multiply Addition T16 x T16)
+ * \details
+ * **Type**: SIMD (RV64 only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KDMAxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT)
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
+ * of the 32-bit chunks in registers and then double and saturate the Q31 results, add the results with
+ * the values of the corresponding 32-bit chunks from the destination register and write the saturated
+ * addition results back into the corresponding 32-bit chunks of the destination register. If saturation
+ * happens, an overflow flag OV will be set.
+ *
+ * **Description**:\n
+ * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top
+ * or bottom 16-bit Q15 content of the corresponding 32-bit portions in Rs2. The Q30 results are then
+ * doubled and saturated into Q31 values. The Q31 values are then added with the content of the
+ * corresponding 32-bit portions of Rd. If the addition results are beyond the Q31 number range (-2^31 <=
+ * Q31 <= 2^31-1), they are saturated to the range and the OV flag is set to 1. The results after saturation
+ * are written back to Rd.
+ * When both the two Q15 inputs are 0x8000, saturation will happen and the overflow flag OV will be
+ * set.
+ *
+ * **Operations**:\n
+ * ~~~
+ * // KDMABB16: (x,y,z)=(0,0,0),(2,2,1)
+ * // KDMABT16: (x,y,z)=(0,1,0),(2,3,1)
+ * // KDMATT16: (x,y,z)=(1,1,0),(3,3,1)
+ * aop[z] = Rs1.H[x]; bop[z] = Rs2.H[y];
+ * If (0x8000 != aop[z] | 0x8000 != bop[z]) {
+ *   Mresult[z] = aop[z] * bop[z];
+ *   resQ31[z] = Mresult[z] << 1;
+ * } else {
+ *   resQ31[z] = 0x7FFFFFFF;
+ *   OV = 1;
+ * }
+ * resadd[z] = Rd.W[z] + resQ31[z];
+ * if (resadd[z] > (2^31)-1) {
+ *   resadd[z] = (2^31)-1;
+ *   OV = 1;
+ * } else if (resadd[z] < -2^31) {
+ *   resadd[z] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[z] = resadd[z];
+ * ~~~
+ *
+ * \param [in]  t    unsigned long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KDMATT16(unsigned long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kdmatt16 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 4.9.3. KDMATT16 ===== */
+
+/* ===== Inline Function Start for 4.10.1. KHMBB16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT
+ * \brief KHMBB16 (SIMD Signed Saturating Half Multiply B16 x B16)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KHMxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT)
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
+ * of the 32-bit chunks in registers and then right-shift 15 bits to turn the Q30 results into Q15
+ * numbers again and saturate the Q15 results into the destination register. If saturation happens, an
+ * overflow flag OV will be set.
+ *
+ * **Description**:\n
+ * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top
+ * or bottom 16-bit Q15 content of the 32-bit portion in Rs2. The Q30 results are then right-shifted 15-
+ * bits and saturated into Q15 values. The 32-bit Q15 values are then written into the 32-bit chunks in
+ * Rd. When both the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated
+ * to 0x7FFF and the overflow flag OV will be set.
+ *
+ * **Operations**:\n
+ * ~~~
+ * // KHMBB16: (x,y,z)=(0,0,0),(2,2,1)
+ * // KHMBT16: (x,y,z)=(0,1,0),(2,3,1)
+ * // KHMTT16: (x,y,z)=(1,1,0),(3,3,1)
+ * aop = Rs1.H[x]; bop = Rs2.H[y];
+ * If (0x8000 != aop | 0x8000 != bop) {
+ *   Mresult[31:0] = aop * bop;
+ *   res[15:0] = Mresult[30:15];
+ * } else {
+ *   res[15:0] = 0x7FFF;
+ *   OV = 1;
+ * }
+ * Rd.W[z] = SE32(res[15:0]);
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KHMBB16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("khmbb16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.10.1. KHMBB16 ===== */
+
+/* ===== Inline Function Start for 4.10.2. KHMBT16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT
+ * \brief KHMBT16 (SIMD Signed Saturating Half Multiply B16 x T16)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KHMxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT)
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
+ * of the 32-bit chunks in registers and then right-shift 15 bits to turn the Q30 results into Q15
+ * numbers again and saturate the Q15 results into the destination register. If saturation happens, an
+ * overflow flag OV will be set.
+ *
+ * **Description**:\n
+ * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top
+ * or bottom 16-bit Q15 content of the 32-bit portion in Rs2. The Q30 results are then right-shifted 15-
+ * bits and saturated into Q15 values. The 32-bit Q15 values are then written into the 32-bit chunks in
+ * Rd. When both the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated
+ * to 0x7FFF and the overflow flag OV will be set.
+ *
+ * **Operations**:\n
+ * ~~~
+ * // KHMBB16: (x,y,z)=(0,0,0),(2,2,1)
+ * // KHMBT16: (x,y,z)=(0,1,0),(2,3,1)
+ * // KHMTT16: (x,y,z)=(1,1,0),(3,3,1)
+ * aop = Rs1.H[x]; bop = Rs2.H[y];
+ * If (0x8000 != aop | 0x8000 != bop) {
+ *   Mresult[31:0] = aop * bop;
+ *   res[15:0] = Mresult[30:15];
+ * } else {
+ *   res[15:0] = 0x7FFF;
+ *   OV = 1;
+ * }
+ * Rd.W[z] = SE32(res[15:0]);
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KHMBT16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("khmbt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.10.2. KHMBT16 ===== */
+
+/* ===== Inline Function Start for 4.10.3. KHMTT16 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT
+ * \brief KHMTT16 (SIMD Signed Saturating Half Multiply T16 x T16)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KHMxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT)
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
+ * of the 32-bit chunks in registers and then right-shift 15 bits to turn the Q30 results into Q15
+ * numbers again and saturate the Q15 results into the destination register. If saturation happens, an
+ * overflow flag OV will be set.
+ *
+ * **Description**:\n
+ * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top
+ * or bottom 16-bit Q15 content of the 32-bit portion in Rs2. The Q30 results are then right-shifted 15-
+ * bits and saturated into Q15 values. The 32-bit Q15 values are then written into the 32-bit chunks in
+ * Rd. When both the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated
+ * to 0x7FFF and the overflow flag OV will be set.
+ *
+ * **Operations**:\n
+ * ~~~
+ * // KHMBB16: (x,y,z)=(0,0,0),(2,2,1)
+ * // KHMBT16: (x,y,z)=(0,1,0),(2,3,1)
+ * // KHMTT16: (x,y,z)=(1,1,0),(3,3,1)
+ * aop = Rs1.H[x]; bop = Rs2.H[y];
+ * If (0x8000 != aop | 0x8000 != bop) {
+ *   Mresult[31:0] = aop * bop;
+ *   res[15:0] = Mresult[30:15];
+ * } else {
+ *   res[15:0] = 0x7FFF;
+ *   OV = 1;
+ * }
+ * Rd.W[z] = SE32(res[15:0]);
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KHMTT16(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("khmtt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.10.3. KHMTT16 ===== */
+
+/* ===== Inline Function Start for 4.11.1. KMABB32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT_ADD
+ * \brief KMABB32 (Saturating Signed Multiply Bottom Words & Add)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMABB32 Rd, Rs1, Rs2
+ * KMABT32 Rd, Rs1, Rs2
+ * KMATT32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit element in a register with the 32-bit element in another register
+ * and add the result to the content of 64-bit data in the third register. The addition result may be
+ * saturated and is written to the third register.
+ * * KMABB32: rd + bottom*bottom
+ * * KMABT32: rd + bottom*top
+ * * KMATT32: rd + top*top
+ *
+ * **Description**:\n
+ * For the `KMABB32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-bit
+ * element in Rs2.
+ * For the `KMABT32` instruction, it multiplies the bottom 32-bit element in Rs1 with the top 32-bit
+ * element in Rs2.
+ * For the `KMATT32` instruction, it multiplies the top 32-bit element in Rs1 with the top 32-bit
+ * element in Rs2.
+ * The multiplication result is added to the content of 64-bit data in Rd. If the addition result is beyond
+ * the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The
+ * result after saturation is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed
+ * integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res = Rd + (Rs1.W[0] * Rs2.W[0]); // KMABB32
+ *  res = Rd + (Rs1.W[0] * Rs2.W[1]); // KMABT32
+ *  res = Rd + (Rs1.W[1] * Rs2.W[1]); // KMATT32
+ *  if (res > (2^63)-1) {
+ *    res = (2^63)-1;
+ *    OV = 1;
+ *  } else if (res < -2^63) {
+ *    res = -2^63;
+ *    OV = 1;
+ *  }
+ *  Rd = res;
+ * *Exceptions:* None
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMABB32(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmabb32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 4.11.1. KMABB32 ===== */
+
+/* ===== Inline Function Start for 4.11.2. KMABT32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT_ADD
+ * \brief KMABT32 (Saturating Signed Multiply Bottom & Top Words & Add)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMABB32 Rd, Rs1, Rs2
+ * KMABT32 Rd, Rs1, Rs2
+ * KMATT32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit element in a register with the 32-bit element in another register
+ * and add the result to the content of 64-bit data in the third register. The addition result may be
+ * saturated and is written to the third register.
+ * * KMABB32: rd + bottom*bottom
+ * * KMABT32: rd + bottom*top
+ * * KMATT32: rd + top*top
+ *
+ * **Description**:\n
+ * For the `KMABB32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-bit
+ * element in Rs2.
+ * For the `KMABT32` instruction, it multiplies the bottom 32-bit element in Rs1 with the top 32-bit
+ * element in Rs2.
+ * For the `KMATT32` instruction, it multiplies the top 32-bit element in Rs1 with the top 32-bit
+ * element in Rs2.
+ * The multiplication result is added to the content of 64-bit data in Rd. If the addition result is beyond
+ * the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The
+ * result after saturation is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed
+ * integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res = Rd + (Rs1.W[0] * Rs2.W[0]); // KMABB32
+ *  res = Rd + (Rs1.W[0] * Rs2.W[1]); // KMABT32
+ *  res = Rd + (Rs1.W[1] * Rs2.W[1]); // KMATT32
+ *  if (res > (2^63)-1) {
+ *    res = (2^63)-1;
+ *    OV = 1;
+ *  } else if (res < -2^63) {
+ *    res = -2^63;
+ *    OV = 1;
+ *  }
+ *  Rd = res;
+ * *Exceptions:* None
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMABT32(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmabt32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 4.11.2. KMABT32 ===== */
+
+/* ===== Inline Function Start for 4.11.3. KMATT32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT_ADD
+ * \brief KMATT32 (Saturating Signed Multiply Top Words & Add)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMABB32 Rd, Rs1, Rs2
+ * KMABT32 Rd, Rs1, Rs2
+ * KMATT32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit element in a register with the 32-bit element in another register
+ * and add the result to the content of 64-bit data in the third register. The addition result may be
+ * saturated and is written to the third register.
+ * * KMABB32: rd + bottom*bottom
+ * * KMABT32: rd + bottom*top
+ * * KMATT32: rd + top*top
+ *
+ * **Description**:\n
+ * For the `KMABB32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-bit
+ * element in Rs2.
+ * For the `KMABT32` instruction, it multiplies the bottom 32-bit element in Rs1 with the top 32-bit
+ * element in Rs2.
+ * For the `KMATT32` instruction, it multiplies the top 32-bit element in Rs1 with the top 32-bit
+ * element in Rs2.
+ * The multiplication result is added to the content of 64-bit data in Rd. If the addition result is beyond
+ * the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The
+ * result after saturation is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed
+ * integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res = Rd + (Rs1.W[0] * Rs2.W[0]); // KMABB32
+ *  res = Rd + (Rs1.W[0] * Rs2.W[1]); // KMABT32
+ *  res = Rd + (Rs1.W[1] * Rs2.W[1]); // KMATT32
+ *  if (res > (2^63)-1) {
+ *    res = (2^63)-1;
+ *    OV = 1;
+ *  } else if (res < -2^63) {
+ *    res = -2^63;
+ *    OV = 1;
+ *  }
+ *  Rd = res;
+ * *Exceptions:* None
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMATT32(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmatt32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 4.11.3. KMATT32 ===== */
+
+/* ===== Inline Function Start for 4.12.1. KMADA32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC
+ * \brief KMADA32 (Saturating Signed Multiply Two Words and Two Adds)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMADA32 Rd, Rs1, Rs2
+ * KMAXDA32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 32-bit multiplications from 32-bit data in two registers; and then adds the
+ * two 64-bit results and 64-bit data in a third register together. The addition result may be saturated.
+ * * KMADA32: rd + top*top + bottom*bottom
+ * * KMAXDA32: rd + top*bottom + bottom*top
+ *
+ * **Description**:\n
+ * For the `KMADA32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-
+ * bit element in Rs2 and then adds the result to the result of multiplying the top 32-bit element in Rs1
+ * with the top 32-bit element in Rs2. It is actually an alias of the `KMAR64` instruction.
+ * For the `KMAXDA32` instruction, it multiplies the top 32-bit element in Rs1 with the bottom 32-bit
+ * element in Rs2 and then adds the result to the result of multiplying the bottom 32-bit element in Rs1
+ * with the top 32-bit element in Rs2.
+ * The result is added to the content of 64-bit data in Rd. If the addition result is beyond the Q63
+ * number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The 64-bit
+ * result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res = Rd + (Rs1.W[1] * Rs2.w[1]) + (Rs1.W[0] * Rs2.W[0]); // KMADA32
+ * res = Rd + (Rs1.W[1] * Rs2.W[0]) + (Rs1.W[0] * Rs2.W[1]); // KMAXDA32
+ * if (res > (2^63)-1) {
+ *   res = (2^63)-1;
+ *   OV = 1;
+ * } else if (res < -2^63) {
+ *   res = -2^63;
+ *   OV = 1;
+ * }
+ * Rd = res;
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMADA32(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmada32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 4.12.1. KMADA32 ===== */
+
+/* ===== Inline Function Start for 4.12.2. KMAXDA32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC
+ * \brief KMAXDA32 (Saturating Signed Crossed Multiply Two Words and Two Adds)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMADA32 Rd, Rs1, Rs2
+ * KMAXDA32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 32-bit multiplications from 32-bit data in two registers; and then adds the
+ * two 64-bit results and 64-bit data in a third register together. The addition result may be saturated.
+ * * KMADA32: rd + top*top + bottom*bottom
+ * * KMAXDA32: rd + top*bottom + bottom*top
+ *
+ * **Description**:\n
+ * For the `KMADA32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-
+ * bit element in Rs2 and then adds the result to the result of multiplying the top 32-bit element in Rs1
+ * with the top 32-bit element in Rs2. It is actually an alias of the `KMAR64` instruction.
+ * For the `KMAXDA32` instruction, it multiplies the top 32-bit element in Rs1 with the bottom 32-bit
+ * element in Rs2 and then adds the result to the result of multiplying the bottom 32-bit element in Rs1
+ * with the top 32-bit element in Rs2.
+ * The result is added to the content of 64-bit data in Rd. If the addition result is beyond the Q63
+ * number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The 64-bit
+ * result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res = Rd + (Rs1.W[1] * Rs2.w[1]) + (Rs1.W[0] * Rs2.W[0]); // KMADA32
+ * res = Rd + (Rs1.W[1] * Rs2.W[0]) + (Rs1.W[0] * Rs2.W[1]); // KMAXDA32
+ * if (res > (2^63)-1) {
+ *   res = (2^63)-1;
+ *   OV = 1;
+ * } else if (res < -2^63) {
+ *   res = -2^63;
+ *   OV = 1;
+ * }
+ * Rd = res;
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMAXDA32(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmaxda32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 4.12.2. KMAXDA32 ===== */
+
+/* ===== Inline Function Start for 4.13.1. KMDA32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC
+ * \brief KMDA32 (Signed Multiply Two Words and Add)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMDA32 Rd, Rs1, Rs2
+ * KMXDA32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 32-bit multiplications from the 32-bit element of two registers; and then
+ * adds the two 64-bit results together. The addition result may be saturated.
+ * * KMDA32: top*top + bottom*bottom
+ * * KMXDA32: top*bottom + bottom*top
+ *
+ * **Description**:\n
+ * For the `KMDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit
+ * element of Rs2 and then adds the result to the result of multiplying the top 32-bit element of Rs1
+ * with the top 32-bit element of Rs2.
+ * For the `KMXDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit
+ * element of Rs2 and then adds the result to the result of multiplying the top 32-bit element of Rs1
+ * with the bottom 32-bit element of Rs2.
+ * The addition result is checked for saturation. If saturation happens, the result is saturated to 2^63-1.
+ * The final result is written to Rd. The 32-bit contents are treated as signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if ((Rs1 != 0x8000000080000000) or (Rs2 != 0x8000000080000000)) {
+ *   Rd = (Rs1.W[1] * Rs2.W[1]) + (Rs1.W[0] * Rs2.W[0]); // KMDA32
+ *   Rd = (Rs1.W[1] * Rs2.W[0]) + (Rs1.W[0] * Rs2.W[1]); // KMXDA32
+ * } else {
+ *   Rd = 0x7fffffffffffffff;
+ *   OV = 1;
+ * }
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMDA32(unsigned long a, unsigned long b)
+{
+    register long result;
+    __ASM volatile("kmda32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.13.1. KMDA32 ===== */
+
+/* ===== Inline Function Start for 4.13.2. KMXDA32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC
+ * \brief KMXDA32 (Signed Crossed Multiply Two Words and Add)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMDA32 Rd, Rs1, Rs2
+ * KMXDA32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 32-bit multiplications from the 32-bit element of two registers; and then
+ * adds the two 64-bit results together. The addition result may be saturated.
+ * * KMDA32: top*top + bottom*bottom
+ * * KMXDA32: top*bottom + bottom*top
+ *
+ * **Description**:\n
+ * For the `KMDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit
+ * element of Rs2 and then adds the result to the result of multiplying the top 32-bit element of Rs1
+ * with the top 32-bit element of Rs2.
+ * For the `KMXDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit
+ * element of Rs2 and then adds the result to the result of multiplying the top 32-bit element of Rs1
+ * with the bottom 32-bit element of Rs2.
+ * The addition result is checked for saturation. If saturation happens, the result is saturated to 2^63-1.
+ * The final result is written to Rd. The 32-bit contents are treated as signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if ((Rs1 != 0x8000000080000000) or (Rs2 != 0x8000000080000000)) {
+ *   Rd = (Rs1.W[1] * Rs2.W[1]) + (Rs1.W[0] * Rs2.W[0]); // KMDA32
+ *   Rd = (Rs1.W[1] * Rs2.W[0]) + (Rs1.W[0] * Rs2.W[1]); // KMXDA32
+ * } else {
+ *   Rd = 0x7fffffffffffffff;
+ *   OV = 1;
+ * }
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMXDA32(unsigned long a, unsigned long b)
+{
+    register long result;
+    __ASM volatile("kmxda32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.13.2. KMXDA32 ===== */
+
+/* ===== Inline Function Start for 4.14.1. KMADS32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC
+ * \brief KMADS32 (Saturating Signed Multiply Two Words & Subtract & Add)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMADS32 Rd, Rs1, Rs2
+ * KMADRS32 Rd, Rs1, Rs2
+ * KMAXDS32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 32-bit multiplications from 32-bit elements in two registers; and then
+ * perform a subtraction operation between the two 64-bit results. Then add the subtraction result to
+ * 64-bit data in a third register. The addition result may be saturated.
+ * * KMADS32: rd + (top*top - bottom*bottom)
+ * * KMADRS32: rd + (bottom*bottom - top*top)
+ * * KMAXDS32: rd + (top*bottom - bottom*top)
+ *
+ * **Description**:\n
+ * For the `KMADS32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-bit
+ * element in Rs2 and then subtracts the result from the result of multiplying the top 32-bit element in
+ * Rs1 with the top 32-bit element in Rs2.
+ * For the `KMADRS32` instruction, it multiplies the top 32-bit element in Rs1 with the top 32-bit
+ * element in Rs2 and then subtracts the result from the result of multiplying the bottom 32-bit
+ * element in Rs1 with the bottom 32-bit element in Rs2.
+ * For the `KMAXDS32` instruction, it multiplies the bottom 32-bit element in Rs1 with the top 32-bit
+ * element in Rs2 and then subtracts the result from the result of multiplying the top 32-bit element in
+ * Rs1 with the bottom 32-bit element in Rs2.
+ * The subtraction result is then added to the content of 64-bit data in Rd. If the addition result is
+ * beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to
+ * 1. The 64-bit result after saturation is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated
+ * as signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res = Rd + (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // KMADS32
+ * res = Rd + (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); // KMADRS32
+ * res = Rd + (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // KMAXDS32
+ * if (res > (2^63)-1) {
+ *   res = (2^63)-1;
+ *   OV = 1;
+ * } else if (res < -2^63) {
+ *   res = -2^63;
+ *   OV = 1;
+ * }
+ * Rd = res;
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMADS32(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmads32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 4.14.1. KMADS32 ===== */
+
+/* ===== Inline Function Start for 4.14.2. KMADRS32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC
+ * \brief KMADRS32 (Saturating Signed Multiply Two Words & Reverse Subtract & Add)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMADS32 Rd, Rs1, Rs2
+ * KMADRS32 Rd, Rs1, Rs2
+ * KMAXDS32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 32-bit multiplications from 32-bit elements in two registers; and then
+ * perform a subtraction operation between the two 64-bit results. Then add the subtraction result to
+ * 64-bit data in a third register. The addition result may be saturated.
+ * * KMADS32: rd + (top*top - bottom*bottom)
+ * * KMADRS32: rd + (bottom*bottom - top*top)
+ * * KMAXDS32: rd + (top*bottom - bottom*top)
+ *
+ * **Description**:\n
+ * For the `KMADS32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-bit
+ * element in Rs2 and then subtracts the result from the result of multiplying the top 32-bit element in
+ * Rs1 with the top 32-bit element in Rs2.
+ * For the `KMADRS32` instruction, it multiplies the top 32-bit element in Rs1 with the top 32-bit
+ * element in Rs2 and then subtracts the result from the result of multiplying the bottom 32-bit
+ * element in Rs1 with the bottom 32-bit element in Rs2.
+ * For the `KMAXDS32` instruction, it multiplies the bottom 32-bit element in Rs1 with the top 32-bit
+ * element in Rs2 and then subtracts the result from the result of multiplying the top 32-bit element in
+ * Rs1 with the bottom 32-bit element in Rs2.
+ * The subtraction result is then added to the content of 64-bit data in Rd. If the addition result is
+ * beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to
+ * 1. The 64-bit result after saturation is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated
+ * as signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res = Rd + (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // KMADS32
+ * res = Rd + (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); // KMADRS32
+ * res = Rd + (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // KMAXDS32
+ * if (res > (2^63)-1) {
+ *   res = (2^63)-1;
+ *   OV = 1;
+ * } else if (res < -2^63) {
+ *   res = -2^63;
+ *   OV = 1;
+ * }
+ * Rd = res;
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMADRS32(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmadrs32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 4.14.2. KMADRS32 ===== */
+
+/* ===== Inline Function Start for 4.14.3. KMAXDS32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC
+ * \brief KMAXDS32 (Saturating Signed Crossed Multiply Two Words & Subtract & Add)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMADS32 Rd, Rs1, Rs2
+ * KMADRS32 Rd, Rs1, Rs2
+ * KMAXDS32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 32-bit multiplications from 32-bit elements in two registers; and then
+ * perform a subtraction operation between the two 64-bit results. Then add the subtraction result to
+ * 64-bit data in a third register. The addition result may be saturated.
+ * * KMADS32: rd + (top*top - bottom*bottom)
+ * * KMADRS32: rd + (bottom*bottom - top*top)
+ * * KMAXDS32: rd + (top*bottom - bottom*top)
+ *
+ * **Description**:\n
+ * For the `KMADS32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-bit
+ * element in Rs2 and then subtracts the result from the result of multiplying the top 32-bit element in
+ * Rs1 with the top 32-bit element in Rs2.
+ * For the `KMADRS32` instruction, it multiplies the top 32-bit element in Rs1 with the top 32-bit
+ * element in Rs2 and then subtracts the result from the result of multiplying the bottom 32-bit
+ * element in Rs1 with the bottom 32-bit element in Rs2.
+ * For the `KMAXDS32` instruction, it multiplies the bottom 32-bit element in Rs1 with the top 32-bit
+ * element in Rs2 and then subtracts the result from the result of multiplying the top 32-bit element in
+ * Rs1 with the bottom 32-bit element in Rs2.
+ * The subtraction result is then added to the content of 64-bit data in Rd. If the addition result is
+ * beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to
+ * 1. The 64-bit result after saturation is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated
+ * as signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res = Rd + (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // KMADS32
+ * res = Rd + (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); // KMADRS32
+ * res = Rd + (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // KMAXDS32
+ * if (res > (2^63)-1) {
+ *   res = (2^63)-1;
+ *   OV = 1;
+ * } else if (res < -2^63) {
+ *   res = -2^63;
+ *   OV = 1;
+ * }
+ * Rd = res;
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMAXDS32(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmaxds32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 4.14.3. KMAXDS32 ===== */
+
+/* ===== Inline Function Start for 4.15.1. KMSDA32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC
+ * \brief KMSDA32 (Saturating Signed Multiply Two Words & Add & Subtract)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMSDA32 Rd, Rs1, Rs2
+ * KMSXDA32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 32-bit multiplications from the 32-bit element of two registers; and then
+ * subtracts the two 64-bit results from a third register. The subtraction result may be saturated.
+ * * KMSDA: rd - top*top - bottom*bottom
+ * * KMSXDA: rd - top*bottom - bottom*top
+ *
+ * **Description**:\n
+ * For the `KMSDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit
+ * element of Rs2 and multiplies the top 32-bit element of Rs1 with the top 32-bit element of Rs2.
+ * For the `KMSXDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit
+ * element of Rs2 and multiplies the top 32-bit element of Rs1 with the bottom 32-bit element of Rs2.
+ * The two 64-bit multiplication results are then subtracted from the content of Rd. If the subtraction
+ * result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit
+ * is set to 1. The result after saturation is written to Rd. The 32-bit contents are treated as signed
+ * integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res = Rd - (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // KMSDA32
+ * res = Rd - (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // KMSXDA32
+ * if (res > (2^63)-1) {
+ *   res = (2^63)-1;
+ *   OV = 1;
+ * } else if (res < -2^63) {
+ *   res = -2^63;
+ *   OV = 1;
+ * }
+ * Rd = res;
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMSDA32(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmsda32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 4.15.1. KMSDA32 ===== */
+
+/* ===== Inline Function Start for 4.15.2. KMSXDA32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC
+ * \brief KMSXDA32 (Saturating Signed Crossed Multiply Two Words & Add & Subtract)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KMSDA32 Rd, Rs1, Rs2
+ * KMSXDA32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 32-bit multiplications from the 32-bit element of two registers; and then
+ * subtracts the two 64-bit results from a third register. The subtraction result may be saturated.
+ * * KMSDA: rd - top*top - bottom*bottom
+ * * KMSXDA: rd - top*bottom - bottom*top
+ *
+ * **Description**:\n
+ * For the `KMSDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit
+ * element of Rs2 and multiplies the top 32-bit element of Rs1 with the top 32-bit element of Rs2.
+ * For the `KMSXDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit
+ * element of Rs2 and multiplies the top 32-bit element of Rs1 with the bottom 32-bit element of Rs2.
+ * The two 64-bit multiplication results are then subtracted from the content of Rd. If the subtraction
+ * result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit
+ * is set to 1. The result after saturation is written to Rd. The 32-bit contents are treated as signed
+ * integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res = Rd - (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // KMSDA32
+ * res = Rd - (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // KMSXDA32
+ * if (res > (2^63)-1) {
+ *   res = (2^63)-1;
+ *   OV = 1;
+ * } else if (res < -2^63) {
+ *   res = -2^63;
+ *   OV = 1;
+ * }
+ * Rd = res;
+ * ~~~
+ *
+ * \param [in]  t    long type of value stored in t
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_KMSXDA32(long t, unsigned long a, unsigned long b)
+{
+    __ASM volatile("kmsxda32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
+    return t;
+}
+/* ===== Inline Function End for 4.15.2. KMSXDA32 ===== */
+
+/* ===== Inline Function Start for 4.16. KSLL32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
+ * \brief KSLL32 (SIMD 32-bit Saturating Shift Left Logical)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSLL32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit elements logical left shift operations with saturation simultaneously. The shift
+ * amount is a variable from a GPR.
+ *
+ * **Description**:\n
+ * The 32-bit data elements in Rs1 are left-shifted logically. The shifted out bits are filled
+ * with zero and the shift amount is specified by the low-order 5-bits of the value in the Rs2 register.
+ * Any shifted value greater than 2^31-1 is saturated to 2^31-1. Any shifted value smaller than -2^31 is
+ * saturated to -2^31. And the saturated results are written to Rd. If any saturation is performed, set OV
+ * bit to 1.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = Rs2[4:0];
+ * if (sa != 0) {
+ *   res[(31+sa):0] = Rs1.W[x] << sa;
+ *   if (res > (2^31)-1) {
+ *     res = 0x7fffffff; OV = 1;
+ *   } else if (res < -2^31) {
+ *     res = 0x80000000; OV = 1;
+ *   }
+ *   Rd.W[x] = res[31:0];
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KSLL32(unsigned long a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("ksll32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.16. KSLL32 ===== */
+
+/* ===== Inline Function Start for 4.17. KSLLI32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
+ * \brief KSLLI32 (SIMD 32-bit Saturating Shift Left Logical Immediate)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSLLI32 Rd, Rs1, imm5u
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit elements logical left shift operations with saturation simultaneously. The shift
+ * amount is an immediate value.
+ *
+ * **Description**:\n
+ * The 32-bit data elements in Rs1 are left-shifted logically. The shifted out bits are filled
+ * with zero and the shift amount is specified by the imm5u constant. Any shifted value greater than
+ * 2^31-1 is saturated to 2^31-1. Any shifted value smaller than -2^31 is saturated to -2^31. And the saturated
+ * results are written to Rd. If any saturation is performed, set OV bit to 1.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = imm5u[4:0];
+ * if (sa != 0) {
+ *   res[(31+sa):0] = Rs1.W[x] << sa;
+ *   if (res > (2^31)-1) {
+ *     res = 0x7fffffff; OV = 1;
+ *   } else if (res < -2^31) {
+ *     res = 0x80000000; OV = 1;
+ *   }
+ *   Rd.W[x] = res[31:0];
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KSLLI32(unsigned long a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("kslli32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.17. KSLLI32 ===== */
+
+/* ===== Inline Function Start for 4.18.1. KSLRA32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
+ * \brief KSLRA32 (SIMD 32-bit Shift Left Logical with Saturation or Shift Right Arithmetic)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSLRA32 Rd, Rs1, Rs2
+ * KSLRA32.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit elements logical left (positive) or arithmetic right (negative) shift operation with
+ * Q31 saturation for the left shift. The `.u` form performs additional rounding up operations for the
+ * right shift.
+ *
+ * **Description**:\n
+ * The 32-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically
+ * based on the value of Rs2[5:0]. Rs2[5:0] is in the signed range of [-25, 25-1]. A positive Rs2[5:0] means
+ * logical left shift and a negative Rs2[5:0] means arithmetic right shift. The shift amount is the
+ * absolute value of Rs2[5:0]. However, the behavior of `Rs2[5:0]==-25 (0x20)` is defined to be
+ * equivalent to the behavior of `Rs2[5:0]==-(25-1) (0x21)`.
+ * The left-shifted results are saturated to the 32-bit signed integer range of [-2^31, 2^31-1]. For the `.u`
+ * form of the instruction, the right-shifted results are added a 1 to the most significant discarded bit
+ * position for rounding effect. After the shift, saturation, or rounding, the final results are written to
+ * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:6] will not affect
+ * this instruction.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if (Rs2[5:0] < 0) {
+ *   sa = -Rs2[5:0];
+ *   sa = (sa == 32)? 31 : sa;
+ *   if (`.u` form) {
+ *     res[31:-1] = SE33(Rs1.W[x][31:sa-1]) + 1;
+ *     Rd.W[x] = res[31:0];
+ *   } else {
+ *     Rd.W[x] = SE32(Rs1.W[x][31:sa]);
+ *   }
+ * } else {
+ *   sa = Rs2[4:0];
+ *   res[(31+sa):0] = Rs1.W[x] <<(logic) sa;
+ *   if (res > (2^31)-1) {
+ *     res[31:0] = 0x7fffffff; OV = 1;
+ *   } else if (res < -2^31) {
+ *     res[31:0] = 0x80000000; OV = 1;
+ *   }
+ *   Rd.W[x] = res[31:0];
+ * }
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KSLRA32(unsigned long a, int b)
+{
+    register unsigned long result;
+    __ASM volatile("kslra32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.18.1. KSLRA32 ===== */
+
+/* ===== Inline Function Start for 4.18.2. KSLRA32.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
+ * \brief KSLRA32.u (SIMD 32-bit Shift Left Logical with Saturation or Rounding Shift Right Arithmetic)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSLRA32 Rd, Rs1, Rs2
+ * KSLRA32.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit elements logical left (positive) or arithmetic right (negative) shift operation with
+ * Q31 saturation for the left shift. The `.u` form performs additional rounding up operations for the
+ * right shift.
+ *
+ * **Description**:\n
+ * The 32-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically
+ * based on the value of Rs2[5:0]. Rs2[5:0] is in the signed range of [-25, 25-1]. A positive Rs2[5:0] means
+ * logical left shift and a negative Rs2[5:0] means arithmetic right shift. The shift amount is the
+ * absolute value of Rs2[5:0]. However, the behavior of `Rs2[5:0]==-25 (0x20)` is defined to be
+ * equivalent to the behavior of `Rs2[5:0]==-(25-1) (0x21)`.
+ * The left-shifted results are saturated to the 32-bit signed integer range of [-2^31, 2^31-1]. For the `.u`
+ * form of the instruction, the right-shifted results are added a 1 to the most significant discarded bit
+ * position for rounding effect. After the shift, saturation, or rounding, the final results are written to
+ * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:6] will not affect
+ * this instruction.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if (Rs2[5:0] < 0) {
+ *   sa = -Rs2[5:0];
+ *   sa = (sa == 32)? 31 : sa;
+ *   if (`.u` form) {
+ *     res[31:-1] = SE33(Rs1.W[x][31:sa-1]) + 1;
+ *     Rd.W[x] = res[31:0];
+ *   } else {
+ *     Rd.W[x] = SE32(Rs1.W[x][31:sa]);
+ *   }
+ * } else {
+ *   sa = Rs2[4:0];
+ *   res[(31+sa):0] = Rs1.W[x] <<(logic) sa;
+ *   if (res > (2^31)-1) {
+ *     res[31:0] = 0x7fffffff; OV = 1;
+ *   } else if (res < -2^31) {
+ *     res[31:0] = 0x80000000; OV = 1;
+ *   }
+ *   Rd.W[x] = res[31:0];
+ * }
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KSLRA32_U(unsigned long a, int b)
+{
+    register unsigned long result;
+    __ASM volatile("kslra32.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.18.2. KSLRA32.u ===== */
+
+/* ===== Inline Function Start for 4.19. KSTAS32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief KSTAS32 (SIMD 32-bit Signed Saturating Straight Addition & Subtraction)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSTAS32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit signed integer element saturating addition and 32-bit signed integer element
+ * saturating subtraction in a 64-bit chunk simultaneously. Operands are from corresponding 32-bit
+ * elements.
+ *
+ * **Description**:\n
+ * This instruction adds the 32-bit integer element in [63:32] of Rs1 with the 32-bit
+ * integer element in [63:32] of Rs2; at the same time, it subtracts the 32-bit integer element in [31:0] of
+ * Rs2 from the 32-bit integer element in [31:0] of Rs1. If any of the results are beyond the Q31 number
+ * range (-2^31 <= Q31 <= 2^31-1), they are saturated to the range and the OV bit is set to 1. The saturated
+ * results are written to [63:32] of Rd for addition and [31:0] of Rd for subtraction.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[1] = Rs1.W[1] + Rs2.W[1];
+ * res[0] = Rs1.W[0] - Rs2.W[0];
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[1] = res[1];
+ * Rd.W[0] = res[0];
+ * for RV64, x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KSTAS32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("kstas32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.19. KSTAS32 ===== */
+
+/* ===== Inline Function Start for 4.20. KSTSA32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief KSTSA32 (SIMD 32-bit Signed Saturating Straight Subtraction & Addition)
+ * \details
+ * **Type**: SIM (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSTSA32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit signed integer element saturating subtraction and 32-bit signed integer element
+ * saturating addition in a 64-bit chunk simultaneously. Operands are from corresponding 32-bit
+ * elements.
+ * *Description: *
+ * This instruction subtracts the 32-bit integer element in [63:32] of Rs2 from the 32-bit integer
+ * element in [63:32] of Rs1; at the same time, it adds the 32-bit integer element in [31:0] of Rs1 with
+ * the 32-bit integer element in [31:0] of Rs2. If any of the results are beyond the Q31 number range (-
+ * 231 <= Q31 <= 2^31-1), they are saturated to the range and the OV bit is set to 1. The saturated results are
+ * written to [63:32] of Rd for subtraction and [31:0] of Rd for addition.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[1] = Rs1.W[1] - Rs2.W[1];
+ * res[0] = Rs1.W[0] + Rs2.W[0];
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[1] = res[1];
+ * Rd.W[0] = res[0];
+ * for RV64, x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KSTSA32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("kstsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.20. KSTSA32 ===== */
+
+/* ===== Inline Function Start for 4.21. KSUB32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief KSUB32 (SIMD 32-bit Signed Saturating Subtraction)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * KSUB32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit signed integer elements saturating subtractions simultaneously.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 32-bit signed integer elements in Rs2 from the 32-bit
+ * signed integer elements in Rs1. If any of the results are beyond the Q31 number range (-2^31 <= Q31 <=
+ * 2^31-1), they are saturated to the range and the OV bit is set to 1. The saturated results are written to
+ * Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[x] = Rs1.W[x] - Rs2.W[x];
+ * if (res[x] > (2^31)-1) {
+ *   res[x] = (2^31)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^31) {
+ *   res[x] = -2^31;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_KSUB32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("ksub32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.21. KSUB32 ===== */
+
+/* ===== Inline Function Start for 4.22.1. PKBB32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PACK
+ * \brief PKBB32 (Pack Two 32-bit Data from Both Bottom Half)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * PKBB32 Rd, Rs1, Rs2
+ * PKBT32 Rd, Rs1, Rs2
+ * PKTT32 Rd, Rs1, Rs2
+ * PKTB32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Pack 32-bit data from 64-bit chunks in two registers.
+ * * PKBB32: bottom.bottom
+ * * PKBT32: bottom.top
+ * * PKTT32: top.top
+ * * PKTB32: top.bottom
+ *
+ * **Description**:\n
+ * (PKBB32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0].
+ * (PKBT32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0].
+ * (PKTT32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0].
+ * (PKTB32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0].
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*0*_]); // PKBB32
+ * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*1*_]); // PKBT32
+ * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*1*_]); // PKTT32
+ * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*0*_]); // PKTB32
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_PKBB32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("pkbb32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.22.1. PKBB32 ===== */
+
+/* ===== Inline Function Start for 4.22.2. PKBT32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PACK
+ * \brief PKBT32 (Pack Two 32-bit Data from Bottom and Top Half)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * PKBB32 Rd, Rs1, Rs2
+ * PKBT32 Rd, Rs1, Rs2
+ * PKTT32 Rd, Rs1, Rs2
+ * PKTB32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Pack 32-bit data from 64-bit chunks in two registers.
+ * * PKBB32: bottom.bottom
+ * * PKBT32: bottom.top
+ * * PKTT32: top.top
+ * * PKTB32: top.bottom
+ *
+ * **Description**:\n
+ * (PKBB32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0].
+ * (PKBT32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0].
+ * (PKTT32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0].
+ * (PKTB32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0].
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*0*_]); // PKBB32
+ * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*1*_]); // PKBT32
+ * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*1*_]); // PKTT32
+ * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*0*_]); // PKTB32
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_PKBT32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("pkbt32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.22.2. PKBT32 ===== */
+
+/* ===== Inline Function Start for 4.22.3. PKTT32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PACK
+ * \brief PKTT32 (Pack Two 32-bit Data from Both Top Half)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * PKBB32 Rd, Rs1, Rs2
+ * PKBT32 Rd, Rs1, Rs2
+ * PKTT32 Rd, Rs1, Rs2
+ * PKTB32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Pack 32-bit data from 64-bit chunks in two registers.
+ * * PKBB32: bottom.bottom
+ * * PKBT32: bottom.top
+ * * PKTT32: top.top
+ * * PKTB32: top.bottom
+ *
+ * **Description**:\n
+ * (PKBB32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0].
+ * (PKBT32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0].
+ * (PKTT32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0].
+ * (PKTB32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0].
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*0*_]); // PKBB32
+ * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*1*_]); // PKBT32
+ * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*1*_]); // PKTT32
+ * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*0*_]); // PKTB32
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_PKTT32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("pktt32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.22.3. PKTT32 ===== */
+
+/* ===== Inline Function Start for 4.22.4. PKTB32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PACK
+ * \brief PKTB32 (Pack Two 32-bit Data from Top and Bottom Half)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * PKBB32 Rd, Rs1, Rs2
+ * PKBT32 Rd, Rs1, Rs2
+ * PKTT32 Rd, Rs1, Rs2
+ * PKTB32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Pack 32-bit data from 64-bit chunks in two registers.
+ * * PKBB32: bottom.bottom
+ * * PKBT32: bottom.top
+ * * PKTT32: top.top
+ * * PKTB32: top.bottom
+ *
+ * **Description**:\n
+ * (PKBB32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0].
+ * (PKBT32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0].
+ * (PKTT32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0].
+ * (PKTB32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0].
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*0*_]); // PKBB32
+ * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*1*_]); // PKBT32
+ * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*1*_]); // PKTT32
+ * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*0*_]); // PKTB32
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_PKTB32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("pktb32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.22.4. PKTB32 ===== */
+
+/* ===== Inline Function Start for 4.23. RADD32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief RADD32 (SIMD 32-bit Signed Halving Addition)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * RADD32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit signed integer element additions simultaneously. The results are halved to avoid
+ * overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction adds the 32-bit signed integer elements in Rs1 with the 32-bit signed
+ * integer elements in Rs2. The results are first arithmetically right-shifted by 1 bit and then written to
+ * Rd.
+ *
+ * **Examples**:\n
+ * ~~~
+ * * Rs1 = 0x7FFFFFFF, Rs2 = 0x7FFFFFFF Rd = 0x7FFFFFFF
+ * * Rs1 = 0x80000000, Rs2 = 0x80000000 Rd = 0x80000000
+ * * Rs1 = 0x40000000, Rs2 = 0x80000000 Rd = 0xE0000000
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x] = (Rs1.W[x] + Rs2.W[x]) s>> 1;
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_RADD32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("radd32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.23. RADD32 ===== */
+
+/* ===== Inline Function Start for 4.24. RCRAS32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief RCRAS32 (SIMD 32-bit Signed Halving Cross Addition & Subtraction)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * RCRAS32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit signed integer element addition and 32-bit signed integer element subtraction in
+ * a 64-bit chunk simultaneously. Operands are from crossed 32-bit elements. The results are halved to
+ * avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction adds the 32-bit signed integer element in [63:32] of Rs1 with the 32-bit
+ * signed integer element in [31:0] of Rs2, and subtracts the 32-bit signed integer element in [63:32] of
+ * Rs2 from the 32-bit signed integer element in [31:0] of Rs1. The element results are first
+ * arithmetically right-shifted by 1 bit and then written to [63:32] of Rd for addition and [31:0] of Rd
+ * for subtraction.
+ *
+ * **Examples**:\n
+ * ~~~
+ * Please see `RADD32` and `RSUB32` instructions.
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[1] = (Rs1.W[1] + Rs2.W[0]) s>> 1;
+ * Rd.W[0] = (Rs1.W[0] - Rs2.W[1]) s>> 1;
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_RCRAS32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("rcras32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.24. RCRAS32 ===== */
+
+/* ===== Inline Function Start for 4.25. RCRSA32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief RCRSA32 (SIMD 32-bit Signed Halving Cross Subtraction & Addition)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * RCRSA32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit signed integer element subtraction and 32-bit signed integer element addition in
+ * a 64-bit chunk simultaneously. Operands are from crossed 32-bit elements. The results are halved to
+ * avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 32-bit signed integer element in [31:0] of Rs2 from the
+ * 32-bit signed integer element in [63:32] of Rs1, and adds the 32-bit signed element integer in [31:0]
+ * of Rs1 with the 32-bit signed integer element in [63:32] of Rs2. The two results are first
+ * arithmetically right-shifted by 1 bit and then written to [63:32] of Rd for subtraction and [31:0] of
+ * Rd for addition.
+ *
+ * **Examples**:\n
+ * ~~~
+ * Please see `RADD32` and `RSUB32` instructions.
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[1] = (Rs1.W[1] - Rs2.W[0]) s>> 1;
+ * Rd.W[0] = (Rs1.W[0] + Rs2.W[1]) s>> 1;
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_RCRSA32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("rcrsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.25. RCRSA32 ===== */
+
+/* ===== Inline Function Start for 4.26. RSTAS32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief RSTAS32 (SIMD 32-bit Signed Halving Straight Addition & Subtraction)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * RSTAS32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit signed integer element addition and 32-bit signed integer element subtraction in
+ * a 64-bit chunk simultaneously. Operands are from corresponding 32-bit elements. The results are
+ * halved to avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction adds the 32-bit signed integer element in [63:32] of Rs1 with the 32-bit
+ * signed integer element in [63:32] of Rs2, and subtracts the 32-bit signed integer element in [31:0] of
+ * Rs2 from the 32-bit signed integer element in [31:0] of Rs1. The element results are first
+ * arithmetically right-shifted by 1 bit and then written to [63:32] of Rd for addition and [31:0] of Rd
+ * for subtraction.
+ *
+ * **Examples**:\n
+ * ~~~
+ * Please see `RADD32` and `RSUB32` instructions.
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[1] = (Rs1.W[1] + Rs2.W[1]) s>> 1;
+ * Rd.W[0] = (Rs1.W[0] - Rs2.W[0]) s>> 1;
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_RSTAS32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("rstas32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.26. RSTAS32 ===== */
+
+/* ===== Inline Function Start for 4.27. RSTSA32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief RSTSA32 (SIMD 32-bit Signed Halving Straight Subtraction & Addition)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * RSTSA32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit signed integer element subtraction and 32-bit signed integer element addition in
+ * a 64-bit chunk simultaneously. Operands are from corresponding 32-bit elements. The results are
+ * halved to avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 32-bit signed integer element in [63:32] of Rs2 from the
+ * 32-bit signed integer element in [63:32] of Rs1, and adds the 32-bit signed element integer in [31:0]
+ * of Rs1 with the 32-bit signed integer element in [31:0] of Rs2. The two results are first arithmetically
+ * right-shifted by 1 bit and then written to [63:32] of Rd for subtraction and [31:0] of Rd for addition.
+ *
+ * **Examples**:\n
+ * ~~~
+ * Please see `RADD32` and `RSUB32` instructions.
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[1] = (Rs1.W[1] - Rs2.W[1]) s>> 1;
+ * Rd.W[0] = (Rs1.W[0] + Rs2.W[0]) s>> 1;
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_RSTSA32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("rstsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.27. RSTSA32 ===== */
+
+/* ===== Inline Function Start for 4.28. RSUB32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief RSUB32 (SIMD 32-bit Signed Halving Subtraction)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * RSUB32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit signed integer element subtractions simultaneously. The results are halved to
+ * avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 32-bit signed integer elements in Rs2 from the 32-bit
+ * signed integer elements in Rs1. The results are first arithmetically right-shifted by 1 bit and then
+ * written to Rd.
+ *
+ * **Examples**:\n
+ * ~~~
+ * * Ra = 0x7FFFFFFF, Rb = 0x80000000 Rt = 0x7FFFFFFF
+ * * Ra = 0x80000000, Rb = 0x7FFFFFFF Rt = 0x80000000
+ * * Ra = 0x80000000, Rb = 0x40000000 Rt = 0xA0000000
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x] = (Rs1.W[x] - Rs2.W[x]) s>> 1;
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_RSUB32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("rsub32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.28. RSUB32 ===== */
+
+/* ===== Inline Function Start for 4.29. SLL32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
+ * \brief SLL32 (SIMD 32-bit Shift Left Logical)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SLL32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit elements logical left shift operations simultaneously. The shift amount is a
+ * variable from a GPR.
+ *
+ * **Description**:\n
+ * The 32-bit elements in Rs1 are left-shifted logically. And the results are written to Rd.
+ * The shifted out bits are filled with zero and the shift amount is specified by the low-order 5-bits of
+ * the value in the Rs2 register.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = Rs2[4:0];
+ * Rd.W[x] = Rs1.W[x] << sa;
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SLL32(unsigned long a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("sll32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.29. SLL32 ===== */
+
+/* ===== Inline Function Start for 4.30. SLLI32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
+ * \brief SLLI32 (SIMD 32-bit Shift Left Logical Immediate)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SLLI32 Rd, Rs1, imm5u[4:0]
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit element logical left shift operations simultaneously. The shift amount is an
+ * immediate value.
+ *
+ * **Description**:\n
+ * The 32-bit elements in Rs1 are left-shifted logically. The shifted out bits are filled with
+ * zero and the shift amount is specified by the imm5u[4:0] constant. And the results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = imm5u[4:0];
+ * Rd.W[x] = Rs1.W[x] << sa;
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SLLI32(unsigned long a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("slli32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.30. SLLI32 ===== */
+
+/* ===== Inline Function Start for 4.31. SMAX32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_MISC
+ * \brief SMAX32 (SIMD 32-bit Signed Maximum)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMAX32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit signed integer elements finding maximum operations simultaneously.
+ *
+ * **Description**:\n
+ * This instruction compares the 32-bit signed integer elements in Rs1 with the 32-bit
+ * signed integer elements in Rs2 and selects the numbers that is greater than the other one. The
+ * selected results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x] = (Rs1.W[x] > Rs2.W[x])? Rs1.W[x] : Rs2.W[x];
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SMAX32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("smax32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.31. SMAX32 ===== */
+
+/* ===== Inline Function Start for 4.32.1. SMBB32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT
+ * \brief SMBB32 (Signed Multiply Bottom Word & Bottom Word)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMBB32 Rd, Rs1, Rs2
+ * SMBT32 Rd, Rs1, Rs2
+ * SMTT32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit element of a register with the signed 32-bit element of another
+ * register and write the 64-bit result to a third register.
+ * * SMBB32: bottom*bottom
+ * * SMBT32: bottom*top
+ * * SMTT32: top*top
+ *
+ * **Description**:\n
+ * For the `SMBB32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit
+ * element of Rs2. It is actually an alias of `MULSR64` instruction.
+ * For the `SMBT32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit
+ * element of Rs2.
+ * For the `SMTT32` instruction, it multiplies the top 32-bit element of Rs1 with the top 32-bit element
+ * of Rs2.
+ * The 64-bit multiplication result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as
+ * signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res = Rs1.W[0] * Rs2.W[0]; // SMBB32 res = Rs1.W[0] * Rs2.w[1]; // SMBT32 res = Rs1.W[1] * Rs2.W[1];
+ * // SMTT32 Rd = res;
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_SMBB32(unsigned long a, unsigned long b)
+{
+    register long result;
+    __ASM volatile("smbb32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.32.1. SMBB32 ===== */
+
+/* ===== Inline Function Start for 4.32.2. SMBT32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT
+ * \brief SMBT32 (Signed Multiply Bottom Word & Top Word)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMBB32 Rd, Rs1, Rs2
+ * SMBT32 Rd, Rs1, Rs2
+ * SMTT32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit element of a register with the signed 32-bit element of another
+ * register and write the 64-bit result to a third register.
+ * * SMBB32: bottom*bottom
+ * * SMBT32: bottom*top
+ * * SMTT32: top*top
+ *
+ * **Description**:\n
+ * For the `SMBB32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit
+ * element of Rs2. It is actually an alias of `MULSR64` instruction.
+ * For the `SMBT32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit
+ * element of Rs2.
+ * For the `SMTT32` instruction, it multiplies the top 32-bit element of Rs1 with the top 32-bit element
+ * of Rs2.
+ * The 64-bit multiplication result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as
+ * signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res = Rs1.W[0] * Rs2.W[0]; // SMBB32 res = Rs1.W[0] * Rs2.w[1]; // SMBT32 res = Rs1.W[1] * Rs2.W[1];
+ * // SMTT32 Rd = res;
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_SMBT32(unsigned long a, unsigned long b)
+{
+    register long result;
+    __ASM volatile("smbt32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.32.2. SMBT32 ===== */
+
+/* ===== Inline Function Start for 4.32.3. SMTT32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT
+ * \brief SMTT32 (Signed Multiply Top Word & Top Word)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMBB32 Rd, Rs1, Rs2
+ * SMBT32 Rd, Rs1, Rs2
+ * SMTT32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Multiply the signed 32-bit element of a register with the signed 32-bit element of another
+ * register and write the 64-bit result to a third register.
+ * * SMBB32: bottom*bottom
+ * * SMBT32: bottom*top
+ * * SMTT32: top*top
+ *
+ * **Description**:\n
+ * For the `SMBB32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit
+ * element of Rs2. It is actually an alias of `MULSR64` instruction.
+ * For the `SMBT32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit
+ * element of Rs2.
+ * For the `SMTT32` instruction, it multiplies the top 32-bit element of Rs1 with the top 32-bit element
+ * of Rs2.
+ * The 64-bit multiplication result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as
+ * signed integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res = Rs1.W[0] * Rs2.W[0]; // SMBB32 res = Rs1.W[0] * Rs2.w[1]; // SMBT32 res = Rs1.W[1] * Rs2.W[1];
+ * // SMTT32 Rd = res;
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_SMTT32(unsigned long a, unsigned long b)
+{
+    register long result;
+    __ASM volatile("smtt32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.32.3. SMTT32 ===== */
+
+/* ===== Inline Function Start for 4.33.1. SMDS32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC
+ * \brief SMDS32 (Signed Multiply Two Words and Subtract)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMDS32 Rd, Rs1, Rs2
+ * SMDRS32 Rd, Rs1, Rs2
+ * SMXDS32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 32-bit multiplications from the l 32-bit element of two registers; and then
+ * perform a subtraction operation between the two 64-bit results.
+ * * SMDS32: top*top - bottom*bottom
+ * * SMDRS32: bottom*bottom - top*top
+ * * SMXDS32: top*bottom - bottom*top
+ *
+ * **Description**:\n
+ * For the `SMDS32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit
+ * element of Rs2 and then subtracts the result from the result of multiplying the top 32-bit element of
+ * Rs1 with the top 32-bit element of Rs2.
+ * For the `SMDRS32` instruction, it multiplies the top 32-bit element of Rs1 with the top 32-bit
+ * element of Rs2 and then subtracts the result from the result of multiplying the bottom 32-bit
+ * element of Rs1 with the bottom 32-bit element of Rs2.
+ * For the `SMXDS32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit
+ * element of Rs2 and then subtracts the result from the result of multiplying the top 32-bit element of
+ * Rs1 with the bottom 32-bit element of Rs2.
+ * The subtraction result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed
+ * integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rt = (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // SMDS32
+ * Rt = (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); // SMDRS32
+ * Rt = (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // SMXDS32
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_SMDS32(unsigned long a, unsigned long b)
+{
+    register long result;
+    __ASM volatile("smds32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.33.1. SMDS32 ===== */
+
+/* ===== Inline Function Start for 4.33.2. SMDRS32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC
+ * \brief SMDRS32 (Signed Multiply Two Words and Reverse Subtract)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMDS32 Rd, Rs1, Rs2
+ * SMDRS32 Rd, Rs1, Rs2
+ * SMXDS32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 32-bit multiplications from the l 32-bit element of two registers; and then
+ * perform a subtraction operation between the two 64-bit results.
+ * * SMDS32: top*top - bottom*bottom
+ * * SMDRS32: bottom*bottom - top*top
+ * * SMXDS32: top*bottom - bottom*top
+ *
+ * **Description**:\n
+ * For the `SMDS32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit
+ * element of Rs2 and then subtracts the result from the result of multiplying the top 32-bit element of
+ * Rs1 with the top 32-bit element of Rs2.
+ * For the `SMDRS32` instruction, it multiplies the top 32-bit element of Rs1 with the top 32-bit
+ * element of Rs2 and then subtracts the result from the result of multiplying the bottom 32-bit
+ * element of Rs1 with the bottom 32-bit element of Rs2.
+ * For the `SMXDS32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit
+ * element of Rs2 and then subtracts the result from the result of multiplying the top 32-bit element of
+ * Rs1 with the bottom 32-bit element of Rs2.
+ * The subtraction result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed
+ * integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rt = (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // SMDS32
+ * Rt = (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); // SMDRS32
+ * Rt = (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // SMXDS32
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_SMDRS32(unsigned long a, unsigned long b)
+{
+    register long result;
+    __ASM volatile("smdrs32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.33.2. SMDRS32 ===== */
+
+/* ===== Inline Function Start for 4.33.3. SMXDS32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC
+ * \brief SMXDS32 (Signed Crossed Multiply Two Words and Subtract)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMDS32 Rd, Rs1, Rs2
+ * SMDRS32 Rd, Rs1, Rs2
+ * SMXDS32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do two signed 32-bit multiplications from the l 32-bit element of two registers; and then
+ * perform a subtraction operation between the two 64-bit results.
+ * * SMDS32: top*top - bottom*bottom
+ * * SMDRS32: bottom*bottom - top*top
+ * * SMXDS32: top*bottom - bottom*top
+ *
+ * **Description**:\n
+ * For the `SMDS32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit
+ * element of Rs2 and then subtracts the result from the result of multiplying the top 32-bit element of
+ * Rs1 with the top 32-bit element of Rs2.
+ * For the `SMDRS32` instruction, it multiplies the top 32-bit element of Rs1 with the top 32-bit
+ * element of Rs2 and then subtracts the result from the result of multiplying the bottom 32-bit
+ * element of Rs1 with the bottom 32-bit element of Rs2.
+ * For the `SMXDS32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit
+ * element of Rs2 and then subtracts the result from the result of multiplying the top 32-bit element of
+ * Rs1 with the bottom 32-bit element of Rs2.
+ * The subtraction result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed
+ * integers.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rt = (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // SMDS32
+ * Rt = (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); // SMDRS32
+ * Rt = (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // SMXDS32
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_SMXDS32(unsigned long a, unsigned long b)
+{
+    register long result;
+    __ASM volatile("smxds32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.33.3. SMXDS32 ===== */
+
+/* ===== Inline Function Start for 4.34. SMIN32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_MISC
+ * \brief SMIN32 (SIMD 32-bit Signed Minimum)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SMIN32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit signed integer elements finding minimum operations simultaneously.
+ *
+ * **Description**:\n
+ * This instruction compares the 32-bit signed integer elements in Rs1 with the 32-bit
+ * signed integer elements in Rs2 and selects the numbers that is less than the other one. The selected
+ * results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x] = (Rs1.W[x] < Rs2.W[x])? Rs1.W[x] : Rs2.W[x];
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SMIN32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("smin32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.34. SMIN32 ===== */
+
+/* ===== Inline Function Start for 4.35.1. SRA32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
+ * \brief SRA32 (SIMD 32-bit Shift Right Arithmetic)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRA32 Rd, Rs1, Rs2
+ * SRA32.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit element arithmetic right shift operations simultaneously. The shift amount is a
+ * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted
+ * results.
+ *
+ * **Description**:\n
+ * The 32-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out
+ * bits are filled with the sign-bit of the data elements. The shift amount is specified by the low-order
+ * 5-bits of the value in the Rs2 register. For the rounding operation of the `.u` form, a value of 1 is
+ * added to the most significant discarded bit of each 32-bit data element to calculate the final results.
+ * And the results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = Rs2[4:0];
+ * if (sa > 0) {
+ *   if (`.u` form) { // SRA32.u
+ *     res[31:-1] = SE33(Rs1.W[x][31:sa-1]) + 1;
+ *     Rd.W[x] = res[31:0];
+ *   else { // SRA32
+ *     Rd.W[x] = SE32(Rs1.W[x][31:sa])
+ *   }
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SRA32(unsigned long a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("sra32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.35.1. SRA32 ===== */
+
+/* ===== Inline Function Start for 4.35.2. SRA32.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
+ * \brief SRA32.u (SIMD 32-bit Rounding Shift Right Arithmetic)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRA32 Rd, Rs1, Rs2
+ * SRA32.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit element arithmetic right shift operations simultaneously. The shift amount is a
+ * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted
+ * results.
+ *
+ * **Description**:\n
+ * The 32-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out
+ * bits are filled with the sign-bit of the data elements. The shift amount is specified by the low-order
+ * 5-bits of the value in the Rs2 register. For the rounding operation of the `.u` form, a value of 1 is
+ * added to the most significant discarded bit of each 32-bit data element to calculate the final results.
+ * And the results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = Rs2[4:0];
+ * if (sa > 0) {
+ *   if (`.u` form) { // SRA32.u
+ *     res[31:-1] = SE33(Rs1.W[x][31:sa-1]) + 1;
+ *     Rd.W[x] = res[31:0];
+ *   else { // SRA32
+ *     Rd.W[x] = SE32(Rs1.W[x][31:sa])
+ *   }
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SRA32_U(unsigned long a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("sra32.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.35.2. SRA32.u ===== */
+
+/* ===== Inline Function Start for 4.36.1. SRAI32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
+ * \brief SRAI32 (SIMD 32-bit Shift Right Arithmetic Immediate)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRAI32 Rd, Rs1, imm5u
+ * SRAI32.u Rd, Rs1, imm5u
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit elements arithmetic right shift operations simultaneously. The shift amount is
+ * an immediate value. The `.u` form performs additional rounding up operations on the shifted
+ * results.
+ *
+ * **Description**:\n
+ * The 32-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out
+ * bits are filled with the sign-bit of the 32-bit data elements. The shift amount is specified by the
+ * imm5u constant. For the rounding operation of the `.u` form, a value of 1 is added to the most
+ * significant discarded bit of each 32-bit data to calculate the final results. And the results are written
+ * to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = imm5u[4:0];
+ *   if (sa > 0) {
+ *   if (`.u` form) { // SRAI32.u
+ *     res[31:-1] = SE33(Rs1.W[x][31:sa-1]) + 1;
+ *     Rd.W[x] = res[31:0];
+ *   else { // SRAI32
+ *     Rd.W[x] = SE32(Rs1.W[x][31:sa]);
+ *   }
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SRAI32(unsigned long a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("srai32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.36.1. SRAI32 ===== */
+
+/* ===== Inline Function Start for 4.36.2. SRAI32.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
+ * \brief SRAI32.u (SIMD 32-bit Rounding Shift Right Arithmetic Immediate)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRAI32 Rd, Rs1, imm5u
+ * SRAI32.u Rd, Rs1, imm5u
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit elements arithmetic right shift operations simultaneously. The shift amount is
+ * an immediate value. The `.u` form performs additional rounding up operations on the shifted
+ * results.
+ *
+ * **Description**:\n
+ * The 32-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out
+ * bits are filled with the sign-bit of the 32-bit data elements. The shift amount is specified by the
+ * imm5u constant. For the rounding operation of the `.u` form, a value of 1 is added to the most
+ * significant discarded bit of each 32-bit data to calculate the final results. And the results are written
+ * to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = imm5u[4:0];
+ *   if (sa > 0) {
+ *   if (`.u` form) { // SRAI32.u
+ *     res[31:-1] = SE33(Rs1.W[x][31:sa-1]) + 1;
+ *     Rd.W[x] = res[31:0];
+ *   else { // SRAI32
+ *     Rd.W[x] = SE32(Rs1.W[x][31:sa]);
+ *   }
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SRAI32_U(unsigned long a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("srai32.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.36.2. SRAI32.u ===== */
+
+/* ===== Inline Function Start for 4.37. SRAIW.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_NON_SIMD_32B_SHIFT
+ * \brief SRAIW.u (Rounding Shift Right Arithmetic Immediate Word)
+ * \details
+ * **Type**: DSP (RV64 only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRAIW.u Rd, Rs1, imm5u
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Perform a 32-bit arithmetic right shift operation with rounding. The shift amount is an
+ * immediate value.
+ *
+ * **Description**:\n
+ * This instruction right-shifts the lower 32-bit content of Rs1 arithmetically. The shifted
+ * out bits are filled with the sign-bit Rs1(31) and the shift amount is specified by the imm5u constant.
+ * For the rounding operation, a value of 1 is added to the most significant discarded bit of the data to
+ * calculate the final result. And the result is sign-extended and written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = imm5u;
+ * if (sa != 0) {
+ *   res[31:-1] = SE33(Rs1[31:(sa-1)]) + 1;
+ *   Rd = SE32(res[31:0]);
+ * } else {
+ *   Rd = SE32(Rs1.W[0]);
+ * }
+ * ~~~
+ *
+ * \param [in]  a    int type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in long type
+ */
+__STATIC_FORCEINLINE long __RV_SRAIW_U(int a, unsigned int b)
+{
+    register long result;
+    __ASM volatile("sraiw.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.37. SRAIW.u ===== */
+
+/* ===== Inline Function Start for 4.38.1. SRL32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
+ * \brief SRL32 (SIMD 32-bit Shift Right Logical)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRL32 Rd, Rs1, Rs2
+ * SRL32.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit element logical right shift operations simultaneously. The shift amount is a
+ * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted
+ * results.
+ *
+ * **Description**:\n
+ * The 32-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits
+ * are filled with zero. The shift amount is specified by the low-order 5-bits of the value in the Rs2
+ * register. For the rounding operation of the `.u` form, a value of 1 is added to the most significant
+ * discarded bit of each 32-bit data element to calculate the final results. And the results are written to
+ * Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = Rs2[4:0];
+ * if (sa > 0) {
+ *   if (`.u` form) { // SRA32.u
+ *     res[31:-1] = ZE33(Rs1.W[x][31:sa-1]) + 1;
+ *     Rd.W[x] = res[31:0];
+ *   else { // SRA32
+ *     Rd.W[x] = ZE32(Rs1.W[x][31:sa])
+ *   }
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SRL32(unsigned long a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("srl32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.38.1. SRL32 ===== */
+
+/* ===== Inline Function Start for 4.38.2. SRL32.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
+ * \brief SRL32.u (SIMD 32-bit Rounding Shift Right Logical)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRL32 Rd, Rs1, Rs2
+ * SRL32.u Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit element logical right shift operations simultaneously. The shift amount is a
+ * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted
+ * results.
+ *
+ * **Description**:\n
+ * The 32-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits
+ * are filled with zero. The shift amount is specified by the low-order 5-bits of the value in the Rs2
+ * register. For the rounding operation of the `.u` form, a value of 1 is added to the most significant
+ * discarded bit of each 32-bit data element to calculate the final results. And the results are written to
+ * Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = Rs2[4:0];
+ * if (sa > 0) {
+ *   if (`.u` form) { // SRA32.u
+ *     res[31:-1] = ZE33(Rs1.W[x][31:sa-1]) + 1;
+ *     Rd.W[x] = res[31:0];
+ *   else { // SRA32
+ *     Rd.W[x] = ZE32(Rs1.W[x][31:sa])
+ *   }
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SRL32_U(unsigned long a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("srl32.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.38.2. SRL32.u ===== */
+
+/* ===== Inline Function Start for 4.39.1. SRLI32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
+ * \brief SRLI32 (SIMD 32-bit Shift Right Logical Immediate)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRLI32 Rd, Rs1, imm5u
+ * SRLI32.u Rd, Rs1, imm5u
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit elements logical right shift operations simultaneously. The shift amount is an
+ * immediate value. The `.u` form performs additional rounding up operations on the shifted results.
+ *
+ * **Description**:\n
+ * The 32-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits
+ * are filled with zero. The shift amount is specified by the imm5u constant. For the rounding
+ * operation of the `.u` form, a value of 1 is added to the most significant discarded bit of each 32-bit
+ * data to calculate the final results. And the results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = imm5u[4:0];
+ * if (sa > 0) {
+ *   if (`.u` form) { // SRLI32.u
+ *     res[31:-1] = ZE33(Rs1.W[x][31:sa-1]) + 1;
+ *     Rd.W[x] = res[31:0];
+ *   else { // SRLI32
+ *     Rd.W[x] = ZE32(Rs1.W[x][31:sa]);
+ *   }
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SRLI32(unsigned long a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("srli32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.39.1. SRLI32 ===== */
+
+/* ===== Inline Function Start for 4.39.2. SRLI32.u ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
+ * \brief SRLI32.u (SIMD 32-bit Rounding Shift Right Logical Immediate)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SRLI32 Rd, Rs1, imm5u
+ * SRLI32.u Rd, Rs1, imm5u
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit elements logical right shift operations simultaneously. The shift amount is an
+ * immediate value. The `.u` form performs additional rounding up operations on the shifted results.
+ *
+ * **Description**:\n
+ * The 32-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits
+ * are filled with zero. The shift amount is specified by the imm5u constant. For the rounding
+ * operation of the `.u` form, a value of 1 is added to the most significant discarded bit of each 32-bit
+ * data to calculate the final results. And the results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * sa = imm5u[4:0];
+ * if (sa > 0) {
+ *   if (`.u` form) { // SRLI32.u
+ *     res[31:-1] = ZE33(Rs1.W[x][31:sa-1]) + 1;
+ *     Rd.W[x] = res[31:0];
+ *   else { // SRLI32
+ *     Rd.W[x] = ZE32(Rs1.W[x][31:sa]);
+ *   }
+ * } else {
+ *   Rd = Rs1;
+ * }
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned int type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SRLI32_U(unsigned long a, unsigned int b)
+{
+    register unsigned long result;
+    __ASM volatile("srli32.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.39.2. SRLI32.u ===== */
+
+/* ===== Inline Function Start for 4.40. STAS32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief STAS32 (SIMD 32-bit Straight Addition & Subtraction)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * STAS32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit integer element addition and 32-bit integer element subtraction in a 64-bit
+ * chunk simultaneously. Operands are from corresponding 32-bit elements.
+ *
+ * **Description**:\n
+ * This instruction adds the 32-bit integer element in [63:32] of Rs1 with the 32-bit
+ * integer element in [63:32] of Rs2, and writes the result to [63:32] of Rd; at the same time, it subtracts
+ * the 32-bit integer element in [31:0] of Rs2 from the 32-bit integer element in [31:0] of Rs1, and
+ * writes the result to [31:0] of Rd.
+ *
+ * **Note**:\n
+ * This instruction can be used for either signed or unsigned operations.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[1] = Rs1.W[1] + Rs2.W[1];
+ * Rd.W[0] = Rs1.W[0] - Rs2.W[0];
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_STAS32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("stas32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.40. STAS32 ===== */
+
+/* ===== Inline Function Start for 4.41. STSA32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief STSA32 (SIMD 32-bit Straight Subtraction & Addition)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * STSA32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit integer element subtraction and 32-bit integer element addition in a 64-bit
+ * chunk simultaneously. Operands are from corresponding 32-bit elements.
+ * *Description: *
+ * This instruction subtracts the 32-bit integer element in [63:32] of Rs2 from the 32-bit integer
+ * element in [63:32] of Rs1, and writes the result to [63:32] of Rd; at the same time, it adds the 32-bit
+ * integer element in [31:0] of Rs1 with the 32-bit integer element in [31:0] of Rs2, and writes the result
+ * to [31:0] of Rd
+ *
+ * **Note**:\n
+ * This instruction can be used for either signed or unsigned operations.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[1] = Rs1.W[1] - Rs2.W[1];
+ * Rd.W[0] = Rs1.W[0] + Rs2.W[0];
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_STSA32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("stsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.41. STSA32 ===== */
+
+/* ===== Inline Function Start for 4.42. SUB32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief SUB32 (SIMD 32-bit Subtraction)
+ * \details
+ * **Type**: DSP (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * SUB32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit integer element subtractions simultaneously.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 32-bit integer elements in Rs2 from the 32-bit integer
+ * elements in Rs1, and then writes the results to Rd.
+ *
+ * **Note**:\n
+ * This instruction can be used for either signed or unsigned subtraction.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x] = Rs1.W[x] - Rs2.W[x];
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_SUB32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("sub32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.42. SUB32 ===== */
+
+/* ===== Inline Function Start for 4.43. UKADD32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief UKADD32 (SIMD 32-bit Unsigned Saturating Addition)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UKADD32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit unsigned integer element saturating additions simultaneously.
+ *
+ * **Description**:\n
+ * This instruction adds the 32-bit unsigned integer elements in Rs1 with the 32-bit
+ * unsigned integer elements in Rs2. If any of the results are beyond the 32-bit unsigned number
+ * range (0 <= RES <= 2^32-1), they are saturated to the range and the OV bit is set to 1. The saturated
+ * results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[x] = Rs1.W[x] + Rs2.W[x];
+ * if (res[x] > (2^32)-1) {
+ *   res[x] = (2^32)-1;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_UKADD32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("ukadd32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.43. UKADD32 ===== */
+
+/* ===== Inline Function Start for 4.44. UKCRAS32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief UKCRAS32 (SIMD 32-bit Unsigned Saturating Cross Addition & Subtraction)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UKCRAS32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do one 32-bit unsigned integer element saturating addition and one 32-bit unsigned
+ * integer element saturating subtraction in a 64-bit chunk simultaneously. Operands are from crossed
+ * 32-bit elements.
+ *
+ * **Description**:\n
+ * This instruction adds the 32-bit unsigned integer element in [63:32] of Rs1 with the 32-
+ * bit unsigned integer element in [31:0] of Rs2; at the same time, it subtracts the 32-bit unsigned
+ * integer element in [63:32] of Rs2 from the 32-bit unsigned integer element in [31:0] Rs1. If any of the
+ * results are beyond the 32-bit unsigned number range (0 <= RES <= 2^32-1), they are saturated to the
+ * range and the OV bit is set to 1. The saturated results are written to [63:32] of Rd for addition and
+ * [31:0] of Rd for subtraction.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res1 = Rs1.W[1] + Rs2.W[0];
+ * res2 = Rs1.W[0] - Rs2.W[1];
+ * if (res1 > (2^32)-1) {
+ *   res1 = (2^32)-1;
+ *   OV = 1;
+ * }
+ * if (res2 < 0) {
+ *   res2 = 0;
+ *   OV = 1;
+ * }
+ * Rd.W[1] = res1;
+ * Rd.W[0] = res2;
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_UKCRAS32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("ukcras32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.44. UKCRAS32 ===== */
+
+/* ===== Inline Function Start for 4.45. UKCRSA32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief UKCRSA32 (SIMD 32-bit Unsigned Saturating Cross Subtraction & Addition)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UKCRSA32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do one 32-bit unsigned integer element saturating subtraction and one 32-bit unsigned
+ * integer element saturating addition in a 64-bit chunk simultaneously. Operands are from crossed
+ * 32-bit elements.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 32-bit unsigned integer element in [31:0] of Rs2 from the
+ * 32-bit unsigned integer element in [63:32] of Rs1; at the same time, it adds the 32-bit unsigned
+ * integer element in [63:32] of Rs2 with the 32-bit unsigned integer element in [31:0] Rs1. If any of the
+ * results are beyond the 32-bit unsigned number range (0 <= RES <= 2^32-1), they are saturated to the
+ * range and the OV bit is set to 1. The saturated results are written to [63:32] of Rd for subtraction and
+ * [31:0] of Rd for addition.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res1 = Rs1.W[1] - Rs2.W[0];
+ * res2 = Rs1.W[0] + Rs2.W[1];
+ * if (res1 < 0) {
+ *   res1 = 0;
+ *   OV = 1;
+ * } else if (res2 > (2^32)-1) {
+ *   res2 = (2^32)-1;
+ *   OV = 1;
+ * }
+ * Rd.W[1] = res1;
+ * Rd.W[0] = res2;
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_UKCRSA32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("ukcrsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.45. UKCRSA32 ===== */
+
+/* ===== Inline Function Start for 4.46. UKSTAS32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief UKSTAS32 (SIMD 32-bit Unsigned Saturating Straight Addition & Subtraction)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UKSTAS32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do one 32-bit unsigned integer element saturating addition and one 32-bit unsigned
+ * integer element saturating subtraction in a 64-bit chunk simultaneously. Operands are from
+ * corresponding 32-bit elements.
+ *
+ * **Description**:\n
+ * This instruction adds the 32-bit unsigned integer element in [63:32] of Rs1 with the 32-
+ * bit unsigned integer element in [63:32] of Rs2; at the same time, it subtracts the 32-bit unsigned
+ * integer element in [31:0] of Rs2 from the 32-bit unsigned integer element in [31:0] Rs1. If any of the
+ * results are beyond the 32-bit unsigned number range (0 <= RES <= 2^32-1), they are saturated to the
+ * range and the OV bit is set to 1. The saturated results are written to [63:32] of Rd for addition and
+ * [31:0] of Rd for subtraction.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res1 = Rs1.W[1] + Rs2.W[1];
+ * res2 = Rs1.W[0] - Rs2.W[0];
+ * if (res1 > (2^32)-1) {
+ *   res1 = (2^32)-1;
+ *   OV = 1;
+ * }
+ * if (res2 < 0) {
+ *   res2 = 0;
+ *   OV = 1;
+ * }
+ * Rd.W[1] = res1;
+ * Rd.W[0] = res2;
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_UKSTAS32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("ukstas32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.46. UKSTAS32 ===== */
+
+/* ===== Inline Function Start for 4.47. UKSTSA32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief UKSTSA32 (SIMD 32-bit Unsigned Saturating Straight Subtraction & Addition)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UKSTSA32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do one 32-bit unsigned integer element saturating subtraction and one 32-bit unsigned
+ * integer element saturating addition in a 64-bit chunk simultaneously. Operands are from
+ * corresponding 32-bit elements.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 32-bit unsigned integer element in [63:32] of Rs2 from
+ * the 32-bit unsigned integer element in [63:32] of Rs1; at the same time, it adds the 32-bit unsigned
+ * integer element in [31:0] of Rs2 with the 32-bit unsigned integer element in [31:0] Rs1. If any of the
+ * results are beyond the 32-bit unsigned number range (0 <= RES <= 2^32-1), they are saturated to the
+ * range and the OV bit is set to 1. The saturated results are written to [63:32] of Rd for subtraction and
+ * [31:0] of Rd for addition.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res1 = Rs1.W[1] - Rs2.W[1];
+ * res2 = Rs1.W[0] + Rs2.W[0];
+ * if (res1 < 0) {
+ *   res1 = 0;
+ *   OV = 1;
+ * } else if (res2 > (2^32)-1) {
+ *   res2 = (2^32)-1;
+ *   OV = 1;
+ * }
+ * Rd.W[1] = res1;
+ * Rd.W[0] = res2;
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_UKSTSA32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("ukstsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.47. UKSTSA32 ===== */
+
+/* ===== Inline Function Start for 4.48. UKSUB32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief UKSUB32 (SIMD 32-bit Unsigned Saturating Subtraction)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UKSUB32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit unsigned integer elements saturating subtractions simultaneously.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 32-bit unsigned integer elements in Rs2 from the 32-bit
+ * unsigned integer elements in Rs1. If any of the results are beyond the 32-bit unsigned number
+ * range (0 <= RES <= 2^32-1), they are saturated to the range and the OV bit is set to 1. The saturated
+ * results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[x] = Rs1.W[x] - Rs2.W[x];
+ * if (res[x] < 0) {
+ *   res[x] = 0;
+ *   OV = 1;
+ * }
+ * Rd.W[x] = res[x];
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_UKSUB32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("uksub32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.48. UKSUB32 ===== */
+
+/* ===== Inline Function Start for 4.49. UMAX32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_MISC
+ * \brief UMAX32 (SIMD 32-bit Unsigned Maximum)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UMAX32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit unsigned integer elements finding maximum operations simultaneously.
+ *
+ * **Description**:\n
+ * This instruction compares the 32-bit unsigned integer elements in Rs1 with the 32-bit
+ * unsigned integer elements in Rs2 and selects the numbers that is greater than the other one. The
+ * selected results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x] = (Rs1.W[x] u> Rs2.W[x])? Rs1.W[x] : Rs2.W[x];
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_UMAX32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("umax32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.49. UMAX32 ===== */
+
+/* ===== Inline Function Start for 4.50. UMIN32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_MISC
+ * \brief UMIN32 (SIMD 32-bit Unsigned Minimum)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * UMIN32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit unsigned integer elements finding minimum operations simultaneously.
+ *
+ * **Description**:\n
+ * This instruction compares the 32-bit unsigned integer elements in Rs1 with the 32-bit
+ * unsigned integer elements in Rs2 and selects the numbers that is less than the other one. The
+ * selected results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x] = (Rs1.W[x] > 1;
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_URADD32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("uradd32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.51. URADD32 ===== */
+
+/* ===== Inline Function Start for 4.52. URCRAS32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief URCRAS32 (SIMD 32-bit Unsigned Halving Cross Addition & Subtraction)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * URCRAS32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit unsigned integer element addition and 32-bit unsigned integer element
+ * subtraction in a 64-bit chunk simultaneously. Operands are from crossed 32-bit elements. The
+ * results are halved to avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction adds the 32-bit unsigned integer element in [63:32] of Rs1 with the 32-
+ * bit unsigned integer element in [31:0] of Rs2, and subtracts the 32-bit unsigned integer element in
+ * [63:32] of Rs2 from the 32-bit unsigned integer element in [31:0] of Rs1. The element results are first
+ * logically right-shifted by 1 bit and then written to [63:32] of Rd for addition and [31:0] of Rd for
+ * subtraction.
+ *
+ * **Examples**:\n
+ * ~~~
+ * Please see `URADD32` and `URSUB32` instructions.
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[1] = (Rs1.W[1] + Rs2.W[0]) u>> 1;
+ * Rd.W[0] = (Rs1.W[0] - Rs2.W[1]) u>> 1;
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_URCRAS32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("urcras32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.52. URCRAS32 ===== */
+
+/* ===== Inline Function Start for 4.53. URCRSA32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief URCRSA32 (SIMD 32-bit Unsigned Halving Cross Subtraction & Addition)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * URCRSA32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit unsigned integer element subtraction and 32-bit unsigned integer element
+ * addition in a 64-bit chunk simultaneously. Operands are from crossed 32-bit elements. The results
+ * are halved to avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 32-bit unsigned integer element in [31:0] of Rs2 from the
+ * 32-bit unsigned integer element in [63:32] of Rs1, and adds the 32-bit unsigned element integer in
+ * [31:0] of Rs1 with the 32-bit unsigned integer element in [63:32] of Rs2. The two results are first
+ * logically right-shifted by 1 bit and then written to [63:32] of Rd for subtraction and [31:0] of Rd for
+ * addition.
+ *
+ * **Examples**:\n
+ * ~~~
+ * Please see `URADD32` and `URSUB32` instructions.
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[1] = (Rs1.W[1] - Rs2.W[0]) u>> 1;
+ * Rd.W[0] = (Rs1.W[0] + Rs2.W[1]) u>> 1;
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_URCRSA32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("urcrsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.53. URCRSA32 ===== */
+
+/* ===== Inline Function Start for 4.54. URSTAS32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief URSTAS32 (SIMD 32-bit Unsigned Halving Straight Addition & Subtraction)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * URSTAS32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit unsigned integer element addition and 32-bit unsigned integer element
+ * subtraction in a 64-bit chunk simultaneously. Operands are from corresponding 32-bit elements.
+ * The results are halved to avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction adds the 32-bit unsigned integer element in [63:32] of Rs1 with the 32-
+ * bit unsigned integer element in [63:32] of Rs2, and subtracts the 32-bit unsigned integer element in
+ * [31:0] of Rs2 from the 32-bit unsigned integer element in [31:0] of Rs1. The element results are first
+ * logically right-shifted by 1 bit and then written to [63:32] of Rd for addition and [31:0] of Rd for
+ * subtraction.
+ *
+ * **Examples**:\n
+ * ~~~
+ * Please see `URADD32` and `URSUB32` instructions.
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[1] = (Rs1.W[1] + Rs2.W[1]) u>> 1;
+ * Rd.W[0] = (Rs1.W[0] - Rs2.W[0]) u>> 1;
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_URSTAS32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("urstas32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.54. URSTAS32 ===== */
+
+/* ===== Inline Function Start for 4.55. URSTSA32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief URSTSA32 (SIMD 32-bit Unsigned Halving Straight Subtraction & Addition)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * URSTSA32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit unsigned integer element subtraction and 32-bit unsigned integer element
+ * addition in a 64-bit chunk simultaneously. Operands are from corresponding 32-bit elements. The
+ * results are halved to avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 32-bit unsigned integer element in [63:32] of Rs2 from
+ * the 32-bit unsigned integer element in [63:32] of Rs1, and adds the 32-bit unsigned element integer
+ * in [31:0] of Rs1 with the 32-bit unsigned integer element in [31:0] of Rs2. The two results are first
+ * logically right-shifted by 1 bit and then written to [63:32] of Rd for subtraction and [31:0] of Rd for
+ * addition.
+ *
+ * **Examples**:\n
+ * ~~~
+ * Please see `URADD32` and `URSUB32` instructions.
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[1] = (Rs1.W[1] - Rs2.W[1]) u>> 1;
+ * Rd.W[0] = (Rs1.W[0] + Rs2.W[0]) u>> 1;
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_URSTSA32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("urstsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.55. URSTSA32 ===== */
+
+/* ===== Inline Function Start for 4.56. URSUB32 ===== */
+/**
+ * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
+ * \brief URSUB32 (SIMD 32-bit Unsigned Halving Subtraction)
+ * \details
+ * **Type**: SIMD (RV64 Only)
+ *
+ * **Syntax**:\n
+ * ~~~
+ * URSUB32 Rd, Rs1, Rs2
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 32-bit unsigned integer element subtractions simultaneously. The results are halved to
+ * avoid overflow or saturation.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 32-bit unsigned integer elements in Rs2 from the 32-bit
+ * unsigned integer elements in Rs1. The results are first logically right-shifted by 1 bit and then
+ * written to Rd.
+ *
+ * **Examples**:\n
+ * ~~~
+ * * Ra = 0x7FFFFFFF, Rb = 0x80000000, Rt = 0xFFFFFFFF
+ * * Ra = 0x80000000, Rb = 0x7FFFFFFF, Rt = 0x00000000
+ * * Ra = 0x80000000, Rb = 0x40000000, Rt = 0x20000000
+ * ~~~
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x] = (Rs1.W[x] - Rs2.W[x]) u>> 1;
+ * for RV64: x=1...0
+ * ~~~
+ *
+ * \param [in]  a    unsigned long type of value stored in a
+ * \param [in]  b    unsigned long type of value stored in b
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_URSUB32(unsigned long a, unsigned long b)
+{
+    register unsigned long result;
+    __ASM volatile("ursub32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for 4.56. URSUB32 ===== */
+
+#endif /* __RISCV_XLEN == 64 */
+
+
+#if (__RISCV_XLEN == 32) || defined(__ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__)
+/* XXXXX Nuclei Extended DSP Instructions for RV32 XXXXX */
+/**
+ * \defgroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM      Nuclei Customized DSP Instructions
+ * \ingroup  NMSIS_Core_DSP_Intrinsic
+ * \brief    (RV32 only)Nuclei Customized DSP Instructions
+ * \details  This is Nuclei customized DSP instructions only for RV32
+ */
+/* ===== Inline Function Start for A.1. DKHM8 ===== */
+/**
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
+ * \brief DKHM8 (64-bit SIMD Signed Saturating Q7 Multiply)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * DKHM8 Rd, Rs1, Rs2
+ * # Rd, Rs1, Rs2 are all even/odd pair of registers
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do Q7xQ7 element multiplications simultaneously. The Q14 results are then reduced to Q7
+ * numbers again.
+ *
+ * **Description**:\n
+ * For the `DKHM8` instruction, multiply the top 8-bit Q7 content of 16-bit chunks in Rs1
+ * with the top 8-bit Q7 content of 16-bit chunks in Rs2. At the same time, multiply the bottom 8-bit Q7
+ * content of 16-bit chunks in Rs1 with the bottom 8-bit Q7 content of 16-bit chunks in Rs2.
+ *
+ * The Q14 results are then right-shifted 7-bits and saturated into Q7 values. The Q7 results are then
+ * written into Rd. When both the two Q7 inputs of a multiplication are 0x80, saturation will happen.
+ * The result will be saturated to 0x7F and the overflow flag OV will be set.
+ *
+ * **Operations**:\n
+ * ~~~
+ * op1t = Rs1.B[x+1]; op2t = Rs2.B[x+1]; // top
+ * op1b = Rs1.B[x]; op2b = Rs2.B[x]; // bottom
+ * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) {
+ *   if (0x80 != aop | 0x80 != bop) {
+ *     res = (aop s* bop) >> 7;
+ *   } else {
+ *     res= 0x7F;
+ *     OV = 1;
+ *   }
+ * }
+ * Rd.H[x/2] = concat(rest, resb);
+ * for RV32, x=0,2,4,6
+ * ~~~
+ *
+ * \param [in]  a unsigned long long type of value stored in a
+ * \param [in]  b unsigned long long type of value stored in b
+ * \return value stored in unsigned long long type
+ */
+__STATIC_FORCEINLINE unsigned long long __RV_DKHM8(unsigned long long a, unsigned long long b)
+{
+    unsigned long long result;
+    __ASM volatile("dkhm8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for A.1. DKHM8 ===== */
+
+/* ===== Inline Function Start for A.2. DKHM16 ===== */
+/**
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
+ * \brief DKHM16 (64-bit SIMD Signed Saturating Q15 Multiply)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * DKHM16 Rd, Rs1, Rs2
+ * # Rd, Rs1, Rs2 are all even/odd pair of registers
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do Q15xQ15 element multiplications simultaneously. The Q30 results are then reduced to
+ * Q15 numbers again.
+ *
+ * **Description**:\n
+ * For the `DKHM16` instruction, multiply the top 16-bit Q15 content of 32-bit chunks in
+ * Rs1 with the top 16-bit Q15 content of 32-bit chunks in Rs2. At the same time, multiply the bottom
+ * 16-bit Q15 content of 32-bit chunks in Rs1 with the bottom 16-bit Q15 content of 32-bit chunks in
+ * Rs2.
+ *
+ * The Q30 results are then right-shifted 15-bits and saturated into Q15 values. The Q15 results are
+ * then written into Rd. When both the two Q15 inputs of a multiplication are 0x8000, saturation will
+ * happen. The result will be saturated to 0x7FFF and the overflow flag OV will be set.
+ *
+ * **Operations**:\n
+ * ~~~
+ * op1t = Rs1.H[x+1]; op2t = Rs2.H[x+1]; // top
+ * op1b = Rs1.H[x]; op2b = Rs2.H[x]; // bottom
+ * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) {
+ *   if (0x8000 != aop | 0x8000 != bop) {
+ *     res = (aop s* bop) >> 15;
+ *   } else {
+ *     res= 0x7FFF;
+ *     OV = 1;
+ *   }
+ * }
+ * Rd.W[x/2] = concat(rest, resb);
+ * for RV32: x=0, 2
+ * ~~~
+ *
+ * \param [in]  a unsigned long long type of value stored in a
+ * \param [in]  b unsigned long long type of value stored in b
+ * \return value stored in unsigned long long type
+ */
+__STATIC_FORCEINLINE unsigned long long __RV_DKHM16(unsigned long long a, unsigned long long b)
+{
+    unsigned long long result;
+    __ASM volatile("dkhm16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for A.2. DKHM16 ===== */
+
+/* ===== Inline Function Start for A.3. DKABS8 ===== */
+/**
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
+ * \brief DKABS8 (64-bit SIMD 8-bit Saturating Absolute)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * DKABS8 Rd, Rs1
+ * # Rd, Rs1 are all even/odd pair of registers
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Get the absolute value of 8-bit signed integer elements simultaneously.
+ *
+ * **Description**:\n
+ * This instruction calculates the absolute value of 8-bit signed integer elements stored
+ * in Rs1 and writes the element results to Rd. If the input number is 0x80, this instruction generates
+ * 0x7f as the output and sets the OV bit to 1.
+ *
+ * **Operations**:\n
+ * ~~~
+ * src = Rs1.B[x];
+ * if (src == 0x80) {
+ *   src = 0x7f;
+ *   OV = 1;
+ * } else if (src[7] == 1)
+ *   src = -src;
+ * }
+ * Rd.B[x] = src;
+ * for RV32: x=7...0,
+ * ~~~
+ *
+ * \param [in]  a unsigned long long type of value stored in a
+ * \return value stored in unsigned long long type
+ */
+__STATIC_FORCEINLINE unsigned long long __RV_DKABS8(unsigned long long a)
+{
+    unsigned long long result;
+    __ASM volatile("dkabs8 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for A.3. DKABS8 ===== */
+
+/* ===== Inline Function Start for A.4. DKABS16 ===== */
+/**
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
+ * \brief DKABS16 (64-bit SIMD 16-bit Saturating Absolute)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * DKABS16 Rd, Rs1
+ * # Rd, Rs1 are all even/odd pair of registers
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Get the absolute value of 16-bit signed integer elements simultaneously.
+ *
+ * **Description**:\n
+ * This instruction calculates the absolute value of 16-bit signed integer elements stored
+ * in Rs1 and writes the element results to Rd. If the input number is 0x8000, this instruction
+ * generates 0x7fff as the output and sets the OV bit to 1.
+ *
+ * **Operations**:\n
+ * ~~~
+ * src = Rs1.H[x];
+ * if (src == 0x8000) {
+ *   src = 0x7fff;
+ *   OV = 1;
+ * } else if (src[15] == 1)
+ *   src = -src;
+ * }
+ * Rd.H[x] = src;
+ * for RV32: x=3...0,
+ * ~~~
+ *
+ * \param [in]  a unsigned long long type of value stored in a
+ * \return value stored in unsigned long long type
+ */
+__STATIC_FORCEINLINE unsigned long long __RV_DKABS16(unsigned long long a)
+{
+    unsigned long long result;
+    __ASM volatile("dkabs16 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for A.4. DKABS16 ===== */
+
+/* ===== Inline Function Start for A.5. DKSLRA8 ===== */
+/**
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
+ * \brief DKSLRA8 (64-bit SIMD 8-bit Shift Left Logical with Saturation or Shift Right Arithmetic)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * DKSLRA8 Rd, Rs1, Rs2
+ * # Rd, Rs1 are all even/odd pair of registers
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit elements logical left (positive) or arithmetic right (negative) shift operation with
+ * Q7 saturation for the left shift.
+ *
+ * **Description**:\n
+ * The 8-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically
+ * based on the value of Rs2[3:0]. Rs2[3:0] is in the signed range of [-2^3, 2^3-1]. A positive Rs2[3:0] means
+ * logical left shift and a negative Rs2[3:0] means arithmetic right shift. The shift amount is the
+ * absolute value of Rs2[3:0]. However, the behavior of `Rs2[3:0]==-2^3 (0x8)` is defined to be
+ * equivalent to the behavior of `Rs2[3:0]==-(2^3-1) (0x9)`.
+ * The left-shifted results are saturated to the 8-bit signed integer range of [-2^7, 2^7-1].
+ * If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:4] will not affect
+ * this instruction.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if (Rs2[3:0] < 0) {
+ *   sa = -Rs2[3:0];
+ *   sa = (sa == 8)? 7 : sa;
+ *   Rd.B[x] = SE8(Rs1.B[x][7:sa]);
+ * } else {
+ *   sa = Rs2[2:0];
+ *   res[(7+sa):0] = Rs1.B[x] <<(logic) sa;
+ *   if (res > (2^7)-1) {
+ *     res[7:0] = 0x7f; OV = 1;
+ *   } else if (res < -2^7) {
+ *     res[7:0] = 0x80; OV = 1;
+ *   }
+ *   Rd.B[x] = res[7:0];
+ * }
+ * for RV32: x=7...0,
+ * ~~~
+ *
+ * \param [in]  a unsigned long long type of value stored in a
+ * \param [in]  b int type of value stored in b
+ * \return value stored in unsigned long long type
+ */
+__STATIC_FORCEINLINE unsigned long long __RV_DKSLRA8(unsigned long long a, int b)
+{
+    unsigned long long result;
+    __ASM volatile("dkslra8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for A.5. DKSLRA8 ===== */
+
+/* ===== Inline Function Start for A.6. DKSLRA16 ===== */
+/**
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
+ * \brief DKSLRA16 (64-bit SIMD 16-bit Shift Left Logical with Saturation or Shift Right Arithmetic)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * DKSLRA16 Rd, Rs1, Rs2
+ * # Rd, Rs1 are all even/odd pair of registers
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit elements logical left (positive) or arithmetic right (negative) shift operation with
+ * Q15 saturation for the left shift.
+ *
+ * **Description**:\n
+ * The 16-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically
+ * based on the value of Rs2[4:0]. Rs2[4:0] is in the signed range of [-2^4, 2^4-1]. A positive Rs2[4:0] means
+ * logical left shift and a negative Rs2[4:0] means arithmetic right shift. The shift amount is the
+ * absolute value of Rs2[4:0]. However, the behavior of `Rs2[4:0]==-2^4 (0x10)` is defined to be
+ * equivalent to the behavior of `Rs2[4:0]==-(2^4-1) (0x11)`.
+ * The left-shifted results are saturated to the 16-bit signed integer range of [-2^15, 2^15-1].
+ * After the shift, saturation, or rounding, the final results are written to
+ * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:5] will not affect
+ * this instruction.
+ *
+ * **Operations**:\n
+ * ~~~
+ * if (Rs2[4:0] < 0) {
+ *   sa = -Rs2[4:0];
+ *   sa = (sa == 16)? 15 : sa;
+ *   Rd.H[x] = SE16(Rs1.H[x][15:sa]);
+ * } else {
+ *   sa = Rs2[3:0];
+ *   res[(15+sa):0] = Rs1.H[x] <<(logic) sa;
+ *   if (res > (2^15)-1) {
+ *     res[15:0] = 0x7fff; OV = 1;
+ *   } else if (res < -2^15) {
+ *     res[15:0] = 0x8000; OV = 1;
+ *   }
+ *   d.H[x] = res[15:0];
+ * }
+ * for RV32: x=3...0,
+ * ~~~
+ *
+ * \param [in]  a unsigned long long type of value stored in a
+ * \param [in]  b int type of value stored in b
+ * \return value stored in unsigned long long type
+ */
+__STATIC_FORCEINLINE unsigned long long __RV_DKSLRA16(unsigned long long a, int b)
+{
+    unsigned long long result;
+    __ASM volatile("dkslra16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for A.6. DKSLRA16 ===== */
+
+/* ===== Inline Function Start for A.7. DKADD8 ===== */
+/**
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
+ * \brief DKADD8 (64-bit SIMD 8-bit Signed Saturating Addition)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * DKADD8 Rd, Rs1, Rs2
+ * # Rd, Rs1, Rs2 are all even/odd pair of registers
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit signed integer element saturating additions simultaneously.
+ *
+ * **Description**:\n
+ * This instruction adds the 8-bit signed integer elements in Rs1 with the 8-bit signed
+ * integer elements in Rs2. If any of the results are beyond the Q7 number range (-2^7 <= Q7 <= 2^7-1), they
+ * are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[x] = Rs1.B[x] + Rs2.B[x];
+ * if (res[x] > 127) {
+ *   res[x] = 127;
+ *   OV = 1;
+ * } else if (res[x] < -128) {
+ *   res[x] = -128;
+ *   OV = 1;
+ * }
+ * Rd.B[x] = res[x];
+ * for RV32: x=7...0,
+ * ~~~
+ *
+ * \param [in]  a unsigned long long type of value stored in a
+ * \param [in]  b unsigned long long type of value stored in b
+ * \return value stored in unsigned long long type
+ */
+__STATIC_FORCEINLINE unsigned long long __RV_DKADD8(unsigned long long a, unsigned long long b)
+{
+    unsigned long long result;
+    __ASM volatile("dkadd8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for A.7. DKADD8 ===== */
+
+/* ===== Inline Function Start for A.8. DKADD16 ===== */
+/**
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
+ * \brief DKADD16 (64-bit SIMD 16-bit Signed Saturating Addition)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * DKADD16 Rd, Rs1, Rs2
+ * # Rd, Rs1, Rs2 are all even/odd pair of registers
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit signed integer element saturating additions simultaneously.
+ *
+ * **Description**:\n
+ * This instruction adds the 16-bit signed integer elements in Rs1 with the 16-bit signed
+ * integer elements in Rs2. If any of the results are beyond the Q15 number range (-2^15 <= Q15 <= 2^15-1),
+ * they are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[x] = Rs1.H[x] + Rs2.H[x];
+ * if (res[x] > 32767) {
+ *   res[x] = 32767;
+ *   OV = 1;
+ * } else if (res[x] < -32768) {
+ *   res[x] = -32768;
+ *   OV = 1;
+ * }
+ * Rd.H[x] = res[x];
+ * for RV32: x=3...0,
+ * ~~~
+ *
+ * \param [in]  a unsigned long long type of value stored in a
+ * \param [in]  b unsigned long long type of value stored in b
+ * \return value stored in unsigned long long type
+ */
+__STATIC_FORCEINLINE unsigned long long __RV_DKADD16(unsigned long long a, unsigned long long b)
+{
+    unsigned long long result;
+    __ASM volatile("dkadd16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for A.8. DKADD16 ===== */
+
+/* ===== Inline Function Start for A.10. DKSUB8 ===== */
+/**
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
+ * \brief DKSUB8 (64-bit SIMD 8-bit Signed Saturating Subtraction)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * DKSUB8 Rd, Rs1, Rs2
+ * # Rd, Rs1, Rs2 are all even/odd pair of registers
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 8-bit signed elements saturating subtractions simultaneously.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 8-bit signed integer elements in Rs2 from the 8-bit
+ * signed integer elements in Rs1. If any of the results are beyond the Q7 number range (-2^7 <= Q7 <= 2^7-1),
+ * they are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[x] = Rs1.B[x] - Rs2.B[x];
+ * if (res[x] > (2^7)-1) {
+ *   res[x] = (2^7)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^7) {
+ *   res[x] = -2^7;
+ *   OV = 1;
+ * }
+ * Rd.B[x] = res[x];
+ * for RV32: x=7...0,
+ * ~~~
+ *
+ * \param [in]  a unsigned long long type of value stored in a
+ * \param [in]  b unsigned long long type of value stored in b
+ * \return value stored in unsigned long long type
+ */
+__STATIC_FORCEINLINE unsigned long long __RV_DKSUB8(unsigned long long a, unsigned long long b)
+{
+    unsigned long long result;
+    __ASM volatile("dksub8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for A.9. DKSUB8 ===== */
+
+/* ===== Inline Function Start for A.10. DKSUB16 ===== */
+/**
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
+ * \brief DKSUB16 (64-bit SIMD 16-bit Signed Saturating Subtraction)
+ * \details
+ * **Type**: SIMD
+ *
+ * **Syntax**:\n
+ * ~~~
+ * DKSUB16 Rd, Rs1, Rs2
+ * # Rd, Rs1, Rs2 are all even/odd pair of registers
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Do 16-bit signed integer elements saturating subtractions simultaneously.
+ *
+ * **Description**:\n
+ * This instruction subtracts the 16-bit signed integer elements in Rs2 from the 16-bit
+ * signed integer elements in Rs1. If any of the results are beyond the Q15 number range (-2^15 <= Q15 <=
+ * 2^15-1), they are saturated to the range and the OV bit is set to 1. The saturated results are written to
+ * Rd.
+ *
+ * **Operations**:\n
+ * ~~~
+ * res[x] = Rs1.H[x] - Rs2.H[x];
+ * if (res[x] > (2^15)-1) {
+ *   res[x] = (2^15)-1;
+ *   OV = 1;
+ * } else if (res[x] < -2^15) {
+ *   res[x] = -2^15;
+ *   OV = 1;
+ * }
+ * Rd.H[x] = res[x];
+ * for RV32: x=3...0,
+ * ~~~
+ *
+ * \param [in]  a unsigned long long type of value stored in a
+ * \param [in]  b unsigned long long type of value stored in b
+ * \return value stored in unsigned long long type
+ */
+__STATIC_FORCEINLINE unsigned long long __RV_DKSUB16(unsigned long long a, unsigned long long b)
+{
+    unsigned long long result;
+    __ASM volatile("dksub16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
+    return result;
+}
+/* ===== Inline Function End for A.10. DKSUB16 ===== */
+
+/* ===== Inline Function Start for A.11.1. EXPD80 ===== */
+/**
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
+ * \brief EXPD80 (Expand and Copy Byte 0 to 32bit)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * EXPD80 Rd, Rs1
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Copy 8-bit data from 32-bit chunks into 4 bytes in a register.
+ *
+ * **Description**:\n
+ * Moves Rs1.B[0][7:0] to Rd.[0][7:0], Rd.[1][7:0], Rd.[2][7:0], Rd.[3][7:0]
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x][31:0] = CONCAT(Rs1.B[0][7:0], Rs1.B[0][7:0], Rs1.B[0][7:0], Rs1.B[0][7:0]);
+ * for RV32: x=0
+ * ~~~
+ *
+ * \param [in]  a unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_EXPD80(unsigned long a)
+{
+    unsigned long result;
+    __ASM volatile("expd80 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for A11.1. EXPD80 ===== */
+
+/* ===== Inline Function Start for A.11.2. EXPD81 ===== */
+/**
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
+ * \brief EXPD81 (Expand and Copy Byte 1 to 32bit)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * EXPD81 Rd, Rs1
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Copy 8-bit data from 32-bit chunks into 4 bytes in a register.
+ *
+ * **Description**:\n
+ * Moves Rs1.B[1][7:0] to Rd.[0][7:0], Rd.[1][7:0], Rd.[2][7:0], Rd.[3][7:0]
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x][31:0] = CONCAT(Rs1.B[1][7:0], Rs1.B[1][7:0], Rs1.B[1][7:0], Rs1.B[1][7:0]);
+ * for RV32: x=0
+ * ~~~
+ *
+ * \param [in]  a unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_EXPD81(unsigned long a)
+{
+    unsigned long result;
+    __ASM volatile("expd81 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for A11.2. EXPD81 ===== */
+
+/* ===== Inline Function Start for A.11.3. EXPD82 ===== */
+/**
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
+ * \brief EXPD82 (Expand and Copy Byte 2 to 32bit)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * EXPD82 Rd, Rs1
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Copy 8-bit data from 32-bit chunks into 4 bytes in a register.
+ *
+ * **Description**:\n
+ * Moves Rs1.B[2][7:0] to Rd.[0][7:0], Rd.[1][7:0], Rd.[2][7:0], Rd.[3][7:0]
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x][31:0] = CONCAT(Rs1.B[2][7:0], Rs1.B[2][7:0], Rs1.B[2][7:0], Rs1.B[2][7:0]);
+ * for RV32: x=0
+ * ~~~
+ *
+ * \param [in]  a unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_EXPD82(unsigned long a)
+{
+    unsigned long result;
+    __ASM volatile("expd82 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for A11.3. EXPD82 ===== */
+
+/* ===== Inline Function Start for A.11.4. EXPD83 ===== */
+/**
+ * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
+ * \brief EXPD83 (Expand and Copy Byte 3 to 32bit)
+ * \details
+ * **Type**: DSP
+ *
+ * **Syntax**:\n
+ * ~~~
+ * EXPD83 Rd, Rs1
+ * ~~~
+ *
+ * **Purpose**:\n
+ * Copy 8-bit data from 32-bit chunks into 4 bytes in a register.
+ *
+ * **Description**:\n
+ * Moves Rs1.B[3][7:0] to Rd.[0][7:0], Rd.[1][7:0], Rd.[2][7:0], Rd.[3][7:0]
+ *
+ * **Operations**:\n
+ * ~~~
+ * Rd.W[x][31:0] = CONCAT(Rs1.B[3][7:0], Rs1.B[3][7:0], Rs1.B[3][7:0], Rs1.B[3][7:0]);
+ * for RV32: x=0
+ * ~~~
+ *
+ * \param [in]  a unsigned long type of value stored in a
+ * \return value stored in unsigned long type
+ */
+__STATIC_FORCEINLINE unsigned long __RV_EXPD83(unsigned long a)
+{
+    unsigned long result;
+    __ASM volatile("expd83 %0, %1" : "=r"(result) : "r"(a));
+    return result;
+}
+/* ===== Inline Function End for A11.4. EXPD83 ===== */
+#endif /* __RISCV_XLEN == 32 */
+
+#if defined(__RISCV_FEATURE_DSP) && (__RISCV_FEATURE_DSP == 1)
+/* XXXXX ARM Compatiable SIMD API XXXXX */
+/** \brief Q setting quad 8-bit saturating addition. */
+#define __QADD8(x, y)               __RV_KADD8(x, y)
+/** \brief Q setting quad 8-bit saturating subtract. */
+#define __QSUB8(x, y)               __RV_KSUB8((x), (y))
+/** \brief Q setting dual 16-bit saturating addition. */
+#define __QADD16(x, y)              __RV_KADD16((x), (y))
+/** \brief Dual 16-bit signed addition with halved results. */
+#define __SHADD16(x, y)             __RV_RADD16((x), (y))
+/** \brief Q setting dual 16-bit saturating subtract. */
+#define __QSUB16(x, y)              __RV_KSUB16((x), (y))
+/** \brief Dual 16-bit signed subtraction with halved results. */
+#define __SHSUB16(x, y)             __RV_RSUB16((x), (y))
+/** \brief Q setting dual 16-bit add and subtract with exchange. */
+#define __QASX(x, y)                __RV_KCRAS16((x), (y))
+/** \brief Dual 16-bit signed addition and subtraction with halved results.*/
+#define __SHASX(x, y)               __RV_RCRAS16((x), (y))
+/** \brief Q setting dual 16-bit subtract and add with exchange. */
+#define __QSAX(x, y)                __RV_KCRSA16((x), (y))
+/** \brief Dual 16-bit signed subtraction and addition with halved results.*/
+#define __SHSAX(x, y)               __RV_RCRSA16((x), (y))
+/** \brief Dual 16-bit signed multiply with exchange returning difference. */
+#define __SMUSDX(x, y)              __RV_SMXDS((y), (x))
+/** \brief Q setting sum of dual 16-bit signed multiply with exchange. */
+__STATIC_FORCEINLINE int32_t __SMUADX (int32_t op1, int32_t op2)
+{
+    return (int32_t)__RV_KMXDA(op1, op2);
+}
+/** \brief Q setting saturating add. */
+#define __QADD(x, y)                __RV_KADDW((x), (y))
+/** \brief Q setting saturating subtract. */
+#define __QSUB(x, y)                __RV_KSUBW((x), (y))
+/** \brief Q setting dual 16-bit signed multiply with single 32-bit accumulator. */
+__STATIC_FORCEINLINE int32_t __SMLAD(int32_t op1, int32_t op2, int32_t op3)
+{
+    return (int32_t)__RV_KMADA(op3, op1, op2);
+}
+/** \brief Q setting pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator.  */
+__STATIC_FORCEINLINE int32_t __SMLADX(int32_t op1, int32_t op2, int32_t op3)
+{
+    return (int32_t)__RV_KMAXDA(op3, op1, op2);
+}
+/** \brief Q setting dual 16-bit signed multiply with exchange subtract with 32-bit accumulate.  */
+__STATIC_FORCEINLINE int32_t __SMLSDX(int32_t op1, int32_t op2, int32_t op3)
+{
+    return (op3 - (int32_t)__RV_SMXDS(op1, op2));
+}
+/** \brief Dual 16-bit signed multiply with single 64-bit accumulator. */
+__STATIC_FORCEINLINE int64_t __SMLALD(int32_t op1, int32_t op2, int64_t acc)
+{
+    return (int64_t)__RV_SMALDA(acc, op1, op2);
+}
+/** \brief Dual 16-bit signed multiply with exchange with single 64-bit accumulator.  */
+__STATIC_FORCEINLINE int64_t __SMLALDX(int32_t op1, int32_t op2, int64_t acc)
+{
+    return (int64_t)__RV_SMALXDA(acc, op1, op2);
+}
+/** \brief Q setting sum of dual 16-bit signed multiply. */
+__STATIC_FORCEINLINE int32_t __SMUAD(int32_t op1, int32_t op2)
+{
+    return (int32_t)__RV_KMDA(op1, op2);
+}
+/** \brief Dual 16-bit signed multiply returning difference. */
+__STATIC_FORCEINLINE int32_t __SMUSD(int32_t op1, int32_t op2)
+{
+    return (int32_t)__RV_SMDRS(op1, op2);
+}
+/** \brief Dual extract 8-bits and sign extend each to 16-bits. */
+#define __SXTB16(x)             __RV_SUNPKD820(x)
+/** \brief Dual extracted 8-bit to 16-bit signed addition. TODO Need test */
+__STATIC_FORCEINLINE int32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+    return __RV_ADD16(op1, __RV_SUNPKD820(op2));
+}
+#define __SXTAB16_RORn(ARG1, ARG2, ROTATE)        __SXTAB16(ARG1, __ROR(ARG2, ROTATE))
+
+/** \brief 32-bit signed multiply with 32-bit truncated accumulator. */
+__STATIC_FORCEINLINE int32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3)
+{
+    int32_t mul;
+    mul = (int32_t)__RV_SMMUL(op1, op2);
+    return (op3 + mul);
+}
+#define __DKHM8                 __RV_DKHM8
+#define __DKHM16                __RV_DKHM16
+#define __DKSUB16               __RV_DKSUB16
+#define __SMAQA                 __RV_SMAQA
+#define __MULSR64               __RV_MULSR64
+#define __DQADD8                __RV_DKADD8
+#define __DQSUB8                __RV_DKSUB8
+#define __DKADD16               __RV_DKADD16
+#define __PKBB16                __RV_PKBB16
+#define __DKSLRA16              __RV_DKSLRA16
+#define __DKSLRA8               __RV_DKSLRA8
+#define __KABSW                 __RV_KABSW
+#define __DKABS8                __RV_DKABS8
+#define __DKABS16               __RV_DKABS16
+#define __SMALDA                __RV_SMALDA
+#define __SMSLDA                __RV_SMSLDA
+#define __SMALBB                __RV_SMALBB
+#define __SUB64                 __RV_SUB64
+#define __ADD64                 __RV_ADD64
+#define __SMBB16                __RV_SMBB16
+#define __SMBT16                __RV_SMBT16
+#define __SMTT16                __RV_SMTT16
+#define __EXPD80                __RV_EXPD80
+#define __SMAX8                 __RV_SMAX8
+#define __SMAX16                __RV_SMAX16
+#define __PKTT16                __RV_PKTT16
+#define __KADD16                __RV_KADD16
+#define __SADD16                __RV_ADD16
+#define __SSUB8                 __RV_KSUB8
+#define __SADD8                 __RV_KADD8
+#define __USAT16                __RV_UCLIP16
+
+/** \brief Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16] of val2 levitated with the val3. */
+#define __PKHBT(ARG1,ARG2,ARG3)     ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                    ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+/** \brief Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0] of val2 right-shifted with the val3. */
+#define __PKHTB(ARG1,ARG2,ARG3)     ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                    ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+/** first rotate then extract. This is more suitable for arm compiler for it can rotate and extract in one command*/
+#define __SXTB16_RORn(ARG1, ARG2)   __RV_SUNPKD820(__ROR(ARG1, ARG2))
+
+#endif /* (__RISCV_FEATURE_DSP == 1) */
+
+#endif /* defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_FEATURE_DSP__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_eclic.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_eclic.h
new file mode 100644
index 00000000..cac14ef0
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_eclic.h
@@ -0,0 +1,897 @@
+/*
+ * Copyright (c) 2019 Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __CORE_FEATURE_ECLIC__
+#define __CORE_FEATURE_ECLIC__
+/*!
+ * @file     core_feature_eclic.h
+ * @brief    ECLIC feature API header file for Nuclei N/NX Core
+ */
+/*
+ * ECLIC Feature Configuration Macro:
+ * 1. __ECLIC_PRESENT:  Define whether Enhanced Core Local Interrupt Controller (ECLIC) Unit is present or not
+ *   * 0: Not present
+ *   * 1: Present
+ * 2. __ECLIC_BASEADDR:  Base address of the ECLIC unit.
+ * 3. ECLIC_GetInfoCtlbits():  Define the number of hardware bits are actually implemented in the clicintctl registers.
+ *   Valid number is 1 - 8.
+ * 4. __ECLIC_INTNUM  : Define the external interrupt number of ECLIC Unit
+ *
+ */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1)
+/**
+ * \defgroup NMSIS_Core_ECLIC_Registers     Register Define and Type Definitions Of ECLIC
+ * \ingroup NMSIS_Core_Registers
+ * \brief   Type definitions and defines for eclic registers.
+ *
+ * @{
+ */
+
+/**
+ * \brief  Union type to access CLICFG configure register.
+ */
+typedef union
+{
+    struct {
+        uint8_t _reserved0:1;                   /*!< bit:     0   Overflow condition code flag */
+        uint8_t nlbits:4;                       /*!< bit:     29  Carry condition code flag */
+        uint8_t _reserved1:2;                   /*!< bit:     30  Zero condition code flag */
+        uint8_t _reserved2:1;                   /*!< bit:     31  Negative condition code flag */
+    } b;                                        /*!< Structure used for bit  access */
+    uint8_t w;                                  /*!< Type      used for byte access */
+} CLICCFG_Type;
+
+/**
+ * \brief  Union type to access CLICINFO information register.
+ */
+typedef union {
+    struct {
+        uint32_t numint:13;                     /*!< bit:  0..12   number of maximum interrupt inputs supported */
+        uint32_t version:8;                     /*!< bit:  13..20  20:17 for architecture version,16:13 for implementation version */
+        uint32_t intctlbits:4;                  /*!< bit:  21..24  specifies how many hardware bits are actually implemented in the clicintctl registers */
+        uint32_t _reserved0:7;                  /*!< bit:  25..31  Reserved */
+    } b;                                        /*!< Structure used for bit  access */
+    uint32_t w;                                 /*!< Type      used for word access */
+} CLICINFO_Type;
+
+/**
+ * \brief Access to the structure of a vector interrupt controller.
+ */
+typedef struct {
+    __IOM uint8_t  INTIP;                       /*!< Offset: 0x000 (R/W)  Interrupt set pending register */
+    __IOM uint8_t  INTIE;                       /*!< Offset: 0x001 (R/W)  Interrupt set enable register */
+    __IOM uint8_t  INTATTR;                     /*!< Offset: 0x002 (R/W)  Interrupt set attributes register */
+    __IOM uint8_t  INTCTRL;                     /*!< Offset: 0x003 (R/W)  Interrupt configure register */
+} CLIC_CTRL_Type;
+
+typedef struct {
+    __IOM uint8_t   CFG;                        /*!< Offset: 0x000 (R/W)  CLIC configuration register */
+    uint8_t RESERVED0[3];
+    __IM uint32_t  INFO;                        /*!< Offset: 0x004 (R/ )  CLIC information register */
+    uint8_t RESERVED1[3];
+    __IOM uint8_t  MTH;                         /*!< Offset: 0x00B (R/W)  CLIC machine mode threshold register */
+    uint32_t RESERVED2[0x3FD];
+    CLIC_CTRL_Type CTRL[4096];                  /*!< Offset: 0x1000 (R/W) CLIC register structure for INTIP, INTIE, INTATTR, INTCTL */
+} CLIC_Type;
+
+#define CLIC_CLICCFG_NLBIT_Pos                 1U                                       /*!< CLIC CLICCFG: NLBIT Position */
+#define CLIC_CLICCFG_NLBIT_Msk                 (0xFUL << CLIC_CLICCFG_NLBIT_Pos)        /*!< CLIC CLICCFG: NLBIT Mask */
+
+#define CLIC_CLICINFO_CTLBIT_Pos                21U                                     /*!< CLIC INTINFO: __ECLIC_GetInfoCtlbits() Position */
+#define CLIC_CLICINFO_CTLBIT_Msk                (0xFUL << CLIC_CLICINFO_CTLBIT_Pos)     /*!< CLIC INTINFO: __ECLIC_GetInfoCtlbits() Mask */
+
+#define CLIC_CLICINFO_VER_Pos                  13U                                      /*!< CLIC CLICINFO: VERSION Position */
+#define CLIC_CLICINFO_VER_Msk                  (0xFFUL << CLIC_CLICCFG_NLBIT_Pos)       /*!< CLIC CLICINFO: VERSION Mask */
+
+#define CLIC_CLICINFO_NUM_Pos                  0U                                       /*!< CLIC CLICINFO: NUM Position */
+#define CLIC_CLICINFO_NUM_Msk                  (0xFFFUL << CLIC_CLICINFO_NUM_Pos)       /*!< CLIC CLICINFO: NUM Mask */
+
+#define CLIC_INTIP_IP_Pos                      0U                                       /*!< CLIC INTIP: IP Position */
+#define CLIC_INTIP_IP_Msk                      (0x1UL << CLIC_INTIP_IP_Pos)             /*!< CLIC INTIP: IP Mask */
+
+#define CLIC_INTIE_IE_Pos                      0U                                       /*!< CLIC INTIE: IE Position */
+#define CLIC_INTIE_IE_Msk                      (0x1UL << CLIC_INTIE_IE_Pos)             /*!< CLIC INTIE: IE Mask */
+
+#define CLIC_INTATTR_TRIG_Pos                  1U                                       /*!< CLIC INTATTR: TRIG Position */
+#define CLIC_INTATTR_TRIG_Msk                  (0x3UL << CLIC_INTATTR_TRIG_Pos)         /*!< CLIC INTATTR: TRIG Mask */
+
+#define CLIC_INTATTR_SHV_Pos                   0U                                       /*!< CLIC INTATTR: SHV Position */
+#define CLIC_INTATTR_SHV_Msk                   (0x1UL << CLIC_INTATTR_SHV_Pos)          /*!< CLIC INTATTR: SHV Mask */
+
+#define ECLIC_MAX_NLBITS                       8U                                       /*!< Max nlbit of the CLICINTCTLBITS */
+#define ECLIC_MODE_MTVEC_Msk                   3U                                       /*!< ECLIC Mode mask for MTVT CSR Register */
+
+#define ECLIC_NON_VECTOR_INTERRUPT             0x0                                      /*!< Non-Vector Interrupt Mode of ECLIC */
+#define ECLIC_VECTOR_INTERRUPT                 0x1                                      /*!< Vector Interrupt Mode of ECLIC */
+
+/**\brief ECLIC Trigger Enum for different Trigger Type */
+typedef enum ECLIC_TRIGGER {
+    ECLIC_LEVEL_TRIGGER = 0x0,          /*!< Level Triggerred, trig[0] = 0 */
+    ECLIC_POSTIVE_EDGE_TRIGGER = 0x1,   /*!< Postive/Rising Edge Triggered, trig[0] = 1, trig[1] = 0 */
+    ECLIC_NEGTIVE_EDGE_TRIGGER = 0x3,   /*!< Negtive/Falling Edge Triggered, trig[0] = 1, trig[1] = 1 */
+    ECLIC_MAX_TRIGGER = 0x3             /*!< MAX Supported Trigger Mode */
+} ECLIC_TRIGGER_Type;
+
+#ifndef __ECLIC_BASEADDR
+/* Base address of ECLIC(__ECLIC_BASEADDR) should be defined in  */
+#error "__ECLIC_BASEADDR is not defined, please check!"
+#endif
+
+#ifndef __ECLIC_INTCTLBITS
+/* Define __ECLIC_INTCTLBITS to get via ECLIC->INFO if not defined */
+#define __ECLIC_INTCTLBITS                  (__ECLIC_GetInfoCtlbits())
+#endif
+
+/* ECLIC Memory mapping of Device */
+#define ECLIC_BASE                          __ECLIC_BASEADDR                            /*!< ECLIC Base Address */
+#define ECLIC                               ((CLIC_Type *) ECLIC_BASE)                  /*!< CLIC configuration struct */
+
+/** @} */ /* end of group NMSIS_Core_ECLIC_Registers */
+
+/* ##########################   ECLIC functions  #################################### */
+/**
+ * \defgroup   NMSIS_Core_IntExc        Interrupts and Exceptions
+ * \brief Functions that manage interrupts and exceptions via the ECLIC.
+ *
+ * @{
+ */
+
+/**
+ * \brief  Definition of IRQn numbers
+ * \details
+ * The core interrupt enumeration names for IRQn values are defined in the file .h.
+ * - Interrupt ID(IRQn) from 0 to 18 are reserved for core internal interrupts.
+ * - Interrupt ID(IRQn) start from 19 represent device-specific external interrupts.
+ * - The first device-specific interrupt has the IRQn value 19.
+ *
+ * The table below describes the core interrupt names and their availability in various Nuclei Cores.
+ */
+/* The following enum IRQn definition in this file
+ * is only used for doxygen documentation generation,
+ * The .h is the real file to define it by vendor
+ */
+#if defined(__ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__)
+typedef enum IRQn {
+    /* ========= Nuclei N/NX Core Specific Interrupt Numbers  =========== */
+    /* Core Internal Interrupt IRQn definitions */
+    Reserved0_IRQn            =   0,              /*!<  Internal reserved */
+    Reserved1_IRQn            =   1,              /*!<  Internal reserved */
+    Reserved2_IRQn            =   2,              /*!<  Internal reserved */
+    SysTimerSW_IRQn           =   3,              /*!<  System Timer SW interrupt */
+    Reserved3_IRQn            =   4,              /*!<  Internal reserved */
+    Reserved4_IRQn            =   5,              /*!<  Internal reserved */
+    Reserved5_IRQn            =   6,              /*!<  Internal reserved */
+    SysTimer_IRQn             =   7,              /*!<  System Timer Interrupt */
+    Reserved6_IRQn            =   8,              /*!<  Internal reserved */
+    Reserved7_IRQn            =   9,              /*!<  Internal reserved */
+    Reserved8_IRQn            =  10,              /*!<  Internal reserved */
+    Reserved9_IRQn            =  11,              /*!<  Internal reserved */
+    Reserved10_IRQn           =  12,              /*!<  Internal reserved */
+    Reserved11_IRQn           =  13,              /*!<  Internal reserved */
+    Reserved12_IRQn           =  14,              /*!<  Internal reserved */
+    Reserved13_IRQn           =  15,              /*!<  Internal reserved */
+    Reserved14_IRQn           =  16,              /*!<  Internal reserved */
+    Reserved15_IRQn           =  17,              /*!<  Internal reserved */
+    Reserved16_IRQn           =  18,              /*!<  Internal reserved */
+
+    /* ========= Device Specific Interrupt Numbers  =================== */
+    /* ToDo: add here your device specific external interrupt numbers.
+     * 19~max(NUM_INTERRUPT, 1023) is reserved number for user.
+     * Maxmum interrupt supported could get from clicinfo.NUM_INTERRUPT.
+     * According the interrupt handlers defined in startup_Device.S
+     * eg.: Interrupt for Timer#1       eclic_tim1_handler   ->   TIM1_IRQn */
+    FirstDeviceSpecificInterrupt_IRQn    = 19,    /*!< First Device Specific Interrupt */
+    SOC_INT_MAX,                                  /*!< Number of total interrupts */
+} IRQn_Type;
+#endif /* __ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__ */
+
+#ifdef NMSIS_ECLIC_VIRTUAL
+    #ifndef NMSIS_ECLIC_VIRTUAL_HEADER_FILE
+        #define NMSIS_ECLIC_VIRTUAL_HEADER_FILE "nmsis_eclic_virtual.h"
+    #endif
+    #include NMSIS_ECLIC_VIRTUAL_HEADER_FILE
+#else
+    #define ECLIC_SetCfgNlbits            __ECLIC_SetCfgNlbits
+    #define ECLIC_GetCfgNlbits            __ECLIC_GetCfgNlbits
+    #define ECLIC_GetInfoVer              __ECLIC_GetInfoVer
+    #define ECLIC_GetInfoCtlbits          __ECLIC_GetInfoCtlbits
+    #define ECLIC_GetInfoNum              __ECLIC_GetInfoNum
+    #define ECLIC_SetMth                  __ECLIC_SetMth
+    #define ECLIC_GetMth                  __ECLIC_GetMth
+    #define ECLIC_EnableIRQ               __ECLIC_EnableIRQ
+    #define ECLIC_GetEnableIRQ            __ECLIC_GetEnableIRQ
+    #define ECLIC_DisableIRQ              __ECLIC_DisableIRQ
+    #define ECLIC_SetPendingIRQ           __ECLIC_SetPendingIRQ
+    #define ECLIC_GetPendingIRQ           __ECLIC_GetPendingIRQ
+    #define ECLIC_ClearPendingIRQ         __ECLIC_ClearPendingIRQ
+    #define ECLIC_SetTrigIRQ              __ECLIC_SetTrigIRQ
+    #define ECLIC_GetTrigIRQ              __ECLIC_GetTrigIRQ
+    #define ECLIC_SetShvIRQ               __ECLIC_SetShvIRQ
+    #define ECLIC_GetShvIRQ               __ECLIC_GetShvIRQ
+    #define ECLIC_SetCtrlIRQ              __ECLIC_SetCtrlIRQ
+    #define ECLIC_GetCtrlIRQ              __ECLIC_GetCtrlIRQ
+    #define ECLIC_SetLevelIRQ             __ECLIC_SetLevelIRQ
+    #define ECLIC_GetLevelIRQ             __ECLIC_GetLevelIRQ
+    #define ECLIC_SetPriorityIRQ          __ECLIC_SetPriorityIRQ
+    #define ECLIC_GetPriorityIRQ          __ECLIC_GetPriorityIRQ
+
+#endif /* NMSIS_ECLIC_VIRTUAL */
+
+#ifdef NMSIS_VECTAB_VIRTUAL
+    #ifndef NMSIS_VECTAB_VIRTUAL_HEADER_FILE
+        #define NMSIS_VECTAB_VIRTUAL_HEADER_FILE "nmsis_vectab_virtual.h"
+    #endif
+    #include NMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+    #define ECLIC_SetVector              __ECLIC_SetVector
+    #define ECLIC_GetVector              __ECLIC_GetVector
+#endif  /* (NMSIS_VECTAB_VIRTUAL) */
+
+/**
+ * \brief  Set nlbits value
+ * \details
+ * This function set the nlbits value of CLICCFG register.
+ * \param [in]    nlbits    nlbits value
+ * \remarks
+ * - nlbits is used to set the width of level in the CLICINTCTL[i].
+ * \sa
+ * - \ref ECLIC_GetCfgNlbits
+ */
+__STATIC_FORCEINLINE void __ECLIC_SetCfgNlbits(uint32_t nlbits)
+{
+    ECLIC->CFG &= ~CLIC_CLICCFG_NLBIT_Msk;
+    ECLIC->CFG |= (uint8_t)((nlbits <CFG & CLIC_CLICCFG_NLBIT_Msk) >> CLIC_CLICCFG_NLBIT_Pos));
+}
+
+/**
+ * \brief  Get the ECLIC version number
+ * \details
+ * This function gets the hardware version information from CLICINFO register.
+ * \return   hardware version number in CLICINFO register.
+ * \remarks
+ * - This function gets harware version information from CLICINFO register.
+ * - Bit 20:17 for architecture version, bit 16:13 for implementation version.
+ * \sa
+ * - \ref ECLIC_GetInfoNum
+*/
+__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoVer(void)
+{
+    return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_VER_Msk) >> CLIC_CLICINFO_VER_Pos));
+}
+
+/**
+ * \brief  Get CLICINTCTLBITS
+ * \details
+ * This function gets CLICINTCTLBITS from CLICINFO register.
+ * \return  CLICINTCTLBITS from CLICINFO register.
+ * \remarks
+ * - In the CLICINTCTL[i] registers, with 2 <= CLICINTCTLBITS <= 8.
+ * - The implemented bits are kept left-justified in the most-significant bits of each 8-bit
+ *   CLICINTCTL[I] register, with the lower unimplemented bits treated as hardwired to 1.
+ * \sa
+ * - \ref ECLIC_GetInfoNum
+ */
+__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoCtlbits(void)
+{
+    return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_CTLBIT_Msk) >> CLIC_CLICINFO_CTLBIT_Pos));
+}
+
+/**
+ * \brief  Get number of maximum interrupt inputs supported
+ * \details
+ * This function gets number of maximum interrupt inputs supported from CLICINFO register.
+ * \return  number of maximum interrupt inputs supported from CLICINFO register.
+ * \remarks
+ * - This function gets number of maximum interrupt inputs supported from CLICINFO register.
+ * - The num_interrupt field specifies the actual number of maximum interrupt inputs supported in this implementation.
+ * \sa
+ * - \ref ECLIC_GetInfoCtlbits
+ */
+__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoNum(void)
+{
+    return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_NUM_Msk) >> CLIC_CLICINFO_NUM_Pos));
+}
+
+/**
+ * \brief  Set Machine Mode Interrupt Level Threshold
+ * \details
+ * This function sets machine mode interrupt level threshold.
+ * \param [in]  mth       Interrupt Level Threshold.
+ * \sa
+ * - \ref ECLIC_GetMth
+ */
+__STATIC_FORCEINLINE void __ECLIC_SetMth(uint8_t mth)
+{
+    ECLIC->MTH = mth;
+}
+
+/**
+ * \brief  Get Machine Mode Interrupt Level Threshold
+ * \details
+ * This function gets machine mode interrupt level threshold.
+ * \return       Interrupt Level Threshold.
+ * \sa
+ * - \ref ECLIC_SetMth
+ */
+__STATIC_FORCEINLINE uint8_t __ECLIC_GetMth(void)
+{
+    return (ECLIC->MTH);
+}
+
+
+/**
+ * \brief  Enable a specific interrupt
+ * \details
+ * This function enables the specific interrupt \em IRQn.
+ * \param [in]  IRQn  Interrupt number
+ * \remarks
+ * - IRQn must not be negative.
+ * \sa
+ * - \ref ECLIC_DisableIRQ
+ */
+__STATIC_FORCEINLINE void __ECLIC_EnableIRQ(IRQn_Type IRQn)
+{
+    ECLIC->CTRL[IRQn].INTIE |= CLIC_INTIE_IE_Msk;
+}
+
+/**
+ * \brief  Get a specific interrupt enable status
+ * \details
+ * This function returns the interrupt enable status for the specific interrupt \em IRQn.
+ * \param [in]  IRQn  Interrupt number
+ * \returns
+ * - 0  Interrupt is not enabled
+ * - 1  Interrupt is pending
+ * \remarks
+ * - IRQn must not be negative.
+ * \sa
+ * - \ref ECLIC_EnableIRQ
+ * - \ref ECLIC_DisableIRQ
+ */
+__STATIC_FORCEINLINE uint32_t __ECLIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+    return((uint32_t) (ECLIC->CTRL[IRQn].INTIE) & CLIC_INTIE_IE_Msk);
+}
+
+/**
+ * \brief  Disable a specific interrupt
+ * \details
+ * This function disables the specific interrupt \em IRQn.
+ * \param [in]  IRQn  Number of the external interrupt to disable
+ * \remarks
+ * - IRQn must not be negative.
+ * \sa
+ * - \ref ECLIC_EnableIRQ
+ */
+__STATIC_FORCEINLINE void __ECLIC_DisableIRQ(IRQn_Type IRQn)
+{
+    ECLIC->CTRL[IRQn].INTIE &= ~CLIC_INTIE_IE_Msk;
+}
+
+/**
+ * \brief  Get the pending specific interrupt
+ * \details
+ * This function returns the pending status of the specific interrupt \em IRQn.
+ * \param [in]      IRQn  Interrupt number
+ * \returns
+ * - 0  Interrupt is not pending
+ * - 1  Interrupt is pending
+ * \remarks
+ * - IRQn must not be negative.
+ * \sa
+ * - \ref ECLIC_SetPendingIRQ
+ * - \ref ECLIC_ClearPendingIRQ
+ */
+__STATIC_FORCEINLINE int32_t __ECLIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    return((uint32_t)(ECLIC->CTRL[IRQn].INTIP) & CLIC_INTIP_IP_Msk);
+}
+
+/**
+ * \brief  Set a specific interrupt to pending
+ * \details
+ * This function sets the pending bit for the specific interrupt \em IRQn.
+ * \param [in]      IRQn  Interrupt number
+ * \remarks
+ * - IRQn must not be negative.
+ * \sa
+ * - \ref ECLIC_GetPendingIRQ
+ * - \ref ECLIC_ClearPendingIRQ
+ */
+__STATIC_FORCEINLINE void __ECLIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    ECLIC->CTRL[IRQn].INTIP |= CLIC_INTIP_IP_Msk;
+}
+
+/**
+ * \brief  Clear a specific interrupt from pending
+ * \details
+ * This function removes the pending state of the specific interrupt \em IRQn.
+ * \em IRQn cannot be a negative number.
+ * \param [in]      IRQn  Interrupt number
+ * \remarks
+ * - IRQn must not be negative.
+ * \sa
+ * - \ref ECLIC_SetPendingIRQ
+ * - \ref ECLIC_GetPendingIRQ
+ */
+__STATIC_FORCEINLINE void __ECLIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    ECLIC->CTRL[IRQn].INTIP &= ~ CLIC_INTIP_IP_Msk;
+}
+
+/**
+ * \brief  Set trigger mode and polarity for a specific interrupt
+ * \details
+ * This function set trigger mode and polarity of the specific interrupt \em IRQn.
+ * \param [in]      IRQn  Interrupt number
+ * \param [in]      trig
+ *                   - 00  level trigger, \ref ECLIC_LEVEL_TRIGGER
+ *                   - 01  positive edge trigger, \ref ECLIC_POSTIVE_EDGE_TRIGGER
+ *                   - 02  level trigger, \ref ECLIC_LEVEL_TRIGGER
+ *                   - 03  negative edge trigger, \ref ECLIC_NEGTIVE_EDGE_TRIGGER
+ * \remarks
+ * - IRQn must not be negative.
+ *
+ * \sa
+ * - \ref ECLIC_GetTrigIRQ
+ */
+__STATIC_FORCEINLINE void __ECLIC_SetTrigIRQ(IRQn_Type IRQn, uint32_t trig)
+{
+    ECLIC->CTRL[IRQn].INTATTR &= ~CLIC_INTATTR_TRIG_Msk;
+    ECLIC->CTRL[IRQn].INTATTR |= (uint8_t)(trig<CTRL[IRQn].INTATTR) & CLIC_INTATTR_TRIG_Msk)>>CLIC_INTATTR_TRIG_Pos));
+}
+
+/**
+ * \brief  Set interrupt working mode for a specific interrupt
+ * \details
+ * This function set selective hardware vector or non-vector working mode of the specific interrupt \em IRQn.
+ * \param [in]      IRQn  Interrupt number
+ * \param [in]      shv
+ *                        - 0  non-vector mode, \ref ECLIC_NON_VECTOR_INTERRUPT
+ *                        - 1  vector mode, \ref ECLIC_VECTOR_INTERRUPT
+ * \remarks
+ * - IRQn must not be negative.
+ * \sa
+ * - \ref ECLIC_GetShvIRQ
+ */
+__STATIC_FORCEINLINE void __ECLIC_SetShvIRQ(IRQn_Type IRQn, uint32_t shv)
+{
+    ECLIC->CTRL[IRQn].INTATTR &= ~CLIC_INTATTR_SHV_Msk;
+    ECLIC->CTRL[IRQn].INTATTR |= (uint8_t)(shv<CTRL[IRQn].INTATTR) & CLIC_INTATTR_SHV_Msk)>>CLIC_INTATTR_SHV_Pos));
+}
+
+/**
+ * \brief  Modify ECLIC Interrupt Input Control Register for a specific interrupt
+ * \details
+ * This function modify ECLIC Interrupt Input Control(CLICINTCTL[i]) register of the specific interrupt \em IRQn.
+ * \param [in]      IRQn  Interrupt number
+ * \param [in]      intctrl  Set value for CLICINTCTL[i] register
+ * \remarks
+ * - IRQn must not be negative.
+ * \sa
+ * - \ref ECLIC_GetCtrlIRQ
+ */
+__STATIC_FORCEINLINE void __ECLIC_SetCtrlIRQ(IRQn_Type IRQn, uint8_t intctrl)
+{
+    ECLIC->CTRL[IRQn].INTCTRL = intctrl;
+}
+
+/**
+ * \brief  Get ECLIC Interrupt Input Control Register value for a specific interrupt
+ * \details
+ * This function modify ECLIC Interrupt Input Control register of the specific interrupt \em IRQn.
+ * \param [in]      IRQn  Interrupt number
+ * \return       value of ECLIC Interrupt Input Control register
+ * \remarks
+ * - IRQn must not be negative.
+ * \sa
+ * - \ref ECLIC_SetCtrlIRQ
+ */
+__STATIC_FORCEINLINE uint8_t __ECLIC_GetCtrlIRQ(IRQn_Type IRQn)
+{
+    return (ECLIC->CTRL[IRQn].INTCTRL);
+}
+
+/**
+ * \brief  Set ECLIC Interrupt level of a specific interrupt
+ * \details
+ * This function set interrupt level of the specific interrupt \em IRQn.
+ * \param [in]      IRQn  Interrupt number
+ * \param [in]      lvl_abs   Interrupt level
+ * \remarks
+ * - IRQn must not be negative.
+ * - If lvl_abs to be set is larger than the max level allowed, it will be force to be max level.
+ * - When you set level value you need use clciinfo.nlbits to get the width of level.
+ *   Then we could know the maximum of level. CLICINTCTLBITS is how many total bits are
+ *   present in the CLICINTCTL register.
+ * \sa
+ * - \ref ECLIC_GetLevelIRQ
+ */
+__STATIC_FORCEINLINE void __ECLIC_SetLevelIRQ(IRQn_Type IRQn, uint8_t lvl_abs)
+{
+    uint8_t nlbits = __ECLIC_GetCfgNlbits();
+    uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
+
+    if (nlbits == 0) {
+        return;
+    }
+
+    if (nlbits > intctlbits) {
+        nlbits = intctlbits;
+    }
+    uint8_t maxlvl = ((1 << nlbits) - 1);
+    if (lvl_abs > maxlvl) {
+        lvl_abs = maxlvl;
+    }
+    uint8_t lvl = lvl_abs << (ECLIC_MAX_NLBITS - nlbits);
+    uint8_t cur_ctrl = __ECLIC_GetCtrlIRQ(IRQn);
+    cur_ctrl = cur_ctrl << nlbits;
+    cur_ctrl = cur_ctrl >> nlbits;
+    __ECLIC_SetCtrlIRQ(IRQn, (cur_ctrl | lvl));
+}
+
+/**
+ * \brief  Get ECLIC Interrupt level of a specific interrupt
+ * \details
+ * This function get interrupt level of the specific interrupt \em IRQn.
+ * \param [in]      IRQn  Interrupt number
+ * \return         Interrupt level
+ * \remarks
+ * - IRQn must not be negative.
+ * \sa
+ * - \ref ECLIC_SetLevelIRQ
+ */
+__STATIC_FORCEINLINE uint8_t __ECLIC_GetLevelIRQ(IRQn_Type IRQn)
+{
+    uint8_t nlbits = __ECLIC_GetCfgNlbits();
+    uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
+
+    if (nlbits == 0) {
+        return 0;
+    }
+
+    if (nlbits > intctlbits) {
+        nlbits = intctlbits;
+    }
+    uint8_t intctrl = __ECLIC_GetCtrlIRQ(IRQn);
+    uint8_t lvl_abs = intctrl >> (ECLIC_MAX_NLBITS - nlbits);
+    return lvl_abs;
+}
+
+/**
+ * \brief  Get ECLIC Interrupt priority of a specific interrupt
+ * \details
+ * This function get interrupt priority of the specific interrupt \em IRQn.
+ * \param [in]      IRQn  Interrupt number
+ * \param [in]      pri   Interrupt priority
+ * \remarks
+ * - IRQn must not be negative.
+ * - If pri to be set is larger than the max priority allowed, it will be force to be max priority.
+ * - Priority width is CLICINTCTLBITS minus clciinfo.nlbits if clciinfo.nlbits
+ *   is less than CLICINTCTLBITS. Otherwise priority width is 0.
+ * \sa
+ * - \ref ECLIC_GetPriorityIRQ
+ */
+__STATIC_FORCEINLINE void __ECLIC_SetPriorityIRQ(IRQn_Type IRQn, uint8_t pri)
+{
+    uint8_t nlbits = __ECLIC_GetCfgNlbits();
+    uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
+    if (nlbits < intctlbits) {
+        uint8_t maxpri = ((1 << (intctlbits - nlbits)) - 1);
+        if (pri > maxpri) {
+            pri = maxpri;
+        }
+        pri = pri << (ECLIC_MAX_NLBITS - intctlbits);
+        uint8_t mask = ((uint8_t)(-1)) >> intctlbits;
+        pri = pri | mask;
+        uint8_t cur_ctrl = __ECLIC_GetCtrlIRQ(IRQn);
+        cur_ctrl = cur_ctrl >> (ECLIC_MAX_NLBITS - nlbits);
+        cur_ctrl = cur_ctrl << (ECLIC_MAX_NLBITS - nlbits);
+        __ECLIC_SetCtrlIRQ(IRQn, (cur_ctrl | pri));
+    }
+}
+
+/**
+ * \brief  Get ECLIC Interrupt priority of a specific interrupt
+ * \details
+ * This function get interrupt priority of the specific interrupt \em IRQn.
+ * \param [in]      IRQn  Interrupt number
+ * \return   Interrupt priority
+ * \remarks
+ * - IRQn must not be negative.
+ * \sa
+ * - \ref ECLIC_SetPriorityIRQ
+ */
+__STATIC_FORCEINLINE uint8_t __ECLIC_GetPriorityIRQ(IRQn_Type IRQn)
+{
+    uint8_t nlbits = __ECLIC_GetCfgNlbits();
+    uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
+    if (nlbits < intctlbits) {
+        uint8_t cur_ctrl = __ECLIC_GetCtrlIRQ(IRQn);
+        uint8_t pri = cur_ctrl << nlbits;
+        pri = pri >> nlbits;
+        pri = pri >> (ECLIC_MAX_NLBITS - intctlbits);
+        return pri;
+    } else {
+        return 0;
+    }
+}
+
+/**
+ * \brief  Set Interrupt Vector of a specific interrupt
+ * \details
+ * This function set interrupt handler address of the specific interrupt \em IRQn.
+ * \param [in]      IRQn  Interrupt number
+ * \param [in]      vector   Interrupt handler address
+ * \remarks
+ * - IRQn must not be negative.
+ * - You can set the \ref CSR_CSR_MTVT to set interrupt vector table entry address.
+ * - If your vector table is placed in readonly section, the vector for IRQn will not be modified.
+ *   For this case, you need to use the correct irq handler name defined in your vector table as
+ *   your irq handler function name.
+ * - This function will only work correctly when the vector table is placed in an read-write enabled section.
+ * \sa
+ * - \ref ECLIC_GetVector
+ */
+__STATIC_FORCEINLINE void __ECLIC_SetVector(IRQn_Type IRQn, rv_csr_t vector)
+{
+#if __RISCV_XLEN == 32
+    volatile uint32_t vec_base;
+    vec_base = ((uint32_t)__RV_CSR_READ(CSR_MTVT));
+    (* (unsigned long *) (vec_base + ((int32_t)IRQn) * 4)) = vector;
+#elif __RISCV_XLEN == 64
+    volatile uint64_t vec_base;
+    vec_base = ((uint64_t)__RV_CSR_READ(CSR_MTVT));
+    (* (unsigned long *) (vec_base + ((int32_t)IRQn) * 8)) = vector;
+#else // TODO Need cover for XLEN=128 case in future
+    volatile uint64_t vec_base;
+    vec_base = ((uint64_t)__RV_CSR_READ(CSR_MTVT));
+    (* (unsigned long *) (vec_base + ((int32_t)IRQn) * 8)) = vector;
+#endif
+}
+
+/**
+ * \brief  Get Interrupt Vector of a specific interrupt
+ * \details
+ * This function get interrupt handler address of the specific interrupt \em IRQn.
+ * \param [in]      IRQn  Interrupt number
+ * \return        Interrupt handler address
+ * \remarks
+ * - IRQn must not be negative.
+ * - You can read \ref CSR_CSR_MTVT to get interrupt vector table entry address.
+ * \sa
+ *     - \ref ECLIC_SetVector
+ */
+__STATIC_FORCEINLINE rv_csr_t __ECLIC_GetVector(IRQn_Type IRQn)
+{
+#if __RISCV_XLEN == 32
+    return (*(uint32_t *)(__RV_CSR_READ(CSR_MTVT)+IRQn*4));
+#elif __RISCV_XLEN == 64
+    return (*(uint64_t *)(__RV_CSR_READ(CSR_MTVT)+IRQn*8));
+#else // TODO Need cover for XLEN=128 case in future
+    return (*(uint64_t *)(__RV_CSR_READ(CSR_MTVT)+IRQn*8));
+#endif
+}
+
+/**
+ * \brief  Set Exception entry address
+ * \details
+ * This function set exception handler address to 'CSR_MTVEC'.
+ * \param [in]      addr  Exception handler address
+ * \remarks
+ * - This function use to set exception handler address to 'CSR_MTVEC'. Address is 4 bytes align.
+ * \sa
+ * - \ref __get_exc_entry
+ */
+__STATIC_FORCEINLINE void __set_exc_entry(rv_csr_t addr)
+{
+    addr &= (rv_csr_t)(~0x3F);
+    addr |= ECLIC_MODE_MTVEC_Msk;
+    __RV_CSR_WRITE(CSR_MTVEC, addr);
+}
+
+/**
+ * \brief  Get Exception entry address
+ * \details
+ * This function get exception handler address from 'CSR_MTVEC'.
+ * \return       Exception handler address
+ * \remarks
+ * - This function use to get exception handler address from 'CSR_MTVEC'. Address is 4 bytes align
+ * \sa
+ * - \ref __set_exc_entry
+ */
+__STATIC_FORCEINLINE rv_csr_t __get_exc_entry(void)
+{
+    unsigned long addr = __RV_CSR_READ(CSR_MTVEC);
+    return (addr & ~ECLIC_MODE_MTVEC_Msk);
+}
+
+/**
+ * \brief  Set Non-vector interrupt entry address
+ * \details
+ * This function set Non-vector interrupt address.
+ * \param [in]      addr  Non-vector interrupt entry address
+ * \remarks
+ * - This function use to set non-vector interrupt entry address to 'CSR_MTVT2' if
+ * - CSR_MTVT2 bit0 is 1. If 'CSR_MTVT2' bit0 is 0 then set address to 'CSR_MTVEC'
+ * \sa
+ * - \ref __get_nonvec_entry
+ */
+__STATIC_FORCEINLINE void __set_nonvec_entry(rv_csr_t addr)
+{
+    if (__RV_CSR_READ(CSR_MTVT2) & 0x1){
+        __RV_CSR_WRITE(CSR_MTVT2, addr | 0x01);
+    } else {
+        addr &= (rv_csr_t)(~0x3F);
+        addr |= ECLIC_MODE_MTVEC_Msk;
+        __RV_CSR_WRITE(CSR_MTVEC, addr);
+    }
+}
+
+/**
+ * \brief  Get Non-vector interrupt entry address
+ * \details
+ * This function get Non-vector interrupt address.
+ * \return      Non-vector interrupt handler address
+ * \remarks
+ * - This function use to get non-vector interrupt entry address from 'CSR_MTVT2' if
+ * - CSR_MTVT2 bit0 is 1. If 'CSR_MTVT2' bit0 is 0 then get address from 'CSR_MTVEC'.
+ * \sa
+ * - \ref __set_nonvec_entry
+ */
+__STATIC_FORCEINLINE rv_csr_t __get_nonvec_entry(void)
+{
+    if (__RV_CSR_READ(CSR_MTVT2) & 0x1) {
+        return __RV_CSR_READ(CSR_MTVT2) & (~(rv_csr_t)(0x1));
+    } else {
+        rv_csr_t addr = __RV_CSR_READ(CSR_MTVEC);
+        return (addr & ~ECLIC_MODE_MTVEC_Msk);
+    }
+}
+
+/**
+ * \brief  Get NMI interrupt entry from 'CSR_MNVEC'
+ * \details
+ * This function get NMI interrupt address from 'CSR_MNVEC'.
+ * \return      NMI interrupt handler address
+ * \remarks
+ * - This function use to get NMI interrupt handler address from 'CSR_MNVEC'. If CSR_MMISC_CTL[9] = 1 'CSR_MNVEC'
+ * - will be equal as mtvec. If CSR_MMISC_CTL[9] = 0 'CSR_MNVEC' will be equal as reset vector.
+ * - NMI entry is defined via \ref CSR_MMISC_CTL, writing to \ref CSR_MNVEC will be ignored.
+ */
+__STATIC_FORCEINLINE rv_csr_t __get_nmi_entry(void)
+{
+    return __RV_CSR_READ(CSR_MNVEC);
+}
+
+/**
+ * \brief   Save necessary CSRs into variables for vector interrupt nesting
+ * \details
+ * This macro is used to declare variables which are used for saving
+ * CSRs(MCAUSE, MEPC, MSUB), and it will read these CSR content into
+ * these variables, it need to be used in a vector-interrupt if nesting
+ * is required.
+ * \remarks
+ * - Interrupt will be enabled after this macro is called
+ * - It need to be used together with \ref RESTORE_IRQ_CSR_CONTEXT
+ * - Don't use variable names __mcause, __mpec, __msubm in your ISR code
+ * - If you want to enable interrupt nesting feature for vector interrupt,
+ * you can do it like this:
+ * \code
+ * // __INTERRUPT attribute will generates function entry and exit sequences suitable
+ * // for use in an interrupt handler when this attribute is present
+ * __INTERRUPT void eclic_mtip_handler(void)
+ * {
+ *     // Must call this to save CSRs
+ *     SAVE_IRQ_CSR_CONTEXT();
+ *     // !!!Interrupt is enabled here!!!
+ *     // !!!Higher priority interrupt could nest it!!!
+ *
+ *     // put you own interrupt handling code here
+ *
+ *     // Must call this to restore CSRs
+ *     RESTORE_IRQ_CSR_CONTEXT();
+ * }
+ * \endcode
+ */
+#define SAVE_IRQ_CSR_CONTEXT()                                              \
+        rv_csr_t __mcause = __RV_CSR_READ(CSR_MCAUSE);                      \
+        rv_csr_t __mepc = __RV_CSR_READ(CSR_MEPC);                          \
+        rv_csr_t __msubm = __RV_CSR_READ(CSR_MSUBM);                        \
+        __enable_irq();
+
+/**
+ * \brief   Restore necessary CSRs from variables for vector interrupt nesting
+ * \details
+ * This macro is used restore CSRs(MCAUSE, MEPC, MSUB) from pre-defined variables
+ * in \ref SAVE_IRQ_CSR_CONTEXT macro.
+ * \remarks
+ * - Interrupt will be disabled after this macro is called
+ * - It need to be used together with \ref SAVE_IRQ_CSR_CONTEXT
+ */
+#define RESTORE_IRQ_CSR_CONTEXT()                                           \
+        __disable_irq();                                                    \
+        __RV_CSR_WRITE(CSR_MSUBM, __msubm);                                 \
+        __RV_CSR_WRITE(CSR_MEPC, __mepc);                                   \
+        __RV_CSR_WRITE(CSR_MCAUSE, __mcause);
+
+/** @} */ /* End of Doxygen Group NMSIS_Core_IntExc */
+
+#endif /* defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1) */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /** __CORE_FEATURE_ECLIC__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_fpu.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_fpu.h
new file mode 100644
index 00000000..c9e13b79
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_fpu.h
@@ -0,0 +1,304 @@
+/*
+ * Copyright (c) 2019 Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __CORE_FEATURE_FPU_H__
+#define __CORE_FEATURE_FPU_H__
+/*!
+ * @file     core_feature_fpu.h
+ * @brief    FPU feature API header file for Nuclei N/NX Core
+ */
+/*
+ * FPU Feature Configuration Macro:
+ * 1. __FPU_PRESENT:  Define whether Floating Point Unit(FPU) is present or not
+ *   * 0: Not present
+ *   * 1: Single precision FPU present, __RISCV_FLEN == 32
+ *   * 2: Double precision FPU present, __RISCV_FLEN == 64
+ */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* ===== FPU Operations ===== */
+/**
+ * \defgroup NMSIS_Core_FPU_Functions   FPU Functions
+ * \ingroup  NMSIS_Core
+ * \brief    Functions that related to the RISC-V FPU (F and D extension).
+ * \details
+ *
+ * Nuclei provided floating point unit by RISC-V F and D extension.
+ * * `F extension` adds single-precision floating-point computational
+ * instructions compliant with the IEEE 754-2008 arithmetic standard, __RISCV_FLEN = 32.
+ *   The F extension adds 32 floating-point registers, f0-f31, each 32 bits wide,
+ *   and a floating-point control and status register fcsr, which contains the
+ *   operating mode and exception status of the floating-point unit.
+ * * `D extension` adds double-precision floating-point computational instructions
+ * compliant with the IEEE 754-2008 arithmetic standard.
+ *   The D extension widens the 32 floating-point registers, f0-f31, to 64 bits, __RISCV_FLEN = 64
+ *   @{
+ */
+#if defined(__FPU_PRESENT) && (__FPU_PRESENT > 0)
+
+#if __FPU_PRESENT == 1
+  /** \brief Refer to the width of the floating point register in bits(either 32 or 64) */
+  #define __RISCV_FLEN          32
+#elif __FPU_PRESENT == 2
+  #define __RISCV_FLEN          64
+#else
+  #define __RISCV_FLEN          __riscv_flen
+#endif /* __FPU_PRESENT == 1 */
+
+/** \brief Get FCSR CSR Register */
+#define __get_FCSR()            __RV_CSR_READ(CSR_FCSR)
+/** \brief Set FCSR CSR Register with val */
+#define __set_FCSR(val)         __RV_CSR_WRITE(CSR_FCSR, (val))
+/** \brief Get FRM CSR Register */
+#define __get_FRM()             __RV_CSR_READ(CSR_FRM)
+/** \brief Set FRM CSR Register with val */
+#define __set_FRM(val)          __RV_CSR_WRITE(CSR_FRM, (val))
+/** \brief Get FFLAGS CSR Register */
+#define __get_FFLAGS()          __RV_CSR_READ(CSR_FFLAGS)
+/** \brief Set FFLAGS CSR Register with val */
+#define __set_FFLAGS(val)       __RV_CSR_WRITE(CSR_FFLAGS, (val))
+
+/** \brief Enable FPU Unit */
+#define __enable_FPU()          __RV_CSR_SET(CSR_MSTATUS, MSTATUS_FS)
+/**
+ * \brief Disable FPU Unit
+ * \details
+ * * We can save power by disable FPU Unit.
+ * * When FPU Unit is disabled, any access to FPU related CSR registers
+ * and FPU instructions will cause illegal Instuction Exception.
+ * */
+#define __disable_FPU()         __RV_CSR_CLEAR(CSR_MSTATUS, MSTATUS_FS)
+
+
+/**
+ * \brief   Load a single-precision value from memory into float point register freg using flw instruction
+ * \details The FLW instruction loads a single-precision floating point value from memory
+ * address (addr + ofs) into floating point register freg(f0-f31)
+ * \param [in]    freg   The floating point register, eg. FREG(0), f0
+ * \param [in]    addr   The memory base address, 4 byte aligned required
+ * \param [in]    ofs    a 12-bit immediate signed byte offset value, should be an const value
+ * \remarks
+ * * FLW and FSW operations need to make sure the address is 4 bytes aligned,
+ *   otherwise it will cause exception code 4(Load address misaligned) or 6 (Store/AMO address misaligned)
+ * * FLW and FSW do not modify the bits being transferred; in particular, the payloads of non-canonical
+ * NaNs are preserved
+ *
+ */
+#define __RV_FLW(freg, addr, ofs)                              \
+    ({                                                         \
+        register rv_csr_t __addr = (rv_csr_t)(addr);           \
+        __ASM volatile("flw " STRINGIFY(freg) ", %0(%1)  "     \
+                     : : "I"(ofs), "r"(__addr)                 \
+                     : "memory");                              \
+    })
+
+/**
+ * \brief   Store a single-precision value from float point freg into memory using fsw instruction
+ * \details The FSW instruction stores a single-precision value from floating point register to memory
+ * \param [in]    freg   The floating point register(f0-f31), eg. FREG(0), f0
+ * \param [in]    addr   The memory base address, 4 byte aligned required
+ * \param [in]    ofs    a 12-bit immediate signed byte offset value, should be an const value
+ * \remarks
+ * * FLW and FSW operations need to make sure the address is 4 bytes aligned,
+ *   otherwise it will cause exception code 4(Load address misaligned) or 6 (Store/AMO address misaligned)
+ * * FLW and FSW do not modify the bits being transferred; in particular, the payloads of non-canonical
+ * NaNs are preserved
+ *
+ */
+#define __RV_FSW(freg, addr, ofs)                              \
+    ({                                                         \
+        register rv_csr_t __addr = (rv_csr_t)(addr);           \
+        __ASM volatile("fsw " STRINGIFY(freg) ", %0(%1)  "     \
+                     : : "I"(ofs), "r"(__addr)                 \
+                     : "memory");                              \
+    })
+
+/**
+ * \brief   Load a double-precision value from memory into float point register freg using fld instruction
+ * \details The FLD instruction loads a double-precision floating point value from memory
+ * address (addr + ofs) into floating point register freg(f0-f31)
+ * \param [in]    freg   The floating point register, eg. FREG(0), f0
+ * \param [in]    addr   The memory base address, 8 byte aligned required
+ * \param [in]    ofs    a 12-bit immediate signed byte offset value, should be an const value
+ * \attention
+ * * Function only available for double precision floating point unit, FLEN = 64
+ * \remarks
+ * * FLD and FSD operations need to make sure the address is 8 bytes aligned,
+ *   otherwise it will cause exception code 4(Load address misaligned) or 6 (Store/AMO address misaligned)
+ * * FLD and FSD do not modify the bits being transferred; in particular, the payloads of non-canonical
+ * NaNs are preserved.
+ */
+#define __RV_FLD(freg, addr, ofs)                              \
+    ({                                                         \
+        register rv_csr_t __addr = (rv_csr_t)(addr);           \
+        __ASM volatile("fld " STRINGIFY(freg) ", %0(%1)  "     \
+                     : : "I"(ofs), "r"(__addr)                 \
+                     : "memory");                              \
+    })
+
+/**
+ * \brief   Store a double-precision value from float point freg into memory using fsd instruction
+ * \details The FSD instruction stores double-precision value from floating point register to memory
+ * \param [in]    freg   The floating point register(f0-f31), eg. FREG(0), f0
+ * \param [in]    addr   The memory base address, 8 byte aligned required
+ * \param [in]    ofs    a 12-bit immediate signed byte offset value, should be an const value
+ * \attention
+ * * Function only available for double precision floating point unit, FLEN = 64
+ * \remarks
+ * * FLD and FSD operations need to make sure the address is 8 bytes aligned,
+ *   otherwise it will cause exception code 4(Load address misaligned) or 6 (Store/AMO address misaligned)
+ * * FLD and FSD do not modify the bits being transferred; in particular, the payloads of non-canonical
+ * NaNs are preserved.
+ *
+ */
+#define __RV_FSD(freg, addr, ofs)                              \
+    ({                                                         \
+        register rv_csr_t __addr = (rv_csr_t)(addr);           \
+        __ASM volatile("fsd " STRINGIFY(freg) ", %0(%1)  "     \
+                     : : "I"(ofs), "r"(__addr)                 \
+                     : "memory");                              \
+    })
+
+/**
+ * \def __RV_FLOAD
+ * \brief   Load a float point value from memory into float point register freg using flw/fld instruction
+ * \details
+ * * For Single-Precison Floating-Point Mode(__FPU_PRESENT == 1, __RISCV_FLEN == 32):
+ *   It will call \ref __RV_FLW to load a single-precision floating point value from memory to floating point register
+ * * For Double-Precison Floating-Point Mode(__FPU_PRESENT == 2, __RISCV_FLEN == 64):
+ *   It will call \ref __RV_FLD to load a double-precision floating point value from memory to floating point register
+ *
+ * \attention
+ * Function behaviour is different for __FPU_PRESENT = 1 or 2, please see the real function this macro represent
+ */
+/**
+ * \def __RV_FSTORE
+ * \brief   Store a float value from float point freg into memory using fsw/fsd instruction
+ * \details
+ * * For Single-Precison Floating-Point Mode(__FPU_PRESENT == 1, __RISCV_FLEN == 32):
+ *   It will call \ref __RV_FSW to store floating point register into memory
+ * * For Double-Precison Floating-Point Mode(__FPU_PRESENT == 2, __RISCV_FLEN == 64):
+ *   It will call \ref __RV_FSD to store floating point register into memory
+ *
+ * \attention
+ * Function behaviour is different for __FPU_PRESENT = 1 or 2, please see the real function this macro represent
+ */
+#if __FPU_PRESENT == 1
+#define __RV_FLOAD              __RV_FLW
+#define __RV_FSTORE             __RV_FSW
+/** \brief Type of FPU register, depends on the FLEN defined in RISC-V */
+typedef uint32_t rv_fpu_t;
+#elif __FPU_PRESENT == 2
+#define __RV_FLOAD              __RV_FLD
+#define __RV_FSTORE             __RV_FSD
+/** \brief Type of FPU register, depends on the FLEN defined in RISC-V */
+typedef uint64_t rv_fpu_t;
+#endif /* __FPU_PRESENT == 2 */
+
+/**
+ * \brief   Save FPU context into variables for interrupt nesting
+ * \details
+ * This macro is used to declare variables which are used for saving
+ * FPU context, and it will store the nessary fpu registers into
+ * these variables, it need to be used in a interrupt when in this
+ * interrupt fpu registers are used.
+ * \remarks
+ * - It need to be used together with \ref RESTORE_FPU_CONTEXT
+ * - Don't use variable names __fpu_context in your ISR code
+ * - If you isr code will use fpu registers, and this interrupt is nested.
+ * Then you can do it like this:
+ * \code
+ * void eclic_mtip_handler(void)
+ * {
+ *     // !!!Interrupt is enabled here!!!
+ *     // !!!Higher priority interrupt could nest it!!!
+ *
+ *     // Necessary only when you need to use fpu registers
+ *     // in this isr handler functions
+ *     SAVE_FPU_CONTEXT();
+ *
+ *     // put you own interrupt handling code here
+ *
+ *     // pair of SAVE_FPU_CONTEXT()
+ *     RESTORE_FPU_CONTEXT();
+ * }
+ * \endcode
+ */
+#define SAVE_FPU_CONTEXT()                                                  \
+        rv_fpu_t __fpu_context[20];                                         \
+        __RV_FSTORE(FREG(0),  __fpu_context, 0  << LOG_FPREGBYTES);         \
+        __RV_FSTORE(FREG(1),  __fpu_context, 1  << LOG_FPREGBYTES);         \
+        __RV_FSTORE(FREG(2),  __fpu_context, 2  << LOG_FPREGBYTES);         \
+        __RV_FSTORE(FREG(3),  __fpu_context, 3  << LOG_FPREGBYTES);         \
+        __RV_FSTORE(FREG(4),  __fpu_context, 4  << LOG_FPREGBYTES);         \
+        __RV_FSTORE(FREG(5),  __fpu_context, 5  << LOG_FPREGBYTES);         \
+        __RV_FSTORE(FREG(6),  __fpu_context, 6  << LOG_FPREGBYTES);         \
+        __RV_FSTORE(FREG(7),  __fpu_context, 7  << LOG_FPREGBYTES);         \
+        __RV_FSTORE(FREG(10), __fpu_context, 8  << LOG_FPREGBYTES);         \
+        __RV_FSTORE(FREG(11), __fpu_context, 9  << LOG_FPREGBYTES);         \
+        __RV_FSTORE(FREG(12), __fpu_context, 10 << LOG_FPREGBYTES);         \
+        __RV_FSTORE(FREG(13), __fpu_context, 11 << LOG_FPREGBYTES);         \
+        __RV_FSTORE(FREG(14), __fpu_context, 12 << LOG_FPREGBYTES);         \
+        __RV_FSTORE(FREG(15), __fpu_context, 13 << LOG_FPREGBYTES);         \
+        __RV_FSTORE(FREG(16), __fpu_context, 14 << LOG_FPREGBYTES);         \
+        __RV_FSTORE(FREG(17), __fpu_context, 15 << LOG_FPREGBYTES);         \
+        __RV_FSTORE(FREG(28), __fpu_context, 16 << LOG_FPREGBYTES);         \
+        __RV_FSTORE(FREG(29), __fpu_context, 17 << LOG_FPREGBYTES);         \
+        __RV_FSTORE(FREG(30), __fpu_context, 18 << LOG_FPREGBYTES);         \
+        __RV_FSTORE(FREG(31), __fpu_context, 19 << LOG_FPREGBYTES);
+
+/**
+ * \brief   Restore necessary fpu registers from variables for interrupt nesting
+ * \details
+ * This macro is used restore necessary fpu registers from pre-defined variables
+ * in \ref SAVE_FPU_CONTEXT macro.
+ * \remarks
+ * - It need to be used together with \ref SAVE_FPU_CONTEXT
+ */
+#define RESTORE_FPU_CONTEXT()                                               \
+        __RV_FLOAD(FREG(0),  __fpu_context, 0  << LOG_FPREGBYTES);          \
+        __RV_FLOAD(FREG(1),  __fpu_context, 1  << LOG_FPREGBYTES);          \
+        __RV_FLOAD(FREG(2),  __fpu_context, 2  << LOG_FPREGBYTES);          \
+        __RV_FLOAD(FREG(3),  __fpu_context, 3  << LOG_FPREGBYTES);          \
+        __RV_FLOAD(FREG(4),  __fpu_context, 4  << LOG_FPREGBYTES);          \
+        __RV_FLOAD(FREG(5),  __fpu_context, 5  << LOG_FPREGBYTES);          \
+        __RV_FLOAD(FREG(6),  __fpu_context, 6  << LOG_FPREGBYTES);          \
+        __RV_FLOAD(FREG(7),  __fpu_context, 7  << LOG_FPREGBYTES);          \
+        __RV_FLOAD(FREG(10), __fpu_context, 8  << LOG_FPREGBYTES);          \
+        __RV_FLOAD(FREG(11), __fpu_context, 9  << LOG_FPREGBYTES);          \
+        __RV_FLOAD(FREG(12), __fpu_context, 10 << LOG_FPREGBYTES);          \
+        __RV_FLOAD(FREG(13), __fpu_context, 11 << LOG_FPREGBYTES);          \
+        __RV_FLOAD(FREG(14), __fpu_context, 12 << LOG_FPREGBYTES);          \
+        __RV_FLOAD(FREG(15), __fpu_context, 13 << LOG_FPREGBYTES);          \
+        __RV_FLOAD(FREG(16), __fpu_context, 14 << LOG_FPREGBYTES);          \
+        __RV_FLOAD(FREG(17), __fpu_context, 15 << LOG_FPREGBYTES);          \
+        __RV_FLOAD(FREG(28), __fpu_context, 16 << LOG_FPREGBYTES);          \
+        __RV_FLOAD(FREG(29), __fpu_context, 17 << LOG_FPREGBYTES);          \
+        __RV_FLOAD(FREG(30), __fpu_context, 18 << LOG_FPREGBYTES);          \
+        __RV_FLOAD(FREG(31), __fpu_context, 19 << LOG_FPREGBYTES);
+#else
+#define SAVE_FPU_CONTEXT()
+#define RESTORE_FPU_CONTEXT()
+#endif /* __FPU_PRESENT > 0 */
+/** @} */ /* End of Doxygen Group NMSIS_Core_FPU_Functions */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /** __RISCV_EXT_FPU_H__  */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_pmp.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_pmp.h
new file mode 100644
index 00000000..997dfaee
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_pmp.h
@@ -0,0 +1,260 @@
+/*
+ * Copyright (c) 2019 Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __CORE_FEATURE_PMP_H__
+#define __CORE_FEATURE_PMP_H__
+/*!
+ * @file     core_feature_pmp.h
+ * @brief    PMP feature API header file for Nuclei N/NX Core
+ */
+/*
+ * PMP Feature Configuration Macro:
+ * 1. __PMP_PRESENT:  Define whether Physical Memory Protection(PMP) is present or not
+ *   * 0: Not present
+ *   * 1: Present
+ * 2. __PMP_ENTRY_NUM:  Define the number of PMP entries, only 8 or 16 is configurable.
+ */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(__PMP_PRESENT) && (__PMP_PRESENT == 1)
+/* ===== PMP Operations ===== */
+/**
+ * \defgroup NMSIS_Core_PMP_Functions   PMP Functions
+ * \ingroup  NMSIS_Core
+ * \brief    Functions that related to the RISCV Phyiscal Memory Protection.
+ * \details
+ * Optional physical memory protection (PMP) unit provides per-hart machine-mode
+ * control registers to allow physical memory access privileges (read, write, execute)
+ * to be specified for each physical memory region.
+ *
+ * The PMP can supports region access control settings as small as four bytes.
+ *
+ *   @{
+ */
+#ifndef __PMP_ENTRY_NUM
+/* numbers of PMP entries(__PMP_ENTRY_NUM) should be defined in  */
+#error "__PMP_ENTRY_NUM is not defined, please check!"
+#endif
+
+/**
+ * \brief   Get 8bit PMPxCFG Register by PMP entry index
+ * \details Return the content of the PMPxCFG Register.
+ * \param [in]    idx    PMP region index(0-15)
+ * \return               PMPxCFG Register value
+ */
+__STATIC_INLINE uint8_t __get_PMPxCFG(uint32_t idx)
+{
+    rv_csr_t pmpcfg = 0;
+
+    if (idx >= __PMP_ENTRY_NUM) return 0;
+#if __RISCV_XLEN == 32
+    if (idx < 4) {
+        pmpcfg = __RV_CSR_READ(CSR_PMPCFG0);
+    } else if ((idx >=4) && (idx < 8)) {
+        idx -= 4;
+        pmpcfg = __RV_CSR_READ(CSR_PMPCFG1);
+    } else if ((idx >=8) && (idx < 12)) {
+        idx -= 8;
+        pmpcfg = __RV_CSR_READ(CSR_PMPCFG2);
+    } else {
+        idx -= 12;
+        pmpcfg = __RV_CSR_READ(CSR_PMPCFG3);
+    }
+
+    idx = idx << 3;
+    return (uint8_t)((pmpcfg>>idx) & 0xFF);
+#elif __RISCV_XLEN == 64
+    if (idx < 8) {
+        pmpcfg = __RV_CSR_READ(CSR_PMPCFG0);
+    } else {
+        idx -= 8;
+        pmpcfg = __RV_CSR_READ(CSR_PMPCFG2);
+    }
+    idx = idx << 3;
+    return (uint8_t)((pmpcfg>>idx) & 0xFF);
+#else
+    // TODO Add RV128 Handling
+    return 0;
+#endif
+}
+
+/**
+ * \brief   Set 8bit PMPxCFG by pmp entry index
+ * \details Set the given pmpxcfg value to the PMPxCFG Register.
+ * \param [in]    idx      PMPx region index(0-15)
+ * \param [in]    pmpxcfg  PMPxCFG register value to set
+ */
+__STATIC_INLINE void __set_PMPxCFG(uint32_t idx, uint8_t pmpxcfg)
+{
+    rv_csr_t pmpcfgx = 0;
+    if (idx >= __PMP_ENTRY_NUM) return;
+
+#if __RISCV_XLEN == 32
+    if (idx < 4) {
+        pmpcfgx = __RV_CSR_READ(CSR_PMPCFG0);
+        idx = idx << 3;
+        pmpcfgx = (pmpcfgx & ~(0xFFUL << idx)) | ((rv_csr_t)pmpxcfg << idx);
+        __RV_CSR_WRITE(CSR_PMPCFG0, pmpcfgx);
+    } else if ((idx >=4) && (idx < 8)) {
+        idx -= 4;
+        pmpcfgx = __RV_CSR_READ(CSR_PMPCFG1);
+        idx = idx << 3;
+        pmpcfgx = (pmpcfgx & ~(0xFFUL << idx)) | ((rv_csr_t)pmpxcfg << idx);
+        __RV_CSR_WRITE(CSR_PMPCFG1, pmpcfgx);
+    } else if ((idx >=8) && (idx < 12)) {
+        idx -= 8;
+        pmpcfgx = __RV_CSR_READ(CSR_PMPCFG2);
+        idx = idx << 3;
+        pmpcfgx = (pmpcfgx & ~(0xFFUL << idx)) | ((rv_csr_t)pmpxcfg << idx);
+        __RV_CSR_WRITE(CSR_PMPCFG2, pmpcfgx);
+    } else {
+        idx -= 12;
+        pmpcfgx = __RV_CSR_READ(CSR_PMPCFG3);
+        idx = idx << 3;
+        pmpcfgx = (pmpcfgx & ~(0xFFUL << idx)) | ((rv_csr_t)pmpxcfg << idx);
+        __RV_CSR_WRITE(CSR_PMPCFG3, pmpcfgx);
+    }
+#elif __RISCV_XLEN == 64
+    if (idx < 8) {
+        pmpcfgx = __RV_CSR_READ(CSR_PMPCFG0);
+        idx = idx << 3;
+        pmpcfgx = (pmpcfgx & ~(0xFFULL << idx)) | ((rv_csr_t)pmpxcfg << idx);
+        __RV_CSR_WRITE(CSR_PMPCFG0, pmpcfgx);
+    } else {
+        idx -= 8;
+        pmpcfgx = __RV_CSR_READ(CSR_PMPCFG2);
+        idx = idx << 3;
+        pmpcfgx = (pmpcfgx & ~(0xFFULL << idx)) | ((rv_csr_t)pmpxcfg << idx);
+        __RV_CSR_WRITE(CSR_PMPCFG2, pmpcfgx);
+    }
+#else
+    // TODO Add RV128 Handling
+#endif
+}
+
+/**
+ * \brief   Get PMPCFGx Register by index
+ * \details Return the content of the PMPCFGx Register.
+ * \param [in]    idx    PMPCFG CSR index(0-3)
+ * \return               PMPCFGx Register value
+ * \remark
+ * - For RV64, only idx = 0 and idx = 2 is allowed.
+ *   pmpcfg0 and pmpcfg2 hold the configurations
+ *   for the 16 PMP entries, pmpcfg1 and pmpcfg3 are illegal
+ * - For RV32, pmpcfg0–pmpcfg3, hold the configurations
+ *   pmp0cfg–pmp15cfg for the 16 PMP entries
+ */
+__STATIC_INLINE rv_csr_t __get_PMPCFGx(uint32_t idx)
+{
+    switch (idx) {
+        case 0: return __RV_CSR_READ(CSR_PMPCFG0);
+        case 1: return __RV_CSR_READ(CSR_PMPCFG1);
+        case 2: return __RV_CSR_READ(CSR_PMPCFG2);
+        case 3: return __RV_CSR_READ(CSR_PMPCFG3);
+        default: return 0;
+    }
+}
+
+/**
+ * \brief   Set PMPCFGx by index
+ * \details Write the given value to the PMPCFGx Register.
+ * \param [in]    idx      PMPCFG CSR index(0-3)
+ * \param [in]    pmpcfg   PMPCFGx Register value to set
+ * \remark
+ * - For RV64, only idx = 0 and idx = 2 is allowed.
+ *   pmpcfg0 and pmpcfg2 hold the configurations
+ *   for the 16 PMP entries, pmpcfg1 and pmpcfg3 are illegal
+ * - For RV32, pmpcfg0–pmpcfg3, hold the configurations
+ *   pmp0cfg–pmp15cfg for the 16 PMP entries
+ */
+__STATIC_INLINE void __set_PMPCFGx(uint32_t idx, rv_csr_t pmpcfg)
+{
+    switch (idx) {
+        case 0: __RV_CSR_WRITE(CSR_PMPCFG0, pmpcfg); break;
+        case 1: __RV_CSR_WRITE(CSR_PMPCFG1, pmpcfg); break;
+        case 2: __RV_CSR_WRITE(CSR_PMPCFG2, pmpcfg); break;
+        case 3: __RV_CSR_WRITE(CSR_PMPCFG3, pmpcfg); break;
+        default: return;
+    }
+}
+
+/**
+ * \brief   Get PMPADDRx Register by index
+ * \details Return the content of the PMPADDRx Register.
+ * \param [in]    idx    PMP region index(0-15)
+ * \return               PMPADDRx Register value
+ */
+__STATIC_INLINE rv_csr_t __get_PMPADDRx(uint32_t idx)
+{
+    switch (idx) {
+        case 0: return __RV_CSR_READ(CSR_PMPADDR0);
+        case 1: return __RV_CSR_READ(CSR_PMPADDR1);
+        case 2: return __RV_CSR_READ(CSR_PMPADDR2);
+        case 3: return __RV_CSR_READ(CSR_PMPADDR3);
+        case 4: return __RV_CSR_READ(CSR_PMPADDR4);
+        case 5: return __RV_CSR_READ(CSR_PMPADDR5);
+        case 6: return __RV_CSR_READ(CSR_PMPADDR6);
+        case 7: return __RV_CSR_READ(CSR_PMPADDR7);
+        case 8: return __RV_CSR_READ(CSR_PMPADDR8);
+        case 9: return __RV_CSR_READ(CSR_PMPADDR9);
+        case 10: return __RV_CSR_READ(CSR_PMPADDR10);
+        case 11: return __RV_CSR_READ(CSR_PMPADDR11);
+        case 12: return __RV_CSR_READ(CSR_PMPADDR12);
+        case 13: return __RV_CSR_READ(CSR_PMPADDR13);
+        case 14: return __RV_CSR_READ(CSR_PMPADDR14);
+        case 15: return __RV_CSR_READ(CSR_PMPADDR15);
+        default: return 0;
+    }
+}
+
+/**
+ * \brief   Set PMPADDRx by index
+ * \details Write the given value to the PMPADDRx Register.
+ * \param [in]    idx      PMP region index(0-15)
+ * \param [in]    pmpaddr  PMPADDRx Register value to set
+ */
+__STATIC_INLINE void __set_PMPADDRx(uint32_t idx, rv_csr_t pmpaddr)
+{
+    switch (idx) {
+        case 0: __RV_CSR_WRITE(CSR_PMPADDR0, pmpaddr); break;
+        case 1: __RV_CSR_WRITE(CSR_PMPADDR1, pmpaddr); break;
+        case 2: __RV_CSR_WRITE(CSR_PMPADDR2, pmpaddr); break;
+        case 3: __RV_CSR_WRITE(CSR_PMPADDR3, pmpaddr); break;
+        case 4: __RV_CSR_WRITE(CSR_PMPADDR4, pmpaddr); break;
+        case 5: __RV_CSR_WRITE(CSR_PMPADDR5, pmpaddr); break;
+        case 6: __RV_CSR_WRITE(CSR_PMPADDR6, pmpaddr); break;
+        case 7: __RV_CSR_WRITE(CSR_PMPADDR7, pmpaddr); break;
+        case 8: __RV_CSR_WRITE(CSR_PMPADDR8, pmpaddr); break;
+        case 9: __RV_CSR_WRITE(CSR_PMPADDR9, pmpaddr); break;
+        case 10: __RV_CSR_WRITE(CSR_PMPADDR10, pmpaddr); break;
+        case 11: __RV_CSR_WRITE(CSR_PMPADDR11, pmpaddr); break;
+        case 12: __RV_CSR_WRITE(CSR_PMPADDR12, pmpaddr); break;
+        case 13: __RV_CSR_WRITE(CSR_PMPADDR13, pmpaddr); break;
+        case 14: __RV_CSR_WRITE(CSR_PMPADDR14, pmpaddr); break;
+        case 15: __RV_CSR_WRITE(CSR_PMPADDR15, pmpaddr); break;
+        default: return;
+    }
+}
+/** @} */ /* End of Doxygen Group NMSIS_Core_PMP_Functions */
+#endif /* defined(__PMP_PRESENT) && (__PMP_PRESENT == 1) */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /** __CORE_FEATURE_PMP_H__  */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_timer.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_timer.h
new file mode 100644
index 00000000..6e9b7af3
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_timer.h
@@ -0,0 +1,364 @@
+/*
+ * Copyright (c) 2019 Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __CORE_FEATURE_TIMER_H__
+#define __CORE_FEATURE_TIMER_H__
+/*!
+ * @file     core_feature_timer.h
+ * @brief    System Timer feature API header file for Nuclei N/NX Core
+ */
+/*
+ * System Timer Feature Configuration Macro:
+ * 1. __SYSTIMER_PRESENT:  Define whether Private System Timer is present or not.
+ *   * 0: Not present
+ *   * 1: Present
+ * 2. __SYSTIMER_BASEADDR:  Define the base address of the System Timer.
+ */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(__SYSTIMER_PRESENT) && (__SYSTIMER_PRESENT == 1)
+/**
+ * \defgroup NMSIS_Core_SysTimer_Registers     Register Define and Type Definitions Of System Timer
+ * \ingroup NMSIS_Core_Registers
+ * \brief   Type definitions and defines for system timer registers.
+ *
+ * @{
+ */
+/**
+ * \brief  Structure type to access the System Timer (SysTimer).
+ * \details
+ * Structure definition to access the system timer(SysTimer).
+ * \remarks
+ * - MSFTRST register is introduced in Nuclei N Core version 1.3(\ref __NUCLEI_N_REV >= 0x0103)
+ * - MSTOP register is renamed to MTIMECTL register in Nuclei N Core version 1.4(\ref __NUCLEI_N_REV >= 0x0104)
+ * - CMPCLREN and CLKSRC bit in MTIMECTL register is introduced in Nuclei N Core version 1.4(\ref __NUCLEI_N_REV >= 0x0104)
+ */
+typedef struct {
+    __IOM uint64_t MTIMER;                  /*!< Offset: 0x000 (R/W)  System Timer current value 64bits Register */
+    __IOM uint64_t MTIMERCMP;               /*!< Offset: 0x008 (R/W)  System Timer compare Value 64bits Register */
+    __IOM uint32_t RESERVED0[0x3F8];        /*!< Offset: 0x010 - 0xFEC Reserved */
+    __IOM uint32_t MSFTRST;                 /*!< Offset: 0xFF0 (R/W)  System Timer Software Core Reset Register */
+    __IOM uint32_t RESERVED1;               /*!< Offset: 0xFF4 Reserved */
+    __IOM uint32_t MTIMECTL;                /*!< Offset: 0xFF8 (R/W)  System Timer Control Register, previously MSTOP register */
+    __IOM uint32_t MSIP;                    /*!< Offset: 0xFFC (R/W)  System Timer SW interrupt Register */
+} SysTimer_Type;
+
+/* Timer Control / Status Register Definitions */
+#define SysTimer_MTIMECTL_TIMESTOP_Pos      0U                                          /*!< SysTick Timer MTIMECTL: TIMESTOP bit Position */
+#define SysTimer_MTIMECTL_TIMESTOP_Msk      (1UL << SysTimer_MTIMECTL_TIMESTOP_Pos)     /*!< SysTick Timer MTIMECTL: TIMESTOP Mask */
+#define SysTimer_MTIMECTL_CMPCLREN_Pos      1U                                          /*!< SysTick Timer MTIMECTL: CMPCLREN bit Position */
+#define SysTimer_MTIMECTL_CMPCLREN_Msk      (1UL << SysTimer_MTIMECTL_CMPCLREN_Pos)     /*!< SysTick Timer MTIMECTL: CMPCLREN Mask */
+#define SysTimer_MTIMECTL_CLKSRC_Pos        2U                                          /*!< SysTick Timer MTIMECTL: CLKSRC bit Position */
+#define SysTimer_MTIMECTL_CLKSRC_Msk        (1UL << SysTimer_MTIMECTL_CLKSRC_Pos)       /*!< SysTick Timer MTIMECTL: CLKSRC Mask */
+
+#define SysTimer_MSIP_MSIP_Pos              0U                                          /*!< SysTick Timer MSIP: MSIP bit Position */
+#define SysTimer_MSIP_MSIP_Msk              (1UL << SysTimer_MSIP_MSIP_Pos)             /*!< SysTick Timer MSIP: MSIP Mask */
+
+#define SysTimer_MTIMER_Msk                 (0xFFFFFFFFFFFFFFFFULL)                     /*!< SysTick Timer MTIMER value Mask */
+#define SysTimer_MTIMERCMP_Msk              (0xFFFFFFFFFFFFFFFFULL)                     /*!< SysTick Timer MTIMERCMP value Mask */
+#define SysTimer_MTIMECTL_Msk               (0xFFFFFFFFUL)                              /*!< SysTick Timer MTIMECTL/MSTOP value Mask */
+#define SysTimer_MSIP_Msk                   (0xFFFFFFFFUL)                              /*!< SysTick Timer MSIP   value Mask */
+#define SysTimer_MSFTRST_Msk                (0xFFFFFFFFUL)                              /*!< SysTick Timer MSFTRST value Mask */
+
+#define SysTimer_MSFRST_KEY                 (0x80000A5FUL)                              /*!< SysTick Timer Software Reset Request Key */
+
+#ifndef __SYSTIMER_BASEADDR
+/* Base address of SYSTIMER(__SYSTIMER_BASEADDR) should be defined in  */
+#error "__SYSTIMER_BASEADDR is not defined, please check!"
+#endif
+/* System Timer Memory mapping of Device  */
+#define SysTimer_BASE                       __SYSTIMER_BASEADDR                         /*!< SysTick Base Address */
+#define SysTimer                            ((SysTimer_Type *) SysTimer_BASE)           /*!< SysTick configuration struct */
+/** @} */ /* end of group NMSIS_Core_SysTimer_Registers */
+
+/* ##################################    SysTimer function  ############################################ */
+/**
+ * \defgroup NMSIS_Core_SysTimer SysTimer Functions
+ * \brief    Functions that configure the Core System Timer.
+ * @{
+ */
+/**
+ * \brief  Set system timer load value
+ * \details
+ * This function set the system timer load value in MTIMER register.
+ * \param [in]  value   value to set system timer MTIMER register.
+ * \remarks
+ * - Load value is 64bits wide.
+ * - \ref SysTimer_GetLoadValue
+ */
+__STATIC_FORCEINLINE void SysTimer_SetLoadValue(uint64_t value)
+{
+    SysTimer->MTIMER = value;
+}
+
+/**
+ * \brief  Get system timer load value
+ * \details
+ * This function get the system timer current value in MTIMER register.
+ * \return  current value(64bit) of system timer MTIMER register.
+ * \remarks
+ * - Load value is 64bits wide.
+ * - \ref SysTimer_SetLoadValue
+ */
+__STATIC_FORCEINLINE uint64_t SysTimer_GetLoadValue(void)
+{
+    return SysTimer->MTIMER;
+}
+
+/**
+ * \brief  Set system timer compare value
+ * \details
+ * This function set the system Timer compare value in MTIMERCMP register.
+ * \param [in]  value   compare value to set system timer MTIMERCMP register.
+ * \remarks
+ * - Compare value is 64bits wide.
+ * - If compare value is larger than current value timer interrupt generate.
+ * - Modify the load value or compare value less to clear the interrupt.
+ * - \ref SysTimer_GetCompareValue
+ */
+__STATIC_FORCEINLINE void SysTimer_SetCompareValue(uint64_t value)
+{
+    SysTimer->MTIMERCMP = value;
+}
+
+/**
+ * \brief  Get system timer compare value
+ * \details
+ * This function get the system timer compare value in MTIMERCMP register.
+ * \return  compare value of system timer MTIMERCMP register.
+ * \remarks
+ * - Compare value is 64bits wide.
+ * - \ref SysTimer_SetCompareValue
+ */
+__STATIC_FORCEINLINE uint64_t SysTimer_GetCompareValue(void)
+{
+    return SysTimer->MTIMERCMP;
+}
+
+/**
+ * \brief  Enable system timer counter running
+ * \details
+ * Enable system timer counter running by clear
+ * TIMESTOP bit in MTIMECTL register.
+ */
+__STATIC_FORCEINLINE void SysTimer_Start(void)
+{
+    SysTimer->MTIMECTL &= ~(SysTimer_MTIMECTL_TIMESTOP_Msk);
+}
+
+/**
+ * \brief  Stop system timer counter running
+ * \details
+ * Stop system timer counter running by set
+ * TIMESTOP bit in MTIMECTL register.
+ */
+__STATIC_FORCEINLINE void SysTimer_Stop(void)
+{
+    SysTimer->MTIMECTL |= SysTimer_MTIMECTL_TIMESTOP_Msk;
+}
+
+/**
+ * \brief  Set system timer control value
+ * \details
+ * This function set the system timer MTIMECTL register value.
+ * \param [in]  mctl    value to set MTIMECTL register
+ * \remarks
+ * - Bit TIMESTOP is used to start and stop timer.
+ *   Clear TIMESTOP bit to 0 to start timer, otherwise to stop timer.
+ * - Bit CMPCLREN is used to enable auto MTIMER clear to zero when MTIMER >= MTIMERCMP.
+ *   Clear CMPCLREN bit to 0 to stop auto clear MTIMER feature, otherwise to enable it.
+ * - Bit CLKSRC is used to select timer clock source.
+ *   Clear CLKSRC bit to 0 to use *mtime_toggle_a*, otherwise use *core_clk_aon*
+ * - \ref SysTimer_GetControlValue
+ */
+__STATIC_FORCEINLINE void SysTimer_SetControlValue(uint32_t mctl)
+{
+    SysTimer->MTIMECTL = (mctl & SysTimer_MTIMECTL_Msk);
+}
+
+/**
+ * \brief  Get system timer control value
+ * \details
+ * This function get the system timer MTIMECTL register value.
+ * \return  MTIMECTL register value
+ * \remarks
+ * - \ref SysTimer_SetControlValue
+ */
+__STATIC_FORCEINLINE uint32_t SysTimer_GetControlValue(void)
+{
+    return (SysTimer->MTIMECTL & SysTimer_MTIMECTL_Msk);
+}
+
+/**
+ * \brief  Trigger or set software interrupt via system timer
+ * \details
+ * This function set the system timer MSIP bit in MSIP register.
+ * \remarks
+ * - Set system timer MSIP bit and generate a SW interrupt.
+ * - \ref SysTimer_ClearSWIRQ
+ * - \ref SysTimer_GetMsipValue
+ */
+__STATIC_FORCEINLINE void SysTimer_SetSWIRQ(void)
+{
+    SysTimer->MSIP |= SysTimer_MSIP_MSIP_Msk;
+}
+
+/**
+ * \brief  Clear system timer software interrupt pending request
+ * \details
+ * This function clear the system timer MSIP bit in MSIP register.
+ * \remarks
+ * - Clear system timer MSIP bit in MSIP register to clear the software interrupt pending.
+ * - \ref SysTimer_SetSWIRQ
+ * - \ref SysTimer_GetMsipValue
+ */
+__STATIC_FORCEINLINE void SysTimer_ClearSWIRQ(void)
+{
+    SysTimer->MSIP &= ~SysTimer_MSIP_MSIP_Msk;
+}
+
+/**
+ * \brief  Get system timer MSIP register value
+ * \details
+ * This function get the system timer MSIP register value.
+ * \return    Value of Timer MSIP register.
+ * \remarks
+ * - Bit0 is SW interrupt flag.
+ *   Bit0 is 1 then SW interrupt set. Bit0 is 0 then SW interrupt clear.
+ * - \ref SysTimer_SetSWIRQ
+ * - \ref SysTimer_ClearSWIRQ
+ */
+__STATIC_FORCEINLINE uint32_t SysTimer_GetMsipValue(void)
+{
+    return (uint32_t)(SysTimer->MSIP & SysTimer_MSIP_Msk);
+}
+
+/**
+ * \brief  Set system timer MSIP register value
+ * \details
+ * This function set the system timer MSIP register value.
+ * \param [in]  msip   value to set MSIP register
+ */
+__STATIC_FORCEINLINE void SysTimer_SetMsipValue(uint32_t msip)
+{
+    SysTimer->MSIP = (msip & SysTimer_MSIP_Msk);
+}
+
+/**
+ * \brief  Do software reset request
+ * \details
+ * This function will do software reset request through MTIMER
+ * - Software need to write \ref SysTimer_MSFRST_KEY to generate software reset request
+ * - The software request flag can be cleared by reset operation to clear
+ * \remarks
+ * - The software reset is sent to SoC, SoC need to generate reset signal and send back to Core
+ * - This function will not return, it will do while(1) to wait the Core reset happened
+ */
+__STATIC_FORCEINLINE void SysTimer_SoftwareReset(void)
+{
+    SysTimer->MSFTRST = SysTimer_MSFRST_KEY;
+    while(1);
+}
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) && defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1)
+/**
+ * \brief   System Tick Configuration
+ * \details Initializes the System Timer and its non-vector interrupt, and starts the System Tick Timer.
+ *
+ *  In our default implementation, the timer counter will be set to zero, and it will start a timer compare non-vector interrupt
+ *  when it matchs the ticks user set, during the timer interrupt user should reload the system tick using \ref SysTick_Reload function
+ *  or similar function written by user, so it can produce period timer interrupt.
+ * \param [in]  ticks  Number of ticks between two interrupts.
+ * \return          0  Function succeeded.
+ * \return          1  Function failed.
+ * \remarks
+ * - For \ref __NUCLEI_N_REV >= 0x0104, the CMPCLREN bit in MTIMECTL is introduced,
+ *   but we assume that the CMPCLREN bit is set to 0, so MTIMER register will not be
+ *   auto cleared to 0 when MTIMER >= MTIMERCMP.
+ * - When the variable \ref __Vendor_SysTickConfig is set to 1, then the
+ *   function \ref SysTick_Config is not included.
+ * - In this case, the file .h must contain a vendor-specific implementation
+ *   of this function.
+ * - If user need this function to start a period timer interrupt, then in timer interrupt handler
+ *   routine code, user should call \ref SysTick_Reload with ticks to reload the timer.
+ * - This function only available when __SYSTIMER_PRESENT == 1 and __ECLIC_PRESENT == 1 and __Vendor_SysTickConfig == 0
+ * \sa
+ * - \ref SysTimer_SetCompareValue; SysTimer_SetLoadValue
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint64_t ticks)
+{
+    SysTimer_SetLoadValue(0);
+    SysTimer_SetCompareValue(ticks);
+    ECLIC_SetShvIRQ(SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT);
+    ECLIC_SetLevelIRQ(SysTimer_IRQn, 0);
+    ECLIC_EnableIRQ(SysTimer_IRQn);
+    return (0UL);
+}
+
+/**
+ * \brief   System Tick Reload
+ * \details Reload the System Timer Tick when the MTIMECMP reached TIME value
+ *
+ * \param [in]  ticks  Number of ticks between two interrupts.
+ * \return          0  Function succeeded.
+ * \return          1  Function failed.
+ * \remarks
+ * - For \ref __NUCLEI_N_REV >= 0x0104, the CMPCLREN bit in MTIMECTL is introduced,
+ *   but for this \ref SysTick_Config function, we assume this CMPCLREN bit is set to 0,
+ *   so in interrupt handler function, user still need to set the MTIMERCMP or MTIMER to reload
+ *   the system tick, if vendor want to use this timer's auto clear feature, they can define
+ *   \ref __Vendor_SysTickConfig to 1, and implement \ref SysTick_Config and \ref SysTick_Reload functions.
+ * - When the variable \ref __Vendor_SysTickConfig is set to 1, then the
+ *   function \ref SysTick_Reload is not included.
+ * - In this case, the file .h must contain a vendor-specific implementation
+ *   of this function.
+ * - This function only available when __SYSTIMER_PRESENT == 1 and __ECLIC_PRESENT == 1 and __Vendor_SysTickConfig == 0
+ * - Since the MTIMERCMP value might overflow, if overflowed, MTIMER will be set to 0, and MTIMERCMP set to ticks
+ * \sa
+ * - \ref SysTimer_SetCompareValue
+ * - \ref SysTimer_SetLoadValue
+ */
+__STATIC_FORCEINLINE uint32_t SysTick_Reload(uint64_t ticks)
+{
+    uint64_t cur_ticks = SysTimer->MTIMER;
+    uint64_t reload_ticks = ticks + cur_ticks;
+
+    if (__USUALLY(reload_ticks > cur_ticks)) {
+        SysTimer->MTIMERCMP = reload_ticks;
+    } else {
+        /* When added the ticks value, then the MTIMERCMP < TIMER,
+         * which means the MTIMERCMP is overflowed,
+         * so we need to reset the counter to zero */
+        SysTimer->MTIMER = 0;
+        SysTimer->MTIMERCMP = ticks;
+    }
+
+    return (0UL);
+}
+
+#endif /* defined(__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) */
+/** @} */ /* End of Doxygen Group NMSIS_Core_SysTimer */
+
+#endif /* defined(__SYSTIMER_PRESENT) && (__SYSTIMER_PRESENT == 1) */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /** __CORE_FEATURE_TIMER_H__  */
+
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/nmsis_compiler.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/nmsis_compiler.h
new file mode 100644
index 00000000..c5278db1
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/nmsis_compiler.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2019 Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NMSIS_COMPILER_H
+#define __NMSIS_COMPILER_H
+
+#include 
+
+/*!
+ * @file     nmsis_compiler.h
+ * @brief    NMSIS compiler generic header file
+ */
+#if defined ( __GNUC__ )
+  /** GNU GCC Compiler */
+  #include "nmsis_gcc.h"
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __NMSIS_COMPILER_H */
+
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/nmsis_core.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/nmsis_core.h
new file mode 100644
index 00000000..91a8fbcf
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/nmsis_core.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ * -- Adaptable modifications made for Nuclei Processors. --
+ * Copyright (c) 2019 Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __NMSIS_CORE_H__
+#define __NMSIS_CORE_H__
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nmsis_version.h"
+
+/**
+ * \ingroup NMSIS_Core_VersionControl
+ * @{
+ */
+/* The following enum __NUCLEI_N_REV/__NUCLEI_NX_REV definition in this file
+ * is only used for doxygen documentation generation,
+ * The .h is the real file to define it by vendor
+ */
+#if defined(__ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__)
+/**
+ * \brief Nuclei N class core revision number
+ * \details
+ * Reversion number format: [15:8] revision number, [7:0] patch number
+ * \attention
+ * This define is exclusive with \ref __NUCLEI_NX_REV
+ */
+#define __NUCLEI_N_REV (0x0104)
+/**
+ * \brief Nuclei NX class core revision number
+ * \details
+ * Reversion number format: [15:8] revision number, [7:0] patch number
+ * \attention
+ * This define is exclusive with \ref __NUCLEI_N_REV
+ */
+#define __NUCLEI_NX_REV (0x0100)
+#endif /* __ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__ */
+/** @} */ /* End of Group NMSIS_Core_VersionControl */
+
+#include "nmsis_compiler.h" /* NMSIS compiler specific defines */
+
+/* === Include Nuclei Core Related Headers === */
+/* Include core base feature header file */
+#include "core_feature_base.h"
+
+#ifndef __NMSIS_GENERIC
+/* Include core eclic feature header file */
+#include "core_feature_eclic.h"
+/* Include core systimer feature header file */
+#include "core_feature_timer.h"
+#endif
+
+/* Include core fpu feature header file */
+#include "core_feature_fpu.h"
+/* Include core dsp feature header file */
+#include "core_feature_dsp.h"
+/* Include core pmp feature header file */
+#include "core_feature_pmp.h"
+/* Include core cache feature header file */
+#include "core_feature_cache.h"
+
+/* Include compatiable functions header file */
+#include "core_compatiable.h"
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __NMSIS_CORE_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/nmsis_gcc.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/nmsis_gcc.h
new file mode 100644
index 00000000..ac093e23
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/nmsis_gcc.h
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2019 Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NMSIS_GCC_H__
+#define __NMSIS_GCC_H__
+/*!
+ * @file     nmsis_gcc.h
+ * @brief    NMSIS compiler GCC header file
+ */
+#include 
+#include "riscv_encoding.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+/**
+ * \defgroup NMSIS_Core_CompilerControl    Compiler Control
+ * \ingroup  NMSIS_Core
+ * \brief    Compiler agnostic \#define symbols for generic c/c++ source code
+ * \details
+ *
+ * The NMSIS-Core provides the header file nmsis_compiler.h with consistent \#define symbols for generate C or C++ source files that should be compiler agnostic.
+ * Each NMSIS compliant compiler should support the functionality described in this section.
+ *
+ * The header file nmsis_compiler.h is also included by each Device Header File  so that these definitions are available.
+ *   @{
+ */
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+#define __has_builtin(x) (0)
+#endif
+
+/* NMSIS compiler specific defines */
+/** \brief Pass information from the compiler to the assembler. */
+#ifndef __ASM
+#define __ASM __asm
+#endif
+
+/** \brief Recommend that function should be inlined by the compiler. */
+#ifndef __INLINE
+#define __INLINE inline
+#endif
+
+/** \brief Define a static function that may be inlined by the compiler. */
+#ifndef __STATIC_INLINE
+#define __STATIC_INLINE static inline
+#endif
+
+/** \brief Define a static function that should be always inlined by the compiler. */
+#ifndef __STATIC_FORCEINLINE
+#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+#endif
+
+/** \brief Inform the compiler that a function does not return. */
+#ifndef __NO_RETURN
+#define __NO_RETURN __attribute__((__noreturn__))
+#endif
+
+/** \brief Inform that a variable shall be retained in executable image. */
+#ifndef __USED
+#define __USED __attribute__((used))
+#endif
+
+/** \brief restrict pointer qualifier to enable additional optimizations. */
+#ifndef __WEAK
+#define __WEAK __attribute__((weak))
+#endif
+
+/** \brief specified the vector size of the variable, measured in bytes */
+#ifndef __VECTOR_SIZE
+#define __VECTOR_SIZE(x) __attribute__((vector_size(x)))
+#endif
+
+/** \brief Request smallest possible alignment. */
+#ifndef __PACKED
+#define __PACKED __attribute__((packed, aligned(1)))
+#endif
+
+/** \brief Request smallest possible alignment for a structure. */
+#ifndef __PACKED_STRUCT
+#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+
+/** \brief Request smallest possible alignment for a union. */
+#ifndef __PACKED_UNION
+#define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpacked"
+#pragma GCC diagnostic ignored "-Wattributes"
+/** \brief Packed struct for unaligned uint16_t write access */
+__PACKED_STRUCT T_UINT16_WRITE
+{
+    uint16_t v;
+};
+#pragma GCC diagnostic pop
+/** \brief Pointer for unaligned write of a uint16_t variable. */
+#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpacked"
+#pragma GCC diagnostic ignored "-Wattributes"
+/** \brief Packed struct for unaligned uint16_t read access */
+__PACKED_STRUCT T_UINT16_READ
+{
+    uint16_t v;
+};
+#pragma GCC diagnostic pop
+/** \brief Pointer for unaligned read of a uint16_t variable. */
+#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpacked"
+#pragma GCC diagnostic ignored "-Wattributes"
+/** \brief Packed struct for unaligned uint32_t write access */
+__PACKED_STRUCT T_UINT32_WRITE
+{
+    uint32_t v;
+};
+#pragma GCC diagnostic pop
+/** \brief Pointer for unaligned write of a uint32_t variable. */
+#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpacked"
+#pragma GCC diagnostic ignored "-Wattributes"
+/** \brief Packed struct for unaligned uint32_t read access */
+__PACKED_STRUCT T_UINT32_READ
+{
+    uint32_t v;
+};
+#pragma GCC diagnostic pop
+/** \brief Pointer for unaligned read of a uint32_t variable. */
+#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+
+/** \brief Minimum `x` bytes alignment for a variable. */
+#ifndef __ALIGNED
+#define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+
+/** \brief restrict pointer qualifier to enable additional optimizations. */
+#ifndef __RESTRICT
+#define __RESTRICT __restrict
+#endif
+
+/** \brief Barrier to prevent compiler from reordering instructions. */
+#ifndef __COMPILER_BARRIER
+#define __COMPILER_BARRIER() __ASM volatile("" :: \
+                                                : "memory")
+#endif
+
+/** \brief provide the compiler with branch prediction information, the branch is usually true */
+#ifndef __USUALLY
+#define __USUALLY(exp) __builtin_expect((exp), 1)
+#endif
+
+/** \brief provide the compiler with branch prediction information, the branch is rarely true */
+#ifndef __RARELY
+#define __RARELY(exp) __builtin_expect((exp), 0)
+#endif
+
+/** \brief Use this attribute to indicate that the specified function is an interrupt handler. */
+#ifndef __INTERRUPT
+#define __INTERRUPT __attribute__((interrupt))
+#endif
+
+/** @} */ /* End of Doxygen Group NMSIS_Core_CompilerControl */
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ * \defgroup NMSIS_Core_PeriphAccess     Peripheral Access
+ * \brief  Naming conventions and optional features for accessing peripherals.
+ *
+ * The section below describes the naming conventions, requirements, and optional features
+ * for accessing device specific peripherals.
+ * Most of the rules also apply to the core peripherals.
+ *
+ * The **Device Header File ** contains typically these definition
+ * and also includes the core specific header files.
+ *
+ * @{
+ */
+/** \brief Defines 'read only' permissions */
+#ifdef __cplusplus
+#define __I volatile
+#else
+#define __I volatile const
+#endif
+/** \brief Defines 'write only' permissions */
+#define __O volatile
+/** \brief Defines 'read / write' permissions */
+#define __IO volatile
+
+/* following defines should be used for structure members */
+/** \brief Defines 'read only' structure member permissions */
+#define __IM volatile const
+/** \brief Defines 'write only' structure member permissions */
+#define __OM volatile
+/** \brief Defines 'read/write' structure member permissions */
+#define __IOM volatile
+
+/**
+ * \brief   Mask and shift a bit field value for use in a register bit range.
+ * \details The macro \ref _VAL2FLD uses the #define's _Pos and _Msk of the related bit
+ * field to shift bit-field values for assigning to a register.
+ *
+ * **Example**:
+ * \code
+ * ECLIC->CFG = _VAL2FLD(CLIC_CLICCFG_NLBIT, 3);
+ * \endcode
+ * \param[in] field  Name of the register bit field.
+ * \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+ * \return           Masked and shifted value.
+ */
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field##_Pos) & field##_Msk)
+
+/**
+ * \brief   Mask and shift a register value to extract a bit filed value.
+ * \details The macro \ref _FLD2VAL uses the #define's _Pos and _Msk of the related bit
+ * field to extract the value of a bit field from a register.
+ *
+ * **Example**:
+ * \code
+ * nlbits = _FLD2VAL(CLIC_CLICCFG_NLBIT, ECLIC->CFG);
+ * \endcode
+ * \param[in] field  Name of the register bit field.
+ * \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+ * \return           Masked and shifted bit field value.
+ */
+#define _FLD2VAL(field, value) (((uint32_t)(value)&field##_Msk) >> field##_Pos)
+
+    /** @} */ /* end of group NMSIS_Core_PeriphAccess */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __NMSIS_GCC_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/nmsis_version.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/nmsis_version.h
new file mode 100644
index 00000000..16507998
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/nmsis_version.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2019 Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __NMSIS_VERSION_H
+#define __NMSIS_VERSION_H
+
+/**
+ * \defgroup NMSIS_Core_VersionControl    Version Control
+ * \ingroup  NMSIS_Core
+ * \brief    Version \#define symbols for NMSIS release specific C/C++ source code
+ * \details
+ *
+ * We followed the [semantic versioning 2.0.0](https://semver.org/) to control NMSIS version.
+ * The version format is **MAJOR.MINOR.PATCH**, increment the:
+ * 1. MAJOR version when you make incompatible API changes,
+ * 2. MINOR version when you add functionality in a backwards compatible manner, and
+ * 3. PATCH version when you make backwards compatible bug fixes.
+ *
+ * The header file `nmsis_version.h` is included by each core header so that these definitions are available.
+ *
+ * **Example Usage for NMSIS Version Check**:
+ * \code
+ *   #if defined(__NMSIS_VERSION) && (__NMSIS_VERSION >= 0x00010105)
+ *      #warning "Yes, we have NMSIS 1.1.5 or later"
+ *   #else
+ *      #error "We need NMSIS 1.1.5 or later!"
+ *   #endif
+ * \endcode
+ *
+ * @{
+ */
+
+/*!
+ * \file     nmsis_version.h
+ * \brief    NMSIS Version definitions
+ **/
+
+/**
+ * \brief   Represent the NMSIS major version
+ * \details
+ * The NMSIS major version can be used to
+ * differentiate between NMSIS major releases.
+ * */
+#define __NMSIS_VERSION_MAJOR            (1U)
+
+/**
+ * \brief   Represent the NMSIS minor version
+ * \details
+ * The NMSIS minor version can be used to
+ * query a NMSIS release update including new features.
+ *
+ **/
+#define __NMSIS_VERSION_MINOR            (0U)
+
+/**
+ * \brief   Represent the NMSIS patch version
+ * \details
+ * The NMSIS patch version can be used to
+ * show bug fixes in this package.
+ **/
+#define __NMSIS_VERSION_PATCH            (1U)
+/**
+ * \brief   Represent the NMSIS Version
+ * \details
+ * NMSIS Version format: **MAJOR.MINOR.PATCH**
+ * * MAJOR: \ref __NMSIS_VERSION_MAJOR, stored in `bits [31:16]` of \ref __NMSIS_VERSION
+ * * MINOR: \ref __NMSIS_VERSION_MINOR, stored in `bits [15:8]` of \ref __NMSIS_VERSION
+ * * PATCH: \ref __NMSIS_VERSION_PATCH, stored in `bits [7:0]` of \ref __NMSIS_VERSION
+ **/
+#define __NMSIS_VERSION                  ((__NMSIS_VERSION_MAJOR << 16U) | (__NMSIS_VERSION_MINOR << 8) | __NMSIS_VERSION_PATCH)
+
+/** @} */ /* End of Doxygen Group NMSIS_Core_VersionControl */
+#endif
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/riscv_bits.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/riscv_bits.h
new file mode 100644
index 00000000..fe0beb95
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/riscv_bits.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2019 Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __RISCV_BITS_H__
+#define __RISCV_BITS_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if __riscv_xlen == 64
+# define SLL32                  sllw
+# define STORE                  sd
+# define LOAD                   ld
+# define LWU                    lwu
+# define LOG_REGBYTES           3
+#else
+# define SLL32                  sll
+# define STORE                  sw
+# define LOAD                   lw
+# define LWU                    lw
+# define LOG_REGBYTES           2
+#endif /* __riscv_xlen */
+
+#define REGBYTES (1 << LOG_REGBYTES)
+
+#if defined(__riscv_flen)
+#if __riscv_flen == 64
+# define FPSTORE                fsd
+# define FPLOAD                 fld
+# define LOG_FPREGBYTES         3
+#else
+# define FPSTORE                fsw
+# define FPLOAD                 flw
+# define LOG_FPREGBYTES         2
+#endif /* __riscv_flen == 64 */
+#define FPREGBYTES              (1 << LOG_FPREGBYTES)
+#endif /* __riscv_flen */
+
+#define __rv_likely(x)          __builtin_expect((x), 1)
+#define __rv_unlikely(x)        __builtin_expect((x), 0)
+
+#define __RV_ROUNDUP(a, b)      ((((a)-1)/(b)+1)*(b))
+#define __RV_ROUNDDOWN(a, b)    ((a)/(b)*(b))
+
+#define __RV_MAX(a, b)          ((a) > (b) ? (a) : (b))
+#define __RV_MIN(a, b)          ((a) < (b) ? (a) : (b))
+#define __RV_CLAMP(a, lo, hi)   MIN(MAX(a, lo), hi)
+
+#define __RV_EXTRACT_FIELD(val, which)                  (((val) & (which)) / ((which) & ~((which)-1)))
+#define __RV_INSERT_FIELD(val, which, fieldval)         (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
+
+#ifdef __ASSEMBLY__
+#define _AC(X,Y)                X
+#define _AT(T,X)                X
+#else
+#define __AC(X,Y)               (X##Y)
+#define _AC(X,Y)                __AC(X,Y)
+#define _AT(T,X)                ((T)(X))
+#endif /* __ASSEMBLY__ */
+
+#define _UL(x)                  (_AC(x, UL))
+#define _ULL(x)                 (_AC(x, ULL))
+
+#define _BITUL(x)               (_UL(1) << (x))
+#define _BITULL(x)              (_ULL(1) << (x))
+
+#define UL(x)                   (_UL(x))
+#define ULL(x)                  (_ULL(x))
+
+#define STR(x)                  XSTR(x)
+#define XSTR(x)                 #x
+#define __STR(s)                #s
+#define STRINGIFY(s)            __STR(s)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /** __RISCV_BITS_H__  */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/riscv_encoding.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/riscv_encoding.h
new file mode 100644
index 00000000..a0ec9684
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/riscv_encoding.h
@@ -0,0 +1,690 @@
+/*
+ * Copyright (c) 2019 Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __RISCV_ENCODING_H__
+#define __RISCV_ENCODING_H__
+
+#include "riscv_bits.h"
+#ifdef __cplusplus
+ extern "C" {
+#endif
+/**
+ * \defgroup NMSIS_Core_CSR_Encoding    Core CSR Encodings
+ * \ingroup  NMSIS_Core
+ * \brief    NMSIS Core CSR Encodings
+ * \details
+ *
+ * The following macros are used for CSR encodings
+ *   @{
+ */
+/* === Standard CSR bit mask === */
+#define MSTATUS_UIE         0x00000001
+#define MSTATUS_SIE         0x00000002
+#define MSTATUS_HIE         0x00000004
+#define MSTATUS_MIE         0x00000008
+#define MSTATUS_UPIE        0x00000010
+#define MSTATUS_SPIE        0x00000020
+#define MSTATUS_HPIE        0x00000040
+#define MSTATUS_MPIE        0x00000080
+#define MSTATUS_SPP         0x00000100
+#define MSTATUS_MPP         0x00001800
+#define MSTATUS_FS          0x00006000
+#define MSTATUS_XS          0x00018000
+#define MSTATUS_MPRV        0x00020000
+#define MSTATUS_PUM         0x00040000
+#define MSTATUS_MXR         0x00080000
+#define MSTATUS_VM          0x1F000000
+#define MSTATUS32_SD        0x80000000
+#define MSTATUS64_SD        0x8000000000000000
+
+#define MSTATUS_FS_INITIAL  0x00002000
+#define MSTATUS_FS_CLEAN    0x00004000
+#define MSTATUS_FS_DIRTY    0x00006000
+
+#define SSTATUS_UIE         0x00000001
+#define SSTATUS_SIE         0x00000002
+#define SSTATUS_UPIE        0x00000010
+#define SSTATUS_SPIE        0x00000020
+#define SSTATUS_SPP         0x00000100
+#define SSTATUS_FS          0x00006000
+#define SSTATUS_XS          0x00018000
+#define SSTATUS_PUM         0x00040000
+#define SSTATUS32_SD        0x80000000
+#define SSTATUS64_SD        0x8000000000000000
+
+#define CSR_MCACHE_CTL_IE   0x00000001
+#define CSR_MCACHE_CTL_DE   0x00010000
+
+#define DCSR_XDEBUGVER      (3U<<30)
+#define DCSR_NDRESET        (1<<29)
+#define DCSR_FULLRESET      (1<<28)
+#define DCSR_EBREAKM        (1<<15)
+#define DCSR_EBREAKH        (1<<14)
+#define DCSR_EBREAKS        (1<<13)
+#define DCSR_EBREAKU        (1<<12)
+#define DCSR_STOPCYCLE      (1<<10)
+#define DCSR_STOPTIME       (1<<9)
+#define DCSR_CAUSE          (7<<6)
+#define DCSR_DEBUGINT       (1<<5)
+#define DCSR_HALT           (1<<3)
+#define DCSR_STEP           (1<<2)
+#define DCSR_PRV            (3<<0)
+
+#define DCSR_CAUSE_NONE     0
+#define DCSR_CAUSE_SWBP     1
+#define DCSR_CAUSE_HWBP     2
+#define DCSR_CAUSE_DEBUGINT 3
+#define DCSR_CAUSE_STEP     4
+#define DCSR_CAUSE_HALT     5
+
+#define MCONTROL_TYPE(xlen)    (0xfULL<<((xlen)-4))
+#define MCONTROL_DMODE(xlen)   (1ULL<<((xlen)-5))
+#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
+
+#define MCONTROL_SELECT     (1<<19)
+#define MCONTROL_TIMING     (1<<18)
+#define MCONTROL_ACTION     (0x3f<<12)
+#define MCONTROL_CHAIN      (1<<11)
+#define MCONTROL_MATCH      (0xf<<7)
+#define MCONTROL_M          (1<<6)
+#define MCONTROL_H          (1<<5)
+#define MCONTROL_S          (1<<4)
+#define MCONTROL_U          (1<<3)
+#define MCONTROL_EXECUTE    (1<<2)
+#define MCONTROL_STORE      (1<<1)
+#define MCONTROL_LOAD       (1<<0)
+
+#define MCONTROL_TYPE_NONE      0
+#define MCONTROL_TYPE_MATCH     2
+
+#define MCONTROL_ACTION_DEBUG_EXCEPTION   0
+#define MCONTROL_ACTION_DEBUG_MODE        1
+#define MCONTROL_ACTION_TRACE_START       2
+#define MCONTROL_ACTION_TRACE_STOP        3
+#define MCONTROL_ACTION_TRACE_EMIT        4
+
+#define MCONTROL_MATCH_EQUAL     0
+#define MCONTROL_MATCH_NAPOT     1
+#define MCONTROL_MATCH_GE        2
+#define MCONTROL_MATCH_LT        3
+#define MCONTROL_MATCH_MASK_LOW  4
+#define MCONTROL_MATCH_MASK_HIGH 5
+
+#define MIP_SSIP            (1 << IRQ_S_SOFT)
+#define MIP_HSIP            (1 << IRQ_H_SOFT)
+#define MIP_MSIP            (1 << IRQ_M_SOFT)
+#define MIP_STIP            (1 << IRQ_S_TIMER)
+#define MIP_HTIP            (1 << IRQ_H_TIMER)
+#define MIP_MTIP            (1 << IRQ_M_TIMER)
+#define MIP_SEIP            (1 << IRQ_S_EXT)
+#define MIP_HEIP            (1 << IRQ_H_EXT)
+#define MIP_MEIP            (1 << IRQ_M_EXT)
+
+#define MIE_SSIE            MIP_SSIP
+#define MIE_HSIE            MIP_HSIP
+#define MIE_MSIE            MIP_MSIP
+#define MIE_STIE            MIP_STIP
+#define MIE_HTIE            MIP_HTIP
+#define MIE_MTIE            MIP_MTIP
+#define MIE_SEIE            MIP_SEIP
+#define MIE_HEIE            MIP_HEIP
+#define MIE_MEIE            MIP_MEIP
+
+/* === P-ext CSR bit mask === */
+
+#define UCODE_OV            (0x1)
+
+/* === Nuclei custom CSR bit mask === */
+
+#define WFE_WFE                     (0x1)
+#define TXEVT_TXEVT                 (0x1)
+#define SLEEPVALUE_SLEEPVALUE       (0x1)
+
+#define MCOUNTINHIBIT_IR            (1<<2)
+#define MCOUNTINHIBIT_CY            (1<<0)
+
+#define MILM_CTL_ILM_BPA            (((1ULL<<((__riscv_xlen)-10))-1)<<10)
+#define MILM_CTL_ILM_RWECC          (1<<3)
+#define MILM_CTL_ILM_ECC_EXCP_EN    (1<<2)
+#define MILM_CTL_ILM_ECC_EN         (1<<1)
+#define MILM_CTL_ILM_EN             (1<<0)
+
+#define MDLM_CTL_DLM_BPA            (((1ULL<<((__riscv_xlen)-10))-1)<<10)
+#define MDLM_CTL_DLM_RWECC          (1<<3)
+#define MDLM_CTL_DLM_ECC_EXCP_EN    (1<<2)
+#define MDLM_CTL_DLM_ECC_EN         (1<<1)
+#define MDLM_CTL_DLM_EN             (1<<0)
+
+#define MSUBM_PTYP                  (0x3<<8)
+#define MSUBM_TYP                   (0x3<<6)
+
+#define MDCAUSE_MDCAUSE             (0x3)
+
+#define MMISC_CTL_NMI_CAUSE_FFF     (1<<9)
+#define MMISC_CTL_MISALIGN          (1<<6)
+#define MMISC_CTL_BPU               (1<<3)
+
+#define MCACHE_CTL_IC_EN            (1<<0)
+#define MCACHE_CTL_IC_SCPD_MOD      (1<<1)
+#define MCACHE_CTL_IC_ECC_EN        (1<<2)
+#define MCACHE_CTL_IC_ECC_EXCP_EN   (1<<3)
+#define MCACHE_CTL_IC_RWTECC        (1<<4)
+#define MCACHE_CTL_IC_RWDECC        (1<<5)
+#define MCACHE_CTL_DC_EN            (1<<16)
+#define MCACHE_CTL_DC_ECC_EN        (1<<17)
+#define MCACHE_CTL_DC_ECC_EXCP_EN   (1<<18)
+#define MCACHE_CTL_DC_RWTECC        (1<<19)
+#define MCACHE_CTL_DC_RWDECC        (1<<20)
+
+#define MTVT2_MTVT2EN               (1<<0)
+#define MTVT2_COMMON_CODE_ENTRY     (((1ULL<<((__riscv_xlen)-2))-1)<<2)
+
+#define MCFG_INFO_TEE               (1<<0)
+#define MCFG_INFO_ECC               (1<<1)
+#define MCFG_INFO_CLIC              (1<<2)
+#define MCFG_INFO_PLIC              (1<<3)
+#define MCFG_INFO_FIO               (1<<4)
+#define MCFG_INFO_PPI               (1<<5)
+#define MCFG_INFO_NICE              (1<<6)
+#define MCFG_INFO_ILM               (1<<7)
+#define MCFG_INFO_DLM               (1<<8)
+#define MCFG_INFO_ICACHE            (1<<9)
+#define MCFG_INFO_DCACHE            (1<<10)
+
+#define MICFG_IC_SET                (0xF<<0)
+#define MICFG_IC_WAY                (0x7<<4)
+#define MICFG_IC_LSIZE              (0x7<<7)
+#define MICFG_IC_ECC                (0x1<<10)
+#define MICFG_ILM_SIZE              (0x1F<<16)
+#define MICFG_ILM_XONLY             (0x1<<21)
+#define MICFG_ILM_ECC               (0x1<<22)
+
+#define MDCFG_DC_SET                (0xF<<0)
+#define MDCFG_DC_WAY                (0x7<<4)
+#define MDCFG_DC_LSIZE              (0x7<<7)
+#define MDCFG_DC_ECC                (0x1<<10)
+#define MDCFG_DLM_SIZE              (0x1F<<16)
+#define MDCFG_DLM_ECC               (0x1<<21)
+
+#define MPPICFG_INFO_PPI_SIZE       (0x1F<<1)
+#define MPPICFG_INFO_PPI_BPA        (((1ULL<<((__riscv_xlen)-10))-1)<<10)
+
+#define MFIOCFG_INFO_FIO_SIZE       (0x1F<<1)
+#define MFIOCFG_INFO_FIO_BPA        (((1ULL<<((__riscv_xlen)-10))-1)<<10)
+
+#define MECC_LOCK_ECC_LOCK          (0x1)
+
+#define MECC_CODE_CODE              (0x1FF)
+#define MECC_CODE_RAMID             (0x1F<<16)
+#define MECC_CODE_SRAMID            (0x1F<<24)
+
+#define CCM_SUEN_SUEN               (0x1<<0)
+#define CCM_DATA_DATA               (0x7<<0)
+#define CCM_COMMAND_COMMAND         (0x1F<<0)
+
+#define SIP_SSIP MIP_SSIP
+#define SIP_STIP MIP_STIP
+
+#define PRV_U 0
+#define PRV_S 1
+#define PRV_H 2
+#define PRV_M 3
+
+#define VM_MBARE 0
+#define VM_MBB   1
+#define VM_MBBID 2
+#define VM_SV32  8
+#define VM_SV39  9
+#define VM_SV48  10
+
+#define IRQ_S_SOFT   1
+#define IRQ_H_SOFT   2
+#define IRQ_M_SOFT   3
+#define IRQ_S_TIMER  5
+#define IRQ_H_TIMER  6
+#define IRQ_M_TIMER  7
+#define IRQ_S_EXT    9
+#define IRQ_H_EXT    10
+#define IRQ_M_EXT    11
+#define IRQ_COP      12
+#define IRQ_HOST     13
+
+
+/* === FPU FRM Rounding Mode === */
+/** FPU Round to Nearest, ties to Even*/
+#define FRM_RNDMODE_RNE     0x0
+/** FPU Round Towards Zero */
+#define FRM_RNDMODE_RTZ     0x1
+/** FPU Round Down (towards -inf) */
+#define FRM_RNDMODE_RDN     0x2
+/** FPU Round Up (towards +inf) */
+#define FRM_RNDMODE_RUP     0x3
+/** FPU Round to nearest, ties to Max Magnitude */
+#define FRM_RNDMODE_RMM     0x4
+/**
+ * In instruction's rm, selects dynamic rounding mode.
+ * In Rounding Mode register, Invalid */
+#define FRM_RNDMODE_DYN     0x7
+
+/* === FPU FFLAGS Accrued Exceptions === */
+/** FPU Inexact */
+#define FFLAGS_AE_NX        (1<<0)
+/** FPU Underflow */
+#define FFLAGS_AE_UF        (1<<1)
+/** FPU Overflow */
+#define FFLAGS_AE_OF        (1<<2)
+/** FPU Divide by Zero */
+#define FFLAGS_AE_DZ        (1<<3)
+/** FPU Invalid Operation */
+#define FFLAGS_AE_NV        (1<<4)
+
+/** Floating Point Register f0-f31, eg. f0 -> FREG(0) */
+#define FREG(idx)           f##idx
+
+
+/* === PMP CFG Bits === */
+#define PMP_R                0x01
+#define PMP_W                0x02
+#define PMP_X                0x04
+#define PMP_A                0x18
+#define PMP_A_TOR            0x08
+#define PMP_A_NA4            0x10
+#define PMP_A_NAPOT          0x18
+#define PMP_L                0x80
+
+#define PMP_SHIFT            2
+#define PMP_COUNT            16
+
+// page table entry (PTE) fields
+#define PTE_V     0x001 // Valid
+#define PTE_R     0x002 // Read
+#define PTE_W     0x004 // Write
+#define PTE_X     0x008 // Execute
+#define PTE_U     0x010 // User
+#define PTE_G     0x020 // Global
+#define PTE_A     0x040 // Accessed
+#define PTE_D     0x080 // Dirty
+#define PTE_SOFT  0x300 // Reserved for Software
+
+#define PTE_PPN_SHIFT 10
+
+#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
+
+#ifdef __riscv
+
+#ifdef __riscv64
+# define MSTATUS_SD MSTATUS64_SD
+# define SSTATUS_SD SSTATUS64_SD
+# define RISCV_PGLEVEL_BITS 9
+#else
+# define MSTATUS_SD MSTATUS32_SD
+# define SSTATUS_SD SSTATUS32_SD
+# define RISCV_PGLEVEL_BITS 10
+#endif /* __riscv64 */
+
+#define RISCV_PGSHIFT 12
+#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
+
+#endif /* __riscv */
+
+/**
+ * \defgroup NMSIS_Core_CSR_Registers    Core CSR Registers
+ * \ingroup  NMSIS_Core
+ * \brief    NMSIS Core CSR Register Definitions
+ * \details
+ *
+ * The following macros are used for CSR Register Defintions.
+ *   @{
+ */
+/* === Standard RISC-V CSR Registers === */
+#define CSR_USTATUS 0x0
+#define CSR_FFLAGS 0x1
+#define CSR_FRM 0x2
+#define CSR_FCSR 0x3
+#define CSR_CYCLE 0xc00
+#define CSR_TIME 0xc01
+#define CSR_INSTRET 0xc02
+#define CSR_HPMCOUNTER3 0xc03
+#define CSR_HPMCOUNTER4 0xc04
+#define CSR_HPMCOUNTER5 0xc05
+#define CSR_HPMCOUNTER6 0xc06
+#define CSR_HPMCOUNTER7 0xc07
+#define CSR_HPMCOUNTER8 0xc08
+#define CSR_HPMCOUNTER9 0xc09
+#define CSR_HPMCOUNTER10 0xc0a
+#define CSR_HPMCOUNTER11 0xc0b
+#define CSR_HPMCOUNTER12 0xc0c
+#define CSR_HPMCOUNTER13 0xc0d
+#define CSR_HPMCOUNTER14 0xc0e
+#define CSR_HPMCOUNTER15 0xc0f
+#define CSR_HPMCOUNTER16 0xc10
+#define CSR_HPMCOUNTER17 0xc11
+#define CSR_HPMCOUNTER18 0xc12
+#define CSR_HPMCOUNTER19 0xc13
+#define CSR_HPMCOUNTER20 0xc14
+#define CSR_HPMCOUNTER21 0xc15
+#define CSR_HPMCOUNTER22 0xc16
+#define CSR_HPMCOUNTER23 0xc17
+#define CSR_HPMCOUNTER24 0xc18
+#define CSR_HPMCOUNTER25 0xc19
+#define CSR_HPMCOUNTER26 0xc1a
+#define CSR_HPMCOUNTER27 0xc1b
+#define CSR_HPMCOUNTER28 0xc1c
+#define CSR_HPMCOUNTER29 0xc1d
+#define CSR_HPMCOUNTER30 0xc1e
+#define CSR_HPMCOUNTER31 0xc1f
+#define CSR_SSTATUS 0x100
+#define CSR_SIE 0x104
+#define CSR_STVEC 0x105
+#define CSR_SSCRATCH 0x140
+#define CSR_SEPC 0x141
+#define CSR_SCAUSE 0x142
+#define CSR_SBADADDR 0x143
+#define CSR_SIP 0x144
+#define CSR_SPTBR 0x180
+#define CSR_MSTATUS 0x300
+#define CSR_MISA 0x301
+#define CSR_MEDELEG 0x302
+#define CSR_MIDELEG 0x303
+#define CSR_MIE 0x304
+#define CSR_MTVEC 0x305
+#define CSR_MCOUNTEREN 0x306
+#define CSR_MSCRATCH 0x340
+#define CSR_MEPC 0x341
+#define CSR_MCAUSE 0x342
+#define CSR_MBADADDR 0x343
+#define CSR_MTVAL 0x343
+#define CSR_MIP 0x344
+#define CSR_PMPCFG0 0x3a0
+#define CSR_PMPCFG1 0x3a1
+#define CSR_PMPCFG2 0x3a2
+#define CSR_PMPCFG3 0x3a3
+#define CSR_PMPADDR0 0x3b0
+#define CSR_PMPADDR1 0x3b1
+#define CSR_PMPADDR2 0x3b2
+#define CSR_PMPADDR3 0x3b3
+#define CSR_PMPADDR4 0x3b4
+#define CSR_PMPADDR5 0x3b5
+#define CSR_PMPADDR6 0x3b6
+#define CSR_PMPADDR7 0x3b7
+#define CSR_PMPADDR8 0x3b8
+#define CSR_PMPADDR9 0x3b9
+#define CSR_PMPADDR10 0x3ba
+#define CSR_PMPADDR11 0x3bb
+#define CSR_PMPADDR12 0x3bc
+#define CSR_PMPADDR13 0x3bd
+#define CSR_PMPADDR14 0x3be
+#define CSR_PMPADDR15 0x3bf
+#define CSR_TSELECT 0x7a0
+#define CSR_TDATA1 0x7a1
+#define CSR_TDATA2 0x7a2
+#define CSR_TDATA3 0x7a3
+#define CSR_DCSR 0x7b0
+#define CSR_DPC 0x7b1
+#define CSR_DSCRATCH 0x7b2
+#define CSR_MCYCLE 0xb00
+#define CSR_MINSTRET 0xb02
+#define CSR_MHPMCOUNTER3 0xb03
+#define CSR_MHPMCOUNTER4 0xb04
+#define CSR_MHPMCOUNTER5 0xb05
+#define CSR_MHPMCOUNTER6 0xb06
+#define CSR_MHPMCOUNTER7 0xb07
+#define CSR_MHPMCOUNTER8 0xb08
+#define CSR_MHPMCOUNTER9 0xb09
+#define CSR_MHPMCOUNTER10 0xb0a
+#define CSR_MHPMCOUNTER11 0xb0b
+#define CSR_MHPMCOUNTER12 0xb0c
+#define CSR_MHPMCOUNTER13 0xb0d
+#define CSR_MHPMCOUNTER14 0xb0e
+#define CSR_MHPMCOUNTER15 0xb0f
+#define CSR_MHPMCOUNTER16 0xb10
+#define CSR_MHPMCOUNTER17 0xb11
+#define CSR_MHPMCOUNTER18 0xb12
+#define CSR_MHPMCOUNTER19 0xb13
+#define CSR_MHPMCOUNTER20 0xb14
+#define CSR_MHPMCOUNTER21 0xb15
+#define CSR_MHPMCOUNTER22 0xb16
+#define CSR_MHPMCOUNTER23 0xb17
+#define CSR_MHPMCOUNTER24 0xb18
+#define CSR_MHPMCOUNTER25 0xb19
+#define CSR_MHPMCOUNTER26 0xb1a
+#define CSR_MHPMCOUNTER27 0xb1b
+#define CSR_MHPMCOUNTER28 0xb1c
+#define CSR_MHPMCOUNTER29 0xb1d
+#define CSR_MHPMCOUNTER30 0xb1e
+#define CSR_MHPMCOUNTER31 0xb1f
+#define CSR_MUCOUNTEREN 0x320
+#define CSR_MSCOUNTEREN 0x321
+#define CSR_MHPMEVENT3 0x323
+#define CSR_MHPMEVENT4 0x324
+#define CSR_MHPMEVENT5 0x325
+#define CSR_MHPMEVENT6 0x326
+#define CSR_MHPMEVENT7 0x327
+#define CSR_MHPMEVENT8 0x328
+#define CSR_MHPMEVENT9 0x329
+#define CSR_MHPMEVENT10 0x32a
+#define CSR_MHPMEVENT11 0x32b
+#define CSR_MHPMEVENT12 0x32c
+#define CSR_MHPMEVENT13 0x32d
+#define CSR_MHPMEVENT14 0x32e
+#define CSR_MHPMEVENT15 0x32f
+#define CSR_MHPMEVENT16 0x330
+#define CSR_MHPMEVENT17 0x331
+#define CSR_MHPMEVENT18 0x332
+#define CSR_MHPMEVENT19 0x333
+#define CSR_MHPMEVENT20 0x334
+#define CSR_MHPMEVENT21 0x335
+#define CSR_MHPMEVENT22 0x336
+#define CSR_MHPMEVENT23 0x337
+#define CSR_MHPMEVENT24 0x338
+#define CSR_MHPMEVENT25 0x339
+#define CSR_MHPMEVENT26 0x33a
+#define CSR_MHPMEVENT27 0x33b
+#define CSR_MHPMEVENT28 0x33c
+#define CSR_MHPMEVENT29 0x33d
+#define CSR_MHPMEVENT30 0x33e
+#define CSR_MHPMEVENT31 0x33f
+#define CSR_MVENDORID 0xf11
+#define CSR_MARCHID 0xf12
+#define CSR_MIMPID 0xf13
+#define CSR_MHARTID 0xf14
+#define CSR_CYCLEH 0xc80
+#define CSR_TIMEH 0xc81
+#define CSR_INSTRETH 0xc82
+#define CSR_HPMCOUNTER3H 0xc83
+#define CSR_HPMCOUNTER4H 0xc84
+#define CSR_HPMCOUNTER5H 0xc85
+#define CSR_HPMCOUNTER6H 0xc86
+#define CSR_HPMCOUNTER7H 0xc87
+#define CSR_HPMCOUNTER8H 0xc88
+#define CSR_HPMCOUNTER9H 0xc89
+#define CSR_HPMCOUNTER10H 0xc8a
+#define CSR_HPMCOUNTER11H 0xc8b
+#define CSR_HPMCOUNTER12H 0xc8c
+#define CSR_HPMCOUNTER13H 0xc8d
+#define CSR_HPMCOUNTER14H 0xc8e
+#define CSR_HPMCOUNTER15H 0xc8f
+#define CSR_HPMCOUNTER16H 0xc90
+#define CSR_HPMCOUNTER17H 0xc91
+#define CSR_HPMCOUNTER18H 0xc92
+#define CSR_HPMCOUNTER19H 0xc93
+#define CSR_HPMCOUNTER20H 0xc94
+#define CSR_HPMCOUNTER21H 0xc95
+#define CSR_HPMCOUNTER22H 0xc96
+#define CSR_HPMCOUNTER23H 0xc97
+#define CSR_HPMCOUNTER24H 0xc98
+#define CSR_HPMCOUNTER25H 0xc99
+#define CSR_HPMCOUNTER26H 0xc9a
+#define CSR_HPMCOUNTER27H 0xc9b
+#define CSR_HPMCOUNTER28H 0xc9c
+#define CSR_HPMCOUNTER29H 0xc9d
+#define CSR_HPMCOUNTER30H 0xc9e
+#define CSR_HPMCOUNTER31H 0xc9f
+#define CSR_MCYCLEH 0xb80
+#define CSR_MINSTRETH 0xb82
+#define CSR_MHPMCOUNTER3H 0xb83
+#define CSR_MHPMCOUNTER4H 0xb84
+#define CSR_MHPMCOUNTER5H 0xb85
+#define CSR_MHPMCOUNTER6H 0xb86
+#define CSR_MHPMCOUNTER7H 0xb87
+#define CSR_MHPMCOUNTER8H 0xb88
+#define CSR_MHPMCOUNTER9H 0xb89
+#define CSR_MHPMCOUNTER10H 0xb8a
+#define CSR_MHPMCOUNTER11H 0xb8b
+#define CSR_MHPMCOUNTER12H 0xb8c
+#define CSR_MHPMCOUNTER13H 0xb8d
+#define CSR_MHPMCOUNTER14H 0xb8e
+#define CSR_MHPMCOUNTER15H 0xb8f
+#define CSR_MHPMCOUNTER16H 0xb90
+#define CSR_MHPMCOUNTER17H 0xb91
+#define CSR_MHPMCOUNTER18H 0xb92
+#define CSR_MHPMCOUNTER19H 0xb93
+#define CSR_MHPMCOUNTER20H 0xb94
+#define CSR_MHPMCOUNTER21H 0xb95
+#define CSR_MHPMCOUNTER22H 0xb96
+#define CSR_MHPMCOUNTER23H 0xb97
+#define CSR_MHPMCOUNTER24H 0xb98
+#define CSR_MHPMCOUNTER25H 0xb99
+#define CSR_MHPMCOUNTER26H 0xb9a
+#define CSR_MHPMCOUNTER27H 0xb9b
+#define CSR_MHPMCOUNTER28H 0xb9c
+#define CSR_MHPMCOUNTER29H 0xb9d
+#define CSR_MHPMCOUNTER30H 0xb9e
+#define CSR_MHPMCOUNTER31H 0xb9f
+
+/* === TEE CSR Registers === */
+#define CSR_SPMPCFG0            0x1A0
+#define CSR_SPMPCFG1            0x1A1
+#define CSR_SPMPCFG2            0x1A2
+#define CSR_SPMPCFG3            0x1A3
+#define CSR_SPMPADDR0           0x1B0
+#define CSR_SPMPADDR1           0x1B1
+#define CSR_SPMPADDR2           0x1B2
+#define CSR_SPMPADDR3           0x1B3
+#define CSR_SPMPADDR4           0x1B4
+#define CSR_SPMPADDR5           0x1B5
+#define CSR_SPMPADDR6           0x1B6
+#define CSR_SPMPADDR7           0x1B7
+#define CSR_SPMPADDR8           0x1B8
+#define CSR_SPMPADDR9           0x1B9
+#define CSR_SPMPADDR10          0x1BA
+#define CSR_SPMPADDR11          0x1BB
+#define CSR_SPMPADDR12          0x1BC
+#define CSR_SPMPADDR13          0x1BD
+#define CSR_SPMPADDR14          0x1BE
+#define CSR_SPMPADDR15          0x1BF
+
+#define CSR_JALSNXTI            0x947
+#define CSR_STVT2               0x948
+#define CSR_PUSHSCAUSE          0x949
+#define CSR_PUSHSEPC            0x94A
+
+
+/* === CLIC CSR Registers === */
+#define CSR_MTVT                0x307
+#define CSR_MNXTI               0x345
+#define CSR_MINTSTATUS          0x346
+#define CSR_MSCRATCHCSW         0x348
+#define CSR_MSCRATCHCSWL        0x349
+#define CSR_MCLICBASE           0x350
+
+/* === P-Extension Registers === */
+#define CSR_UCODE               0x801
+
+/* === Nuclei custom CSR Registers === */
+#define CSR_MCOUNTINHIBIT       0x320
+#define CSR_MILM_CTL            0x7C0
+#define CSR_MDLM_CTL            0x7C1
+#define CSR_MECC_CODE           0x7C2
+#define CSR_MNVEC               0x7C3
+#define CSR_MSUBM               0x7C4
+#define CSR_MDCAUSE             0x7C9
+#define CSR_MCACHE_CTL          0x7CA
+#define CSR_MMISC_CTL           0x7D0
+#define CSR_MSAVESTATUS         0x7D6
+#define CSR_MSAVEEPC1           0x7D7
+#define CSR_MSAVECAUSE1         0x7D8
+#define CSR_MSAVEEPC2           0x7D9
+#define CSR_MSAVECAUSE2         0x7DA
+#define CSR_MSAVEDCAUSE1        0x7DB
+#define CSR_MSAVEDCAUSE2        0x7DC
+#define CSR_MTLB_CTL            0x7DD
+#define CSR_MECC_LOCK           0x7DE
+#define CSR_MFP16MODE           0x7E2
+#define CSR_LSTEPFORC           0x7E9
+#define CSR_PUSHMSUBM           0x7EB
+#define CSR_MTVT2               0x7EC
+#define CSR_JALMNXTI            0x7ED
+#define CSR_PUSHMCAUSE          0x7EE
+#define CSR_PUSHMEPC            0x7EF
+#define CSR_MPPICFG_INFO        0x7F0
+#define CSR_MFIOCFG_INFO        0x7F1
+#define CSR_MSMPCFG_INFO        0x7F7
+#define CSR_SLEEPVALUE          0x811
+#define CSR_TXEVT               0x812
+#define CSR_WFE                 0x810
+#define CSR_MICFG_INFO          0xFC0
+#define CSR_MDCFG_INFO          0xFC1
+#define CSR_MCFG_INFO           0xFC2
+#define CSR_MTLBCFG_INFO        0xFC3
+
+/* === Nuclei CCM Registers === */
+#define CSR_CCM_MBEGINADDR      0x7CB
+#define CSR_CCM_MCOMMAND        0x7CC
+#define CSR_CCM_MDATA           0x7CD
+#define CSR_CCM_SUEN            0x7CE
+#define CSR_CCM_SBEGINADDR      0x5CB
+#define CSR_CCM_SCOMMAND        0x5CC
+#define CSR_CCM_SDATA           0x5CD
+#define CSR_CCM_UBEGINADDR      0x4CB
+#define CSR_CCM_UCOMMAND        0x4CC
+#define CSR_CCM_UDATA           0x4CD
+#define CSR_CCM_FPIPE           0x4CF
+
+/** @} */ /** End of Doxygen Group NMSIS_Core_CSR_Registers **/
+
+/* Exception Code in MCAUSE CSR */
+#define CAUSE_MISALIGNED_FETCH 0x0
+#define CAUSE_FAULT_FETCH 0x1
+#define CAUSE_ILLEGAL_INSTRUCTION 0x2
+#define CAUSE_BREAKPOINT 0x3
+#define CAUSE_MISALIGNED_LOAD 0x4
+#define CAUSE_FAULT_LOAD 0x5
+#define CAUSE_MISALIGNED_STORE 0x6
+#define CAUSE_FAULT_STORE 0x7
+#define CAUSE_USER_ECALL 0x8
+#define CAUSE_SUPERVISOR_ECALL 0x9
+#define CAUSE_HYPERVISOR_ECALL 0xa
+#define CAUSE_MACHINE_ECALL 0xb
+
+/* Exception Subcode in MDCAUSE CSR */
+#define DCAUSE_FAULT_FETCH_PMP      0x1
+#define DCAUSE_FAULT_FETCH_INST     0x2
+
+#define DCAUSE_FAULT_LOAD_PMP       0x1
+#define DCAUSE_FAULT_LOAD_INST      0x2
+#define DCAUSE_FAULT_LOAD_NICE      0x3
+
+#define DCAUSE_FAULT_STORE_PMP      0x1
+#define DCAUSE_FAULT_STORE_INST     0x2
+
+/** @} */ /** End of Doxygen Group NMSIS_Core_CSR_Encoding **/
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __RISCV_ENCODING_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/CMakeLists.txt b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/CMakeLists.txt
new file mode 100644
index 00000000..b140a927
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/CMakeLists.txt
@@ -0,0 +1,52 @@
+################# Add global include #################
+list(APPEND ADD_INCLUDE
+"${CMAKE_CURRENT_SOURCE_DIR}/core"
+"${CMAKE_CURRENT_SOURCE_DIR}/common"
+"${CMAKE_CURRENT_SOURCE_DIR}/class/cdc"
+"${CMAKE_CURRENT_SOURCE_DIR}/class/hid"
+"${CMAKE_CURRENT_SOURCE_DIR}/class/msc"
+"${CMAKE_CURRENT_SOURCE_DIR}/class/video"
+"${CMAKE_CURRENT_SOURCE_DIR}/class/audio"
+"${CMAKE_CURRENT_SOURCE_DIR}/class/winusb"
+)
+#######################################################
+
+################# Add private include #################
+# list(APPEND ADD_PRIVATE_INCLUDE
+# )
+#######################################################
+
+############## Add current dir source files ###########
+file(GLOB_RECURSE sources "${CMAKE_CURRENT_SOURCE_DIR}/core/*.c"
+"${CMAKE_CURRENT_SOURCE_DIR}/class/*.c"
+)
+list(APPEND ADD_SRCS  ${sources})
+# aux_source_directory(src ADD_SRCS)
+#######################################################
+
+########### Add required/dependent components #########
+#list(APPEND ADD_REQUIREMENTS xxx)
+#######################################################
+
+############ Add static libs ##########################
+#list(APPEND ADD_STATIC_LIB "libxxx.a")
+#######################################################
+
+############ Add dynamic libs #########################
+# list(APPEND ADD_DYNAMIC_LIB "libxxx.so"
+# )
+#######################################################
+
+############ Add global compile option ################
+#add components denpend on this component
+if(CONFIG_USB_HS)
+list(APPEND ADD_DEFINITIONS -DCONFIG_USB_HS)
+endif()
+#######################################################
+
+############ Add private compile option ################
+#add compile option for this component that won't affect other modules
+# list(APPEND ADD_PRIVATE_DEFINITIONS -Dxxx)
+#######################################################
+
+generate_library()
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/audio/usbd_audio.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/audio/usbd_audio.c
new file mode 100644
index 00000000..94d4311f
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/audio/usbd_audio.c
@@ -0,0 +1,114 @@
+#include "usbd_core.h"
+#include "usbd_audio.h"
+
+struct usbd_audio_control_info audio_control_info = { 0xdb00, 0x0000, 0x0100, 0xf600, 0 };
+
+int audio_class_request_handler(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len)
+{
+    USBD_LOG_DBG("AUDIO Class request: "
+                 "bRequest 0x%02x\r\n",
+                 setup->bRequest);
+
+    switch (setup->bRequest) {
+        case AUDIO_REQUEST_SET_CUR:
+
+            if (setup->wValueL == 0x01) {
+                if (setup->wValueH == AUDIO_FU_CONTROL_MUTE) {
+                    memcpy(&audio_control_info.mute, *data, *len);
+                } else if (setup->wValueH == AUDIO_FU_CONTROL_VOLUME) {
+                    memcpy(&audio_control_info.vol_current, *data, *len);
+                    uint32_t vol;
+                    if (audio_control_info.vol_current == 0) {
+                        vol = 100;
+                    } else {
+                        vol = (audio_control_info.vol_current - 0xDB00 + 1) * 100 / (0xFFFF - 0xDB00);
+                    }
+                    usbd_audio_set_volume(vol);
+                    USBD_LOG_INFO("current audio volume:%d\r\n", vol);
+                }
+            }
+
+            break;
+
+        case AUDIO_REQUEST_GET_CUR:
+            if (setup->wValueH == AUDIO_FU_CONTROL_MUTE) {
+                *data = (uint8_t *)&audio_control_info.mute;
+                *len = 1;
+            } else if (setup->wValueH == AUDIO_FU_CONTROL_VOLUME) {
+                *data = (uint8_t *)&audio_control_info.vol_current;
+                *len = 2;
+            }
+
+            break;
+
+        case AUDIO_REQUEST_SET_RES:
+            break;
+
+        case AUDIO_REQUEST_SET_MEM:
+            break;
+
+        case AUDIO_REQUEST_GET_MIN:
+            *data = (uint8_t *)&audio_control_info.vol_min;
+            *len = 2;
+            break;
+
+        case AUDIO_REQUEST_GET_MAX:
+            *data = (uint8_t *)&audio_control_info.vol_max;
+            *len = 2;
+            break;
+
+        case AUDIO_REQUEST_GET_RES:
+            *data = (uint8_t *)&audio_control_info.vol_res;
+            *len = 2;
+            break;
+        case AUDIO_REQUEST_GET_MEM:
+            *data[0] = 0;
+            *len = 1;
+            break;
+
+        default:
+            USBD_LOG_WRN("Unhandled Audio Class bRequest 0x%02x\r\n", setup->bRequest);
+            return -1;
+    }
+
+    return 0;
+}
+
+void audio_notify_handler(uint8_t event, void *arg)
+{
+    switch (event) {
+        case USB_EVENT_RESET:
+
+            break;
+
+        case USB_EVENT_SOF:
+            break;
+
+        case USB_EVENT_SET_INTERFACE:
+            usbd_audio_set_interface_callback(((uint8_t *)arg)[3]);
+            break;
+
+        default:
+            break;
+    }
+}
+
+__weak void usbd_audio_set_volume(uint8_t vol)
+{
+}
+
+void usbd_audio_add_interface(usbd_class_t *class, usbd_interface_t *intf)
+{
+    static usbd_class_t *last_class = NULL;
+
+    if (last_class != class) {
+        last_class = class;
+        usbd_class_register(class);
+    }
+
+    intf->class_handler = audio_class_request_handler;
+    intf->custom_handler = NULL;
+    intf->vendor_handler = NULL;
+    intf->notify_handler = audio_notify_handler;
+    usbd_class_add_interface(class, intf);
+}
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/audio/usbd_audio.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/audio/usbd_audio.h
new file mode 100644
index 00000000..35f3fe25
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/audio/usbd_audio.h
@@ -0,0 +1,277 @@
+/**
+ * @file
+ * @brief USB Audio Device Class public header
+ *
+ * Header follows below documentation:
+ * - USB Device Class Definition for Audio Devices (audio10.pdf)
+ *
+ * Additional documentation considered a part of USB Audio v1.0:
+ * - USB Device Class Definition for Audio Data Formats (frmts10.pdf)
+ * - USB Device Class Definition for Terminal Types (termt10.pdf)
+ */
+
+#ifndef _USBD_AUDIO_H_
+#define _USBD_AUDIO_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Audio Interface Subclass Codes
+ * Refer to Table A-2 from audio10.pdf
+ */
+#define AUDIO_SUBCLASS_UNDEFINED      0x00
+#define AUDIO_SUBCLASS_AUDIOCONTROL   0x01
+#define AUDIO_SUBCLASS_AUDIOSTREAMING 0x02
+#define AUDIO_SUBCLASS_MIDISTREAMING  0x03
+
+#define AUDIO_PROTOCOL_UNDEFINED 0x00U
+
+#define AUDIO_ENDPOINT_GENERAL 0x01U
+
+/** Audio Class-Specific Control Interface Descriptor Subtypes
+ * Refer to Table A-5 from audio10.pdf
+ */
+#define AUDIO_CONTROL_UNDEFINED       0x01U
+#define AUDIO_CONTROL_HEADER          0x01U
+#define AUDIO_CONTROL_INPUT_TERMINAL  0x02U
+#define AUDIO_CONTROL_OUTPUT_TERMINAL 0x03U
+#define AUDIO_CONTROL_MIXER_UNIT      0x04U
+#define AUDIO_CONTROL_SELECTOR_UNIT   0x05U
+#define AUDIO_CONTROL_FEATURE_UNIT    0x06U
+#define AUDIO_CONTROL_PROCESSING_UNIT 0x07U
+#define AUDIO_CONTROL_EXTENSION_UNIT  0x08U
+
+/** Audio Class-Specific AS Interface Descriptor Subtypes
+ * Refer to Table A-6 from audio10.pdf
+ */
+#define AUDIO_STREAMING_UNDEFINED       0x00U
+#define AUDIO_STREAMING_GENERAL         0x01U
+#define AUDIO_STREAMING_FORMAT_TYPE     0x02U
+#define AUDIO_STREAMING_FORMAT_SPECIFIC 0x03U
+
+/** Audio Class-Specific Request Codes
+ * Refer to Table A-9 from audio10.pdf
+ */
+#define AUDIO_REQUEST_UNDEFINED 0x00
+#define AUDIO_REQUEST_SET_CUR   0x01
+#define AUDIO_REQUEST_GET_CUR   0x81
+#define AUDIO_REQUEST_SET_MIN   0x02
+#define AUDIO_REQUEST_GET_MIN   0x82
+#define AUDIO_REQUEST_SET_MAX   0x03
+#define AUDIO_REQUEST_GET_MAX   0x83
+#define AUDIO_REQUEST_SET_RES   0x04
+#define AUDIO_REQUEST_GET_RES   0x84
+#define AUDIO_REQUEST_SET_MEM   0x05
+#define AUDIO_REQUEST_GET_MEM   0x85
+#define AUDIO_REQUEST_GET_STAT  0xFF
+
+/* Feature Unit Control Bits */
+#define AUDIO_CONTROL_MUTE              0x0001
+#define AUDIO_CONTROL_VOLUME            0x0002
+#define AUDIO_CONTROL_BASS              0x0004
+#define AUDIO_CONTROL_MID               0x0008
+#define AUDIO_CONTROL_TREBLE            0x0010
+#define AUDIO_CONTROL_GRAPHIC_EQUALIZER 0x0020
+#define AUDIO_CONTROL_AUTOMATIC_GAIN    0x0040
+#define AUDIO_CONTROL_DEALY             0x0080
+#define AUDIO_CONTROL_BASS_BOOST        0x0100
+#define AUDIO_CONTROL_LOUDNESS          0x0200
+
+/** Feature Unit Control Selectors
+ * Refer to Table A-11 from audio10.pdf
+ */
+#define AUDIO_FU_CONTROL_MUTE              0x01
+#define AUDIO_FU_CONTROL_VOLUME            0x02
+#define AUDIO_FU_CONTROL_BASS              0x03
+#define AUDIO_FU_CONTROL_MID               0x04
+#define AUDIO_FU_CONTROL_TREBLE            0x05
+#define AUDIO_FU_CONTROL_GRAPHIC_EQUALIZER 0x06
+#define AUDIO_FU_CONTROL_AUTOMATIC_GAIN    0x07
+#define AUDIO_FU_CONTROL_DELAY             0x08
+#define AUDIO_FU_CONTROL_BASS_BOOST        0x09
+#define AUDIO_FU_CONTROL_LOUDNESS          0x0A
+
+/* Audio Descriptor Types */
+#define AUDIO_UNDEFINED_DESCRIPTOR_TYPE     0x20
+#define AUDIO_DEVICE_DESCRIPTOR_TYPE        0x21
+#define AUDIO_CONFIGURATION_DESCRIPTOR_TYPE 0x22
+#define AUDIO_STRING_DESCRIPTOR_TYPE        0x23
+#define AUDIO_INTERFACE_DESCRIPTOR_TYPE     0x24
+#define AUDIO_ENDPOINT_DESCRIPTOR_TYPE      0x25
+
+/* Audio Data Format Type I Codes */
+#define AUDIO_FORMAT_TYPE_I_UNDEFINED 0x0000
+#define AUDIO_FORMAT_PCM              0x0001
+#define AUDIO_FORMAT_PCM8             0x0002
+#define AUDIO_FORMAT_IEEE_FLOAT       0x0003
+#define AUDIO_FORMAT_ALAW             0x0004
+#define AUDIO_FORMAT_MULAW            0x0005
+
+/* Predefined Audio Channel Configuration Bits */
+#define AUDIO_CHANNEL_M   0x0000 /* Mono */
+#define AUDIO_CHANNEL_L   0x0001 /* Left Front */
+#define AUDIO_CHANNEL_R   0x0002 /* Right Front */
+#define AUDIO_CHANNEL_C   0x0004 /* Center Front */
+#define AUDIO_CHANNEL_LFE 0x0008 /* Low Freq. Enhance. */
+#define AUDIO_CHANNEL_LS  0x0010 /* Left Surround */
+#define AUDIO_CHANNEL_RS  0x0020 /* Right Surround */
+#define AUDIO_CHANNEL_LC  0x0040 /* Left of Center */
+#define AUDIO_CHANNEL_RC  0x0080 /* Right of Center */
+#define AUDIO_CHANNEL_S   0x0100 /* Surround */
+#define AUDIO_CHANNEL_SL  0x0200 /* Side Left */
+#define AUDIO_CHANNEL_SR  0x0400 /* Side Right */
+#define AUDIO_CHANNEL_T   0x0800 /* Top */
+
+#define AUDIO_FORMAT_TYPE_I   0x01
+#define AUDIO_FORMAT_TYPE_II  0x02
+#define AUDIO_FORMAT_TYPE_III 0x03
+
+/** USB Terminal Types
+ * Refer to Table 2-1 - Table 2-4 from termt10.pdf
+ */
+enum usb_audio_terminal_types {
+    /* USB Terminal Types */
+    USB_AUDIO_USB_UNDEFINED = 0x0100,
+    USB_AUDIO_USB_STREAMING = 0x0101,
+    USB_AUDIO_USB_VENDOR_SPEC = 0x01FF,
+
+    /* Input Terminal Types */
+    USB_AUDIO_IN_UNDEFINED = 0x0200,
+    USB_AUDIO_IN_MICROPHONE = 0x0201,
+    USB_AUDIO_IN_DESKTOP_MIC = 0x0202,
+    USB_AUDIO_IN_PERSONAL_MIC = 0x0203,
+    USB_AUDIO_IN_OM_DIR_MIC = 0x0204,
+    USB_AUDIO_IN_MIC_ARRAY = 0x0205,
+    USB_AUDIO_IN_PROC_MIC_ARRAY = 0x0205,
+
+    /* Output Terminal Types */
+    USB_AUDIO_OUT_UNDEFINED = 0x0300,
+    USB_AUDIO_OUT_SPEAKER = 0x0301,
+    USB_AUDIO_OUT_HEADPHONES = 0x0302,
+    USB_AUDIO_OUT_HEAD_AUDIO = 0x0303,
+    USB_AUDIO_OUT_DESKTOP_SPEAKER = 0x0304,
+    USB_AUDIO_OUT_ROOM_SPEAKER = 0x0305,
+    USB_AUDIO_OUT_COMM_SPEAKER = 0x0306,
+    USB_AUDIO_OUT_LOW_FREQ_SPEAKER = 0x0307,
+
+    /* Bi-directional Terminal Types */
+    USB_AUDIO_IO_UNDEFINED = 0x0400,
+    USB_AUDIO_IO_HANDSET = 0x0401,
+    USB_AUDIO_IO_HEADSET = 0x0402,
+    USB_AUDIO_IO_SPEAKERPHONE_ECHO_NONE = 0x0403,
+    USB_AUDIO_IO_SPEAKERPHONE_ECHO_SUP = 0x0404,
+    USB_AUDIO_IO_SPEAKERPHONE_ECHO_CAN = 0x0405,
+};
+
+/**
+ * @warning Size of baInterface is 2 just to make it useable
+ * for all kind of devices: headphones, microphone and headset.
+ * Actual size of the struct should be checked by reading
+ * .bLength.
+ */
+struct cs_ac_if_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bDescriptorSubtype;
+    uint16_t bcdADC;
+    uint16_t wTotalLength;
+    uint8_t bInCollection;
+    uint8_t baInterfaceNr[2];
+} __packed;
+
+struct input_terminal_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bDescriptorSubtype;
+    uint8_t bTerminalID;
+    uint16_t wTerminalType;
+    uint8_t bAssocTerminal;
+    uint8_t bNrChannels;
+    uint16_t wChannelConfig;
+    uint8_t iChannelNames;
+    uint8_t iTerminal;
+} __packed;
+
+/**
+ * @note Size of Feature unit descriptor is not fixed.
+ * This structure is just a helper not a common type.
+ */
+struct feature_unit_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bDescriptorSubtype;
+    uint8_t bUnitID;
+    uint8_t bSourceID;
+    uint8_t bControlSize;
+    uint16_t bmaControls[1];
+} __packed;
+
+struct output_terminal_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bDescriptorSubtype;
+    uint8_t bTerminalID;
+    uint16_t wTerminalType;
+    uint8_t bAssocTerminal;
+    uint8_t bSourceID;
+    uint8_t iTerminal;
+} __packed;
+
+struct as_cs_interface_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bDescriptorSubtype;
+    uint8_t bTerminalLink;
+    uint8_t bDelay;
+    uint16_t wFormatTag;
+} __packed;
+
+struct format_type_i_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bDescriptorSubtype;
+    uint8_t bFormatType;
+    uint8_t bNrChannels;
+    uint8_t bSubframeSize;
+    uint8_t bBitResolution;
+    uint8_t bSamFreqType;
+    uint8_t tSamFreq[3];
+} __packed;
+
+struct std_as_ad_endpoint_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bEndpointAddress;
+    uint8_t bmAttributes;
+    uint16_t wMaxPacketSize;
+    uint8_t bInterval;
+    uint8_t bRefresh;
+    uint8_t bSynchAddress;
+} __packed;
+
+struct cs_as_ad_ep_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bDescriptorSubtype;
+    uint8_t bmAttributes;
+    uint8_t bLockDelayUnits;
+    uint16_t wLockDelay;
+} __packed;
+
+struct usbd_audio_control_info {
+    uint16_t vol_min;
+    uint16_t vol_max;
+    uint16_t vol_res;
+    uint16_t vol_current;
+    uint8_t mute;
+};
+
+void usbd_audio_add_interface(usbd_class_t *class, usbd_interface_t *intf);
+void usbd_audio_set_interface_callback(uint8_t value);
+void usbd_audio_set_volume(uint8_t vol);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _USB_AUDIO_H_ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/cdc/usbd_cdc.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/cdc/usbd_cdc.c
new file mode 100644
index 00000000..c48a74a8
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/cdc/usbd_cdc.c
@@ -0,0 +1,171 @@
+/**
+ * @file usbd_cdc.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "usbd_core.h"
+#include "usbd_cdc.h"
+
+const char *stop_name[] = { "1", "1.5", "2" };
+const char *parity_name[] = { "N", "O", "E", "M", "S" };
+
+/* Device data structure */
+struct cdc_acm_cfg_private {
+    /* CDC ACM line coding properties. LE order */
+    struct cdc_line_coding line_coding;
+    /* CDC ACM line state bitmap, DTE side */
+    uint8_t line_state;
+    /* CDC ACM serial state bitmap, DCE side */
+    uint8_t serial_state;
+    /* CDC ACM notification sent status */
+    uint8_t notification_sent;
+    /* CDC ACM configured flag */
+    bool configured;
+    /* CDC ACM suspended flag */
+    bool suspended;
+    uint32_t uart_first_init_flag;
+
+} usbd_cdc_acm_cfg;
+
+static void usbd_cdc_acm_reset(void)
+{
+    usbd_cdc_acm_cfg.line_coding.dwDTERate = 2000000;
+    usbd_cdc_acm_cfg.line_coding.bDataBits = 8;
+    usbd_cdc_acm_cfg.line_coding.bParityType = 0;
+    usbd_cdc_acm_cfg.line_coding.bCharFormat = 0;
+    usbd_cdc_acm_cfg.configured = false;
+    usbd_cdc_acm_cfg.uart_first_init_flag = 0;
+}
+
+/**
+ * @brief Handler called for Class requests not handled by the USB stack.
+ *
+ * @param setup    Information about the request to execute.
+ * @param len       Size of the buffer.
+ * @param data      Buffer containing the request result.
+ *
+ * @return  0 on success, negative errno code on fail.
+ */
+static int cdc_acm_class_request_handler(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len)
+{
+    USBD_LOG_DBG("CDC Class request: "
+                 "bRequest 0x%02x\r\n",
+                 setup->bRequest);
+
+    switch (setup->bRequest) {
+        case CDC_REQUEST_SET_LINE_CODING:
+
+            /*******************************************************************************/
+            /* Line Coding Structure                                                       */
+            /*-----------------------------------------------------------------------------*/
+            /* Offset | Field       | Size | Value  | Description                          */
+            /* 0      | dwDTERate   |   4  | Number |Data terminal rate, in bits per second*/
+            /* 4      | bCharFormat |   1  | Number | Stop bits                            */
+            /*                                        0 - 1 Stop bit                       */
+            /*                                        1 - 1.5 Stop bits                    */
+            /*                                        2 - 2 Stop bits                      */
+            /* 5      | bParityType |  1   | Number | Parity                               */
+            /*                                        0 - None                             */
+            /*                                        1 - Odd                              */
+            /*                                        2 - Even                             */
+            /*                                        3 - Mark                             */
+            /*                                        4 - Space                            */
+            /* 6      | bDataBits  |   1   | Number Data bits (5, 6, 7, 8 or 16).          */
+            /*******************************************************************************/
+            if (usbd_cdc_acm_cfg.uart_first_init_flag == 0) {
+                usbd_cdc_acm_cfg.uart_first_init_flag = 1;
+                return 0;
+            }
+
+            memcpy(&usbd_cdc_acm_cfg.line_coding, *data, sizeof(usbd_cdc_acm_cfg.line_coding));
+            USBD_LOG_DBG("CDC_SET_LINE_CODING <%d %d %s %s>\r\n",
+                         usbd_cdc_acm_cfg.line_coding.dwDTERate,
+                         usbd_cdc_acm_cfg.line_coding.bDataBits,
+                         parity_name[usbd_cdc_acm_cfg.line_coding.bParityType],
+                         stop_name[usbd_cdc_acm_cfg.line_coding.bCharFormat]);
+            usbd_cdc_acm_set_line_coding(usbd_cdc_acm_cfg.line_coding.dwDTERate, usbd_cdc_acm_cfg.line_coding.bDataBits,
+                                         usbd_cdc_acm_cfg.line_coding.bParityType, usbd_cdc_acm_cfg.line_coding.bCharFormat);
+            break;
+
+        case CDC_REQUEST_SET_CONTROL_LINE_STATE:
+            usbd_cdc_acm_cfg.line_state = (uint8_t)setup->wValue;
+            bool dtr = (setup->wValue & 0x01);
+            bool rts = (setup->wValue & 0x02);
+            USBD_LOG_DBG("DTR 0x%x,RTS 0x%x\r\n",
+                         dtr, rts);
+            usbd_cdc_acm_set_dtr(dtr);
+            usbd_cdc_acm_set_rts(rts);
+            break;
+
+        case CDC_REQUEST_GET_LINE_CODING:
+            *data = (uint8_t *)(&usbd_cdc_acm_cfg.line_coding);
+            *len = sizeof(usbd_cdc_acm_cfg.line_coding);
+            USBD_LOG_DBG("CDC_GET_LINE_CODING %d %d %d %d\r\n",
+                         usbd_cdc_acm_cfg.line_coding.dwDTERate,
+                         usbd_cdc_acm_cfg.line_coding.bCharFormat,
+                         usbd_cdc_acm_cfg.line_coding.bParityType,
+                         usbd_cdc_acm_cfg.line_coding.bDataBits);
+            break;
+
+        default:
+            USBD_LOG_WRN("Unhandled CDC Class bRequest 0x%02x\r\n", setup->bRequest);
+            return -1;
+    }
+
+    return 0;
+}
+
+static void cdc_notify_handler(uint8_t event, void *arg)
+{
+    switch (event) {
+        case USB_EVENT_RESET:
+            usbd_cdc_acm_reset();
+            break;
+
+        default:
+            break;
+    }
+}
+
+__weak void usbd_cdc_acm_set_line_coding(uint32_t baudrate, uint8_t databits, uint8_t parity, uint8_t stopbits)
+{
+}
+__weak void usbd_cdc_acm_set_dtr(bool dtr)
+{
+}
+__weak void usbd_cdc_acm_set_rts(bool rts)
+{
+}
+
+void usbd_cdc_add_acm_interface(usbd_class_t *class, usbd_interface_t *intf)
+{
+    static usbd_class_t *last_class = NULL;
+
+    if (last_class != class) {
+        last_class = class;
+        usbd_class_register(class);
+    }
+
+    intf->class_handler = cdc_acm_class_request_handler;
+    intf->custom_handler = NULL;
+    intf->vendor_handler = NULL;
+    intf->notify_handler = cdc_notify_handler;
+    usbd_class_add_interface(class, intf);
+}
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/cdc/usbd_cdc.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/cdc/usbd_cdc.h
new file mode 100644
index 00000000..33c2ac29
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/cdc/usbd_cdc.h
@@ -0,0 +1,442 @@
+/**
+ * @file
+ * @brief USB Communications Device Class (CDC) public header
+ *
+ * Header follows the Class Definitions for
+ * Communications Devices Specification (CDC120-20101103-track.pdf),
+ * PSTN Devices Specification (PSTN120.pdf) and
+ * Ethernet Control Model Devices Specification (ECM120.pdf).
+ * Header is limited to ACM and ECM Subclasses.
+ */
+
+#ifndef _USBD_CDC_H
+#define _USBD_CDC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ *      Definitions  based on usbcdc11.pdf (www.usb.org)
+ *----------------------------------------------------------------------------*/
+/* Communication device class specification version 1.10 */
+#define CDC_V1_10 0x0110U
+// Communication device class specification version 1.2
+#define CDC_V1_2_0 0x0120U
+
+/* Communication interface class code */
+/* (usbcdc11.pdf, 4.2, Table 15) */
+#define CDC_COMMUNICATION_INTERFACE_CLASS 0x02U
+
+/* Communication interface class subclass codes */
+/* (usbcdc11.pdf, 4.3, Table 16) */
+#define CDC_DIRECT_LINE_CONTROL_MODEL         0x01U
+#define CDC_ABSTRACT_CONTROL_MODEL            0x02U
+#define CDC_TELEPHONE_CONTROL_MODEL           0x03U
+#define CDC_MULTI_CHANNEL_CONTROL_MODEL       0x04U
+#define CDC_CAPI_CONTROL_MODEL                0x05U
+#define CDC_ETHERNET_NETWORKING_CONTROL_MODEL 0x06U
+#define CDC_ATM_NETWORKING_CONTROL_MODEL      0x07U
+#define CDC_WIRELESS_HANDSET_CONTROL_MODEL    0x08U
+#define CDC_DEVICE_MANAGEMENT                 0x09U
+#define CDC_MOBILE_DIRECT_LINE_MODEL          0x0AU
+#define CDC_OBEX                              0x0BU
+#define CDC_ETHERNET_EMULATION_MODEL          0x0CU
+#define CDC_NETWORK_CONTROL_MODEL             0x0DU
+
+/* Communication interface class control protocol codes */
+/* (usbcdc11.pdf, 4.4, Table 17) */
+#define CDC_COMMON_PROTOCOL_NONE                            0x00U
+#define CDC_COMMON_PROTOCOL_AT_COMMANDS                     0x01U
+#define CDC_COMMON_PROTOCOL_AT_COMMANDS_PCCA_101            0x02U
+#define CDC_COMMON_PROTOCOL_AT_COMMANDS_PCCA_101_AND_ANNEXO 0x03U
+#define CDC_COMMON_PROTOCOL_AT_COMMANDS_GSM_707             0x04U
+#define CDC_COMMON_PROTOCOL_AT_COMMANDS_3GPP_27007          0x05U
+#define CDC_COMMON_PROTOCOL_AT_COMMANDS_CDMA                0x06U
+#define CDC_COMMON_PROTOCOL_ETHERNET_EMULATION_MODEL        0x07U
+// NCM Communication Interface Protocol Codes
+// (usbncm10.pdf, 4.2, Table 4-2)
+#define CDC_NCM_PROTOCOL_NONE 0x00U
+#define CDC_NCM_PROTOCOL_OEM  0xFEU
+
+/* Data interface class code */
+/* (usbcdc11.pdf, 4.5, Table 18) */
+#define CDC_DATA_INTERFACE_CLASS 0x0A
+
+/* Data interface class protocol codes */
+/* (usbcdc11.pdf, 4.7, Table 19) */
+#define CDC_DATA_PROTOCOL_ISDN_BRI            0x30
+#define CDC_DATA_PROTOCOL_HDLC                0x31
+#define CDC_DATA_PROTOCOL_TRANSPARENT         0x32
+#define CDC_DATA_PROTOCOL_Q921_MANAGEMENT     0x50
+#define CDC_DATA_PROTOCOL_Q921_DATA_LINK      0x51
+#define CDC_DATA_PROTOCOL_Q921_MULTIPLEXOR    0x52
+#define CDC_DATA_PROTOCOL_V42                 0x90
+#define CDC_DATA_PROTOCOL_EURO_ISDN           0x91
+#define CDC_DATA_PROTOCOL_V24_RATE_ADAPTATION 0x92
+#define CDC_DATA_PROTOCOL_CAPI                0x93
+#define CDC_DATA_PROTOCOL_HOST_BASED_DRIVER   0xFD
+#define CDC_DATA_PROTOCOL_DESCRIBED_IN_PUFD   0xFE
+
+/* Type values for bDescriptorType field of functional descriptors */
+/* (usbcdc11.pdf, 5.2.3, Table 24) */
+#define CDC_CS_INTERFACE 0x24
+#define CDC_CS_ENDPOINT  0x25
+
+/* Type values for bDescriptorSubtype field of functional descriptors */
+/* (usbcdc11.pdf, 5.2.3, Table 25) */
+#define CDC_FUNC_DESC_HEADER                          0x00
+#define CDC_FUNC_DESC_CALL_MANAGEMENT                 0x01
+#define CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT     0x02
+#define CDC_FUNC_DESC_DIRECT_LINE_MANAGEMENT          0x03
+#define CDC_FUNC_DESC_TELEPHONE_RINGER                0x04
+#define CDC_FUNC_DESC_REPORTING_CAPABILITIES          0x05
+#define CDC_FUNC_DESC_UNION                           0x06
+#define CDC_FUNC_DESC_COUNTRY_SELECTION               0x07
+#define CDC_FUNC_DESC_TELEPHONE_OPERATIONAL_MODES     0x08
+#define CDC_FUNC_DESC_USB_TERMINAL                    0x09
+#define CDC_FUNC_DESC_NETWORK_CHANNEL                 0x0A
+#define CDC_FUNC_DESC_PROTOCOL_UNIT                   0x0B
+#define CDC_FUNC_DESC_EXTENSION_UNIT                  0x0C
+#define CDC_FUNC_DESC_MULTI_CHANNEL_MANAGEMENT        0x0D
+#define CDC_FUNC_DESC_CAPI_CONTROL_MANAGEMENT         0x0E
+#define CDC_FUNC_DESC_ETHERNET_NETWORKING             0x0F
+#define CDC_FUNC_DESC_ATM_NETWORKING                  0x10
+#define CDC_FUNC_DESC_WIRELESS_HANDSET_CONTROL_MODEL  0x11
+#define CDC_FUNC_DESC_MOBILE_DIRECT_LINE_MODEL        0x12
+#define CDC_FUNC_DESC_MOBILE_DIRECT_LINE_MODEL_DETAIL 0x13
+#define CDC_FUNC_DESC_DEVICE_MANAGEMENT_MODEL         0x14
+#define CDC_FUNC_DESC_OBEX                            0x15
+#define CDC_FUNC_DESC_COMMAND_SET                     0x16
+#define CDC_FUNC_DESC_COMMAND_SET_DETAIL              0x17
+#define CDC_FUNC_DESC_TELEPHONE_CONTROL_MODEL         0x18
+#define CDC_FUNC_DESC_OBEX_SERVICE_IDENTIFIER         0x19
+
+/* CDC class-specific request codes */
+/* (usbcdc11.pdf, 6.2, Table 46) */
+/* see Table 45 for info about the specific requests. */
+#define CDC_REQUEST_SEND_ENCAPSULATED_COMMAND      0x00
+#define CDC_REQUEST_GET_ENCAPSULATED_RESPONSE      0x01
+#define CDC_REQUEST_SET_COMM_FEATURE               0x02
+#define CDC_REQUEST_GET_COMM_FEATURE               0x03
+#define CDC_REQUEST_CLEAR_COMM_FEATURE             0x04
+#define CDC_REQUEST_SET_AUX_LINE_STATE             0x10
+#define CDC_REQUEST_SET_HOOK_STATE                 0x11
+#define CDC_REQUEST_PULSE_SETUP                    0x12
+#define CDC_REQUEST_SEND_PULSE                     0x13
+#define CDC_REQUEST_SET_PULSE_TIME                 0x14
+#define CDC_REQUEST_RING_AUX_JACK                  0x15
+#define CDC_REQUEST_SET_LINE_CODING                0x20
+#define CDC_REQUEST_GET_LINE_CODING                0x21
+#define CDC_REQUEST_SET_CONTROL_LINE_STATE         0x22
+#define CDC_REQUEST_SEND_BREAK                     0x23
+#define CDC_REQUEST_SET_RINGER_PARMS               0x30
+#define CDC_REQUEST_GET_RINGER_PARMS               0x31
+#define CDC_REQUEST_SET_OPERATION_PARMS            0x32
+#define CDC_REQUEST_GET_OPERATION_PARMS            0x33
+#define CDC_REQUEST_SET_LINE_PARMS                 0x34
+#define CDC_REQUEST_GET_LINE_PARMS                 0x35
+#define CDC_REQUEST_DIAL_DIGITS                    0x36
+#define CDC_REQUEST_SET_UNIT_PARAMETER             0x37
+#define CDC_REQUEST_GET_UNIT_PARAMETER             0x38
+#define CDC_REQUEST_CLEAR_UNIT_PARAMETER           0x39
+#define CDC_REQUEST_GET_PROFILE                    0x3A
+#define CDC_REQUEST_SET_ETHERNET_MULTICAST_FILTERS 0x40
+#define CDC_REQUEST_SET_ETHERNET_PMP_FILTER        0x41
+#define CDC_REQUEST_GET_ETHERNET_PMP_FILTER        0x42
+#define CDC_REQUEST_SET_ETHERNET_PACKET_FILTER     0x43
+#define CDC_REQUEST_GET_ETHERNET_STATISTIC         0x44
+#define CDC_REQUEST_SET_ATM_DATA_FORMAT            0x50
+#define CDC_REQUEST_GET_ATM_DEVICE_STATISTICS      0x51
+#define CDC_REQUEST_SET_ATM_DEFAULT_VC             0x52
+#define CDC_REQUEST_GET_ATM_VC_STATISTICS          0x53
+
+/* Communication feature selector codes */
+/* (usbcdc11.pdf, 6.2.2..6.2.4, Table 47) */
+#define CDC_ABSTRACT_STATE  0x01
+#define CDC_COUNTRY_SETTING 0x02
+
+/** Control Signal Bitmap Values for SetControlLineState */
+#define SET_CONTROL_LINE_STATE_RTS 0x02
+#define SET_CONTROL_LINE_STATE_DTR 0x01
+
+/* Feature Status returned for ABSTRACT_STATE Selector */
+/* (usbcdc11.pdf, 6.2.3, Table 48) */
+#define CDC_IDLE_SETTING          (1 << 0)
+#define CDC_DATA_MULTPLEXED_STATE (1 << 1)
+
+/* Control signal bitmap values for the SetControlLineState request */
+/* (usbcdc11.pdf, 6.2.14, Table 51) */
+#define CDC_DTE_PRESENT      (1 << 0)
+#define CDC_ACTIVATE_CARRIER (1 << 1)
+
+/* CDC class-specific notification codes */
+/* (usbcdc11.pdf, 6.3, Table 68) */
+/* see Table 67 for Info about class-specific notifications */
+#define CDC_NOTIFICATION_NETWORK_CONNECTION 0x00
+#define CDC_RESPONSE_AVAILABLE              0x01
+#define CDC_AUX_JACK_HOOK_STATE             0x08
+#define CDC_RING_DETECT                     0x09
+#define CDC_NOTIFICATION_SERIAL_STATE       0x20
+#define CDC_CALL_STATE_CHANGE               0x28
+#define CDC_LINE_STATE_CHANGE               0x29
+#define CDC_CONNECTION_SPEED_CHANGE         0x2A
+
+/* UART state bitmap values (Serial state notification). */
+/* (usbcdc11.pdf, 6.3.5, Table 69) */
+#define CDC_SERIAL_STATE_OVERRUN        (1 << 6) /* receive data overrun error has occurred */
+#define CDC_SERIAL_STATE_OVERRUN_Pos    (6)
+#define CDC_SERIAL_STATE_OVERRUN_Msk    (1 << CDC_SERIAL_STATE_OVERRUN_Pos)
+#define CDC_SERIAL_STATE_PARITY         (1 << 5) /* parity error has occurred */
+#define CDC_SERIAL_STATE_PARITY_Pos     (5)
+#define CDC_SERIAL_STATE_PARITY_Msk     (1 << CDC_SERIAL_STATE_PARITY_Pos)
+#define CDC_SERIAL_STATE_FRAMING        (1 << 4) /* framing error has occurred */
+#define CDC_SERIAL_STATE_FRAMING_Pos    (4)
+#define CDC_SERIAL_STATE_FRAMING_Msk    (1 << CDC_SERIAL_STATE_FRAMING_Pos)
+#define CDC_SERIAL_STATE_RING           (1 << 3) /* state of ring signal detection */
+#define CDC_SERIAL_STATE_RING_Pos       (3)
+#define CDC_SERIAL_STATE_RING_Msk       (1 << CDC_SERIAL_STATE_RING_Pos)
+#define CDC_SERIAL_STATE_BREAK          (1 << 2) /* state of break detection */
+#define CDC_SERIAL_STATE_BREAK_Pos      (2)
+#define CDC_SERIAL_STATE_BREAK_Msk      (1 << CDC_SERIAL_STATE_BREAK_Pos)
+#define CDC_SERIAL_STATE_TX_CARRIER     (1 << 1) /* state of transmission carrier */
+#define CDC_SERIAL_STATE_TX_CARRIER_Pos (1)
+#define CDC_SERIAL_STATE_TX_CARRIER_Msk (1 << CDC_SERIAL_STATE_TX_CARRIER_Pos)
+#define CDC_SERIAL_STATE_RX_CARRIER     (1 << 0) /* state of receiver carrier */
+#define CDC_SERIAL_STATE_RX_CARRIER_Pos (0)
+#define CDC_SERIAL_STATE_RX_CARRIER_Msk (1 << CDC_SERIAL_STATE_RX_CARRIER_Pos)
+
+/*------------------------------------------------------------------------------
+ *      Structures  based on usbcdc11.pdf (www.usb.org)
+ *----------------------------------------------------------------------------*/
+
+/* Header functional descriptor */
+/* (usbcdc11.pdf, 5.2.3.1) */
+/* This header must precede any list of class-specific descriptors. */
+struct cdc_header_descriptor {
+    uint8_t bFunctionLength;    /* size of this descriptor in bytes */
+    uint8_t bDescriptorType;    /* CS_INTERFACE descriptor type */
+    uint8_t bDescriptorSubtype; /* Header functional descriptor subtype */
+    uint16_t bcdCDC;            /* USB CDC specification release version */
+} __packed;
+
+/* Call management functional descriptor */
+/* (usbcdc11.pdf, 5.2.3.2) */
+/* Describes the processing of calls for the communication class interface. */
+struct cdc_call_management_descriptor {
+    uint8_t bFunctionLength;    /* size of this descriptor in bytes */
+    uint8_t bDescriptorType;    /* CS_INTERFACE descriptor type */
+    uint8_t bDescriptorSubtype; /* call management functional descriptor subtype */
+    uint8_t bmCapabilities;     /* capabilities that this configuration supports */
+    uint8_t bDataInterface;     /* interface number of the data class interface used for call management (optional) */
+} __packed;
+
+/* Abstract control management functional descriptor */
+/* (usbcdc11.pdf, 5.2.3.3) */
+/* Describes the command supported by the communication interface class with the Abstract Control Model subclass code. */
+struct cdc_abstract_control_management_descriptor {
+    uint8_t bFunctionLength;    /* size of this descriptor in bytes */
+    uint8_t bDescriptorType;    /* CS_INTERFACE descriptor type */
+    uint8_t bDescriptorSubtype; /* abstract control management functional descriptor subtype */
+    uint8_t bmCapabilities;     /* capabilities supported by this configuration */
+} __packed;
+
+/* Union functional descriptors */
+/* (usbcdc11.pdf, 5.2.3.8) */
+/* Describes the relationship between a group of interfaces that can be considered to form a functional unit. */
+struct cdc_union_descriptor {
+    uint8_t bFunctionLength;    /* size of this descriptor in bytes */
+    uint8_t bDescriptorType;    /* CS_INTERFACE descriptor type */
+    uint8_t bDescriptorSubtype; /* union functional descriptor subtype */
+    uint8_t bMasterInterface;   /* interface number designated as master */
+} __packed;
+
+/* Union functional descriptors with one slave interface */
+/* (usbcdc11.pdf, 5.2.3.8) */
+struct cdc_union_1slave_descriptor {
+    uint8_t bFunctionLength;
+    uint8_t bDescriptorType;
+    uint8_t bDescriptorSubtype;
+    uint8_t bControlInterface;
+    uint8_t bSubordinateInterface0;
+} __packed;
+
+/* Line coding structure for GET_LINE_CODING / SET_LINE_CODING class requests*/
+/* Format of the data returned when a GetLineCoding request is received */
+/* (usbcdc11.pdf, 6.2.13) */
+struct cdc_line_coding {
+    uint32_t dwDTERate;  /* Data terminal rate in bits per second */
+    uint8_t bCharFormat; /* Number of stop bits */
+    uint8_t bParityType; /* Parity bit type */
+    uint8_t bDataBits;   /* Number of data bits */
+} __packed;
+
+/** Data structure for the notification about SerialState */
+struct cdc_acm_notification {
+    uint8_t bmRequestType;
+    uint8_t bNotificationType;
+    uint16_t wValue;
+    uint16_t wIndex;
+    uint16_t wLength;
+    uint16_t data;
+} __packed;
+
+/** Ethernet Networking Functional Descriptor */
+struct cdc_ecm_descriptor {
+    uint8_t bFunctionLength;
+    uint8_t bDescriptorType;
+    uint8_t bDescriptorSubtype;
+    uint8_t iMACAddress;
+    uint32_t bmEthernetStatistics;
+    uint16_t wMaxSegmentSize;
+    uint16_t wNumberMCFilters;
+    uint8_t bNumberPowerFilters;
+} __packed;
+
+/*Length of template descriptor: 66 bytes*/
+#define CDC_ACM_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 4 + 5 + 7 + 9 + 7 + 7)
+// clang-format off
+#ifndef CONFIG_USB_HS
+#define CDC_ACM_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, str_idx)               \
+    /* Interface Associate */                                                                  \
+    0x08,                                                  /* bLength */                       \
+    USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION,             /* bDescriptorType */               \
+    bFirstInterface,                                       /* bFirstInterface */               \
+    0x02,                                                  /* bInterfaceCount */               \
+    USB_DEVICE_CLASS_CDC,                                  /* bFunctionClass */                \
+    CDC_ABSTRACT_CONTROL_MODEL,                            /* bFunctionSubClass */             \
+    CDC_COMMON_PROTOCOL_AT_COMMANDS,                       /* bFunctionProtocol */             \
+    0x00,                                                  /* iFunction */                     \
+    0x09,                                                  /* bLength */                       \
+    USB_DESCRIPTOR_TYPE_INTERFACE,                         /* bDescriptorType */               \
+    bFirstInterface,                                       /* bInterfaceNumber */              \
+    0x00,                                                  /* bAlternateSetting */             \
+    0x01,                                                  /* bNumEndpoints */                 \
+    USB_DEVICE_CLASS_CDC,                                  /* bInterfaceClass */               \
+    CDC_ABSTRACT_CONTROL_MODEL,                            /* bInterfaceSubClass */            \
+    CDC_COMMON_PROTOCOL_AT_COMMANDS,                       /* bInterfaceProtocol */            \
+    str_idx,                                               /* iInterface */                    \
+    0x05,                                                  /* bLength */                       \
+    CDC_CS_INTERFACE,                                      /* bDescriptorType */               \
+    CDC_FUNC_DESC_HEADER,                                  /* bDescriptorSubtype */            \
+    WBVAL(CDC_V1_10),                                      /* bcdCDC */                        \
+    0x05,                                                  /* bLength */                       \
+    CDC_CS_INTERFACE,                                      /* bDescriptorType */               \
+    CDC_FUNC_DESC_CALL_MANAGEMENT,                         /* bDescriptorSubtype */            \
+    bFirstInterface,                                       /* bmCapabilities */                \
+    (uint8_t)(bFirstInterface + 1),                        /* bDataInterface */                \
+    0x04,                                                  /* bLength */                       \
+    CDC_CS_INTERFACE,                                      /* bDescriptorType */               \
+    CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT,             /* bDescriptorSubtype */            \
+    0x02,                                                  /* bmCapabilities */                \
+    0x05,                                                  /* bLength */                       \
+    CDC_CS_INTERFACE,                                      /* bDescriptorType */               \
+    CDC_FUNC_DESC_UNION,                                   /* bDescriptorSubtype */            \
+    bFirstInterface,                                       /* bMasterInterface */              \
+    (uint8_t)(bFirstInterface + 1),                        /* bSlaveInterface0 */              \
+    0x07,                                                  /* bLength */                       \
+    USB_DESCRIPTOR_TYPE_ENDPOINT,                          /* bDescriptorType */               \
+    int_ep,                                                /* bEndpointAddress */              \
+    0x03,                                                  /* bmAttributes */                  \
+    0x40, 0x00,                                            /* wMaxPacketSize */                \
+    0x00,                                                  /* bInterval */                     \
+    0x09,                                                  /* bLength */                       \
+    USB_DESCRIPTOR_TYPE_INTERFACE,                         /* bDescriptorType */               \
+    (uint8_t)(bFirstInterface + 1),                        /* bInterfaceNumber */              \
+    0x00,                                                  /* bAlternateSetting */             \
+    0x02,                                                  /* bNumEndpoints */                 \
+    CDC_DATA_INTERFACE_CLASS,                              /* bInterfaceClass */               \
+    0x00,                                                  /* bInterfaceSubClass */            \
+    0x00,                                                  /* bInterfaceProtocol */            \
+    0x00,                                                  /* iInterface */                    \
+    0x07,                                                  /* bLength */                       \
+    USB_DESCRIPTOR_TYPE_ENDPOINT,                          /* bDescriptorType */               \
+    out_ep,                                                /* bEndpointAddress */              \
+    0x02,                                                  /* bmAttributes */                  \
+    0x40, 0x00,                                            /* wMaxPacketSize */                \
+    0x00,                                                  /* bInterval */                     \
+    0x07,                                                  /* bLength */                       \
+    USB_DESCRIPTOR_TYPE_ENDPOINT,                          /* bDescriptorType */               \
+    in_ep,                                                 /* bEndpointAddress */              \
+    0x02,                                                  /* bmAttributes */                  \
+    0x40, 0x00,                                            /* wMaxPacketSize */                \
+    0x00                                                   /* bInterval */
+#else
+#define CDC_ACM_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, str_idx)               \
+    /* Interface Associate */                                                                  \
+    0x08,                                                  /* bLength */                       \
+    USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION,             /* bDescriptorType */               \
+    bFirstInterface,                                       /* bFirstInterface */               \
+    0x02,                                                  /* bInterfaceCount */               \
+    USB_DEVICE_CLASS_CDC,                                  /* bFunctionClass */                \
+    CDC_ABSTRACT_CONTROL_MODEL,                            /* bFunctionSubClass */             \
+    CDC_COMMON_PROTOCOL_AT_COMMANDS,                       /* bFunctionProtocol */             \
+    0x00,                                                  /* iFunction */                     \
+    0x09,                                                  /* bLength */                       \
+    USB_DESCRIPTOR_TYPE_INTERFACE,                         /* bDescriptorType */               \
+    bFirstInterface,                                       /* bInterfaceNumber */              \
+    0x00,                                                  /* bAlternateSetting */             \
+    0x01,                                                  /* bNumEndpoints */                 \
+    USB_DEVICE_CLASS_CDC,                                  /* bInterfaceClass */               \
+    CDC_ABSTRACT_CONTROL_MODEL,                            /* bInterfaceSubClass */            \
+    CDC_COMMON_PROTOCOL_AT_COMMANDS,                       /* bInterfaceProtocol */            \
+    str_idx,                                               /* iInterface */                    \
+    0x05,                                                  /* bLength */                       \
+    CDC_CS_INTERFACE,                                      /* bDescriptorType */               \
+    CDC_FUNC_DESC_HEADER,                                  /* bDescriptorSubtype */            \
+    WBVAL(CDC_V1_10),                                      /* bcdCDC */                        \
+    0x05,                                                  /* bLength */                       \
+    CDC_CS_INTERFACE,                                      /* bDescriptorType */               \
+    CDC_FUNC_DESC_CALL_MANAGEMENT,                         /* bDescriptorSubtype */            \
+    bFirstInterface,                                       /* bmCapabilities */                \
+    (uint8_t)(bFirstInterface + 1),                        /* bDataInterface */                \
+    0x04,                                                  /* bLength */                       \
+    CDC_CS_INTERFACE,                                      /* bDescriptorType */               \
+    CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT,             /* bDescriptorSubtype */            \
+    0x02,                                                  /* bmCapabilities */                \
+    0x05,                                                  /* bLength */                       \
+    CDC_CS_INTERFACE,                                      /* bDescriptorType */               \
+    CDC_FUNC_DESC_UNION,                                   /* bDescriptorSubtype */            \
+    bFirstInterface,                                       /* bMasterInterface */              \
+    (uint8_t)(bFirstInterface + 1),                        /* bSlaveInterface0 */              \
+    0x07,                                                  /* bLength */                       \
+    USB_DESCRIPTOR_TYPE_ENDPOINT,                          /* bDescriptorType */               \
+    int_ep,                                                /* bEndpointAddress */              \
+    0x03,                                                  /* bmAttributes */                  \
+    0x00, 0x02,                                            /* wMaxPacketSize */                \
+    0x00,                                                  /* bInterval */                     \
+    0x09,                                                  /* bLength */                       \
+    USB_DESCRIPTOR_TYPE_INTERFACE,                         /* bDescriptorType */               \
+    (uint8_t)(bFirstInterface + 1),                        /* bInterfaceNumber */              \
+    0x00,                                                  /* bAlternateSetting */             \
+    0x02,                                                  /* bNumEndpoints */                 \
+    CDC_DATA_INTERFACE_CLASS,                              /* bInterfaceClass */               \
+    0x00,                                                  /* bInterfaceSubClass */            \
+    0x00,                                                  /* bInterfaceProtocol */            \
+    0x00,                                                  /* iInterface */                    \
+    0x07,                                                  /* bLength */                       \
+    USB_DESCRIPTOR_TYPE_ENDPOINT,                          /* bDescriptorType */               \
+    out_ep,                                                /* bEndpointAddress */              \
+    0x02,                                                  /* bmAttributes */                  \
+    0x00, 0x02,                                            /* wMaxPacketSize */                \
+    0x00,                                                  /* bInterval */                     \
+    0x07,                                                  /* bLength */                       \
+    USB_DESCRIPTOR_TYPE_ENDPOINT,                          /* bDescriptorType */               \
+    in_ep,                                                 /* bEndpointAddress */              \
+    0x02,                                                  /* bmAttributes */                  \
+    0x00, 0x02,                                            /* wMaxPacketSize */                \
+    0x00                                                   /* bInterval */
+#endif
+// clang-format on
+
+void usbd_cdc_add_acm_interface(usbd_class_t *class, usbd_interface_t *intf);
+
+void usbd_cdc_acm_set_line_coding(uint32_t baudrate, uint8_t databits, uint8_t parity, uint8_t stopbits);
+void usbd_cdc_acm_set_dtr(bool dtr);
+void usbd_cdc_acm_set_rts(bool rts);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USB_CDC_H_ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/hid/usbd_hid.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/hid/usbd_hid.c
new file mode 100644
index 00000000..5e66d18b
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/hid/usbd_hid.c
@@ -0,0 +1,286 @@
+/**
+ * @file usbd_hid.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "usbd_core.h"
+#include "usbd_hid.h"
+
+#define HID_STATE_IDLE 0
+#define HID_STATE_BUSY 1
+
+struct usbd_hid_cfg_private {
+    const uint8_t *hid_descriptor;
+    const uint8_t *hid_report_descriptor;
+    uint32_t hid_report_descriptor_len;
+    uint8_t current_intf_num;
+    uint8_t hid_state;
+    uint8_t report;
+    uint8_t idle_state;
+    uint8_t protocol;
+
+    uint8_t (*get_report_callback)(uint8_t report_id, uint8_t report_type);
+    void (*set_report_callback)(uint8_t report_id, uint8_t report_type, uint8_t *report, uint8_t report_len);
+    uint8_t (*get_idle_callback)(uint8_t report_id);
+    void (*set_idle_callback)(uint8_t report_id, uint8_t duration);
+    void (*set_protocol_callback)(uint8_t protocol);
+    uint8_t (*get_protocol_callback)(void);
+
+    usb_slist_t list;
+} usbd_hid_cfg[4];
+
+static usb_slist_t usbd_hid_class_head = USB_SLIST_OBJECT_INIT(usbd_hid_class_head);
+
+static void usbd_hid_reset(void)
+{
+    usb_slist_t *i;
+    usb_slist_for_each(i, &usbd_hid_class_head)
+    {
+        struct usbd_hid_cfg_private *hid_intf = usb_slist_entry(i, struct usbd_hid_cfg_private, list);
+        hid_intf->hid_state = HID_STATE_IDLE;
+        hid_intf->report = 0;
+        hid_intf->idle_state = 0;
+        hid_intf->protocol = 0;
+    }
+}
+
+int hid_custom_request_handler(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len)
+{
+    USBD_LOG_DBG("HID Custom request: "
+                 "bRequest 0x%02x\r\n",
+                 setup->bRequest);
+
+    if (REQTYPE_GET_DIR(setup->bmRequestType) == USB_REQUEST_DEVICE_TO_HOST &&
+        setup->bRequest == USB_REQUEST_GET_DESCRIPTOR) {
+        uint8_t value = (uint8_t)(setup->wValue >> 8);
+        uint8_t intf_num = (uint8_t)setup->wIndex;
+
+        struct usbd_hid_cfg_private *current_hid_intf = NULL;
+        usb_slist_t *i;
+        usb_slist_for_each(i, &usbd_hid_class_head)
+        {
+            struct usbd_hid_cfg_private *hid_intf = usb_slist_entry(i, struct usbd_hid_cfg_private, list);
+
+            if (hid_intf->current_intf_num == intf_num) {
+                current_hid_intf = hid_intf;
+                break;
+            }
+        }
+
+        if (current_hid_intf == NULL) {
+            return -2;
+        }
+
+        switch (value) {
+            case HID_DESCRIPTOR_TYPE_HID:
+                USBD_LOG_INFO("get HID Descriptor\r\n");
+                *data = (uint8_t *)current_hid_intf->hid_descriptor;
+                *len = current_hid_intf->hid_descriptor[0];
+                break;
+
+            case HID_DESCRIPTOR_TYPE_HID_REPORT:
+                USBD_LOG_INFO("get Report Descriptor\r\n");
+                *data = (uint8_t *)current_hid_intf->hid_report_descriptor;
+                *len = current_hid_intf->hid_report_descriptor_len;
+                break;
+
+            case HID_DESCRIPTOR_TYPE_HID_PHYSICAL:
+                USBD_LOG_INFO("get PHYSICAL Descriptor\r\n");
+
+                break;
+
+            default:
+                return -2;
+        }
+
+        return 0;
+    }
+
+    return -1;
+}
+
+int hid_class_request_handler(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len)
+{
+    USBD_LOG_DBG("HID Class request: "
+                 "bRequest 0x%02x\r\n",
+                 setup->bRequest);
+
+    struct usbd_hid_cfg_private *current_hid_intf = NULL;
+    usb_slist_t *i;
+    usb_slist_for_each(i, &usbd_hid_class_head)
+    {
+        struct usbd_hid_cfg_private *hid_intf = usb_slist_entry(i, struct usbd_hid_cfg_private, list);
+        uint8_t intf_num = (uint8_t)setup->wIndex;
+        if (hid_intf->current_intf_num == intf_num) {
+            current_hid_intf = hid_intf;
+            break;
+        }
+    }
+
+    if (current_hid_intf == NULL) {
+        return -2;
+    }
+
+    switch (setup->bRequest) {
+        case HID_REQUEST_GET_REPORT:
+            if (current_hid_intf->get_report_callback)
+                current_hid_intf->report = current_hid_intf->get_report_callback(setup->wValueL, setup->wValueH); /*report id ,report type*/
+
+            *data = (uint8_t *)¤t_hid_intf->report;
+            *len = 1;
+            break;
+        case HID_REQUEST_GET_IDLE:
+            if (current_hid_intf->get_idle_callback)
+                current_hid_intf->idle_state = current_hid_intf->get_idle_callback(setup->wValueL);
+
+            *data = (uint8_t *)¤t_hid_intf->idle_state;
+            *len = 1;
+            break;
+        case HID_REQUEST_GET_PROTOCOL:
+            if (current_hid_intf->get_protocol_callback)
+                current_hid_intf->protocol = current_hid_intf->get_protocol_callback();
+
+            *data = (uint8_t *)¤t_hid_intf->protocol;
+            *len = 1;
+            break;
+        case HID_REQUEST_SET_REPORT:
+            if (current_hid_intf->set_report_callback)
+                current_hid_intf->set_report_callback(setup->wValueL, setup->wValueH, *data, *len); /*report id ,report type,report,report len*/
+
+            current_hid_intf->report = **data;
+            break;
+        case HID_REQUEST_SET_IDLE:
+            if (current_hid_intf->set_idle_callback)
+                current_hid_intf->set_idle_callback(setup->wValueL, setup->wIndexH); /*report id ,duration*/
+
+            current_hid_intf->idle_state = setup->wIndexH;
+            break;
+        case HID_REQUEST_SET_PROTOCOL:
+            if (current_hid_intf->set_protocol_callback)
+                current_hid_intf->set_protocol_callback(setup->wValueL); /*protocol*/
+
+            current_hid_intf->protocol = setup->wValueL;
+            break;
+
+        default:
+            USBD_LOG_WRN("Unhandled HID Class bRequest 0x%02x\r\n", setup->bRequest);
+            return -1;
+    }
+
+    return 0;
+}
+
+static void hid_notify_handler(uint8_t event, void *arg)
+{
+    switch (event) {
+        case USB_EVENT_RESET:
+            usbd_hid_reset();
+            break;
+
+        default:
+            break;
+    }
+}
+
+void usbd_hid_reset_state(void)
+{
+    // usbd_hid_cfg.hid_state = HID_STATE_IDLE;
+}
+
+void usbd_hid_send_report(uint8_t ep, uint8_t *data, uint8_t len)
+{
+    // if(usbd_hid_cfg.hid_state == HID_STATE_IDLE)
+    // {
+    //     usbd_hid_cfg.hid_state = HID_STATE_BUSY;
+    //     usbd_ep_write(ep, data, len, NULL);
+    // }
+}
+
+void usbd_hid_descriptor_register(uint8_t intf_num, const uint8_t *desc)
+{
+    // usbd_hid_cfg.hid_descriptor = desc;
+}
+
+void usbd_hid_report_descriptor_register(uint8_t intf_num, const uint8_t *desc, uint32_t desc_len)
+{
+    usb_slist_t *i;
+    usb_slist_for_each(i, &usbd_hid_class_head)
+    {
+        struct usbd_hid_cfg_private *hid_intf = usb_slist_entry(i, struct usbd_hid_cfg_private, list);
+
+        if (hid_intf->current_intf_num == intf_num) {
+            hid_intf->hid_report_descriptor = desc;
+            hid_intf->hid_report_descriptor_len = desc_len;
+            return;
+        }
+    }
+}
+// clang-format off
+void usbd_hid_set_request_callback( uint8_t intf_num,
+                                    uint8_t (*get_report_callback)(uint8_t report_id, uint8_t report_type),
+                                    void (*set_report_callback)(uint8_t report_id, uint8_t report_type, uint8_t *report, uint8_t report_len),
+                                    uint8_t (*get_idle_callback)(uint8_t report_id),
+                                    void (*set_idle_callback)(uint8_t report_id, uint8_t duration),
+                                    void (*set_protocol_callback)(uint8_t protocol),
+                                    uint8_t (*get_protocol_callback)(void))
+// clang-format on
+{
+    usb_slist_t *i;
+    usb_slist_for_each(i, &usbd_hid_class_head)
+    {
+        struct usbd_hid_cfg_private *hid_intf = usb_slist_entry(i, struct usbd_hid_cfg_private, list);
+
+        if (hid_intf->current_intf_num == intf_num) {
+            if (get_report_callback)
+                hid_intf->get_report_callback = get_report_callback;
+            if (set_report_callback)
+                hid_intf->set_report_callback = set_report_callback;
+            if (get_idle_callback)
+                hid_intf->get_idle_callback = get_idle_callback;
+            if (set_idle_callback)
+                hid_intf->set_idle_callback = set_idle_callback;
+            if (set_protocol_callback)
+                hid_intf->set_protocol_callback = set_protocol_callback;
+            if (get_protocol_callback)
+                hid_intf->get_protocol_callback = get_protocol_callback;
+            return;
+        }
+    }
+}
+
+void usbd_hid_add_interface(usbd_class_t *class, usbd_interface_t *intf)
+{
+    static usbd_class_t *last_class = NULL;
+    static uint8_t hid_num = 0;
+    if (last_class != class) {
+        last_class = class;
+        usbd_class_register(class);
+    }
+
+    intf->class_handler = hid_class_request_handler;
+    intf->custom_handler = hid_custom_request_handler;
+    intf->vendor_handler = NULL;
+    intf->notify_handler = hid_notify_handler;
+    usbd_class_add_interface(class, intf);
+
+    usbd_hid_cfg[hid_num].current_intf_num = intf->intf_num;
+    usb_slist_add_tail(&usbd_hid_class_head, &usbd_hid_cfg[hid_num].list);
+    hid_num++;
+}
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/hid/usbd_hid.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/hid/usbd_hid.h
new file mode 100644
index 00000000..9319e7f2
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/hid/usbd_hid.h
@@ -0,0 +1,360 @@
+/**
+ * @file
+ * @brief USB Human Interface Device (HID) Class public header
+ *
+ * Header follows Device Class Definition for Human Interface Devices (HID)
+ * Version 1.11 document (HID1_11-1.pdf).
+ */
+#ifndef _USBD_HID_H_
+#define _USBD_HID_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* HID Protocol Codes */
+#define HID_PROTOCOL_NONE     0x00
+#define HID_PROTOCOL_BOOT     0x00
+#define HID_PROTOCOL_KEYBOARD 0x01
+#define HID_PROTOCOL_REPORT   0x01
+#define HID_PROTOCOL_MOUSE    0x02
+
+/* HID Class Descriptor Types */
+#define HID_DESCRIPTOR_TYPE_HID          0x21
+#define HID_DESCRIPTOR_TYPE_HID_REPORT   0x22
+#define HID_DESCRIPTOR_TYPE_HID_PHYSICAL 0x23
+
+/* HID Class Specific Requests */
+#define HID_REQUEST_GET_REPORT   0x01
+#define HID_REQUEST_GET_IDLE     0x02
+#define HID_REQUEST_GET_PROTOCOL 0x03
+#define HID_REQUEST_SET_REPORT   0x09
+#define HID_REQUEST_SET_IDLE     0x0A
+#define HID_REQUEST_SET_PROTOCOL 0x0B
+
+/* HID Report Types */
+#define HID_REPORT_INPUT   0x01
+#define HID_REPORT_OUTPUT  0x02
+#define HID_REPORT_FEATURE 0x03
+
+/* HID Report Definitions */
+struct usb_hid_class_subdescriptor {
+    uint8_t bDescriptorType;
+    uint16_t wDescriptorLength;
+} __packed;
+
+struct usb_hid_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint16_t bcdHID;
+    uint8_t bCountryCode;
+    uint8_t bNumDescriptors;
+
+    /*
+     * Specification says at least one Class Descriptor needs to
+     * be present (Report Descriptor).
+     */
+    struct usb_hid_class_subdescriptor subdesc[1];
+} __packed;
+
+/* HID Items types */
+#define ITEM_MAIN   0x0
+#define ITEM_GLOBAL 0x1
+#define ITEM_LOCAL  0x2
+
+/* HID Main Items tags */
+#define ITEM_TAG_INPUT          0x8
+#define ITEM_TAG_OUTPUT         0x9
+#define ITEM_TAG_COLLECTION     0xA
+#define ITEM_TAG_COLLECTION_END 0xC
+
+/* HID Global Items tags */
+#define ITEM_TAG_USAGE_PAGE   0x0
+#define ITEM_TAG_LOGICAL_MIN  0x1
+#define ITEM_TAG_LOGICAL_MAX  0x2
+#define ITEM_TAG_REPORT_SIZE  0x7
+#define ITEM_TAG_REPORT_ID    0x8
+#define ITEM_TAG_REPORT_COUNT 0x9
+
+/* HID Local Items tags */
+#define ITEM_TAG_USAGE     0x0
+#define ITEM_TAG_USAGE_MIN 0x1
+#define ITEM_TAG_USAGE_MAX 0x2
+
+#define HID_ITEM(bTag, bType, bSize) (((bTag & 0xF) << 4) | \
+                                      ((bType & 0x3) << 2) | (bSize & 0x3))
+
+#define HID_MAIN_ITEM(bTag, bSize)   HID_ITEM(bTag, ITEM_MAIN, bSize)
+#define HID_GLOBAL_ITEM(bTag, bSize) HID_ITEM(bTag, ITEM_GLOBAL, bSize)
+#define HID_LOCAL_ITEM(bTag, bSize)  HID_ITEM(bTag, ITEM_LOCAL, bSize)
+
+#define HID_MI_COLLECTION     HID_MAIN_ITEM(ITEM_TAG_COLLECTION, 1)
+#define HID_MI_COLLECTION_END HID_MAIN_ITEM(ITEM_TAG_COLLECTION_END, \
+                                            0)
+#define HID_MI_INPUT  HID_MAIN_ITEM(ITEM_TAG_INPUT, 1)
+#define HID_MI_OUTPUT HID_MAIN_ITEM(ITEM_TAG_OUTPUT, 1)
+
+#define HID_GI_USAGE_PAGE        HID_GLOBAL_ITEM(ITEM_TAG_USAGE_PAGE, 1)
+#define HID_GI_LOGICAL_MIN(size) HID_GLOBAL_ITEM(ITEM_TAG_LOGICAL_MIN, \
+                                                 size)
+#define HID_GI_LOGICAL_MAX(size) HID_GLOBAL_ITEM(ITEM_TAG_LOGICAL_MAX, \
+                                                 size)
+#define HID_GI_REPORT_SIZE HID_GLOBAL_ITEM(ITEM_TAG_REPORT_SIZE, \
+                                           1)
+#define HID_GI_REPORT_ID HID_GLOBAL_ITEM(ITEM_TAG_REPORT_ID, \
+                                         1)
+#define HID_GI_REPORT_COUNT HID_GLOBAL_ITEM(ITEM_TAG_REPORT_COUNT, \
+                                            1)
+
+#define HID_LI_USAGE           HID_LOCAL_ITEM(ITEM_TAG_USAGE, 1)
+#define HID_LI_USAGE_MIN(size) HID_LOCAL_ITEM(ITEM_TAG_USAGE_MIN, \
+                                              size)
+#define HID_LI_USAGE_MAX(size) HID_LOCAL_ITEM(ITEM_TAG_USAGE_MAX, \
+                                              size)
+
+/* Defined in Universal Serial Bus HID Usage Tables version 1.11 */
+#define USAGE_GEN_DESKTOP  0x01
+#define USAGE_GEN_KEYBOARD 0x07
+#define USAGE_GEN_LEDS     0x08
+#define USAGE_GEN_BUTTON   0x09
+
+/* Generic Desktop Page usages */
+#define USAGE_GEN_DESKTOP_UNDEFINED 0x00
+#define USAGE_GEN_DESKTOP_POINTER   0x01
+#define USAGE_GEN_DESKTOP_MOUSE     0x02
+#define USAGE_GEN_DESKTOP_JOYSTICK  0x04
+#define USAGE_GEN_DESKTOP_GAMEPAD   0x05
+#define USAGE_GEN_DESKTOP_KEYBOARD  0x06
+#define USAGE_GEN_DESKTOP_KEYPAD    0x07
+#define USAGE_GEN_DESKTOP_X         0x30
+#define USAGE_GEN_DESKTOP_Y         0x31
+#define USAGE_GEN_DESKTOP_WHEEL     0x38
+
+/* Collection types */
+#define COLLECTION_PHYSICAL    0x00
+#define COLLECTION_APPLICATION 0x01
+
+/* Example HID report descriptors */
+/**
+ * @brief Simple HID mouse report descriptor for n button mouse.
+ *
+ * @param bcnt  Button count. Allowed values from 1 to 8.
+ */
+#define HID_MOUSE_REPORT_DESC(bcnt)                                                                                          \
+    {                                                                                                                        \
+        /* USAGE_PAGE (Generic Desktop) */                                                                                   \
+        HID_GI_USAGE_PAGE, USAGE_GEN_DESKTOP,                                             /* USAGE (Mouse) */                \
+            HID_LI_USAGE, USAGE_GEN_DESKTOP_MOUSE,                                        /* COLLECTION (Application) */     \
+            HID_MI_COLLECTION, COLLECTION_APPLICATION,                                    /* USAGE (Pointer) */              \
+            HID_LI_USAGE, USAGE_GEN_DESKTOP_POINTER,                                      /* COLLECTION (Physical) */        \
+            HID_MI_COLLECTION, COLLECTION_PHYSICAL, /* Bits used for button signalling */ /* USAGE_PAGE (Button) */          \
+            HID_GI_USAGE_PAGE, USAGE_GEN_BUTTON,                                          /* USAGE_MINIMUM (Button 1) */     \
+            HID_LI_USAGE_MIN(1), 0x01,                                                    /* USAGE_MAXIMUM (Button bcnt) */  \
+            HID_LI_USAGE_MAX(1), bcnt,                                                    /* LOGICAL_MINIMUM (0) */          \
+            HID_GI_LOGICAL_MIN(1), 0x00,                                                  /* LOGICAL_MAXIMUM (1) */          \
+            HID_GI_LOGICAL_MAX(1), 0x01,                                                  /* REPORT_SIZE (1) */              \
+            HID_GI_REPORT_SIZE, 0x01,                                                     /* REPORT_COUNT (bcnt) */          \
+            HID_GI_REPORT_COUNT, bcnt,                                                    /* INPUT (Data,Var,Abs) */         \
+            HID_MI_INPUT, 0x02, /* Unused bits */                                         /* REPORT_SIZE (8 - bcnt) */       \
+            HID_GI_REPORT_SIZE, (8 - bcnt),                                               /* REPORT_COUNT (1) */             \
+            HID_GI_REPORT_COUNT, 0x01,                                                    /* INPUT (Cnst,Ary,Abs) */         \
+            HID_MI_INPUT, 0x01, /* X and Y axis, scroll */                                /* USAGE_PAGE (Generic Desktop) */ \
+            HID_GI_USAGE_PAGE, USAGE_GEN_DESKTOP,                                         /* USAGE (X) */                    \
+            HID_LI_USAGE, USAGE_GEN_DESKTOP_X,                                            /* USAGE (Y) */                    \
+            HID_LI_USAGE, USAGE_GEN_DESKTOP_Y,                                            /* USAGE (WHEEL) */                \
+            HID_LI_USAGE, USAGE_GEN_DESKTOP_WHEEL,                                        /* LOGICAL_MINIMUM (-127) */       \
+            HID_GI_LOGICAL_MIN(1), -127,                                                  /* LOGICAL_MAXIMUM (127) */        \
+            HID_GI_LOGICAL_MAX(1), 127,                                                   /* REPORT_SIZE (8) */              \
+            HID_GI_REPORT_SIZE, 0x08,                                                     /* REPORT_COUNT (3) */             \
+            HID_GI_REPORT_COUNT, 0x03,                                                    /* INPUT (Data,Var,Rel) */         \
+            HID_MI_INPUT, 0x06,                                                           /* END_COLLECTION */               \
+            HID_MI_COLLECTION_END,                                                        /* END_COLLECTION */               \
+            HID_MI_COLLECTION_END,                                                                                           \
+    }
+
+/**
+ * @brief Simple HID keyboard report descriptor.
+ */
+#define HID_KEYBOARD_REPORT_DESC()                                                                  \
+    {                                                                                               \
+        /* USAGE_PAGE (Generic Desktop) */                                                          \
+        HID_GI_USAGE_PAGE, USAGE_GEN_DESKTOP,            /* USAGE (Keyboard) */                     \
+            HID_LI_USAGE, USAGE_GEN_DESKTOP_KEYBOARD,    /* COLLECTION (Application) */             \
+            HID_MI_COLLECTION, COLLECTION_APPLICATION,   /* USAGE_PAGE (Keypad) */                  \
+            HID_GI_USAGE_PAGE, USAGE_GEN_DESKTOP_KEYPAD, /* USAGE_MINIMUM (Keyboard LeftControl) */ \
+            HID_LI_USAGE_MIN(1), 0xE0,                   /* USAGE_MAXIMUM (Keyboard Right GUI) */   \
+            HID_LI_USAGE_MAX(1), 0xE7,                   /* LOGICAL_MINIMUM (0) */                  \
+            HID_GI_LOGICAL_MIN(1), 0x00,                 /* LOGICAL_MAXIMUM (1) */                  \
+            HID_GI_LOGICAL_MAX(1), 0x01,                 /* REPORT_SIZE (1) */                      \
+            HID_GI_REPORT_SIZE, 0x01,                    /* REPORT_COUNT (8) */                     \
+            HID_GI_REPORT_COUNT, 0x08,                   /* INPUT (Data,Var,Abs) */                 \
+            HID_MI_INPUT, 0x02,                          /* REPORT_SIZE (8) */                      \
+            HID_GI_REPORT_SIZE, 0x08,                    /* REPORT_COUNT (1) */                     \
+            HID_GI_REPORT_COUNT, 0x01,                   /* INPUT (Cnst,Var,Abs) */                 \
+            HID_MI_INPUT, 0x03,                          /* REPORT_SIZE (1) */                      \
+            HID_GI_REPORT_SIZE, 0x01,                    /* REPORT_COUNT (5) */                     \
+            HID_GI_REPORT_COUNT, 0x05,                   /* USAGE_PAGE (LEDs) */                    \
+            HID_GI_USAGE_PAGE, USAGE_GEN_LEDS,           /* USAGE_MINIMUM (Num Lock) */             \
+            HID_LI_USAGE_MIN(1), 0x01,                   /* USAGE_MAXIMUM (Kana) */                 \
+            HID_LI_USAGE_MAX(1), 0x05,                   /* OUTPUT (Data,Var,Abs) */                \
+            HID_MI_OUTPUT, 0x02,                         /* REPORT_SIZE (3) */                      \
+            HID_GI_REPORT_SIZE, 0x03,                    /* REPORT_COUNT (1) */                     \
+            HID_GI_REPORT_COUNT, 0x01,                   /* OUTPUT (Cnst,Var,Abs) */                \
+            HID_MI_OUTPUT, 0x03,                         /* REPORT_SIZE (8) */                      \
+            HID_GI_REPORT_SIZE, 0x08,                    /* REPORT_COUNT (6) */                     \
+            HID_GI_REPORT_COUNT, 0x06,                   /* LOGICAL_MINIMUM (0) */                  \
+            HID_GI_LOGICAL_MIN(1), 0x00,                 /* LOGICAL_MAXIMUM (101) */                \
+            HID_GI_LOGICAL_MAX(1), 0x65,                 /* USAGE_PAGE (Keypad) */                  \
+            HID_GI_USAGE_PAGE, USAGE_GEN_DESKTOP_KEYPAD, /* USAGE_MINIMUM (Reserved) */             \
+            HID_LI_USAGE_MIN(1), 0x00,                   /* USAGE_MAXIMUM (Keyboard Application) */ \
+            HID_LI_USAGE_MAX(1), 0x65,                   /* INPUT (Data,Ary,Abs) */                 \
+            HID_MI_INPUT, 0x00,                          /* END_COLLECTION */                       \
+            HID_MI_COLLECTION_END,                                                                  \
+    }
+
+/**
+ * @brief HID keyboard button codes.
+ */
+enum hid_kbd_code {
+    HID_KEY_A = 4,
+    HID_KEY_B = 5,
+    HID_KEY_C = 6,
+    HID_KEY_D = 7,
+    HID_KEY_E = 8,
+    HID_KEY_F = 9,
+    HID_KEY_G = 10,
+    HID_KEY_H = 11,
+    HID_KEY_I = 12,
+    HID_KEY_J = 13,
+    HID_KEY_K = 14,
+    HID_KEY_L = 15,
+    HID_KEY_M = 16,
+    HID_KEY_N = 17,
+    HID_KEY_O = 18,
+    HID_KEY_P = 19,
+    HID_KEY_Q = 20,
+    HID_KEY_R = 21,
+    HID_KEY_S = 22,
+    HID_KEY_T = 23,
+    HID_KEY_U = 24,
+    HID_KEY_V = 25,
+    HID_KEY_W = 26,
+    HID_KEY_X = 27,
+    HID_KEY_Y = 28,
+    HID_KEY_Z = 29,
+    HID_KEY_1 = 30,
+    HID_KEY_2 = 31,
+    HID_KEY_3 = 32,
+    HID_KEY_4 = 33,
+    HID_KEY_5 = 34,
+    HID_KEY_6 = 35,
+    HID_KEY_7 = 36,
+    HID_KEY_8 = 37,
+    HID_KEY_9 = 38,
+    HID_KEY_0 = 39,
+    HID_KEY_ENTER = 40,
+    HID_KEY_ESC = 41,
+    HID_KEY_BACKSPACE = 42,
+    HID_KEY_TAB = 43,
+    HID_KEY_SPACE = 44,
+    HID_KEY_MINUS = 45,
+    HID_KEY_EQUAL = 46,
+    HID_KEY_LEFTBRACE = 47,
+    HID_KEY_RIGHTBRACE = 48,
+    HID_KEY_BACKSLASH = 49,
+    HID_KEY_HASH = 50, /* Non-US # and ~ */
+    HID_KEY_SEMICOLON = 51,
+    HID_KEY_APOSTROPHE = 52,
+    HID_KEY_GRAVE = 53,
+    HID_KEY_COMMA = 54,
+    HID_KEY_DOT = 55,
+    HID_KEY_SLASH = 56,
+    HID_KEY_CAPSLOCK = 57,
+    HID_KEY_F1 = 58,
+    HID_KEY_F2 = 59,
+    HID_KEY_F3 = 60,
+    HID_KEY_F4 = 61,
+    HID_KEY_F5 = 62,
+    HID_KEY_F6 = 63,
+    HID_KEY_F7 = 64,
+    HID_KEY_F8 = 65,
+    HID_KEY_F9 = 66,
+    HID_KEY_F10 = 67,
+    HID_KEY_F11 = 68,
+    HID_KEY_F12 = 69,
+    HID_KEY_SYSRQ = 70, /* PRINTSCREEN */
+    HID_KEY_SCROLLLOCK = 71,
+    HID_KEY_PAUSE = 72,
+    HID_KEY_INSERT = 73,
+    HID_KEY_HOME = 74,
+    HID_KEY_PAGEUP = 75,
+    HID_KEY_DELETE = 76,
+    HID_KEY_END = 77,
+    HID_KEY_PAGEDOWN = 78,
+    HID_KEY_RIGHT = 79,
+    HID_KEY_LEFT = 80,
+    HID_KEY_DOWN = 81,
+    HID_KEY_UP = 82,
+    HID_KEY_NUMLOCK = 83,
+    HID_KEY_KPSLASH = 84,    /* NUMPAD DIVIDE */
+    HID_KEY_KPASTERISK = 85, /* NUMPAD MULTIPLY */
+    HID_KEY_KPMINUS = 86,
+    HID_KEY_KPPLUS = 87,
+    HID_KEY_KPENTER = 88,
+    HID_KEY_KP_1 = 89,
+    HID_KEY_KP_2 = 90,
+    HID_KEY_KP_3 = 91,
+    HID_KEY_KP_4 = 92,
+    HID_KEY_KP_5 = 93,
+    HID_KEY_KP_6 = 94,
+    HID_KEY_KP_7 = 95,
+    HID_KEY_KP_8 = 96,
+    HID_KEY_KP_9 = 97,
+    HID_KEY_KP_0 = 98,
+};
+
+/**
+ * @brief HID keyboard modifiers.
+ */
+enum hid_kbd_modifier {
+    HID_KBD_MODIFIER_NONE = 0x00,
+    HID_KBD_MODIFIER_LEFT_CTRL = 0x01,
+    HID_KBD_MODIFIER_LEFT_SHIFT = 0x02,
+    HID_KBD_MODIFIER_LEFT_ALT = 0x04,
+    HID_KBD_MODIFIER_LEFT_UI = 0x08,
+    HID_KBD_MODIFIER_RIGHT_CTRL = 0x10,
+    HID_KBD_MODIFIER_RIGHT_SHIFT = 0x20,
+    HID_KBD_MODIFIER_RIGHT_ALT = 0x40,
+    HID_KBD_MODIFIER_RIGHT_UI = 0x80,
+};
+
+/**
+ * @brief HID keyboard LEDs.
+ */
+enum hid_kbd_led {
+    HID_KBD_LED_NUM_LOCK = 0x01,
+    HID_KBD_LED_CAPS_LOCK = 0x02,
+    HID_KBD_LED_SCROLL_LOCK = 0x04,
+    HID_KBD_LED_COMPOSE = 0x08,
+    HID_KBD_LED_KANA = 0x10,
+};
+
+void usbd_hid_descriptor_register(uint8_t intf_num, const uint8_t *desc);
+void usbd_hid_report_descriptor_register(uint8_t intf_num, const uint8_t *desc, uint32_t desc_len);
+void usbd_hid_add_interface(usbd_class_t *class, usbd_interface_t *intf);
+void usbd_hid_reset_state(void);
+void usbd_hid_send_report(uint8_t ep, uint8_t *data, uint8_t len);
+// clang-format off
+void usbd_hid_set_request_callback( uint8_t intf_num,
+                                    uint8_t (*get_report_callback)(uint8_t report_id, uint8_t report_type),
+                                    void (*set_report_callback)(uint8_t report_id, uint8_t report_type, uint8_t *report, uint8_t report_len),
+                                    uint8_t (*get_idle_callback)(uint8_t report_id),
+                                    void (*set_idle_callback)(uint8_t report_id, uint8_t duration),
+                                    void (*set_protocol_callback)(uint8_t protocol),
+                                    uint8_t (*get_protocol_callback)(void));
+// clang-format on
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _USB_HID_H_ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/msc/usbd_msc.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/msc/usbd_msc.c
new file mode 100644
index 00000000..262adbb1
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/msc/usbd_msc.c
@@ -0,0 +1,1004 @@
+/**
+ * @file usbd_msc.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "usbd_core.h"
+#include "usbd_scsi.h"
+#include "usbd_msc.h"
+
+/* max USB packet size */
+#ifndef CONFIG_USB_HS
+#define MASS_STORAGE_BULK_EP_MPS 64
+#else
+#define MASS_STORAGE_BULK_EP_MPS 512
+#endif
+
+#define MSD_OUT_EP_IDX 0
+#define MSD_IN_EP_IDX  1
+
+/* Describe EndPoints configuration */
+static usbd_endpoint_t mass_ep_data[2];
+
+/* MSC Bulk-only Stage */
+enum Stage {
+    MSC_READ_CBW = 0, /* Command Block Wrapper */
+    MSC_DATA_OUT = 1, /* Data Out Phase */
+    MSC_DATA_IN = 2,  /* Data In Phase */
+    MSC_SEND_CSW = 3, /* Command Status Wrapper */
+    MSC_WAIT_CSW = 4, /* Command Status Wrapper */
+};
+
+/** MSC Bulk-Only Command Block Wrapper (CBW) */
+struct CBW {
+    uint32_t dSignature;
+    uint32_t dTag;
+    uint32_t dDataLength;
+    uint8_t bmFlags;
+    uint8_t bLUN;
+    uint8_t bCBLength;
+    uint8_t CB[16];
+} __packed;
+
+/** MSC Bulk-Only Command Status Wrapper (CSW) */
+struct CSW {
+    uint32_t dSignature;
+    uint32_t dTag;
+    uint32_t dDataResidue;
+    uint8_t bStatus;
+} __packed;
+
+/* Device data structure */
+struct usbd_msc_cfg_private {
+    /* state of the bulk-only state machine */
+    enum Stage stage;
+    struct CBW cbw;
+    struct CSW csw;
+
+    uint8_t sKey; /* Sense key */
+    uint8_t ASC;  /* Additional Sense Code */
+    uint8_t ASQ;  /* Additional Sense Qualifier */
+    uint8_t max_lun;
+    uint16_t scsi_blk_size;
+    uint32_t scsi_blk_nbr;
+
+    uint32_t scsi_blk_addr;
+    uint32_t scsi_blk_len;
+    uint8_t *block_buffer;
+
+} usbd_msc_cfg;
+
+/*memory OK (after a usbd_msc_memory_verify)*/
+static bool memOK;
+
+static void usbd_msc_reset(void)
+{
+    usbd_msc_cfg.stage = MSC_READ_CBW;
+    usbd_msc_cfg.scsi_blk_addr = 0U;
+    usbd_msc_cfg.scsi_blk_len = 0U;
+    usbd_msc_cfg.max_lun = 0;
+    usbd_msc_cfg.sKey = 0;
+    usbd_msc_cfg.ASC = 0;
+    usbd_msc_cfg.ASQ = 0;
+
+    (void)memset((void *)&usbd_msc_cfg.cbw, 0, sizeof(struct CBW));
+    (void)memset((void *)&usbd_msc_cfg.csw, 0, sizeof(struct CSW));
+
+    usbd_msc_get_cap(0, &usbd_msc_cfg.scsi_blk_nbr, &usbd_msc_cfg.scsi_blk_size);
+
+    if (usbd_msc_cfg.block_buffer) {
+        free(usbd_msc_cfg.block_buffer);
+    }
+    usbd_msc_cfg.block_buffer = malloc(usbd_msc_cfg.scsi_blk_size * sizeof(uint8_t));
+    memset(usbd_msc_cfg.block_buffer, 0, usbd_msc_cfg.scsi_blk_size * sizeof(uint8_t));
+}
+
+/**
+ * @brief Handler called for Class requests not handled by the USB stack.
+ *
+ * @param setup    Information about the request to execute.
+ * @param len       Size of the buffer.
+ * @param data      Buffer containing the request result.
+ *
+ * @return  0 on success, negative errno code on fail.
+ */
+static int msc_storage_class_request_handler(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len)
+{
+    USBD_LOG_DBG("MSC Class request: "
+                 "bRequest 0x%02x\r\n",
+                 setup->bRequest);
+
+    switch (setup->bRequest) {
+        case MSC_REQUEST_RESET:
+            USBD_LOG_DBG("MSC_REQUEST_RESET\r\n");
+
+            if (setup->wLength) {
+                USBD_LOG_WRN("Invalid length\r\n");
+                return -1;
+            }
+
+            usbd_msc_reset();
+            break;
+
+        case MSC_REQUEST_GET_MAX_LUN:
+            USBD_LOG_DBG("MSC_REQUEST_GET_MAX_LUN\r\n");
+
+            if (setup->wLength != 1) {
+                USBD_LOG_WRN("Invalid length\r\n");
+                return -1;
+            }
+
+            *data = (uint8_t *)(&usbd_msc_cfg.max_lun);
+            *len = 1;
+            break;
+
+        default:
+            USBD_LOG_WRN("Unhandled MSC Class bRequest 0x%02x\r\n", setup->bRequest);
+            return -1;
+    }
+
+    return 0;
+}
+
+static void usbd_msc_bot_abort(void)
+{
+    if ((usbd_msc_cfg.cbw.bmFlags == 0) && (usbd_msc_cfg.cbw.dDataLength != 0)) {
+        usbd_ep_set_stall(mass_ep_data[MSD_OUT_EP_IDX].ep_addr);
+    }
+    usbd_ep_set_stall(mass_ep_data[MSD_IN_EP_IDX].ep_addr);
+}
+
+static void sendCSW(uint8_t CSW_Status)
+{
+    usbd_msc_cfg.csw.dSignature = MSC_CSW_Signature;
+    usbd_msc_cfg.csw.bStatus = CSW_Status;
+
+    /* updating the State Machine , so that we wait CSW when this
+	 * transfer is complete, ie when we get a bulk in callback
+	 */
+    usbd_msc_cfg.stage = MSC_WAIT_CSW;
+
+    if (usbd_ep_write(mass_ep_data[MSD_IN_EP_IDX].ep_addr, (uint8_t *)&usbd_msc_cfg.csw,
+                      sizeof(struct CSW), NULL) != 0) {
+        USBD_LOG_ERR("usb write failure\r\n");
+    }
+}
+
+static void sendLastData(uint8_t *buffer, uint8_t size)
+{
+    size = MIN(size, usbd_msc_cfg.cbw.dDataLength);
+
+    /* updating the State Machine , so that we send CSW when this
+	 * transfer is complete, ie when we get a bulk in callback
+	 */
+    usbd_msc_cfg.stage = MSC_SEND_CSW;
+
+    if (usbd_ep_write(mass_ep_data[MSD_IN_EP_IDX].ep_addr, buffer, size, NULL) != 0) {
+        USBD_LOG_ERR("USB write failed\r\n");
+    }
+
+    usbd_msc_cfg.csw.dDataResidue -= size;
+    usbd_msc_cfg.csw.bStatus = CSW_STATUS_CMD_PASSED;
+}
+
+/**
+ * @brief SCSI COMMAND
+ */
+static bool SCSI_testUnitReady(uint8_t **data, uint32_t *len);
+static bool SCSI_requestSense(uint8_t **data, uint32_t *len);
+static bool SCSI_inquiry(uint8_t **data, uint32_t *len);
+static bool SCSI_startStopUnit(uint8_t **data, uint32_t *len);
+static bool SCSI_preventAllowMediaRemoval(uint8_t **data, uint32_t *len);
+static bool SCSI_modeSense6(uint8_t **data, uint32_t *len);
+static bool SCSI_modeSense10(uint8_t **data, uint32_t *len);
+static bool SCSI_readFormatCapacity(uint8_t **data, uint32_t *len);
+static bool SCSI_readCapacity10(uint8_t **data, uint32_t *len);
+static bool SCSI_read10(uint8_t **data, uint32_t *len);
+static bool SCSI_read12(uint8_t **data, uint32_t *len);
+static bool SCSI_write10(uint8_t **data, uint32_t *len);
+static bool SCSI_write12(uint8_t **data, uint32_t *len);
+static bool SCSI_verify10(uint8_t **data, uint32_t *len);
+
+/**
+* @brief  SCSI_SenseCode
+*         Load the last error code in the error list
+* @param  sKey: Sense Key
+* @param  ASC: Additional Sense Code
+* @retval none
+
+*/
+static void SCSI_SenseCode(uint8_t sKey, uint8_t ASC)
+{
+    usbd_msc_cfg.sKey = sKey;
+    usbd_msc_cfg.ASC = ASC;
+}
+
+static bool SCSI_processRead(void)
+{
+    uint32_t transfer_len;
+
+    USBD_LOG_DBG("read addr:%d\r\n", usbd_msc_cfg.scsi_blk_addr);
+
+    transfer_len = MIN(usbd_msc_cfg.scsi_blk_len, MASS_STORAGE_BULK_EP_MPS);
+
+    /* we read an entire block */
+    if (!(usbd_msc_cfg.scsi_blk_addr % usbd_msc_cfg.scsi_blk_size)) {
+        if (usbd_msc_sector_read((usbd_msc_cfg.scsi_blk_addr / usbd_msc_cfg.scsi_blk_size), usbd_msc_cfg.block_buffer, usbd_msc_cfg.scsi_blk_size) != 0) {
+            SCSI_SenseCode(SCSI_SENSE_HARDWARE_ERROR, SCSI_ASC_UNRECOVERED_READ_ERROR);
+            return false;
+        }
+    }
+
+    usbd_ep_write(mass_ep_data[MSD_IN_EP_IDX].ep_addr,
+                  &usbd_msc_cfg.block_buffer[usbd_msc_cfg.scsi_blk_addr % usbd_msc_cfg.scsi_blk_size], transfer_len, NULL);
+
+    usbd_msc_cfg.scsi_blk_addr += transfer_len;
+    usbd_msc_cfg.scsi_blk_len -= transfer_len;
+    usbd_msc_cfg.csw.dDataResidue -= transfer_len;
+
+    if (usbd_msc_cfg.scsi_blk_len == 0) {
+        usbd_msc_cfg.stage = MSC_SEND_CSW;
+    }
+
+    return true;
+}
+
+static bool SCSI_processWrite(uint8_t *buf, uint16_t len)
+{
+    USBD_LOG_DBG("write addr:%d\r\n", usbd_msc_cfg.scsi_blk_addr);
+
+    /* we fill an array in RAM of 1 block before writing it in memory */
+    for (int i = 0; i < len; i++) {
+        usbd_msc_cfg.block_buffer[usbd_msc_cfg.scsi_blk_addr % usbd_msc_cfg.scsi_blk_size + i] = buf[i];
+    }
+
+    /* if the array is filled, write it in memory */
+    if ((usbd_msc_cfg.scsi_blk_addr % usbd_msc_cfg.scsi_blk_size) + len >= usbd_msc_cfg.scsi_blk_size) {
+        if (usbd_msc_sector_write((usbd_msc_cfg.scsi_blk_addr / usbd_msc_cfg.scsi_blk_size), usbd_msc_cfg.block_buffer, usbd_msc_cfg.scsi_blk_size) != 0) {
+            SCSI_SenseCode(SCSI_SENSE_HARDWARE_ERROR, SCSI_ASC_WRITE_FAULT);
+            return false;
+        }
+    }
+
+    usbd_msc_cfg.scsi_blk_addr += len;
+    usbd_msc_cfg.scsi_blk_len -= len;
+    usbd_msc_cfg.csw.dDataResidue -= len;
+
+    if (usbd_msc_cfg.scsi_blk_len == 0) {
+        sendCSW(CSW_STATUS_CMD_PASSED);
+    }
+
+    return true;
+}
+
+static bool SCSI_processVerify(uint8_t *buf, uint16_t len)
+{
+    USBD_LOG_DBG("verify addr:%d\r\n", usbd_msc_cfg.scsi_blk_addr);
+
+    /* we read an entire block */
+    if (!(usbd_msc_cfg.scsi_blk_addr % usbd_msc_cfg.scsi_blk_size)) {
+        if (usbd_msc_sector_read((usbd_msc_cfg.scsi_blk_addr / usbd_msc_cfg.scsi_blk_size), usbd_msc_cfg.block_buffer, usbd_msc_cfg.scsi_blk_size) != 0) {
+            SCSI_SenseCode(SCSI_SENSE_HARDWARE_ERROR, SCSI_ASC_UNRECOVERED_READ_ERROR);
+            return false;
+        }
+    }
+
+    /* info are in RAM -> no need to re-read memory */
+    for (uint16_t i = 0U; i < len; i++) {
+        if (usbd_msc_cfg.block_buffer[usbd_msc_cfg.scsi_blk_addr % usbd_msc_cfg.scsi_blk_size + i] != buf[i]) {
+            USBD_LOG_DBG("Mismatch sector %d offset %d",
+                         usbd_msc_cfg.scsi_blk_addr / usbd_msc_cfg.scsi_blk_size, i);
+            memOK = false;
+            break;
+        }
+    }
+
+    usbd_msc_cfg.scsi_blk_addr += len;
+    usbd_msc_cfg.scsi_blk_len -= len;
+    usbd_msc_cfg.csw.dDataResidue -= len;
+
+    if (usbd_msc_cfg.scsi_blk_len == 0) {
+        sendCSW(CSW_STATUS_CMD_PASSED);
+    }
+
+    return true;
+}
+
+static bool SCSI_CBWDecode(uint8_t *buf, uint16_t size)
+{
+    uint8_t send_buffer[64];
+    uint8_t *buf2send = send_buffer;
+    uint32_t len2send = 0;
+    bool ret = false;
+
+    if (size != sizeof(struct CBW)) {
+        USBD_LOG_ERR("size != sizeof(cbw)\r\n");
+        SCSI_SenseCode(SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB);
+        return false;
+    }
+
+    memcpy((uint8_t *)&usbd_msc_cfg.cbw, buf, size);
+
+    usbd_msc_cfg.csw.dTag = usbd_msc_cfg.cbw.dTag;
+    usbd_msc_cfg.csw.dDataResidue = usbd_msc_cfg.cbw.dDataLength;
+
+    if ((usbd_msc_cfg.cbw.bLUN > 1) || (usbd_msc_cfg.cbw.dSignature != MSC_CBW_Signature) || (usbd_msc_cfg.cbw.bCBLength < 1) || (usbd_msc_cfg.cbw.bCBLength > 16)) {
+        SCSI_SenseCode(SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB);
+        return false;
+    } else {
+        switch (usbd_msc_cfg.cbw.CB[0]) {
+            case SCSI_TEST_UNIT_READY:
+                ret = SCSI_testUnitReady(&buf2send, &len2send);
+                break;
+            case SCSI_REQUEST_SENSE:
+                ret = SCSI_requestSense(&buf2send, &len2send);
+                break;
+            case SCSI_INQUIRY:
+                ret = SCSI_inquiry(&buf2send, &len2send);
+                break;
+            case SCSI_START_STOP_UNIT:
+                ret = SCSI_startStopUnit(&buf2send, &len2send);
+                break;
+            case SCSI_PREVENT_ALLOW_MEDIA_REMOVAL:
+                ret = SCSI_preventAllowMediaRemoval(&buf2send, &len2send);
+                break;
+            case SCSI_MODE_SENSE6:
+                ret = SCSI_modeSense6(&buf2send, &len2send);
+                break;
+            case SCSI_MODE_SENSE10:
+                ret = SCSI_modeSense10(&buf2send, &len2send);
+                break;
+            case SCSI_READ_FORMAT_CAPACITIES:
+                ret = SCSI_readFormatCapacity(&buf2send, &len2send);
+                break;
+            case SCSI_READ_CAPACITY10:
+                ret = SCSI_readCapacity10(&buf2send, &len2send);
+                break;
+            case SCSI_READ10:
+                ret = SCSI_read10(NULL, 0);
+                break;
+            case SCSI_READ12:
+                ret = SCSI_read12(NULL, 0);
+                break;
+            case SCSI_WRITE10:
+                ret = SCSI_write10(NULL, 0);
+                break;
+            case SCSI_WRITE12:
+                ret = SCSI_write12(NULL, 0);
+                break;
+            case SCSI_VERIFY10:
+                ret = SCSI_verify10(NULL, 0);
+                break;
+
+            default:
+                SCSI_SenseCode(SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB);
+                USBD_LOG_WRN("unsupported cmd:0x%02x\r\n", usbd_msc_cfg.cbw.CB[0]);
+                ret = false;
+                break;
+        }
+    }
+    if (ret) {
+        if (usbd_msc_cfg.stage == MSC_READ_CBW) {
+            if (len2send) {
+                sendLastData(buf2send, len2send);
+            } else {
+                sendCSW(CSW_STATUS_CMD_PASSED);
+            }
+        }
+    }
+    return ret;
+}
+
+static bool SCSI_testUnitReady(uint8_t **data, uint32_t *len)
+{
+    if (usbd_msc_cfg.cbw.dDataLength != 0U) {
+        SCSI_SenseCode(SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB);
+        return false;
+    }
+    *data = NULL;
+    *len = 0;
+    return true;
+}
+
+static bool SCSI_requestSense(uint8_t **data, uint32_t *len)
+{
+    uint8_t data_len = REQUEST_SENSE_DATA_LEN;
+    if (usbd_msc_cfg.cbw.dDataLength == 0U) {
+        SCSI_SenseCode(SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB);
+        return false;
+    }
+
+    if (usbd_msc_cfg.cbw.CB[4] < REQUEST_SENSE_DATA_LEN) {
+        data_len = usbd_msc_cfg.cbw.CB[4];
+    }
+
+    uint8_t request_sense[REQUEST_SENSE_DATA_LEN] = {
+        0x70,
+        0x00,
+        0x00, /* Sense Key */
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        REQUEST_SENSE_DATA_LEN - 8,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00, /* Additional Sense Code */
+        0x00, /* Additional Sense Request */
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+    };
+
+    request_sense[2] = usbd_msc_cfg.sKey;
+    request_sense[12] = usbd_msc_cfg.ASC;
+    request_sense[13] = usbd_msc_cfg.ASQ;
+#if 0
+    request_sense[ 2] = 0x06;           /* UNIT ATTENTION */
+    request_sense[12] = 0x28;           /* Additional Sense Code: Not ready to ready transition */
+    request_sense[13] = 0x00;           /* Additional Sense Code Qualifier */
+#endif
+#if 0
+    request_sense[ 2] = 0x02;           /* NOT READY */
+    request_sense[12] = 0x3A;           /* Additional Sense Code: Medium not present */
+    request_sense[13] = 0x00;           /* Additional Sense Code Qualifier */
+#endif
+#if 0
+    request_sense[ 2] = 0x05;         /* ILLEGAL REQUEST */
+    request_sense[12] = 0x20;         /* Additional Sense Code: Invalid command */
+    request_sense[13] = 0x00;         /* Additional Sense Code Qualifier */
+#endif
+#if 0
+    request_sense[ 2] = 0x00;         /* NO SENSE */
+    request_sense[12] = 0x00;         /* Additional Sense Code: No additional code */
+    request_sense[13] = 0x00;         /* Additional Sense Code Qualifier */
+#endif
+
+    memcpy(*data, (uint8_t *)&request_sense, data_len);
+    *len = data_len;
+    return true;
+}
+
+static bool SCSI_inquiry(uint8_t **data, uint32_t *len)
+{
+    uint8_t data_len = STANDARD_INQUIRY_DATA_LEN;
+
+    uint8_t inquiry00[6] = {
+        0x00,
+        0x00,
+        0x00,
+        (0x06 - 4U),
+        0x00,
+        0x80
+    };
+
+    /* USB Mass storage VPD Page 0x80 Inquiry Data for Unit Serial Number */
+    uint8_t inquiry80[8] = {
+        0x00,
+        0x80,
+        0x00,
+        0x08,
+        0x20, /* Put Product Serial number */
+        0x20,
+        0x20,
+        0x20
+    };
+
+    uint8_t inquiry[STANDARD_INQUIRY_DATA_LEN] = {
+        /* 36 */
+
+        /* LUN 0 */
+        0x00,
+        0x80,
+        0x02,
+        0x02,
+        (STANDARD_INQUIRY_DATA_LEN - 5),
+        0x00,
+        0x00,
+        0x00,
+        'B', 'o', 'u', 'f', 'f', 'a', 'l', 'o', /* Manufacturer : 8 bytes */
+        'P', 'r', 'o', 'd', 'u', 'c', 't', ' ', /* Product      : 16 Bytes */
+        ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ',
+        '0', '.', '0', '1' /* Version      : 4 Bytes */
+    };
+
+    if (usbd_msc_cfg.cbw.dDataLength == 0U) {
+        SCSI_SenseCode(SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB);
+        return false;
+    }
+
+    if ((usbd_msc_cfg.cbw.CB[1] & 0x01U) != 0U) { /* Evpd is set */
+        if (usbd_msc_cfg.cbw.CB[2] == 0U) {       /* Request for Supported Vital Product Data Pages*/
+            data_len = 0x06;
+            memcpy(*data, (uint8_t *)&inquiry00, data_len);
+        } else if (usbd_msc_cfg.cbw.CB[2] == 0x80U) { /* Request for VPD page 0x80 Unit Serial Number */
+            data_len = 0x08;
+            memcpy(*data, (uint8_t *)&inquiry80, data_len);
+        } else { /* Request Not supported */
+            SCSI_SenseCode(SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INVALID_FIELED_IN_COMMAND);
+            return false;
+        }
+    } else {
+        if (usbd_msc_cfg.cbw.CB[4] < STANDARD_INQUIRY_DATA_LEN) {
+            data_len = usbd_msc_cfg.cbw.CB[4];
+        }
+        memcpy(*data, (uint8_t *)&inquiry, data_len);
+    }
+
+    *len = data_len;
+    return true;
+}
+
+static bool SCSI_startStopUnit(uint8_t **data, uint32_t *len)
+{
+    if (usbd_msc_cfg.cbw.dDataLength != 0U) {
+        SCSI_SenseCode(SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB);
+        return false;
+    }
+
+    if ((usbd_msc_cfg.cbw.CB[4] & 0x3U) == 0x1U) /* START=1 */
+    {
+        //SCSI_MEDIUM_UNLOCKED;
+    } else if ((usbd_msc_cfg.cbw.CB[4] & 0x3U) == 0x2U) /* START=0 and LOEJ Load Eject=1 */
+    {
+        //SCSI_MEDIUM_EJECTED;
+    } else if ((usbd_msc_cfg.cbw.CB[4] & 0x3U) == 0x3U) /* START=1 and LOEJ Load Eject=1 */
+    {
+        //SCSI_MEDIUM_UNLOCKED;
+    } else {
+    }
+
+    *data = NULL;
+    *len = 0;
+    return true;
+}
+
+static bool SCSI_preventAllowMediaRemoval(uint8_t **data, uint32_t *len)
+{
+    if (usbd_msc_cfg.cbw.dDataLength != 0U) {
+        SCSI_SenseCode(SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB);
+        return false;
+    }
+    if (usbd_msc_cfg.cbw.CB[4] == 0U) {
+        //SCSI_MEDIUM_UNLOCKED;
+    } else {
+        //SCSI_MEDIUM_LOCKED;
+    }
+    *data = NULL;
+    *len = 0;
+    return true;
+}
+
+static bool SCSI_modeSense6(uint8_t **data, uint32_t *len)
+{
+    uint8_t data_len = 4;
+    if (usbd_msc_cfg.cbw.dDataLength == 0U) {
+        SCSI_SenseCode(SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB);
+        return false;
+    }
+    if (usbd_msc_cfg.cbw.CB[4] < MODE_SENSE6_DATA_LEN) {
+        data_len = usbd_msc_cfg.cbw.CB[4];
+    }
+
+    uint8_t sense6[] = { 0x03, 0x00, 0x00, 0x00 };
+
+    memcpy(*data, (uint8_t *)&sense6, data_len);
+    *len = data_len;
+    return true;
+}
+
+static bool SCSI_modeSense10(uint8_t **data, uint32_t *len)
+{
+    uint8_t data_len = MODE_SENSE10_DATA_LEN;
+    if (usbd_msc_cfg.cbw.dDataLength == 0U) {
+        SCSI_SenseCode(SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB);
+        return false;
+    }
+    if (usbd_msc_cfg.cbw.CB[8] < MODE_SENSE10_DATA_LEN) {
+        data_len = usbd_msc_cfg.cbw.CB[8];
+    }
+
+    uint8_t sense10[MODE_SENSE10_DATA_LEN] = {
+        0x00,
+        0x26,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x08,
+        0x12,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00
+    };
+    memcpy(*data, (uint8_t *)&sense10, data_len);
+    *len = data_len;
+    return true;
+}
+
+static bool SCSI_readFormatCapacity(uint8_t **data, uint32_t *len)
+{
+    if (usbd_msc_cfg.cbw.dDataLength == 0U) {
+        SCSI_SenseCode(SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB);
+        return false;
+    }
+    uint8_t capacity[READ_FORMAT_CAPACITY_DATA_LEN] = {
+        0x00,
+        0x00,
+        0x00,
+        0x08, /* Capacity List Length */
+        (uint8_t)((usbd_msc_cfg.scsi_blk_nbr >> 24) & 0xff),
+        (uint8_t)((usbd_msc_cfg.scsi_blk_nbr >> 16) & 0xff),
+        (uint8_t)((usbd_msc_cfg.scsi_blk_nbr >> 8) & 0xff),
+        (uint8_t)((usbd_msc_cfg.scsi_blk_nbr >> 0) & 0xff),
+
+        0x02, /* Descriptor Code: Formatted Media */
+        0x00,
+        (uint8_t)((usbd_msc_cfg.scsi_blk_size >> 8) & 0xff),
+        (uint8_t)((usbd_msc_cfg.scsi_blk_size >> 0) & 0xff),
+    };
+
+    memcpy(*data, (uint8_t *)&capacity, READ_FORMAT_CAPACITY_DATA_LEN);
+    *len = READ_FORMAT_CAPACITY_DATA_LEN;
+    return true;
+}
+
+static bool SCSI_readCapacity10(uint8_t **data, uint32_t *len)
+{
+    if (usbd_msc_cfg.cbw.dDataLength == 0U) {
+        SCSI_SenseCode(SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB);
+        return false;
+    }
+
+    uint8_t capacity[READ_CAPACITY10_DATA_LEN] = {
+        (uint8_t)(((usbd_msc_cfg.scsi_blk_nbr - 1) >> 24) & 0xff),
+        (uint8_t)(((usbd_msc_cfg.scsi_blk_nbr - 1) >> 16) & 0xff),
+        (uint8_t)(((usbd_msc_cfg.scsi_blk_nbr - 1) >> 8) & 0xff),
+        (uint8_t)(((usbd_msc_cfg.scsi_blk_nbr - 1) >> 0) & 0xff),
+
+        (uint8_t)((usbd_msc_cfg.scsi_blk_size >> 24) & 0xff),
+        (uint8_t)((usbd_msc_cfg.scsi_blk_size >> 16) & 0xff),
+        (uint8_t)((usbd_msc_cfg.scsi_blk_size >> 8) & 0xff),
+        (uint8_t)((usbd_msc_cfg.scsi_blk_size >> 0) & 0xff),
+    };
+
+    memcpy(*data, (uint8_t *)&capacity, READ_CAPACITY10_DATA_LEN);
+    *len = READ_CAPACITY10_DATA_LEN;
+    return true;
+}
+
+static bool SCSI_read10(uint8_t **data, uint32_t *len)
+{
+    /* Logical Block Address of First Block */
+    uint32_t lba = 0;
+    uint32_t blk_num = 0;
+    if (((usbd_msc_cfg.cbw.bmFlags & 0x80U) != 0x80U) || (usbd_msc_cfg.cbw.dDataLength == 0U)) {
+        SCSI_SenseCode(SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB);
+        return false;
+    }
+
+    lba = GET_BE32(&usbd_msc_cfg.cbw.CB[2]);
+    USBD_LOG_DBG("lba: 0x%x\r\n", lba);
+
+    usbd_msc_cfg.scsi_blk_addr = lba * usbd_msc_cfg.scsi_blk_size;
+
+    /* Number of Blocks to transfer */
+    blk_num = GET_BE16(&usbd_msc_cfg.cbw.CB[7]);
+
+    USBD_LOG_DBG("num (block) : 0x%x\r\n", blk_num);
+    usbd_msc_cfg.scsi_blk_len = blk_num * usbd_msc_cfg.scsi_blk_size;
+
+    if ((lba + blk_num) > usbd_msc_cfg.scsi_blk_nbr) {
+        USBD_LOG_ERR("LBA out of range\r\n");
+        SCSI_SenseCode(SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ADDRESS_OUT_OF_RANGE);
+        return false;
+    }
+
+    if (usbd_msc_cfg.cbw.dDataLength != usbd_msc_cfg.scsi_blk_len) {
+        return false;
+    }
+    usbd_msc_cfg.stage = MSC_DATA_IN;
+    return SCSI_processRead();
+}
+
+static bool SCSI_read12(uint8_t **data, uint32_t *len)
+{
+    /* Logical Block Address of First Block */
+    uint32_t lba = 0;
+    uint32_t blk_num = 0;
+    if (((usbd_msc_cfg.cbw.bmFlags & 0x80U) != 0x80U) || (usbd_msc_cfg.cbw.dDataLength == 0U)) {
+        SCSI_SenseCode(SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB);
+        return false;
+    }
+
+    lba = GET_BE32(&usbd_msc_cfg.cbw.CB[2]);
+    USBD_LOG_DBG("lba: 0x%x\r\n", lba);
+
+    usbd_msc_cfg.scsi_blk_addr = lba * usbd_msc_cfg.scsi_blk_size;
+
+    /* Number of Blocks to transfer */
+    blk_num = GET_BE32(&usbd_msc_cfg.cbw.CB[6]);
+
+    USBD_LOG_DBG("num (block) : 0x%x\r\n", blk_num);
+    usbd_msc_cfg.scsi_blk_len = blk_num * usbd_msc_cfg.scsi_blk_size;
+
+    if ((lba + blk_num) > usbd_msc_cfg.scsi_blk_nbr) {
+        USBD_LOG_ERR("LBA out of range\r\n");
+        return false;
+    }
+
+    if (usbd_msc_cfg.cbw.dDataLength != usbd_msc_cfg.scsi_blk_len) {
+        return false;
+    }
+    usbd_msc_cfg.stage = MSC_DATA_IN;
+    return SCSI_processRead();
+}
+
+static bool SCSI_write10(uint8_t **data, uint32_t *len)
+{
+    /* Logical Block Address of First Block */
+    uint32_t lba = 0;
+    uint32_t blk_num = 0;
+    if (((usbd_msc_cfg.cbw.bmFlags & 0x80U) != 0x00U) || (usbd_msc_cfg.cbw.dDataLength == 0U)) {
+        SCSI_SenseCode(SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB);
+        return false;
+    }
+
+    lba = GET_BE32(&usbd_msc_cfg.cbw.CB[2]);
+    USBD_LOG_DBG("lba: 0x%x\r\n", lba);
+
+    usbd_msc_cfg.scsi_blk_addr = lba * usbd_msc_cfg.scsi_blk_size;
+
+    /* Number of Blocks to transfer */
+    blk_num = GET_BE16(&usbd_msc_cfg.cbw.CB[7]);
+
+    USBD_LOG_DBG("num (block) : 0x%x\r\n", blk_num);
+    usbd_msc_cfg.scsi_blk_len = blk_num * usbd_msc_cfg.scsi_blk_size;
+
+    if ((lba + blk_num) > usbd_msc_cfg.scsi_blk_nbr) {
+        USBD_LOG_ERR("LBA out of range\r\n");
+        return false;
+    }
+
+    if (usbd_msc_cfg.cbw.dDataLength != usbd_msc_cfg.scsi_blk_len) {
+        return false;
+    }
+    usbd_msc_cfg.stage = MSC_DATA_OUT;
+    return true;
+}
+
+static bool SCSI_write12(uint8_t **data, uint32_t *len)
+{
+    /* Logical Block Address of First Block */
+    uint32_t lba = 0;
+    uint32_t blk_num = 0;
+    if (((usbd_msc_cfg.cbw.bmFlags & 0x80U) != 0x00U) || (usbd_msc_cfg.cbw.dDataLength == 0U)) {
+        SCSI_SenseCode(SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB);
+        return false;
+    }
+
+    lba = GET_BE32(&usbd_msc_cfg.cbw.CB[2]);
+    USBD_LOG_DBG("lba: 0x%x\r\n", lba);
+
+    usbd_msc_cfg.scsi_blk_addr = lba * usbd_msc_cfg.scsi_blk_size;
+
+    /* Number of Blocks to transfer */
+    blk_num = GET_BE32(&usbd_msc_cfg.cbw.CB[6]);
+
+    USBD_LOG_DBG("num (block) : 0x%x\r\n", blk_num);
+    usbd_msc_cfg.scsi_blk_len = blk_num * usbd_msc_cfg.scsi_blk_size;
+
+    if ((lba + blk_num) > usbd_msc_cfg.scsi_blk_nbr) {
+        USBD_LOG_ERR("LBA out of range\r\n");
+        return false;
+    }
+
+    if (usbd_msc_cfg.cbw.dDataLength != usbd_msc_cfg.scsi_blk_len) {
+        return false;
+    }
+    usbd_msc_cfg.stage = MSC_DATA_OUT;
+    return true;
+}
+
+static bool SCSI_verify10(uint8_t **data, uint32_t *len)
+{
+    /* Logical Block Address of First Block */
+    uint32_t lba = 0;
+    uint32_t blk_num = 0;
+
+    if ((usbd_msc_cfg.cbw.CB[1] & 0x02U) == 0x00U) {
+        return true;
+    }
+
+    if (((usbd_msc_cfg.cbw.bmFlags & 0x80U) != 0x00U) || (usbd_msc_cfg.cbw.dDataLength == 0U)) {
+        SCSI_SenseCode(SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB);
+        return false;
+    }
+
+    if ((usbd_msc_cfg.cbw.CB[1] & 0x02U) == 0x02U) {
+        SCSI_SenseCode(SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INVALID_FIELED_IN_COMMAND);
+        return false; /* Error, Verify Mode Not supported*/
+    }
+
+    lba = GET_BE32(&usbd_msc_cfg.cbw.CB[2]);
+    USBD_LOG_DBG("lba: 0x%x\r\n", lba);
+
+    usbd_msc_cfg.scsi_blk_addr = lba * usbd_msc_cfg.scsi_blk_size;
+
+    /* Number of Blocks to transfer */
+    blk_num = GET_BE16(&usbd_msc_cfg.cbw.CB[7]);
+
+    USBD_LOG_DBG("num (block) : 0x%x\r\n", blk_num);
+    usbd_msc_cfg.scsi_blk_len = blk_num * usbd_msc_cfg.scsi_blk_size;
+
+    if ((lba + blk_num) > usbd_msc_cfg.scsi_blk_nbr) {
+        USBD_LOG_ERR("LBA out of range\r\n");
+        return false;
+    }
+
+    if (usbd_msc_cfg.cbw.dDataLength != usbd_msc_cfg.scsi_blk_len) {
+        return false;
+    }
+
+    memOK = true;
+    usbd_msc_cfg.stage = MSC_DATA_OUT;
+    return true;
+}
+
+static void mass_storage_bulk_out(uint8_t ep)
+{
+    uint8_t out_buf[MASS_STORAGE_BULK_EP_MPS];
+    uint32_t bytes_read;
+
+    usbd_ep_read(ep, out_buf, MASS_STORAGE_BULK_EP_MPS,
+                 &bytes_read);
+
+    switch (usbd_msc_cfg.stage) {
+        case MSC_READ_CBW:
+            if (SCSI_CBWDecode(out_buf, bytes_read) == false) {
+                USBD_LOG_ERR("Command:0x%02x decode err\r\n", usbd_msc_cfg.cbw.CB[0]);
+                usbd_msc_bot_abort();
+                return;
+            }
+            break;
+        /* last command is write10 or write12,and has caculated blk_addr and blk_len,so the device start reading data from host*/
+        case MSC_DATA_OUT:
+            switch (usbd_msc_cfg.cbw.CB[0]) {
+                case SCSI_WRITE10:
+                case SCSI_WRITE12:
+                    if (SCSI_processWrite(out_buf, bytes_read) == false) {
+                        sendCSW(CSW_STATUS_CMD_FAILED); /* send fail status to host,and the host will retry*/
+                        //return;
+                    }
+                    break;
+                case SCSI_VERIFY10:
+                    if (SCSI_processVerify(out_buf, bytes_read) == false) {
+                        sendCSW(CSW_STATUS_CMD_FAILED); /* send fail status to host,and the host will retry*/
+                        //return;
+                    }
+                    break;
+                default:
+                    break;
+            }
+            break;
+        default:
+            break;
+    }
+
+    /*set ep ack to recv next data*/
+    usbd_ep_read(ep, NULL, 0, NULL);
+}
+
+/**
+ * @brief EP Bulk IN handler, used to send data to the Host
+ *
+ * @param ep        Endpoint address.
+ * @param ep_status Endpoint status code.
+ *
+ * @return  N/A.
+ */
+static void mass_storage_bulk_in(uint8_t ep)
+{
+    switch (usbd_msc_cfg.stage) {
+        /* last command is read10 or read12,and has caculated blk_addr and blk_len,so the device has to send remain data to host*/
+        case MSC_DATA_IN:
+            switch (usbd_msc_cfg.cbw.CB[0]) {
+                case SCSI_READ10:
+                case SCSI_READ12:
+                    if (SCSI_processRead() == false) {
+                        sendCSW(CSW_STATUS_CMD_FAILED); /* send fail status to host,and the host will retry*/
+                        return;
+                    }
+                    break;
+                default:
+                    break;
+            }
+
+            break;
+
+        /*the device has to send a CSW*/
+        case MSC_SEND_CSW:
+            sendCSW(CSW_STATUS_CMD_PASSED);
+            break;
+
+        /*the host has received the CSW*/
+        case MSC_WAIT_CSW:
+            usbd_msc_cfg.stage = MSC_READ_CBW;
+            break;
+
+        default:
+            break;
+    }
+}
+
+void msc_storage_notify_handler(uint8_t event, void *arg)
+{
+    switch (event) {
+        case USB_EVENT_RESET:
+            usbd_msc_reset();
+            break;
+
+        default:
+            break;
+    }
+}
+
+static usbd_class_t msc_class;
+
+static usbd_interface_t msc_intf = {
+    .class_handler = msc_storage_class_request_handler,
+    .vendor_handler = NULL,
+    .notify_handler = msc_storage_notify_handler,
+};
+
+void usbd_msc_class_init(uint8_t out_ep, uint8_t in_ep)
+{
+    msc_class.name = "usbd_msc";
+
+    usbd_class_register(&msc_class);
+    usbd_class_add_interface(&msc_class, &msc_intf);
+
+    mass_ep_data[0].ep_addr = out_ep;
+    mass_ep_data[0].ep_cb = mass_storage_bulk_out;
+    mass_ep_data[1].ep_addr = in_ep;
+    mass_ep_data[1].ep_cb = mass_storage_bulk_in;
+
+    usbd_interface_add_endpoint(&msc_intf, &mass_ep_data[0]);
+    usbd_interface_add_endpoint(&msc_intf, &mass_ep_data[1]);
+}
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/msc/usbd_msc.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/msc/usbd_msc.h
new file mode 100644
index 00000000..3b5fe3e5
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/msc/usbd_msc.h
@@ -0,0 +1,109 @@
+/**
+ * @file
+ * @brief USB Mass Storage Class public header
+ *
+ * Header follows the Mass Storage Class Specification
+ * (Mass_Storage_Specification_Overview_v1.4_2-19-2010.pdf) and
+ * Mass Storage Class Bulk-Only Transport Specification
+ * (usbmassbulk_10.pdf).
+ * Header is limited to Bulk-Only Transfer protocol.
+ */
+
+#ifndef _USBD_MSC_H__
+#define _USBD_MSC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* MSC Subclass Codes */
+#define MSC_SUBCLASS_RBC           0x01
+#define MSC_SUBCLASS_SFF8020I_MMC2 0x02
+#define MSC_SUBCLASS_QIC157        0x03
+#define MSC_SUBCLASS_UFI           0x04
+#define MSC_SUBCLASS_SFF8070I      0x05
+#define MSC_SUBCLASS_SCSI          0x06
+
+/* MSC Protocol Codes */
+#define MSC_PROTOCOL_CBI_INT   0x00
+#define MSC_PROTOCOL_CBI_NOINT 0x01
+#define MSC_PROTOCOL_BULK_ONLY 0x50
+
+/* MSC Request Codes */
+#define MSC_REQUEST_RESET       0xFF
+#define MSC_REQUEST_GET_MAX_LUN 0xFE
+
+/** MSC Command Block Wrapper (CBW) Signature */
+#define MSC_CBW_Signature 0x43425355
+/** Bulk-only Command Status Wrapper (CSW) Signature */
+#define MSC_CSW_Signature 0x53425355
+
+/** MSC Command Block Status Values */
+#define CSW_STATUS_CMD_PASSED  0x00
+#define CSW_STATUS_CMD_FAILED  0x01
+#define CSW_STATUS_PHASE_ERROR 0x02
+
+/*Length of template descriptor: 23 bytes*/
+#define MSC_DESCRIPTOR_LEN (9 + 7 + 7)
+// clang-format off
+#ifndef SUPPORT_USB_HS
+#define MSC_DESCRIPTOR_INIT(bFirstInterface, out_ep, in_ep,str_idx) \
+    /* Interface */                                              \
+    0x09,                          /* bLength */                 \
+    USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */         \
+    bFirstInterface,               /* bInterfaceNumber */        \
+    0x00,                          /* bAlternateSetting */       \
+    0x02,                          /* bNumEndpoints */           \
+    USB_DEVICE_CLASS_MASS_STORAGE, /* bInterfaceClass */         \
+    MSC_SUBCLASS_SCSI,             /* bInterfaceSubClass */      \
+    MSC_PROTOCOL_BULK_ONLY,        /* bInterfaceProtocol */      \
+    str_idx,                       /* iInterface */              \
+    0x07,                          /* bLength */                 \
+    USB_DESCRIPTOR_TYPE_ENDPOINT,  /* bDescriptorType */         \
+    out_ep,                        /* bEndpointAddress */        \
+    0x02,                          /* bmAttributes */            \
+    0x40, 0x00,                    /* wMaxPacketSize */          \
+    0x00,                          /* bInterval */               \
+    0x07,                          /* bLength */                 \
+    USB_DESCRIPTOR_TYPE_ENDPOINT,  /* bDescriptorType */         \
+    in_ep,                         /* bEndpointAddress */        \
+    0x02,                          /* bmAttributes */            \
+    0x40, 0x00,                    /* wMaxPacketSize */          \
+    0x00                           /* bInterval */
+#else
+#define MSC_DESCRIPTOR_INIT(bFirstInterface, out_ep, in_ep,str_idx) \
+    /* Interface */                                              \
+    0x09,                          /* bLength */                 \
+    USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */         \
+    bFirstInterface,               /* bInterfaceNumber */        \
+    0x00,                          /* bAlternateSetting */       \
+    0x02,                          /* bNumEndpoints */           \
+    USB_DEVICE_CLASS_MASS_STORAGE, /* bInterfaceClass */         \
+    MSC_SUBCLASS_SCSI,             /* bInterfaceSubClass */      \
+    MSC_PROTOCOL_BULK_ONLY,        /* bInterfaceProtocol */      \
+    str_idx,                       /* iInterface */              \
+    0x07,                          /* bLength */                 \
+    USB_DESCRIPTOR_TYPE_ENDPOINT,  /* bDescriptorType */         \
+    out_ep,                        /* bEndpointAddress */        \
+    0x02,                          /* bmAttributes */            \
+    0x00, 0x02,                    /* wMaxPacketSize */          \
+    0x00,                          /* bInterval */               \
+    0x07,                          /* bLength */                 \
+    USB_DESCRIPTOR_TYPE_ENDPOINT,  /* bDescriptorType */         \
+    in_ep,                         /* bEndpointAddress */        \
+    0x02,                          /* bmAttributes */            \
+    0x00, 0x02,                    /* wMaxPacketSize */          \
+    0x00                           /* bInterval */
+#endif
+// clang-format on
+
+void usbd_msc_class_init(uint8_t out_ep, uint8_t in_ep);
+void usbd_msc_get_cap(uint8_t lun, uint32_t *block_num, uint16_t *block_size);
+int usbd_msc_sector_read(uint32_t sector, uint8_t *buffer, uint32_t length);
+int usbd_msc_sector_write(uint32_t sector, uint8_t *buffer, uint32_t length);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USB_MSC_H_ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/msc/usbd_scsi.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/msc/usbd_scsi.h
new file mode 100644
index 00000000..618d8f7a
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/msc/usbd_scsi.h
@@ -0,0 +1,325 @@
+/**
+ * @file
+ * @brief USB Mass Storage Class SCSI public header
+ *
+ * Header follows the Mass Storage Class Specification
+ * (Mass_Storage_Specification_Overview_v1.4_2-19-2010.pdf) and
+ * Mass Storage Class Bulk-Only Transport Specification
+ * (usbmassbulk_10.pdf).
+ * Header is limited to Bulk-Only Transfer protocol.
+ */
+
+#ifndef _USBD_SCSI_H_
+#define _USBD_SCSI_H_
+
+/* SCSI Commands */
+#define SCSI_TEST_UNIT_READY             0x00
+#define SCSI_REQUEST_SENSE               0x03
+#define SCSI_FORMAT_UNIT                 0x04
+#define SCSI_INQUIRY                     0x12
+#define SCSI_MODE_SELECT6                0x15
+#define SCSI_MODE_SENSE6                 0x1A
+#define SCSI_START_STOP_UNIT             0x1B
+#define SCSI_SEND_DIAGNOSTIC             0x1D
+#define SCSI_PREVENT_ALLOW_MEDIA_REMOVAL 0x1E
+#define SCSI_READ_FORMAT_CAPACITIES      0x23
+#define SCSI_READ_CAPACITY10             0x25
+#define SCSI_READ10                      0x28
+#define SCSI_WRITE10                     0x2A
+#define SCSI_VERIFY10                    0x2F
+#define SCSI_SYNC_CACHE10                0x35
+#define SCSI_READ12                      0xA8
+#define SCSI_WRITE12                     0xAA
+#define SCSI_MODE_SELECT10               0x55
+#define SCSI_MODE_SENSE10                0x5A
+#define SCSI_ATA_COMMAND_PASS_THROUGH16  0x85
+#define SCSI_READ16                      0x88
+#define SCSI_WRITE16                     0x8A
+#define SCSI_VERIFY16                    0x8F
+#define SCSI_SYNC_CACHE16                0x91
+#define SCSI_SERVICE_ACTION_IN16         0x9E
+#define SCSI_READ_CAPACITY16             0x9E
+#define SCSI_SERVICE_ACTION_OUT16        0x9F
+#define SCSI_ATA_COMMAND_PASS_THROUGH12  0xA1
+#define SCSI_REPORT_ID_INFO              0xA3
+#define SCSI_READ12                      0xA8
+#define SCSI_SERVICE_ACTION_OUT12        0xA9
+#define SCSI_SERVICE_ACTION_IN12         0xAB
+#define SCSI_VERIFY12                    0xAF
+
+/* SCSI Sense Key */
+#define SCSI_SENSE_NONE            0x00
+#define SCSI_SENSE_RECOVERED_ERROR 0x01
+#define SCSI_SENSE_NOT_READY       0x02
+#define SCSI_SENSE_MEDIUM_ERROR    0x03
+#define SCSI_SENSE_HARDWARE_ERROR  0x04
+#define SCSI_SENSE_ILLEGAL_REQUEST 0x05
+#define SCSI_SENSE_UNIT_ATTENTION  0x06
+#define SCSI_SENSE_DATA_PROTECT    0x07
+#define SCSI_SENSE_FIRMWARE_ERROR  0x08
+#define SCSI_SENSE_ABORTED_COMMAND 0x0b
+#define SCSI_SENSE_EQUAL           0x0c
+#define SCSI_SENSE_VOLUME_OVERFLOW 0x0d
+#define SCSI_SENSE_MISCOMPARE      0x0e
+
+/* Additional Sense Code */
+#define SCSI_ASC_INVALID_CDB                     0x20U
+#define SCSI_ASC_INVALID_FIELED_IN_COMMAND       0x24U
+#define SCSI_ASC_PARAMETER_LIST_LENGTH_ERROR     0x1AU
+#define SCSI_ASC_INVALID_FIELD_IN_PARAMETER_LIST 0x26U
+#define SCSI_ASC_ADDRESS_OUT_OF_RANGE            0x21U
+#define SCSI_ASC_MEDIUM_NOT_PRESENT              0x3AU
+#define SCSI_ASC_MEDIUM_HAVE_CHANGED             0x28U
+#define SCSI_ASC_WRITE_PROTECTED                 0x27U
+#define SCSI_ASC_UNRECOVERED_READ_ERROR          0x11U
+#define SCSI_ASC_WRITE_FAULT                     0x03U
+
+#define READ_FORMAT_CAPACITY_DATA_LEN 0x0CU
+#define READ_CAPACITY10_DATA_LEN      0x08U
+#define REQUEST_SENSE_DATA_LEN        0x12U
+#define STANDARD_INQUIRY_DATA_LEN     0x24U
+#define MODE_SENSE6_DATA_LEN          0x17U
+#define MODE_SENSE10_DATA_LEN         0x1BU
+
+#define SCSI_MEDIUM_STATUS_UNLOCKED 0x00U
+#define SCSI_MEDIUM_STATUS_LOCKED   0x01U
+#define SCSI_MEDIUM_STATUS_EJECTED  0x02U
+
+//--------------------------------------------------------------------+
+// SCSI Primary Command (SPC-4)
+//--------------------------------------------------------------------+
+
+/// SCSI Test Unit Ready Command
+typedef struct __packed {
+    uint8_t cmd_code; ///< SCSI OpCode for \ref SCSI_CMD_TEST_UNIT_READY
+    uint8_t lun;      ///< Logical Unit
+    uint8_t reserved[3];
+    uint8_t control;
+} scsi_test_unit_ready_cmd_t;
+
+/// SCSI Inquiry Command
+typedef struct __packed {
+    uint8_t cmd_code; ///< SCSI OpCode for \ref SCSI_CMD_INQUIRY
+    uint8_t reserved1;
+    uint8_t page_code;
+    uint8_t reserved2;
+    uint8_t alloc_length; ///< specifies the maximum number of bytes that USB host has allocated in the Data-In Buffer. An allocation length of zero specifies that no data shall be transferred.
+    uint8_t control;
+} scsi_inquiry_cmd_t, scsi_request_sense_cmd_t;
+
+/// SCSI Inquiry Response Data
+typedef struct __packed {
+    uint8_t peripheral_device_type : 5;
+    uint8_t peripheral_qualifier   : 3;
+
+    uint8_t              : 7;
+    uint8_t is_removable : 1;
+
+    uint8_t version;
+
+    uint8_t response_data_format : 4;
+    uint8_t hierarchical_support : 1;
+    uint8_t normal_aca           : 1;
+    uint8_t                      : 2;
+
+    uint8_t additional_length;
+
+    uint8_t protect                    : 1;
+    uint8_t                            : 2;
+    uint8_t third_party_copy           : 1;
+    uint8_t target_port_group_support  : 2;
+    uint8_t access_control_coordinator : 1;
+    uint8_t scc_support                : 1;
+
+    uint8_t addr16            : 1;
+    uint8_t                   : 3;
+    uint8_t multi_port        : 1;
+    uint8_t                   : 1; // vendor specific
+    uint8_t enclosure_service : 1;
+    uint8_t                   : 1;
+
+    uint8_t         : 1; // vendor specific
+    uint8_t cmd_que : 1;
+    uint8_t         : 2;
+    uint8_t sync    : 1;
+    uint8_t wbus16  : 1;
+    uint8_t         : 2;
+
+    uint8_t vendor_id[8];   ///< 8 bytes of ASCII data identifying the vendor of the product.
+    uint8_t product_id[16]; ///< 16 bytes of ASCII data defined by the vendor.
+    uint8_t product_rev[4]; ///< 4 bytes of ASCII data defined by the vendor.
+} scsi_inquiry_resp_t;
+
+typedef struct __packed {
+    uint8_t response_code : 7; ///< 70h - current errors, Fixed Format 71h - deferred errors, Fixed Format
+    uint8_t valid         : 1;
+
+    uint8_t reserved;
+
+    uint8_t sense_key     : 4;
+    uint8_t               : 1;
+    uint8_t ili           : 1; ///< Incorrect length indicator
+    uint8_t end_of_medium : 1;
+    uint8_t filemark      : 1;
+
+    uint32_t information;
+    uint8_t add_sense_len;
+    uint32_t command_specific_info;
+    uint8_t add_sense_code;
+    uint8_t add_sense_qualifier;
+    uint8_t field_replaceable_unit_code;
+
+    uint8_t sense_key_specific[3]; ///< sense key specific valid bit is bit 7 of key[0], aka MSB in Big Endian layout
+
+} scsi_sense_fixed_resp_t;
+
+typedef struct __packed {
+    uint8_t cmd_code; ///< SCSI OpCode for \ref SCSI_CMD_MODE_SENSE_6
+
+    uint8_t                          : 3;
+    uint8_t disable_block_descriptor : 1;
+    uint8_t                          : 4;
+
+    uint8_t page_code    : 6;
+    uint8_t page_control : 2;
+
+    uint8_t subpage_code;
+    uint8_t alloc_length;
+    uint8_t control;
+} scsi_mode_sense6_cmd_t;
+
+// This is only a Mode parameter header(6).
+typedef struct __packed {
+    uint8_t data_len;
+    uint8_t medium_type;
+
+    uint8_t reserved     : 7;
+    bool write_protected : 1;
+
+    uint8_t block_descriptor_len;
+} scsi_mode_sense6_resp_t;
+
+typedef struct
+{
+    uint8_t cmd_code;
+
+    uint8_t reserved1                : 3;
+    uint8_t disable_block_descriptor : 1;
+    uint8_t long_LBA                 : 1;
+    uint8_t reserved2                : 3;
+
+    uint8_t page_code    : 6;
+    uint8_t page_control : 2;
+
+    uint8_t subpage_code;
+
+    uint8_t reserved3;
+    uint8_t reserved4;
+    uint8_t reserved5;
+
+    uint8_t length[2];
+
+    uint8_t control;
+} scsi_mode_sense_10_cmd_t;
+
+typedef struct
+{
+    uint8_t mode_data_length_high;
+    uint8_t mode_data_length_low;
+    uint8_t medium_type;
+
+    uint8_t reserved1     : 4;
+    uint8_t DPO_FUA       : 1; /**< [Disable Page Out] and [Force Unit Access] in the SCSI_READ10 command is valid or not */
+    uint8_t reserved2     : 2;
+    uint8_t write_protect : 1;
+
+    uint8_t long_LBA  : 1;
+    uint8_t reserved3 : 7;
+
+    uint8_t reserved4;
+    uint8_t block_desc_length[2];
+} scsi_mode_10_resp_t;
+
+typedef struct __packed {
+    uint8_t cmd_code; ///< SCSI OpCode for \ref SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL
+    uint8_t reserved[3];
+    uint8_t prohibit_removal;
+    uint8_t control;
+} scsi_prevent_allow_medium_removal_t;
+
+typedef struct __packed {
+    uint8_t cmd_code;
+
+    uint8_t immded : 1;
+    uint8_t        : 7;
+
+    uint8_t TU_RESERVED;
+
+    uint8_t power_condition_mod : 4;
+    uint8_t                     : 4;
+
+    uint8_t start           : 1;
+    uint8_t load_eject      : 1;
+    uint8_t no_flush        : 1;
+    uint8_t                 : 1;
+    uint8_t power_condition : 4;
+
+    uint8_t control;
+} scsi_start_stop_unit_cmd_t;
+
+//--------------------------------------------------------------------+
+// SCSI MMC
+//--------------------------------------------------------------------+
+/// SCSI Read Format Capacity: Write Capacity
+typedef struct __packed {
+    uint8_t cmd_code;
+    uint8_t reserved[6];
+    uint16_t alloc_length;
+    uint8_t control;
+} scsi_read_format_capacity_cmd_t;
+
+typedef struct __packed {
+    uint8_t reserved[3];
+    uint8_t list_length; /// must be 8*n, length in bytes of formattable capacity descriptor followed it.
+
+    uint32_t block_num;      /// Number of Logical Blocks
+    uint8_t descriptor_type; // 00: reserved, 01 unformatted media , 10 Formatted media, 11 No media present
+
+    uint8_t reserved2;
+    uint16_t block_size_u16;
+
+} scsi_read_format_capacity_resp_t;
+
+//--------------------------------------------------------------------+
+// SCSI Block Command (SBC-3)
+// NOTE: All data in SCSI command are in Big Endian
+//--------------------------------------------------------------------+
+
+/// SCSI Read Capacity 10 Command: Read Capacity
+typedef struct __packed {
+    uint8_t cmd_code; ///< SCSI OpCode for \ref SCSI_CMD_READ_CAPACITY_10
+    uint8_t reserved1;
+    uint32_t lba; ///< The first Logical Block Address (LBA) accessed by this command
+    uint16_t reserved2;
+    uint8_t partial_medium_indicator;
+    uint8_t control;
+} scsi_read_capacity10_cmd_t;
+
+/// SCSI Read Capacity 10 Response Data
+typedef struct
+{
+    uint32_t last_lba;   ///< The last Logical Block Address of the device
+    uint32_t block_size; ///< Block size in bytes
+} scsi_read_capacity10_resp_t;
+
+/// SCSI Read 10 Command
+typedef struct __packed {
+    uint8_t cmd_code; ///< SCSI OpCode
+    uint8_t reserved; // has LUN according to wiki
+    uint32_t lba;     ///< The first Logical Block Address (LBA) accessed by this command
+    uint8_t reserved2;
+    uint16_t block_count; ///< Number of Blocks used by this command
+    uint8_t control;
+} scsi_read10_t, scsi_write10_t, scsi_read_write_10_t;
+
+#endif /* ZEPHYR_INCLUDE_USB_CLASS_USB_CDC_H_ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/video/usbd_video.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/video/usbd_video.c
new file mode 100644
index 00000000..6eb2554b
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/video/usbd_video.c
@@ -0,0 +1,134 @@
+/**
+ * @file usbd_video.c
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "usbd_core.h"
+#include "usbd_video.h"
+
+extern struct video_probe_and_commit_controls probe;
+extern struct video_probe_and_commit_controls commit;
+
+int video_class_request_handler(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len)
+{
+    USBD_LOG_DBG("Video Class request: "
+                 "bRequest 0x%02x\r\n",
+                 setup->bRequest);
+
+    switch (setup->bRequest) {
+        case VIDEO_REQUEST_SET_CUR:
+            if (setup->wValue == 256) {
+                memcpy((uint8_t *)&probe, *data, setup->wLength);
+            } else if (setup->wValue == 512) {
+                memcpy((uint8_t *)&commit, *data, setup->wLength);
+            }
+
+            break;
+
+        case VIDEO_REQUEST_GET_CUR:
+            if (setup->wValue == 256) {
+                *data = (uint8_t *)&probe;
+            } else if (setup->wValue == 512) {
+                *data = (uint8_t *)&commit;
+            }
+
+            break;
+
+        case VIDEO_REQUEST_GET_MIN:
+            if (setup->wValue == 256) {
+                *data = (uint8_t *)&probe;
+            } else if (setup->wValue == 512) {
+                *data = (uint8_t *)&commit;
+            }
+
+            break;
+
+        case VIDEO_REQUEST_GET_MAX:
+            if (setup->wValue == 256) {
+                *data = (uint8_t *)&probe;
+            } else if (setup->wValue == 512) {
+                *data = (uint8_t *)&commit;
+            }
+
+            break;
+
+        case VIDEO_REQUEST_GET_RES:
+
+            break;
+
+        case VIDEO_REQUEST_GET_LEN:
+
+            break;
+
+        case VIDEO_REQUEST_GET_INFO:
+
+            break;
+
+        case VIDEO_REQUEST_GET_DEF:
+            if (setup->wLength == 256) {
+                *data = (uint8_t *)&probe;
+            } else if (setup->wLength == 512) {
+                *data = (uint8_t *)&commit;
+            }
+
+            break;
+
+        default:
+            USBD_LOG_WRN("Unhandled Video Class bRequest 0x%02x\r\n", setup->bRequest);
+            return -1;
+    }
+
+    return 0;
+}
+
+void video_notify_handler(uint8_t event, void *arg)
+{
+    switch (event) {
+        case USB_EVENT_RESET:
+
+            break;
+
+        case USB_EVENT_SOF:
+            usbd_video_sof_callback();
+            break;
+
+        case USB_EVENT_SET_INTERFACE:
+            usbd_video_set_interface_callback(((uint8_t *)arg)[3]);
+            break;
+
+        default:
+            break;
+    }
+}
+
+void usbd_video_add_interface(usbd_class_t *class, usbd_interface_t *intf)
+{
+    static usbd_class_t *last_class = NULL;
+
+    if (last_class != class) {
+        last_class = class;
+        usbd_class_register(class);
+    }
+
+    intf->class_handler = video_class_request_handler;
+    intf->custom_handler = NULL;
+    intf->vendor_handler = NULL;
+    intf->notify_handler = video_notify_handler;
+    usbd_class_add_interface(class, intf);
+}
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/video/usbd_video.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/video/usbd_video.h
new file mode 100644
index 00000000..09c452f5
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/video/usbd_video.h
@@ -0,0 +1,821 @@
+/**
+ * @file
+ * @brief USB Video Device Class public header
+ *
+ * Header follows below documentation:
+ * - USB Device Class Definition for Video Devices UVC 1.5 Class specification.pdf
+ */
+
+#ifndef _USBD_VIDEO_H_
+#define _USBD_VIDEO_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define USB_DEVICE_VIDEO_CLASS_VERSION_1_5 0
+
+/*! @brief Video device subclass code */
+#define VIDEO_SC_UNDEFINED                  0x00U
+#define VIDEO_SC_VIDEOCONTROL               0x01U
+#define VIDEO_SC_VIDEOSTREAMING             0x02U
+#define VIDEO_SC_VIDEO_INTERFACE_COLLECTION 0x03U
+
+/*! @brief Video device protocol code */
+#define VIDEO_PC_PROTOCOL_UNDEFINED 0x00U
+#define VIDEO_PC_PROTOCOL_15        0x01U
+
+/*! @brief Video device class-specific descriptor type */
+#define VIDEO_CS_UNDEFINED_DESCRIPTOR_TYPE     0x20U
+#define VIDEO_CS_DEVICE_DESCRIPTOR_TYPE        0x21U
+#define VIDEO_CS_CONFIGURATION_DESCRIPTOR_TYPE 0x22U
+#define VIDEO_CS_STRING_DESCRIPTOR_TYPE        0x23U
+#define VIDEO_CS_INTERFACE_DESCRIPTOR_TYPE     0x24U
+#define VIDEO_CS_ENDPOINT_DESCRIPTOR_TYPE      0x25U
+
+/*! @brief Video device class-specific VC interface descriptor subtype */
+#define VIDEO_VC_DESCRIPTOR_UNDEFINED_DESCRIPTOR_SUBTYPE 0x00U
+#define VIDEO_VC_HEADER_DESCRIPTOR_SUBTYPE               0x01U
+#define VIDEO_VC_INPUT_TERMINAL_DESCRIPTOR_SUBTYPE       0x02U
+#define VIDEO_VC_OUTPUT_TERMINAL_DESCRIPTOR_SUBTYPE      0x03U
+#define VIDEO_VC_SELECTOR_UNIT_DESCRIPTOR_SUBTYPE        0x04U
+#define VIDEO_VC_PROCESSING_UNIT_DESCRIPTOR_SUBTYPE      0x05U
+#define VIDEO_VC_EXTENSION_UNIT_DESCRIPTOR_SUBTYPE       0x06U
+#define VIDEO_VC_ENCODING_UNIT_DESCRIPTOR_SUBTYPE        0x07U
+
+/*! @brief Video device class-specific VS interface descriptor subtype */
+#define VIDEO_VS_UNDEFINED_DESCRIPTOR_SUBTYPE             0x00U
+#define VIDEO_VS_INPUT_HEADER_DESCRIPTOR_SUBTYPE          0x01U
+#define VIDEO_VS_OUTPUT_HEADER_DESCRIPTOR_SUBTYPE         0x02U
+#define VIDEO_VS_STILL_IMAGE_FRAME_DESCRIPTOR_SUBTYPE     0x03U
+#define VIDEO_VS_FORMAT_UNCOMPRESSED_DESCRIPTOR_SUBTYPE   0x04U
+#define VIDEO_VS_FRAME_UNCOMPRESSED_DESCRIPTOR_SUBTYPE    0x05U
+#define VIDEO_VS_FORMAT_MJPEG_DESCRIPTOR_SUBTYPE          0x06U
+#define VIDEO_VS_FRAME_MJPEG_DESCRIPTOR_SUBTYPE           0x07U
+#define VIDEO_VS_FORMAT_MPEG2TS_DESCRIPTOR_SUBTYPE        0x0AU
+#define VIDEO_VS_FORMAT_DV_DESCRIPTOR_SUBTYPE             0x0CU
+#define VIDEO_VS_COLORFORMAT_DESCRIPTOR_SUBTYPE           0x0DU
+#define VIDEO_VS_FORMAT_FRAME_BASED_DESCRIPTOR_SUBTYPE    0x10U
+#define VIDEO_VS_FRAME_FRAME_BASED_DESCRIPTOR_SUBTYPE     0x11U
+#define VIDEO_VS_FORMAT_STREAM_BASED_DESCRIPTOR_SUBTYPE   0x12U
+#define VIDEO_VS_FORMAT_H264_DESCRIPTOR_SUBTYPE           0x13U
+#define VIDEO_VS_FRAME_H264_DESCRIPTOR_SUBTYPE            0x14U
+#define VIDEO_VS_FORMAT_H264_SIMULCAST_DESCRIPTOR_SUBTYPE 0x15U
+#define VIDEO_VS_FORMAT_VP8_DESCRIPTOR_SUBTYPE            0x16U
+#define VIDEO_VS_FRAME_VP8_DESCRIPTOR_SUBTYPE             0x17U
+#define VIDEO_VS_FORMAT_VP8_SIMULCAST_DESCRIPTOR_SUBTYPE  0x18U
+
+/*! @brief Video device class-specific VC endpoint descriptor subtype */
+#define VIDEO_EP_UNDEFINED_DESCRIPTOR_SUBTYPE 0x00U
+#define VIDEO_EP_GENERAL_DESCRIPTOR_SUBTYPE   0x01U
+#define VIDEO_EP_ENDPOINT_DESCRIPTOR_SUBTYPE  0x02U
+#define VIDEO_EP_INTERRUPT_DESCRIPTOR_SUBTYPE 0x03U
+
+/*! @brief Video device class-specific request code */
+#define VIDEO_REQUEST_UNDEFINED   0x00U
+#define VIDEO_REQUEST_SET_CUR     0x01U
+#define VIDEO_REQUEST_SET_CUR_ALL 0x11U
+#define VIDEO_REQUEST_GET_CUR     0x81U
+#define VIDEO_REQUEST_GET_MIN     0x82U
+#define VIDEO_REQUEST_GET_MAX     0x83U
+#define VIDEO_REQUEST_GET_RES     0x84U
+#define VIDEO_REQUEST_GET_LEN     0x85U
+#define VIDEO_REQUEST_GET_INFO    0x86U
+#define VIDEO_REQUEST_GET_DEF     0x87U
+#define VIDEO_REQUEST_GET_CUR_ALL 0x91U
+#define VIDEO_REQUEST_GET_MIN_ALL 0x92U
+#define VIDEO_REQUEST_GET_MAX_ALL 0x93U
+#define VIDEO_REQUEST_GET_RES_ALL 0x94U
+#define VIDEO_REQUEST_GET_DEF_ALL 0x97U
+
+/*! @brief Video device class-specific VideoControl interface control selector */
+#define VIDEO_VC_CONTROL_UNDEFINED          0x00U
+#define VIDEO_VC_VIDEO_POWER_MODE_CONTROL   0x01U
+#define VIDEO_VC_REQUEST_ERROR_CODE_CONTROL 0x02U
+
+/*! @brief Video device class-specific Terminal control selector */
+#define VIDEO_TE_CONTROL_UNDEFINED 0x00U
+
+/*! @brief Video device class-specific Selector Unit control selector */
+#define VIDEO_SU_CONTROL_UNDEFINED    0x00U
+#define VIDEO_SU_INPUT_SELECT_CONTROL 0x01U
+
+/*! @brief Video device class-specific Camera Terminal control selector */
+#define VIDEO_CT_CONTROL_UNDEFINED              0x00U
+#define VIDEO_CT_SCANNING_MODE_CONTROL          0x01U
+#define VIDEO_CT_AE_MODE_CONTROL                0x02U
+#define VIDEO_CT_AE_PRIORITY_CONTROL            0x03U
+#define VIDEO_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x04U
+#define VIDEO_CT_EXPOSURE_TIME_RELATIVE_CONTROL 0x05U
+#define VIDEO_CT_FOCUS_ABSOLUTE_CONTROL         0x06U
+#define VIDEO_CT_FOCUS_RELATIVE_CONTROL         0x07U
+#define VIDEO_CT_FOCUS_AUTO_CONTROL             0x08U
+#define VIDEO_CT_IRIS_ABSOLUTE_CONTROL          0x09U
+#define VIDEO_CT_IRIS_RELATIVE_CONTROL          0x0AU
+#define VIDEO_CT_ZOOM_ABSOLUTE_CONTROL          0x0BU
+#define VIDEO_CT_ZOOM_RELATIVE_CONTROL          0x0CU
+#define VIDEO_CT_PANTILT_ABSOLUTE_CONTROL       0x0DU
+#define VIDEO_CT_PANTILT_RELATIVE_CONTROL       0x0EU
+#define VIDEO_CT_ROLL_ABSOLUTE_CONTROL          0x0FU
+#define VIDEO_CT_ROLL_RELATIVE_CONTROL          0x10U
+#define VIDEO_CT_PRIVACY_CONTROL                0x11U
+#define VIDEO_CT_FOCUS_SIMPLE_CONTROL           0x12U
+#define VIDEO_CT_WINDOW_CONTROL                 0x13U
+#define VIDEO_CT_REGION_OF_INTEREST_CONTROL     0x14U
+
+/*! @brief Video device class-specific Processing Unit control selector */
+#define VIDEO_PU_CONTROL_UNDEFINED                      0x00U
+#define VIDEO_PU_BACKLIGHT_COMPENSATION_CONTROL         0x01U
+#define VIDEO_PU_BRIGHTNESS_CONTROL                     0x02U
+#define VIDEO_PU_CONTRAST_CONTROL                       0x03U
+#define VIDEO_PU_GAIN_CONTROL                           0x04U
+#define VIDEO_PU_POWER_LINE_FREQUENCY_CONTROL           0x05U
+#define VIDEO_PU_HUE_CONTROL                            0x06U
+#define VIDEO_PU_SATURATION_CONTROL                     0x07U
+#define VIDEO_PU_SHARPNESS_CONTROL                      0x08U
+#define VIDEO_PU_GAMMA_CONTROL                          0x09U
+#define VIDEO_PU_WHITE_BALANCE_TEMPERATURE_CONTROL      0x0AU
+#define VIDEO_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x0BU
+#define VIDEO_PU_WHITE_BALANCE_COMPONENT_CONTROL        0x0CU
+#define VIDEO_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL   0x0DU
+#define VIDEO_PU_DIGITAL_MULTIPLIER_CONTROL             0x0EU
+#define VIDEO_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL       0x0FU
+#define VIDEO_PU_HUE_AUTO_CONTROL                       0x10U
+#define VIDEO_PU_ANALOG_VIDEO_STANDARD_CONTROL          0x11U
+#define VIDEO_PU_ANALOG_LOCK_STATUS_CONTROL             0x12U
+#define VIDEO_PU_CONTRAST_AUTO_CONTROL                  0x13U
+
+/*! @brief Video device class-specific Encoding Unit control selector */
+#define VIDEO_EU_CONTROL_UNDEFINED           0x00U
+#define VIDEO_EU_SELECT_LAYER_CONTROL        0x01U
+#define VIDEO_EU_PROFILE_TOOLSET_CONTROL     0x02U
+#define VIDEO_EU_VIDEO_RESOLUTION_CONTROL    0x03U
+#define VIDEO_EU_MIN_FRAME_INTERVAL_CONTROL  0x04U
+#define VIDEO_EU_SLICE_MODE_CONTROL          0x05U
+#define VIDEO_EU_RATE_CONTROL_MODE_CONTROL   0x06U
+#define VIDEO_EU_AVERAGE_BITRATE_CONTROL     0x07U
+#define VIDEO_EU_CPB_SIZE_CONTROL            0x08U
+#define VIDEO_EU_PEAK_BIT_RATE_CONTROL       0x09U
+#define VIDEO_EU_QUANTIZATION_PARAMS_CONTROL 0x0AU
+#define VIDEO_EU_SYNC_REF_FRAME_CONTROL      0x0BU
+#define VIDEO_EU_LTR_BUFFER_                 CONTROL0x0CU
+#define VIDEO_EU_LTR_PICTURE_CONTROL         0x0DU
+#define VIDEO_EU_LTR_VALIDATION_CONTROL      0x0EU
+#define VIDEO_EU_LEVEL_IDC_LIMIT_CONTROL     0x0FU
+#define VIDEO_EU_SEI_PAYLOADTYPE_CONTROL     0x10U
+#define VIDEO_EU_QP_RANGE_CONTROL            0x11U
+#define VIDEO_EU_PRIORITY_CONTROL            0x12U
+#define VIDEO_EU_START_OR_STOP_LAYER_CONTROL 0x13U
+#define VIDEO_EU_ERROR_RESILIENCY_CONTROL    0x14U
+
+/*! @brief Video device class-specific Extension Unit control selector */
+#define VIDEO_XU_CONTROL_UNDEFINED 0x00U
+
+/*! @brief Video device class-specific VideoStreaming Interface control selector */
+#define VIDEO_VS_CONTROL_UNDEFINED            0x00U
+#define VIDEO_VS_PROBE_CONTROL                0x01U
+#define VIDEO_VS_COMMIT_CONTROL               0x02U
+#define VIDEO_VS_STILL_PROBE_CONTROL          0x03U
+#define VIDEO_VS_STILL_COMMIT_CONTROL         0x04U
+#define VIDEO_VS_STILL_IMAGE_TRIGGER_CONTROL  0x05U
+#define VIDEO_VS_STREAM_ERROR_CODE_CONTROL    0x06U
+#define VIDEO_VS_GENERATE_KEY_FRAME_CONTROL   0x07U
+#define VIDEO_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x08U
+#define VIDEO_VS_SYNCH_DELAY_CONTROL          0x09U
+
+/*! @}*/
+
+/*!
+ * @name USB Video class terminal types
+ * @{
+ */
+
+/*! @brief Video device USB terminal type */
+#define VIDEO_TT_VENDOR_SPECIFIC 0x0100U
+#define VIDEO_TT_STREAMING       0x0101U
+
+/*! @brief Video device input terminal type */
+#define VIDEO_ITT_VENDOR_SPECIFIC       0x0200U
+#define VIDEO_ITT_CAMERA                0x0201U
+#define VIDEO_ITT_MEDIA_TRANSPORT_INPUT 0x0202U
+
+/*! @brief Video device output terminal type */
+#define VIDEO_OTT_VENDOR_SPECIFIC        0x0300U
+#define VIDEO_OTT_DISPLAY                0x0301U
+#define VIDEO_OTT_MEDIA_TRANSPORT_OUTPUT 0x0302U
+
+/*! @brief Video device external terminal type */
+#define VIDEO_ET_VENDOR_SPECIFIC     0x0400U
+#define VIDEO_ET_COMPOSITE_CONNECTOR 0x0401U
+#define VIDEO_ET_SVIDEO_CONNECTOR    0x0402U
+#define VIDEO_ET_COMPONENT_CONNECTOR 0x0403U
+
+/*! @}*/
+
+/*!
+ * @name USB Video class setup request types
+ * @{
+ */
+
+/*! @brief Video device class setup request set type */
+#define VIDEO_SET_REQUEST_INTERFACE 0x21U
+#define VIDEO_SET_REQUEST_ENDPOINT  0x22U
+
+/*! @brief Video device class setup request get type */
+#define VIDEO_GET_REQUEST_INTERFACE 0xA1U
+#define VIDEO_GET_REQUEST_ENDPOINT  0xA2U
+
+/*! @}*/
+
+/*! @brief Video device still image trigger control */
+#define VIDEO_STILL_IMAGE_TRIGGER_NORMAL_OPERATION                            0x00U
+#define VIDEO_STILL_IMAGE_TRIGGER_TRANSMIT_STILL_IMAGE                        0x01U
+#define VIDEO_STILL_IMAGE_TRIGGER_TRANSMIT_STILL_IMAGE_VS_DEDICATED_BULK_PIPE 0x02U
+#define VIDEO_STILL_IMAGE_TRIGGER_ABORT_STILL_IMAGE_TRANSMISSION              0x03U
+
+/*!
+ * @name USB Video device class-specific request commands
+ * @{
+ */
+
+/*! @brief Video device class-specific request GET CUR COMMAND */
+#define VIDEO_GET_CUR_VC_POWER_MODE_CONTROL 0x8101U
+#define VIDEO_GET_CUR_VC_ERROR_CODE_CONTROL 0x8102U
+
+#define VIDEO_GET_CUR_PU_BACKLIGHT_COMPENSATION_CONTROL         0x8121U
+#define VIDEO_GET_CUR_PU_BRIGHTNESS_CONTROL                     0x8122U
+#define VIDEO_GET_CUR_PU_CONTRACT_CONTROL                       0x8123U
+#define VIDEO_GET_CUR_PU_GAIN_CONTROL                           0x8124U
+#define VIDEO_GET_CUR_PU_POWER_LINE_FREQUENCY_CONTROL           0x8125U
+#define VIDEO_GET_CUR_PU_HUE_CONTROL                            0x8126U
+#define VIDEO_GET_CUR_PU_SATURATION_CONTROL                     0x8127U
+#define VIDEO_GET_CUR_PU_SHARRNESS_CONTROL                      0x8128U
+#define VIDEO_GET_CUR_PU_GAMMA_CONTROL                          0x8129U
+#define VIDEO_GET_CUR_PU_WHITE_BALANCE_TEMPERATURE_CONTROL      0x812AU
+#define VIDEO_GET_CUR_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x812BU
+#define VIDEO_GET_CUR_PU_WHITE_BALANCE_COMPONENT_CONTROL        0x812CU
+#define VIDEO_GET_CUR_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL   0x812DU
+#define VIDEO_GET_CUR_PU_DIGITAL_MULTIPLIER_CONTROL             0x812EU
+#define VIDEO_GET_CUR_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL       0x812FU
+#define VIDEO_GET_CUR_PU_HUE_AUTO_CONTROL                       0x8130U
+#define VIDEO_GET_CUR_PU_ANALOG_VIDEO_STANDARD_CONTROL          0x8131U
+#define VIDEO_GET_CUR_PU_ANALOG_LOCK_STATUS_CONTROL             0x8132U
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_CUR_PU_CONTRAST_AUTO_CONTROL 0x8133U
+#endif
+
+#define VIDEO_GET_CUR_CT_SCANNING_MODE_CONTROL          0x8141U
+#define VIDEO_GET_CUR_CT_AE_MODE_CONTROL                0x8142U
+#define VIDEO_GET_CUR_CT_AE_PRIORITY_CONTROL            0x8143U
+#define VIDEO_GET_CUR_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x8144U
+#define VIDEO_GET_CUR_CT_EXPOSURE_TIME_RELATIVE_CONTROL 0x8145U
+#define VIDEO_GET_CUR_CT_FOCUS_ABSOLUTE_CONTROL         0x8146U
+#define VIDEO_GET_CUR_CT_FOCUS_RELATIVE_CONTROL         0x8147U
+#define VIDEO_GET_CUR_CT_FOCUS_AUTO_CONTROL             0x8148U
+#define VIDEO_GET_CUR_CT_IRIS_ABSOLUTE_CONTROL          0x8149U
+#define VIDEO_GET_CUR_CT_IRIS_RELATIVE_CONTROL          0x814AU
+#define VIDEO_GET_CUR_CT_ZOOM_ABSOLUTE_CONTROL          0x814BU
+#define VIDEO_GET_CUR_CT_ZOOM_RELATIVE_CONTROL          0x814CU
+#define VIDEO_GET_CUR_CT_PANTILT_ABSOLUTE_CONTROL       0x814DU
+#define VIDEO_GET_CUR_CT_PANTILT_RELATIVE_CONTROL       0x814EU
+#define VIDEO_GET_CUR_CT_ROLL_ABSOLUTE_CONTROL          0x814FU
+#define VIDEO_GET_CUR_CT_ROLL_RELATIVE_CONTROL          0x8150U
+#define VIDEO_GET_CUR_CT_PRIVACY_CONTROL                0x8151U
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_CUR_CT_FOCUS_SIMPLE_CONTROL       0x8152U
+#define VIDEO_GET_CUR_CT_DIGITAL_WINDOW_CONTROL     0x8153U
+#define VIDEO_GET_CUR_CT_REGION_OF_INTEREST_CONTROL 0x8154U
+#endif
+
+#define VIDEO_GET_CUR_VS_PROBE_CONTROL                0x8161U
+#define VIDEO_GET_CUR_VS_COMMIT_CONTROL               0x8162U
+#define VIDEO_GET_CUR_VS_STILL_PROBE_CONTROL          0x8163U
+#define VIDEO_GET_CUR_VS_STILL_COMMIT_CONTROL         0x8164U
+#define VIDEO_GET_CUR_VS_STILL_IMAGE_TRIGGER_CONTROL  0x8165U
+#define VIDEO_GET_CUR_VS_STREAM_ERROR_CODE_CONTROL    0x8166U
+#define VIDEO_GET_CUR_VS_GENERATE_KEY_FRAME_CONTROL   0x8167U
+#define VIDEO_GET_CUR_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x8168U
+#define VIDEO_GET_CUR_VS_SYNCH_DELAY_CONTROL          0x8169U
+
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_CUR_EU_SELECT_LAYER_CONTROL        0x8181U
+#define VIDEO_GET_CUR_EU_PROFILE_TOOLSET_CONTROL     0x8182U
+#define VIDEO_GET_CUR_EU_VIDEO_RESOLUTION_CONTROL    0x8183U
+#define VIDEO_GET_CUR_EU_MIN_FRAME_INTERVAL_CONTROL  0x8184U
+#define VIDEO_GET_CUR_EU_SLICE_MODE_CONTROL          0x8185U
+#define VIDEO_GET_CUR_EU_RATE_CONTROL_MODE_CONTROL   0x8186U
+#define VIDEO_GET_CUR_EU_AVERAGE_BITRATE_CONTROL     0x8187U
+#define VIDEO_GET_CUR_EU_CPB_SIZE_CONTROL            0x8188U
+#define VIDEO_GET_CUR_EU_PEAK_BIT_RATE_CONTROL       0x8189U
+#define VIDEO_GET_CUR_EU_QUANTIZATION_PARAMS_CONTROL 0x818AU
+#define VIDEO_GET_CUR_EU_SYNC_REF_FRAME_CONTROL      0x818BU
+#define VIDEO_GET_CUR_EU_LTR_BUFFER_CONTROL          0x818CU
+#define VIDEO_GET_CUR_EU_LTR_PICTURE_CONTROL         0x818DU
+#define VIDEO_GET_CUR_EU_LTR_VALIDATION_CONTROL      0x818EU
+#define VIDEO_GET_CUR_EU_LEVEL_IDC_LIMIT_CONTROL     0x818FU
+#define VIDEO_GET_CUR_EU_SEI_PAYLOADTYPE_CONTROL     0x8190U
+#define VIDEO_GET_CUR_EU_QP_RANGE_CONTROL            0x8191U
+#define VIDEO_GET_CUR_EU_PRIORITY_CONTROL            0x8192U
+#define VIDEO_GET_CUR_EU_START_OR_STOP_LAYER_CONTROL 0x8193U
+#define VIDEO_GET_CUR_EU_ERROR_RESILIENCY_CONTROL    0x8194U
+#endif
+
+/*! @brief Video device class-specific request GET MIN COMMAND */
+#define VIDEO_GET_MIN_PU_BACKLIGHT_COMPENSATION_CONTROL    0x8221U
+#define VIDEO_GET_MIN_PU_BRIGHTNESS_CONTROL                0x8222U
+#define VIDEO_GET_MIN_PU_CONTRACT_CONTROL                  0x8223U
+#define VIDEO_GET_MIN_PU_GAIN_CONTROL                      0x8224U
+#define VIDEO_GET_MIN_PU_HUE_CONTROL                       0x8226U
+#define VIDEO_GET_MIN_PU_SATURATION_CONTROL                0x8227U
+#define VIDEO_GET_MIN_PU_SHARRNESS_CONTROL                 0x8228U
+#define VIDEO_GET_MIN_PU_GAMMA_CONTROL                     0x8229U
+#define VIDEO_GET_MIN_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x822AU
+#define VIDEO_GET_MIN_PU_WHITE_BALANCE_COMPONENT_CONTROL   0x822CU
+#define VIDEO_GET_MIN_PU_DIGITAL_MULTIPLIER_CONTROL        0x822EU
+#define VIDEO_GET_MIN_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL  0x822FU
+
+#define VIDEO_GET_MIN_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x8244U
+#define VIDEO_GET_MIN_CT_FOCUS_ABSOLUTE_CONTROL         0x8246U
+#define VIDEO_GET_MIN_CT_FOCUS_RELATIVE_CONTROL         0x8247U
+#define VIDEO_GET_MIN_CT_IRIS_ABSOLUTE_CONTROL          0x8249U
+#define VIDEO_GET_MIN_CT_ZOOM_ABSOLUTE_CONTROL          0x824BU
+#define VIDEO_GET_MIN_CT_ZOOM_RELATIVE_CONTROL          0x824CU
+#define VIDEO_GET_MIN_CT_PANTILT_ABSOLUTE_CONTROL       0x824DU
+#define VIDEO_GET_MIN_CT_PANTILT_RELATIVE_CONTROL       0x824EU
+#define VIDEO_GET_MIN_CT_ROLL_ABSOLUTE_CONTROL          0x824FU
+#define VIDEO_GET_MIN_CT_ROLL_RELATIVE_CONTROL          0x8250U
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_MIN_CT_DIGITAL_WINDOW_CONTROL     0x8251U
+#define VIDEO_GET_MIN_CT_REGION_OF_INTEREST_CONTROL 0x8252U
+#endif
+
+#define VIDEO_GET_MIN_VS_PROBE_CONTROL                0x8261U
+#define VIDEO_GET_MIN_VS_STILL_PROBE_CONTROL          0x8263U
+#define VIDEO_GET_MIN_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x8268U
+#define VIDEO_GET_MIN_VS_SYNCH_DELAY_CONTROL          0x8269U
+
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_MIN_EU_VIDEO_RESOLUTION_CONTROL    0x8283U
+#define VIDEO_GET_MIN_EU_MIN_FRAME_INTERVAL_CONTROL  0x8284U
+#define VIDEO_GET_MIN_EU_SLICE_MODE_CONTROL          0x8285U
+#define VIDEO_GET_MIN_EU_AVERAGE_BITRATE_CONTROL     0x8287U
+#define VIDEO_GET_MIN_EU_CPB_SIZE_CONTROL            0x8288U
+#define VIDEO_GET_MIN_EU_PEAK_BIT_RATE_CONTROL       0x8289U
+#define VIDEO_GET_MIN_EU_QUANTIZATION_PARAMS_CONTROL 0x828AU
+#define VIDEO_GET_MIN_EU_SYNC_REF_FRAME_CONTROL      0x828BU
+#define VIDEO_GET_MIN_EU_LEVEL_IDC_LIMIT_CONTROL     0x828FU
+#define VIDEO_GET_MIN_EU_SEI_PAYLOADTYPE_CONTROL     0x8290U
+#define VIDEO_GET_MIN_EU_QP_RANGE_CONTROL            0x8291U
+#endif
+
+/*! @brief Video device class-specific request GET MAX COMMAND */
+#define VIDEO_GET_MAX_PU_BACKLIGHT_COMPENSATION_CONTROL    0x8321U
+#define VIDEO_GET_MAX_PU_BRIGHTNESS_CONTROL                0x8322U
+#define VIDEO_GET_MAX_PU_CONTRACT_CONTROL                  0x8323U
+#define VIDEO_GET_MAX_PU_GAIN_CONTROL                      0x8324U
+#define VIDEO_GET_MAX_PU_HUE_CONTROL                       0x8326U
+#define VIDEO_GET_MAX_PU_SATURATION_CONTROL                0x8327U
+#define VIDEO_GET_MAX_PU_SHARRNESS_CONTROL                 0x8328U
+#define VIDEO_GET_MAX_PU_GAMMA_CONTROL                     0x8329U
+#define VIDEO_GET_MAX_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x832AU
+#define VIDEO_GET_MAX_PU_WHITE_BALANCE_COMPONENT_CONTROL   0x832CU
+#define VIDEO_GET_MAX_PU_DIGITAL_MULTIPLIER_CONTROL        0x832EU
+#define VIDEO_GET_MAX_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL  0x832FU
+
+#define VIDEO_GET_MAX_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x8344U
+#define VIDEO_GET_MAX_CT_FOCUS_ABSOLUTE_CONTROL         0x8346U
+#define VIDEO_GET_MAX_CT_FOCUS_RELATIVE_CONTROL         0x8347U
+#define VIDEO_GET_MAX_CT_IRIS_ABSOLUTE_CONTROL          0x8349U
+#define VIDEO_GET_MAX_CT_ZOOM_ABSOLUTE_CONTROL          0x834BU
+#define VIDEO_GET_MAX_CT_ZOOM_RELATIVE_CONTROL          0x834CU
+#define VIDEO_GET_MAX_CT_PANTILT_ABSOLUTE_CONTROL       0x834DU
+#define VIDEO_GET_MAX_CT_PANTILT_RELATIVE_CONTROL       0x834EU
+#define VIDEO_GET_MAX_CT_ROLL_ABSOLUTE_CONTROL          0x834FU
+#define VIDEO_GET_MAX_CT_ROLL_RELATIVE_CONTROL          0x8350U
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_MAX_CT_DIGITAL_WINDOW_CONTROL     0x8351U
+#define VIDEO_GET_MAX_CT_REGION_OF_INTEREST_CONTROL 0x8352U
+#endif
+
+#define VIDEO_GET_MAX_VS_PROBE_CONTROL                0x8361U
+#define VIDEO_GET_MAX_VS_STILL_PROBE_CONTROL          0x8363U
+#define VIDEO_GET_MAX_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x8368U
+#define VIDEO_GET_MAX_VS_SYNCH_DELAY_CONTROL          0x8369U
+
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_MAX_EU_VIDEO_RESOLUTION_CONTROL    0x8383U
+#define VIDEO_GET_MAX_EU_MIN_FRAME_INTERVAL_CONTROL  0x8384U
+#define VIDEO_GET_MAX_EU_SLICE_MODE_CONTROL          0x8385U
+#define VIDEO_GET_MAX_EU_AVERAGE_BITRATE_CONTROL     0x8387U
+#define VIDEO_GET_MAX_EU_CPB_SIZE_CONTROL            0x8388U
+#define VIDEO_GET_MAX_EU_PEAK_BIT_RATE_CONTROL       0x8389U
+#define VIDEO_GET_MAX_EU_QUANTIZATION_PARAMS_CONTROL 0x838AU
+#define VIDEO_GET_MAX_EU_SYNC_REF_FRAME_CONTROL      0x838BU
+#define VIDEO_GET_MAX_EU_LTR_BUFFER_CONTROL          0x838CU
+#define VIDEO_GET_MAX_EU_LEVEL_IDC_LIMIT_CONTROL     0x838FU
+#define VIDEO_GET_MAX_EU_SEI_PAYLOADTYPE_CONTROL     0x8390U
+#define VIDEO_GET_MAX_EU_QP_RANGE_CONTROL            0x8391U
+#endif
+
+/*! @brief Video device class-specific request GET RES COMMAND */
+#define VIDEO_GET_RES_PU_BACKLIGHT_COMPENSATION_CONTROL    0x8421U
+#define VIDEO_GET_RES_PU_BRIGHTNESS_CONTROL                0x8422U
+#define VIDEO_GET_RES_PU_CONTRACT_CONTROL                  0x8423U
+#define VIDEO_GET_RES_PU_GAIN_CONTROL                      0x8424U
+#define VIDEO_GET_RES_PU_HUE_CONTROL                       0x8426U
+#define VIDEO_GET_RES_PU_SATURATION_CONTROL                0x8427U
+#define VIDEO_GET_RES_PU_SHARRNESS_CONTROL                 0x8428U
+#define VIDEO_GET_RES_PU_GAMMA_CONTROL                     0x8429U
+#define VIDEO_GET_RES_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x842AU
+#define VIDEO_GET_RES_PU_WHITE_BALANCE_COMPONENT_CONTROL   0x842CU
+#define VIDEO_GET_RES_PU_DIGITAL_MULTIPLIER_CONTROL        0x842EU
+#define VIDEO_GET_RES_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL  0x842FU
+
+#define VIDEO_GET_RES_CT_AE_MODE_CONTROL                0x8442U
+#define VIDEO_GET_RES_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x8444U
+#define VIDEO_GET_RES_CT_FOCUS_ABSOLUTE_CONTROL         0x8446U
+#define VIDEO_GET_RES_CT_FOCUS_RELATIVE_CONTROL         0x8447U
+#define VIDEO_GET_RES_CT_IRIS_ABSOLUTE_CONTROL          0x8449U
+#define VIDEO_GET_RES_CT_ZOOM_ABSOLUTE_CONTROL          0x844BU
+#define VIDEO_GET_RES_CT_ZOOM_RELATIVE_CONTROL          0x844CU
+#define VIDEO_GET_RES_CT_PANTILT_ABSOLUTE_CONTROL       0x844DU
+#define VIDEO_GET_RES_CT_PANTILT_RELATIVE_CONTROL       0x844EU
+#define VIDEO_GET_RES_CT_ROLL_ABSOLUTE_CONTROL          0x844FU
+#define VIDEO_GET_RES_CT_ROLL_RELATIVE_CONTROL          0x8450U
+
+#define VIDEO_GET_RES_VS_PROBE_CONTROL                0x8461U
+#define VIDEO_GET_RES_VS_STILL_PROBE_CONTROL          0x8463U
+#define VIDEO_GET_RES_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x8468U
+#define VIDEO_GET_RES_VS_SYNCH_DELAY_CONTROL          0x8469U
+
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_RES_EU_AVERAGE_BITRATE_CONTROL     0x8487U
+#define VIDEO_GET_RES_EU_CPB_SIZE_CONTROL            0x8488U
+#define VIDEO_GET_RES_EU_PEAK_BIT_RATE_CONTROL       0x8489U
+#define VIDEO_GET_RES_EU_QUANTIZATION_PARAMS_CONTROL 0x848AU
+#define VIDEO_GET_RES_EU_ERROR_RESILIENCY_CONTROL    0x8494U
+#endif
+
+/*! @brief Video device class-specific request GET LEN COMMAND */
+
+#define VIDEO_GET_LEN_VS_PROBE_CONTROL        0x8561U
+#define VIDEO_GET_LEN_VS_COMMIT_CONTROL       0x8562U
+#define VIDEO_GET_LEN_VS_STILL_PROBE_CONTROL  0x8563U
+#define VIDEO_GET_LEN_VS_STILL_COMMIT_CONTROL 0x8564U
+
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_LEN_EU_SELECT_LAYER_CONTROL        0x8581U
+#define VIDEO_GET_LEN_EU_PROFILE_TOOLSET_CONTROL     0x8582U
+#define VIDEO_GET_LEN_EU_VIDEO_RESOLUTION_CONTROL    0x8583U
+#define VIDEO_GET_LEN_EU_MIN_FRAME_INTERVAL_CONTROL  0x8584U
+#define VIDEO_GET_LEN_EU_SLICE_MODE_CONTROL          0x8585U
+#define VIDEO_GET_LEN_EU_RATE_CONTROL_MODE_CONTROL   0x8586U
+#define VIDEO_GET_LEN_EU_AVERAGE_BITRATE_CONTROL     0x8587U
+#define VIDEO_GET_LEN_EU_CPB_SIZE_CONTROL            0x8588U
+#define VIDEO_GET_LEN_EU_PEAK_BIT_RATE_CONTROL       0x8589U
+#define VIDEO_GET_LEN_EU_QUANTIZATION_PARAMS_CONTROL 0x858AU
+#define VIDEO_GET_LEN_EU_SYNC_REF_FRAME_CONTROL      0x858BU
+#define VIDEO_GET_LEN_EU_LTR_BUFFER_CONTROL          0x858CU
+#define VIDEO_GET_LEN_EU_LTR_PICTURE_CONTROL         0x858DU
+#define VIDEO_GET_LEN_EU_LTR_VALIDATION_CONTROL      0x858EU
+#define VIDEO_GET_LEN_EU_QP_RANGE_CONTROL            0x8591U
+#define VIDEO_GET_LEN_EU_PRIORITY_CONTROL            0x8592U
+#define VIDEO_GET_LEN_EU_START_OR_STOP_LAYER_CONTROL 0x8593U
+#endif
+
+/*! @brief Video device class-specific request GET INFO COMMAND */
+#define VIDEO_GET_INFO_VC_POWER_MODE_CONTROL 0x8601U
+#define VIDEO_GET_INFO_VC_ERROR_CODE_CONTROL 0x8602U
+
+#define VIDEO_GET_INFO_PU_BACKLIGHT_COMPENSATION_CONTROL         0x8621U
+#define VIDEO_GET_INFO_PU_BRIGHTNESS_CONTROL                     0x8622U
+#define VIDEO_GET_INFO_PU_CONTRACT_CONTROL                       0x8623U
+#define VIDEO_GET_INFO_PU_GAIN_CONTROL                           0x8624U
+#define VIDEO_GET_INFO_PU_POWER_LINE_FREQUENCY_CONTROL           0x8625U
+#define VIDEO_GET_INFO_PU_HUE_CONTROL                            0x8626U
+#define VIDEO_GET_INFO_PU_SATURATION_CONTROL                     0x8627U
+#define VIDEO_GET_INFO_PU_SHARRNESS_CONTROL                      0x8628U
+#define VIDEO_GET_INFO_PU_GAMMA_CONTROL                          0x8629U
+#define VIDEO_GET_INFO_PU_WHITE_BALANCE_TEMPERATURE_CONTROL      0x862AU
+#define VIDEO_GET_INFO_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x862BU
+#define VIDEO_GET_INFO_PU_WHITE_BALANCE_COMPONENT_CONTROL        0x862CU
+#define VIDEO_GET_INFO_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL   0x862DU
+#define VIDEO_GET_INFO_PU_DIGITAL_MULTIPLIER_CONTROL             0x862EU
+#define VIDEO_GET_INFO_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL       0x862FU
+#define VIDEO_GET_INFO_PU_HUE_AUTO_CONTROL                       0x8630U
+#define VIDEO_GET_INFO_PU_ANALOG_VIDEO_STANDARD_CONTROL          0x8631U
+#define VIDEO_GET_INFO_PU_ANALOG_LOCK_STATUS_CONTROL             0x8632U
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_INFO_PU_CONTRAST_AUTO_CONTROL 0x8633U
+#endif
+
+#define VIDEO_GET_INFO_CT_SCANNING_MODE_CONTROL          0x8641U
+#define VIDEO_GET_INFO_CT_AE_MODE_CONTROL                0x8642U
+#define VIDEO_GET_INFO_CT_AE_PRIORITY_CONTROL            0x8643U
+#define VIDEO_GET_INFO_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x8644U
+#define VIDEO_GET_INFO_CT_EXPOSURE_TIME_RELATIVE_CONTROL 0x8645U
+#define VIDEO_GET_INFO_CT_FOCUS_ABSOLUTE_CONTROL         0x8646U
+#define VIDEO_GET_INFO_CT_FOCUS_RELATIVE_CONTROL         0x8647U
+#define VIDEO_GET_INFO_CT_FOCUS_AUTO_CONTROL             0x8648U
+#define VIDEO_GET_INFO_CT_IRIS_ABSOLUTE_CONTROL          0x8649U
+#define VIDEO_GET_INFO_CT_IRIS_RELATIVE_CONTROL          0x864AU
+#define VIDEO_GET_INFO_CT_ZOOM_ABSOLUTE_CONTROL          0x864BU
+#define VIDEO_GET_INFO_CT_ZOOM_RELATIVE_CONTROL          0x864CU
+#define VIDEO_GET_INFO_CT_PANTILT_ABSOLUTE_CONTROL       0x864DU
+#define VIDEO_GET_INFO_CT_PANTILT_RELATIVE_CONTROL       0x864EU
+#define VIDEO_GET_INFO_CT_ROLL_ABSOLUTE_CONTROL          0x864FU
+#define VIDEO_GET_INFO_CT_ROLL_RELATIVE_CONTROL          0x8650U
+#define VIDEO_GET_INFO_CT_PRIVACY_CONTROL                0x8651U
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_INFO_CT_FOCUS_SIMPLE_CONTROL 0x8652U
+#endif
+
+#define VIDEO_GET_INFO_VS_PROBE_CONTROL                0x8661U
+#define VIDEO_GET_INFO_VS_COMMIT_CONTROL               0x8662U
+#define VIDEO_GET_INFO_VS_STILL_PROBE_CONTROL          0x8663U
+#define VIDEO_GET_INFO_VS_STILL_COMMIT_CONTROL         0x8664U
+#define VIDEO_GET_INFO_VS_STILL_IMAGE_TRIGGER_CONTROL  0x8665U
+#define VIDEO_GET_INFO_VS_STREAM_ERROR_CODE_CONTROL    0x8666U
+#define VIDEO_GET_INFO_VS_GENERATE_KEY_FRAME_CONTROL   0x8667U
+#define VIDEO_GET_INFO_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x8668U
+#define VIDEO_GET_INFO_VS_SYNCH_DELAY_CONTROL          0x8669U
+
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_INFO_EU_SELECT_LAYER_CONTROL        0x8681U
+#define VIDEO_GET_INFO_EU_PROFILE_TOOLSET_CONTROL     0x8682U
+#define VIDEO_GET_INFO_EU_VIDEO_RESOLUTION_CONTROL    0x8683U
+#define VIDEO_GET_INFO_EU_MIN_FRAME_INTERVAL_CONTROL  0x8684U
+#define VIDEO_GET_INFO_EU_SLICE_MODE_CONTROL          0x8685U
+#define VIDEO_GET_INFO_EU_RATE_CONTROL_MODE_CONTROL   0x8686U
+#define VIDEO_GET_INFO_EU_AVERAGE_BITRATE_CONTROL     0x8687U
+#define VIDEO_GET_INFO_EU_CPB_SIZE_CONTROL            0x8688U
+#define VIDEO_GET_INFO_EU_PEAK_BIT_RATE_CONTROL       0x8689U
+#define VIDEO_GET_INFO_EU_QUANTIZATION_PARAMS_CONTROL 0x868AU
+#define VIDEO_GET_INFO_EU_SYNC_REF_FRAME_CONTROL      0x868BU
+#define VIDEO_GET_INFO_EU_LTR_BUFFER_CONTROL          0x868CU
+#define VIDEO_GET_INFO_EU_LTR_PICTURE_CONTROL         0x868DU
+#define VIDEO_GET_INFO_EU_LTR_VALIDATION_CONTROL      0x868EU
+#define VIDEO_GET_INFO_EU_SEI_PAYLOADTYPE_CONTROL     0x8690U
+#define VIDEO_GET_INFO_EU_QP_RANGE_CONTROL            0x8691U
+#define VIDEO_GET_INFO_EU_PRIORITY_CONTROL            0x8692U
+#define VIDEO_GET_INFO_EU_START_OR_STOP_LAYER_CONTROL 0x8693U
+#endif
+
+/*! @brief Video device class-specific request GET DEF COMMAND */
+#define VIDEO_GET_DEF_PU_BACKLIGHT_COMPENSATION_CONTROL         0x8721U
+#define VIDEO_GET_DEF_PU_BRIGHTNESS_CONTROL                     0x8722U
+#define VIDEO_GET_DEF_PU_CONTRACT_CONTROL                       0x8723U
+#define VIDEO_GET_DEF_PU_GAIN_CONTROL                           0x8724U
+#define VIDEO_GET_DEF_PU_POWER_LINE_FREQUENCY_CONTROL           0x8725U
+#define VIDEO_GET_DEF_PU_HUE_CONTROL                            0x8726U
+#define VIDEO_GET_DEF_PU_SATURATION_CONTROL                     0x8727U
+#define VIDEO_GET_DEF_PU_SHARRNESS_CONTROL                      0x8728U
+#define VIDEO_GET_DEF_PU_GAMMA_CONTROL                          0x8729U
+#define VIDEO_GET_DEF_PU_WHITE_BALANCE_TEMPERATURE_CONTROL      0x872AU
+#define VIDEO_GET_DEF_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x872BU
+#define VIDEO_GET_DEF_PU_WHITE_BALANCE_COMPONENT_CONTROL        0x872CU
+#define VIDEO_GET_DEF_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL   0x872DU
+#define VIDEO_GET_DEF_PU_DIGITAL_MULTIPLIER_CONTROL             0x872EU
+#define VIDEO_GET_DEF_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL       0x872FU
+#define VIDEO_GET_DEF_PU_HUE_AUTO_CONTROL                       0x8730U
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_DEF_PU_CONTRAST_AUTO_CONTROL 0x8731U
+#endif
+
+#define VIDEO_GET_DEF_CT_AE_MODE_CONTROL                0x8742U
+#define VIDEO_GET_DEF_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x8744U
+#define VIDEO_GET_DEF_CT_FOCUS_ABSOLUTE_CONTROL         0x8746U
+#define VIDEO_GET_DEF_CT_FOCUS_RELATIVE_CONTROL         0x8747U
+#define VIDEO_GET_DEF_CT_FOCUS_AUTO_CONTROL             0x8748U
+#define VIDEO_GET_DEF_CT_IRIS_ABSOLUTE_CONTROL          0x8749U
+#define VIDEO_GET_DEF_CT_ZOOM_ABSOLUTE_CONTROL          0x874BU
+#define VIDEO_GET_DEF_CT_ZOOM_RELATIVE_CONTROL          0x874CU
+#define VIDEO_GET_DEF_CT_PANTILT_ABSOLUTE_CONTROL       0x874DU
+#define VIDEO_GET_DEF_CT_PANTILT_RELATIVE_CONTROL       0x874EU
+#define VIDEO_GET_DEF_CT_ROLL_ABSOLUTE_CONTROL          0x874FU
+#define VIDEO_GET_DEF_CT_ROLL_RELATIVE_CONTROL          0x8750U
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_DEF_CT_FOCUS_SIMPLE_CONTROL       0x8751U
+#define VIDEO_GET_DEF_CT_DIGITAL_WINDOW_CONTROL     0x8752U
+#define VIDEO_GET_DEF_CT_REGION_OF_INTEREST_CONTROL 0x8753U
+#endif
+
+#define VIDEO_GET_DEF_VS_PROBE_CONTROL                0x8761U
+#define VIDEO_GET_DEF_VS_STILL_PROBE_CONTROL          0x8763U
+#define VIDEO_GET_DEF_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x8768U
+#define VIDEO_GET_DEF_VS_SYNCH_DELAY_CONTROL          0x8769U
+
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_GET_DEF_EU_PROFILE_TOOLSET_CONTROL     0x8782U
+#define VIDEO_GET_DEF_EU_VIDEO_RESOLUTION_CONTROL    0x8783U
+#define VIDEO_GET_DEF_EU_MIN_FRAME_INTERVAL_CONTROL  0x8784U
+#define VIDEO_GET_DEF_EU_SLICE_MODE_CONTROL          0x8785U
+#define VIDEO_GET_DEF_EU_RATE_CONTROL_MODE_CONTROL   0x8786U
+#define VIDEO_GET_DEF_EU_AVERAGE_BITRATE_CONTROL     0x8787U
+#define VIDEO_GET_DEF_EU_CPB_SIZE_CONTROL            0x8788U
+#define VIDEO_GET_DEF_EU_PEAK_BIT_RATE_CONTROL       0x8789U
+#define VIDEO_GET_DEF_EU_QUANTIZATION_PARAMS_CONTROL 0x878AU
+#define VIDEO_GET_DEF_EU_LTR_BUFFER_CONTROL          0x878CU
+#define VIDEO_GET_DEF_EU_LTR_PICTURE_CONTROL         0x878DU
+#define VIDEO_GET_DEF_EU_LTR_VALIDATION_CONTROL      0x878EU
+#define VIDEO_GET_DEF_EU_LEVEL_IDC_LIMIT_CONTROL     0x878FU
+#define VIDEO_GET_DEF_EU_SEI_PAYLOADTYPE_CONTROL     0x8790U
+#define VIDEO_GET_DEF_EU_QP_RANGE_CONTROL            0x8791U
+#define VIDEO_GET_DEF_EU_ERROR_RESILIENCY_CONTROL    0x8794U
+#endif
+
+/*! @brief Video device class-specific request SET CUR COMMAND */
+#define VIDEO_SET_CUR_VC_POWER_MODE_CONTROL 0x0101U
+
+#define VIDEO_SET_CUR_PU_BACKLIGHT_COMPENSATION_CONTROL         0x0121U
+#define VIDEO_SET_CUR_PU_BRIGHTNESS_CONTROL                     0x0122U
+#define VIDEO_SET_CUR_PU_CONTRACT_CONTROL                       0x0123U
+#define VIDEO_SET_CUR_PU_GAIN_CONTROL                           0x0124U
+#define VIDEO_SET_CUR_PU_POWER_LINE_FREQUENCY_CONTROL           0x0125U
+#define VIDEO_SET_CUR_PU_HUE_CONTROL                            0x0126U
+#define VIDEO_SET_CUR_PU_SATURATION_CONTROL                     0x0127U
+#define VIDEO_SET_CUR_PU_SHARRNESS_CONTROL                      0x0128U
+#define VIDEO_SET_CUR_PU_GAMMA_CONTROL                          0x0129U
+#define VIDEO_SET_CUR_PU_WHITE_BALANCE_TEMPERATURE_CONTROL      0x012AU
+#define VIDEO_SET_CUR_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x012BU
+#define VIDEO_SET_CUR_PU_WHITE_BALANCE_COMPONENT_CONTROL        0x012CU
+#define VIDEO_SET_CUR_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL   0x012DU
+#define VIDEO_SET_CUR_PU_DIGITAL_MULTIPLIER_CONTROL             0x012EU
+#define VIDEO_SET_CUR_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL       0x012FU
+#define VIDEO_SET_CUR_PU_HUE_AUTO_CONTROL                       0x0130U
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_SET_CUR_PU_CONTRAST_AUTO_CONTROL 0x0131U
+#endif
+
+#define VIDEO_SET_CUR_CT_SCANNING_MODE_CONTROL          0x0141U
+#define VIDEO_SET_CUR_CT_AE_MODE_CONTROL                0x0142U
+#define VIDEO_SET_CUR_CT_AE_PRIORITY_CONTROL            0x0143U
+#define VIDEO_SET_CUR_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x0144U
+#define VIDEO_SET_CUR_CT_EXPOSURE_TIME_RELATIVE_CONTROL 0x0145U
+#define VIDEO_SET_CUR_CT_FOCUS_ABSOLUTE_CONTROL         0x0146U
+#define VIDEO_SET_CUR_CT_FOCUS_RELATIVE_CONTROL         0x0147U
+#define VIDEO_SET_CUR_CT_FOCUS_AUTO_CONTROL             0x0148U
+#define VIDEO_SET_CUR_CT_IRIS_ABSOLUTE_CONTROL          0x0149U
+#define VIDEO_SET_CUR_CT_IRIS_RELATIVE_CONTROL          0x014AU
+#define VIDEO_SET_CUR_CT_ZOOM_ABSOLUTE_CONTROL          0x014BU
+#define VIDEO_SET_CUR_CT_ZOOM_RELATIVE_CONTROL          0x014CU
+#define VIDEO_SET_CUR_CT_PANTILT_ABSOLUTE_CONTROL       0x014DU
+#define VIDEO_SET_CUR_CT_PANTILT_RELATIVE_CONTROL       0x014EU
+#define VIDEO_SET_CUR_CT_ROLL_ABSOLUTE_CONTROL          0x014FU
+#define VIDEO_SET_CUR_CT_ROLL_RELATIVE_CONTROL          0x0150U
+#define VIDEO_SET_CUR_CT_PRIVACY_CONTROL                0x0151U
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_SET_CUR_CT_FOCUS_SIMPLE_CONTROL       0x0152U
+#define VIDEO_SET_CUR_CT_DIGITAL_WINDOW_CONTROL     0x0153U
+#define VIDEO_SET_CUR_CT_REGION_OF_INTEREST_CONTROL 0x0154U
+#endif
+
+#define VIDEO_SET_CUR_VS_PROBE_CONTROL                0x0161U
+#define VIDEO_SET_CUR_VS_COMMIT_CONTROL               0x0162U
+#define VIDEO_SET_CUR_VS_STILL_PROBE_CONTROL          0x0163U
+#define VIDEO_SET_CUR_VS_STILL_COMMIT_CONTROL         0x0164U
+#define VIDEO_SET_CUR_VS_STILL_IMAGE_TRIGGER_CONTROL  0x0165U
+#define VIDEO_SET_CUR_VS_STREAM_ERROR_CODE_CONTROL    0x0166U
+#define VIDEO_SET_CUR_VS_GENERATE_KEY_FRAME_CONTROL   0x0167U
+#define VIDEO_SET_CUR_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x0168U
+#define VIDEO_SET_CUR_VS_SYNCH_DELAY_CONTROL          0x0169U
+
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+#define VIDEO_SET_CUR_EU_SELECT_LAYER_CONTROL        0x0181U
+#define VIDEO_SET_CUR_EU_PROFILE_TOOLSET_CONTROL     0x0182U
+#define VIDEO_SET_CUR_EU_VIDEO_RESOLUTION_CONTROL    0x0183U
+#define VIDEO_SET_CUR_EU_MIN_FRAME_INTERVAL_CONTROL  0x0184U
+#define VIDEO_SET_CUR_EU_SLICE_MODE_CONTROL          0x0185U
+#define VIDEO_SET_CUR_EU_RATE_CONTROL_MODE_CONTROL   0x0186U
+#define VIDEO_SET_CUR_EU_AVERAGE_BITRATE_CONTROL     0x0187U
+#define VIDEO_SET_CUR_EU_CPB_SIZE_CONTROL            0x0188U
+#define VIDEO_SET_CUR_EU_PEAK_BIT_RATE_CONTROL       0x0189U
+#define VIDEO_SET_CUR_EU_QUANTIZATION_PARAMS_CONTROL 0x018AU
+#define VIDEO_SET_CUR_EU_SYNC_REF_FRAME_CONTROL      0x018BU
+#define VIDEO_SET_CUR_EU_LTR_BUFFER_CONTROL          0x018CU
+#define VIDEO_SET_CUR_EU_LTR_PICTURE_CONTROL         0x018DU
+#define VIDEO_SET_CUR_EU_LTR_VALIDATION_CONTROL      0x018EU
+#define VIDEO_SET_CUR_EU_LEVEL_IDC_LIMIT_CONTROL     0x018FU
+#define VIDEO_SET_CUR_EU_SEI_PAYLOADTYPE_CONTROL     0x0190U
+#define VIDEO_SET_CUR_EU_QP_RANGE_CONTROL            0x0191U
+#define VIDEO_SET_CUR_EU_PRIORITY_CONTROL            0x0192U
+#define VIDEO_SET_CUR_EU_START_OR_STOP_LAYER_CONTROL 0x0193U
+#define VIDEO_SET_CUR_EU_ERROR_RESILIENCY_CONTROL    0x0194U
+#endif
+
+/*! @brief The payload header structure for MJPEG payload format. */
+struct video_mjpeg_payload_header {
+    uint8_t bHeaderLength; /*!< The payload header length. */
+    union {
+        uint8_t bmheaderInfo; /*!< The payload header bitmap field. */
+        struct
+        {
+            uint8_t frameIdentifier : 1U; /*!< Frame Identifier. This bit toggles at each frame start boundary and stays
+                                             constant for the rest of the frame.*/
+            uint8_t endOfFrame      : 1U; /*!< End of Frame. This bit indicates the end of a video frame and is set in the
+                                        last video sample that belongs to a frame.*/
+            uint8_t
+                presentationTimeStamp    : 1U; /*!< Presentation Time Stamp. This bit, when set, indicates the presence of
+                                               a PTS field.*/
+            uint8_t sourceClockReference : 1U; /*!< Source Clock Reference. This bit, when set, indicates the presence
+                                                  of a SCR field.*/
+            uint8_t reserved             : 1U; /*!< Reserved. Set to 0. */
+            uint8_t stillImage           : 1U; /*!< Still Image. This bit, when set, identifies a video sample that belongs to a
+                                         still image.*/
+            uint8_t errorBit             : 1U; /*!< Error Bit. This bit, when set, indicates an error in the device streaming.*/
+            uint8_t endOfHeader          : 1U; /*!< End of Header. This bit, when set, indicates the end of the BFH fields.*/
+        } headerInfoBits;
+        struct
+        {
+            uint8_t FID : 1U; /*!< Frame Identifier. This bit toggles at each frame start boundary and stays constant
+                                 for the rest of the frame.*/
+            uint8_t EOI : 1U; /*!< End of Frame. This bit indicates the end of a video frame and is set in the last
+                                 video sample that belongs to a frame.*/
+            uint8_t PTS : 1U; /*!< Presentation Time Stamp. This bit, when set, indicates the presence of a PTS field.*/
+            uint8_t SCR : 1U; /*!< Source Clock Reference. This bit, when set, indicates the presence of a SCR field.*/
+            uint8_t RES : 1U; /*!< Reserved. Set to 0. */
+            uint8_t STI : 1U; /*!< Still Image. This bit, when set, identifies a video sample that belongs to a still
+                                 image.*/
+            uint8_t ERR : 1U; /*!< Error Bit. This bit, when set, indicates an error in the device streaming.*/
+            uint8_t EOH : 1U; /*!< End of Header. This bit, when set, indicates the end of the BFH fields.*/
+        } headerInfoBitmap;
+    } headerInfoUnion;
+    uint32_t dwPresentationTime;      /*!< Presentation time stamp (PTS) field.*/
+    uint8_t bSourceClockReference[6]; /*!< Source clock reference (SCR) field.*/
+} __packed;
+
+/*! @brief The Video probe and commit controls structure.*/
+struct video_probe_and_commit_controls {
+    union {
+        uint8_t bmHint; /*!< Bit-field control indicating to the function what fields shall be kept fixed. */
+        struct
+        {
+            uint8_t dwFrameInterval : 1U; /*!< dwFrameInterval field.*/
+            uint8_t wKeyFrameRate   : 1U; /*!< wKeyFrameRate field.*/
+            uint8_t wPFrameRate     : 1U; /*!< wPFrameRate field.*/
+            uint8_t wCompQuality    : 1U; /*!< wCompQuality field.*/
+            uint8_t wCompWindowSize : 1U; /*!< wCompWindowSize field.*/
+            uint8_t reserved        : 3U; /*!< Reserved field.*/
+        } hintBitmap;
+    } hintUnion;
+    union {
+        uint8_t bmHint; /*!< Bit-field control indicating to the function what fields shall be kept fixed. */
+        struct
+        {
+            uint8_t reserved : 8U; /*!< Reserved field.*/
+        } hintBitmap;
+    } hintUnion1;
+    uint8_t bFormatIndex;              /*!< Video format index from a format descriptor.*/
+    uint8_t bFrameIndex;               /*!< Video frame index from a frame descriptor.*/
+    uint32_t dwFrameInterval;          /*!< Frame interval in 100ns units.*/
+    uint16_t wKeyFrameRate;            /*!< Key frame rate in key-frame per video-frame units.*/
+    uint16_t wPFrameRate;              /*!< PFrame rate in PFrame/key frame units.*/
+    uint16_t wCompQuality;             /*!< Compression quality control in abstract units 0U (lowest) to 10000U (highest).*/
+    uint16_t wCompWindowSize;          /*!< Window size for average bit rate control.*/
+    uint16_t wDelay;                   /*!< Internal video streaming interface latency in ms from video data capture to presentation on
+                        the USB.*/
+    uint32_t dwMaxVideoFrameSize;      /*!< Maximum video frame or codec-specific segment size in bytes.*/
+    uint32_t dwMaxPayloadTransferSize; /*!< Specifies the maximum number of bytes that the device can transmit or
+                                          receive in a single payload transfer.*/
+    uint32_t dwClockFrequency;         /*!< The device clock frequency in Hz for the specified format. This specifies the
+                                  units used for the time information fields in the Video Payload Headers in the data
+                                  stream.*/
+    uint8_t bmFramingInfo;             /*!< Bit-field control supporting the following values: D0 Frame ID, D1 EOF.*/
+    uint8_t bPreferedVersion;          /*!< The preferred payload format version supported by the host or device for the
+                                  specified bFormatIndex value.*/
+    uint8_t bMinVersion;               /*!< The minimum payload format version supported by the device for the specified bFormatIndex
+                            value.*/
+    uint8_t bMaxVersion;               /*!< The maximum payload format version supported by the device for the specified bFormatIndex
+                            value.*/
+#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5
+    uint8_t bUsage; /*!< This bitmap enables features reported by the bmUsages field of the Video Frame Descriptor.*/
+    uint8_t
+        bBitDepthLuma;                  /*!< Represents bit_depth_luma_minus8 + 8U, which must be the same as bit_depth_chroma_minus8 +
+                           8.*/
+    uint8_t bmSettings;                 /*!< A bitmap of flags that is used to discover and control specific features of a temporally
+                           encoded video stream.*/
+    uint8_t bMaxNumberOfRefFramesPlus1; /*!< Host indicates the maximum number of frames stored for use as references.*/
+    uint16_t bmRateControlModes;        /*!< This field contains 4U sub-fields, each of which is a 4U bit number.*/
+    uint64_t bmLayoutPerStream;         /*!< This field contains 4U sub-fields, each of which is a 2U byte number.*/
+#endif
+} __packed;
+
+/*! @brief The Video still probe and still commit controls structure.*/
+struct video_still_probe_and_commit_controls {
+    uint8_t bFormatIndex;              /*!< Video format index from a format descriptor.*/
+    uint8_t bFrameIndex;               /*!< Video frame index from a frame descriptor.*/
+    uint8_t bCompressionIndex;         /*!< Compression index from a frame descriptor.*/
+    uint32_t dwMaxVideoFrameSize;      /*!< Maximum still image size in bytes.*/
+    uint32_t dwMaxPayloadTransferSize; /*!< Specifies the maximum number of bytes that the device can transmit or
+                                          receive in a single payload transfer.*/
+} __packed;
+
+void usbd_video_sof_callback(void);
+void usbd_video_set_interface_callback(uint8_t value);
+void usbd_video_add_interface(usbd_class_t *class, usbd_interface_t *intf);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USB_VIDEO_H_ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/webusb/usbd_webusb.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/webusb/usbd_webusb.h
new file mode 100644
index 00000000..d94d1702
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/webusb/usbd_webusb.h
@@ -0,0 +1,22 @@
+#ifndef _USBD_WEBUSB_H
+#define _USBD_WEBUSB_H
+
+/* WebUSB Descriptor Types */
+#define WEBUSB_DESCRIPTOR_SET_HEADER_TYPE       0x00
+#define WEBUSB_CONFIGURATION_SUBSET_HEADER_TYPE 0x01
+#define WEBUSB_FUNCTION_SUBSET_HEADER_TYPE      0x02
+#define WEBUSB_URL_TYPE                         0x03
+
+/* WebUSB Request Codes */
+#define WEBUSB_REQUEST_GET_URL 0x02
+
+/* bScheme in URL descriptor */
+#define WEBUSB_URL_SCHEME_HTTP  0x00
+#define WEBUSB_URL_SCHEME_HTTPS 0x01
+
+/* WebUSB Descriptor sizes */
+#define WEBUSB_DESCRIPTOR_SET_HEADER_SIZE       5
+#define WEBUSB_CONFIGURATION_SUBSET_HEADER_SIZE 4
+#define WEBUSB_FUNCTION_SUBSET_HEADER_SIZE      3
+
+#endif
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/winusb/usbd_winusb.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/winusb/usbd_winusb.h
new file mode 100644
index 00000000..dc4a51dd
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/class/winusb/usbd_winusb.h
@@ -0,0 +1,26 @@
+#ifndef _USBD_WINUSB_H
+#define _USBD_WINUSB_H
+
+/* WinUSB Microsoft OS 2.0 descriptor request codes */
+#define WINUSB_REQUEST_GET_DESCRIPTOR_SET 0x07
+#define WINUSB_REQUEST_SET_ALT_ENUM       0x08
+
+/* WinUSB Microsoft OS 2.0 descriptor sizes */
+#define WINUSB_DESCRIPTOR_SET_HEADER_SIZE  10
+#define WINUSB_FUNCTION_SUBSET_HEADER_SIZE 8
+#define WINUSB_FEATURE_COMPATIBLE_ID_SIZE  20
+
+/* WinUSB Microsoft OS 2.0 Descriptor Types */
+#define WINUSB_SET_HEADER_DESCRIPTOR_TYPE       0x00
+#define WINUSB_SUBSET_HEADER_CONFIGURATION_TYPE 0x01
+#define WINUSB_SUBSET_HEADER_FUNCTION_TYPE      0x02
+#define WINUSB_FEATURE_COMPATIBLE_ID_TYPE       0x03
+#define WINUSB_FEATURE_REG_PROPERTY_TYPE        0x04
+#define WINUSB_FEATURE_MIN_RESUME_TIME_TYPE     0x05
+#define WINUSB_FEATURE_MODEL_ID_TYPE            0x06
+#define WINUSB_FEATURE_CCGP_DEVICE_TYPE         0x07
+
+#define WINUSB_PROP_DATA_TYPE_REG_SZ       0x01
+#define WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ 0x07
+
+#endif
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/common/usb_dc.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/common/usb_dc.h
new file mode 100644
index 00000000..bb838382
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/common/usb_dc.h
@@ -0,0 +1,197 @@
+#ifndef _USB_DC_H
+#define _USB_DC_H
+
+#include "stdint.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * USB endpoint direction and number.
+ */
+#define USB_EP_DIR_MASK 0x80U
+#define USB_EP_DIR_IN   0x80U
+#define USB_EP_DIR_OUT  0x00U
+
+/** Get endpoint index (number) from endpoint address */
+#define USB_EP_GET_IDX(ep) ((ep) & ~USB_EP_DIR_MASK)
+/** Get direction from endpoint address */
+#define USB_EP_GET_DIR(ep) ((ep)&USB_EP_DIR_MASK)
+/** Get endpoint address from endpoint index and direction */
+#define USB_EP_GET_ADDR(idx, dir) ((idx) | ((dir)&USB_EP_DIR_MASK))
+/** True if the endpoint is an IN endpoint */
+#define USB_EP_DIR_IS_IN(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_IN)
+/** True if the endpoint is an OUT endpoint */
+#define USB_EP_DIR_IS_OUT(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_OUT)
+
+/**
+ * USB endpoint Transfer Type mask.
+ */
+#define USBD_EP_TYPE_CTRL 0
+#define USBD_EP_TYPE_ISOC 1
+#define USBD_EP_TYPE_BULK 2
+#define USBD_EP_TYPE_INTR 3
+#define USBD_EP_TYPE_MASK 3
+
+/* Default USB control EP, always 0 and 0x80 */
+#define USB_CONTROL_OUT_EP0 0
+#define USB_CONTROL_IN_EP0  0x80
+
+/**
+ * @brief USB Device Controller API
+ * @defgroup _usb_device_controller_api USB Device Controller API
+ * @{
+ */
+/**< maximum packet size (MPS) for EP 0 */
+#define USB_CTRL_EP_MPS 64
+
+/**
+ * @brief USB Endpoint Transfer Type
+ */
+enum usb_dc_ep_transfer_type {
+    /** Control type endpoint */
+    USB_DC_EP_CONTROL = 0,
+    /** Isochronous type endpoint */
+    USB_DC_EP_ISOCHRONOUS,
+    /** Bulk type endpoint */
+    USB_DC_EP_BULK,
+    /** Interrupt type endpoint  */
+    USB_DC_EP_INTERRUPT
+};
+
+/**
+ * @brief USB Endpoint Configuration.
+ *
+ * Structure containing the USB endpoint configuration.
+ */
+struct usbd_endpoint_cfg {
+    /** The number associated with the EP in the device
+     *  configuration structure
+     *       IN  EP = 0x80 | \
+     *       OUT EP = 0x00 | \
+     */
+    uint8_t ep_addr;
+    /** Endpoint max packet size */
+    uint16_t ep_mps;
+    /** Endpoint Transfer Type.
+     * May be Bulk, Interrupt, Control or Isochronous
+     */
+    enum usb_dc_ep_transfer_type ep_type;
+};
+
+/**
+ * @brief USB Device Core Layer API
+ * @defgroup _usb_device_core_api USB Device Core API
+ * @{
+ */
+
+/**
+ * @brief Set USB device address
+ *
+ * @param[in] addr Device address
+ *
+ * @return 0 on success, negative errno code on fail.
+ */
+int usbd_set_address(const uint8_t addr);
+
+/*
+ * @brief configure and enable endpoint
+ *
+ * This function sets endpoint configuration according to one specified in USB
+ * endpoint descriptor and then enables it for data transfers.
+ *
+ * @param [in]  ep_desc Endpoint descriptor byte array
+ *
+ * @return true if successfully configured and enabled
+ */
+int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg);
+/**
+ * @brief Disable the selected endpoint
+ *
+ * Function to disable the selected endpoint. Upon success interrupts are
+ * disabled for the corresponding endpoint and the endpoint is no longer able
+ * for transmitting/receiving data.
+ *
+ * @param[in] ep Endpoint address corresponding to the one
+ *               listed in the device configuration table
+ *
+ * @return 0 on success, negative errno code on fail.
+ */
+int usbd_ep_close(const uint8_t ep);
+/**
+ * @brief Set stall condition for the selected endpoint
+ *
+ * @param[in] ep Endpoint address corresponding to the one
+ *               listed in the device configuration table
+ *
+ * @return 0 on success, negative errno code on fail.
+ */
+int usbd_ep_set_stall(const uint8_t ep);
+/**
+ * @brief Clear stall condition for the selected endpoint
+ *
+ * @param[in] ep Endpoint address corresponding to the one
+ *               listed in the device configuration table
+ *
+ * @return 0 on success, negative errno code on fail.
+ */
+int usbd_ep_clear_stall(const uint8_t ep);
+/**
+ * @brief Check if the selected endpoint is stalled
+ *
+ * @param[in]  ep       Endpoint address corresponding to the one
+ *                      listed in the device configuration table
+ * @param[out] stalled  Endpoint stall status
+ *
+ * @return 0 on success, negative errno code on fail.
+ */
+int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled);
+/**
+ * @brief Write data to the specified endpoint
+ *
+ * This function is called to write data to the specified endpoint. The
+ * supplied usbd_endpoint_callback function will be called when data is transmitted
+ * out.
+ *
+ * @param[in]  ep        Endpoint address corresponding to the one
+ *                       listed in the device configuration table
+ * @param[in]  data      Pointer to data to write
+ * @param[in]  data_len  Length of the data requested to write. This may
+ *                       be zero for a zero length status packet.
+ * @param[out] ret_bytes Bytes scheduled for transmission. This value
+ *                       may be NULL if the application expects all
+ *                       bytes to be written
+ *
+ * @return 0 on success, negative errno code on fail.
+ */
+int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes);
+/**
+ * @brief Read data from the specified endpoint
+ *
+ * This is similar to usb_dc_ep_read, the difference being that, it doesn't
+ * clear the endpoint NAKs so that the consumer is not bogged down by further
+ * upcalls till he is done with the processing of the data. The caller should
+ * reactivate ep by setting max_data_len 0 do so.
+ *
+ * @param[in]  ep           Endpoint address corresponding to the one
+ *                          listed in the device configuration table
+ * @param[in]  data         Pointer to data buffer to write to
+ * @param[in]  max_data_len Max length of data to read
+ * @param[out] read_bytes   Number of bytes read. If data is NULL and
+ *                          max_data_len is 0 the number of bytes
+ *                          available for read should be returned.
+ *
+ * @return 0 on success, negative errno code on fail.
+ */
+int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t max_data_len, uint32_t *read_bytes);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/common/usb_def.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/common/usb_def.h
new file mode 100644
index 00000000..57903f6b
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/common/usb_def.h
@@ -0,0 +1,566 @@
+#ifndef USB_REQUEST_H
+#define USB_REQUEST_H
+
+/* Useful define */
+#define USB_1_1 0x0110
+#define USB_2_0 0x0200
+/* Set USB version to 2.1 so that the host will request the BOS descriptor */
+#define USB_2_1 0x0210
+
+// USB Speed
+#define USB_SPEED_LOW  0U
+#define USB_SPEED_FULL 1U
+#define USB_SPEED_HIGH 2U
+
+// USB PID Types
+#define USB_PID_RESERVED 0U
+#define USB_PID_OUT      1U
+#define USB_PID_ACK      2U
+#define USB_PID_DATA0    3U
+#define USB_PID_PING     4U
+#define USB_PID_SOF      5U
+#define USB_PID_DATA2    7U
+#define USB_PID_NYET     6U
+#define USB_PID_SPLIT    8U
+#define USB_PID_IN       9U
+#define USB_PID_NAK      10U
+#define USB_PID_DATA1    11U
+#define USB_PID_PRE      12U
+#define USB_PID_ERR      12U
+#define USB_PID_SETUP    13U
+#define USB_PID_STALL    14U
+#define USB_PID_MDATA    15U
+
+// bmRequestType.Dir
+#define USB_REQUEST_HOST_TO_DEVICE 0U
+#define USB_REQUEST_DEVICE_TO_HOST 1U
+
+// bmRequestType.Type
+#define USB_REQUEST_STANDARD 0U
+#define USB_REQUEST_CLASS    1U
+#define USB_REQUEST_VENDOR   2U
+#define USB_REQUEST_RESERVED 3U
+
+// bmRequestType.Recipient
+#define USB_REQUEST_TO_DEVICE    0U
+#define USB_REQUEST_TO_INTERFACE 1U
+#define USB_REQUEST_TO_ENDPOINT  2U
+#define USB_REQUEST_TO_OTHER     3U
+
+/* USB Standard Request Codes */
+#define USB_REQUEST_GET_STATUS          0x00
+#define USB_REQUEST_CLEAR_FEATURE       0x01
+#define USB_REQUEST_SET_FEATURE         0x03
+#define USB_REQUEST_SET_ADDRESS         0x05
+#define USB_REQUEST_GET_DESCRIPTOR      0x06
+#define USB_REQUEST_SET_DESCRIPTOR      0x07
+#define USB_REQUEST_GET_CONFIGURATION   0x08
+#define USB_REQUEST_SET_CONFIGURATION   0x09
+#define USB_REQUEST_GET_INTERFACE       0x0A
+#define USB_REQUEST_SET_INTERFACE       0x0B
+#define USB_REQUEST_SYNCH_FRAME         0x0C
+#define USB_REQUEST_SET_ENCRYPTION      0x0D
+#define USB_REQUEST_GET_ENCRYPTION      0x0E
+#define USB_REQUEST_RPIPE_ABORT         0x0E
+#define USB_REQUEST_SET_HANDSHAKE       0x0F
+#define USB_REQUEST_RPIPE_RESET         0x0F
+#define USB_REQUEST_GET_HANDSHAKE       0x10
+#define USB_REQUEST_SET_CONNECTION      0x11
+#define USB_REQUEST_SET_SECURITY_DATA   0x12
+#define USB_REQUEST_GET_SECURITY_DATA   0x13
+#define USB_REQUEST_SET_WUSB_DATA       0x14
+#define USB_REQUEST_LOOPBACK_DATA_WRITE 0x15
+#define USB_REQUEST_LOOPBACK_DATA_READ  0x16
+#define USB_REQUEST_SET_INTERFACE_DS    0x17
+
+/* USB GET_STATUS Bit Values */
+#define USB_GETSTATUS_SELF_POWERED   0x01
+#define USB_GETSTATUS_REMOTE_WAKEUP  0x02
+#define USB_GETSTATUS_ENDPOINT_STALL 0x01
+
+/* USB Standard Feature selectors */
+#define USB_FEATURE_ENDPOINT_STALL 0
+#define USB_FEATURE_REMOTE_WAKEUP  1
+#define USB_FEATURE_TEST_MODE      2
+
+/* Descriptor size in bytes */
+#define USB_DEVICE_DESC_SIZE          0x12
+#define USB_CONFIGURATION_DESC_SIZE   0x09
+#define USB_INTERFACE_DESC_SIZE       0x09
+#define USB_ENDPOINT_DESC_SIZE        0x07
+#define USB_LANGID_STRING_DESC_SIZE   0x04
+#define USB_OTHER_SPEED_DESC_SIZE     0x09
+#define USB_DEVICE_QUAL_DESC_SIZE     0x0A
+#define USB_INTERFACE_ASSOC_DESC_SIZE 0x08
+#define USB_FUNCTION_DESC_SIZE        0x03
+#define USB_OTG_DESC_SIZE             0x03
+
+/* USB Descriptor Types */
+#define USB_DESCRIPTOR_TYPE_DEVICE                0x01U
+#define USB_DESCRIPTOR_TYPE_CONFIGURATION         0x02U
+#define USB_DESCRIPTOR_TYPE_STRING                0x03U
+#define USB_DESCRIPTOR_TYPE_INTERFACE             0x04U
+#define USB_DESCRIPTOR_TYPE_ENDPOINT              0x05U
+#define USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER      0x06U
+#define USB_DESCRIPTOR_TYPE_OTHER_SPEED           0x07U
+#define USB_DESCRIPTOR_TYPE_INTERFACE_POWER       0x08U
+#define USB_DESCRIPTOR_TYPE_OTG                   0x09U
+#define USB_DESCRIPTOR_TYPE_DEBUG                 0x0AU
+#define USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION 0x0BU
+#define USB_DESCRIPTOR_TYPE_BINARY_OBJECT_STORE   0x0FU
+#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY     0x10U
+
+#define USB_DESCRIPTOR_TYPE_FUNCTIONAL 0x21U
+
+// Class Specific Descriptor
+#define USB_CS_DESCRIPTOR_TYPE_DEVICE        0x21U
+#define USB_CS_DESCRIPTOR_TYPE_CONFIGURATION 0x22U
+#define USB_CS_DESCRIPTOR_TYPE_STRING        0x23U
+#define USB_CS_DESCRIPTOR_TYPE_INTERFACE     0x24U
+#define USB_CS_DESCRIPTOR_TYPE_ENDPOINT      0x25U
+
+#define USB_DESCRIPTOR_TYPE_SUPERSPEED_ENDPOINT_COMPANION     0x30U
+#define USB_DESCRIPTOR_TYPE_SUPERSPEED_ISO_ENDPOINT_COMPANION 0x31U
+
+/* USB Device Classes */
+#define USB_DEVICE_CLASS_RESERVED      0x00
+#define USB_DEVICE_CLASS_AUDIO         0x01
+#define USB_DEVICE_CLASS_CDC           0x02
+#define USB_DEVICE_CLASS_HID           0x03
+#define USB_DEVICE_CLASS_MONITOR       0x04
+#define USB_DEVICE_CLASS_PHYSICAL      0x05
+#define USB_DEVICE_CLASS_IMAGE         0x06
+#define USB_DEVICE_CLASS_PRINTER       0x07
+#define USB_DEVICE_CLASS_MASS_STORAGE  0x08
+#define USB_DEVICE_CLASS_HUB           0x09
+#define USB_DEVICE_CLASS_CDC_DATA      0x0a
+#define USB_DEVICE_CLASS_SMART_CARD    0x0b
+#define USB_DEVICE_CLASS_SECURITY      0x0d
+#define USB_DEVICE_CLASS_VIDEO         0x0e
+#define USB_DEVICE_CLASS_HEALTHCARE    0x0f
+#define USB_DEVICE_CLASS_DIAG_DEVICE   0xdc
+#define USB_DEVICE_CLASS_WIRELESS      0xe0
+#define USB_DEVICE_CLASS_MISC          0xef
+#define USB_DEVICE_CLASS_APP_SPECIFIC  0xfe
+#define USB_DEVICE_CLASS_VEND_SPECIFIC 0xff
+
+/* usb string index define */
+#define USB_STRING_LANGID_INDEX    0x00
+#define USB_STRING_MFC_INDEX       0x01
+#define USB_STRING_PRODUCT_INDEX   0x02
+#define USB_STRING_SERIAL_INDEX    0x03
+#define USB_STRING_CONFIG_INDEX    0x04
+#define USB_STRING_INTERFACE_INDEX 0x05
+#define USB_STRING_OS_INDEX        0x06
+#define USB_STRING_MAX             USB_STRING_OS_INDEX
+/*
+ * Devices supporting Microsoft OS Descriptors store special string
+ * descriptor at fixed index (0xEE). It is read when a new device is
+ * attached to a computer for the first time.
+ */
+#define USB_OSDESC_STRING_DESC_INDEX 0xEE
+
+/* bmAttributes in Configuration Descriptor */
+#define USB_CONFIG_POWERED_MASK  0x40
+#define USB_CONFIG_BUS_POWERED   0x80
+#define USB_CONFIG_SELF_POWERED  0xC0
+#define USB_CONFIG_REMOTE_WAKEUP 0x20
+
+/* bMaxPower in Configuration Descriptor */
+#define USB_CONFIG_POWER_MA(mA) ((mA) / 2)
+
+/* bEndpointAddress in Endpoint Descriptor */
+#define USB_ENDPOINT_DIRECTION_MASK 0x80
+#define USB_ENDPOINT_OUT(addr)      ((addr) | 0x00)
+#define USB_ENDPOINT_IN(addr)       ((addr) | 0x80)
+
+/* bmAttributes in Endpoint Descriptor */
+#define USB_ENDPOINT_TYPE_MASK               0x03
+#define USB_ENDPOINT_TYPE_CONTROL            0x00
+#define USB_ENDPOINT_TYPE_ISOCHRONOUS        0x01
+#define USB_ENDPOINT_TYPE_BULK               0x02
+#define USB_ENDPOINT_TYPE_INTERRUPT          0x03
+#define USB_ENDPOINT_SYNC_MASK               0x0C
+#define USB_ENDPOINT_SYNC_NO_SYNCHRONIZATION 0x00
+#define USB_ENDPOINT_SYNC_ASYNCHRONOUS       0x04
+#define USB_ENDPOINT_SYNC_ADAPTIVE           0x08
+#define USB_ENDPOINT_SYNC_SYNCHRONOUS        0x0C
+#define USB_ENDPOINT_USAGE_MASK              0x30
+#define USB_ENDPOINT_USAGE_DATA              0x00
+#define USB_ENDPOINT_USAGE_FEEDBACK          0x10
+#define USB_ENDPOINT_USAGE_IMPLICIT_FEEDBACK 0x20
+#define USB_ENDPOINT_USAGE_RESERVED          0x30
+
+/* bDevCapabilityType in Device Capability Descriptor */
+#define USB_DEVICE_CAPABILITY_WIRELESS_USB                1
+#define USB_DEVICE_CAPABILITY_USB_2_0_EXTENSION           2
+#define USB_DEVICE_CAPABILITY_SUPERSPEED_USB              3
+#define USB_DEVICE_CAPABILITY_CONTAINER_ID                4
+#define USB_DEVICE_CAPABILITY_PLATFORM                    5
+#define USB_DEVICE_CAPABILITY_POWER_DELIVERY_CAPABILITY   6
+#define USB_DEVICE_CAPABILITY_BATTERY_INFO_CAPABILITY     7
+#define USB_DEVICE_CAPABILITY_PD_CONSUMER_PORT_CAPABILITY 8
+#define USB_DEVICE_CAPABILITY_PD_PROVIDER_PORT_CAPABILITY 9
+#define USB_DEVICE_CAPABILITY_SUPERSPEED_PLUS             10
+#define USB_DEVICE_CAPABILITY_PRECISION_TIME_MEASUREMENT  11
+#define USB_DEVICE_CAPABILITY_WIRELESS_USB_EXT            12
+
+#define USB_BOS_CAPABILITY_EXTENSION 0x02
+#define USB_BOS_CAPABILITY_PLATFORM  0x05
+
+/* Setup packet definition used to read raw data from USB line */
+struct usb_setup_packet {
+    __packed union {
+        uint8_t bmRequestType; /* bmRequestType */
+        struct
+        {
+            uint8_t Recipient : 5; /* D4..0: Recipient */
+            uint8_t Type      : 2; /* D6..5: Type */
+            uint8_t Dir       : 1; /* D7:    Data Phase Txsfer Direction */
+        } bmRequestType_b;
+    };
+    uint8_t bRequest;
+    __packed union {
+        uint16_t wValue; /* wValue */
+        struct
+        {
+            uint8_t wValueL;
+            uint8_t wValueH;
+        };
+    };
+    __packed union {
+        uint16_t wIndex; /* wIndex */
+        struct
+        {
+            uint8_t wIndexL;
+            uint8_t wIndexH;
+        };
+    };
+    uint16_t wLength;
+} __packed;
+
+/** Standard Device Descriptor */
+struct usb_device_descriptor {
+    uint8_t bLength;            /* Descriptor size in bytes = 18 */
+    uint8_t bDescriptorType;    /* DEVICE descriptor type = 1 */
+    uint16_t bcdUSB;            /* USB spec in BCD, e.g. 0x0200 */
+    uint8_t bDeviceClass;       /* Class code, if 0 see interface */
+    uint8_t bDeviceSubClass;    /* Sub-Class code, 0 if class = 0 */
+    uint8_t bDeviceProtocol;    /* Protocol, if 0 see interface */
+    uint8_t bMaxPacketSize0;    /* Endpoint 0 max. size */
+    uint16_t idVendor;          /* Vendor ID per USB-IF */
+    uint16_t idProduct;         /* Product ID per manufacturer */
+    uint16_t bcdDevice;         /* Device release # in BCD */
+    uint8_t iManufacturer;      /* Index to manufacturer string */
+    uint8_t iProduct;           /* Index to product string */
+    uint8_t iSerialNumber;      /* Index to serial number string */
+    uint8_t bNumConfigurations; /* Number of possible configurations */
+} __packed;
+
+/** USB device_qualifier descriptor */
+struct usb_device_qualifier_descriptor {
+    uint8_t bLength;            /* Descriptor size in bytes = 10 */
+    uint8_t bDescriptorType;    /* DEVICE QUALIFIER type = 6 */
+    uint16_t bcdUSB;            /* USB spec in BCD, e.g. 0x0200 */
+    uint8_t bDeviceClass;       /* Class code, if 0 see interface */
+    uint8_t bDeviceSubClass;    /* Sub-Class code, 0 if class = 0 */
+    uint8_t bDeviceProtocol;    /* Protocol, if 0 see interface */
+    uint8_t bMaxPacketSize;     /* Endpoint 0 max. size */
+    uint8_t bNumConfigurations; /* Number of possible configurations */
+    uint8_t bReserved;          /* Reserved = 0 */
+} __packed;
+
+/** Standard Configuration Descriptor */
+struct usb_configuration_descriptor {
+    uint8_t bLength;             /* Descriptor size in bytes = 9 */
+    uint8_t bDescriptorType;     /* CONFIGURATION type = 2 or 7 */
+    uint16_t wTotalLength;       /* Length of concatenated descriptors */
+    uint8_t bNumInterfaces;      /* Number of interfaces, this config. */
+    uint8_t bConfigurationValue; /* Value to set this config. */
+    uint8_t iConfiguration;      /* Index to configuration string */
+    uint8_t bmAttributes;        /* Config. characteristics */
+    uint8_t bMaxPower;           /* Max.power from bus, 2mA units */
+} __packed;
+
+/** Standard Interface Descriptor */
+struct usb_interface_descriptor {
+    uint8_t bLength;            /* Descriptor size in bytes = 9 */
+    uint8_t bDescriptorType;    /* INTERFACE descriptor type = 4 */
+    uint8_t bInterfaceNumber;   /* Interface no.*/
+    uint8_t bAlternateSetting;  /* Value to select this IF */
+    uint8_t bNumEndpoints;      /* Number of endpoints excluding 0 */
+    uint8_t bInterfaceClass;    /* Class code, 0xFF = vendor */
+    uint8_t bInterfaceSubClass; /* Sub-Class code, 0 if class = 0 */
+    uint8_t bInterfaceProtocol; /* Protocol, 0xFF = vendor */
+    uint8_t iInterface;         /* Index to interface string */
+} __packed;
+
+/** Standard Endpoint Descriptor */
+struct usb_endpoint_descriptor {
+    uint8_t bLength;          /* Descriptor size in bytes = 7 */
+    uint8_t bDescriptorType;  /* ENDPOINT descriptor type = 5 */
+    uint8_t bEndpointAddress; /* Endpoint # 0 - 15 | IN/OUT */
+    uint8_t bmAttributes;     /* Transfer type */
+    uint16_t wMaxPacketSize;  /* Bits 10:0 = max. packet size */
+    uint8_t bInterval;        /* Polling interval in (micro) frames */
+} __packed;
+
+/** Unicode (UTF16LE) String Descriptor */
+struct usb_string_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint16_t bString;
+} __packed;
+
+/* USB Interface Association Descriptor */
+struct usb_interface_association_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bFirstInterface;
+    uint8_t bInterfaceCount;
+    uint8_t bFunctionClass;
+    uint8_t bFunctionSubClass;
+    uint8_t bFunctionProtocol;
+    uint8_t iFunction;
+} __packed;
+
+/* MS OS 1.0 string descriptor */
+struct usb_msosv1_string_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bString[14];
+    uint8_t bMS_VendorCode; /* Vendor Code, used for a control request */
+    uint8_t bPad;           /* Padding byte for VendorCode look as UTF16 */
+} __packed;
+
+/* MS OS 1.0 Header descriptor */
+struct usb_msosv1_compat_id_header_descriptor {
+    uint32_t dwLength;
+    uint16_t bcdVersion;
+    uint16_t wIndex;
+    uint8_t bCount;
+    uint8_t reserved[7];
+} __packed;
+
+/* MS OS 1.0 Function descriptor */
+struct usb_msosv1_comp_id_function_descriptor {
+    uint8_t bFirstInterfaceNumber;
+    uint8_t reserved1;
+    uint8_t compatibleID[8];
+    uint8_t subCompatibleID[8];
+    uint8_t reserved2[6];
+} __packed;
+
+#define usb_msosv1_comp_id_create(x)                                         \
+    struct usb_msosv1_comp_id {                                              \
+        struct usb_msosv1_compat_id_header_descriptor compat_id_header;      \
+        struct usb_msosv1_comp_id_function_descriptor compat_id_function[x]; \
+    };
+
+struct usb_msosv1_descriptor {
+    uint8_t *string;
+    uint8_t string_len;
+    uint8_t vendor_code;
+    uint8_t *compat_id;
+    uint16_t compat_id_len;
+    uint8_t *comp_id_property;
+    uint16_t comp_id_property_len;
+};
+
+/* MS OS 2.0 Header descriptor */
+struct usb_msosv2_header_descriptor {
+    uint32_t dwLength;
+    uint16_t bcdVersion;
+    uint16_t wIndex;
+    uint8_t bCount;
+} __packed;
+
+/*Microsoft OS 2.0 set header descriptor*/
+struct usb_msosv2_set_header_descriptor {
+    uint16_t wLength;
+    uint16_t wDescriptorType;
+    uint32_t dwWindowsVersion;
+    uint16_t wDescriptorSetTotalLength;
+} __packed;
+
+/* Microsoft OS 2.0 compatibleID descriptor*/
+struct usb_msosv2_comp_id_descriptor {
+    uint16_t wLength;
+    uint16_t wDescriptorType;
+    uint8_t compatibleID[8];
+    uint8_t subCompatibleID[8];
+} __packed;
+
+/* MS OS 2.0 property descriptor */
+struct usb_msosv2_property_descriptor {
+    uint16_t wLength;
+    uint16_t wDescriptorType;
+    uint32_t dwPropertyDataType;
+    uint16_t wPropertyNameLength;
+    const char *bPropertyName;
+    uint32_t dwPropertyDataLength;
+    const char *bPropertyData;
+};
+
+/* Microsoft OS 2.0 subset function descriptor  */
+struct usb_msosv2_subset_function_descriptor {
+    uint16_t wLength;
+    uint16_t wDescriptorType;
+    uint8_t bFirstInterface;
+    uint8_t bReserved;
+    uint16_t wSubsetLength;
+} __packed;
+
+struct usb_msosv2_descriptor {
+    uint8_t *compat_id;
+    uint16_t compat_id_len;
+    uint8_t vendor_code;
+};
+
+/* BOS header Descriptor */
+struct usb_bos_header_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint16_t wTotalLength;
+    uint8_t bNumDeviceCaps;
+} __packed;
+
+/* BOS Capability platform Descriptor */
+struct usb_bos_capability_platform_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bDevCapabilityType;
+    uint8_t bReserved;
+    uint8_t PlatformCapabilityUUID[16];
+} __packed;
+
+/* BOS Capability MS OS Descriptors version 2 */
+struct usb_bos_capability_msosv2_descriptor {
+    uint32_t dwWindowsVersion;
+    uint16_t wMSOSDescriptorSetTotalLength;
+    uint8_t bVendorCode;
+    uint8_t bAltEnumCode;
+} __packed;
+
+/* BOS Capability webusb */
+struct usb_bos_capability_webusb_descriptor {
+    uint16_t bcdVersion;
+    uint8_t bVendorCode;
+    uint8_t iLandingPage;
+} __packed;
+
+/* BOS Capability extension Descriptor*/
+struct usb_bos_capability_extension_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bDevCapabilityType;
+    uint32_t bmAttributes;
+} __packed;
+
+/* Microsoft OS 2.0 Platform Capability Descriptor
+* See https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/
+* microsoft-defined-usb-descriptors
+* Adapted from the source:
+* https://github.com/sowbug/weblight/blob/master/firmware/webusb.c
+* (BSD-2) Thanks http://janaxelson.com/files/ms_os_20_descriptors.c
+*/
+struct usb_bos_capability_platform_msosv2_descriptor {
+    struct usb_bos_capability_platform_descriptor platform_msos;
+    struct usb_bos_capability_msosv2_descriptor data_msosv2;
+} __packed;
+
+/* WebUSB Platform Capability Descriptor:
+* https://wicg.github.io/webusb/#webusb-platform-capability-descriptor
+*/
+struct usb_bos_capability_platform_webusb_descriptor {
+    struct usb_bos_capability_platform_descriptor platform_webusb;
+    struct usb_bos_capability_webusb_descriptor data_webusb;
+} __packed;
+
+struct usb_webusb_url_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bScheme;
+    char URL[];
+} __packed;
+
+struct usb_bos_descriptor {
+    uint8_t *string;
+    uint32_t string_len;
+};
+
+/* USB Device Capability Descriptor */
+struct usb_device_capability_descriptor {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bDevCapabilityType;
+} __packed;
+
+/** USB descriptor header */
+struct usb_desc_header {
+    uint8_t bLength;         /**< descriptor length */
+    uint8_t bDescriptorType; /**< descriptor type */
+};
+// clang-format off
+#define USB_DEVICE_DESCRIPTOR_INIT(bcdUSB, bDeviceClass, bDeviceSubClass, bDeviceProtocol, idVendor, idProduct, bcdDevice, bNumConfigurations) \
+    0x12,                       /* bLength */                                                                                              \
+    USB_DESCRIPTOR_TYPE_DEVICE, /* bDescriptorType */                                                                                      \
+    WBVAL(bcdUSB),              /* bcdUSB */                                                                                               \
+    bDeviceClass,               /* bDeviceClass */                                                                                         \
+    bDeviceSubClass,            /* bDeviceSubClass */                                                                                      \
+    bDeviceProtocol,            /* bDeviceProtocol */                                                                                      \
+    0x40,                       /* bMaxPacketSize */                                                                                       \
+    WBVAL(idVendor),            /* idVendor */                                                                                             \
+    WBVAL(idProduct),           /* idProduct */                                                                                            \
+    WBVAL(bcdDevice),           /* bcdDevice */                                                                                            \
+    USB_STRING_MFC_INDEX,       /* iManufacturer */                                                                                        \
+    USB_STRING_PRODUCT_INDEX,   /* iProduct */                                                                                             \
+    USB_STRING_SERIAL_INDEX,    /* iSerial */                                                                                              \
+    bNumConfigurations          /* bNumConfigurations */
+
+#define USB_CONFIG_DESCRIPTOR_INIT(wTotalLength, bNumInterfaces, bConfigurationValue, bmAttributes, bMaxPower) \
+    0x09,                              /* bLength */                                                       \
+    USB_DESCRIPTOR_TYPE_CONFIGURATION, /* bDescriptorType */                                               \
+    WBVAL(wTotalLength),               /* wTotalLength */                                                  \
+    bNumInterfaces,                    /* bNumInterfaces */                                                \
+    bConfigurationValue,               /* bConfigurationValue */                                           \
+    0x00,                              /* iConfiguration */                                                \
+    bmAttributes,                      /* bmAttributes */                                                  \
+    USB_CONFIG_POWER_MA(bMaxPower)     /* bMaxPower */
+
+#define USB_INTERFACE_DESCRIPTOR_INIT(bInterfaceNumber, bAlternateSetting, bNumEndpoints,                  \
+                                      bInterfaceClass, bInterfaceSubClass, bInterfaceProtocol, iInterface) \
+    0x09,                          /* bLength */                                                       \
+    USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */                                               \
+    bInterfaceNumber,              /* bInterfaceNumber */                                              \
+    bAlternateSetting,             /* bAlternateSetting */                                             \
+    bNumEndpoints,                 /* bNumEndpoints */                                                 \
+    bInterfaceClass,               /* bInterfaceClass */                                               \
+    bInterfaceSubClass,            /* bInterfaceSubClass */                                            \
+    bInterfaceProtocol,            /* bInterfaceProtocol */                                            \
+    iInterface                     /* iInterface */
+
+#define USB_ENDPOINT_DESCRIPTOR_INIT(bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval) \
+    0x07,                         /* bLength */                                             \
+    USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */                                     \
+    bEndpointAddress,             /* bEndpointAddress */                                    \
+    bmAttributes,                 /* bmAttributes */                                        \
+    WBVAL(wMaxPacketSize),        /* wMaxPacketSize */                                      \
+    bInterval                     /* bInterval */
+
+#define USB_IAD_INIT(bFirstInterface, bInterfaceCount, bFunctionClass, bFunctionSubClass, bFunctionProtocol) \
+    0x08,                                      /* bLength */                                             \
+    USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */                                     \
+    bFirstInterface,                           /* bFirstInterface */                                     \
+    bInterfaceCount,                           /* bInterfaceCount */                                     \
+    bFunctionClass,                            /* bFunctionClass */                                      \
+    bFunctionSubClass,                         /* bFunctionSubClass */                                   \
+    bFunctionProtocol,                         /* bFunctionProtocol */                                   \
+    0x00                                       /* iFunction */
+
+#define USB_LANGID_INIT(id)                           \
+    0x04,                           /* bLength */     \
+    USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ \
+    WBVAL(id)                   /* wLangID0 */
+// clang-format on
+#endif
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/common/usb_slist.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/common/usb_slist.h
new file mode 100644
index 00000000..357df1be
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/common/usb_slist.h
@@ -0,0 +1,224 @@
+#ifndef __USB_SLIST_H__
+#define __USB_SLIST_H__
+
+#include "string.h"
+#include "stdint.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * usb_container_of - return the member address of ptr, if the type of ptr is the
+ * struct type.
+ */
+#define usb_container_of(ptr, type, member) \
+    ((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member)))
+
+/**
+ * Single List structure
+ */
+struct usb_slist_node {
+    struct usb_slist_node *next; /**< point to next node. */
+};
+typedef struct usb_slist_node usb_slist_t; /**< Type for single list. */
+
+/**
+ * @brief initialize a single list
+ *
+ * @param l the single list to be initialized
+ */
+static inline void usb_slist_init(usb_slist_t *l)
+{
+    l->next = NULL;
+}
+
+static inline void usb_slist_add_head(usb_slist_t *l, usb_slist_t *n)
+{
+    n->next = l->next;
+    l->next = n;
+}
+
+static inline void usb_slist_add_tail(usb_slist_t *l, usb_slist_t *n)
+{
+    while (l->next) {
+        l = l->next;
+    }
+
+    /* append the node to the tail */
+    l->next = n;
+    n->next = NULL;
+}
+
+static inline void usb_slist_insert(usb_slist_t *l, usb_slist_t *next, usb_slist_t *n)
+{
+    if (!next) {
+        usb_slist_add_tail(next, l);
+        return;
+    }
+
+    while (l->next) {
+        if (l->next == next) {
+            l->next = n;
+            n->next = next;
+        }
+
+        l = l->next;
+    }
+}
+
+static inline usb_slist_t *usb_slist_remove(usb_slist_t *l, usb_slist_t *n)
+{
+    /* remove slist head */
+    while (l->next && l->next != n) {
+        l = l->next;
+    }
+
+    /* remove node */
+    if (l->next != (usb_slist_t *)0) {
+        l->next = l->next->next;
+    }
+
+    return l;
+}
+
+static inline unsigned int usb_slist_len(const usb_slist_t *l)
+{
+    unsigned int len = 0;
+    const usb_slist_t *list = l->next;
+
+    while (list != NULL) {
+        list = list->next;
+        len++;
+    }
+
+    return len;
+}
+
+static inline unsigned int usb_slist_contains(usb_slist_t *l, usb_slist_t *n)
+{
+    while (l->next) {
+        if (l->next == n) {
+            return 0;
+        }
+
+        l = l->next;
+    }
+
+    return 1;
+}
+
+static inline usb_slist_t *usb_slist_head(usb_slist_t *l)
+{
+    return l->next;
+}
+
+static inline usb_slist_t *usb_slist_tail(usb_slist_t *l)
+{
+    while (l->next) {
+        l = l->next;
+    }
+
+    return l;
+}
+
+static inline usb_slist_t *usb_slist_next(usb_slist_t *n)
+{
+    return n->next;
+}
+
+static inline int usb_slist_isempty(usb_slist_t *l)
+{
+    return l->next == NULL;
+}
+
+/**
+ * @brief initialize a slist object
+ */
+#define USB_SLIST_OBJECT_INIT(object) \
+    {                                 \
+        NULL                          \
+    }
+
+/**
+ * @brief initialize a slist object
+ */
+#define USB_SLIST_DEFINE(slist) \
+    usb_slist_t slist = { NULL }
+
+/**
+ * @brief get the struct for this single list node
+ * @param node the entry point
+ * @param type the type of structure
+ * @param member the name of list in structure
+ */
+#define usb_slist_entry(node, type, member) \
+    usb_container_of(node, type, member)
+
+/**
+ * usb_slist_first_entry - get the first element from a slist
+ * @ptr:    the slist head to take the element from.
+ * @type:   the type of the struct this is embedded in.
+ * @member: the name of the slist_struct within the struct.
+ *
+ * Note, that slist is expected to be not empty.
+ */
+#define usb_slist_first_entry(ptr, type, member) \
+    usb_slist_entry((ptr)->next, type, member)
+
+/**
+ * usb_slist_tail_entry - get the tail element from a slist
+ * @ptr:    the slist head to take the element from.
+ * @type:   the type of the struct this is embedded in.
+ * @member: the name of the slist_struct within the struct.
+ *
+ * Note, that slist is expected to be not empty.
+ */
+#define usb_slist_tail_entry(ptr, type, member) \
+    usb_slist_entry(usb_slist_tail(ptr), type, member)
+
+/**
+ * usb_slist_first_entry_or_null - get the first element from a slist
+ * @ptr:    the slist head to take the element from.
+ * @type:   the type of the struct this is embedded in.
+ * @member: the name of the slist_struct within the struct.
+ *
+ * Note, that slist is expected to be not empty.
+ */
+#define usb_slist_first_entry_or_null(ptr, type, member) \
+    (usb_slist_isempty(ptr) ? NULL : usb_slist_first_entry(ptr, type, member))
+
+/**
+ * usb_slist_for_each - iterate over a single list
+ * @pos:    the usb_slist_t * to use as a loop cursor.
+ * @head:   the head for your single list.
+ */
+#define usb_slist_for_each(pos, head) \
+    for (pos = (head)->next; pos != NULL; pos = pos->next)
+
+#define usb_slist_for_each_safe(pos, next, head)    \
+    for (pos = (head)->next, next = pos->next; pos; \
+         pos = next, next = pos->next)
+
+/**
+ * usb_slist_for_each_entry  -   iterate over single list of given type
+ * @pos:    the type * to use as a loop cursor.
+ * @head:   the head for your single list.
+ * @member: the name of the list_struct within the struct.
+ */
+#define usb_slist_for_each_entry(pos, head, member)                 \
+    for (pos = usb_slist_entry((head)->next, typeof(*pos), member); \
+         &pos->member != (NULL);                                    \
+         pos = usb_slist_entry(pos->member.next, typeof(*pos), member))
+
+#define usb_slist_for_each_entry_safe(pos, n, head, member)          \
+    for (pos = usb_slist_entry((head)->next, typeof(*pos), member),  \
+        n = usb_slist_entry(pos->member.next, typeof(*pos), member); \
+         &pos->member != (NULL);                                     \
+         pos = n, n = usb_slist_entry(pos->member.next, typeof(*pos), member))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/common/usb_util.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/common/usb_util.h
new file mode 100644
index 00000000..95e75cba
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/common/usb_util.h
@@ -0,0 +1,150 @@
+#ifndef _USB_UTIL_H
+#define _USB_UTIL_H
+
+#include "stdbool.h"
+#include "string.h"
+#include "stdint.h"
+#include "stdio.h"
+#include "stdlib.h"
+#include "usb_slist.h"
+#include "bflb_platform.h"
+
+#ifndef __packed
+#define __packed __attribute__((__packed__))
+#endif
+#ifndef __aligned
+#define __aligned(x) __attribute__((__aligned__(x)))
+#endif
+#define __may_alias __attribute__((__may_alias__))
+#ifndef __printf_like
+#define __printf_like(f, a) __attribute__((format(printf, f, a)))
+#endif
+#define __used __attribute__((__used__))
+#ifndef __deprecated
+#define __deprecated __attribute__((deprecated))
+#endif
+#define ARG_UNUSED(x) (void)(x)
+
+// #define likely(x)   __builtin_expect((bool)!!(x), true)
+// #define unlikely(x) __builtin_expect((bool)!!(x), false)
+
+#define popcount(x) __builtin_popcount(x)
+
+#ifndef __no_optimization
+#define __no_optimization __attribute__((optimize("-O0")))
+#endif
+
+#ifndef __weak
+#define __weak __attribute__((__weak__))
+#endif
+#define __unused __attribute__((__unused__))
+
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif
+#ifndef __ALIGN_END
+#define __ALIGN_END __attribute__((aligned(4)))
+#endif
+
+#ifndef LO_BYTE
+#define LO_BYTE(x) ((uint8_t)(x & 0x00FF))
+#endif
+
+#ifndef HI_BYTE
+#define HI_BYTE(x) ((uint8_t)((x & 0xFF00) >> 8))
+#endif
+
+/**
+ * @def MAX
+ * @brief The larger value between @p a and @p b.
+ * @note Arguments are evaluated twice.
+ */
+#ifndef MAX
+/* Use Z_MAX for a GCC-only, single evaluation version */
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+
+/**
+ * @def MIN
+ * @brief The smaller value between @p a and @p b.
+ * @note Arguments are evaluated twice.
+ */
+#ifndef MIN
+/* Use Z_MIN for a GCC-only, single evaluation version */
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#ifndef BCD
+#define BCD(x) ((((x) / 10) << 4) | ((x) % 10))
+#endif
+
+#ifdef BIT
+#undef BIT
+#define BIT(n) (1UL << (n))
+#else
+#define BIT(n) (1UL << (n))
+#endif
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(array) \
+    ((int)((sizeof(array) / sizeof((array)[0]))))
+#endif
+
+#ifndef BSWAP16
+#define BSWAP16(u16) (__builtin_bswap16(u16))
+#endif
+#ifndef BSWAP32
+#define BSWAP32(u32) (__builtin_bswap32(u32))
+#endif
+
+#define GET_BE16(field) \
+    (((uint16_t)(field)[0] << 8) | ((uint16_t)(field)[1]))
+
+#define GET_BE32(field) \
+    (((uint32_t)(field)[0] << 24) | ((uint32_t)(field)[1] << 16) | ((uint32_t)(field)[2] << 8) | ((uint32_t)(field)[3] << 0))
+
+#define SET_BE16(field, value)                \
+    do {                                      \
+        (field)[0] = (uint8_t)((value) >> 8); \
+        (field)[1] = (uint8_t)((value) >> 0); \
+    } while (0)
+
+#define SET_BE24(field, value)                 \
+    do {                                       \
+        (field)[0] = (uint8_t)((value) >> 16); \
+        (field)[1] = (uint8_t)((value) >> 8);  \
+        (field)[2] = (uint8_t)((value) >> 0);  \
+    } while (0)
+
+#define SET_BE32(field, value)                 \
+    do {                                       \
+        (field)[0] = (uint8_t)((value) >> 24); \
+        (field)[1] = (uint8_t)((value) >> 16); \
+        (field)[2] = (uint8_t)((value) >> 8);  \
+        (field)[3] = (uint8_t)((value) >> 0);  \
+    } while (0)
+
+#define REQTYPE_GET_DIR(x)   (((x) >> 7) & 0x01)
+#define REQTYPE_GET_TYPE(x)  (((x) >> 5) & 0x03U)
+#define REQTYPE_GET_RECIP(x) ((x)&0x1F)
+
+#define GET_DESC_TYPE(x)  (((x) >> 8) & 0xFFU)
+#define GET_DESC_INDEX(x) ((x)&0xFFU)
+
+#define WBVAL(x) (x & 0xFF), ((x >> 8) & 0xFF)
+#define DBVAL(x) (x & 0xFF), ((x >> 8) & 0xFF), ((x >> 16) & 0xFF), ((x >> 24) & 0xFF)
+
+#define USB_DESC_SECTION __attribute__((section("usb_desc"))) __used __aligned(1)
+
+#if 0
+#define USBD_LOG_WRN(a, ...) bflb_platform_printf(a, ##__VA_ARGS__)
+#define USBD_LOG_DBG(a, ...) bflb_platform_printf(a, ##__VA_ARGS__)
+#define USBD_LOG_ERR(a, ...) bflb_platform_printf(a, ##__VA_ARGS__)
+#else
+#define USBD_LOG_INFO(a, ...) bflb_platform_printf(a, ##__VA_ARGS__)
+#define USBD_LOG_DBG(a, ...)
+#define USBD_LOG_WRN(a, ...) bflb_platform_printf(a, ##__VA_ARGS__)
+#define USBD_LOG_ERR(a, ...)  bflb_platform_printf(a, ##__VA_ARGS__)
+#endif
+
+#endif
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/core/usbd_core.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/core/usbd_core.c
new file mode 100644
index 00000000..47929088
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/core/usbd_core.c
@@ -0,0 +1,1269 @@
+/**
+ * @file usbd_core.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "usbd_core.h"
+#include "usbd_winusb.h"
+
+#define USBD_EP_CALLBACK_LIST_SEARCH   0
+#define USBD_EP_CALLBACK_ARR_SEARCH    1
+#define USBD_EP_CALLBACK_SEARCH_METHOD USBD_EP_CALLBACK_ARR_SEARCH
+
+/* general descriptor field offsets */
+#define DESC_bLength         0 /** Length offset */
+#define DESC_bDescriptorType 1 /** Descriptor type offset */
+
+/* config descriptor field offsets */
+#define CONF_DESC_wTotalLength        2 /** Total length offset */
+#define CONF_DESC_bConfigurationValue 5 /** Configuration value offset */
+#define CONF_DESC_bmAttributes        7 /** configuration characteristics */
+
+/* interface descriptor field offsets */
+#define INTF_DESC_bInterfaceNumber  2 /** Interface number offset */
+#define INTF_DESC_bAlternateSetting 3 /** Alternate setting offset */
+
+#define USB_REQUEST_BUFFER_SIZE 256
+#define USB_EP_OUT_NUM          8
+#define USB_EP_IN_NUM           8
+
+static struct usbd_core_cfg_priv {
+    /** Setup packet */
+    struct usb_setup_packet setup;
+    /** Pointer to data buffer */
+    uint8_t *ep0_data_buf;
+    /** Remaining bytes in buffer */
+    uint32_t ep0_data_buf_residue;
+    /** Total length of control transfer */
+    uint32_t ep0_data_buf_len;
+    /** Zero length packet flag of control transfer */
+    bool zlp_flag;
+    /** Pointer to registered descriptors */
+    const uint8_t *descriptors;
+    /* Buffer used for storing standard, class and vendor request data */
+    uint8_t req_data[USB_REQUEST_BUFFER_SIZE];
+
+#if USBD_EP_CALLBACK_SEARCH_METHOD == 1
+    usbd_endpoint_callback in_ep_cb[USB_EP_IN_NUM];
+    usbd_endpoint_callback out_ep_cb[USB_EP_OUT_NUM];
+#endif
+    /** Variable to check whether the usb has been enabled */
+    bool enabled;
+    /** Variable to check whether the usb has been configured */
+    bool configured;
+    /** Currently selected configuration */
+    uint8_t configuration;
+    /** Remote wakeup feature status */
+    uint16_t remote_wakeup;
+    uint8_t reserved;
+} usbd_core_cfg;
+
+static usb_slist_t usbd_class_head = USB_SLIST_OBJECT_INIT(usbd_class_head);
+static struct usb_msosv1_descriptor *msosv1_desc;
+static struct usb_msosv2_descriptor *msosv2_desc;
+static struct usb_bos_descriptor *bos_desc;
+
+/**
+ * @brief print the contents of a setup packet
+ *
+ * @param [in] setup The setup packet
+ *
+ */
+static void usbd_print_setup(struct usb_setup_packet *setup)
+{
+    USBD_LOG_INFO("Setup: "
+                  "bmRequestType 0x%02x, bRequest 0x%02x, wValue 0x%04x, wIndex 0x%04x, wLength 0x%04x\r\n",
+                  setup->bmRequestType,
+                  setup->bRequest,
+                  setup->wValue,
+                  setup->wIndex,
+                  setup->wLength);
+}
+
+/**
+ * @brief Check if the device is in Configured state
+ *
+ * @return true if Configured, false otherwise.
+ */
+static bool is_device_configured(void)
+{
+    return (usbd_core_cfg.configuration != 0);
+}
+/**
+ * @brief Check if the interface of given number is valid
+ *
+ * @param [in] interface Number of the addressed interface
+ *
+ * This function searches through descriptor and checks
+ * is the Host has addressed valid interface.
+ *
+ * @return true if interface exists - valid
+ */
+static bool is_interface_valid(uint8_t interface)
+{
+    const uint8_t *p = (uint8_t *)usbd_core_cfg.descriptors;
+    const struct usb_configuration_descriptor *cfg_descr;
+
+    /* Search through descriptor for matching interface */
+    while (p[DESC_bLength] != 0U) {
+        if (p[DESC_bDescriptorType] == USB_DESCRIPTOR_TYPE_CONFIGURATION) {
+            cfg_descr = (const struct usb_configuration_descriptor *)p;
+
+            if (interface < cfg_descr->bNumInterfaces) {
+                return true;
+            }
+        }
+
+        p += p[DESC_bLength];
+    }
+
+    return false;
+}
+/**
+ * @brief Check if the endpoint of given address is valid
+ *
+ * @param [in] ep Address of the Endpoint
+ *
+ * This function checks if the Endpoint of given address
+ * is valid for the configured device. Valid Endpoint is
+ * either Control Endpoint or one used by the device.
+ *
+ * @return true if endpoint exists - valid
+ */
+static bool is_ep_valid(uint8_t ep)
+{
+    /* Check if its Endpoint 0 */
+    if ((ep & 0x7f) == 0) {
+        return true;
+    }
+
+    return true;
+}
+#if USBD_EP_CALLBACK_SEARCH_METHOD == 1
+static void usbd_ep_callback_register(void)
+{
+    usb_slist_t *i, *j, *k;
+    usb_slist_for_each(i, &usbd_class_head)
+    {
+        usbd_class_t *class = usb_slist_entry(i, struct usbd_class, list);
+
+        usb_slist_for_each(j, &class->intf_list)
+        {
+            usbd_interface_t *intf = usb_slist_entry(j, struct usbd_interface, list);
+
+            usb_slist_for_each(k, &intf->ep_list)
+            {
+                usbd_endpoint_t *ept = usb_slist_entry(k, struct usbd_endpoint, list);
+
+                if (ept->ep_cb) {
+                    if (ept->ep_addr & 0x80) {
+                        usbd_core_cfg.in_ep_cb[ept->ep_addr & 0x7f] = ept->ep_cb;
+                    } else {
+                        usbd_core_cfg.out_ep_cb[ept->ep_addr & 0x7f] = ept->ep_cb;
+                    }
+                }
+            }
+        }
+    }
+}
+#endif
+/**
+ * @brief configure and enable endpoint
+ *
+ * This function sets endpoint configuration according to one specified in USB
+ * endpoint descriptor and then enables it for data transfers.
+ *
+ * @param [in]  ep_desc Endpoint descriptor byte array
+ *
+ * @return true if successfully configured and enabled
+ */
+static bool usbd_set_endpoint(const struct usb_endpoint_descriptor *ep_desc)
+{
+    struct usbd_endpoint_cfg ep_cfg;
+
+    ep_cfg.ep_addr = ep_desc->bEndpointAddress;
+    ep_cfg.ep_mps = ep_desc->wMaxPacketSize;
+    ep_cfg.ep_type = ep_desc->bmAttributes & USBD_EP_TYPE_MASK;
+
+    USBD_LOG_INFO("Open endpoint:0x%x type:%u mps:%u\r\n",
+                  ep_cfg.ep_addr, ep_cfg.ep_type, ep_cfg.ep_mps);
+
+    usbd_ep_open(&ep_cfg);
+    usbd_core_cfg.configured = true;
+
+    return true;
+}
+/**
+ * @brief Disable endpoint for transferring data
+ *
+ * This function cancels transfers that are associated with endpoint and
+ * disabled endpoint itself.
+ *
+ * @param [in]  ep_desc Endpoint descriptor byte array
+ *
+ * @return true if successfully deconfigured and disabled
+ */
+static bool usbd_reset_endpoint(const struct usb_endpoint_descriptor *ep_desc)
+{
+    struct usbd_endpoint_cfg ep_cfg;
+
+    ep_cfg.ep_addr = ep_desc->bEndpointAddress;
+    ep_cfg.ep_mps = ep_desc->wMaxPacketSize;
+    ep_cfg.ep_type = ep_desc->bmAttributes & USBD_EP_TYPE_MASK;
+
+    USBD_LOG_INFO("Close endpoint:0x%x type:%u\r\n",
+                  ep_cfg.ep_addr, ep_cfg.ep_type);
+
+    usbd_ep_close(ep_cfg.ep_addr);
+
+    return true;
+}
+
+/**
+ * @brief get specified USB descriptor
+ *
+ * This function parses the list of installed USB descriptors and attempts
+ * to find the specified USB descriptor.
+ *
+ * @param [in]  type_index Type and index of the descriptor
+ * @param [in]  lang_id    Language ID of the descriptor (currently unused)
+ * @param [out] len        Descriptor length
+ * @param [out] data       Descriptor data
+ *
+ * @return true if the descriptor was found, false otherwise
+ */
+static bool usbd_get_descriptor(uint16_t type_index, uint8_t **data, uint32_t *len)
+{
+    uint8_t type = 0U;
+    uint8_t index = 0U;
+    uint8_t *p = NULL;
+    uint32_t cur_index = 0U;
+    bool found = false;
+
+    type = GET_DESC_TYPE(type_index);
+    index = GET_DESC_INDEX(type_index);
+
+    if ((type == USB_DESCRIPTOR_TYPE_STRING) && (index == USB_OSDESC_STRING_DESC_INDEX)) {
+        USBD_LOG_INFO("read MS OS 2.0 descriptor string\r\n");
+
+        if (!msosv1_desc) {
+            return false;
+        }
+
+        *data = (uint8_t *)msosv1_desc->string;
+        *len = msosv1_desc->string_len;
+
+        return true;
+    } else if (type == USB_DESCRIPTOR_TYPE_BINARY_OBJECT_STORE) {
+        USBD_LOG_INFO("read BOS descriptor string\r\n");
+
+        if (!bos_desc) {
+            return false;
+        }
+
+        *data = bos_desc->string;
+        *len = bos_desc->string_len;
+        return true;
+    }
+    /*
+     * Invalid types of descriptors,
+     * see USB Spec. Revision 2.0, 9.4.3 Get Descriptor
+     */
+    else if ((type == USB_DESCRIPTOR_TYPE_INTERFACE) || (type == USB_DESCRIPTOR_TYPE_ENDPOINT) ||
+#ifndef CONFIG_USB_HS
+             (type > USB_DESCRIPTOR_TYPE_ENDPOINT)) {
+#else
+             (type > USB_DESCRIPTOR_TYPE_OTHER_SPEED)) {
+#endif
+        return false;
+    }
+
+    p = (uint8_t *)usbd_core_cfg.descriptors;
+
+    cur_index = 0U;
+
+    while (p[DESC_bLength] != 0U) {
+        if (p[DESC_bDescriptorType] == type) {
+            if (cur_index == index) {
+                found = true;
+                break;
+            }
+
+            cur_index++;
+        }
+
+        /* skip to next descriptor */
+        p += p[DESC_bLength];
+    }
+
+    if (found) {
+        /* set data pointer */
+        *data = p;
+
+        /* get length from structure */
+        if (type == USB_DESCRIPTOR_TYPE_CONFIGURATION) {
+            /* configuration descriptor is an
+             * exception, length is at offset
+             * 2 and 3
+             */
+            *len = (p[CONF_DESC_wTotalLength]) |
+                   (p[CONF_DESC_wTotalLength + 1] << 8);
+        } else {
+            /* normally length is at offset 0 */
+            *len = p[DESC_bLength];
+        }
+    } else {
+        /* nothing found */
+        USBD_LOG_ERR("descriptor  not found!\r\n", type, index);
+    }
+
+    return found;
+}
+
+/**
+ * @brief set USB configuration
+ *
+ * This function configures the device according to the specified configuration
+ * index and alternate setting by parsing the installed USB descriptor list.
+ * A configuration index of 0 unconfigures the device.
+ *
+ * @param [in] config_index Configuration index
+ * @param [in] alt_setting  Alternate setting number
+ *
+ * @return true if successfully configured false if error or unconfigured
+ */
+static bool usbd_set_configuration(uint8_t config_index, uint8_t alt_setting)
+{
+    uint8_t *p = (uint8_t *)usbd_core_cfg.descriptors;
+    uint8_t cur_alt_setting = 0xFF;
+    uint8_t cur_config = 0xFF;
+    bool found = false;
+
+    if (config_index == 0U) {
+        /* TODO: unconfigure device */
+        USBD_LOG_ERR("Device not configured - invalid configuration\r\n");
+        return true;
+    }
+
+    /* configure endpoints for this configuration/altsetting */
+    while (p[DESC_bLength] != 0U) {
+        switch (p[DESC_bDescriptorType]) {
+            case USB_DESCRIPTOR_TYPE_CONFIGURATION:
+                /* remember current configuration index */
+                cur_config = p[CONF_DESC_bConfigurationValue];
+
+                if (cur_config == config_index) {
+                    found = true;
+                }
+
+                break;
+
+            case USB_DESCRIPTOR_TYPE_INTERFACE:
+                /* remember current alternate setting */
+                cur_alt_setting =
+                    p[INTF_DESC_bAlternateSetting];
+                break;
+
+            case USB_DESCRIPTOR_TYPE_ENDPOINT:
+                if ((cur_config != config_index) ||
+                    (cur_alt_setting != alt_setting)) {
+                    break;
+                }
+
+                found = usbd_set_endpoint((struct usb_endpoint_descriptor *)p);
+                break;
+
+            default:
+                break;
+        }
+
+        /* skip to next descriptor */
+        p += p[DESC_bLength];
+    }
+
+    return found;
+}
+
+/**
+ * @brief set USB interface
+ *
+ * @param [in] iface Interface index
+ * @param [in] alt_setting  Alternate setting number
+ *
+ * @return true if successfully configured false if error or unconfigured
+ */
+static bool usbd_set_interface(uint8_t iface, uint8_t alt_setting)
+{
+    const uint8_t *p = usbd_core_cfg.descriptors;
+    const uint8_t *if_desc = NULL;
+    struct usb_endpoint_descriptor *ep_desc;
+    uint8_t cur_alt_setting = 0xFF;
+    uint8_t cur_iface = 0xFF;
+    bool ret = false;
+
+    USBD_LOG_DBG("iface %u alt_setting %u\r\n", iface, alt_setting);
+
+    while (p[DESC_bLength] != 0U) {
+        switch (p[DESC_bDescriptorType]) {
+            case USB_DESCRIPTOR_TYPE_INTERFACE:
+                /* remember current alternate setting */
+                cur_alt_setting = p[INTF_DESC_bAlternateSetting];
+                cur_iface = p[INTF_DESC_bInterfaceNumber];
+
+                if (cur_iface == iface &&
+                    cur_alt_setting == alt_setting) {
+                    if_desc = (void *)p;
+                }
+
+                USBD_LOG_DBG("Current iface %u alt setting %u",
+                             cur_iface, cur_alt_setting);
+                break;
+
+            case USB_DESCRIPTOR_TYPE_ENDPOINT:
+                if (cur_iface == iface) {
+                    ep_desc = (struct usb_endpoint_descriptor *)p;
+
+                    if (cur_alt_setting != alt_setting) {
+                        ret = usbd_reset_endpoint(ep_desc);
+                    } else {
+                        ret = usbd_set_endpoint(ep_desc);
+                    }
+                }
+
+                break;
+
+            default:
+                break;
+        }
+
+        /* skip to next descriptor */
+        p += p[DESC_bLength];
+    }
+
+    usbd_event_notify_handler(USB_EVENT_SET_INTERFACE, (void *)if_desc);
+
+    return ret;
+}
+
+/**
+ * @brief handle a standard device request
+ *
+ * @param [in]     setup    The setup packet
+ * @param [in,out] len      Pointer to data length
+ * @param [in,out] ep0_data_buf Data buffer
+ *
+ * @return true if the request was handled successfully
+ */
+static bool usbd_std_device_req_handler(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len)
+{
+    uint16_t value = setup->wValue;
+    // uint16_t index = setup->wIndex;
+    bool ret = true;
+
+    switch (setup->bRequest) {
+        case USB_REQUEST_GET_STATUS:
+            USBD_LOG_DBG("REQ_GET_STATUS\r\n");
+            /* bit 0: self-powered */
+            /* bit 1: remote wakeup */
+            *data = (uint8_t *)&usbd_core_cfg.remote_wakeup;
+
+            *len = 2;
+            break;
+
+        case USB_REQUEST_CLEAR_FEATURE:
+            USBD_LOG_DBG("REQ_CLEAR_FEATURE\r\n");
+            ret = false;
+
+            if (value == USB_FEATURE_REMOTE_WAKEUP) {
+                usbd_core_cfg.remote_wakeup = 0;
+                usbd_event_notify_handler(USB_EVENT_CLEAR_REMOTE_WAKEUP, NULL);
+                ret = true;
+            }
+
+            break;
+
+        case USB_REQUEST_SET_FEATURE:
+            USBD_LOG_DBG("REQ_SET_FEATURE\r\n");
+            ret = false;
+
+            if (value == USB_FEATURE_REMOTE_WAKEUP) {
+                usbd_core_cfg.remote_wakeup = 1;
+                usbd_event_notify_handler(USB_EVENT_SET_REMOTE_WAKEUP, NULL);
+                ret = true;
+            }
+
+            if (value == USB_FEATURE_TEST_MODE) {
+                /* put TEST_MODE code here */
+            }
+
+            break;
+
+        case USB_REQUEST_SET_ADDRESS:
+            USBD_LOG_DBG("REQ_SET_ADDRESS, addr 0x%x\r\n", value);
+            usbd_set_address(value);
+            break;
+
+        case USB_REQUEST_GET_DESCRIPTOR:
+            USBD_LOG_DBG("REQ_GET_DESCRIPTOR\r\n");
+            ret = usbd_get_descriptor(value, data, len);
+            break;
+
+        case USB_REQUEST_SET_DESCRIPTOR:
+            USBD_LOG_DBG("Device req 0x%02x not implemented\r\n", setup->bRequest);
+            ret = false;
+            break;
+
+        case USB_REQUEST_GET_CONFIGURATION:
+            USBD_LOG_DBG("REQ_GET_CONFIGURATION\r\n");
+            /* indicate if we are configured */
+            *data = (uint8_t *)&usbd_core_cfg.configuration;
+            *len = 1;
+            break;
+
+        case USB_REQUEST_SET_CONFIGURATION:
+            value &= 0xFF;
+            USBD_LOG_DBG("REQ_SET_CONFIGURATION, conf 0x%x\r\n", value);
+
+            if (!usbd_set_configuration(value, 0)) {
+                USBD_LOG_DBG("USB Set Configuration failed\r\n");
+                ret = false;
+            } else {
+                /* configuration successful,
+                 * update current configuration
+                 */
+                usbd_core_cfg.configuration = value;
+                usbd_event_notify_handler(USB_EVENT_CONFIGURED, NULL);
+            }
+
+            break;
+
+        case USB_REQUEST_GET_INTERFACE:
+            break;
+
+        case USB_REQUEST_SET_INTERFACE:
+            break;
+
+        default:
+            USBD_LOG_ERR("Illegal device req 0x%02x\r\n", setup->bRequest);
+            ret = false;
+            break;
+    }
+
+    return ret;
+}
+
+/**
+ * @brief handle a standard interface request
+ *
+ * @param [in]     setup    The setup packet
+ * @param [in,out] len      Pointer to data length
+ * @param [in]     ep0_data_buf Data buffer
+ *
+ * @return true if the request was handled successfully
+ */
+static bool usbd_std_interface_req_handler(struct usb_setup_packet *setup,
+                                           uint8_t **data, uint32_t *len)
+{
+    /** The device must be configured to accept standard interface
+     * requests and the addressed Interface must be valid.
+     */
+    if (!is_device_configured() ||
+        (!is_interface_valid((uint8_t)setup->wIndex))) {
+        return false;
+    }
+
+    switch (setup->bRequest) {
+        case USB_REQUEST_GET_STATUS:
+            /* no bits specified */
+            *data = (uint8_t *)&usbd_core_cfg.remote_wakeup;
+
+            *len = 2;
+            break;
+
+        case USB_REQUEST_CLEAR_FEATURE:
+        case USB_REQUEST_SET_FEATURE:
+            /* not defined for interface */
+            return false;
+
+        case USB_REQUEST_GET_INTERFACE:
+            /** This handler is called for classes that does not support
+             * alternate Interfaces so always return 0. Classes that
+             * support alternative interfaces handles GET_INTERFACE
+             * in custom_handler.
+             */
+            *data = (uint8_t *)&usbd_core_cfg.reserved;
+
+            *len = 1;
+            break;
+
+        case USB_REQUEST_SET_INTERFACE:
+            USBD_LOG_DBG("REQ_SET_INTERFACE\r\n");
+            usbd_set_interface(setup->wIndex, setup->wValue);
+            break;
+
+        default:
+            USBD_LOG_ERR("Illegal interface req 0x%02x\r\n", setup->bRequest);
+            return false;
+    }
+
+    return true;
+}
+
+/**
+ * @brief handle a standard endpoint request
+ *
+ * @param [in]     setup    The setup packet
+ * @param [in,out] len      Pointer to data length
+ * @param [in]     ep0_data_buf Data buffer
+ *
+ * @return true if the request was handled successfully
+ */
+static bool usbd_std_endpoint_req_handler(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len)
+{
+    uint8_t ep = (uint8_t)setup->wIndex;
+
+    /* Check if request addresses valid Endpoint */
+    if (!is_ep_valid(ep)) {
+        return false;
+    }
+
+    switch (setup->bRequest) {
+        case USB_REQUEST_GET_STATUS:
+
+            /** This request is valid for Control Endpoints when
+             * the device is not yet configured. For other
+             * Endpoints the device must be configured.
+             * Firstly check if addressed ep is Control Endpoint.
+             * If no then the device must be in Configured state
+             * to accept the request.
+             */
+            if (((ep & 0x7f) == 0) || is_device_configured()) {
+                /* bit 0 - Endpoint halted or not */
+                usbd_ep_is_stalled(ep, (uint8_t *)&usbd_core_cfg.remote_wakeup);
+                *data = (uint8_t *)&usbd_core_cfg.remote_wakeup;
+
+                *len = 2;
+                break;
+            }
+
+            return false;
+
+        case USB_REQUEST_CLEAR_FEATURE:
+            if (setup->wValue == USB_FEATURE_ENDPOINT_STALL) {
+                /** This request is valid for Control Endpoints when
+                 * the device is not yet configured. For other
+                 * Endpoints the device must be configured.
+                 * Firstly check if addressed ep is Control Endpoint.
+                 * If no then the device must be in Configured state
+                 * to accept the request.
+                 */
+                if (((ep & 0x7f) == 0) || is_device_configured()) {
+                    USBD_LOG_ERR("ep:%x clear halt\r\n", ep);
+                    usbd_ep_clear_stall(ep);
+                    usbd_event_notify_handler(USB_EVENT_CLEAR_HALT, NULL);
+                    break;
+                }
+            }
+
+            /* only ENDPOINT_HALT defined for endpoints */
+            return false;
+
+        case USB_REQUEST_SET_FEATURE:
+            if (setup->wValue == USB_FEATURE_ENDPOINT_STALL) {
+                /** This request is valid for Control Endpoints when
+                 * the device is not yet configured. For other
+                 * Endpoints the device must be configured.
+                 * Firstly check if addressed ep is Control Endpoint.
+                 * If no then the device must be in Configured state
+                 * to accept the request.
+                 */
+                if (((ep & 0x7f) == 0) || is_device_configured()) {
+                    /* set HALT by stalling */
+                    USBD_LOG_ERR("ep:%x set halt\r\n", ep);
+                    usbd_ep_set_stall(ep);
+                    usbd_event_notify_handler(USB_EVENT_SET_HALT, NULL);
+                    break;
+                }
+            }
+
+            /* only ENDPOINT_HALT defined for endpoints */
+            return false;
+
+        case USB_REQUEST_SYNCH_FRAME:
+
+            /* For Synch Frame request the device must be configured */
+            if (is_device_configured()) {
+                /* Not supported, return false anyway */
+                USBD_LOG_DBG("ep req 0x%02x not implemented\r\n", setup->bRequest);
+            }
+
+            return false;
+
+        default:
+            USBD_LOG_ERR("Illegal ep req 0x%02x\r\n", setup->bRequest);
+            return false;
+    }
+
+    return true;
+}
+
+/**
+ * @brief default handler for standard ('chapter 9') requests
+ *
+ * If a custom request handler was installed, this handler is called first.
+ *
+ * @param [in]     setup    The setup packet
+ * @param [in]     ep0_data_buf Data buffer
+ * @param [in,out] len      Pointer to data length
+ *
+ * @return true if the request was handled successfully
+ */
+static int usbd_standard_request_handler(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len)
+{
+    int rc = 0;
+
+    switch (setup->bmRequestType_b.Recipient) {
+        case USB_REQUEST_TO_DEVICE:
+            if (usbd_std_device_req_handler(setup, data, len) == false) {
+                rc = -1;
+            }
+
+            break;
+
+        case USB_REQUEST_TO_INTERFACE:
+            if (usbd_std_interface_req_handler(setup, data, len) == false) {
+                rc = -1;
+            }
+
+            break;
+
+        case USB_REQUEST_TO_ENDPOINT:
+            if (usbd_std_endpoint_req_handler(setup, data, len) == false) {
+                rc = -1;
+            }
+
+            break;
+
+        default:
+            rc = -1;
+    }
+
+    return rc;
+}
+
+/*
+ * The functions usbd_class_request_handler(), usbd_custom_request_handler() and usbd_vendor_request_handler()
+ * go through the interfaces one after the other and compare the
+ * bInterfaceNumber with the wIndex and and then call the appropriate
+ * callback of the USB function.
+ * Note, a USB function can have more than one interface and the
+ * request does not have to be directed to the first interface (unlikely).
+ * These functions can be simplified and moved to usb_handle_request()
+ * when legacy initialization throgh the usb_set_config() and
+ * usb_enable() is no longer needed.
+ */
+static int usbd_class_request_handler(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len)
+{
+    USBD_LOG_DBG("bRequest 0x%02x, wIndex 0x%04x\r\n", setup->bRequest, setup->wIndex);
+
+    if (setup->bmRequestType_b.Recipient != USB_REQUEST_TO_INTERFACE) {
+        return -1;
+    }
+
+    usb_slist_t *i, *j;
+    usb_slist_for_each(i, &usbd_class_head)
+    {
+        usbd_class_t *class = usb_slist_entry(i, struct usbd_class, list);
+
+        usb_slist_for_each(j, &class->intf_list)
+        {
+            usbd_interface_t *intf = usb_slist_entry(j, struct usbd_interface, list);
+
+            if (intf->class_handler && (intf->intf_num == (setup->wIndex & 0xFF))) {
+                return intf->class_handler(setup, data, len);
+            }
+        }
+    }
+    return -1;
+}
+
+static int usbd_vendor_request_handler(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len)
+{
+    USBD_LOG_DBG("bRequest 0x%02x, wValue0x%04x, wIndex 0x%04x\r\n", setup->bRequest, setup->wValue, setup->wIndex);
+
+    // if(setup->bmRequestType_b.Recipient != USB_REQUEST_TO_DEVICE)
+    // {
+    //     return -1;
+    // }
+
+    if (msosv1_desc) {
+        if (setup->bRequest == msosv1_desc->vendor_code) {
+            switch (setup->wIndex) {
+                case 0x04:
+                    USBD_LOG_INFO("get Compat ID\r\n");
+                    *data = (uint8_t *)msosv1_desc->compat_id;
+                    *len = msosv1_desc->compat_id_len;
+
+                    return 0;
+                case 0x05:
+                    USBD_LOG_INFO("get Compat id properties\r\n");
+                    *data = (uint8_t *)msosv1_desc->comp_id_property;
+                    *len = msosv1_desc->comp_id_property_len;
+
+                    return 0;
+                default:
+                    USBD_LOG_ERR("unknown vendor code\r\n");
+                    return -1;
+            }
+        }
+    } else if (msosv2_desc) {
+        if (setup->bRequest == msosv2_desc->vendor_code) {
+            switch (setup->wIndex) {
+                case WINUSB_REQUEST_GET_DESCRIPTOR_SET:
+                    USBD_LOG_INFO("GET MS OS 2.0 Descriptor\r\n");
+                    *data = (uint8_t *)msosv2_desc->compat_id;
+                    *len = msosv2_desc->compat_id_len;
+                    return 0;
+                default:
+                    USBD_LOG_ERR("unknown vendor code\r\n");
+                    return -1;
+            }
+        }
+    }
+
+    usb_slist_t *i, *j;
+
+    usb_slist_for_each(i, &usbd_class_head)
+    {
+        usbd_class_t *class = usb_slist_entry(i, struct usbd_class, list);
+
+        usb_slist_for_each(j, &class->intf_list)
+        {
+            usbd_interface_t *intf = usb_slist_entry(j, struct usbd_interface, list);
+
+            if (intf->vendor_handler && !intf->vendor_handler(setup, data, len)) {
+                return 0;
+            }
+        }
+    }
+
+    return -1;
+}
+
+static int usbd_custom_request_handler(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len)
+{
+    USBD_LOG_DBG("bRequest 0x%02x, wIndex 0x%04x\r\n", setup->bRequest, setup->wIndex);
+
+    if (setup->bmRequestType_b.Recipient != USB_REQUEST_TO_INTERFACE) {
+        return -1;
+    }
+
+    usb_slist_t *i, *j;
+    usb_slist_for_each(i, &usbd_class_head)
+    {
+        usbd_class_t *class = usb_slist_entry(i, struct usbd_class, list);
+
+        usb_slist_for_each(j, &class->intf_list)
+        {
+            usbd_interface_t *intf = usb_slist_entry(j, struct usbd_interface, list);
+
+            if (intf->custom_handler && (intf->intf_num == (setup->wIndex & 0xFF))) {
+                return intf->custom_handler(setup, data, len);
+            }
+        }
+    }
+
+    return -1;
+}
+
+/**
+ * @brief handle a request by calling one of the installed request handlers
+ *
+ * Local function to handle a request by calling one of the installed request
+ * handlers. In case of data going from host to device, the data is at *ppbData.
+ * In case of data going from device to host, the handler can either choose to
+ * write its data at *ppbData or update the data pointer.
+ *
+ * @param [in]     setup The setup packet
+ * @param [in,out] data  Data buffer
+ * @param [in,out] len   Pointer to data length
+ *
+ * @return true if the request was handles successfully
+ */
+static bool usbd_setup_request_handler(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len)
+{
+    uint8_t type = setup->bmRequestType_b.Type;
+
+    if (type == USB_REQUEST_STANDARD) {
+        if (!usbd_custom_request_handler(setup, data, len)) {
+            return true;
+        }
+
+        if (usbd_standard_request_handler(setup, data, len) < 0) {
+            USBD_LOG_ERR("Handler Error %d\r\n", type);
+            usbd_print_setup(setup);
+            return false;
+        }
+    } else if (type == USB_REQUEST_CLASS) {
+        if (usbd_class_request_handler(setup, data, len) < 0) {
+            USBD_LOG_ERR("Handler Error %d\r\n", type);
+            usbd_print_setup(setup);
+            return false;
+        }
+    } else if (type == USB_REQUEST_VENDOR) {
+        if (usbd_vendor_request_handler(setup, data, len) < 0) {
+            USBD_LOG_ERR("Handler Error %d\r\n", type);
+            usbd_print_setup(setup);
+            return false;
+        }
+    } else {
+        return false;
+    }
+
+    return true;
+}
+/**
+ * @brief send data or status to host
+ *
+ * @return N/A
+ */
+static void usbd_send_to_host(uint16_t len)
+{
+    uint32_t chunk = 0U;
+
+    if (usbd_core_cfg.zlp_flag == false) {
+        chunk = usbd_core_cfg.ep0_data_buf_residue;
+
+        if (usbd_ep_write(USB_CONTROL_IN_EP0, usbd_core_cfg.ep0_data_buf, usbd_core_cfg.ep0_data_buf_residue, &chunk) < 0) {
+            USBD_LOG_ERR("USB write data failed\r\n");
+            return;
+        }
+
+        usbd_core_cfg.ep0_data_buf += chunk;
+        usbd_core_cfg.ep0_data_buf_residue -= chunk;
+
+        /*
+         * Set ZLP flag when host asks for a bigger length and the
+         * last chunk is wMaxPacketSize long, to indicate the last
+         * packet.
+         */
+        if ((!usbd_core_cfg.ep0_data_buf_residue) && (usbd_core_cfg.ep0_data_buf_len >= USB_CTRL_EP_MPS) && !(usbd_core_cfg.ep0_data_buf_len % USB_CTRL_EP_MPS)) {
+            /* Transfers a zero-length packet next*/
+            usbd_core_cfg.zlp_flag = true;
+        }
+    } else {
+        usbd_core_cfg.zlp_flag = false;
+        USBD_LOG_DBG("send zlp\r\n");
+        if (usbd_ep_write(USB_CONTROL_IN_EP0, NULL, 0, NULL) < 0) {
+            USBD_LOG_ERR("USB write zlp failed\r\n");
+            return;
+        }
+    }
+}
+
+static void usbd_ep0_setup_handler(void)
+{
+    struct usb_setup_packet *setup = &usbd_core_cfg.setup;
+
+    /*
+    * OUT transfer, Setup packet,
+    * reset request message state machine
+    */
+    if (usbd_ep_read(USB_CONTROL_OUT_EP0, (uint8_t *)setup,
+                     sizeof(struct usb_setup_packet), NULL) < 0) {
+        USBD_LOG_ERR("Read Setup Packet failed\r\n");
+        usbd_ep_set_stall(USB_CONTROL_IN_EP0);
+        return;
+    }
+
+    //usbd_print_setup(setup);
+
+    if (setup->wLength > USB_REQUEST_BUFFER_SIZE) {
+        if (setup->bmRequestType_b.Dir != USB_REQUEST_DEVICE_TO_HOST) {
+            USBD_LOG_ERR("Request buffer too small\r\n");
+            usbd_ep_set_stall(USB_CONTROL_IN_EP0);
+            return;
+        }
+    }
+
+    // usbd_core_cfg.ep0_data_buf = usbd_core_cfg.req_data;
+    usbd_core_cfg.ep0_data_buf_residue = setup->wLength;
+    usbd_core_cfg.ep0_data_buf_len = setup->wLength;
+    usbd_core_cfg.zlp_flag = false;
+
+    /* this maybe set code in class request code  */
+    if (setup->wLength &&
+        setup->bmRequestType_b.Dir == USB_REQUEST_HOST_TO_DEVICE) {
+        USBD_LOG_DBG("prepare to out data\r\n");
+        return;
+    }
+
+    /* Ask installed handler to process request */
+    if (!usbd_setup_request_handler(setup, &usbd_core_cfg.ep0_data_buf, &usbd_core_cfg.ep0_data_buf_len)) {
+        USBD_LOG_ERR("usbd_setup_request_handler failed\r\n");
+        usbd_ep_set_stall(USB_CONTROL_IN_EP0);
+        return;
+    }
+
+    /* Send smallest of requested and offered length */
+    usbd_core_cfg.ep0_data_buf_residue = MIN(usbd_core_cfg.ep0_data_buf_len,
+                                             setup->wLength);
+    /*Send data or status to host*/
+    usbd_send_to_host(setup->wLength);
+}
+
+static void usbd_ep0_out_handler(void)
+{
+    uint32_t chunk = 0U;
+    struct usb_setup_packet *setup = &usbd_core_cfg.setup;
+
+    /* OUT transfer, status packets */
+    if (usbd_core_cfg.ep0_data_buf_residue == 0) {
+        /* absorb zero-length status message */
+        USBD_LOG_DBG("recv status\r\n");
+
+        if (usbd_ep_read(USB_CONTROL_OUT_EP0,
+                         NULL,
+                         0, NULL) < 0) {
+            USBD_LOG_ERR("Read DATA Packet failed\r\n");
+            usbd_ep_set_stall(USB_CONTROL_IN_EP0);
+        }
+
+        return;
+    }
+
+    usbd_core_cfg.ep0_data_buf = usbd_core_cfg.req_data;
+
+    /* OUT transfer, data packets */
+    if (usbd_ep_read(USB_CONTROL_OUT_EP0,
+                     usbd_core_cfg.ep0_data_buf,
+                     usbd_core_cfg.ep0_data_buf_residue, &chunk) < 0) {
+        USBD_LOG_ERR("Read DATA Packet failed\r\n");
+        usbd_ep_set_stall(USB_CONTROL_IN_EP0);
+        return;
+    }
+
+    usbd_core_cfg.ep0_data_buf += chunk;
+    usbd_core_cfg.ep0_data_buf_residue -= chunk;
+
+    if (usbd_core_cfg.ep0_data_buf_residue == 0) {
+        /* Received all, send data to handler */
+        usbd_core_cfg.ep0_data_buf = usbd_core_cfg.req_data;
+
+        if (!usbd_setup_request_handler(setup, &usbd_core_cfg.ep0_data_buf, &usbd_core_cfg.ep0_data_buf_len)) {
+            USBD_LOG_ERR("usbd_setup_request_handler1 failed\r\n");
+            usbd_ep_set_stall(USB_CONTROL_IN_EP0);
+            return;
+        }
+
+        /*Send status to host*/
+        usbd_send_to_host(setup->wLength);
+    } else {
+        USBD_LOG_ERR("ep0_data_buf_residue is not zero\r\n");
+    }
+}
+
+static void usbd_ep0_in_handler(void)
+{
+    struct usb_setup_packet *setup = &usbd_core_cfg.setup;
+
+    /* Send more data if available */
+    if (usbd_core_cfg.ep0_data_buf_residue != 0 || usbd_core_cfg.zlp_flag == true) {
+        usbd_send_to_host(setup->wLength);
+    } else {
+        /*ep0 tx has completed,and no data to send,so do nothing*/
+    }
+}
+
+static void usbd_ep_out_handler(uint8_t ep)
+{
+#if USBD_EP_CALLBACK_SEARCH_METHOD == 0
+    usb_slist_t *i, *j, *k;
+    usb_slist_for_each(i, &usbd_class_head)
+    {
+        usbd_class_t *class = usb_slist_entry(i, struct usbd_class, list);
+
+        usb_slist_for_each(j, &class->intf_list)
+        {
+            usbd_interface_t *intf = usb_slist_entry(j, struct usbd_interface, list);
+
+            usb_slist_for_each(k, &intf->ep_list)
+            {
+                usbd_endpoint_t *ept = usb_slist_entry(k, struct usbd_endpoint, list);
+
+                if ((ept->ep_addr == ep) && ept->ep_cb) {
+                    ept->ep_cb(ep);
+                }
+            }
+        }
+    }
+#else
+
+    if (usbd_core_cfg.out_ep_cb[ep & 0x7f]) {
+        usbd_core_cfg.out_ep_cb[ep & 0x7f](ep);
+    }
+
+#endif
+}
+
+static void usbd_ep_in_handler(uint8_t ep)
+{
+#if USBD_EP_CALLBACK_SEARCH_METHOD == 0
+    usb_slist_t *i, *j, *k;
+    usb_slist_for_each(i, &usbd_class_head)
+    {
+        usbd_class_t *class = usb_slist_entry(i, struct usbd_class, list);
+
+        usb_slist_for_each(j, &class->intf_list)
+        {
+            usbd_interface_t *intf = usb_slist_entry(j, struct usbd_interface, list);
+
+            usb_slist_for_each(k, &intf->ep_list)
+            {
+                usbd_endpoint_t *ept = usb_slist_entry(k, struct usbd_endpoint, list);
+
+                if ((ept->ep_addr == ep) && ept->ep_cb) {
+                    ept->ep_cb(ep);
+                }
+            }
+        }
+    }
+#else
+
+    if (usbd_core_cfg.in_ep_cb[ep & 0x7f]) {
+        usbd_core_cfg.in_ep_cb[ep & 0x7f](ep);
+    }
+
+#endif
+}
+
+static void usbd_class_event_notify_handler(uint8_t event, void *arg)
+{
+    usb_slist_t *i, *j;
+    usb_slist_for_each(i, &usbd_class_head)
+    {
+        usbd_class_t *class = usb_slist_entry(i, struct usbd_class, list);
+
+        usb_slist_for_each(j, &class->intf_list)
+        {
+            usbd_interface_t *intf = usb_slist_entry(j, struct usbd_interface, list);
+
+            if (intf->notify_handler) {
+                intf->notify_handler(event, arg);
+            }
+        }
+    }
+}
+
+void usbd_event_notify_handler(uint8_t event, void *arg)
+{
+    switch (event) {
+        case USB_EVENT_RESET:
+            usbd_set_address(0);
+#if USBD_EP_CALLBACK_SEARCH_METHOD == 1
+            usbd_ep_callback_register();
+#endif
+
+        case USB_EVENT_ERROR:
+        case USB_EVENT_SOF:
+        case USB_EVENT_CONNECTED:
+        case USB_EVENT_CONFIGURED:
+        case USB_EVENT_SUSPEND:
+        case USB_EVENT_DISCONNECTED:
+        case USB_EVENT_RESUME:
+        case USB_EVENT_SET_INTERFACE:
+        case USB_EVENT_SET_REMOTE_WAKEUP:
+        case USB_EVENT_CLEAR_REMOTE_WAKEUP:
+        case USB_EVENT_SET_HALT:
+        case USB_EVENT_CLEAR_HALT:
+            usbd_class_event_notify_handler(event, arg);
+            break;
+
+        case USB_EVENT_SETUP_NOTIFY:
+            usbd_ep0_setup_handler();
+            break;
+
+        case USB_EVENT_EP0_IN_NOTIFY:
+            usbd_ep0_in_handler();
+            break;
+
+        case USB_EVENT_EP0_OUT_NOTIFY:
+            usbd_ep0_out_handler();
+            break;
+
+        case USB_EVENT_EP_IN_NOTIFY:
+            usbd_ep_in_handler((uint32_t)arg);
+            break;
+
+        case USB_EVENT_EP_OUT_NOTIFY:
+            usbd_ep_out_handler((uint32_t)arg);
+            break;
+
+        default:
+            USBD_LOG_ERR("USB unknown event: %d\r\n", event);
+            break;
+    }
+}
+
+void usbd_desc_register(const uint8_t *desc)
+{
+    usbd_core_cfg.descriptors = desc;
+}
+/* Register MS OS Descriptors version 1 */
+void usbd_msosv1_desc_register(struct usb_msosv1_descriptor *desc)
+{
+    msosv1_desc = desc;
+}
+
+/* Register MS OS Descriptors version 2 */
+void usbd_msosv2_desc_register(struct usb_msosv2_descriptor *desc)
+{
+    msosv2_desc = desc;
+}
+
+void usbd_bos_desc_register(struct usb_bos_descriptor *desc)
+{
+    bos_desc = desc;
+}
+
+void usbd_class_register(usbd_class_t *class)
+{
+    usb_slist_add_tail(&usbd_class_head, &class->list);
+    usb_slist_init(&class->intf_list);
+}
+
+void usbd_class_add_interface(usbd_class_t *class, usbd_interface_t *intf)
+{
+    static uint8_t intf_offset = 0;
+    intf->intf_num = intf_offset;
+    usb_slist_add_tail(&class->intf_list, &intf->list);
+    usb_slist_init(&intf->ep_list);
+    intf_offset++;
+}
+
+void usbd_interface_add_endpoint(usbd_interface_t *intf, usbd_endpoint_t *ep)
+{
+    usb_slist_add_tail(&intf->ep_list, &ep->list);
+}
+
+bool usb_device_is_configured(void)
+{
+    return usbd_core_cfg.configured;
+}
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/core/usbd_core.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/core/usbd_core.h
new file mode 100644
index 00000000..6884a76e
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/usb_stack/core/usbd_core.h
@@ -0,0 +1,138 @@
+/**
+ * @file usbd_core.h
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef _USBD_CORE_H
+#define _USBD_CORE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "usb_util.h"
+#include "usb_def.h"
+#include "usb_dc.h"
+
+enum usb_event_type {
+    /** USB error reported by the controller */
+    USB_EVENT_ERROR,
+    /** USB reset */
+    USB_EVENT_RESET,
+    /** Start of Frame received */
+    USB_EVENT_SOF,
+    /** USB connection established, hardware enumeration is completed */
+    USB_EVENT_CONNECTED,
+    /** USB configuration done */
+    USB_EVENT_CONFIGURED,
+    /** USB connection suspended by the HOST */
+    USB_EVENT_SUSPEND,
+    /** USB connection lost */
+    USB_EVENT_DISCONNECTED,
+    /** USB connection resumed by the HOST */
+    USB_EVENT_RESUME,
+
+    /** USB interface selected */
+    USB_EVENT_SET_INTERFACE,
+    /** USB interface selected */
+    USB_EVENT_SET_REMOTE_WAKEUP,
+    /** USB interface selected */
+    USB_EVENT_CLEAR_REMOTE_WAKEUP,
+    /** Set Feature ENDPOINT_HALT received */
+    USB_EVENT_SET_HALT,
+    /** Clear Feature ENDPOINT_HALT received */
+    USB_EVENT_CLEAR_HALT,
+    /** setup packet received */
+    USB_EVENT_SETUP_NOTIFY,
+    /** ep0 in packet received */
+    USB_EVENT_EP0_IN_NOTIFY,
+    /** ep0 out packet received */
+    USB_EVENT_EP0_OUT_NOTIFY,
+    /** ep in packet except ep0 received */
+    USB_EVENT_EP_IN_NOTIFY,
+    /** ep out packet except ep0 received */
+    USB_EVENT_EP_OUT_NOTIFY,
+    /** Initial USB connection status */
+    USB_EVENT_UNKNOWN
+};
+
+/**
+ * @brief Callback function signature for the USB Endpoint status
+ */
+typedef void (*usbd_endpoint_callback)(uint8_t ep);
+
+/**
+ * @brief Callback function signature for class specific requests
+ *
+ * Function which handles Class specific requests corresponding to an
+ * interface number specified in the device descriptor table. For host
+ * to device direction the 'len' and 'payload_data' contain the length
+ * of the received data and the pointer to the received data respectively.
+ * For device to host class requests, 'len' and 'payload_data' should be
+ * set by the callback function with the length and the address of the
+ * data to be transmitted buffer respectively.
+ */
+typedef int (*usbd_request_handler)(struct usb_setup_packet *setup,
+                                    uint8_t **data, uint32_t *transfer_len);
+
+/* callback function pointer structure for Application to handle events */
+typedef void (*usbd_notify_handler)(uint8_t event, void *arg);
+
+typedef struct usbd_endpoint {
+    usb_slist_t list;
+    uint8_t ep_addr;
+    usbd_endpoint_callback ep_cb;
+} usbd_endpoint_t;
+
+typedef struct usbd_interface {
+    usb_slist_t list;
+    /** Handler for USB Class specific Control (EP 0) communications */
+    usbd_request_handler class_handler;
+    /** Handler for USB Vendor specific commands */
+    usbd_request_handler vendor_handler;
+    /** Handler for USB custom specific commands */
+    usbd_request_handler custom_handler;
+    /** Handler for USB event notify commands */
+    usbd_notify_handler notify_handler;
+    uint8_t intf_num;
+    usb_slist_t ep_list;
+} usbd_interface_t;
+
+typedef struct usbd_class {
+    usb_slist_t list;
+    const char *name;
+    usb_slist_t intf_list;
+} usbd_class_t;
+
+void usbd_event_notify_handler(uint8_t event, void *arg);
+
+void usbd_desc_register(const uint8_t *desc);
+void usbd_class_register(usbd_class_t *class);
+void usbd_msosv1_desc_register(struct usb_msosv1_descriptor *desc);
+void usbd_msosv2_desc_register(struct usb_msosv2_descriptor *desc);
+void usbd_bos_desc_register(struct usb_bos_descriptor *desc);
+void usbd_class_add_interface(usbd_class_t *class, usbd_interface_t *intf);
+void usbd_interface_add_endpoint(usbd_interface_t *intf, usbd_endpoint_t *ep);
+bool usb_device_is_configured(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/CMakeLists.txt b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/CMakeLists.txt
new file mode 100644
index 00000000..30acb40b
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/CMakeLists.txt
@@ -0,0 +1,64 @@
+################# Add global include #################
+list(APPEND ADD_INCLUDE
+"${CMAKE_CURRENT_SOURCE_DIR}/hal_drv/inc"
+"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/inc"
+"${CMAKE_CURRENT_SOURCE_DIR}/regs"
+"${CMAKE_CURRENT_SOURCE_DIR}/startup"
+"${CMAKE_CURRENT_SOURCE_DIR}"
+)
+#######################################################
+
+################# Add private include #################
+list(APPEND ADD_PRIVATE_INCLUDE
+"${CMAKE_CURRENT_SOURCE_DIR}/hal_drv/default_config"
+)
+#######################################################
+
+############## Add current dir source files ###########
+file(GLOB_RECURSE sources
+"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/*.c"
+"${CMAKE_CURRENT_SOURCE_DIR}/hal_drv/src/*.c"
+"${CMAKE_CURRENT_SOURCE_DIR}/startup/interrupt.c"
+"${CMAKE_CURRENT_SOURCE_DIR}/startup/system_bl702.c"
+"${CMAKE_CURRENT_SOURCE_DIR}/startup/GCC/entry.S"
+"${CMAKE_CURRENT_SOURCE_DIR}/startup/GCC/start_load.c"
+)
+list(APPEND ADD_SRCS  ${sources})
+# aux_source_directory(src ADD_SRCS)
+list(REMOVE_ITEM ADD_SRCS "${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/bl702_snflash.c"
+"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/bl702_romdriver.c"
+"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/bl702_clock.c"
+)
+#######################################################
+
+########### Add required/dependent components #########
+list(APPEND ADD_REQUIREMENTS common)
+#######################################################
+
+############ Add static libs ##########################
+#list(APPEND ADD_STATIC_LIB "lib/libtest.a")
+#######################################################
+
+############ Add dynamic libs #########################
+# list(APPEND ADD_DYNAMIC_LIB "lib/arch/v831/libmaix_nn.so"
+#                             "lib/arch/v831/libmaix_cam.so"
+# )
+#######################################################
+
+############ Add global compile option ################
+#add components denpend on this component
+if(CONFIG_ROMAPI)
+list(APPEND ADD_DEFINITIONS -DBFLB_USE_ROM_DRIVER)
+endif()
+if(CONFIG_HALAPI)
+list(APPEND ADD_DEFINITIONS -DBFLB_USE_HAL_DRIVER)
+endif()
+list(APPEND ADD_DEFINITIONS -DARCH_RISCV)
+#######################################################
+
+############ Add private compile option ################
+#add compile option for this component that won't affect other modules
+# list(APPEND ADD_PRIVATE_DEFINITIONS -DAAAAA=1)
+#######################################################
+
+generate_library()
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/bl702_flash.ld b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/bl702_flash.ld
new file mode 100644
index 00000000..3fb9b5ec
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/bl702_flash.ld
@@ -0,0 +1,299 @@
+/****************************************************************************************
+* @file bl702_flash.ld
+*
+* @brief This file is the map file (gnuarm or armgcc).
+*
+* Copyright (C) BouffaloLab 2021
+*
+****************************************************************************************
+*/
+
+/* configure the CPU type */
+OUTPUT_ARCH( "riscv" )
+/* link with the standard c library */
+/* INPUT(-lc) */
+/* link with the standard GCC library */
+/* INPUT(-lgcc) */
+/* configure the entry point */
+ENTRY(_enter)
+
+StackSize = 0x1000; /*  4KB */
+
+MEMORY
+{
+    xip_memory  (rx)  : ORIGIN = 0x23000000, LENGTH = 1022K /* 1024K, less the two pages we are using for settings and logo*/
+    itcm_memory (rx)  : ORIGIN = 0x22014000, LENGTH = 16K
+    dtcm_memory (rx)  : ORIGIN = 0x42018000, LENGTH = 16K
+    ram_memory  (!rx) : ORIGIN = 0x4201C000, LENGTH = 80K
+    hbn_memory  (rx)  : ORIGIN = 0x40010000, LENGTH = 0xE00     /* hbn ram 4K used 3.5K*/
+}
+
+SECTIONS
+{
+    PROVIDE(__metal_chicken_bit = 0);
+
+    .text :
+    {
+        . = ALIGN(4);
+        __text_code_start__ = .;
+
+        KEEP (*(.text.metal.init.enter))
+        KEEP (*(SORT_NONE(.init)))
+        /* section information for shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+
+        /* section information for usb desc */
+        . = ALIGN(4);
+        _usb_desc_start = .;
+        KEEP(*(usb_desc))
+        . = ALIGN(4);
+        _usb_desc_end = .;
+
+        *(.text)
+        *(.text.*)
+
+        /*put .rodata**/
+        *(EXCLUDE_FILE( *bl702_glb*.o* \
+                        *bl702_pds*.o* \
+                        *bl702_common*.o* \
+                        *bl702_sf_cfg*.o* \
+                        *bl702_sf_cfg_ext*.o* \
+                        *bl702_sf_ctrl*.o* \
+                        *bl702_sflash*.o* \
+                        *bl702_sflash_ext*.o* \
+                        *bl702_xip_sflash*.o* \
+                        *bl702_xip_sflash_ext*.o* \
+                        *bl702_ef_ctrl*.o*) .rodata*)
+
+        *(.srodata)
+        *(.srodata.*)
+
+        . = ALIGN(4);
+        __text_code_end__ = .;
+    } > xip_memory
+
+
+    .preinit_array  :
+    {
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP (*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+    } >xip_memory AT>xip_memory
+
+    .init_array     :
+    {
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+        KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+        PROVIDE_HIDDEN (__init_array_end = .);
+    } >xip_memory AT>xip_memory
+
+    .fini_array     :
+    {
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+        KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+    } >xip_memory AT>xip_memory
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+     * the constructors, so we make sure it is
+     * first.  Because this is a wildcard, it
+     * doesn't matter if the user does not
+     * actually link against crtbegin.o; the
+     * linker won't look for a file to match a
+     * wildcard.  The wildcard also means that it
+     * doesn't matter which directory crtbegin.o
+     * is in.
+     */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+     * the crtend.o file until after the sorted ctors.
+     * The .ctor section from the crtend file contains the
+     * end of ctors marker and it must be last
+     */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >xip_memory AT>xip_memory
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >xip_memory AT>xip_memory
+
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >xip_memory AT>xip_memory
+
+
+    . = ALIGN(4);
+    __itcm_load_addr = .;
+
+    .itcm_region : AT (__itcm_load_addr)
+    {
+        . = ALIGN(4);
+        __tcm_code_start__ = .;
+
+        *(.tcm_code.*)
+        *(.tcm_const.*)
+        *(.sclock_rlt_code.*)
+        *(.sclock_rlt_const.*)
+
+        *bl702_glb*.o*(.rodata*)
+        *bl702_pds*.o*(.rodata*)
+        *bl702_common*.o*(.rodata*)
+        *bl702_sf_cfg*.o*(.rodata*)
+        *bl702_sf_cfg_ext*.o*(.rodata*)
+        *bl702_sf_ctrl*.o*(.rodata*)
+        *bl702_sflash*.o*(.rodata*)
+        *bl702_sflash_ext*.o*(.rodata*)
+        *bl702_xip_sflash*.o*(.rodata*)
+        *bl702_xip_sflash_ext*.o*(.rodata*)
+        *bl702_ef_ctrl*.o*(.rodata*)
+
+        . = ALIGN(4);
+        __tcm_code_end__ = .;
+    } > itcm_memory
+
+    __hbn_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
+
+    .hbn_ram_region : AT (__hbn_load_addr)
+    {
+        . = ALIGN(4);
+        __hbn_ram_start__ = .;
+        *bl702_hbn_wakeup*.o*(.rodata*)
+        *(.hbn_ram_code*)
+        *(.hbn_ram_data)
+        . = ALIGN(4);
+        __hbn_ram_end__ = .;
+    } > hbn_memory
+
+    __dtcm_load_addr = __hbn_load_addr + SIZEOF(.hbn_ram_region);
+
+    .dtcm_region : AT (__dtcm_load_addr)
+    {
+        . = ALIGN(4);
+        __tcm_data_start__ = .;
+
+        *(.tcm_data)
+        /* *finger_print.o(.data*) */
+
+        . = ALIGN(4);
+        __tcm_data_end__ = .;
+    } > dtcm_memory
+
+    /*************************************************************************/
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (NOLOAD):
+    {
+        . = ALIGN(0x4);
+        . = . + StackSize;
+        . = ALIGN(0x4);
+    } > dtcm_memory
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
+    PROVIDE( __freertos_irq_stack_top = __StackTop);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
+    /*************************************************************************/
+
+    __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
+
+    .system_ram_data_region : AT (__system_ram_load_addr)
+    {
+        . = ALIGN(4);
+        __system_ram_data_start__ = .;
+
+        *(.system_ram)
+
+        . = ALIGN(4);
+        __system_ram_data_end__ = .;
+    } > ram_memory
+
+    __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
+
+    /* Data section */
+    RAM_DATA : AT (__ram_load_addr)
+    {
+        . = ALIGN(4);
+        __ram_data_start__ = .;
+
+        PROVIDE( __global_pointer$ = . + 0x800 );
+
+        *(.data)
+        *(.data.*)
+        *(.sdata)
+        *(.sdata.*)
+        *(.sdata2)
+        *(.sdata2.*)
+
+        . = ALIGN(4);
+        __ram_data_end__ = .;
+    } > ram_memory
+
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+
+        *(.bss*)
+        *(.sbss*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > ram_memory
+
+    .noinit_data (NOLOAD) :
+    {
+        . = ALIGN(4);
+        __noinit_data_start__ = .;
+
+        *(.noinit_data*)
+
+        . = ALIGN(4);
+        __noinit_data_end__ = .;
+    } > ram_memory
+
+    .heap (NOLOAD):
+    {
+        . = ALIGN(4);
+        __HeapBase = .;
+
+        KEEP(*(.heap*))
+
+        . = ALIGN(4);
+        __HeapLimit = .;
+    } > ram_memory
+
+    PROVIDE (__heap_min_size = 0x400);
+    __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
+
+    ASSERT((__HeapLimit -  __HeapBase ) >= __heap_min_size, "heap size is too short.")
+
+}
+
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/cpu_flags.cmake b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/cpu_flags.cmake
new file mode 100644
index 00000000..484d5b28
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/cpu_flags.cmake
@@ -0,0 +1,11 @@
+SET(CPU_ARCH "RISCV")
+SET(MCPU "riscv-e24")
+SET(MARCH "rv32imafc")
+SET(MABI "ilp32f")
+
+list(APPEND GLOBAL_C_FLAGS -march=${MARCH} -mabi=${MABI})
+list(APPEND GLOBAL_LD_FLAGS -march=${MARCH} -mabi=${MABI})
+
+SET(LINKER_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/bl702_flash.ld)
+SET(RAM_LINKER_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/bl702_ram.ld)
+SET(BOOT2_LINKER_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/blsp_boot2_iap_flash.ld)
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/adc_config.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/adc_config.h
new file mode 100644
index 00000000..e0350e01
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/adc_config.h
@@ -0,0 +1,17 @@
+#ifndef _ADC_CONFIG_H
+#define _ADC_CONFIG_H
+
+#define ADC_DATA_WIDIH_12 (0)
+
+#define ADC_V18_SELECT (2) /*!< ADC 1.8V select */
+#define ADC_V11_SELECT (1) /*!< ADC 1.1V select */
+
+#define ADC_PGA_VCM          (0) /*!< ADC VCM value */
+#define ADC_PGA_GAIN1        (0) /*!< PGA gain 1 */
+#define ADC_PGA_GAIN2        (0) /*!< PGA gain 2 */
+#define ADC_CHOP_MODE        (2) /*!< ADC chop mode select */
+#define ADC_BIAS_SELECT      (0) /*!< ADC current form main bandgap or aon bandgap */
+#define ADC_OFFSET_CALIB_EN  (0) /*!< Offset calibration enable */
+#define ADC_OFFSER_CALIB_VAL (0) /*!< Offset calibration value */
+
+#endif
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/dac_config.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/dac_config.h
new file mode 100644
index 00000000..2a1e81db
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/dac_config.h
@@ -0,0 +1,7 @@
+#ifndef _DAC_CONFIG_H
+#define _DAC_CONFIG_H
+
+#define DAC_REF_SEL      (0)
+#define DAC_EXT_REF_GPIO (7)
+
+#endif
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/i2s_config.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/i2s_config.h
new file mode 100644
index 00000000..44691dc7
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/i2s_config.h
@@ -0,0 +1,11 @@
+#ifndef _I2S_CONFIG_H
+#define _I2S_CONFIG_H
+
+#define I2S_ADUIO_PLL_DEFAULT AUDIO_PLL_12288000_HZ
+#define I2S_DATA_ENDIAN       I2S_DATA_ENDIAN_MSB
+#define I2S_MONO_CHANNEL      I2S_RX_MONO_MODE_RIGHT_CHANNEL
+#define I2S_LR_EXCHANGE       DISABLE /*The position of L/R channel data within each entry is exchanged if enabled*/
+#define I2S_FS_INVERT         DISABLE
+#define I2S_BCLK_INVERT       DISABLE
+
+#endif
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/uart_config.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/uart_config.h
new file mode 100644
index 00000000..4a31ddd3
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/uart_config.h
@@ -0,0 +1,16 @@
+#ifndef _UART_CONFIG_H
+#define _UART_CONFIG_H
+
+#define UART_CTS_FLOWCONTROL_ENABLE  (0)
+#define UART_RTS_FLOWCONTROL_ENABLE  (0)
+#define UART_RX_DEGLITCH_ENABLE      (0)
+#define UART_MSB_FIRST_ENABLE        (0)
+#define UART_TX_SWCONTROL_ENABLE     (0)
+#define UART_TX_LINMODE_ENABLE       (0)
+#define UART_RX_LINMODE_ENABLE       (0)
+#define UART_TX_BREAKBIT_CNT         (0)
+
+#define UART_FIFO_MAX_LEN        128
+#define UART_DEFAULT_RTO_TIMEOUT 100
+
+#endif
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_adc.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_adc.h
new file mode 100644
index 00000000..d4e84258
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_adc.h
@@ -0,0 +1,185 @@
+/**
+ * @file hal_adc.h
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef __HAL_ADC__H__
+#define __HAL_ADC__H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "hal_common.h"
+#include "drv_device.h"
+#include "bl702_config.h"
+
+#define DEVICE_CTRL_ADC_CHANNEL_START  0x10
+#define DEVICE_CTRL_ADC_CHANNEL_STOP   0x11
+#define DEVICE_CTRL_ADC_CHANNEL_CONFIG 0x12
+#define DEVICE_CTRL_ADC_VBAT_ON        0x13
+#define DEVICE_CTRL_ADC_VBAT_OFF       0x14
+#define DEVICE_CTRL_ADC_TSEN_ON        0x15
+#define DEVICE_CTRL_ADC_TSEN_OFF       0x16
+#define DEVICE_CTRL_ADC_DATA_PARSE     0x17
+
+enum adc_index_type {
+#ifdef BSP_USING_ADC0
+    ADC0_INDEX,
+#endif
+    ADC_MAX_INDEX
+};
+
+#define adc_channel_start(dev)        device_control(dev, DEVICE_CTRL_ADC_CHANNEL_START, NULL)
+#define adc_channel_stop(dev)         device_control(dev, DEVICE_CTRL_ADC_CHANNEL_STOP, NULL)
+#define adc_channel_config(dev, list) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_CONFIG, list)
+
+typedef enum {
+    ADC_CHANNEL0,          /* ADC channel 0 */
+    ADC_CHANNEL1,          /* ADC channel 1 */
+    ADC_CHANNEL2,          /* ADC channel 2 */
+    ADC_CHANNEL3,          /* ADC channel 3 */
+    ADC_CHANNEL4,          /* ADC channel 4 */
+    ADC_CHANNEL5,          /* ADC channel 5 */
+    ADC_CHANNEL6,          /* ADC channel 6 */
+    ADC_CHANNEL7,          /* ADC channel 7 */
+    ADC_CHANNEL8,          /* ADC channel 8 */
+    ADC_CHANNEL9,          /* ADC channel 9 */
+    ADC_CHANNEL10,         /* ADC channel 10 */
+    ADC_CHANNEL11,         /* ADC channel 11 */
+    ADC_CHANNEL_DAC_OUTA,  /* DACA, ADC channel 12 */
+    ADC_CHANNEL_DAC_OUTB,  /* DACB, ADC channel 13 */
+    ADC_CHANNEL_TSEN_P,    /* TSenp, ADC channel 14 */
+    ADC_CHANNEL_TSEN_N,    /* TSenn, ADC channel 15 */
+    ADC_CHANNEL_VREF,      /* Vref, ADC channel 16 */
+    ADC_CHANNEL_DCTEST,    /* DCTest, ADC channel 17 */
+    ADC_CHANNEL_VABT_HALF, /* VBAT/2, ADC channel 18 */
+    ADC_CHANNEL_SENP3,     /* SenVP3, ADC channel 19 */
+    ADC_CHANNEL_SENP2,     /* SenVP2, ADC channel 20 */
+    ADC_CHANNEL_SENP1,     /* SenVP1, ADC channel 21 */
+    ADC_CHANNEL_SENP0,     /* SenVP0, ADC channel 22 */
+    ADC_CHANNEL_GND,       /* GND, ADC channel 23 */
+} adc_channel_t;
+
+typedef enum {
+    ADC_CLOCK_DIV_1,  /*!< ADC clock:on 32M clock is 32M */
+    ADC_CLOCK_DIV_4,  /*!< ADC clock:on 32M clock is 8M */
+    ADC_CLOCK_DIV_8,  /*!< ADC clock:on 32M clock is 4M */
+    ADC_CLOCK_DIV_12, /*!< ADC clock:on 32M clock is 2.666M */
+    ADC_CLOCK_DIV_16, /*!< ADC clock:on 32M clock is 2M */
+    ADC_CLOCK_DIV_20, /*!< ADC clock:on 32M clock is 1.6M */
+    ADC_CLOCK_DIV_24, /*!< ADC clock:on 32M clock is 1.333M */
+    ADC_CLOCK_DIV_32, /*!< ADC clock:on 32M clock is 1M */
+} adc_clk_div_t;
+
+typedef enum {
+    ADC_VREF_3V2 = 0, /* ADC select 3.2V as reference voltage */
+    ADC_VREF_2V = 1,  /* ADC select 2V as reference voltage */
+} adc_vref_t;
+
+/**
+ *  @brief ADC data width type definition
+ */
+typedef enum {
+    ADC_DATA_WIDTH_12B,                  /*!< ADC 12 bits */
+    ADC_DATA_WIDTH_14B_WITH_16_AVERAGE,  /*!< ADC 14 bits,and the value is average of 16 converts */
+    ADC_DATA_WIDTH_14B_WITH_64_AVERAGE,  /*!< ADC 14 bits,and the value is average of 64 converts */
+    ADC_DATA_WIDTH_16B_WITH_128_AVERAGE, /*!< ADC 16 bits,and the value is average of 128 converts */
+    ADC_DATA_WIDTH_16B_WITH_256_AVERAGE, /*!< ADC 16 bits,and the value is average of 256 converts */
+} adc_data_width_t;
+
+/**
+ *  @brief ADC FIFO threshold type definition
+ */
+typedef enum {
+    ADC_FIFO_THRESHOLD_1BYTE,  /*!< ADC FIFO threshold is 1 */
+    ADC_FIFO_THRESHOLD_4BYTE,  /*!< ADC FIFO threshold is 4 */
+    ADC_FIFO_THRESHOLD_8BYTE,  /*!< ADC FIFO threshold is 8 */
+    ADC_FIFO_THRESHOLD_16BYTE, /*!< ADC FIFO threshold is 16 */
+} adc_fifo_threshold_t;
+
+/**
+ *  @brief ADC PGA gain type definition
+ */
+typedef enum {
+    ADC_GAIN_NONE, /*!< No PGA gain */
+    ADC_GAIN_1,    /*!< PGA gain 1 */
+    ADC_GAIN_2,    /*!< PGA gain 2 */
+    ADC_GAIN_4,    /*!< PGA gain 4 */
+    ADC_GAIN_8,    /*!< PGA gain 8 */
+    ADC_GAIN_16,   /*!< PGA gain 16 */
+    ADC_GAIN_32,   /*!< PGA gain 32 */
+} adc_pga_gain_t;
+
+enum adc_event_type {
+    ADC_EVENT_UNDERRUN,
+    ADC_EVENT_OVERRUN,
+    ADC_EVENT_FIFO,
+    ADC_EVENT_UNKNOWN
+};
+
+enum adc_it_type {
+    ADC_UNDERRUN_IT = 1 << 2,
+    ADC_OVERRUN_IT = 1 << 3,
+    ADC_FIFO_IT = 1 << 5,
+};
+
+typedef struct {
+    uint8_t *pos_channel;
+    uint8_t *neg_channel;
+    uint8_t num;
+} adc_channel_cfg_t;
+
+typedef struct {
+    int8_t posChan; /*!< Positive channel */
+    int8_t negChan; /*!< Negative channel */
+    uint16_t value; /*!< ADC value */
+    float volt;     /*!< ADC voltage result */
+} adc_channel_val_t;
+
+typedef struct
+{
+    uint32_t *input;
+    adc_channel_val_t *output;
+    uint32_t num;
+} adc_data_parse_t;
+
+typedef struct adc_device {
+    struct device parent;
+    adc_clk_div_t clk_div;     /* CLK is not more than 2Mhz */
+    adc_vref_t vref;           /* ADC voltage reference*/
+    bool continuous_conv_mode; /** conversion mode: shot conversion mode or continuous conversion mode. */
+    bool differential_mode;    /** Channel type: single-ended or differential. */
+    adc_data_width_t data_width;
+    adc_fifo_threshold_t fifo_threshold;
+    adc_pga_gain_t gain;
+    void *rx_dma;
+} adc_device_t;
+
+#define ADC_DEV(dev) ((adc_device_t *)dev)
+
+int adc_register(enum adc_index_type index, const char *name);
+int adc_trim_tsen(uint16_t *tsen_offset);
+float adc_get_tsen(uint16_t tsen_offset);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_boot2.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_boot2.h
new file mode 100644
index 00000000..ba1921f1
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_boot2.h
@@ -0,0 +1,273 @@
+/**
+ * *****************************************************************************
+ * @file hal_boot2_custom.h
+ * @version 0.1
+ * @date 2021-07-17
+ * @brief
+ * *****************************************************************************
+ * @attention
+ *
+ *  
© COPYRIGHT(c) 2020 Bouffalo Lab

+ *
+ *  Redistribution and use in source and binary forms, with or without modification,
+ *  are permitted provided that the following conditions are met:
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *    2. Redistributions in binary form must reproduce the above copyright notice,
+ *       this list of conditions and the following disclaimer in the documentation
+ *       and/or other materials provided with the distribution.
+ *    3. Neither the name of Bouffalo Lab nor the names of its contributors
+ *       may be used to endorse or promote products derived from this software
+ *       without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ *  SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ *  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ *  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * *****************************************************************************
+ */
+#ifndef __HAL_BOOT2_H__
+#define __HAL_BOOT2_H__
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_common.h"
+#include "bl702_sflash.h"
+#include "bl702_glb.h"
+
+#define BL_TCM_BASE           BL702_TCM_BASE
+#define BL_SYS_CLK_PLL        GLB_SYS_CLK_DLL144M
+#define BL_SFLASH_CLK         GLB_SFLASH_CLK_72M
+#define HAL_PLL_CFG_MAGICCODE "PCFG"
+
+#define HAL_BOOT2_PK_HASH_SIZE                256 / 8
+#define HAL_BOOT2_IMG_HASH_SIZE               256 / 8
+#define HAL_BOOT2_ECC_KEYXSIZE                256 / 8
+#define HAL_BOOT2_ECC_KEYYSIZE                256 / 8
+#define HAL_BOOT2_SIGN_MAXSIZE                (2048 / 8)
+#define HAL_BOOT2_DEADBEEF_VAL                0xdeadbeef
+#define HAL_BOOT2_CPU0_MAGIC                  "BFNP"
+#define HAL_BOOT2_CPU1_MAGIC                  "BFAP"
+#define HAL_BOOT2_CP_FLAG                     0x02
+#define HAL_BOOT2_MP_FLAG                     0x01
+#define HAL_BOOT2_SP_FLAG                     0x00
+
+#define HAL_BOOT2_SUPPORT_DECOMPRESS          1 /* 1 support decompress, 0 not support */
+#define HAL_BOOT2_SUPPORT_USB_IAP             0 /* 1 support decompress, 0 not support */
+#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_RAM   1 /* 1 support decompress, 0 not support */
+#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_FLASH 0 /* 1 support decompress, 0 not support */
+
+#define HAL_BOOT2_CPU_GROUP_MAX               1
+#define HAL_BOOT2_CPU_MAX                     1
+#define HAL_BOOT2_RAM_IMG_COUNT_MAX           0
+
+#define HAL_BOOT2_FW_IMG_OFFSET_AFTER_HEADER  4*1024  
+typedef struct
+{
+    uint8_t encrypted[HAL_BOOT2_CPU_GROUP_MAX];
+    uint8_t sign[HAL_BOOT2_CPU_GROUP_MAX];
+    uint8_t hbn_check_sign;
+    uint8_t rsvd[1];
+    uint8_t chip_id[8];
+    uint8_t pk_hash_cpu0[HAL_BOOT2_PK_HASH_SIZE];
+    uint8_t pk_hash_cpu1[HAL_BOOT2_PK_HASH_SIZE];
+    uint8_t uart_download_cfg;
+    uint8_t sf_pin_cfg;
+    uint8_t keep_dbg_port_closed;
+    uint8_t boot_pin_cfg;
+} boot2_efuse_hw_config;
+
+struct __attribute__((packed, aligned(4))) hal_flash_config 
+{
+    uint32_t magicCode; /*'FCFG'*/
+    SPI_Flash_Cfg_Type cfg;
+    uint32_t crc32;
+} ;
+
+typedef struct
+{
+    uint8_t xtal_type;
+    uint8_t pll_clk;
+    uint8_t hclk_div;
+    uint8_t bclk_div;
+
+    uint8_t flash_clk_type;
+    uint8_t flash_clk_div;
+    uint8_t rsvd[2];
+} hal_sys_clk_config;
+
+typedef struct
+{
+    uint32_t magicCode; /*'PCFG'*/
+    hal_sys_clk_config cfg;
+    uint32_t crc32;
+} hal_pll_config;
+
+
+struct __attribute__((packed, aligned(4))) hal_basic_cfg_t {
+    uint32_t sign_type          : 2; /* [1: 0]   for sign */
+    uint32_t encrypt_type       : 2; /* [3: 2]   for encrypt */
+    uint32_t key_sel            : 2; /* [5: 4]   key slot */
+    uint32_t xts_mode           : 1; /* [6]      for xts mode */
+    uint32_t aes_region_lock    : 1; /* [7]      rsvd */
+    uint32_t no_segment         : 1; /* [8]      no segment info */
+    uint32_t boot2_enable       : 1; /* [9]      boot2 enable */
+    uint32_t boot2_rollback     : 1; /* [10]     boot2 rollback */
+    uint32_t cpu_master_id      : 4; /* [14: 11] master id */
+    uint32_t notload_in_bootrom : 1; /* [15]     notload in bootrom */
+    uint32_t crc_ignore         : 1; /* [16]     ignore crc */
+    uint32_t hash_ignore        : 1; /* [17]     hash ignore */
+    uint32_t power_on_mm        : 1; /* [18]     power on mm */
+    uint32_t em_sel             : 3; /* [21: 19] em_sel */
+    uint32_t cmds_en            : 1; /* [22]     command spliter enable */
+    uint32_t cmds_wrap_mode     : 2; /* [24: 23] cmds wrap mode */
+    uint32_t cmds_wrap_len      : 4; /* [28: 25] cmds wrap len */
+    uint32_t icache_invalid     : 1; /* [29] icache invalid */
+    uint32_t dcache_invalid     : 1; /* [30] dcache invalid */
+    uint32_t fpga_halt_release  : 1; /* [31] FPGA halt release function */
+
+    uint32_t group_image_offset;     /* flash controller offset */
+    uint32_t aes_region_len;         /* aes region length */
+
+    uint32_t img_len_cnt;            /* image length or segment count */
+    uint32_t hash[8];                /* hash of the image */
+};
+
+struct __attribute__((packed, aligned(4))) hal_cpu_cfg_t {
+    uint8_t config_enable;          /* coinfig this cpu */
+    uint8_t halt_cpu;               /* halt this cpu */
+    uint8_t cache_enable  : 1;      /* cache setting */
+    uint8_t cache_wa      : 1;      /* cache setting */
+    uint8_t cache_wb      : 1;      /* cache setting */
+    uint8_t cache_wt      : 1;      /* cache setting */
+    uint8_t cache_way_dis : 4;      /* cache setting */
+    uint8_t rsvd;
+
+    uint32_t image_address_offset;  /* image address on flash */
+    uint32_t boot_entry;            /* entry point of the m0 image */
+    uint32_t msp_val;               /* msp value */
+};
+
+
+struct  hal_bootheader_t
+{
+    uint32_t magicCode; /*'BFXP'*/
+    uint32_t rivison;
+    struct hal_flash_config flash_cfg;
+    hal_pll_config clk_cfg;
+    __PACKED_UNION
+    {
+        __PACKED_STRUCT
+        {
+            uint32_t sign              : 2;  /* [1: 0]      for sign*/
+            uint32_t encrypt_type      : 2;  /* [3: 2]      for encrypt */
+            uint32_t key_sel           : 2;  /* [5: 4]      for key sel in boot interface*/
+            uint32_t rsvd6_7           : 2;  /* [7: 6]      for encrypt*/
+            uint32_t no_segment        : 1;  /* [8]         no segment info */
+            uint32_t cache_enable      : 1;  /* [9]         for cache */
+            uint32_t notLoadInBoot     : 1;  /* [10]        not load this img in bootrom */
+            uint32_t aes_region_lock   : 1;  /* [11]        aes region lock */
+            uint32_t cache_way_disable : 4;  /* [15: 12]    cache way disable info*/
+            uint32_t crcIgnore         : 1;  /* [16]        ignore crc */
+            uint32_t hash_ignore       : 1;  /* [17]        hash crc */
+            uint32_t halt_cpu1         : 1;  /* [18]        halt ap */
+            uint32_t rsvd19_31         : 13; /* [31:19]     rsvd */
+        }
+        bval;
+        uint32_t wval;
+    }
+    bootCfg;
+
+    __PACKED_UNION
+    {
+        uint32_t segment_cnt;
+        uint32_t img_len;
+    }
+    img_segment_info;
+
+    uint32_t bootEntry; /* entry point of the image*/
+    __PACKED_UNION
+    {
+        uint32_t ram_addr;
+        uint32_t flash_offset;
+    }
+    img_start;
+
+    uint8_t hash[HAL_BOOT2_IMG_HASH_SIZE]; /*hash of the image*/
+
+    uint32_t rsv1;
+    uint32_t rsv2;
+    uint32_t crc32;
+} ;
+
+typedef struct
+{
+    uint8_t img_valid;
+    uint8_t pk_src;
+    uint8_t rsvd[2];
+
+    struct hal_basic_cfg_t basic_cfg;
+
+    struct hal_cpu_cfg_t cpu_cfg[HAL_BOOT2_CPU_MAX];
+
+    uint8_t aes_iv[16 + 4];                         //iv in boot header
+
+    uint8_t eckye_x[HAL_BOOT2_ECC_KEYXSIZE];  //ec key in boot header
+    uint8_t eckey_y[HAL_BOOT2_ECC_KEYYSIZE];  //ec key in boot header
+    uint8_t eckey_x2[HAL_BOOT2_ECC_KEYXSIZE]; //ec key in boot header
+    uint8_t eckey_y2[HAL_BOOT2_ECC_KEYYSIZE]; //ec key in boot header
+
+    uint8_t signature[HAL_BOOT2_SIGN_MAXSIZE];  //signature in boot header
+    uint8_t signature2[HAL_BOOT2_SIGN_MAXSIZE]; //signature in boot header
+
+} boot2_image_config;
+
+extern boot2_efuse_hw_config g_efuse_cfg;
+extern uint8_t g_ps_mode;
+extern uint32_t g_user_hash_ignored;
+extern struct device *dev_check_hash;
+
+
+
+
+uint32_t hal_boot2_custom(void);
+void hal_boot2_reset_sec_eng(void);
+void hal_boot2_sw_system_reset(void);
+void hal_boot2_set_psmode_status(uint32_t flag);
+uint32_t hal_boot2_get_psmode_status(void);
+uint32_t hal_boot2_get_user_fw(void);
+void hal_boot2_clr_user_fw(void);
+void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg);
+int32_t hal_boot2_get_clk_cfg(hal_pll_config *cfg);
+void hal_boot2_sboot_finish(void);
+void hal_boot2_uart_gpio_init(void);
+void hal_boot2_debug_uart_gpio_init(void);
+#if HAL_BOOT2_SUPPORT_USB_IAP
+void hal_boot2_debug_usb_port_init(void);
+#endif
+
+void hal_boot2_debug_uart_gpio_deinit(void);
+int32_t hal_boot_parse_bootheader(boot2_image_config *boot_img_cfg, uint8_t *data);
+void hal_boot2_clean_cache(void);
+BL_Err_Type hal_boot2_set_cache(uint8_t cont_read, boot2_image_config *boot_img_cfg);
+void hal_boot2_get_ram_img_cnt(char* img_name[],uint32_t *ram_img_cnt );
+void hal_boot2_get_img_info(uint8_t *data, uint32_t *image_offset, uint32_t *img_len,uint8_t **hash);
+void hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr);
+uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr);
+uint32_t hal_boot2_get_grp_count(void);
+uint32_t hal_boot2_get_cpu_count(void);
+uint32_t hal_boot2_get_feature_flag(void);
+uint32_t hal_boot2_get_bootheader_offset(void);
+#ifdef __cplusplus
+}
+#endif
+#endif
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_clock.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_clock.h
new file mode 100644
index 00000000..33c8e6f8
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_clock.h
@@ -0,0 +1,95 @@
+/**
+ * @file hal_clock.h
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef __HAL_CLOCK__H__
+#define __HAL_CLOCK__H__
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_common.h"
+#include "bl702_config.h"
+
+/*XTAL_TYPE*/
+#define XTAL_NONE         0
+#define EXTERNAL_XTAL_32M 1
+#define INTERNAL_RC_32M   2
+
+/*CLOCK_32K_XTAL*/
+#define EXTERNAL_XTAL_32K 0
+#define INTERNAL_RC_32K   1
+
+/*BSP_ROOT_CLOCK_SOURCE*/
+#if XTAL_TYPE != EXTERNAL_XTAL_32M
+#define ROOT_CLOCK_SOURCE_XCLK 0
+#else
+#define ROOT_CLOCK_SOURCE_XCLK 1
+#endif
+#define ROOT_CLOCK_SOURCE_PLL_57P6M 2
+#define ROOT_CLOCK_SOURCE_PLL_96M   3
+#define ROOT_CLOCK_SOURCE_PLL_144M  4
+/*BSP_XXX_CLOCK_SOURCE*/
+#define ROOT_CLOCK_SOURCE_32K_CLK 5
+#define ROOT_CLOCK_SOURCE_FCLK    6
+#define ROOT_CLOCK_SOURCE_BCLK    7
+#define ROOT_CLOCK_SOURCE_1K_CLK  8
+
+/*BSP_AUDIO_PLL_CLOCK_SOURCE*/
+#define ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ 9
+#define ROOT_CLOCK_SOURCE_AUPLL_11289600_HZ 10
+#define ROOT_CLOCK_SOURCE_AUPLL_5644800_HZ  11
+#define ROOT_CLOCK_SOURCE_AUPLL_24576000_HZ 12
+#define ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ 13
+
+enum system_clock_type {
+    SYSTEM_CLOCK_ROOT_CLOCK = 0, /* clock source before fclk_div*/
+    SYSTEM_CLOCK_FCLK,           /* clock source after fclk_div*/
+    SYSTEM_CLOCK_BCLK,           /* clock source after bclk_div*/
+    SYSTEM_CLOCK_XCLK,           /* xtal clock*/
+    SYSTEM_CLOCK_32K_CLK,
+    SYSTEM_CLOCK_AUPLL,
+};
+enum peripheral_clock_type {
+    PERIPHERAL_CLOCK_UART = 0,
+    PERIPHERAL_CLOCK_SPI,
+    PERIPHERAL_CLOCK_I2C,
+    PERIPHERAL_CLOCK_ADC,
+    PERIPHERAL_CLOCK_DAC,
+    PERIPHERAL_CLOCK_I2S,
+    PERIPHERAL_CLOCK_PWM,
+    PERIPHERAL_CLOCK_CAM,
+    PERIPHERAL_CLOCK_TIMER0,
+    PERIPHERAL_CLOCK_TIMER1,
+    PERIPHERAL_CLOCK_WDT,
+};
+
+void system_clock_init(void);
+void peripheral_clock_init(void);
+uint32_t system_clock_get(enum system_clock_type type);
+uint32_t peripheral_clock_get(enum peripheral_clock_type type);
+void system_mtimer_clock_init(void);
+void system_mtimer_clock_reinit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_common.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_common.h
new file mode 100644
index 00000000..f9e17a04
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_common.h
@@ -0,0 +1,46 @@
+/**
+ * @file hal_common.h
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef __HAL_COMMON__H__
+#define __HAL_COMMON__H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bl702_common.h"
+
+void cpu_global_irq_enable(void);
+void cpu_global_irq_disable(void);
+void hal_por_reset(void);
+void hal_system_reset(void);
+void hal_cpu_reset(void);
+void hal_get_chip_id(uint8_t chip_id[8]);
+void hal_enter_usb_iap(void);
+void hal_jump2app(uint32_t flash_offset);
+int hal_get_trng_seed(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_dma.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_dma.h
new file mode 100644
index 00000000..dda00291
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_dma.h
@@ -0,0 +1,190 @@
+/**
+ * @file hal_dma.h
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef __HAL_DMA__H__
+#define __HAL_DMA__H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "hal_common.h"
+#include "drv_device.h"
+#include "bl702_config.h"
+
+#define DEVICE_CTRL_DMA_CHANNEL_GET_STATUS 0x10
+#define DEVICE_CTRL_DMA_CHANNEL_START      0x11
+#define DEVICE_CTRL_DMA_CHANNEL_STOP       0x12
+#define DEVICE_CTRL_DMA_CHANNEL_UPDATE     0x13
+#define DEVICE_CTRL_DMA_CONFIG_SI          0x14
+#define DEVICE_CTRL_DMA_CONFIG_DI          0x15
+
+enum dma_index_type {
+#ifdef BSP_USING_DMA0_CH0
+    DMA0_CH0_INDEX,
+#endif
+#ifdef BSP_USING_DMA0_CH1
+    DMA0_CH1_INDEX,
+#endif
+#ifdef BSP_USING_DMA0_CH2
+    DMA0_CH2_INDEX,
+#endif
+#ifdef BSP_USING_DMA0_CH3
+    DMA0_CH3_INDEX,
+#endif
+#ifdef BSP_USING_DMA0_CH4
+    DMA0_CH4_INDEX,
+#endif
+#ifdef BSP_USING_DMA0_CH5
+    DMA0_CH5_INDEX,
+#endif
+#ifdef BSP_USING_DMA0_CH6
+    DMA0_CH6_INDEX,
+#endif
+#ifdef BSP_USING_DMA0_CH7
+    DMA0_CH7_INDEX,
+#endif
+    DMA_MAX_INDEX
+};
+
+#define dma_channel_start(dev)        device_control(dev, DEVICE_CTRL_DMA_CHANNEL_START, NULL)
+#define dma_channel_stop(dev)         device_control(dev, DEVICE_CTRL_DMA_CHANNEL_STOP, NULL)
+#define dma_channel_update(dev, list) device_control(dev, DEVICE_CTRL_DMA_CHANNEL_UPDATE, list)
+#define dma_channel_check_busy(dev)   device_control(dev, DEVICE_CTRL_DMA_CHANNEL_GET_STATUS, NULL)
+
+#define DMA_LLI_ONCE_MODE  0
+#define DMA_LLI_CYCLE_MODE 1
+
+#define DMA_ADDR_INCREMENT_DISABLE 0 /*!< Addr increment mode disable */
+#define DMA_ADDR_INCREMENT_ENABLE  1 /*!< Addr increment mode enable  */
+
+#define DMA_TRANSFER_WIDTH_8BIT  0
+#define DMA_TRANSFER_WIDTH_16BIT 1
+#define DMA_TRANSFER_WIDTH_32BIT 2
+
+#define DMA_BURST_1BYTE  0
+#define DMA_BURST_4BYTE  1
+#define DMA_BURST_8BYTE  2
+#define DMA_BURST_16BYTE 3
+
+#define DMA_ADDR_UART0_TDR (0x4000A000 + 0x88)
+#define DMA_ADDR_UART0_RDR (0x4000A000 + 0x8C)
+#define DMA_ADDR_UART1_TDR (0x4000A100 + 0x88)
+#define DMA_ADDR_UART1_RDR (0x4000A100 + 0x8C)
+#define DMA_ADDR_I2C_TDR   (0x4000A300 + 0x88)
+#define DMA_ADDR_I2C_RDR   (0x4000A300 + 0x8C)
+#define DMA_ADDR_SPI_TDR   (0x4000A200 + 0x88)
+#define DMA_ADDR_SPI_RDR   (0x4000A200 + 0x8C)
+#define DMA_ADDR_I2S_TDR   (0x4000AA00 + 0x88)
+#define DMA_ADDR_I2S_RDR   (0x4000AA00 + 0x8C)
+#define DMA_ADDR_ADC_RDR   (0x40002000 + 0x04)
+#define DMA_ADDR_DAC_TDR   (0x40002000 + 0X48)
+
+#define DMA_REQUEST_NONE     0x00000000 /*!< DMA request peripheral:None */
+#define DMA_REQUEST_UART0_RX 0x00000000 /*!< DMA request peripheral:UART0 RX */
+#define DMA_REQUEST_UART0_TX 0x00000001 /*!< DMA request peripheral:UART0 TX */
+#define DMA_REQUEST_UART1_RX 0x00000002 /*!< DMA request peripheral:UART1 RX */
+#define DMA_REQUEST_UART1_TX 0x00000003 /*!< DMA request peripheral:UART1 TX */
+#define DMA_REQUEST_I2C0_RX  0x00000006 /*!< DMA request peripheral:I2C RX */
+#define DMA_REQUEST_I2C0_TX  0x00000007 /*!< DMA request peripheral:I2C TX */
+#define DMA_REQUEST_SPI0_RX  0x0000000A /*!< DMA request peripheral:SPI RX */
+#define DMA_REQUEST_SPI0_TX  0x0000000B /*!< DMA request peripheral:SPI TX */
+#define DMA_REQUEST_I2S_RX   0x00000014 /*!< DMA request peripheral:I2S RX */
+#define DMA_REQUEST_I2S_TX   0x00000015 /*!< DMA request peripheral:I2S TX */
+#define DMA_REQUEST_ADC0     0x00000016 /*!< DMA request peripheral:ADC0 */
+#define DMA_REQUEST_DAC0     0x00000017 /*!< DMA request peripheral:DAC0 */
+#define DMA_REQUEST_USB_EP0  0x00000018 /*!< DMA request peripheral:USB EP0*/
+#define DMA_REQUEST_USB_EP1  0x00000019 /*!< DMA request peripheral:USB EP1*/
+#define DMA_REQUEST_USB_EP2  0x0000001A /*!< DMA request peripheral:USB EP2*/
+#define DMA_REQUEST_USB_EP3  0x0000001B /*!< DMA request peripheral:USB EP3*/
+#define DMA_REQUEST_USB_EP4  0x0000001C /*!< DMA request peripheral:USB EP4*/
+#define DMA_REQUEST_USB_EP5  0x0000001D /*!< DMA request peripheral:USB EP5*/
+#define DMA_REQUEST_USB_EP6  0x0000001E /*!< DMA request peripheral:USB EP6*/
+#define DMA_REQUEST_USB_EP7  0x0000001F /*!< DMA request peripheral:USB EP7 */
+
+/**
+ *  @brief DMA transfer direction type definition
+ */
+typedef enum {
+    DMA_MEMORY_TO_MEMORY = 0, /*!< DMA transfer type:memory to memory */
+    DMA_MEMORY_TO_PERIPH,     /*!< DMA transfer type:memory to peripheral */
+    DMA_PERIPH_TO_MEMORY,     /*!< DMA transfer type:peripheral to memory */
+    DMA_PERIPH_TO_PERIPH,     /*!< DMA transfer type:peripheral to peripheral */
+} dma_transfer_dir_type;
+
+typedef union {
+    struct
+    {
+        uint32_t TransferSize : 12; /* [11: 0],        r/w,        0x0 */
+        uint32_t SBSize       : 2;  /* [13:12],        r/w,        0x1 */
+        uint32_t dst_min_mode : 1;  /* [   14],        r/w,        0x0 */
+        uint32_t DBSize       : 2;  /* [16:15],        r/w,        0x1 */
+        uint32_t dst_add_mode : 1;  /* [   17],        r/w,        0x0 */
+        uint32_t SWidth       : 2;  /* [19:18],        r/w,        0x2 */
+        uint32_t reserved_20  : 1;  /* [   20],       rsvd,        0x0 */
+        uint32_t DWidth       : 2;  /* [22:21],        r/w,        0x2 */
+        uint32_t fix_cnt      : 2;  /* [24:23],        r/w,        0x0 */
+        uint32_t SLargerD     : 1;  /* [   25],        r/w,        0x0 */
+        uint32_t SI           : 1;  /* [   26],        r/w,        0x1 */
+        uint32_t DI           : 1;  /* [   27],        r/w,        0x1 */
+        uint32_t Prot         : 3;  /* [30:28],        r/w,        0x0 */
+        uint32_t I            : 1;  /* [   31],        r/w,        0x0 */
+    } bits;
+    uint32_t WORD;
+} dma_control_data_t;
+
+typedef struct
+{
+    uint32_t src_addr;
+    uint32_t dst_addr;
+    uint32_t nextlli;
+    dma_control_data_t cfg;
+} dma_lli_ctrl_t;
+
+typedef struct dma_device {
+    struct device parent;
+    uint8_t id;
+    uint8_t ch;
+    uint8_t transfer_mode;
+    uint8_t direction;
+    uint32_t src_req;
+    uint32_t dst_req;
+    uint8_t src_addr_inc;
+    uint8_t dst_addr_inc;
+    uint8_t src_burst_size;
+    uint8_t dst_burst_size;
+    uint8_t src_width;
+    uint8_t dst_width;
+    dma_lli_ctrl_t *lli_cfg;
+} dma_device_t;
+
+#define DMA_DEV(dev) ((dma_device_t *)dev)
+
+int dma_register(enum dma_index_type index, const char *name);
+int dma_allocate_register(const char *name);
+int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_flash.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_flash.h
new file mode 100644
index 00000000..ac00fb0d
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_flash.h
@@ -0,0 +1,50 @@
+/**
+ * @file hal_flash.h
+ * @brief
+ *
+ * Copyright 2019-2030 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef __HAL_FLASH__H__
+#define __HAL_FLASH__H__
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_common.h"
+#include "bl702_sflash.h"
+#include "bl702_sflash_ext.h"
+
+#define FLASH_NOT_DETECT  0x10
+#define BL_FLASH_XIP_BASE BL702_FLASH_XIP_BASE
+
+uint32_t flash_get_jedecid(void);
+BL_Err_Type flash_init(void);
+BL_Err_Type flash_read_jedec_id(uint8_t *data);
+BL_Err_Type flash_read_via_xip(uint32_t addr, uint8_t *data, uint32_t len);
+BL_Err_Type flash_read(uint32_t addr, uint8_t *data, uint32_t len);
+BL_Err_Type flash_write(uint32_t addr, uint8_t *data, uint32_t len);
+BL_Err_Type flash_erase(uint32_t startaddr, uint32_t len);
+BL_Err_Type flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset);
+BL_Err_Type flash_get_cfg(uint8_t **cfg_addr, uint32_t *len);
+BL_Err_Type flash_write_protect_set(SFlash_Protect_Kh25v40_Type protect);
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_gpio.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_gpio.h
new file mode 100644
index 00000000..94227094
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_gpio.h
@@ -0,0 +1,96 @@
+/**
+ * @file hal_gpio.h
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef __HAL_GPIO__H__
+#define __HAL_GPIO__H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bl702_config.h"
+#include "drv_device.h"
+#include "hal_common.h"
+
+enum gpio_pin_type {
+  GPIO_PIN_0 = 0,
+  GPIO_PIN_1,
+  GPIO_PIN_2,
+  GPIO_PIN_3,
+  GPIO_PIN_4,
+  GPIO_PIN_5,
+  GPIO_PIN_6,
+  GPIO_PIN_7,
+  GPIO_PIN_8,
+  GPIO_PIN_9,
+  GPIO_PIN_10,
+  GPIO_PIN_11,
+  GPIO_PIN_12,
+  GPIO_PIN_13,
+  GPIO_PIN_14,
+  GPIO_PIN_15,
+  GPIO_PIN_16,
+  GPIO_PIN_17,
+  GPIO_PIN_18,
+  GPIO_PIN_19,
+  GPIO_PIN_20,
+  GPIO_PIN_21,
+  GPIO_PIN_22,
+  GPIO_PIN_23,
+  GPIO_PIN_24,
+  GPIO_PIN_25,
+  GPIO_PIN_26,
+  GPIO_PIN_27,
+  GPIO_PIN_28,
+  GPIO_PIN_29,
+  GPIO_PIN_30,
+  GPIO_PIN_31,
+  GPIO_PIN_MAX,
+};
+
+#define GPIO_OUTPUT_MODE                   0
+#define GPIO_OUTPUT_PP_MODE                1
+#define GPIO_OUTPUT_PD_MODE                2
+#define GPIO_INPUT_MODE                    3
+#define GPIO_INPUT_PU_MODE                 4
+#define GPIO_INPUT_PD_MODE                 5
+#define GPIO_ASYNC_RISING_TRIGER_INT_MODE  6
+#define GPIO_ASYNC_FALLING_TRIGER_INT_MODE 7
+#define GPIO_ASYNC_HIGH_LEVEL_INT_MODE     8
+#define GPIO_ASYNC_LOW_LEVEL_INT_MODE      9
+#define GPIO_SYNC_RISING_TRIGER_INT_MODE   10
+#define GPIO_SYNC_FALLING_TRIGER_INT_MODE  11
+#define GPIO_SYNC_HIGH_LEVEL_INT_MODE      12
+#define GPIO_SYNC_LOW_LEVEL_INT_MODE       13
+#define GPIO_HZ_MODE                       14
+
+void gpio_set_mode(uint32_t pin, uint32_t mode);
+void gpio_write(uint32_t pin, uint32_t value);
+void gpio_toggle(uint32_t pin);
+int  gpio_read(uint32_t pin);
+void gpio_attach_irq(uint32_t pin, void (*cbfun)(uint32_t pin));
+void gpio_irq_enable(uint32_t pin, uint8_t enabled);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_i2c.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_i2c.h
new file mode 100644
index 00000000..5892a721
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_i2c.h
@@ -0,0 +1,75 @@
+/**
+ * @file hal_i2c.h
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef __HAL_I2C__H__
+#define __HAL_I2C__H__
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_common.h"
+#include "drv_device.h"
+#include "bl702_config.h"
+
+enum i2c_index_type {
+#ifdef BSP_USING_I2C0
+    I2C0_INDEX,
+#endif
+    I2C_MAX_INDEX
+};
+
+#define I2C_WR      0x0000
+#define I2C_RD      0x0001
+#define I2C_RW_MASK 0x0001
+
+#define SUB_ADDR_0BYTE 0x0010
+#define SUB_ADDR_1BYTE 0x0020
+#define SUB_ADDR_2BYTE 0x0040
+
+#define I2C_HW_MODE 0
+#define I2C_SW_MODE 1
+
+typedef struct i2c_msg {
+    uint8_t slaveaddr;
+    uint32_t subaddr;
+    uint16_t flags;
+    uint16_t len;
+    uint8_t *buf;
+} i2c_msg_t;
+
+typedef struct i2c_device {
+    struct device parent;
+    uint8_t id;
+    uint8_t mode;
+    uint32_t phase;
+} i2c_device_t;
+
+#define I2C_DEV(dev) ((i2c_device_t *)dev)
+
+int i2c_register(enum i2c_index_type index, const char *name);
+int i2c_transfer(struct device *dev, i2c_msg_t msgs[], uint32_t num);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_mtimer.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_mtimer.h
new file mode 100644
index 00000000..211182a8
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_mtimer.h
@@ -0,0 +1,42 @@
+/**
+ * @file hal_mtimer.h
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef __HAL_MTIMER__H__
+#define __HAL_MTIMER__H__
+
+#include "stdint.h"
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+void mtimer_set_alarm_time(uint64_t ticks, void (*interruptfun)(void));
+uint64_t mtimer_get_time_ms();
+uint64_t mtimer_get_time_us();
+void mtimer_delay_ms(uint32_t time);
+void mtimer_delay_us(uint32_t time);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_pm.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_pm.h
new file mode 100644
index 00000000..f45aade0
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_pm.h
@@ -0,0 +1,75 @@
+/**
+ * @file hal_pm.h
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef __HAL_PM__H__
+#define __HAL_PM__H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "hal_common.h"
+
+enum pm_pds_sleep_level {
+    PM_PDS_LEVEL_0,
+    PM_PDS_LEVEL_1,
+    PM_PDS_LEVEL_2,
+    PM_PDS_LEVEL_3,
+    PM_PDS_LEVEL_4, /*do not recommend to use*/
+    PM_PDS_LEVEL_5, /*do not recommend to use*/
+    PM_PDS_LEVEL_6, /*do not recommend to use*/
+    PM_PDS_LEVEL_7, /*do not recommend to use*/
+    PM_PDS_LEVEL_31 = 31,
+};
+
+enum pm_hbn_sleep_level {
+    PM_HBN_LEVEL_0,
+    PM_HBN_LEVEL_1,
+    PM_HBN_LEVEL_2,
+};
+
+enum pm_event_type {
+    PM_HBN_WAKEUP_EVENT_NONE,
+    PM_HBN_GPIO9_WAKEUP_EVENT,
+    PM_HBN_GPIO10_WAKEUP_EVENT,
+    PM_HBN_GPIO11_WAKEUP_EVENT,
+    PM_HBN_GPIO12_WAKEUP_EVENT,
+    PM_HBN_RTC_WAKEUP_EVENT,
+    PM_HBN_BOR_WAKEUP_EVENT,
+    PM_HBN_ACOMP0_WAKEUP_EVENT,
+    PM_HBN_ACOMP1_WAKEUP_EVENT,
+};
+
+void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint32_t sleep_time);
+void pm_hbn_mode_enter(enum pm_hbn_sleep_level hbn_level, uint8_t sleep_time);
+void pm_hbn_enter_again(bool reset);
+void pm_set_wakeup_callback(void (*wakeup_callback)(void));
+enum pm_event_type pm_get_wakeup_event(void);
+void pm_bor_init(void);
+void pm_hbn_out0_irq_register(void);
+void pm_hbn_out1_irq_register(void);
+void pm_irq_callback(enum pm_event_type event);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_pm_util.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_pm_util.h
new file mode 100644
index 00000000..b7b55e07
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_pm_util.h
@@ -0,0 +1,33 @@
+/**
+ * @file hal_pm_util.h
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef __HAL_PM_UTIL_H__
+#define __HAL_PM_UTIL_H__
+
+#include "hal_common.h"
+
+#define ATTR_PDS_RAM_SECTION       __attribute__((section(".pds_ram_code")))
+#define ATTR_PDS_RAM_CONST_SECTION __attribute__((section(".pds_ram_data")))
+
+uint32_t hal_pds_enter_with_time_compensation(uint32_t pdsLevel, uint32_t pdsSleepCycles);
+void pm_set_hardware_recovery_callback(void (*hardware_recovery_cb)(void));
+#endif
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_rtc.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_rtc.h
new file mode 100644
index 00000000..feb33b9a
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_rtc.h
@@ -0,0 +1,39 @@
+/**
+ * @file hal_rtc.h
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef __HAL_RTC__H__
+#define __HAL_RTC__H__
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_common.h"
+
+void rtc_init(uint64_t sleep_time);
+void rtc_set_timestamp(uint64_t time_stamp);
+uint64_t rtc_get_timestamp(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_aes.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_aes.h
new file mode 100644
index 00000000..16830276
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_aes.h
@@ -0,0 +1,62 @@
+/**
+ * @file hal_sec_aes.h
+ * @brief
+ *
+ * Copyright 2019-2030 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef __HAL_SEC_AES__H__
+#define __HAL_SEC_AES__H__
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_common.h"
+
+typedef enum {
+    SEC_AES_CBC,
+    SEC_AES_CTR,
+    SEC_AES_ECB
+} sec_aes_type;
+
+typedef enum {
+    SEC_AES_KEY_128,
+    SEC_AES_KEY_256,
+    SEC_AES_KEY_192
+} sec_aes_key_type;
+
+typedef struct sec_aes_handle_t {
+    sec_aes_type aes_type;
+    sec_aes_key_type key_type;
+} sec_aes_handle_t;
+
+typedef enum {
+    SEC_AES_DIR_ENCRYPT,
+    SEC_AES_DIR_DECRYPT
+} sec_aes_dir_type;
+
+int sec_aes_init(sec_aes_handle_t *handle, sec_aes_type aes_tye, sec_aes_key_type key_type);
+int sec_aes_setkey(sec_aes_handle_t *handle, const uint8_t *key, uint8_t key_len, const uint8_t *nonce, uint8_t dir);
+int sec_aes_encrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out);
+int sec_aes_decrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out);
+int sec_aes_deinit(sec_aes_handle_t *handle);
+#ifdef __cplusplus
+}
+#endif
+#endif
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_dsa.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_dsa.h
new file mode 100644
index 00000000..b08016a6
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_dsa.h
@@ -0,0 +1,63 @@
+/**
+ * @file hal_sec_dsa.h
+ * @brief
+ *
+ * Copyright 2019-2030 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef __HAL_SEC_DSA__H__
+#define __HAL_SEC_DSA__H__
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_common.h"
+
+typedef struct sec_dsa_crt_cfg_tag {
+    uint32_t *dP;
+    uint32_t *dQ;
+    uint32_t *qInv;
+    uint32_t *p;
+    uint32_t *invR_p;
+    uint32_t *primeN_p;
+    uint32_t *q;
+    uint32_t *invR_q;
+    uint32_t *primeN_q;
+} sec_dsa_crt_cfg_t;
+
+typedef struct
+{
+    uint32_t size;
+    uint32_t crtSize;
+    uint32_t *n;
+    uint32_t *e;
+    uint32_t *d;
+    sec_dsa_crt_cfg_t crtCfg;
+} sec_dsa_handle_t;
+
+int sec_dsa_init(sec_dsa_handle_t *handle, uint32_t size);
+int sec_dsa_mexp_binary(uint32_t size, const uint32_t *a, const uint32_t *b, const uint32_t *c, uint32_t *r);
+int sec_dsa_mexp_mont(uint32_t size, uint32_t *a, uint32_t *b, uint32_t *c, uint32_t *invR_c, uint32_t *primeN_c, uint32_t *r);
+int sec_dsa_decrypt_crt(uint32_t size, uint32_t *c, sec_dsa_crt_cfg_t *crtCfg, uint32_t *d, uint32_t *r);
+int sec_dsa_sign(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *s);
+int sec_dsa_verify(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *s);
+#ifdef __cplusplus
+}
+#endif
+#endif
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_ecdsa.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_ecdsa.h
new file mode 100644
index 00000000..cb9d2291
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_ecdsa.h
@@ -0,0 +1,69 @@
+/**
+ * @file hal_sec_ecdsa.h
+ * @brief
+ *
+ * Copyright 2019-2030 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef __HAL_SEC_ECDSA__H__
+#define __HAL_SEC_ECDSA__H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "hal_common.h"
+
+typedef enum {
+    ECP_SECP256R1 = 0,
+    ECP_SECP256K1 = 1,
+    ECP_TYPE_MAX = 2,
+} sec_ecp_type;
+
+typedef struct
+{
+    sec_ecp_type ecpId;
+    uint32_t *privateKey;
+    uint32_t *publicKeyx;
+    uint32_t *publicKeyy;
+} sec_ecdsa_handle_t;
+
+typedef struct
+{
+    sec_ecp_type ecpId;
+} sec_ecdh_handle_t;
+
+int sec_ecdsa_init(sec_ecdsa_handle_t *handle, sec_ecp_type id);
+int sec_ecdsa_deinit(sec_ecdsa_handle_t *handle);
+int sec_ecdsa_sign(sec_ecdsa_handle_t *handle, const uint32_t *random_k, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *r, uint32_t *s);
+int sec_ecdsa_verify(sec_ecdsa_handle_t *handle, const uint32_t *hash, uint32_t hashLen, const uint32_t *r, const uint32_t *s);
+int sec_ecdsa_get_private_key(sec_ecdsa_handle_t *handle, uint32_t *private_key);
+int sec_ecdsa_get_public_key(sec_ecdsa_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy);
+
+int sec_ecdh_init(sec_ecdh_handle_t *handle, sec_ecp_type id);
+int sec_ecdh_deinit(sec_ecdh_handle_t *handle);
+int sec_ecdh_get_encrypt_key(sec_ecdh_handle_t *handle, const uint32_t *pkX, const uint32_t *pkY, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy);
+int sec_ecdh_get_public_key(sec_ecdh_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy);
+int sec_ecc_get_random_value(uint32_t *randomData, uint32_t *maxRef, uint32_t size);
+int sec_eng_trng_enable(void);
+void sec_eng_trng_disable(void);
+int sec_eng_trng_read(uint8_t data[32]);
+#ifdef __cplusplus
+}
+#endif
+#endif
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_hash.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_hash.h
new file mode 100644
index 00000000..172ad679
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_hash.h
@@ -0,0 +1,72 @@
+/**
+ * @file hal_sec_hash.h
+ * @brief
+ *
+ * Copyright 2019-2030 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef __HAL_SEC_HASH__H__
+#define __HAL_SEC_HASH__H__
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_common.h"
+#include "drv_device.h"
+#include "bl702_config.h"
+
+enum sec_hash_index_type {
+    SEC_HASH0_INDEX,
+    SEC_HASH_MAX_INDEX
+};
+
+enum sec_hash_type {
+    SEC_HASH_SHA1,
+    SEC_HASH_SHA224,
+    SEC_HASH_SHA256,
+    SEC_HASH_SHA384,
+    SEC_HASH_SHA512,
+    SEC_HASH_UNKNOWN
+};
+
+typedef struct sec_hash_device {
+    struct device parent;
+    uint32_t shaBuf[64 / 4];     /*!< Data not processed but in this temp buffer */
+    uint32_t shaPadding[64 / 4]; /*!< Padding data */
+    uint8_t type;                /*!< Sha has feed data */
+} sec_hash_device_t;
+
+typedef struct
+{
+    uint32_t shaBuf[64 / 4];     /*!< Data not processed but in this temp buffer */
+    uint32_t shaPadding[64 / 4]; /*!< Padding data */
+    uint8_t type;                /*!< Sha has feed data */
+} sec_hash_handle_t;
+
+int sec_hash_init(sec_hash_handle_t *handle, uint8_t type);
+int sec_hash_deinit(sec_hash_handle_t *handle);
+int sec_hash_update(sec_hash_handle_t *handle, const void *buffer, uint32_t size);
+int sec_hash_finish(sec_hash_handle_t *handle, void *buffer);
+int sec_hash_sha256_register(enum sec_hash_index_type index, const char *name);
+int sec_hash_sha224_register(enum sec_hash_index_type index, const char *name);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_uart.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_uart.h
new file mode 100644
index 00000000..06f93f44
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_uart.h
@@ -0,0 +1,136 @@
+/**
+ * @file hal_uart.h
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef __HAL_UART__H__
+#define __HAL_UART__H__
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_common.h"
+#include "drv_device.h"
+#include "bl702_config.h"
+
+#define UART_FIFO_LEN 128
+
+#define DEVICE_CTRL_UART_GET_TX_FIFO 0x10
+#define DEVICE_CTRL_UART_GET_RX_FIFO 0x11
+#define DEVICE_CTRL_UART_CLEAR_TX_FIFO 0x12
+#define DEVICE_CTRL_UART_CLEAR_RX_FIFO 0x13
+
+enum uart_index_type {
+#ifdef BSP_USING_UART0
+    UART0_INDEX,
+#endif
+#ifdef BSP_USING_UART1
+    UART1_INDEX,
+#endif
+    UART_MAX_INDEX
+};
+
+/*!
+ *  @brief    UART data length settings
+ *
+ *  This enumeration defines the UART data lengths.
+ */
+typedef enum {
+    UART_DATA_LEN_5 = 0, /*!< Data length is 5 bits */
+    UART_DATA_LEN_6 = 1, /*!< Data length is 6 bits */
+    UART_DATA_LEN_7 = 2, /*!< Data length is 7 bits */
+    UART_DATA_LEN_8 = 3  /*!< Data length is 8 bits */
+} uart_databits_t;
+
+/*!
+ *  @brief    UART stop bit settings
+ *
+ *  This enumeration defines the UART stop bits.
+ */
+typedef enum {
+    UART_STOP_ZERO_D_FIVE = 0, /*!< 0.5 stop bit */
+    UART_STOP_ONE = 1,         /*!< 1 stop bit */
+    UART_STOP_ONE_D_FIVE = 2,  /*!< 1.5 stop bit */
+    UART_STOP_TWO = 3          /*!< 2 stop bits */
+} uart_stopbits_t;
+
+/*!
+ *  @brief    UART parity type settings
+ *
+ *  This enumeration defines the UART parity types.
+ */
+typedef enum {
+    UART_PAR_NONE = 0, /*!< No parity */
+    UART_PAR_ODD = 1,  /*!< Parity bit is odd */
+    UART_PAR_EVEN = 2, /*!< Parity bit is even */
+} uart_parity_t;
+
+enum uart_event_type {
+    UART_EVENT_TX_END,
+    UART_EVENT_TX_FIFO,
+    UART_EVENT_RX_END,
+    UART_EVENT_RX_FIFO,
+    UART_EVENT_RTO,
+    UART_EVENT_PCE,
+    UART_EVENT_TX_FER,
+    UART_EVENT_RX_FER,
+    UART_EVENT_UNKNOWN
+};
+
+enum uart_it_type {
+    UART_TX_END_IT = 1 << 0,
+    UART_RX_END_IT = 1 << 1,
+    UART_TX_FIFO_IT = 1 << 2,
+    UART_RX_FIFO_IT = 1 << 3,
+    UART_RTO_IT = 1 << 4,
+    UART_PCE_IT = 1 << 5,
+    UART_TX_FER_IT = 1 << 6,
+    UART_RX_FER_IT = 1 << 7,
+    UART_ALL_IT = 1 << 8
+};
+
+typedef struct
+{
+    uint32_t baudrate;
+    uart_databits_t databits;
+    uart_stopbits_t stopbits;
+    uart_parity_t parity;
+} uart_param_cfg_t;
+
+typedef struct uart_device {
+    struct device parent;
+    uint8_t id;
+    uint32_t baudrate;
+    uart_databits_t databits;
+    uart_stopbits_t stopbits;
+    uart_parity_t parity;
+    uint8_t fifo_threshold;
+    void *tx_dma;
+    void *rx_dma;
+} uart_device_t;
+
+#define UART_DEV(dev) ((uart_device_t *)dev)
+
+int uart_register(enum uart_index_type index, const char *name);
+#ifdef __cplusplus
+}
+#endif
+#endif
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_usb.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_usb.h
new file mode 100644
index 00000000..fdd1f60f
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_usb.h
@@ -0,0 +1,236 @@
+/**
+ * @file hal_usb.h
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef __HAL_USB__H__
+#define __HAL_USB__H__
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_common.h"
+#include "ring_buffer.h"
+#include "drv_device.h"
+#include "bl702_config.h"
+
+#define DEVICE_CTRL_USB_DC_SET_ACK            0X10
+#define DEVICE_CTRL_USB_DC_ENUM_ON            0X11
+#define DEVICE_CTRL_USB_DC_ENUM_OFF           0X12
+#define DEVICE_CTRL_USB_DC_GET_EP_TX_FIFO_CNT 0x13
+#define DEVICE_CTRL_USB_DC_GET_EP_RX_FIFO_CNT 0x14
+#define DEVICE_CTRL_USB_DC_SET_TX_DMA         0x15
+#define DEVICE_CTRL_USB_DC_SET_RX_DMA         0x16
+
+enum usb_index_type {
+#ifdef BSP_USING_USB
+    USB_INDEX,
+#endif
+    USB_MAX_INDEX
+};
+
+/**
+ * USB endpoint Transfer Type mask.
+ */
+#define USBD_EP_TYPE_CTRL 0
+#define USBD_EP_TYPE_ISOC 1
+#define USBD_EP_TYPE_BULK 2
+#define USBD_EP_TYPE_INTR 3
+#define USBD_EP_TYPE_MASK 3
+
+/**
+ * USB endpoint direction and number.
+ */
+#define USB_EP_DIR_MASK 0x80U
+#define USB_EP_DIR_IN   0x80U
+#define USB_EP_DIR_OUT  0x00U
+
+#define USB_EP_OUT_MSK 0x7FU
+#define USB_EP_IN_MSK  0x80U
+
+/** Get endpoint index (number) from endpoint address */
+#define USB_EP_GET_IDX(ep) ((ep) & ~USB_EP_DIR_MASK)
+/** Get direction from endpoint address */
+#define USB_EP_GET_DIR(ep) ((ep)&USB_EP_DIR_MASK)
+/** Get endpoint address from endpoint index and direction */
+#define USB_EP_GET_ADDR(idx, dir) ((idx) | ((dir)&USB_EP_DIR_MASK))
+/** True if the endpoint is an IN endpoint */
+#define USB_EP_DIR_IS_IN(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_IN)
+/** True if the endpoint is an OUT endpoint */
+#define USB_EP_DIR_IS_OUT(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_OUT)
+
+#define USB_SET_EP_OUT(ep) (ep & USB_EP_OUT_MSK)
+#define USB_SET_EP_IN(ep)  (ep | USB_EP_IN_MSK)
+
+#define USB_OUT_EP_NUM 8
+#define USB_IN_EP_NUM  8
+
+#define USB_CTRL_EP_MPS        64 /**< maximum packet size (MPS) for EP 0 */
+#define USB_FS_MAX_PACKET_SIZE 64 /**< full speed MPS for bulk EP */
+
+/* Default USB control EP, always 0 and 0x80 */
+#define USB_CONTROL_OUT_EP0 0
+#define USB_CONTROL_IN_EP0  0x80
+
+#define USB_DC_EP_TYPE_CTRL 0x5 /*0*/
+#define USB_DC_EP_TYPE_ISOC 0x2 /*1*/
+#define USB_DC_EP_TYPE_BULK 0x4 /*2*/
+#define USB_DC_EP_TYPE_INTR 0x0 /*3*/
+
+#define USB_DC_EP1_IN_DR  (0x4000D800 + 0x118)
+#define USB_DC_EP1_OUT_DR (0x4000D800 + 0x11c)
+#define USB_DC_EP2_IN_DR  (0x4000D800 + 0x128)
+#define USB_DC_EP2_OUT_DR (0x4000D800 + 0x12c)
+#define USB_DC_EP3_IN_DR  (0x4000D800 + 0x138)
+#define USB_DC_EP3_OUT_DR (0x4000D800 + 0x13c)
+#define USB_DC_EP4_IN_DR  (0x4000D800 + 0x148)
+#define USB_DC_EP4_OUT_DR (0x4000D800 + 0x14c)
+#define USB_DC_EP5_IN_DR  (0x4000D800 + 0x158)
+#define USB_DC_EP5_OUT_DR (0x4000D800 + 0x15c)
+#define USB_DC_EP6_IN_DR  (0x4000D800 + 0x168)
+#define USB_DC_EP6_OUT_DR (0x4000D800 + 0x16c)
+#define USB_DC_EP7_IN_DR  (0x4000D800 + 0x178)
+#define USB_DC_EP7_OUT_DR (0x4000D800 + 0x17c)
+
+enum usb_dc_event_type {
+    /** USB error reported by the controller */
+    USB_DC_EVENT_ERROR,
+    /** USB reset */
+    USB_DC_EVENT_RESET,
+    /** Start of Frame received */
+    USB_DC_EVENT_SOF,
+    /** USB connection established, hardware enumeration is completed */
+    USB_DC_EVENT_CONNECTED,
+    /** USB configuration done */
+    USB_DC_EVENT_CONFIGURED,
+    /** USB connection suspended by the HOST */
+    USB_DC_EVENT_SUSPEND,
+    /** USB connection lost */
+    USB_DC_EVENT_DISCONNECTED,
+    /** USB connection resumed by the HOST */
+    USB_DC_EVENT_RESUME,
+
+    /** USB interface selected */
+    USB_DC_EVENT_SET_INTERFACE,
+    /** USB interface selected */
+    USB_DC_EVENT_SET_REMOTE_WAKEUP,
+    /** USB interface selected */
+    USB_DC_EVENT_CLEAR_REMOTE_WAKEUP,
+    /** Set Feature ENDPOINT_HALT received */
+    USB_DC_EVENT_SET_HALT,
+    /** Clear Feature ENDPOINT_HALT received */
+    USB_DC_EVENT_CLEAR_HALT,
+    /** setup packet received */
+    USB_DC_EVENT_SETUP_NOTIFY,
+    /** ep0 in packet received */
+    USB_DC_EVENT_EP0_IN_NOTIFY,
+    /** ep0 out packet received */
+    USB_DC_EVENT_EP0_OUT_NOTIFY,
+    /** ep in packet except ep0 received */
+    USB_DC_EVENT_EP_IN_NOTIFY,
+    /** ep out packet except ep0 received */
+    USB_DC_EVENT_EP_OUT_NOTIFY,
+    /** Initial USB connection status */
+    USB_DC_EVENT_UNKNOWN
+};
+
+enum usb_dc_ep_it_type {
+    USB_SOF_IT = 1 << 0,
+    USB_EP1_DATA_IN_IT = 1 << 10,
+    USB_EP1_DATA_OUT_IT = 1 << 11,
+    USB_EP2_DATA_IN_IT = 1 << 12,
+    USB_EP2_DATA_OUT_IT = 1 << 13,
+    USB_EP3_DATA_IN_IT = 1 << 14,
+    USB_EP3_DATA_OUT_IT = 1 << 15,
+    USB_EP4_DATA_IN_IT = 1 << 16,
+    USB_EP4_DATA_OUT_IT = 1 << 17,
+    USB_EP5_DATA_IN_IT = 1 << 18,
+    USB_EP5_DATA_OUT_IT = 1 << 19,
+    USB_EP6_DATA_IN_IT = 1 << 20,
+    USB_EP6_DATA_OUT_IT = 1 << 21,
+    USB_EP7_DATA_IN_IT = 1 << 22,
+    USB_EP7_DATA_OUT_IT = 1 << 23,
+};
+
+enum usb_error_type {
+    USB_DC_OK = 0,
+    USB_DC_EP_DIR_ERR = 1,
+    USB_DC_EP_EN_ERR = 2,
+    USB_DC_EP_TIMEOUT_ERR = 3,
+    USB_DC_ADDR_ERR = 4,
+    USB_DC_RB_SIZE_SMALL_ERR = 5,
+    USB_DC_ZLP_ERR = 6,
+};
+/**
+ * @brief USB Endpoint Configuration.
+ *
+ * Structure containing the USB endpoint configuration.
+ */
+struct usb_dc_ep_cfg {
+    /** The number associated with the EP in the device
+     *  configuration structure
+     *       IN  EP = 0x80 | \
+     *       OUT EP = 0x00 | \
+     */
+    uint8_t ep_addr;
+    /** Endpoint max packet size */
+    uint16_t ep_mps;
+    /** Endpoint Transfer Type.
+     * May be Bulk, Interrupt, Control or Isochronous
+     */
+    uint8_t ep_type;
+};
+
+/*
+ * USB endpoint  structure.
+ */
+typedef struct
+{
+    uint8_t ep_ena;
+    uint32_t is_stalled;
+    struct usb_dc_ep_cfg ep_cfg;
+} usb_dc_ep_state_t;
+
+typedef struct usb_dc_device {
+    struct device parent;
+    uint8_t id;
+    usb_dc_ep_state_t in_ep[8];  /*!< IN endpoint parameters             */
+    usb_dc_ep_state_t out_ep[8]; /*!< OUT endpoint parameters            */
+    void *tx_dma;
+    void *rx_dma;
+} usb_dc_device_t;
+
+int usb_dc_register(enum usb_index_type index, const char *name);
+
+int usb_dc_set_dev_address(const uint8_t addr);
+int usb_dc_ep_open(struct device *dev, const struct usb_dc_ep_cfg *ep_cfg);
+int usb_dc_ep_close(const uint8_t ep);
+int usb_dc_ep_set_stall(const uint8_t ep);
+int usb_dc_ep_clear_stall(const uint8_t ep);
+int usb_dc_ep_is_stalled(struct device *dev, const uint8_t ep, uint8_t *stalled);
+int usb_dc_ep_write(struct device *dev, const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes);
+int usb_dc_ep_read(struct device *dev, const uint8_t ep, uint8_t *data, uint32_t data_len, uint32_t *read_bytes);
+int usb_dc_receive_to_ringbuffer(struct device *dev, Ring_Buffer_Type *rb, uint8_t ep);
+int usb_dc_send_from_ringbuffer(struct device *dev, Ring_Buffer_Type *rb, uint8_t ep);
+#ifdef __cplusplus
+}
+#endif
+#endif
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_wdt.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_wdt.h
new file mode 100644
index 00000000..0a538e61
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_wdt.h
@@ -0,0 +1,64 @@
+/**
+ * @file hal_wdt.h
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef __HAL_WDT__H__
+#define __HAL_WDT__H__
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_common.h"
+#include "drv_device.h"
+#include "bl702_config.h"
+
+#define DEVICE_CTRL_GET_WDT_COUNTER (0x10)
+#define DEVICE_CTRL_RST_WDT_COUNTER (0x11)
+#define DEVICE_CTRL_GET_RST_STATUS  (0x12)
+#define DEVICE_CTRL_CLR_RST_STATUS  (0x13)
+
+enum wdt_index_type {
+#ifdef BSP_USING_WDT
+    WDT_INDEX,
+#endif
+    WDT_MAX_INDEX
+};
+
+enum wdt_event_type {
+    WDT_EVENT,
+    WDT_EVENT_UNKNOWN
+};
+
+typedef struct wdt_device {
+    struct device parent;
+    uint8_t id;
+    uint32_t wdt_timeout;
+} wdt_device_t;
+
+#define WDT_DEV(dev) ((wdt_device_t *)dev)
+
+int wdt_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size);
+int wdt_register(enum wdt_index_type index, const char *name);
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_boot2.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_boot2.c
new file mode 100644
index 00000000..0767d521
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_boot2.c
@@ -0,0 +1,477 @@
+#include "hal_boot2.h"
+#include "hal_flash.h"
+#include "bl702_ef_ctrl.h"
+#include "bl702_hbn.h"
+#include "bl702_glb.h"
+#include "bl702_xip_sflash.h"
+#include "tzc_sec_reg.h"
+#include "hal_gpio.h"
+#include "softcrc.h"
+#include "hal_sec_hash.h"
+
+/**
+ * @brief boot2 custom
+ *
+ * @param None
+ * @return uint32
+ */
+uint32_t hal_boot2_custom(void)
+{
+    return 0;
+}
+
+/**
+ * @brief get efuse Boot2 config
+ *
+ * @param g_efuse_cfg
+ * @param
+ * @param
+ * @return None
+ */
+void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg)
+{
+    uint32_t tmp;
+    uint32_t rootClk;
+    uint8_t hdiv = 0, bdiv = 0;
+
+    /* save bclk fclk div and root clock sel */
+    bdiv = GLB_Get_BCLK_Div();
+    hdiv = GLB_Get_HCLK_Div();
+    rootClk = BL_RD_REG(HBN_BASE, HBN_GLB);
+
+    /* change root clock to rc32m for efuse operation */
+    HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M);
+
+    /* Get sign and aes type*/
+    EF_Ctrl_Read_Secure_Boot((EF_Ctrl_Sign_Type *)efuse_cfg->sign, (EF_Ctrl_SF_AES_Type *)efuse_cfg->encrypted);
+    /* Get hash:aes key slot 0 and slot1*/
+    EF_Ctrl_Read_AES_Key(0, (uint32_t *)efuse_cfg->pk_hash_cpu0, 8);
+    EF_Ctrl_Read_Chip_ID(efuse_cfg->chip_id);
+    /* Get HBN check sign config */
+    EF_Ctrl_Read_Sw_Usage(0, &tmp);
+    efuse_cfg->hbn_check_sign = (tmp >> 22) & 0x01;
+
+    /* restore bclk fclk div and root clock sel */
+    GLB_Set_System_CLK_Div(hdiv, bdiv);
+    BL_WR_REG(HBN_BASE, HBN_GLB, rootClk);
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+}
+/**
+ * @brief reset sec eng clock
+ *
+ * @return
+ */
+void hal_boot2_reset_sec_eng(void)
+{
+    GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_SEC);
+}
+
+/**
+ * @brief system soft reset
+ *
+ * @return
+ */
+void hal_boot2_sw_system_reset(void)
+{
+    GLB_SW_System_Reset();
+}
+
+/**
+ * @brief
+ *
+ * @param flag
+ * @param
+ * @param
+ * @return
+ */
+void hal_boot2_set_psmode_status(uint32_t flag)
+{
+    HBN_Set_Status_Flag(flag);
+}
+
+/**
+ * @brief
+ *
+ * @param
+ * @param
+ * @param
+ * @return flag
+ */
+uint32_t hal_boot2_get_psmode_status(void)
+{
+    return HBN_Get_Status_Flag();
+}
+
+/**
+ * @brief
+ *
+ * @param
+ * @param
+ * @param
+ * @return user define flag
+ */
+uint32_t hal_boot2_get_user_fw(void)
+{
+    return BL_RD_WORD(HBN_BASE + HBN_RSV0_OFFSET);
+}
+
+/**
+ * @brief clr user define flag
+ *
+ * @param
+ * @param
+ * @param
+ * @return
+ */
+void hal_boot2_clr_user_fw(void)
+{
+    uint32_t *p = (uint32_t *)(HBN_BASE + HBN_RSV0_OFFSET);
+    *p = 0;
+}
+
+/**
+ * @brief hal_boot2_sboot_finish
+ *
+ * @return
+ */
+void ATTR_TCM_SECTION hal_boot2_sboot_finish(void)
+{
+    uint32_t tmp_val;
+
+    tmp_val = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL);
+
+    tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TZC_SEC_TZC_SBOOT_DONE, 0xf);
+
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmp_val);
+}
+
+/**
+ * @brief hal_boot2_uart_gpio_init
+ *
+ * @return
+ */
+void hal_boot2_uart_gpio_init(void)
+{
+    GLB_GPIO_Type gpios[] = { GPIO_PIN_14, GPIO_PIN_15 };
+
+    GLB_GPIO_Func_Init(GPIO_FUN_UART, gpios, 2);
+
+    GLB_UART_Fun_Sel((GPIO_PIN_14 % 8), GLB_UART_SIG_FUN_UART0_TXD); //  GPIO_FUN_UART1_TX
+    GLB_UART_Fun_Sel((GPIO_PIN_15 % 8), GLB_UART_SIG_FUN_UART0_RXD);
+}
+
+/**
+ * @brief hal_boot2_pll_init
+ *
+ * @return
+ */
+void hal_boot2_debug_uart_gpio_init(void)
+{
+    GLB_GPIO_Type gpios[] = { GPIO_PIN_17 };
+
+    GLB_GPIO_Func_Init(GPIO_FUN_UART, gpios, 1);
+
+    GLB_UART_Fun_Sel((GPIO_PIN_17 % 8), GLB_UART_SIG_FUN_UART1_TXD);
+}
+
+/**
+ * @brief hal_boot2_debug_usb_port_init
+ *
+ * @return
+ */
+#if HAL_BOOT2_SUPPORT_USB_IAP
+void hal_boot2_debug_usb_port_init(void)
+{
+    /* must do this , or usb can not be recognized */
+    cpu_global_irq_disable();
+    cpu_global_irq_enable();
+
+    GLB_GPIO_Type gpios[] = { GPIO_PIN_7, GPIO_PIN_8 };
+    GLB_GPIO_Func_Init(GPIO_FUN_ANALOG, gpios, 2);
+}
+#endif
+
+/**
+ * @brief hal_boot2_debug_uart_gpio_deinit
+ *
+ * @return
+ */
+void hal_boot2_debug_uart_gpio_deinit(void)
+{
+    GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART0);
+    GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART1);
+    GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE);
+}
+
+
+/****************************************************************************/ /**
+ * @brief  Check bootheader crc
+ *
+ * @param  data: bootheader data pointer
+ *
+ * @return boot_error_code type
+ *
+*******************************************************************************/
+static uint32_t hal_boot_check_bootheader(struct hal_bootheader_t *header)
+{
+    uint32_t crc_pass = 0;
+    uint32_t crc;
+
+    if (header->bootCfg.bval.crcIgnore == 1 && header->crc32 == HAL_BOOT2_DEADBEEF_VAL) {
+        //MSG("Crc ignored\r\n");
+        crc_pass = 1;
+    } else {
+        crc = BFLB_Soft_CRC32((uint8_t *)header, sizeof(struct hal_bootheader_t) - sizeof(header->crc32));
+
+        if (header->crc32 == crc) {
+            crc_pass = 1;
+        }
+    }
+    return crc_pass;
+}
+
+/****************************************************************************/ /**
+ * @brief  Check if the input public key is the same as  burned in the efuse
+ *
+ * @param  g_boot_img_cfg: Boot image config pointer
+ * @param  data: Image data pointer
+ *
+ * @return boot_error_code type
+ *
+*******************************************************************************/
+int32_t hal_boot_parse_bootheader(boot2_image_config *boot_img_cfg, uint8_t *data)
+{
+    struct  hal_bootheader_t *header = (struct  hal_bootheader_t *)data;
+    uint32_t crc_pass = 0;
+    uint32_t i = 0;
+    uint32_t *phash = (uint32_t *)header->hash;
+
+    crc_pass=hal_boot_check_bootheader(header);
+
+    if (!crc_pass) {
+        //MSG_ERR("bootheader crc error\r\n");
+        //blsp_dump_data((uint8_t *)&crc, 4);
+        return 0x0204;
+    }
+
+    if (header->bootCfg.bval.notLoadInBoot) {
+        return 0x0202;
+    }
+
+    /* Get which CPU's img it is*/
+    for (i = 0; i < HAL_BOOT2_CPU_MAX; i++) {
+        if (0 == memcmp((void *)&header->magicCode, HAL_BOOT2_CPU0_MAGIC,
+                        sizeof(header->magicCode))) {
+            break;
+        } else if (0 == memcmp((void *)&header->magicCode, HAL_BOOT2_CPU1_MAGIC,
+                               sizeof(header->magicCode))) {
+            break;
+        }
+    }
+
+    if (i == HAL_BOOT2_CPU_MAX) {
+        /* No cpu img magic match */
+        //MSG_ERR("Magic code error\r\n");
+        return 0x0203;
+    }
+
+    if(boot_img_cfg==NULL){
+        return 0;
+    }
+    
+    boot_img_cfg->pk_src=i;    
+    boot_img_cfg->img_valid=0;
+
+    /* Deal with pll config */
+
+    /* Encrypt and sign */
+    boot_img_cfg->basic_cfg.encrypt_type = header->bootCfg.bval.encrypt_type;
+    boot_img_cfg->basic_cfg.sign_type = header->bootCfg.bval.sign;
+    boot_img_cfg->basic_cfg.key_sel = header->bootCfg.bval.key_sel;
+
+    /* Xip relative */
+    boot_img_cfg->basic_cfg.no_segment = header->bootCfg.bval.no_segment;
+    boot_img_cfg->cpu_cfg[0].cache_enable = header->bootCfg.bval.cache_enable;
+    boot_img_cfg->basic_cfg.aes_region_lock = header->bootCfg.bval.aes_region_lock;
+    //boot_img_cfg->cpu_cfg[1].halt_cpu = header->bootCfg.bval.halt_cpu1;
+    boot_img_cfg->cpu_cfg[0].cache_way_dis = header->bootCfg.bval.cache_way_disable;
+    boot_img_cfg->basic_cfg.hash_ignore = header->bootCfg.bval.hash_ignore;
+    /* Firmware len*/
+    boot_img_cfg->basic_cfg.img_len_cnt= header->img_segment_info.img_len;
+
+    /* Boot entry and flash offset */
+    boot_img_cfg->cpu_cfg[0].boot_entry = header->bootEntry;
+    boot_img_cfg->basic_cfg.group_image_offset = header->img_start.flash_offset;
+
+    boot_img_cfg->cpu_cfg[0].config_enable=1;
+    boot_img_cfg->cpu_cfg[0].halt_cpu =0;
+
+    //MSG("sign %d,encrypt:%d\r\n", boot_img_cfg->sign_type,boot_img_cfg->encrypt_type);
+
+    /* Check encrypt and sign match*/
+    if (g_efuse_cfg.encrypted[i] != 0) {
+        if (boot_img_cfg->basic_cfg.encrypt_type == 0) {
+            //MSG_ERR("Encrypt not fit\r\n");
+            return 0x0205;
+        }
+    }
+
+    if (g_efuse_cfg.sign[i] !=boot_img_cfg->basic_cfg.sign_type) {
+        //MSG_ERR("sign not fit\r\n");
+        boot_img_cfg->basic_cfg.sign_type = g_efuse_cfg.sign[i];
+        return 0x0206;
+    }
+
+    if (g_ps_mode == 1 && (!g_efuse_cfg.hbn_check_sign)) {
+        /* In HBN Mode, if user select to ignore hash and sign*/
+        boot_img_cfg->basic_cfg.hash_ignore = 1;
+    } else if ((boot_img_cfg->basic_cfg.hash_ignore == 1 && *phash != HAL_BOOT2_DEADBEEF_VAL) ||
+                g_efuse_cfg.sign[i] != 0) {
+        /* If signed or user not really want to ignore, hash can't be ignored*/
+        boot_img_cfg->basic_cfg.hash_ignore = 0;
+    }
+
+    if (g_user_hash_ignored) {
+        boot_img_cfg->basic_cfg.hash_ignore = 1;
+    }
+
+    ARCH_MemCpy_Fast(boot_img_cfg->basic_cfg.hash, header->hash, sizeof(header->hash));
+
+    if (boot_img_cfg->basic_cfg.img_len_cnt == 0) {
+        return 0x0207;
+    }
+
+    return 0;
+}
+
+void ATTR_TCM_SECTION hal_boot2_clean_cache(void)
+{
+    /* no need clean again since hal_boot2_set_cache will also clean
+      unused way,and bl702 no data cache except psram */
+}
+
+
+BL_Err_Type ATTR_TCM_SECTION hal_boot2_set_cache(uint8_t cont_read, boot2_image_config *boot_img_cfg)
+{
+    return flash_set_cache(cont_read, boot_img_cfg->cpu_cfg[0].cache_enable, 
+                    boot_img_cfg->cpu_cfg[0].cache_way_dis,
+                    boot_img_cfg->basic_cfg.group_image_offset);
+}
+ 
+/****************************************************************************/ /**
+ * @brief  get the ram image name and count
+ *
+ * @param  img_name: ram image name in partition
+ * @param  ram_img_cnt: ram image count that support boot from flash
+ *
+ * @return None
+ *
+*******************************************************************************/
+void hal_boot2_get_ram_img_cnt(char* img_name[],uint32_t *ram_img_cnt )
+{
+    *ram_img_cnt=0;
+}
+
+/****************************************************************************/ /**
+ * @brief  get the ram image info
+ *
+ * @param  data: bootheader information
+ * @param  image_offset: ram image offset in flash(from of bootheader)
+ * @param  img_len: ram image length
+ * @param  hash: pointer to hash pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void hal_boot2_get_img_info(uint8_t *data, uint32_t *image_offset, uint32_t *img_len,uint8_t **hash)
+{
+    *img_len=0;
+}
+
+/****************************************************************************/ /**
+ * @brief  release other cpu to boot up
+ *
+ * @param  core: core number
+ * @param  boot_addr: boot address
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr)
+{
+
+}
+
+/****************************************************************************/ /**
+ * @brief  get xip address according to flash addr
+ *
+ * @param  flash_addr: flash address
+ *
+ * @return XIP Address
+ *
+*******************************************************************************/
+uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr)
+{
+    uint32_t img_offset= SF_Ctrl_Get_Flash_Image_Offset();
+    if(flash_addr>=img_offset){
+        return BL702_FLASH_XIP_BASE+(flash_addr-img_offset);
+    }else{
+        return 0;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  get multi-group count
+ *
+ * @param  None
+ *
+ * @return 1 for multi-group 0 for not
+ *
+*******************************************************************************/
+uint32_t hal_boot2_get_grp_count(void)
+{
+    return 1;
+}
+
+/****************************************************************************/ /**
+ * @brief  get cpu count
+ *
+ * @param  None
+ *
+ * @return 1 for multi-group 0 for not
+ *
+*******************************************************************************/
+uint32_t hal_boot2_get_cpu_count(void)
+{
+    return 1;
+}
+
+/****************************************************************************/ /**
+ * @brief  get cpu count
+ *
+ * @param  None
+ *
+ * @return 1 for multi-group 0 for not
+ *
+*******************************************************************************/
+uint32_t ATTR_TCM_SECTION hal_boot2_get_feature_flag(void)
+{
+    return HAL_BOOT2_SP_FLAG;
+}
+
+/****************************************************************************/ /**
+ * @brief  get boot header offset
+ *
+ * @param  None
+ *
+ * @return bootheader offset
+ *
+*******************************************************************************/
+uint32_t hal_boot2_get_bootheader_offset(void)
+{
+    return 0x00;
+}
+
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_clock.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_clock.c
new file mode 100644
index 00000000..56a00373
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_clock.c
@@ -0,0 +1,660 @@
+/**
+ * @file hal_clock.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+
+#include "hal_clock.h"
+#include "bl702_glb.h"
+#include "bl702_pwm.h"
+#include "bl702_timer.h"
+
+#if XTAL_TYPE != EXTERNAL_XTAL_32M
+static void internal_rc32m_init(void) {
+  uint32_t tmpVal;
+  tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
+  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_XTAL_CAPCODE_EXTRA_AON);
+  BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
+
+  tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_OUT_AON, 0);
+  BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
+
+  tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON, 0);
+  BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
+
+  tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_RDY_SEL_AON, 0);
+  BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
+
+  tmpVal = BL_RD_REG(AON_BASE, AON_TSEN);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_RDY_INT_SEL_AON, 0);
+  BL_WR_REG(AON_BASE, AON_TSEN, tmpVal);
+
+  for (uint32_t i = 0; i < 20000; i++) {
+    tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_XTAL_EXT_SEL_AON);
+    BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
+    tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_XTAL_EXT_SEL_AON);
+    BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
+    if (BL_IS_REG_BIT_SET(BL_RD_REG(GLB_BASE, GLB_CLK_CFG0), GLB_CHIP_RDY))
+      break;
+  }
+}
+#endif
+
+static uint32_t mtimer_get_clk_src_div(void) { return (system_clock_get(SYSTEM_CLOCK_BCLK) / 1000 / 1000 - 1); }
+
+static void peripheral_clock_gate_all() {
+  uint32_t tmpVal;
+  tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
+  // tmpVal &= (~(1 << BL_AHB_SLAVE1_GPIP));
+  // tmpVal &= (~(1 << BL_AHB_SLAVE1_SEC_DBG));
+  // tmpVal &= (~(1 << BL_AHB_SLAVE1_SEC));
+  tmpVal &= (~(1 << BL_AHB_SLAVE1_TZ1));
+  tmpVal &= (~(1 << BL_AHB_SLAVE1_TZ2));
+  tmpVal &= (~(1 << BL_AHB_SLAVE1_DMA));
+  tmpVal &= (~(1 << BL_AHB_SLAVE1_EMAC));
+  tmpVal &= (~(1 << BL_AHB_SLAVE1_UART0));
+  tmpVal &= (~(1 << BL_AHB_SLAVE1_UART1));
+  tmpVal &= (~(1 << BL_AHB_SLAVE1_SPI));
+  tmpVal &= (~(1 << BL_AHB_SLAVE1_I2C));
+  tmpVal &= (~(1 << BL_AHB_SLAVE1_PWM));
+  tmpVal &= (~(1 << BL_AHB_SLAVE1_TMR));
+  tmpVal &= (~(1 << BL_AHB_SLAVE1_IRR));
+  tmpVal &= (~(1 << BL_AHB_SLAVE1_CKS));
+  tmpVal &= (~(1 << 24)); // QDEC0
+  tmpVal &= (~(1 << 25)); // QDEC1
+  tmpVal &= (~(1 << 26)); // QDEC2/I2S
+  tmpVal &= (~(1 << 27)); // KYS
+  tmpVal &= (~(1 << BL_AHB_SLAVE1_USB));
+  tmpVal &= (~(1 << BL_AHB_SLAVE1_CAM));
+  tmpVal &= (~(1 << BL_AHB_SLAVE1_MJPEG));
+  BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
+}
+
+void system_clock_init(void) {
+#if XTAL_TYPE != EXTERNAL_XTAL_32M
+  internal_rc32m_init();
+  AON_Power_Off_XTAL();
+#endif
+  /*select root clock*/
+  GLB_Set_System_CLK(XTAL_TYPE, BSP_ROOT_CLOCK_SOURCE);
+#if BSP_ROOT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_57P6M
+  /* fix 57.6M */
+  SystemCoreClockSet(57.6 * 1000 * 1000);
+#endif
+  /*set fclk/hclk and bclk clock*/
+  GLB_Set_System_CLK_Div(BSP_FCLK_DIV, BSP_BCLK_DIV);
+  /* Set MTimer the same frequency as SystemCoreClock */
+  GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div());
+#ifndef FAST_WAKEUP
+#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE
+  PDS_Set_Audio_PLL_Freq(BSP_AUDIO_PLL_CLOCK_SOURCE - ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ);
+#endif
+#endif
+#if XTAL_32K_TYPE == INTERNAL_RC_32K
+  HBN_32K_Sel(HBN_32K_RC);
+  HBN_Power_Off_Xtal_32K();
+#else
+  HBN_Power_On_Xtal_32K();
+  HBN_32K_Sel(HBN_32K_XTAL);
+#endif
+#if XTAL_TYPE == EXTERNAL_XTAL_32M
+  HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_XTAL);
+#else
+  HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_RC32M);
+#endif
+}
+
+void peripheral_clock_init(void) {
+  uint32_t tmpVal = 0;
+
+  peripheral_clock_gate_all();
+
+  tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
+#if defined(BSP_USING_UART0) || defined(BSP_USING_UART1)
+#if defined(BSP_USING_UART0)
+  tmpVal |= (1 << BL_AHB_SLAVE1_UART0);
+#endif
+#if defined(BSP_USING_UART1)
+  tmpVal |= (1 << BL_AHB_SLAVE1_UART1);
+#endif
+#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_96M
+  GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_96M, BSP_UART_CLOCK_DIV);
+#elif BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK
+  GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_FCLK, BSP_UART_CLOCK_DIV);
+#else
+#error "please select correct uart clock source"
+#endif
+#endif
+
+#if defined(BSP_USING_I2C0)
+#if BSP_I2C_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK
+  tmpVal |= (1 << BL_AHB_SLAVE1_I2C);
+  GLB_Set_I2C_CLK(ENABLE, BSP_I2C_CLOCK_DIV);
+#else
+#error "please select correct i2c clock source"
+#endif
+#endif
+
+#if defined(BSP_USING_SPI0)
+#if BSP_SPI_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK
+  tmpVal |= (1 << BL_AHB_SLAVE1_SPI);
+  GLB_Set_SPI_CLK(ENABLE, BSP_SPI_CLOCK_DIV);
+#else
+#error "please select correct spi clock source"
+#endif
+#endif
+
+#if defined(BSP_USING_TIMER0)
+  tmpVal |= (1 << BL_AHB_SLAVE1_TMR);
+  BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
+
+#if BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK
+  /* Configure timer clock source */
+  uint32_t tmp = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
+  tmp          = BL_SET_REG_BITS_VAL(tmp, TIMER_CS_1, TIMER_CLKSRC_FCLK);
+  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp);
+
+  /* Configure timer clock division */
+  tmp = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
+  tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR2, BSP_TIMER0_CLOCK_DIV);
+  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp);
+#elif BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
+  /* Configure timer clock source */
+  uint32_t tmp = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
+  tmp          = BL_SET_REG_BITS_VAL(tmp, TIMER_CS_1, TIMER_CLKSRC_XTAL);
+  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp);
+
+  /* Configure timer clock division */
+  tmp = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
+  tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR2, BSP_TIMER0_CLOCK_DIV);
+  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp);
+#elif BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
+  /* Configure timer clock source */
+  uint32_t tmp = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
+  tmp          = BL_SET_REG_BITS_VAL(tmp, TIMER_CS_1, TIMER_CLKSRC_32K);
+  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp);
+
+  /* Configure timer clock division */
+  tmp = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
+  tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR2, BSP_TIMER0_CLOCK_DIV);
+  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp);
+#elif BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_1K_CLK
+  /* Configure timer clock source */
+  uint32_t tmp = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
+  tmp          = BL_SET_REG_BITS_VAL(tmp, TIMER_CS_1, TIMER_CLKSRC_1K);
+  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp);
+
+  /* Configure timer clock division */
+  tmp = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
+  tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR2, BSP_TIMER0_CLOCK_DIV);
+  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp);
+#else
+#error "please select correct timer0 clock source"
+#endif
+#endif
+
+#if defined(BSP_USING_TIMER1)
+  tmpVal |= (1 << BL_AHB_SLAVE1_TMR);
+  BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
+
+#if BSP_TIMER1_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK
+  /* Configure timer clock source */
+  uint32_t tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
+  tmp1          = BL_SET_REG_BITS_VAL(tmp1, TIMER_CS_2, TIMER_CLKSRC_FCLK);
+  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp1);
+
+  /* Configure timer clock division */
+  tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
+  tmp1 = BL_SET_REG_BITS_VAL(tmp1, TIMER_TCDR3, BSP_TIMER1_CLOCK_DIV);
+  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp1);
+#elif BSP_TIMER1_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
+  /* Configure timer clock source */
+  uint32_t tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
+  tmp1          = BL_SET_REG_BITS_VAL(tmp1, TIMER_CS_2, TIMER_CLKSRC_XTAL);
+  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp1);
+
+  /* Configure timer clock division */
+  tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
+  tmp1 = BL_SET_REG_BITS_VAL(tmp1, TIMER_TCDR3, BSP_TIMER1_CLOCK_DIV);
+  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp1);
+#elif BSP_TIMER1_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
+  /* Configure timer clock source */
+  uint32_t tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
+  tmp1          = BL_SET_REG_BITS_VAL(tmp1, TIMER_CS_2, TIMER_CLKSRC_32K);
+  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp1);
+
+  /* Configure timer clock division */
+  tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
+  tmp1 = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR3, BSP_TIMER1_CLOCK_DIV);
+  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp1);
+#elif BSP_TIMER1_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_1K_CLK
+  /* Configure timer clock source */
+  uint32_t tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
+  tmp1          = BL_SET_REG_BITS_VAL(tmp1, TIMER_CS_2, TIMER_CLKSRC_1K);
+  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp1);
+
+  /* Configure timer clock division */
+  tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
+  tmp1 = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR3, BSP_TIMER1_CLOCK_DIV);
+  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp1);
+#else
+#error "please select correct timer1 clock source"
+#endif
+#endif
+
+#if defined(BSP_USING_WDT)
+  tmpVal |= (1 << BL_AHB_SLAVE1_TMR);
+  BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
+
+#if BSP_WDT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK
+  /* Configure watchdog timer clock source */
+  uint32_t tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
+  tmpwdt          = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_CS_WDT, TIMER_CLKSRC_FCLK);
+  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpwdt);
+
+  /* Configure watchdog timer clock division */
+  tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
+  tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_WCDR, BSP_WDT_CLOCK_DIV);
+  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpwdt);
+#elif BSP_WDT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
+  /* Configure watchdog timer clock source */
+  uint32_t tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
+  tmpwdt          = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_CS_WDT, TIMER_CLKSRC_XTAL);
+  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpwdt);
+
+  /* Configure watchdog timer clock division */
+  tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
+  tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_WCDR, BSP_WDT_CLOCK_DIV);
+  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpwdt);
+#elif BSP_WDT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
+  /* Configure watchdog timer clock source */
+  uint32_t tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
+  tmpwdt          = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_CS_WDT, TIMER_CLKSRC_32K);
+  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpwdt);
+
+  /* Configure watchdog timer clock division */
+  tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
+  tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_WCDR, BSP_WDT_CLOCK_DIV);
+  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpwdt);
+#elif BSP_WDT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_1K_CLK
+  /* Configure watchdog timer clock source */
+  uint32_t tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
+  tmpwdt          = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_CS_WDT, TIMER_CLKSRC_1K);
+  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpwdt);
+
+  /* Configure watchdog timer clock division */
+  tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
+  tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_WCDR, BSP_WDT_CLOCK_DIV);
+  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpwdt);
+#else
+#error "please select correct watchdog timer clock source"
+#endif
+#endif
+
+#if defined(BSP_USING_PWM_CH0) || defined(BSP_USING_PWM_CH1) || defined(BSP_USING_PWM_CH2) || defined(BSP_USING_PWM_CH3) || defined(BSP_USING_PWM_CH4) || defined(BSP_USING_PWM_CH5)
+  tmpVal |= (1 << BL_AHB_SLAVE1_PWM);
+  BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
+
+  uint32_t timeoutCnt = 160 * 1000;
+  uint32_t tmp_pwm;
+  uint32_t PWMx;
+#if BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
+
+  for (int i = 0; i < 5; i++) {
+    PWMx    = PWM_BASE + PWM_CHANNEL_OFFSET + (i)*0x20;
+    tmp_pwm = BL_RD_REG(PWMx, PWM_CONFIG);
+    BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmp_pwm, PWM_STOP_EN));
+
+    while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)) {
+      timeoutCnt--;
+
+      if (timeoutCnt == 0) {
+        return;
+      }
+    }
+    tmp_pwm = BL_RD_REG(PWMx, PWM_CONFIG);
+    tmp_pwm = BL_SET_REG_BITS_VAL(tmp_pwm, PWM_REG_CLK_SEL, PWM_CLK_32K);
+    BL_WR_REG(PWMx, PWM_CONFIG, tmp_pwm);
+    /* Config pwm division */
+    BL_WR_REG(PWMx, PWM_CLKDIV, BSP_PWM_CLOCK_DIV + 1);
+  }
+#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK
+
+  for (int i = 0; i < 5; i++) {
+    PWMx    = PWM_BASE + PWM_CHANNEL_OFFSET + (i)*0x20;
+    tmp_pwm = BL_RD_REG(PWMx, PWM_CONFIG);
+    BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmp_pwm, PWM_STOP_EN));
+
+    while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)) {
+      timeoutCnt--;
+
+      if (timeoutCnt == 0) {
+        return;
+      }
+    }
+    tmp_pwm = BL_RD_REG(PWMx, PWM_CONFIG);
+    tmp_pwm = BL_SET_REG_BITS_VAL(tmp_pwm, PWM_REG_CLK_SEL, PWM_CLK_BCLK);
+    BL_WR_REG(PWMx, PWM_CONFIG, tmp_pwm);
+    /* Config pwm division */
+    BL_WR_REG(PWMx, PWM_CLKDIV, BSP_PWM_CLOCK_DIV + 1);
+  }
+#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
+
+  for (int i = 0; i < 5; i++) {
+    PWMx    = PWM_BASE + PWM_CHANNEL_OFFSET + (i)*0x20;
+    tmp_pwm = BL_RD_REG(PWMx, PWM_CONFIG);
+    BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmp_pwm, PWM_STOP_EN));
+
+    while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)) {
+      timeoutCnt--;
+
+      if (timeoutCnt == 0) {
+        return;
+      }
+    }
+    tmp_pwm = BL_RD_REG(PWMx, PWM_CONFIG);
+    tmp_pwm = BL_SET_REG_BITS_VAL(tmp_pwm, PWM_REG_CLK_SEL, PWM_CLK_XCLK);
+    BL_WR_REG(PWMx, PWM_CONFIG, tmp_pwm);
+    /* Config pwm division */
+    BL_WR_REG(PWMx, PWM_CLKDIV, BSP_PWM_CLOCK_DIV + 1);
+  }
+#else
+#error "please select correct pwm clock source"
+#endif
+#endif
+
+#if defined(BSP_USING_IR)
+  tmpVal |= (1 << BL_AHB_SLAVE1_IRR);
+  GLB_Set_IR_CLK(ENABLE, 0, BSP_IR_CLOCK_DIV);
+#endif
+
+#if defined(BSP_USING_I2S0)
+  tmpVal |= (1 << BL_AHB_SLAVE1_I2S);
+  GLB_Set_I2S_CLK(ENABLE, GLB_I2S_OUT_REF_CLK_NONE);
+#endif
+
+#if defined(BSP_USING_ADC0)
+  tmpVal |= (1 << BL_AHB_SLAVE1_GPIP);
+#if BSP_ADC_CLOCK_SOURCE >= ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ
+  GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_AUDIO_PLL, BSP_ADC_CLOCK_DIV);
+#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
+  GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, BSP_ADC_CLOCK_DIV);
+#else
+#error "please select correct adc clock source"
+#endif
+#endif
+
+#if defined(BSP_USING_DAC0)
+  tmpVal |= (1 << BL_AHB_SLAVE1_GPIP);
+#if BSP_DAC_CLOCK_SOURCE >= ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ
+  GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_AUDIO_PLL, BSP_DAC_CLOCK_DIV + 1);
+#elif BSP_DAC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
+  GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_XCLK, BSP_DAC_CLOCK_DIV + 1);
+#else
+#error "please select correct dac clock source"
+#endif
+#endif
+
+#if defined(BSP_USING_CAM0)
+  tmpVal |= (1 << BL_AHB_SLAVE1_CAM);
+#if BSP_CAM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_96M
+  GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_DLL96M, BSP_CAM_CLOCK_DIV);
+  GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_CAM);
+#elif BSP_CAM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
+  GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_XCLK, BSP_CAM_CLOCK_DIV);
+  GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_CAM);
+#else
+#error "please select correct camera clock source"
+#endif
+#endif
+
+#if defined(BSP_USING_QDEC0) || defined(BSP_USING_QDEC1) || defined(BSP_USING_QDEC2) || defined(BSP_USING_KEYSCAN)
+#ifdef BSP_USING_KEYSCAN
+  tmpVal |= (1 << 27);
+#endif
+#if defined(BSP_USING_QDEC0)
+  tmpVal |= (1 << 24);
+#endif
+#if defined(BSP_USING_QDEC1)
+  tmpVal |= (1 << 25);
+#endif
+#if defined(BSP_USING_QDEC2)
+  tmpVal |= (1 << 26);
+#endif
+#if BSP_QDEC_KEYSCAN_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
+  GLB_Set_QDEC_CLK(GLB_QDEC_CLK_F32K, BSP_QDEC_KEYSCAN_CLOCK_DIV);
+#elif BSP_QDEC_KEYSCAN_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
+  GLB_Set_QDEC_CLK(GLB_QDEC_CLK_XCLK, BSP_QDEC_KEYSCAN_CLOCK_DIV);
+#else
+#error "please select correct qdec or keyscan clock source"
+#endif
+#endif
+
+#if defined(BSP_USING_USB)
+  tmpVal |= (1 << BL_AHB_SLAVE1_USB);
+  GLB_Set_USB_CLK(1);
+#endif
+  BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
+}
+
+uint32_t system_clock_get(enum system_clock_type type) {
+  switch (type) {
+  case SYSTEM_CLOCK_ROOT_CLOCK:
+    if (GLB_Get_Root_CLK_Sel() == 0) {
+      return 32 * 1000 * 1000;
+    } else if (GLB_Get_Root_CLK_Sel() == 1)
+      return 32 * 1000 * 1000;
+    else {
+      uint32_t tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+      tmpVal          = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PLL_SEL);
+      if (tmpVal == 0) {
+        return 57.6 * 1000 * 1000;
+      } else if (tmpVal == 1) {
+        return 96 * 1000 * 1000;
+      } else if (tmpVal == 2) {
+        return 144 * 1000 * 1000;
+      } else {
+        return 0;
+      }
+    }
+  case SYSTEM_CLOCK_FCLK:
+    return system_clock_get(SYSTEM_CLOCK_ROOT_CLOCK) / (GLB_Get_HCLK_Div() + 1);
+
+  case SYSTEM_CLOCK_BCLK:
+    return system_clock_get(SYSTEM_CLOCK_ROOT_CLOCK) / (GLB_Get_HCLK_Div() + 1) / (GLB_Get_BCLK_Div() + 1);
+
+  case SYSTEM_CLOCK_XCLK:
+    return 32000000;
+  case SYSTEM_CLOCK_32K_CLK:
+    return 32000;
+  case SYSTEM_CLOCK_AUPLL:
+#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE
+    if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ) {
+      return 12288000;
+    } else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_11289600_HZ) {
+      return 11289600;
+    } else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_5644800_HZ) {
+      return 5644800;
+    } else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_24576000_HZ) {
+      return 24576000;
+    } else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ) {
+      return 24000000;
+    }
+#endif
+  default:
+    break;
+  }
+
+  return 0;
+}
+
+uint32_t peripheral_clock_get(enum peripheral_clock_type type) {
+  uint32_t tmpVal;
+  uint32_t div;
+
+  switch (type) {
+#if defined(BSP_USING_UART0) || defined(BSP_USING_UART1)
+  case PERIPHERAL_CLOCK_UART:
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL);
+
+    div = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    div = BL_GET_REG_BITS_VAL(div, GLB_UART_CLK_DIV);
+    if (tmpVal == HBN_UART_CLK_FCLK) {
+      return system_clock_get(SYSTEM_CLOCK_FCLK) / (div + 1);
+    } else if (tmpVal == HBN_UART_CLK_96M) {
+      return 96000000 / (div + 1);
+    }
+#endif
+#if defined(BSP_USING_SPI0)
+  case PERIPHERAL_CLOCK_SPI:
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    div    = BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV);
+    return system_clock_get(SYSTEM_CLOCK_BCLK) / (div + 1);
+#endif
+#if defined(BSP_USING_I2C0)
+  case PERIPHERAL_CLOCK_I2C:
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    div    = BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV);
+    return system_clock_get(SYSTEM_CLOCK_BCLK) / (div + 1);
+#endif
+#if defined(BSP_USING_I2S0)
+  case PERIPHERAL_CLOCK_I2S:
+    return system_clock_get(SYSTEM_CLOCK_AUPLL);
+#endif
+#if defined(BSP_USING_ADC0)
+  case PERIPHERAL_CLOCK_ADC:
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
+    div    = BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL);
+    if (tmpVal == GLB_ADC_CLK_AUDIO_PLL) {
+      return system_clock_get(SYSTEM_CLOCK_AUPLL) / (div + 1);
+    } else if (tmpVal == GLB_ADC_CLK_XCLK) {
+      return system_clock_get(SYSTEM_CLOCK_XCLK) / (div + 1);
+    }
+#endif
+#if defined(BSP_USING_DAC0)
+  case PERIPHERAL_CLOCK_DAC:
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    div    = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL);
+    if (tmpVal == GLB_DAC_CLK_AUDIO_PLL) {
+      return system_clock_get(SYSTEM_CLOCK_AUPLL) / div;
+    } else if (tmpVal == GLB_DAC_CLK_XCLK) {
+      return system_clock_get(SYSTEM_CLOCK_XCLK) / div;
+    }
+#endif
+#if defined(BSP_USING_TIMER0)
+  case PERIPHERAL_CLOCK_TIMER0:
+    tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, TIMER_CS_1);
+
+    div = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
+    div = BL_GET_REG_BITS_VAL(div, TIMER_TCDR2);
+    if (tmpVal == TIMER_CLKSRC_FCLK) {
+      return system_clock_get(SYSTEM_CLOCK_FCLK) / (div + 1);
+    } else if (tmpVal == TIMER_CLKSRC_32K) {
+      return system_clock_get(SYSTEM_CLOCK_32K_CLK) / (div + 1);
+    } else if (tmpVal == TIMER_CLKSRC_1K) {
+      return 1000 / (div + 1);
+    } else if (tmpVal == TIMER_CLKSRC_XTAL) {
+      return system_clock_get(SYSTEM_CLOCK_XCLK) / (div + 1);
+    }
+#endif
+#if defined(BSP_USING_TIMER1)
+  case PERIPHERAL_CLOCK_TIMER1:
+    tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, TIMER_CS_2);
+
+    div = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
+    div = BL_GET_REG_BITS_VAL(div, TIMER_TCDR3);
+    if (tmpVal == TIMER_CLKSRC_FCLK) {
+      return system_clock_get(SYSTEM_CLOCK_FCLK) / (div + 1);
+    } else if (tmpVal == TIMER_CLKSRC_32K) {
+      return system_clock_get(SYSTEM_CLOCK_32K_CLK) / (div + 1);
+    } else if (tmpVal == TIMER_CLKSRC_1K) {
+      return 1000 / (div + 1);
+    } else if (tmpVal == TIMER_CLKSRC_XTAL) {
+      return system_clock_get(SYSTEM_CLOCK_XCLK) / (div + 1);
+    }
+#endif
+#if defined(BSP_USING_WDT)
+  case PERIPHERAL_CLOCK_WDT:
+    tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, TIMER_CS_WDT);
+
+    div = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
+    div = BL_GET_REG_BITS_VAL(div, TIMER_WCDR);
+    if (tmpVal == TIMER_CLKSRC_FCLK) {
+      return system_clock_get(SYSTEM_CLOCK_FCLK) / (div + 1);
+    } else if (tmpVal == TIMER_CLKSRC_32K) {
+      return system_clock_get(SYSTEM_CLOCK_32K_CLK) / (div + 1);
+    } else if (tmpVal == TIMER_CLKSRC_1K) {
+      return 1000 / (div + 1);
+    } else if (tmpVal == TIMER_CLKSRC_XTAL) {
+      return system_clock_get(SYSTEM_CLOCK_XCLK) / (div + 1);
+    }
+#endif
+#if defined(BSP_USING_PWM_CH0) || defined(BSP_USING_PWM_CH1) || defined(BSP_USING_PWM_CH2) || defined(BSP_USING_PWM_CH3) || defined(BSP_USING_PWM_CH4)
+  case PERIPHERAL_CLOCK_PWM:
+    tmpVal = BL_RD_REG(PWM_BASE + PWM_CHANNEL_OFFSET, PWM_CONFIG);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL);
+    div    = BL_RD_REG(PWM_BASE + PWM_CHANNEL_OFFSET, PWM_CLKDIV);
+    if (tmpVal == PWM_CLK_XCLK) {
+      return system_clock_get(SYSTEM_CLOCK_XCLK) / div;
+    } else if (tmpVal == PWM_CLK_BCLK) {
+      return system_clock_get(SYSTEM_CLOCK_BCLK) / div;
+    } else if (tmpVal == PWM_CLK_32K) {
+      return system_clock_get(SYSTEM_CLOCK_32K_CLK) / div;
+    }
+#endif
+#if defined(BSP_USING_CAM)
+  case PERIPHERAL_CLOCK_CAM:
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_SRC_SEL);
+    div    = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV);
+
+    if (tmpVal == GLB_CAM_CLK_XCLK) {
+      return system_clock_get(SYSTEM_CLOCK_XCLK) / (div + 1);
+    } else if (tmpVal == GLB_CAM_CLK_DLL96M) {
+      return 96000000 / (div + 1);
+    }
+#endif
+  default:
+
+    break;
+  }
+
+  (void)(tmpVal);
+  (void)(div);
+  return 0;
+}
+
+void system_mtimer_clock_init(void) { GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div()); }
+
+void system_mtimer_clock_reinit(void) {
+  /* reinit clock to 10M */
+  GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, 7);
+}
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_common.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_common.c
new file mode 100644
index 00000000..34fc9f01
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_common.c
@@ -0,0 +1,104 @@
+/**
+ * @file hal_common.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "hal_common.h"
+#include "bl702_ef_ctrl.h"
+#include "bl702_romdriver.h"
+#include "bl702_sec_eng.h"
+#include "bl702_l1c.h"
+#include "hbn_reg.h"
+
+volatile uint32_t nesting = 0;
+
+void ATTR_TCM_SECTION cpu_global_irq_enable(void)
+{
+    nesting--;
+    if (nesting == 0) {
+        __enable_irq();
+    }
+}
+
+void ATTR_TCM_SECTION cpu_global_irq_disable(void)
+{
+    __disable_irq();
+    nesting++;
+}
+
+void hal_por_reset(void)
+{
+    RomDriver_GLB_SW_POR_Reset();
+}
+
+void hal_system_reset(void)
+{
+    RomDriver_GLB_SW_System_Reset();
+}
+
+void hal_cpu_reset(void)
+{
+    RomDriver_GLB_SW_CPU_Reset();
+}
+
+void hal_get_chip_id(uint8_t chip_id[8])
+{
+    EF_Ctrl_Read_MAC_Address(chip_id);
+}
+
+void hal_enter_usb_iap(void)
+{
+    BL_WR_WORD(HBN_BASE + HBN_RSV0_OFFSET, 0x00425355); //"\0BSU"
+
+    arch_delay_ms(1000);
+    RomDriver_GLB_SW_POR_Reset();
+}
+
+void ATTR_TCM_SECTION hal_jump2app(uint32_t flash_offset)
+{
+    /*flash_offset from 48K to 3.98M*/
+    if ((flash_offset >= 0xc000) && (flash_offset < (0x400000 - 20 * 1024))) {
+        void (*app_main)(void) = (void (*)(void))0x23000000;
+        BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET, flash_offset);
+        L1C_Cache_Flush_Ext();
+        app_main();
+    } else {
+        while(1)
+        {}
+    }
+}
+
+int hal_get_trng_seed(void)
+{
+    uint32_t seed[8];
+    uint32_t tmpVal;
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
+    tmpVal |= (1 << BL_AHB_SLAVE1_SEC);
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
+
+    Sec_Eng_Trng_Enable();
+    Sec_Eng_Trng_Read((uint8_t *)seed);
+    Sec_Eng_Trng_Disable();
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
+    tmpVal &= (~(1 << BL_AHB_SLAVE1_SEC));
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
+
+    return seed[0];
+}
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_dma.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_dma.c
new file mode 100644
index 00000000..0fbe57f8
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_dma.c
@@ -0,0 +1,431 @@
+/**
+ * @file hal_dma.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "hal_dma.h"
+#include "bl702_dma.h"
+
+#define DMA_CHANNEL_BASE(id_base, ch) ((id_base) + DMA_CHANNEL_OFFSET + (ch)*0x100)
+
+static const uint32_t dma_channel_base[][8] = {
+    {
+        DMA_CHANNEL_BASE(DMA_BASE, 0),
+        DMA_CHANNEL_BASE(DMA_BASE, 1),
+        DMA_CHANNEL_BASE(DMA_BASE, 2),
+        DMA_CHANNEL_BASE(DMA_BASE, 3),
+        DMA_CHANNEL_BASE(DMA_BASE, 4),
+        DMA_CHANNEL_BASE(DMA_BASE, 5),
+        DMA_CHANNEL_BASE(DMA_BASE, 6),
+        DMA_CHANNEL_BASE(DMA_BASE, 7),
+    }
+
+};
+
+static void DMA0_IRQ(void);
+
+static dma_device_t dmax_device[DMA_MAX_INDEX] = {
+#ifdef BSP_USING_DMA0_CH0
+    DMA0_CH0_CONFIG,
+#endif
+#ifdef BSP_USING_DMA0_CH1
+    DMA0_CH1_CONFIG,
+#endif
+#ifdef BSP_USING_DMA0_CH2
+    DMA0_CH2_CONFIG,
+#endif
+#ifdef BSP_USING_DMA0_CH3
+    DMA0_CH3_CONFIG,
+#endif
+#ifdef BSP_USING_DMA0_CH4
+    DMA0_CH4_CONFIG,
+#endif
+#ifdef BSP_USING_DMA0_CH5
+    DMA0_CH5_CONFIG,
+#endif
+#ifdef BSP_USING_DMA0_CH6
+    DMA0_CH6_CONFIG,
+#endif
+#ifdef BSP_USING_DMA0_CH7
+    DMA0_CH7_CONFIG,
+#endif
+};
+/**
+ * @brief
+ *
+ * @param dev
+ * @param oflag
+ * @return int
+ */
+int dma_open(struct device *dev, uint16_t oflag)
+{
+    dma_device_t *dma_device = (dma_device_t *)dev;
+    DMA_Channel_Cfg_Type chCfg = { 0 };
+
+    /* Disable all interrupt */
+    DMA_IntMask(dma_device->ch, DMA_INT_ALL, MASK);
+    /* Enable uart interrupt*/
+    CPU_Interrupt_Disable(DMA_ALL_IRQn);
+
+    DMA_Disable();
+
+    DMA_Channel_Disable(dma_device->ch);
+
+    chCfg.ch = dma_device->ch;
+    chCfg.dir = dma_device->direction;
+    chCfg.srcPeriph = dma_device->src_req;
+    chCfg.dstPeriph = dma_device->dst_req;
+    chCfg.srcAddrInc = dma_device->src_addr_inc;
+    chCfg.destAddrInc = dma_device->dst_addr_inc;
+    chCfg.srcBurstSzie = dma_device->src_burst_size;
+    chCfg.dstBurstSzie = dma_device->dst_burst_size;
+    chCfg.srcTransfWidth = dma_device->src_width;
+    chCfg.dstTransfWidth = dma_device->dst_width;
+    DMA_Channel_Init(&chCfg);
+
+    DMA_Enable();
+
+    Interrupt_Handler_Register(DMA_ALL_IRQn, DMA0_IRQ);
+    /* Enable uart interrupt*/
+    CPU_Interrupt_Enable(DMA_ALL_IRQn);
+    return 0;
+}
+/**
+ * @brief
+ *
+ * @param dev
+ * @param cmd
+ * @param args
+ * @return int
+ */
+int dma_control(struct device *dev, int cmd, void *args)
+{
+    dma_device_t *dma_device = (dma_device_t *)dev;
+
+    switch (cmd) {
+        case DEVICE_CTRL_SET_INT:
+            /* Dma interrupt configuration */
+            DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, UNMASK);
+            DMA_IntMask(dma_device->ch, DMA_INT_ERR, UNMASK);
+
+            break;
+
+        case DEVICE_CTRL_CLR_INT:
+            /* Dma interrupt configuration */
+            DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, MASK);
+            DMA_IntMask(dma_device->ch, DMA_INT_ERR, MASK);
+
+            break;
+
+        case DEVICE_CTRL_GET_INT:
+            break;
+
+        case DEVICE_CTRL_CONFIG:
+            break;
+
+        case DEVICE_CTRL_DMA_CHANNEL_UPDATE:
+            DMA_LLI_Update(dma_device->ch, (uint32_t)args);
+            break;
+
+        case DEVICE_CTRL_DMA_CHANNEL_GET_STATUS:
+            return DMA_Channel_Is_Busy(dma_device->ch);
+
+        case DEVICE_CTRL_DMA_CHANNEL_START:
+            DMA_Channel_Enable(dma_device->ch);
+            break;
+
+        case DEVICE_CTRL_DMA_CHANNEL_STOP:
+            DMA_Channel_Disable(dma_device->ch);
+            break;
+        case DEVICE_CTRL_DMA_CONFIG_SI: {
+            uint32_t tmpVal = BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SI, ((uint32_t)args) & 0x01);
+            BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL, tmpVal);
+
+        } break;
+        case DEVICE_CTRL_DMA_CONFIG_DI: {
+            uint32_t tmpVal = BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DI, ((uint32_t)args) & 0x01);
+            BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL, tmpVal);
+
+        } break;
+        default:
+            break;
+    }
+
+    return 0;
+}
+/**
+ * @brief
+ *
+ * @param dev
+ * @return int
+ */
+int dma_close(struct device *dev)
+{
+    dma_device_t *dma_device = (dma_device_t *)dev;
+    DMA_Channel_Cfg_Type chCfg = { 0 };
+
+    DMA_Channel_Disable(dma_device->ch);
+    DMA_Channel_Init(&chCfg);
+    return 0;
+}
+
+int dma_register(enum dma_index_type index, const char *name)
+{
+    struct device *dev;
+
+    if (DMA_MAX_INDEX == 0) {
+        return -DEVICE_EINVAL;
+    }
+
+    dev = &(dmax_device[index].parent);
+
+    dev->open = dma_open;
+    dev->close = dma_close;
+    dev->control = dma_control;
+    // dev->write = dma_write;
+    // dev->read = dma_read;
+
+    dev->type = DEVICE_CLASS_DMA;
+    dev->handle = NULL;
+
+    return device_register(dev, name);
+}
+
+static BL_Err_Type dma_scan_unregister_device(uint8_t *allocate_index)
+{
+    struct device *dev;
+    dlist_t *node;
+    uint8_t dma_index = 0;
+    uint32_t dma_handle[DMA_MAX_INDEX];
+
+    for (dma_index = 0; dma_index < DMA_MAX_INDEX; dma_index++) {
+        dma_handle[dma_index] = 0xff;
+    }
+
+    /* get registered dma handle list*/
+    dlist_for_each(node, device_get_list_header())
+    {
+        dev = dlist_entry(node, struct device, list);
+
+        if (dev->type == DEVICE_CLASS_DMA) {
+            dma_handle[(((uint32_t)dev - (uint32_t)dmax_device) / sizeof(dma_device_t)) % DMA_MAX_INDEX] = SET;
+        }
+    }
+
+    for (dma_index = 0; dma_index < DMA_MAX_INDEX; dma_index++) {
+        if (dma_handle[dma_index] == 0xff) {
+            *allocate_index = dma_index;
+            return SUCCESS;
+        }
+    }
+
+    return ERROR;
+}
+
+int dma_allocate_register(const char *name)
+{
+    struct device *dev;
+    uint8_t index;
+
+    if (DMA_MAX_INDEX == 0) {
+        return -DEVICE_EINVAL;
+    }
+
+    if (dma_scan_unregister_device(&index) == ERROR) {
+        return -DEVICE_ENOSPACE;
+    }
+
+    dev = &(dmax_device[index].parent);
+
+    dev->open = dma_open;
+    dev->close = dma_close;
+    dev->control = dma_control;
+    // dev->write = dma_write;
+    // dev->read = dma_read;
+
+    dev->status = DEVICE_UNREGISTER;
+    dev->type = DEVICE_CLASS_DMA;
+    dev->handle = NULL;
+
+    return device_register(dev, name);
+}
+
+/**
+ * @brief
+ *
+ * @param dev
+ * @param src_addr
+ * @param dst_addr
+ * @param transfer_size
+ * @return int
+ */
+int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size)
+{
+#if defined(BSP_USING_DMA0_CH0) || defined(BSP_USING_DMA0_CH1) || defined(BSP_USING_DMA0_CH2) || defined(BSP_USING_DMA0_CH3) || \
+    defined(BSP_USING_DMA0_CH4) || defined(BSP_USING_DMA0_CH5) || defined(BSP_USING_DMA0_CH6) || defined(BSP_USING_DMA0_CH7)
+
+    uint32_t malloc_count;
+    uint32_t remain_len;
+    uint32_t actual_transfer_len = 0;
+    uint32_t actual_transfer_offset = 0;
+    dma_control_data_t dma_ctrl_cfg;
+
+    dma_device_t *dma_device = (dma_device_t *)dev;
+
+    DMA_Channel_Disable(dma_device->ch);
+
+    if (transfer_size == 0) {
+        return 0;
+    }
+
+    switch (dma_device->src_width) {
+        case DMA_TRANSFER_WIDTH_8BIT:
+            actual_transfer_offset = 4095;
+            actual_transfer_len = transfer_size;
+            break;
+        case DMA_TRANSFER_WIDTH_16BIT:
+            if (transfer_size % 2) {
+                return -1;
+            }
+            actual_transfer_offset = 4095 << 1;
+            actual_transfer_len = transfer_size >> 1;
+            break;
+        case DMA_TRANSFER_WIDTH_32BIT:
+            if (transfer_size % 4) {
+                return -1;
+            }
+
+            actual_transfer_offset = 4095 << 2;
+            actual_transfer_len = transfer_size >> 2;
+            break;
+
+        default:
+            return -3;
+            break;
+    }
+
+    dma_ctrl_cfg = (dma_control_data_t)(BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL));
+
+    malloc_count = actual_transfer_len / 4095;
+    remain_len = actual_transfer_len % 4095;
+
+    if (remain_len) {
+        malloc_count++;
+    }
+
+    dma_device->lli_cfg = (dma_lli_ctrl_t *)realloc(dma_device->lli_cfg, sizeof(dma_lli_ctrl_t) * malloc_count);
+
+    if (dma_device->lli_cfg) {
+        /*transfer_size will be integer multiple of 4095*n or 4095*2*n or 4095*4*n,(n>0) */
+        for (uint32_t i = 0; i < malloc_count; i++) {
+            dma_device->lli_cfg[i].src_addr = src_addr;
+            dma_device->lli_cfg[i].dst_addr = dst_addr;
+            dma_device->lli_cfg[i].nextlli = 0;
+
+            dma_ctrl_cfg.bits.TransferSize = 4095;
+            dma_ctrl_cfg.bits.I = 0;
+
+            if (dma_ctrl_cfg.bits.SI) {
+                src_addr += actual_transfer_offset;
+            }
+
+            if (dma_ctrl_cfg.bits.DI) {
+                dst_addr += actual_transfer_offset;
+            }
+
+            if (i == malloc_count - 1) {
+                if (remain_len) {
+                    dma_ctrl_cfg.bits.TransferSize = remain_len;
+                }
+                dma_ctrl_cfg.bits.I = 1;
+
+                if (dma_device->transfer_mode == DMA_LLI_CYCLE_MODE) {
+                    dma_device->lli_cfg[i].nextlli = (uint32_t)&dma_device->lli_cfg[0];
+                }
+            }
+
+            if (i) {
+                dma_device->lli_cfg[i - 1].nextlli = (uint32_t)&dma_device->lli_cfg[i];
+            }
+
+            dma_device->lli_cfg[i].cfg = dma_ctrl_cfg;
+        }
+        BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_SRCADDR, dma_device->lli_cfg[0].src_addr);
+        BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_DSTADDR, dma_device->lli_cfg[0].dst_addr);
+        BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_LLI, dma_device->lli_cfg[0].nextlli);
+        BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL, dma_device->lli_cfg[0].cfg.WORD);
+    } else {
+        return -2;
+    }
+#endif
+    return 0;
+}
+
+/**
+ * @brief
+ *
+ * @param handle
+ */
+void dma_channel_isr(dma_device_t *handle)
+{
+    uint32_t tmpVal;
+    uint32_t intClr;
+
+    /* Get DMA register */
+    uint32_t DMAChs = DMA_BASE;
+
+    if (!handle->parent.callback) {
+        return;
+    }
+
+    tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS);
+    if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << handle->ch)) != 0) {
+        /* Clear interrupt */
+        tmpVal = BL_RD_REG(DMAChs, DMA_INTTCCLEAR);
+        intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR);
+        intClr |= (1 << handle->ch);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR, intClr);
+        BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpVal);
+        handle->parent.callback(&handle->parent, NULL, 0, DMA_INT_TCOMPLETED);
+    }
+
+    tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS);
+    if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << handle->ch)) != 0) {
+        /*Clear interrupt */
+        tmpVal = BL_RD_REG(DMAChs, DMA_INTERRCLR);
+        intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR);
+        intClr |= (1 << handle->ch);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR, intClr);
+        BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpVal);
+        handle->parent.callback(&handle->parent, NULL, 0, DMA_INT_ERR);
+    }
+}
+/**
+ * @brief
+ *
+ */
+void DMA0_IRQ(void)
+{
+    for (uint8_t i = 0; i < DMA_MAX_INDEX; i++) {
+        dma_channel_isr(&dmax_device[i]);
+    }
+}
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_flash.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_flash.c
new file mode 100644
index 00000000..dad0210c
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_flash.c
@@ -0,0 +1,346 @@
+/**
+ * @file hal_flash.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "bl702_glb.h"
+#include "bl702_xip_sflash.h"
+#include "bl702_xip_sflash_ext.h"
+#include "bl702_sf_cfg.h"
+#include "bl702_sf_cfg_ext.h"
+#include "hal_flash.h"
+
+static uint32_t g_jedec_id = 0;
+static SPI_Flash_Cfg_Type g_flash_cfg;
+
+/**
+ * @brief flash_get_jedecid
+ *
+ * @return BL_Err_Type
+ */
+uint32_t flash_get_jedecid(void)
+{
+    uint32_t jid = 0;
+
+    jid = ((g_jedec_id&0xff)<<16) + (g_jedec_id&0xff00) + ((g_jedec_id&0xff0000)>>16);
+    return jid;
+}
+
+/**
+ * @brief flash_get_cfg
+ *
+ * @return BL_Err_Type
+ */
+BL_Err_Type flash_get_cfg(uint8_t **cfg_addr, uint32_t *len)
+{
+    *cfg_addr = (uint8_t *)&g_flash_cfg;
+    *len = sizeof(SPI_Flash_Cfg_Type);
+
+    return SUCCESS;
+}
+
+/**
+ * @brief flash_set_qspi_enable
+ *
+ * @return BL_Err_Type
+ */
+static BL_Err_Type ATTR_TCM_SECTION flash_set_qspi_enable(SPI_Flash_Cfg_Type *p_flash_cfg)
+{
+    if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) {
+        SFlash_Qspi_Enable(p_flash_cfg);
+    }
+
+    return SUCCESS;
+}
+
+/**
+ * @brief flash_set_l1c_wrap
+ *
+ * @return BL_Err_Type
+ */
+static BL_Err_Type ATTR_TCM_SECTION flash_set_l1c_wrap(SPI_Flash_Cfg_Type *p_flash_cfg)
+{
+    if (((p_flash_cfg->ioMode >> 4) & 0x01) == 1) {
+        L1C_Set_Wrap(DISABLE);
+    } else {
+        L1C_Set_Wrap(ENABLE);
+        if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) {
+            SFlash_SetBurstWrap(p_flash_cfg);
+        }
+    }
+
+    return SUCCESS;
+}
+
+/**
+ * @brief flash_config_init
+ *
+ * @return BL_Err_Type
+ */
+static BL_Err_Type ATTR_TCM_SECTION flash_config_init(SPI_Flash_Cfg_Type *p_flash_cfg, uint8_t *jedec_id)
+{
+    BL_Err_Type ret = ERROR;
+    uint32_t jid = 0;
+    uint32_t offset = 0;
+
+    cpu_global_irq_disable();
+    XIP_SFlash_Opt_Enter();
+    XIP_SFlash_State_Save(p_flash_cfg, &offset);
+    SFlash_GetJedecId(p_flash_cfg, (uint8_t *)&jid);
+    arch_memcpy(jedec_id, (uint8_t *)&jid, 3);
+    jid &= 0xFFFFFF;
+    g_jedec_id = jid;
+    ret = SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(jid, p_flash_cfg);
+    if (ret == SUCCESS) {
+        p_flash_cfg->mid = (jid & 0xff);
+    }
+
+    /* Set flash controler from p_flash_cfg */
+    flash_set_qspi_enable(p_flash_cfg);
+    flash_set_l1c_wrap(p_flash_cfg);
+    XIP_SFlash_State_Restore(p_flash_cfg, p_flash_cfg->ioMode & 0x0f, offset);
+    XIP_SFlash_Opt_Exit();
+    cpu_global_irq_enable();
+
+    return ret;
+}
+
+/**
+ * @brief multi flash adapter
+ *
+ * @return BL_Err_Type
+ */
+BL_Err_Type ATTR_TCM_SECTION flash_init(void)
+{
+    BL_Err_Type ret = ERROR;
+    uint8_t clkDelay = 1;
+    uint8_t clkInvert = 1;
+    uint32_t jedec_id = 0;
+
+    cpu_global_irq_disable();
+    L1C_Cache_Flush_Ext();
+    SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(0, &g_flash_cfg);
+    L1C_Cache_Flush_Ext();
+    cpu_global_irq_enable();
+    if (g_flash_cfg.mid != 0xff) {
+        return SUCCESS;
+    }
+    clkDelay = g_flash_cfg.clkDelay;
+    clkInvert = g_flash_cfg.clkInvert;
+    g_flash_cfg.ioMode = g_flash_cfg.ioMode & 0x0f;
+
+    ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id);
+#if 0
+    MSG("flash ID = %08x\r\n", jedec_id);
+    bflb_platform_dump((uint8_t *)&g_flash_cfg, sizeof(g_flash_cfg));
+    if (ret != SUCCESS) {
+        MSG("flash config init fail!\r\n");
+    }
+#endif
+    g_flash_cfg.clkDelay = clkDelay;
+    g_flash_cfg.clkInvert = clkInvert;
+
+    return ret;
+}
+
+/**
+ * @brief read jedec id
+ *
+ * @param data
+ * @return BL_Err_Type
+ */
+BL_Err_Type ATTR_TCM_SECTION flash_read_jedec_id(uint8_t *data)
+{
+    uint32_t jid = 0;
+
+    cpu_global_irq_disable();
+    XIP_SFlash_Opt_Enter();
+    XIP_SFlash_GetJedecId_Need_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, (uint8_t *)&jid);
+    XIP_SFlash_Opt_Exit();
+    cpu_global_irq_enable();
+    jid &= 0xFFFFFF;
+    arch_memcpy(data, (void *)&jid, 4);
+
+    return SUCCESS;
+}
+
+/**
+ * @brief read flash data via xip
+ *
+ * @param addr
+ * @param data
+ * @param len
+ * @return BL_Err_Type
+ */
+BL_Err_Type ATTR_TCM_SECTION flash_read_via_xip(uint32_t addr, uint8_t *data, uint32_t len)
+{
+    cpu_global_irq_disable();
+    L1C_Cache_Flush_Ext();
+    XIP_SFlash_Read_Via_Cache_Need_Lock(addr, data, len);
+    L1C_Cache_Flush_Ext();
+    cpu_global_irq_enable();
+
+    return SUCCESS;
+}
+
+/**
+ * @brief flash read data
+ *
+ * @param addr
+ * @param data
+ * @param len
+ * @return BL_Err_Type
+ */
+BL_Err_Type ATTR_TCM_SECTION flash_read(uint32_t addr, uint8_t *data, uint32_t len)
+{
+    BL_Err_Type ret = ERROR;
+
+    cpu_global_irq_disable();
+    XIP_SFlash_Opt_Enter();
+    ret = XIP_SFlash_Read_Need_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, addr, data, len);
+    XIP_SFlash_Opt_Exit();
+    cpu_global_irq_enable();
+
+    return ret;
+}
+
+/**
+ * @brief flash write data
+ *
+ * @param addr
+ * @param data
+ * @param len
+ * @return BL_Err_Type
+ */
+BL_Err_Type ATTR_TCM_SECTION flash_write(uint32_t addr, uint8_t *data, uint32_t len)
+{
+    BL_Err_Type ret = ERROR;
+
+    cpu_global_irq_disable();
+    XIP_SFlash_Opt_Enter();
+    ret = XIP_SFlash_Write_Need_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, addr, data, len);
+    XIP_SFlash_Opt_Exit();
+    cpu_global_irq_enable();
+
+    return ret;
+}
+
+/**
+ * @brief flash erase
+ *
+ * @param startaddr
+ * @param endaddr
+ * @return BL_Err_Type
+ */
+BL_Err_Type ATTR_TCM_SECTION flash_erase(uint32_t startaddr, uint32_t len)
+{
+    BL_Err_Type ret = ERROR;
+
+    cpu_global_irq_disable();
+    XIP_SFlash_Opt_Enter();
+    ret = XIP_SFlash_Erase_Need_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, startaddr, startaddr + len - 1);
+    XIP_SFlash_Opt_Exit();
+    cpu_global_irq_enable();
+
+    return ret;
+}
+
+/**
+ * @brief flash write protect set
+ *
+ * @param protect
+ * @return BL_Err_Type
+ */
+BL_Err_Type ATTR_TCM_SECTION flash_write_protect_set(SFlash_Protect_Kh25v40_Type protect)
+{
+    BL_Err_Type ret = ERROR;
+
+    cpu_global_irq_disable();
+    XIP_SFlash_Opt_Enter();
+    ret = XIP_SFlash_KH25V40_Write_Protect_Need_Lock(&g_flash_cfg, protect);
+    XIP_SFlash_Opt_Exit();
+    cpu_global_irq_enable();
+
+    return ret;
+}
+
+/**
+ * @brief flash clear status register
+ *
+ * @param None
+ * @return BL_Err_Type
+ */
+BL_Err_Type ATTR_TCM_SECTION flash_clear_status_register(void)
+{
+    BL_Err_Type ret = ERROR;
+
+    cpu_global_irq_disable();
+    XIP_SFlash_Opt_Enter();
+    ret = XIP_SFlash_Clear_Status_Register_Need_Lock(&g_flash_cfg);
+    XIP_SFlash_Opt_Exit();
+    cpu_global_irq_enable();
+
+    return ret;
+}
+
+/**
+ * @brief set flash cache
+ *
+ * @param cont_read
+ * @param cache_enable
+ * @param cache_way_disable
+ * @param flash_offset
+ * @return BL_Err_Type
+ */
+BL_Err_Type ATTR_TCM_SECTION flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset)
+{
+    uint32_t tmp[1];
+    BL_Err_Type stat;
+
+    SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
+
+    XIP_SFlash_Opt_Enter();
+    /* To make it simple, exit cont read anyway */
+    SFlash_Reset_Continue_Read(&g_flash_cfg);
+
+    if (g_flash_cfg.cReadSupport == 0) {
+        cont_read = 0;
+    }
+
+    if (cont_read == 1) {
+        stat = SFlash_Read(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp));
+
+        if (SUCCESS != stat) {
+            XIP_SFlash_Opt_Exit();
+            return ERROR;
+        }
+    }
+
+    /* Set default value */
+    L1C_Cache_Enable_Set(0xf);
+
+    if (cache_enable) {
+        SF_Ctrl_Set_Flash_Image_Offset(flash_offset);
+        SFlash_Cache_Read_Enable(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, cont_read, cache_way_disable);
+    }
+    XIP_SFlash_Opt_Exit();
+
+    return SUCCESS;
+}
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_gpio.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_gpio.c
new file mode 100644
index 00000000..20778c90
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_gpio.c
@@ -0,0 +1,224 @@
+/**
+ * @file hal_gpio.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "hal_gpio.h"
+#include "bl702_glb.h"
+#include "bl702_gpio.h"
+
+static void GPIO_IRQ(void);
+
+struct gpio_int_cfg_private {
+  slist_t  list;
+  uint32_t pin;
+  void (*cbfun)(uint32_t pin);
+};
+
+static slist_t gpio_int_head = SLIST_OBJECT_INIT(gpio_int_head);
+
+/**
+ * @brief
+ *
+ * @param pin
+ * @param mode
+ */
+void gpio_set_mode(uint32_t pin, uint32_t mode) {
+  GLB_GPIO_Cfg_Type gpio_cfg;
+
+  gpio_cfg.gpioFun = GPIO_FUN_GPIO;
+  gpio_cfg.gpioPin = pin;
+  gpio_cfg.drive   = 3;
+  gpio_cfg.smtCtrl = 1;
+
+  switch (mode) {
+  case GPIO_OUTPUT_MODE:
+    gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
+    gpio_cfg.pullType = GPIO_PULL_NONE;
+    break;
+
+  case GPIO_OUTPUT_PP_MODE:
+    gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
+    gpio_cfg.pullType = GPIO_PULL_UP;
+    break;
+
+  case GPIO_OUTPUT_PD_MODE:
+    gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
+    gpio_cfg.pullType = GPIO_PULL_DOWN;
+    break;
+
+  case GPIO_INPUT_MODE:
+    gpio_cfg.gpioMode = GPIO_MODE_INPUT;
+    gpio_cfg.pullType = GPIO_PULL_NONE;
+    break;
+
+  case GPIO_INPUT_PU_MODE:
+    gpio_cfg.gpioMode = GPIO_MODE_INPUT;
+    gpio_cfg.pullType = GPIO_PULL_UP;
+    break;
+
+  case GPIO_INPUT_PD_MODE:
+    gpio_cfg.gpioMode = GPIO_MODE_INPUT;
+    gpio_cfg.pullType = GPIO_PULL_DOWN;
+    break;
+  case GPIO_HZ_MODE:
+    GLB_GPIO_Set_HZ(pin);
+  default:
+    CPU_Interrupt_Disable(GPIO_INT0_IRQn);
+    GLB_GPIO_IntMask(pin, MASK);
+
+    gpio_cfg.gpioMode = GPIO_MODE_INPUT;
+
+    if (mode == GPIO_ASYNC_RISING_TRIGER_INT_MODE) {
+      gpio_cfg.pullType = GPIO_PULL_DOWN;
+      GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_POS_PULSE);
+    }
+
+    else if (mode == GPIO_ASYNC_FALLING_TRIGER_INT_MODE) {
+      gpio_cfg.pullType = GPIO_PULL_UP;
+      GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_NEG_PULSE);
+    }
+
+    else if (mode == GPIO_ASYNC_HIGH_LEVEL_INT_MODE) {
+      gpio_cfg.pullType = GPIO_PULL_DOWN;
+      GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_POS_LEVEL);
+    }
+
+    else if (mode == GPIO_ASYNC_LOW_LEVEL_INT_MODE) {
+      gpio_cfg.pullType = GPIO_PULL_UP;
+      GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_NEG_LEVEL);
+    }
+
+    else if (mode == GPIO_SYNC_RISING_TRIGER_INT_MODE) {
+      gpio_cfg.pullType = GPIO_PULL_DOWN;
+      GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_POS_PULSE);
+    }
+
+    else if (mode == GPIO_SYNC_FALLING_TRIGER_INT_MODE) {
+      gpio_cfg.pullType = GPIO_PULL_UP;
+      GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_NEG_PULSE);
+    }
+
+    else if (mode == GPIO_SYNC_HIGH_LEVEL_INT_MODE) {
+      gpio_cfg.pullType = GPIO_PULL_DOWN;
+      GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_POS_LEVEL);
+    }
+
+    else if (mode == GPIO_SYNC_LOW_LEVEL_INT_MODE) {
+      gpio_cfg.pullType = GPIO_PULL_UP;
+      GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_NEG_LEVEL);
+    }
+
+    else {
+      return;
+    }
+
+    break;
+  }
+
+  GLB_GPIO_Init(&gpio_cfg);
+}
+/**
+ * @brief
+ *
+ * @param pin
+ * @param value
+ */
+void gpio_write(uint32_t pin, uint32_t value) {
+  uint32_t tmp = BL_RD_REG(GLB_BASE, GLB_GPIO_OUTPUT);
+
+  if (value)
+    tmp |= (1 << pin);
+  else
+    tmp &= ~(1 << pin);
+
+  BL_WR_REG(GLB_BASE, GLB_GPIO_OUTPUT, tmp);
+}
+/**
+ * @brief
+ *
+ * @param pin
+ */
+void gpio_toggle(uint32_t pin) {
+  uint32_t tmp = BL_RD_REG(GLB_BASE, GLB_GPIO_OUTPUT);
+  tmp ^= (1 << pin);
+  BL_WR_REG(GLB_BASE, GLB_GPIO_OUTPUT, tmp);
+}
+/**
+ * @brief
+ *
+ * @param pin
+ * @return int
+ */
+int gpio_read(uint32_t pin) { return ((BL_RD_REG(GLB_BASE, GLB_GPIO_INPUT) & (1 << pin)) ? 1 : 0); }
+/**
+ * @brief
+ *
+ * @param pin
+ * @param cbFun
+ */
+void gpio_attach_irq(uint32_t pin, void (*cbfun)(uint32_t pin)) {
+  struct gpio_int_cfg_private *int_cfg = malloc(sizeof(struct gpio_int_cfg_private));
+  int_cfg->cbfun                       = cbfun;
+  int_cfg->pin                         = pin;
+  slist_add_tail(&gpio_int_head, &int_cfg->list);
+  CPU_Interrupt_Disable(GPIO_INT0_IRQn);
+  Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO_IRQ);
+  CPU_Interrupt_Enable(GPIO_INT0_IRQn);
+}
+/**
+ * @brief
+ *
+ * @param pin
+ * @param enabled
+ */
+void gpio_irq_enable(uint32_t pin, uint8_t enabled) {
+  if (enabled) {
+    GLB_GPIO_IntMask(pin, UNMASK);
+  } else {
+    GLB_GPIO_IntMask(pin, MASK);
+  }
+}
+
+static void GPIO_IRQ(void) {
+  slist_t *i;
+  uint32_t timeOut = 0;
+#define GLB_GPIO_INT0_CLEAR_TIMEOUT (32)
+  slist_for_each(i, &gpio_int_head) {
+    struct gpio_int_cfg_private *int_cfg = slist_entry(i, struct gpio_int_cfg_private, list);
+
+    if (SET == GLB_Get_GPIO_IntStatus(int_cfg->pin)) {
+      int_cfg->cbfun(int_cfg->pin);
+      GLB_GPIO_IntClear(int_cfg->pin, SET);
+      /* timeout check */
+      timeOut = GLB_GPIO_INT0_CLEAR_TIMEOUT;
+
+      do {
+        timeOut--;
+      } while ((SET == GLB_Get_GPIO_IntStatus(int_cfg->pin)) && timeOut);
+
+      if (!timeOut) {
+        // MSG("WARNING: Clear GPIO interrupt status fail.\r\n");
+      }
+
+      GLB_GPIO_IntClear(int_cfg->pin, RESET);
+    }
+  }
+}
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_i2c.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_i2c.c
new file mode 100644
index 00000000..cbc88824
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_i2c.c
@@ -0,0 +1,172 @@
+/**
+ * @file hal_i2c.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "hal_i2c.h"
+#include "bl702_i2c.h"
+#include "bl702_glb.h"
+
+static i2c_device_t i2cx_device[I2C_MAX_INDEX] = {
+#ifdef BSP_USING_I2C0
+    I2C0_CONFIG,
+#endif
+#ifdef BSP_USING_I2C1
+    I2C1_CONFIG,
+#endif
+};
+/**
+ * @brief
+ *
+ * @param dev
+ * @param oflag
+ * @return int
+ */
+int i2c_open(struct device *dev, uint16_t oflag)
+{
+    i2c_device_t *i2c_device = (i2c_device_t *)dev;
+
+    if (i2c_device->mode == I2C_HW_MODE) {
+        I2C_SetPrd(i2c_device->id, i2c_device->phase);
+    }
+
+    return 0;
+}
+
+// int i2c_close(struct device *dev)
+// {
+
+//     return 0;
+// }
+
+// int i2c_control(struct device *dev, int cmd, void *args)
+// {
+//     //i2c_device_t *i2c_device = (i2c_device_t *)dev;
+
+//     switch (cmd)
+//     {
+//     case DEVICE_CTRL_SET_INT /* constant-expression */:
+
+//         break;
+//     case DEVICE_CTRL_CLR_INT /* constant-expression */:
+//         /* code */
+//         /* Enable UART interrupt*/
+
+//         break;
+//     case DEVICE_CTRL_GET_INT /* constant-expression */:
+//         /* code */
+//         break;
+//     case DEVICE_CTRL_CONFIG /* constant-expression */:
+//         /* code */
+//         break;
+//     case 4 /* constant-expression */:
+//         /* code */
+//         break;
+//     case 5 /* constant-expression */:
+//         /* code */
+//         break;
+//     default:
+//         break;
+//     }
+
+//     return 0;
+// }
+// int i2c_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
+// {
+
+//     return 0;
+// }
+// int i2c_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
+// {
+
+//     return 0;
+// }
+/**
+ * @brief
+ *
+ * @param index
+ * @param name
+ * @param flag
+ * @return int
+ */
+int i2c_register(enum i2c_index_type index, const char *name)
+{
+    struct device *dev;
+
+    if (I2C_MAX_INDEX == 0) {
+        return -DEVICE_EINVAL;
+    }
+
+    dev = &(i2cx_device[index].parent);
+
+    dev->open = i2c_open;
+    dev->close = NULL;
+    dev->control = NULL;
+    dev->write = NULL;
+    dev->read = NULL;
+
+    dev->type = DEVICE_CLASS_I2C;
+    dev->handle = NULL;
+
+    return device_register(dev, name);
+}
+/**
+ * @brief
+ *
+ * @param dev
+ * @param msgs
+ * @param num
+ * @return uint32_t
+ */
+int i2c_transfer(struct device *dev, i2c_msg_t msgs[], uint32_t num)
+{
+    i2c_msg_t *msg;
+    I2C_Transfer_Cfg i2cCfg = { 0 };
+
+    i2c_device_t *i2c_device = (i2c_device_t *)dev;
+
+    if (i2c_device->mode == I2C_HW_MODE) {
+        for (uint32_t i = 0; i < num; i++) {
+            msg = &msgs[i];
+            i2cCfg.slaveAddr = msg->slaveaddr;
+            i2cCfg.stopEveryByte = DISABLE;
+            i2cCfg.subAddr = msg->subaddr;
+            i2cCfg.dataSize = msg->len;
+            i2cCfg.data = msg->buf;
+
+            if (msg->flags & SUB_ADDR_0BYTE) {
+                i2cCfg.subAddrSize = 0;
+            } else if (msg->flags & SUB_ADDR_1BYTE) {
+                i2cCfg.subAddrSize = 1;
+            } else if (msg->flags & SUB_ADDR_2BYTE) {
+                i2cCfg.subAddrSize = 2;
+            }
+
+            if ((msg->flags & I2C_RW_MASK) == I2C_WR) {
+                return I2C_MasterSendBlocking(i2c_device->id, &i2cCfg);
+            } else if ((msg->flags & I2C_RW_MASK) == I2C_RD) {
+                return I2C_MasterReceiveBlocking(i2c_device->id, &i2cCfg);
+            }
+        }
+    } else {
+    }
+
+    return 0;
+}
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_mtimer.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_mtimer.c
new file mode 100644
index 00000000..2305305e
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_mtimer.c
@@ -0,0 +1,143 @@
+/**
+ * @file hal_mtimer.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "hal_mtimer.h"
+#include "bl702_glb.h"
+#include "risc-v/Core/Include/clic.h"
+
+static void (*systick_callback)(void);
+static uint64_t next_compare_tick = 0;
+static uint64_t current_set_ticks = 0;
+
+static void Systick_Handler(void)
+{
+    *(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIMECMP) = next_compare_tick;
+    systick_callback();
+    next_compare_tick += current_set_ticks;
+}
+
+/**
+ * @brief
+ *
+ * @param time
+ * @param interruptFun
+ */
+void mtimer_set_alarm_time(uint64_t ticks, void (*interruptfun)(void))
+{
+    CPU_Interrupt_Disable(MTIME_IRQn);
+
+    uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
+    volatile uint32_t *const pulTimeHigh = (volatile uint32_t *const)(CLIC_CTRL_ADDR + CLIC_MTIME + 4);
+    volatile uint32_t *const pulTimeLow = (volatile uint32_t *const)(CLIC_CTRL_ADDR + CLIC_MTIME);
+    volatile uint32_t ulHartId = 0;
+
+    current_set_ticks = ticks;
+    systick_callback = interruptfun;
+
+    __asm volatile("csrr %0, mhartid"
+                   : "=r"(ulHartId));
+
+    do {
+        ulCurrentTimeHigh = *pulTimeHigh;
+        ulCurrentTimeLow = *pulTimeLow;
+    } while (ulCurrentTimeHigh != *pulTimeHigh);
+
+    next_compare_tick = (uint64_t)ulCurrentTimeHigh;
+    next_compare_tick <<= 32ULL;
+    next_compare_tick |= (uint64_t)ulCurrentTimeLow;
+    next_compare_tick += (uint64_t)current_set_ticks;
+
+    *(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIMECMP) = next_compare_tick;
+
+    /* Prepare the time to use after the next tick interrupt. */
+    next_compare_tick += (uint64_t)current_set_ticks;
+
+    Interrupt_Handler_Register(MTIME_IRQn, Systick_Handler);
+    CPU_Interrupt_Enable(MTIME_IRQn);
+}
+
+/**
+ * @brief
+ *
+ * @return uint64_t
+ */
+uint64_t mtimer_get_time_ms()
+{
+    return mtimer_get_time_us() / 1000;
+}
+/**
+ * @brief
+ *
+ * @return uint64_t
+ */
+uint64_t mtimer_get_time_us()
+{
+    uint32_t tmpValLow, tmpValHigh, tmpValHigh1;
+
+    do {
+        tmpValLow = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME);
+        tmpValHigh = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME + 4);
+        tmpValHigh1 = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME + 4);
+    } while (tmpValHigh != tmpValHigh1);
+
+    return (((uint64_t)tmpValHigh << 32) + tmpValLow);
+}
+/**
+ * @brief
+ *
+ * @param time
+ */
+void mtimer_delay_ms(uint32_t time)
+{
+    uint64_t cnt = 0;
+    uint32_t clock = SystemCoreClockGet();
+    uint64_t startTime = mtimer_get_time_ms();
+
+    while (mtimer_get_time_ms() - startTime < time) {
+        cnt++;
+
+        /* assume BFLB_BSP_Get_Time_Ms take 32 cycles*/
+        if (cnt > (time * (clock >> (10 + 5))) * 2) {
+            break;
+        }
+    }
+}
+/**
+ * @brief
+ *
+ * @param time
+ */
+void mtimer_delay_us(uint32_t time)
+{
+    uint64_t cnt = 0;
+    uint32_t clock = SystemCoreClockGet();
+    uint64_t startTime = mtimer_get_time_us();
+
+    while (mtimer_get_time_us() - startTime < time) {
+        cnt++;
+
+        /* assume BFLB_BSP_Get_Time_Ms take 32 cycles*/
+        if (cnt > (time * (clock >> (10 + 5))) * 2) {
+            break;
+        }
+    }
+}
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_pm.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_pm.c
new file mode 100644
index 00000000..e7efc2ef
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_pm.c
@@ -0,0 +1,1351 @@
+/**
+ * @file hal_pm.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "hal_pm.h"
+#include "bl702_glb.h"
+#include "bl702_sflash.h"
+#include "hal_clock.h"
+#include "hal_flash.h"
+#include "hal_rtc.h"
+#include "risc-v/Core/Include/clic.h"
+
+/* Cache Way Disable, will get from l1c register */
+uint8_t cacheWayDisable = 0;
+
+/* PSRAM IO Configuration, will get from glb register */
+uint32_t psramIoCfg = 0;
+
+/* Flash offset value, will get from sf_ctrl register */
+uint32_t flash_offset = 0;
+
+SPI_Flash_Cfg_Type *flash_cfg;
+
+#define PM_PDS_FLASH_POWER_OFF   1
+#define PM_PDS_DLL_POWER_OFF     1
+#define PM_PDS_PLL_POWER_OFF     1
+#define PM_PDS_RF_POWER_OFF      1
+#define PM_PDS_LDO_LEVEL_DEFAULT HBN_LDO_LEVEL_1P10V
+#define PM_HBN_LDO_LEVEL_DEFAULT HBN_LDO_LEVEL_0P90V
+
+void HBN_OUT0_IRQ(void);
+void HBN_OUT1_IRQ(void);
+
+/** @defgroup  Hal_Power_Global_Variables
+ *
+ *  @brief PDS level config
+ *  @{
+ */
+static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel0 = {
+    .pdsCtl = {
+        .pdsStart = 1,
+        .sleepForever = 0,
+        .xtalForceOff = 0,
+        .saveWifiState = 0,
+        .dcdc18Off = 1,
+        .bgSysOff = 1,
+        .gpioIePuPd = 1,
+        .puFlash = 0,
+        .clkOff = 1,
+        .memStby = 1,
+        .swPuFlash = 1,
+        .isolation = 1,
+        .waitXtalRdy = 0,
+        .pdsPwrOff = 1,
+        .xtalOff = 0,
+        .socEnbForceOn = 1,
+        .pdsRstSocEn = 0,
+        .pdsRC32mOn = 0,
+        .pdsLdoVselEn = 0,
+        .pdsRamLowPowerWithClkEn = 1,
+        .cpu0WfiMask = 0,
+        .ldo11Off = 1,
+        .pdsForceRamClkEn = 0,
+        .pdsLdoVol = 0xA,
+        .pdsCtlRfSel = 3,
+        .pdsCtlPllSel = 0,
+    },
+    .pdsCtl2 = {
+        .forceCpuPwrOff = 0,
+        .forceBzPwrOff = 0,
+        .forceUsbPwrOff = 0,
+        .forceCpuIsoEn = 0,
+        .forceBzIsoEn = 0,
+        .forceUsbIsoEn = 0,
+        .forceCpuPdsRst = 0,
+        .forceBzPdsRst = 0,
+        .forceUsbPdsRst = 0,
+        .forceCpuMemStby = 0,
+        .forceBzMemStby = 0,
+        .forceUsbMemStby = 0,
+        .forceCpuGateClk = 0,
+        .forceBzGateClk = 0,
+        .forceUsbGateClk = 0,
+    },
+    .pdsCtl3 = {
+        .forceMiscPwrOff = 0,
+        .forceBlePwrOff = 0,
+        .forceBleIsoEn = 0,
+        .forceMiscPdsRst = 0,
+        .forceBlePdsRst = 0,
+        .forceMiscMemStby = 0,
+        .forceBleMemStby = 0,
+        .forceMiscGateClk = 0,
+        .forceBleGateClk = 0,
+        .CpuIsoEn = 0,
+        .BzIsoEn = 0,
+        .BleIsoEn = 1,
+        .UsbIsoEn = 0,
+        .MiscIsoEn = 0,
+    },
+    .pdsCtl4 = {
+        .cpuPwrOff = 0,
+        .cpuRst = 0,
+        .cpuMemStby = 1,
+        .cpuGateClk = 1,
+        .BzPwrOff = 0,
+        .BzRst = 0,
+        .BzMemStby = 1,
+        .BzGateClk = 1,
+        .BlePwrOff = 1,
+        .BleRst = 1,
+        .BleMemStby = 1,
+        .BleGateClk = 1,
+        .UsbPwrOff = 0,
+        .UsbRst = 0,
+        .UsbMemStby = 1,
+        .UsbGateClk = 1,
+        .MiscPwrOff = 0,
+        .MiscRst = 0,
+        .MiscMemStby = 1,
+        .MiscGateClk = 1,
+        .MiscAnaPwrOff = 1,
+        .MiscDigPwrOff = 1,
+    }
+};
+static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel1 = {
+    .pdsCtl = {
+        .pdsStart = 1,
+        .sleepForever = 0,
+        .xtalForceOff = 0,
+        .saveWifiState = 0,
+        .dcdc18Off = 1,
+        .bgSysOff = 1,
+        .gpioIePuPd = 1,
+        .puFlash = 0,
+        .clkOff = 1,
+        .memStby = 1,
+        .swPuFlash = 1,
+        .isolation = 1,
+        .waitXtalRdy = 0,
+        .pdsPwrOff = 1,
+        .xtalOff = 0,
+        .socEnbForceOn = 1,
+        .pdsRstSocEn = 0,
+        .pdsRC32mOn = 0,
+        .pdsLdoVselEn = 0,
+        .pdsRamLowPowerWithClkEn = 1,
+        .cpu0WfiMask = 0,
+        .ldo11Off = 1,
+        .pdsForceRamClkEn = 0,
+        .pdsLdoVol = 0xA,
+        .pdsCtlRfSel = 3,
+        .pdsCtlPllSel = 0,
+    },
+    .pdsCtl2 = {
+        .forceCpuPwrOff = 0,
+        .forceBzPwrOff = 0,
+        .forceUsbPwrOff = 0,
+        .forceCpuIsoEn = 0,
+        .forceBzIsoEn = 0,
+        .forceUsbIsoEn = 0,
+        .forceCpuPdsRst = 0,
+        .forceBzPdsRst = 0,
+        .forceUsbPdsRst = 0,
+        .forceCpuMemStby = 0,
+        .forceBzMemStby = 0,
+        .forceUsbMemStby = 0,
+        .forceCpuGateClk = 0,
+        .forceBzGateClk = 0,
+        .forceUsbGateClk = 0,
+    },
+    .pdsCtl3 = {
+        .forceMiscPwrOff = 0,
+        .forceBlePwrOff = 0,
+        .forceBleIsoEn = 0,
+        .forceMiscPdsRst = 0,
+        .forceBlePdsRst = 0,
+        .forceMiscMemStby = 0,
+        .forceBleMemStby = 0,
+        .forceMiscGateClk = 0,
+        .forceBleGateClk = 0,
+        .CpuIsoEn = 0,
+        .BzIsoEn = 0,
+        .BleIsoEn = 1,
+        .UsbIsoEn = 1,
+        .MiscIsoEn = 0,
+    },
+    .pdsCtl4 = {
+        .cpuPwrOff = 0,
+        .cpuRst = 0,
+        .cpuMemStby = 1,
+        .cpuGateClk = 1,
+        .BzPwrOff = 0,
+        .BzRst = 0,
+        .BzMemStby = 1,
+        .BzGateClk = 1,
+        .BlePwrOff = 1,
+        .BleRst = 1,
+        .BleMemStby = 1,
+        .BleGateClk = 1,
+        .UsbPwrOff = 1,
+        .UsbRst = 1,
+        .UsbMemStby = 1,
+        .UsbGateClk = 1,
+        .MiscPwrOff = 0,
+        .MiscRst = 0,
+        .MiscMemStby = 1,
+        .MiscGateClk = 1,
+        .MiscAnaPwrOff = 1,
+        .MiscDigPwrOff = 1,
+    }
+};
+static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel2 = {
+    .pdsCtl = {
+        .pdsStart = 1,
+        .sleepForever = 0,
+        .xtalForceOff = 0,
+        .saveWifiState = 0,
+        .dcdc18Off = 1,
+        .bgSysOff = 1,
+        .gpioIePuPd = 1,
+        .puFlash = 0,
+        .clkOff = 1,
+        .memStby = 1,
+        .swPuFlash = 1,
+        .isolation = 1,
+        .waitXtalRdy = 0,
+        .pdsPwrOff = 1,
+        .xtalOff = 0,
+        .socEnbForceOn = 1,
+        .pdsRstSocEn = 0,
+        .pdsRC32mOn = 0,
+        .pdsLdoVselEn = 0,
+        .pdsRamLowPowerWithClkEn = 1,
+        .cpu0WfiMask = 0,
+        .ldo11Off = 1,
+        .pdsForceRamClkEn = 0,
+        .pdsLdoVol = 0xA,
+        .pdsCtlRfSel = 2,
+        .pdsCtlPllSel = 0,
+    },
+    .pdsCtl2 = {
+        .forceCpuPwrOff = 0,
+        .forceBzPwrOff = 0,
+        .forceUsbPwrOff = 0,
+        .forceCpuIsoEn = 0,
+        .forceBzIsoEn = 0,
+        .forceUsbIsoEn = 0,
+        .forceCpuPdsRst = 0,
+        .forceBzPdsRst = 0,
+        .forceUsbPdsRst = 0,
+        .forceCpuMemStby = 0,
+        .forceBzMemStby = 0,
+        .forceUsbMemStby = 0,
+        .forceCpuGateClk = 0,
+        .forceBzGateClk = 0,
+        .forceUsbGateClk = 0,
+    },
+    .pdsCtl3 = {
+        .forceMiscPwrOff = 0,
+        .forceBlePwrOff = 0,
+        .forceBleIsoEn = 0,
+        .forceMiscPdsRst = 0,
+        .forceBlePdsRst = 0,
+        .forceMiscMemStby = 0,
+        .forceBleMemStby = 0,
+        .forceMiscGateClk = 0,
+        .forceBleGateClk = 0,
+        .CpuIsoEn = 0,
+        .BzIsoEn = 1,
+        .BleIsoEn = 1,
+        .UsbIsoEn = 0,
+        .MiscIsoEn = 0,
+    },
+    .pdsCtl4 = {
+        .cpuPwrOff = 0,
+        .cpuRst = 0,
+        .cpuMemStby = 1,
+        .cpuGateClk = 1,
+        .BzPwrOff = 1,
+        .BzRst = 1,
+        .BzMemStby = 1,
+        .BzGateClk = 1,
+        .BlePwrOff = 1,
+        .BleRst = 1,
+        .BleMemStby = 1,
+        .BleGateClk = 1,
+        .UsbPwrOff = 0,
+        .UsbRst = 0,
+        .UsbMemStby = 1,
+        .UsbGateClk = 1,
+        .MiscPwrOff = 0,
+        .MiscRst = 0,
+        .MiscMemStby = 1,
+        .MiscGateClk = 1,
+        .MiscAnaPwrOff = 1,
+        .MiscDigPwrOff = 1,
+    }
+};
+static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel3 = {
+    .pdsCtl = {
+        .pdsStart = 1,
+        .sleepForever = 0,
+        .xtalForceOff = 0,
+        .saveWifiState = 0,
+        .dcdc18Off = 1,
+        .bgSysOff = 1,
+        .gpioIePuPd = 1,
+        .puFlash = 0,
+        .clkOff = 1,
+        .memStby = 1,
+        .swPuFlash = 1,
+        .isolation = 1,
+        .waitXtalRdy = 0,
+        .pdsPwrOff = 1,
+        .xtalOff = 0,
+        .socEnbForceOn = 1,
+        .pdsRstSocEn = 0,
+        .pdsRC32mOn = 0,
+        .pdsLdoVselEn = 0,
+        .pdsRamLowPowerWithClkEn = 1,
+        .cpu0WfiMask = 0,
+        .ldo11Off = 1,
+        .pdsForceRamClkEn = 0,
+        .pdsLdoVol = 0xA,
+        .pdsCtlRfSel = 2,
+        .pdsCtlPllSel = 0,
+    },
+    .pdsCtl2 = {
+        .forceCpuPwrOff = 0,
+        .forceBzPwrOff = 0,
+        .forceUsbPwrOff = 0,
+        .forceCpuIsoEn = 0,
+        .forceBzIsoEn = 0,
+        .forceUsbIsoEn = 0,
+        .forceCpuPdsRst = 0,
+        .forceBzPdsRst = 0,
+        .forceUsbPdsRst = 0,
+        .forceCpuMemStby = 0,
+        .forceBzMemStby = 0,
+        .forceUsbMemStby = 0,
+        .forceCpuGateClk = 0,
+        .forceBzGateClk = 0,
+        .forceUsbGateClk = 0,
+    },
+    .pdsCtl3 = {
+        .forceMiscPwrOff = 0,
+        .forceBlePwrOff = 0,
+        .forceBleIsoEn = 0,
+        .forceMiscPdsRst = 0,
+        .forceBlePdsRst = 0,
+        .forceMiscMemStby = 0,
+        .forceBleMemStby = 0,
+        .forceMiscGateClk = 0,
+        .forceBleGateClk = 0,
+        .CpuIsoEn = 0,
+        .BzIsoEn = 1,
+        .BleIsoEn = 1,
+        .UsbIsoEn = 1,
+        .MiscIsoEn = 0,
+    },
+    .pdsCtl4 = {
+        .cpuPwrOff = 0,
+        .cpuRst = 0,
+        .cpuMemStby = 1,
+        .cpuGateClk = 1,
+        .BzPwrOff = 1,
+        .BzRst = 1,
+        .BzMemStby = 1,
+        .BzGateClk = 1,
+        .BlePwrOff = 1,
+        .BleRst = 1,
+        .BleMemStby = 1,
+        .BleGateClk = 1,
+        .UsbPwrOff = 1,
+        .UsbRst = 1,
+        .UsbMemStby = 1,
+        .UsbGateClk = 1,
+        .MiscPwrOff = 0,
+        .MiscRst = 0,
+        .MiscMemStby = 1,
+        .MiscGateClk = 1,
+        .MiscAnaPwrOff = 1,
+        .MiscDigPwrOff = 1,
+    }
+};
+#if 0
+static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel4 = {
+    .pdsCtl = {
+        .pdsStart = 1,
+        .sleepForever = 0,
+        .xtalForceOff = 0,
+        .saveWifiState = 0,
+        .dcdc18Off = 1,
+        .bgSysOff = 1,
+        .gpioIePuPd = 1,
+        .puFlash = 0,
+        .clkOff = 1,
+        .memStby = 1,
+        .swPuFlash = 1,
+        .isolation = 1,
+        .waitXtalRdy = 0,
+        .pdsPwrOff = 1,
+        .xtalOff = 0,
+        .socEnbForceOn = 1,
+        .pdsRstSocEn = 0,
+        .pdsRC32mOn = 0,
+        .pdsLdoVselEn = 0,
+        .pdsRamLowPowerWithClkEn = 1,
+        .cpu0WfiMask = 0,
+        .ldo11Off = 1,
+        .pdsForceRamClkEn = 0,
+        .pdsLdoVol = 0xA,
+        .pdsCtlRfSel = 3,
+        .pdsCtlPllSel = 0,
+    },
+    .pdsCtl2 = {
+        .forceCpuPwrOff = 0,
+        .forceBzPwrOff = 0,
+        .forceUsbPwrOff = 0,
+        .forceCpuIsoEn = 0,
+        .forceBzIsoEn = 0,
+        .forceUsbIsoEn = 0,
+        .forceCpuPdsRst = 0,
+        .forceBzPdsRst = 0,
+        .forceUsbPdsRst = 0,
+        .forceCpuMemStby = 0,
+        .forceBzMemStby = 0,
+        .forceUsbMemStby = 0,
+        .forceCpuGateClk = 0,
+        .forceBzGateClk = 0,
+        .forceUsbGateClk = 0,
+    },
+    .pdsCtl3 = {
+        .forceMiscPwrOff = 0,
+        .forceBlePwrOff = 0,
+        .forceBleIsoEn = 0,
+        .forceMiscPdsRst = 0,
+        .forceBlePdsRst = 0,
+        .forceMiscMemStby = 0,
+        .forceBleMemStby = 0,
+        .forceMiscGateClk = 0,
+        .forceBleGateClk = 0,
+        .CpuIsoEn = 1,
+        .BzIsoEn = 0,
+        .BleIsoEn = 1,
+        .UsbIsoEn = 0,
+        .MiscIsoEn = 0,
+    },
+    .pdsCtl4 = {
+        .cpuPwrOff = 1,
+        .cpuRst = 1,
+        .cpuMemStby = 1,
+        .cpuGateClk = 1,
+        .BzPwrOff = 0,
+        .BzRst = 0,
+        .BzMemStby = 1,
+        .BzGateClk = 1,
+        .BlePwrOff = 1,
+        .BleRst = 1,
+        .BleMemStby = 1,
+        .BleGateClk = 1,
+        .UsbPwrOff = 0,
+        .UsbRst = 0,
+        .UsbMemStby = 1,
+        .UsbGateClk = 1,
+        .MiscPwrOff = 0,
+        .MiscRst = 0,
+        .MiscMemStby = 1,
+        .MiscGateClk = 1,
+        .MiscAnaPwrOff = 1,
+        .MiscDigPwrOff = 1,
+    }
+};
+static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel5 = {
+    .pdsCtl = {
+        .pdsStart = 1,
+        .sleepForever = 0,
+        .xtalForceOff = 0,
+        .saveWifiState = 0,
+        .dcdc18Off = 1,
+        .bgSysOff = 1,
+        .gpioIePuPd = 1,
+        .puFlash = 0,
+        .clkOff = 1,
+        .memStby = 1,
+        .swPuFlash = 1,
+        .isolation = 1,
+        .waitXtalRdy = 0,
+        .pdsPwrOff = 1,
+        .xtalOff = 0,
+        .socEnbForceOn = 1,
+        .pdsRstSocEn = 0,
+        .pdsRC32mOn = 0,
+        .pdsLdoVselEn = 0,
+        .pdsRamLowPowerWithClkEn = 1,
+        .cpu0WfiMask = 0,
+        .ldo11Off = 1,
+        .pdsForceRamClkEn = 0,
+        .pdsLdoVol = 0xA,
+        .pdsCtlRfSel = 3,
+        .pdsCtlPllSel = 0,
+    },
+    .pdsCtl2 = {
+        .forceCpuPwrOff = 0,
+        .forceBzPwrOff = 0,
+        .forceUsbPwrOff = 0,
+        .forceCpuIsoEn = 0,
+        .forceBzIsoEn = 0,
+        .forceUsbIsoEn = 0,
+        .forceCpuPdsRst = 0,
+        .forceBzPdsRst = 0,
+        .forceUsbPdsRst = 0,
+        .forceCpuMemStby = 0,
+        .forceBzMemStby = 0,
+        .forceUsbMemStby = 0,
+        .forceCpuGateClk = 0,
+        .forceBzGateClk = 0,
+        .forceUsbGateClk = 0,
+    },
+    .pdsCtl3 = {
+        .forceMiscPwrOff = 0,
+        .forceBlePwrOff = 0,
+        .forceBleIsoEn = 0,
+        .forceMiscPdsRst = 0,
+        .forceBlePdsRst = 0,
+        .forceMiscMemStby = 0,
+        .forceBleMemStby = 0,
+        .forceMiscGateClk = 0,
+        .forceBleGateClk = 0,
+        .CpuIsoEn = 1,
+        .BzIsoEn = 0,
+        .BleIsoEn = 1,
+        .UsbIsoEn = 1,
+        .MiscIsoEn = 0,
+    },
+    .pdsCtl4 = {
+        .cpuPwrOff = 1,
+        .cpuRst = 1,
+        .cpuMemStby = 1,
+        .cpuGateClk = 1,
+        .BzPwrOff = 0,
+        .BzRst = 0,
+        .BzMemStby = 1,
+        .BzGateClk = 1,
+        .BlePwrOff = 1,
+        .BleRst = 1,
+        .BleMemStby = 1,
+        .BleGateClk = 1,
+        .UsbPwrOff = 1,
+        .UsbRst = 1,
+        .UsbMemStby = 1,
+        .UsbGateClk = 1,
+        .MiscPwrOff = 0,
+        .MiscRst = 0,
+        .MiscMemStby = 1,
+        .MiscGateClk = 1,
+        .MiscAnaPwrOff = 1,
+        .MiscDigPwrOff = 1,
+    }
+};
+static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel6 = {
+    .pdsCtl = {
+        .pdsStart = 1,
+        .sleepForever = 0,
+        .xtalForceOff = 0,
+        .saveWifiState = 0,
+        .dcdc18Off = 1,
+        .bgSysOff = 1,
+        .gpioIePuPd = 1,
+        .puFlash = 0,
+        .clkOff = 1,
+        .memStby = 1,
+        .swPuFlash = 1,
+        .isolation = 1,
+        .waitXtalRdy = 0,
+        .pdsPwrOff = 1,
+        .xtalOff = 0,
+        .socEnbForceOn = 1,
+        .pdsRstSocEn = 0,
+        .pdsRC32mOn = 0,
+        .pdsLdoVselEn = 0,
+        .pdsRamLowPowerWithClkEn = 1,
+        .cpu0WfiMask = 0,
+        .ldo11Off = 1,
+        .pdsForceRamClkEn = 0,
+        .pdsLdoVol = 0xA,
+        .pdsCtlRfSel = 2,
+        .pdsCtlPllSel = 0,
+    },
+    .pdsCtl2 = {
+        .forceCpuPwrOff = 0,
+        .forceBzPwrOff = 0,
+        .forceUsbPwrOff = 0,
+        .forceCpuIsoEn = 0,
+        .forceBzIsoEn = 0,
+        .forceUsbIsoEn = 0,
+        .forceCpuPdsRst = 0,
+        .forceBzPdsRst = 0,
+        .forceUsbPdsRst = 0,
+        .forceCpuMemStby = 0,
+        .forceBzMemStby = 0,
+        .forceUsbMemStby = 0,
+        .forceCpuGateClk = 0,
+        .forceBzGateClk = 0,
+        .forceUsbGateClk = 0,
+    },
+    .pdsCtl3 = {
+        .forceMiscPwrOff = 0,
+        .forceBlePwrOff = 0,
+        .forceBleIsoEn = 0,
+        .forceMiscPdsRst = 0,
+        .forceBlePdsRst = 0,
+        .forceMiscMemStby = 0,
+        .forceBleMemStby = 0,
+        .forceMiscGateClk = 0,
+        .forceBleGateClk = 0,
+        .CpuIsoEn = 1,
+        .BzIsoEn = 1,
+        .BleIsoEn = 1,
+        .UsbIsoEn = 0,
+        .MiscIsoEn = 0,
+    },
+    .pdsCtl4 = {
+        .cpuPwrOff = 1,
+        .cpuRst = 1,
+        .cpuMemStby = 1,
+        .cpuGateClk = 1,
+        .BzPwrOff = 1,
+        .BzRst = 1,
+        .BzMemStby = 1,
+        .BzGateClk = 1,
+        .BlePwrOff = 1,
+        .BleRst = 1,
+        .BleMemStby = 1,
+        .BleGateClk = 1,
+        .UsbPwrOff = 0,
+        .UsbRst = 0,
+        .UsbMemStby = 1,
+        .UsbGateClk = 1,
+        .MiscPwrOff = 0,
+        .MiscRst = 0,
+        .MiscMemStby = 1,
+        .MiscGateClk = 1,
+        .MiscAnaPwrOff = 1,
+        .MiscDigPwrOff = 1,
+    }
+};
+static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel7 = {
+    .pdsCtl = {
+        .pdsStart = 1,
+        .sleepForever = 0,
+        .xtalForceOff = 0,
+        .saveWifiState = 0,
+        .dcdc18Off = 1,
+        .bgSysOff = 1,
+        .gpioIePuPd = 1,
+        .puFlash = 0,
+        .clkOff = 1,
+        .memStby = 1,
+        .swPuFlash = 1,
+        .isolation = 1,
+        .waitXtalRdy = 0,
+        .pdsPwrOff = 1,
+        .xtalOff = 0,
+        .socEnbForceOn = 1,
+        .pdsRstSocEn = 0,
+        .pdsRC32mOn = 0,
+        .pdsLdoVselEn = 0,
+        .pdsRamLowPowerWithClkEn = 1,
+        .cpu0WfiMask = 0,
+        .ldo11Off = 1,
+        .pdsForceRamClkEn = 0,
+        .pdsLdoVol = 0xA,
+        .pdsCtlRfSel = 2,
+        .pdsCtlPllSel = 0,
+    },
+    .pdsCtl2 = {
+        .forceCpuPwrOff = 0,
+        .forceBzPwrOff = 0,
+        .forceUsbPwrOff = 0,
+        .forceCpuIsoEn = 0,
+        .forceBzIsoEn = 0,
+        .forceUsbIsoEn = 0,
+        .forceCpuPdsRst = 0,
+        .forceBzPdsRst = 0,
+        .forceUsbPdsRst = 0,
+        .forceCpuMemStby = 0,
+        .forceBzMemStby = 0,
+        .forceUsbMemStby = 0,
+        .forceCpuGateClk = 0,
+        .forceBzGateClk = 0,
+        .forceUsbGateClk = 0,
+    },
+    .pdsCtl3 = {
+        .forceMiscPwrOff = 0,
+        .forceBlePwrOff = 0,
+        .forceBleIsoEn = 0,
+        .forceMiscPdsRst = 0,
+        .forceBlePdsRst = 0,
+        .forceMiscMemStby = 0,
+        .forceBleMemStby = 0,
+        .forceMiscGateClk = 0,
+        .forceBleGateClk = 0,
+        .CpuIsoEn = 1,
+        .BzIsoEn = 1,
+        .BleIsoEn = 1,
+        .UsbIsoEn = 1,
+        .MiscIsoEn = 0,
+    },
+    .pdsCtl4 = {
+        .cpuPwrOff = 1,
+        .cpuRst = 1,
+        .cpuMemStby = 1,
+        .cpuGateClk = 1,
+        .BzPwrOff = 1,
+        .BzRst = 1,
+        .BzMemStby = 1,
+        .BzGateClk = 1,
+        .BlePwrOff = 1,
+        .BleRst = 1,
+        .BleMemStby = 1,
+        .BleGateClk = 1,
+        .UsbPwrOff = 1,
+        .UsbRst = 1,
+        .UsbMemStby = 1,
+        .UsbGateClk = 1,
+        .MiscPwrOff = 0,
+        .MiscRst = 0,
+        .MiscMemStby = 1,
+        .MiscGateClk = 1,
+        .MiscAnaPwrOff = 1,
+        .MiscDigPwrOff = 1,
+    }
+};
+#endif
+static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel31 = {
+    .pdsCtl = {
+        .pdsStart = 1,
+        .sleepForever = 0,
+        .xtalForceOff = 0,
+        .saveWifiState = 0,
+        .dcdc18Off = 1,
+        .bgSysOff = 1,
+        .gpioIePuPd = 1,
+        .puFlash = 0,
+        .clkOff = 1,
+        .memStby = 1,
+        .swPuFlash = 1,
+        .isolation = 1,
+        .waitXtalRdy = 0,
+        .pdsPwrOff = 1,
+        .xtalOff = 0,
+        .socEnbForceOn = 0,
+        .pdsRstSocEn = 0,
+        .pdsRC32mOn = 0,
+        .pdsLdoVselEn = 0,
+        .pdsRamLowPowerWithClkEn = 1,
+        .cpu0WfiMask = 0,
+        .ldo11Off = 1,
+        .pdsForceRamClkEn = 0,
+        .pdsLdoVol = 0xA,
+        .pdsCtlRfSel = 2,
+        .pdsCtlPllSel = 0,
+    },
+    .pdsCtl2 = {
+        .forceCpuPwrOff = 0,
+        .forceBzPwrOff = 0,
+        .forceUsbPwrOff = 0,
+        .forceCpuIsoEn = 0,
+        .forceBzIsoEn = 0,
+        .forceUsbIsoEn = 0,
+        .forceCpuPdsRst = 0,
+        .forceBzPdsRst = 0,
+        .forceUsbPdsRst = 0,
+        .forceCpuMemStby = 0,
+        .forceBzMemStby = 0,
+        .forceUsbMemStby = 0,
+        .forceCpuGateClk = 0,
+        .forceBzGateClk = 0,
+        .forceUsbGateClk = 0,
+    },
+    .pdsCtl3 = {
+        .forceMiscPwrOff = 0,
+        .forceBlePwrOff = 0,
+        .forceBleIsoEn = 0,
+        .forceMiscPdsRst = 0,
+        .forceBlePdsRst = 0,
+        .forceMiscMemStby = 0,
+        .forceBleMemStby = 0,
+        .forceMiscGateClk = 0,
+        .forceBleGateClk = 0,
+        .CpuIsoEn = 1,
+        .BzIsoEn = 1,
+        .BleIsoEn = 1,
+        .UsbIsoEn = 1,
+        .MiscIsoEn = 1,
+    },
+    .pdsCtl4 = {
+        .cpuPwrOff = 1,
+        .cpuRst = 1,
+        .cpuMemStby = 1,
+        .cpuGateClk = 1,
+        .BzPwrOff = 1,
+        .BzRst = 1,
+        .BzMemStby = 1,
+        .BzGateClk = 1,
+        .BlePwrOff = 1,
+        .BleRst = 1,
+        .BleMemStby = 1,
+        .BleGateClk = 1,
+        .UsbPwrOff = 1,
+        .UsbRst = 1,
+        .UsbMemStby = 1,
+        .UsbGateClk = 1,
+        .MiscPwrOff = 1,
+        .MiscRst = 1,
+        .MiscMemStby = 1,
+        .MiscGateClk = 1,
+        .MiscAnaPwrOff = 1,
+        .MiscDigPwrOff = 1,
+    }
+};
+
+/****************************************************************************/ /**
+                                                                                * @brief  PDS update flash_ctrl setting
+                                                                                *
+                                                                                * @param  fastClock: fast clock
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+static ATTR_TCM_SECTION void PDS_Update_Flash_Ctrl_Setting(uint8_t fastClock) {
+  if (fastClock) {
+    GLB_Set_SF_CLK(1, GLB_SFLASH_CLK_72M, 0);
+  } else {
+    GLB_Set_SF_CLK(1, GLB_SFLASH_CLK_XCLK, 0);
+  }
+
+  SF_Ctrl_Set_Clock_Delay(fastClock);
+}
+
+ATTR_TCM_SECTION void pm_pds_enter_done(void) {
+  __asm__ __volatile__("la     a2,     __ld_pds_bak_addr\n\t"
+                       "sw     ra,     0(a2)\n\t");
+
+  __WFI(); /* if(.wfiMask==0){CPU won't power down until PDS module had seen __wfi} */
+}
+/**
+ * @brief power management in pds(power down sleep) mode
+ *
+ * cpu's behavior after wakeup depend on psd level,see flow table if cpu off , cpu will reset after wakeup
+ *
+ *                      PD_CORE     PD_CORE_MISC_DIG    PD_CORE_MISC_ANA    PD_CORE_CPU     PD_BZ   PD_USB
+ *          PDS0          ON               ON                  ON               ON            ON      ON
+ *          PDS1          ON               ON                  ON               ON            ON      OFF
+ *          PDS2          ON               ON                  ON               ON            OFF     ON
+ *          PDS3          ON               ON                  ON               ON            OFF     OFF
+ *          PDS4          ON               ON                  ON               OFF           ON      ON
+ *          PDS5          ON               ON                  ON               OFF           ON      OFF
+ *          PDS6          ON               ON                  ON               OFF           OFF     ON
+ *          PDS7          ON               ON                  ON               OFF           OFF     OFF
+ *          PDS31         ON               OFF                 OFF              OFF           OFF     OFF
+ */
+ATTR_TCM_SECTION void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint32_t sleep_time) {
+  PDS_DEFAULT_LV_CFG_Type *pPdsCfg = NULL;
+  uint32_t                 tmpVal;
+  uint32_t                 flash_cfg_len;
+
+  /* To make it simple and safe*/
+  cpu_global_irq_disable();
+
+  flash_get_cfg((uint8_t **)&flash_cfg, &flash_cfg_len);
+  HBN_Set_Ldo11_All_Vout(PM_PDS_LDO_LEVEL_DEFAULT);
+
+  PDS_WAKEUP_IRQHandler_Install();
+  BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff);
+  BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0);
+
+  tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+  tmpVal &= ~(1 << 8); // unmask pds wakeup
+
+  if (!BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_GPIO_INT), PDS_GPIO_INT_MASK) || !(BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MASK1) == 0xffffffff)) {
+    tmpVal |= (1 << 19); // enable gpio wakeup for pds
+  }
+  if (BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_IRQ_MODE), HBN_REG_AON_PAD_IE_SMT)) {
+    tmpVal |= (1 << 17); // enable hbn out0 wakeup for pds
+  }
+
+  if (sleep_time) {
+    tmpVal |= (1 << 16); // unmask pds sleep time wakeup
+  }
+  BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+  PDS_Set_Vddcore_GPIO_IntClear();
+  PDS_IntClear();
+
+  /* enable PDS interrupt to wakeup CPU (PDS1:CPU not powerdown, CPU __WFI) */
+  CPU_Interrupt_Enable(PDS_WAKEUP_IRQn);
+
+  switch (pds_level) {
+  case PM_PDS_LEVEL_0:
+    pPdsCfg = &pdsCfgLevel0;
+    break;
+  case PM_PDS_LEVEL_1:
+    pPdsCfg = &pdsCfgLevel1;
+    break;
+  case PM_PDS_LEVEL_2:
+    pPdsCfg = &pdsCfgLevel2;
+    break;
+  case PM_PDS_LEVEL_3:
+    pPdsCfg = &pdsCfgLevel3;
+    break;
+  case PM_PDS_LEVEL_4:
+    return;
+  case PM_PDS_LEVEL_5:
+    return;
+  case PM_PDS_LEVEL_6:
+    return;
+  case PM_PDS_LEVEL_7:
+    return;
+  case PM_PDS_LEVEL_31:
+    pPdsCfg = &pdsCfgLevel31;
+    break;
+  default:
+    return;
+  }
+
+#if PM_PDS_FLASH_POWER_OFF
+  HBN_Power_Down_Flash(flash_cfg);
+  /* turn_off_ext_flash_pin, GPIO23 - GPIO28 */
+  for (uint32_t pin = 23; pin <= 28; pin++) {
+    GLB_GPIO_Set_HZ(pin);
+  }
+  /* SF io select from efuse value */
+  uint32_t flash_select = BL_RD_WORD(0x40007074);
+  if (((flash_select >> 26) & 7) == 0) {
+    HBN_Set_Pad_23_28_Pullup();
+  }
+  pPdsCfg->pdsCtl.puFlash = 1;
+#endif
+
+#if PM_PDS_PLL_POWER_OFF
+  PDS_Power_Off_PLL();
+#endif
+#if PM_PDS_DLL_POWER_OFF
+  GLB_Set_System_CLK(GLB_DLL_XTAL_NONE, GLB_SYS_CLK_RC32M);
+  AON_Power_Off_XTAL();
+  GLB_Power_Off_DLL();
+  PDS_Update_Flash_Ctrl_Setting(0);
+#endif
+
+  /* pds0-pds7 : ldo11rt_iload_sel=3 */
+  /* pds31     : ldo11rt_iload_sel=1 */
+  if (pds_level <= PM_PDS_LEVEL_7) {
+    HBN_Set_Ldo11rt_Drive_Strength(HBN_LDO11RT_DRIVE_STRENGTH_25_250UA);
+  } else if (pds_level == PM_PDS_LEVEL_31) {
+    HBN_Set_Ldo11rt_Drive_Strength(HBN_LDO11RT_DRIVE_STRENGTH_10_100UA);
+  } else {
+    /* pdsLevel error */
+  }
+
+  pPdsCfg->pdsCtl.pdsLdoVol    = PM_PDS_LDO_LEVEL_DEFAULT;
+  pPdsCfg->pdsCtl.pdsLdoVselEn = 1;
+
+  if (BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_GPIO_INT), PDS_GPIO_INT_MASK)) {
+    pPdsCfg->pdsCtl.gpioIePuPd = 0;
+  }
+
+#if PM_PDS_RF_POWER_OFF == 0
+  pPdsCfg->pdsCtl.pdsCtlRfSel = 0;
+#endif
+  /* config  ldo11soc_sstart_delay_aon =2 , cr_pds_pd_ldo11=0 to speedup ldo11soc_rdy_aon */
+  AON_Set_LDO11_SOC_Sstart_Delay(0x2);
+
+  PDS_Default_Level_Config(pPdsCfg, sleep_time);
+
+  __WFI(); /* if(.wfiMask==0){CPU won't power down until PDS module had seen __wfi} */
+
+#if PM_PDS_PLL_POWER_OFF
+  GLB_Set_System_CLK(XTAL_TYPE, BSP_ROOT_CLOCK_SOURCE);
+  PDS_Update_Flash_Ctrl_Setting(1);
+#endif
+
+#if PM_PDS_FLASH_POWER_OFF
+  HBN_Set_Pad_23_28_Pullnone();
+  /* Init flash gpio */
+  SF_Cfg_Init_Flash_Gpio(0, 1);
+
+  SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
+  SFlash_Restore_From_Powerdown(flash_cfg, 0);
+#endif
+
+  cpu_global_irq_enable();
+}
+
+ATTR_TCM_SECTION void pm_pds31_fast_mode_enter(enum pm_pds_sleep_level pds_level, uint32_t sleep_time) {
+  PDS_DEFAULT_LV_CFG_Type *pPdsCfg = &pdsCfgLevel31;
+  uint32_t                 tmpVal;
+  uint32_t                 flash_cfg_len;
+
+  // Get cache way disable setting
+  cacheWayDisable = (*(volatile uint32_t *)(L1C_BASE + 0x00) >> 8) & 0x0F;
+
+  // Get psram io configuration
+  psramIoCfg = *(volatile uint32_t *)(GLB_BASE + 0x88);
+
+  // Get flash offset
+  flash_offset = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET);
+
+  /* To make it simple and safe*/
+  cpu_global_irq_disable();
+
+  flash_get_cfg((uint8_t **)&flash_cfg, &flash_cfg_len);
+  HBN_Set_Ldo11_All_Vout(PM_PDS_LDO_LEVEL_DEFAULT);
+
+  PDS_WAKEUP_IRQHandler_Install();
+  BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff);
+  BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0);
+
+  tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+  tmpVal &= ~(1 << 8); // unmask pds wakeup
+
+  if (!BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_GPIO_INT), PDS_GPIO_INT_MASK)) {
+    tmpVal |= (1 << 19); // enable gpio wakeup for pds
+  }
+  if (BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_IRQ_MODE), HBN_REG_AON_PAD_IE_SMT)) {
+    tmpVal |= (1 << 17); // enable hbn out0 wakeup for pds
+  }
+
+  if (sleep_time) {
+    tmpVal |= (1 << 16); // unmask pds sleep time wakeup
+  }
+  BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+  PDS_IntClear();
+
+  /* enable PDS interrupt to wakeup CPU (PDS1:CPU not powerdown, CPU __WFI) */
+  CPU_Interrupt_Enable(PDS_WAKEUP_IRQn);
+
+#if PM_PDS_FLASH_POWER_OFF
+  HBN_Power_Down_Flash(flash_cfg);
+  /* turn_off_ext_flash_pin, GPIO23 - GPIO28 */
+  for (uint32_t pin = 23; pin <= 28; pin++) {
+    GLB_GPIO_Set_HZ(pin);
+  }
+  /* SF io select from efuse value */
+  uint32_t flash_select = BL_RD_WORD(0x40007074);
+  if (((flash_select >> 26) & 7) == 0) {
+    HBN_Set_Pad_23_28_Pullup();
+  }
+  pPdsCfg->pdsCtl.puFlash = 1;
+#endif
+
+#if PM_PDS_PLL_POWER_OFF
+  PDS_Power_Off_PLL();
+#endif
+#if PM_PDS_DLL_POWER_OFF
+  GLB_Set_System_CLK(GLB_DLL_XTAL_NONE, GLB_SYS_CLK_RC32M);
+  AON_Power_Off_XTAL();
+  GLB_Power_Off_DLL();
+  PDS_Update_Flash_Ctrl_Setting(0);
+#endif
+
+  /* pds31     : ldo11rt_iload_sel=1 */
+  HBN_Set_Ldo11rt_Drive_Strength(HBN_LDO11RT_DRIVE_STRENGTH_10_100UA);
+
+  pPdsCfg->pdsCtl.pdsLdoVol    = PM_PDS_LDO_LEVEL_DEFAULT;
+  pPdsCfg->pdsCtl.pdsLdoVselEn = 1;
+
+  if (BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_GPIO_INT), PDS_GPIO_INT_MASK)) {
+    pPdsCfg->pdsCtl.gpioIePuPd = 0;
+  }
+
+#if PM_PDS_RF_POWER_OFF == 0
+  pPdsCfg->pdsCtl.pdsCtlRfSel = 0;
+#endif
+  /* config  ldo11soc_sstart_delay_aon =2 , cr_pds_pd_ldo11=0 to speedup ldo11soc_rdy_aon */
+  AON_Set_LDO11_SOC_Sstart_Delay(0x2);
+
+  PDS_Default_Level_Config(pPdsCfg, sleep_time);
+
+  __asm__ __volatile__("csrr   a0,     mtvec\n\t"
+                       "csrr   a1,     mstatus\n\t"
+                       "la     a2,     __ld_pds_bak_addr\n\t"
+                       "sw     sp,     1*4(a2)\n\t"
+                       "sw     tp,     2*4(a2)\n\t"
+                       "sw     t0,     3*4(a2)\n\t"
+                       "sw     t1,     4*4(a2)\n\t"
+                       "sw     t2,     5*4(a2)\n\t"
+                       "sw     fp,     6*4(a2)\n\t"
+                       "sw     s1,     7*4(a2)\n\t"
+                       "sw     a0,     8*4(a2)\n\t"
+                       "sw     a1,     9*4(a2)\n\t"
+                       "sw     a3,     10*4(a2)\n\t"
+                       "sw     a4,     11*4(a2)\n\t"
+                       "sw     a5,     12*4(a2)\n\t"
+                       "sw     a6,     13*4(a2)\n\t"
+                       "sw     a7,     14*4(a2)\n\t"
+                       "sw     s2,     15*4(a2)\n\t"
+                       "sw     s3,     16*4(a2)\n\t"
+                       "sw     s4,     17*4(a2)\n\t"
+                       "sw     s5,     18*4(a2)\n\t"
+                       "sw     s6,     19*4(a2)\n\t"
+                       "sw     s7,     20*4(a2)\n\t"
+                       "sw     s8,     21*4(a2)\n\t"
+                       "sw     s9,     22*4(a2)\n\t"
+                       "sw     s10,    23*4(a2)\n\t"
+                       "sw     s11,    24*4(a2)\n\t"
+                       "sw     t3,     25*4(a2)\n\t"
+                       "sw     t4,     26*4(a2)\n\t"
+                       "sw     t5,     27*4(a2)\n\t"
+                       "sw     t6,     28*4(a2)\n\t");
+
+  pm_pds_enter_done();
+
+  cpu_global_irq_enable();
+
+  // Get cache way disable setting
+  *(volatile uint32_t *)(L1C_BASE + 0x00) &= ~(0x0F < 8);
+  *(volatile uint32_t *)(L1C_BASE + 0x00) |= cacheWayDisable;
+
+  // Get psram io configuration
+  *(volatile uint32_t *)(GLB_BASE + 0x88) = psramIoCfg;
+}
+/**
+ * @brief
+ *
+ * power management in hbn(hibernation) mode
+ * cpu will reset after wakeup
+ *
+ * HBN_LEVEL   PD_AON       PD_AON_HNBRTC        PD_AON_HBNCORE        PD_CORE     PD_CORE_MISC_DIG    PD_CORE_MISC_ANA    PD_CORE_CPU     PD_BZ   PD_USB
+ * HBN0          ON               ON                  ON                OFF            OFF                  OFF                 OFF         OFF     OFF
+ * HBN1          ON               ON                  OFF               OFF            OFF                  OFF                 OFF         OFF     OFF
+ * HBN2          ON               OFF                 OFF               OFF            OFF                  OFF                 OFF         OFF     OFF
+ * @param hbn_level
+ */
+ATTR_TCM_SECTION void pm_hbn_mode_enter(enum pm_hbn_sleep_level hbn_level, uint8_t sleep_time) {
+  uint32_t tmpVal;
+
+  /* To make it simple and safe*/
+  cpu_global_irq_disable();
+
+  if (sleep_time && (hbn_level < PM_HBN_LEVEL_2))
+    rtc_init(sleep_time); // sleep time,unit is second
+
+  if (hbn_level >= PM_HBN_LEVEL_2)
+    HBN_Power_Off_RC32K();
+  else
+    HBN_Power_On_RC32K();
+
+  HBN_Power_Down_Flash(NULL);
+  /* SF io select from efuse value */
+  uint32_t flash_select = BL_RD_WORD(0x40007074);
+  if (((flash_select >> 26) & 7) == 0) {
+    HBN_Set_Pad_23_28_Pullup();
+  }
+
+  /* Select RC32M */
+  GLB_Set_System_CLK(GLB_DLL_XTAL_NONE, GLB_SYS_CLK_RC32M);
+  /* power off xtal */
+  AON_Power_Off_XTAL();
+  GLB_Power_Off_DLL();
+  PDS_Power_Off_PLL();
+
+  /* HBN mode LDO level */
+  tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_AON_VOUT_SEL, PM_HBN_LDO_LEVEL_DEFAULT);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_RT_VOUT_SEL, PM_HBN_LDO_LEVEL_DEFAULT);
+  BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+  /* Set HBN flag */
+  BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG);
+
+  tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+
+  /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */
+  switch (hbn_level) {
+  case PM_HBN_LEVEL_0:
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+    break;
+
+  case PM_HBN_LEVEL_1:
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+    break;
+
+  case PM_HBN_LEVEL_2:
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+    break;
+  default:
+    break;
+  }
+
+  /* Set power on option:0 for por reset twice for robust 1 for reset only once*/
+  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION);
+  BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+  *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + HBN_OUT0_IRQn) = 0;
+  *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + HBN_OUT1_IRQn) = 0;
+
+  BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff);
+  BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0);
+
+  /* Enable HBN mode */
+  tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+  tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE);
+  BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+  while (1) {
+    BL702_Delay_MS(1000);
+  }
+}
+
+ATTR_HBN_RAM_SECTION void pm_hbn_enter_again(bool reset) {
+  uint32_t tmpVal;
+  BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff);
+  BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0);
+
+  if (!reset)
+    /* Enable HBN mode */
+    BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG);
+
+  tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+  tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE);
+  BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+}
+
+void pm_set_wakeup_callback(void (*wakeup_callback)(void)) {
+  BL_WR_REG(HBN_BASE, HBN_RSV1, (uint32_t)wakeup_callback);
+  /* Set HBN flag */
+  BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG);
+}
+
+enum pm_event_type pm_get_wakeup_event(void) {
+  if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_GPIO9)) {
+    return PM_HBN_GPIO9_WAKEUP_EVENT;
+  } else if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_GPIO10)) {
+    return PM_HBN_GPIO10_WAKEUP_EVENT;
+  } else if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_GPIO11)) {
+    return PM_HBN_GPIO11_WAKEUP_EVENT;
+  } else if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_GPIO12)) {
+    return PM_HBN_GPIO12_WAKEUP_EVENT;
+  } else if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_GPIO10)) {
+  } else if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_PIR)) {
+  } else if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_BOR)) {
+    return PM_HBN_BOR_WAKEUP_EVENT;
+  } else if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_ACOMP0)) {
+    return PM_HBN_ACOMP0_WAKEUP_EVENT;
+  } else if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_ACOMP1)) {
+    return PM_HBN_ACOMP1_WAKEUP_EVENT;
+  }
+
+  return PM_HBN_WAKEUP_EVENT_NONE;
+}
+
+void pm_bor_init(void) {
+  uint32_t tmpVal;
+
+  tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_IRQ_BOR_EN);
+  BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+  tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC);
+  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_BOR);
+  BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal);
+
+  tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC);
+  tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_BOR);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_VTH, HBN_BOR_THRES_2P4V);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_SEL, HBN_BOR_MODE_POR_INDEPENDENT);
+  BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal);
+
+  tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+  tmpVal = BL_SET_REG_BIT(tmpVal, HBN_IRQ_BOR_EN);
+  BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+}
+
+void pm_hbn_out0_irq_register(void) {
+  Interrupt_Handler_Register(HBN_OUT1_IRQn, HBN_OUT0_IRQ);
+  CPU_Interrupt_Enable(HBN_OUT0_IRQn);
+}
+
+void pm_hbn_out1_irq_register(void) {
+  Interrupt_Handler_Register(HBN_OUT1_IRQn, HBN_OUT1_IRQ);
+  CPU_Interrupt_Enable(HBN_OUT1_IRQn);
+}
+
+void HBN_OUT0_IRQ(void) {
+  if (SET == HBN_Get_INT_State(HBN_INT_GPIO9)) {
+    HBN_Clear_IRQ(HBN_INT_GPIO9);
+    pm_irq_callback(PM_HBN_GPIO9_WAKEUP_EVENT);
+  } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO10)) {
+    HBN_Clear_IRQ(HBN_INT_GPIO10);
+    pm_irq_callback(PM_HBN_GPIO10_WAKEUP_EVENT);
+  } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO11)) {
+    HBN_Clear_IRQ(HBN_INT_GPIO11);
+    pm_irq_callback(PM_HBN_GPIO11_WAKEUP_EVENT);
+  } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO12)) {
+    HBN_Clear_IRQ(HBN_INT_GPIO12);
+    pm_irq_callback(PM_HBN_GPIO12_WAKEUP_EVENT);
+  } else {
+    HBN_Clear_IRQ(HBN_INT_RTC);
+    HBN_Clear_RTC_INT();
+    pm_irq_callback(PM_HBN_RTC_WAKEUP_EVENT);
+  }
+}
+
+void HBN_OUT1_IRQ(void) {
+  /* PIR */
+  if (SET == HBN_Get_INT_State(HBN_INT_PIR)) {
+    HBN_Clear_IRQ(HBN_INT_PIR);
+  }
+  /* BOR */
+  else if (SET == HBN_Get_INT_State(HBN_INT_BOR)) {
+    HBN_Clear_IRQ(HBN_INT_BOR);
+    pm_irq_callback(PM_HBN_BOR_WAKEUP_EVENT);
+  }
+  /* ACOMP0 */
+  else if (SET == HBN_Get_INT_State(HBN_INT_ACOMP0)) {
+    HBN_Clear_IRQ(HBN_INT_ACOMP0);
+    pm_irq_callback(PM_HBN_ACOMP0_WAKEUP_EVENT);
+  }
+  /* ACOMP1 */
+  else if (SET == HBN_Get_INT_State(HBN_INT_ACOMP1)) {
+    HBN_Clear_IRQ(HBN_INT_ACOMP1);
+    pm_irq_callback(PM_HBN_ACOMP1_WAKEUP_EVENT);
+  }
+}
+
+__WEAK void pm_irq_callback(enum pm_event_type event) {}
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_pm_util.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_pm_util.c
new file mode 100644
index 00000000..4636c9d1
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_pm_util.c
@@ -0,0 +1,321 @@
+/**
+ * @file hal_pm_util.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+
+#include "bl702_romdriver.h"
+#include "bl702_sf_ctrl.h"
+#include "bl702_glb.h"
+#include "hal_clock.h"
+#include "hal_pm.h"
+#include "hal_pm_util.h"
+
+/* Cache Way Disable, will get from l1c register */
+extern uint8_t cacheWayDisable;
+
+/* PSRAM IO Configuration, will get from glb register */
+extern uint32_t psramIoCfg;
+
+/* Flash offset value, will get from sf_ctrl register */
+extern uint32_t flash_offset;
+
+extern void pm_pds31_fast_mode_enter(enum pm_pds_sleep_level pds_level, uint32_t sleep_time);
+
+extern SPI_Flash_Cfg_Type *flash_cfg;
+
+void ATTR_PDS_RAM_SECTION pm_pds_fastboot_entry(void);
+
+void (*hardware_recovery)(void) = NULL;
+
+/**
+ * @brief hal_pds_enter_with_time_compensation
+ *
+ * @param pdsLevel pds level support 0~3,31
+ * @param pdsSleepCycles user set sleep time, clock of pds_time is 32768hz
+ * @return uint32_t actual sleep time(ms)
+ *
+ * @note If necessary，please application layer call vTaskStepTick，
+ */
+uint32_t hal_pds_enter_with_time_compensation(uint32_t pdsLevel, uint32_t pdsSleepCycles)
+{
+    uint32_t rtcLowBeforeSleep = 0, rtcHighBeforeSleep = 0;
+    uint32_t rtcLowAfterSleep = 0, rtcHighAfterSleep = 0;
+    uint32_t actualSleepDuration_32768cycles = 0;
+    uint32_t actualSleepDuration_ms = 0;
+
+    pm_set_wakeup_callback(pm_pds_fastboot_entry);
+
+    HBN_Get_RTC_Timer_Val(&rtcLowBeforeSleep, &rtcHighBeforeSleep);
+
+    pm_pds31_fast_mode_enter(pdsLevel, pdsSleepCycles);
+
+    HBN_Get_RTC_Timer_Val(&rtcLowAfterSleep, &rtcHighAfterSleep);
+
+    CHECK_PARAM((rtcHighAfterSleep - rtcHighBeforeSleep) <= 1); // make sure sleep less than 1 hour (2^32 us > 1 hour)
+
+    actualSleepDuration_32768cycles = (rtcLowAfterSleep - rtcLowBeforeSleep);
+
+    actualSleepDuration_ms = (actualSleepDuration_32768cycles >> 5) - (actualSleepDuration_32768cycles >> 11) - (actualSleepDuration_32768cycles >> 12);
+
+    // vTaskStepTick(actualSleepDuration_ms);
+
+    return actualSleepDuration_ms;
+}
+/**
+ * @brief get delay value of spi flash init
+ *
+ * @param delay_index
+ * @return uint8_t
+ */
+static uint8_t ATTR_PDS_RAM_SECTION bflb_spi_flash_get_delay_val(uint8_t delay_index)
+{
+    switch (delay_index) {
+        case 0:
+            return 0x00;
+        case 1:
+            return 0x80;
+        case 2:
+            return 0xc0;
+        case 3:
+            return 0xe0;
+        case 4:
+            return 0xf0;
+        case 5:
+            return 0xf8;
+        case 6:
+            return 0xfc;
+        case 7:
+            return 0xfe;
+        default:
+            return 0x00;
+    }
+}
+/**
+ * @brief config spi flash
+ *
+ * @param pFlashCfg flash parameter
+ */
+static void ATTR_PDS_RAM_SECTION bflb_spi_flash_set_sf_ctrl(SPI_Flash_Cfg_Type *pFlashCfg)
+{
+    SF_Ctrl_Cfg_Type sfCtrlCfg;
+    uint8_t delay_index;
+
+    sfCtrlCfg.owner = SF_CTRL_OWNER_SAHB;
+
+    /* bit0-3 for clk delay */
+    sfCtrlCfg.clkDelay = (pFlashCfg->clkDelay & 0x0f);
+    /* bit0 for clk invert */
+    sfCtrlCfg.clkInvert = pFlashCfg->clkInvert & 0x01;
+    /* bit1 for rx clk invert */
+    sfCtrlCfg.rxClkInvert = (pFlashCfg->clkInvert >> 1) & 0x01;
+    /* bit4-6 for do delay */
+    delay_index = (pFlashCfg->clkDelay >> 4) & 0x07;
+    sfCtrlCfg.doDelay = bflb_spi_flash_get_delay_val(delay_index);
+    /* bit2-4 for di delay */
+    delay_index = (pFlashCfg->clkInvert >> 2) & 0x07;
+    sfCtrlCfg.diDelay = bflb_spi_flash_get_delay_val(delay_index);
+    /* bit5-7 for oe delay */
+    delay_index = (pFlashCfg->clkInvert >> 5) & 0x07;
+    sfCtrlCfg.oeDelay = bflb_spi_flash_get_delay_val(delay_index);
+
+    RomDriver_SFlash_Init(&sfCtrlCfg);
+}
+
+/**
+ * @brief
+ *
+ * @param media_boot
+ * @return int32_t
+ */
+int32_t ATTR_PDS_RAM_SECTION pm_spi_flash_init(uint8_t media_boot)
+{
+    uint32_t stat;
+    uint32_t jdecId = 0;
+    uint32_t flash_read_try = 0;
+
+    /*use fclk as flash clok */
+    RomDriver_GLB_Set_SF_CLK(1, GLB_SFLASH_CLK_XCLK, 0); // 32M
+    RomDriver_SF_Ctrl_Set_Clock_Delay(0);
+
+    bflb_spi_flash_set_sf_ctrl(flash_cfg);
+
+    /* Wake flash up from power down */
+    RomDriver_SFlash_Releae_Powerdown(flash_cfg);
+    //ARCH_Delay_US(15*((pFlashCfg->pdDelay&0x7)+1));
+    RomDriver_BL702_Delay_US(120);
+
+    do {
+        if (flash_read_try > 4) {
+            // bflb_bootrom_printd("Flash read id TO\r\n");
+            break;
+        } else if (flash_read_try > 0) {
+            RomDriver_BL702_Delay_US(500);
+        }
+
+        // bflb_bootrom_printd("reset flash\r\n");
+        /* Exit form continous read for accepting command */
+        RomDriver_SFlash_Reset_Continue_Read(flash_cfg);
+        /* Send software reset command(80bv has no this command)to deburst wrap for ISSI like */
+        RomDriver_SFlash_Software_Reset(flash_cfg);
+        /* Disable burst may be removed(except for 80BV) and only work with winbond,but just for make sure */
+        RomDriver_SFlash_Write_Enable(flash_cfg);
+        /* For disable command that is setting register instaed of send command, we need write enable */
+        RomDriver_SFlash_DisableBurstWrap(flash_cfg);
+
+        stat = RomDriver_SFlash_SetSPIMode(SF_CTRL_SPI_MODE);
+        if (SUCCESS != stat) {
+            // bflb_bootrom_printe("enter spi mode fail %d\r\n", stat);
+            // return BFLB_BOOTROM_FLASH_INIT_ERROR;
+            return -1;
+        }
+
+        RomDriver_SFlash_GetJedecId(flash_cfg, (uint8_t *)&jdecId);
+
+        /* Dummy disable burstwrap for make sure */
+        RomDriver_SFlash_Write_Enable(flash_cfg);
+        /* For disable command that is setting register instead of send command, we need write enable */
+        RomDriver_SFlash_DisableBurstWrap(flash_cfg);
+
+        jdecId = jdecId & 0xffffff;
+        // bflb_bootrom_printd("ID =%08x\r\n", jdecId);
+        flash_read_try++;
+    } while ((jdecId & 0x00ffff) == 0 || (jdecId & 0xffff00) == 0 || (jdecId & 0x00ffff) == 0xffff || (jdecId & 0xffff00) == 0xffff00);
+
+    /*clear offset setting*/
+
+    // reset image offset
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET, flash_offset);
+
+    /* set read mode */
+    if ((flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) {
+        stat = RomDriver_SFlash_Qspi_Enable(flash_cfg);
+    }
+
+    if (media_boot) {
+        RomDriver_L1C_Set_Wrap(DISABLE);
+
+        RomDriver_SFlash_Cache_Read_Enable(flash_cfg, flash_cfg->ioMode & 0xf, 0, 0x00);
+    }
+
+    return jdecId;
+}
+
+// can be placed in flash, here placed in pds section to reduce fast boot time
+static void ATTR_PDS_RAM_SECTION pm_pds_restore_cpu_reg(void)
+{
+    __asm__ __volatile__(
+        "la     a2,     __ld_pds_bak_addr\n\t"
+        "lw     ra,     0(a2)\n\t"
+        "lw     sp,     1*4(a2)\n\t"
+        "lw     tp,     2*4(a2)\n\t"
+        "lw     t0,     3*4(a2)\n\t"
+        "lw     t1,     4*4(a2)\n\t"
+        "lw     t2,     5*4(a2)\n\t"
+        "lw     fp,     6*4(a2)\n\t"
+        "lw     s1,     7*4(a2)\n\t"
+        "lw     a0,     8*4(a2)\n\t"
+        "lw     a1,     9*4(a2)\n\t"
+        "lw     a3,     10*4(a2)\n\t"
+        "lw     a4,     11*4(a2)\n\t"
+        "lw     a5,     12*4(a2)\n\t"
+        "lw     a6,     13*4(a2)\n\t"
+        "lw     a7,     14*4(a2)\n\t"
+        "lw     s2,     15*4(a2)\n\t"
+        "lw     s3,     16*4(a2)\n\t"
+        "lw     s4,     17*4(a2)\n\t"
+        "lw     s5,     18*4(a2)\n\t"
+        "lw     s6,     19*4(a2)\n\t"
+        "lw     s7,     20*4(a2)\n\t"
+        "lw     s8,     21*4(a2)\n\t"
+        "lw     s9,     22*4(a2)\n\t"
+        "lw     s10,    23*4(a2)\n\t"
+        "lw     s11,    24*4(a2)\n\t"
+        "lw     t3,     25*4(a2)\n\t"
+        "lw     t4,     26*4(a2)\n\t"
+        "lw     t5,     27*4(a2)\n\t"
+        "lw     t6,     28*4(a2)\n\t"
+        "csrw   mtvec,  a0\n\t"
+        "csrw   mstatus,a1\n\t"
+        "ret\n\t");
+}
+void ATTR_PDS_RAM_SECTION sf_io_select(void)
+{
+    uint32_t tmpVal = 0;
+    uint8_t flashCfg = 0;
+    uint8_t psramCfg = 0;
+    uint8_t isInternalFlash = 0;
+    uint8_t isInternalPsram = 0;
+
+    /* SF io select from efuse value */
+    tmpVal = BL_RD_WORD(0x40007074);
+    flashCfg = ((tmpVal >> 26) & 7);
+    psramCfg = ((tmpVal >> 24) & 3);
+    if (flashCfg == 1 || flashCfg == 2) {
+        isInternalFlash = 1;
+    } else {
+        isInternalFlash = 0;
+    }
+    if (psramCfg == 1) {
+        isInternalPsram = 1;
+    } else {
+        isInternalPsram = 0;
+    }
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO);
+    if (isInternalFlash == 1 && isInternalPsram == 0) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x3f);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x00);
+    }
+    BL_WR_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO, tmpVal);
+}
+// must be placed in pds section
+void ATTR_PDS_RAM_SECTION pm_pds_fastboot_entry(void)
+{
+    // reload gp register
+    __asm__ __volatile__(
+        ".option push\n\t"
+        ".option norelax\n\t"
+        "la gp, __global_pointer$\n\t"
+        ".option pop\n\t");
+
+#if XTAL_TYPE != INTERNAL_RC_32M
+    /* power on Xtal_32M*/
+    (*(volatile uint32_t *)(AON_BASE + AON_RF_TOP_AON_OFFSET)) |= (3 << 4);
+#endif
+
+    // recovery flash pad and param
+    RomDriver_SF_Cfg_Init_Flash_Gpio(0, 1);
+    pm_spi_flash_init(1);
+    sf_io_select();
+
+    /* Recovery hardware , include tcm , gpio and clock */
+    if (hardware_recovery) {
+        hardware_recovery();
+    }
+
+    // Restore cpu registers
+    pm_pds_restore_cpu_reg();
+}
+
+void pm_set_hardware_recovery_callback(void (*hardware_recovery_cb)(void))
+{
+    hardware_recovery = hardware_recovery_cb;
+}
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_rtc.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_rtc.c
new file mode 100644
index 00000000..9b4a4368
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_rtc.c
@@ -0,0 +1,101 @@
+/**
+ * @file hal_rtc.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "hal_rtc.h"
+#include "bl702_hbn.h"
+
+static uint64_t current_timestamp = 0;
+/**
+ * @brief rtc init withc sleep time
+ *
+ * @param sleep_time
+ */
+void rtc_init(uint64_t sleep_time)
+{
+    uint32_t tmpVal;
+    uint32_t comp_l, comp_h;
+
+    /* Clear & Disable RTC counter */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Clear RTC control bit0 */
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffff0);
+
+    /* Get current RTC timer */
+    /* Tigger RTC val read */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);
+    BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);
+    BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);
+
+    /* Read RTC val */
+    comp_l = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_L);
+    comp_h = (BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H) & 0xff);
+
+    /* calculate RTC Comp time */
+    comp_l += (uint32_t)((sleep_time * 32768) & 0xFFFFFFFF);
+    comp_h += (uint32_t)(((sleep_time * 32768) >> 32) & 0xFFFFFFFF);
+
+    /* Set RTC Comp time  */
+    BL_WR_REG(HBN_BASE, HBN_TIME_L, comp_l);
+    BL_WR_REG(HBN_BASE, HBN_TIME_H, comp_h & 0xff);
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Set interrupt delay option */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RTC_DLY_OPTION, HBN_RTC_INT_DELAY_0T);
+    /* Set RTC compare mode */
+    tmpVal |= (HBN_RTC_COMP_BIT0_39 << 1);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    /* Enable RTC Counter */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Set RTC control bit0 */
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal | 0x01);
+}
+
+void rtc_set_timestamp(uint64_t time_stamp)
+{
+    current_timestamp = time_stamp;
+}
+/**
+* @bref Get rtc value
+*
+*/
+uint64_t rtc_get_timestamp(void)
+{
+    uint32_t tmpVal;
+    uint64_t time_l;
+    uint64_t time_h;
+
+    /* Tigger RTC val read */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);
+    BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);
+    BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);
+
+    /* Read RTC val */
+    time_l = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_L);
+    time_h = (BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H) & 0xff);
+
+    return (((time_h << 32 | time_l) >> 15) + current_timestamp);
+}
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_aes.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_aes.c
new file mode 100644
index 00000000..7cc6410a
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_aes.c
@@ -0,0 +1,119 @@
+/**
+ * @file hal_sec_aes.c
+ * @brief
+ *
+ * Copyright 2019-2030 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "hal_sec_aes.h"
+#include "bl702_sec_eng.h"
+
+static SEC_Eng_AES_Ctx aesCtx;
+
+int sec_aes_init(sec_aes_handle_t *handle, sec_aes_type aes_tye, sec_aes_key_type key_type)
+{
+    handle->aes_type = aes_tye;
+    handle->key_type = key_type;
+
+    return 0;
+}
+
+static SEC_ENG_AES_Key_Type sec_aes_get_key_type(sec_aes_handle_t *handle)
+{
+    SEC_ENG_AES_Key_Type type = 0;
+
+    switch (handle->key_type) {
+        case SEC_AES_KEY_128:
+            type = SEC_ENG_AES_KEY_128BITS;
+            break;
+
+        case SEC_AES_KEY_256:
+            type = SEC_ENG_AES_KEY_256BITS;
+            break;
+
+        case SEC_AES_KEY_192:
+            type = SEC_ENG_AES_KEY_192BITS;
+            break;
+
+        default:
+            return SEC_ENG_AES_KEY_128BITS;
+    }
+
+    return type;
+}
+
+int sec_aes_setkey(sec_aes_handle_t *handle, const uint8_t *key, uint8_t key_len, const uint8_t *nonce, uint8_t dir)
+{
+    SEC_ENG_AES_Key_Type type = sec_aes_get_key_type(handle);
+
+    switch (handle->aes_type) {
+        case SEC_AES_CBC:
+            Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID0);
+            Sec_Eng_AES_Init(&aesCtx, SEC_ENG_AES_ID0, SEC_ENG_AES_CBC, type,
+                             SEC_AES_DIR_ENCRYPT == dir ? SEC_ENG_AES_ENCRYPTION : SEC_ENG_AES_DECRYPTION);
+            break;
+
+        case SEC_AES_CTR:
+            Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID0);
+            Sec_Eng_AES_Init(&aesCtx, SEC_ENG_AES_ID0, SEC_ENG_AES_CTR, type,
+                             SEC_AES_DIR_ENCRYPT == dir ? SEC_ENG_AES_ENCRYPTION : SEC_ENG_AES_DECRYPTION);
+            break;
+
+        case SEC_AES_ECB:
+            break;
+
+        default:
+            return -1;
+    }
+
+    /* if key len is 0, means key is from efuse and *key value is key_sel value */
+    if (key_len == 0) {
+        Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID0, SEC_ENG_AES_KEY_HW, key, nonce);
+    } else {
+        Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID0, SEC_ENG_AES_KEY_SW, key, nonce);
+    }
+
+    return 0;
+}
+
+int sec_aes_encrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out)
+{
+    if (SUCCESS != Sec_Eng_AES_Crypt(&aesCtx, SEC_ENG_AES_ID0, in, len, out)) {
+        return -1;
+    }
+
+    return 0;
+}
+
+int sec_aes_decrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out)
+{
+    if (SUCCESS != Sec_Eng_AES_Crypt(&aesCtx, SEC_ENG_AES_ID0, in, len, out)) {
+        return -1;
+    }
+
+    return 0;
+}
+
+int sec_aes_deinit(sec_aes_handle_t *handle)
+{
+    Sec_Eng_AES_Finish(SEC_ENG_AES_ID0);
+
+    memset(handle, 0, sizeof(sec_aes_handle_t));
+
+    return 0;
+}
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_dsa.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_dsa.c
new file mode 100644
index 00000000..3929b90d
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_dsa.c
@@ -0,0 +1,389 @@
+/**
+ * @file hal_sec_dsa.c
+ * @brief
+ *
+ * Copyright 2019-2030 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "hal_sec_dsa.h"
+#include "bl702_sec_eng.h"
+
+//#define DSA_DBG                                   1
+//#define DSA_DBG_DETAIL                            1
+void bflb_platform_dump(uint8_t *data, uint32_t len);
+
+#if (defined(DSA_DBG) || defined(DSA_DBG_DETAIL))
+uint32_t pka_tmp[64] = { 0 };
+#endif
+
+/*
+n=p*q;
+F(n)=(p-1)*(q-1)
+e*d%F(n)=1[e is public key and d is private key]
+dP=d%(p-1)
+dQ=d%(q-1)
+m1=c^(dP)%p
+m2=c^(dQ)%q
+h=qInv*(m1-m2)%p
+m=m2+h*q
+m=c^d
+*/
+static SEC_ENG_PKA_REG_SIZE_Type sec_dsa_get_reg_size(uint32_t size)
+{
+    switch (size) {
+        case 64:
+            return SEC_ENG_PKA_REG_SIZE_8;
+
+        case 128:
+            return SEC_ENG_PKA_REG_SIZE_16;
+
+        case 256:
+            return SEC_ENG_PKA_REG_SIZE_32;
+
+        case 512:
+            return SEC_ENG_PKA_REG_SIZE_64;
+
+        case 768:
+            return SEC_ENG_PKA_REG_SIZE_96;
+
+        case 1024:
+            return SEC_ENG_PKA_REG_SIZE_128;
+
+        case 1536:
+            return SEC_ENG_PKA_REG_SIZE_192;
+
+        case 2048:
+            return SEC_ENG_PKA_REG_SIZE_256;
+
+        case 3072:
+            return SEC_ENG_PKA_REG_SIZE_384;
+
+        case 4096:
+            return SEC_ENG_PKA_REG_SIZE_512;
+
+        default:
+            return SEC_ENG_PKA_REG_SIZE_32;
+    }
+
+    return SEC_ENG_PKA_REG_SIZE_32;
+}
+
+/* c code:
+number = 1
+base = a
+while b:
+    if b & 1:
+        number = number * base % c
+    b >>= 1
+    base = base * base % c
+return number
+*/
+int sec_dsa_mexp_binary(uint32_t size, const uint32_t *a, const uint32_t *b, const uint32_t *c, uint32_t *r)
+{
+    uint32_t i, j, k;
+    uint32_t tmp;
+    uint32_t isOne = 0;
+    uint8_t *p = (uint8_t *)b;
+    SEC_ENG_PKA_REG_SIZE_Type nregType = sec_dsa_get_reg_size(size);
+    SEC_ENG_PKA_REG_SIZE_Type lregType = sec_dsa_get_reg_size(size * 2);
+    uint32_t dataSize = (size >> 3) >> 2;
+#if 1
+    uint8_t oneBuf[128] ALIGN4 = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                                   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                                   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                                   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                                   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                                   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                                   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                                   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                                   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                                   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                                   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                                   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                                   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                                   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                                   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                                   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 };
+#endif
+    /* 0:c
+     * 4:a
+     * 5:number
+     * 6&7:temp
+     */
+
+    /* base = a */
+    Sec_Eng_PKA_Write_Data(nregType, 4, (uint32_t *)a, dataSize, 0);
+
+    /* number = 1 */
+    Sec_Eng_PKA_Write_Data(nregType, 5, (uint32_t *)oneBuf, sizeof(oneBuf) / 4, 0);
+    //Sec_Eng_PKA_Write_Immediate(nregType,5,0x01,1);
+#ifdef DSA_DBG
+    Sec_Eng_PKA_Read_Data(nregType, 5, (uint32_t *)pka_tmp, dataSize);
+    MSG("number:\r\n");
+    bflb_platform_dump(pka_tmp, dataSize * 4);
+#endif
+
+    Sec_Eng_PKA_Write_Data(nregType, 0, (uint32_t *)c, dataSize, 0);
+
+    Sec_Eng_PKA_CREG(nregType, 6, dataSize, 1);
+    Sec_Eng_PKA_CREG(nregType, 7, dataSize, 1);
+#ifdef DSA_DBG
+    Sec_Eng_PKA_Read_Data(nregType, 4, (uint32_t *)pka_tmp, dataSize);
+    MSG("base:\r\n");
+    bflb_platform_dump(pka_tmp, dataSize * 4);
+#endif
+    /* Remove zeros bytes*/
+    k = 0;
+
+    while (p[k] == 0 && k < (size >> 3)) {
+        k++;
+    }
+
+    i = (size >> 3) - 1;
+
+    for (; i >= k; i--) {
+        tmp = p[i];
+        j = 0;
+
+        for (j = 0; j < 8; j++) {
+            isOne = tmp & (1 << j);
+
+            if (isOne) {
+                /* number = number * base % c */
+                Sec_Eng_PKA_LMUL(lregType, 3, nregType, 5, nregType, 4, 0);
+                Sec_Eng_PKA_MREM(nregType, 5, lregType, 3, nregType, 0, 1);
+#ifdef DSA_DBG
+                Sec_Eng_PKA_Read_Data(nregType, 5, (uint32_t *)pka_tmp, dataSize);
+                MSG("number:\r\n");
+                bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*/);
+#endif
+            }
+
+            /* base = base * base % c */
+            Sec_Eng_PKA_LSQR(lregType, 3, nregType, 4, 0);
+            Sec_Eng_PKA_MREM(nregType, 4, lregType, 3, nregType, 0, 1);
+#ifdef DSA_DBG
+            Sec_Eng_PKA_Read_Data(nregType, 4, (uint32_t *)pka_tmp, dataSize);
+            MSG("base:\r\n");
+            bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*/);
+#endif
+        }
+    }
+
+    Sec_Eng_PKA_Read_Data(nregType, 5, (uint32_t *)r, dataSize);
+#ifdef DSA_DBG
+    MSG("r:\r\n");
+    bflb_platform_dump(r, dataSize * 4);
+#endif
+    return 0;
+}
+
+/*r=a^b%c*/
+int sec_dsa_mexp_mont(uint32_t size, uint32_t *a, uint32_t *b, uint32_t *c, uint32_t *invR_c, uint32_t *primeN_c, uint32_t *r)
+{
+    SEC_ENG_PKA_REG_SIZE_Type nregType = sec_dsa_get_reg_size(size);
+    SEC_ENG_PKA_REG_SIZE_Type lregType = sec_dsa_get_reg_size(size * 2);
+    uint32_t dataSize = (size >> 3) >> 2;
+
+    /* 0:c
+     * 1:NPrime_c
+     * 2:invR_c
+     * 4:a(mont domain)
+     * 5:b
+     * 6:a^b%c(mont domain)
+     * 7:a^b%c(gf domain)
+     * 10&11:2^size for GF2Mont*/
+    Sec_Eng_PKA_Write_Data(nregType, 0, (uint32_t *)c, dataSize, 0);
+    Sec_Eng_PKA_Write_Data(nregType, 1, (uint32_t *)primeN_c, dataSize, 1);
+    Sec_Eng_PKA_Write_Data(nregType, 2, (uint32_t *)invR_c, dataSize, 1);
+
+    /* change a into mont domain*/
+    Sec_Eng_PKA_Write_Data(nregType, 4, (uint32_t *)a, dataSize, 0);
+    Sec_Eng_PKA_CREG(nregType, 10, dataSize, 1);
+    Sec_Eng_PKA_CREG(nregType, 11, dataSize, 1);
+    Sec_Eng_PKA_GF2Mont(nregType, 4, nregType, 4, size, lregType, 5, nregType, 0);
+#ifdef DSA_DBG
+    Sec_Eng_PKA_Read_Data(nregType, 4, (uint32_t *)pka_tmp, dataSize);
+    MSG("GF2Mont Result of a:\r\n");
+    bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*/);
+#endif
+
+    Sec_Eng_PKA_Write_Data(nregType, 5, (uint32_t *)b, dataSize, 0);
+    /* a^b%c*/
+    Sec_Eng_PKA_MEXP(nregType, 6, nregType, 4, nregType, 5, nregType, 0, 1);
+
+    /* change result into gf domain*/
+    Sec_Eng_PKA_CREG(nregType, 10, dataSize, 1);
+    Sec_Eng_PKA_CREG(nregType, 11, dataSize, 1);
+    /*index 2 is invertR*/
+    Sec_Eng_PKA_Mont2GF(nregType, 7, nregType, 6, nregType, 2, lregType, 5, nregType, 0);
+    Sec_Eng_PKA_Read_Data(nregType, 7, (uint32_t *)r, dataSize);
+#ifdef DSA_DBG
+    MSG("r:\r\n");
+    bflb_platform_dump(r, dataSize /*dataSize*4*/);
+#endif
+    return 0;
+}
+
+/**
+ * dP=d%(p-1)
+ * dQ=d%(q-1)
+ * qInv=qp^(1-1):qInv*q%p=1
+ * invR_p*r%p=1(r is 1024/2048/256)
+ * invR_q*r%q=1(r is 1024/2048/256)
+ */
+int sec_dsa_decrypt_crt(uint32_t size, uint32_t *c, sec_dsa_crt_cfg_t *crtCfg, uint32_t *d, uint32_t *r)
+{
+    /*
+     * m1 = pow(c, dP, p)
+     * m2 = pow(c, dQ, q)
+     * h = (qInv * (m1 - m2)) % p
+     * m = m2 + h * q
+     * */
+    SEC_ENG_PKA_REG_SIZE_Type nregType = sec_dsa_get_reg_size(size);
+    SEC_ENG_PKA_REG_SIZE_Type lregType = sec_dsa_get_reg_size(size * 2);
+    uint32_t dataSize = (size >> 3) >> 2;
+#if 0
+    uint8_t  m1[64] = {0x11, 0xdd, 0x19, 0x7e, 0x69, 0x1a, 0x40, 0x0a, 0x28, 0xfc, 0x3b, 0x31, 0x47, 0xa2, 0x6c, 0x14,
+                       0x4e, 0xf6, 0xb0, 0xe6, 0xcd, 0x89, 0x0b, 0x4f, 0x02, 0xe4, 0x86, 0xe2, 0xe5, 0xbe, 0xe1, 0xaf,
+                       0x91, 0xd1, 0x7b, 0x59, 0x8d, 0xdc, 0xb3, 0x57, 0x18, 0xcb, 0x80, 0x05, 0x1c, 0xb5, 0xa4, 0x07,
+                       0xde, 0x31, 0x94, 0xa4, 0x2f, 0x45, 0xc7, 0x95, 0x75, 0x0f, 0x91, 0xf0, 0x37, 0x91, 0x85, 0xa5
+                      };
+    uint8_t  m2[64] = {0x63, 0x89, 0xa3, 0xbb, 0x64, 0x63, 0x87, 0x4f, 0x38, 0xbd, 0x9e, 0x0e, 0x93, 0x29, 0x58, 0xee,
+                       0xf8, 0xe2, 0x20, 0x2d, 0xe5, 0x38, 0x0a, 0x7f, 0x18, 0x38, 0x2f, 0xa3, 0xf5, 0x48, 0xf8, 0xfd,
+                       0xe5, 0x78, 0x4a, 0x10, 0x62, 0x01, 0x09, 0x29, 0xe3, 0xe3, 0x9f, 0xad, 0x9b, 0xbe, 0x20, 0xd2,
+                       0x68, 0x90, 0x57, 0x97, 0xfc, 0x78, 0xd5, 0xdb, 0x07, 0x5b, 0xfe, 0x21, 0x0a, 0x2d, 0x7f, 0xc1
+                      };
+#else
+    uint32_t m1[32];
+    uint32_t m2[32];
+#endif
+    /*
+     * 4:m1
+     * 5:m2
+     * 6:qInv
+     * 7:p
+     * 8:q
+     * 9:h
+     * 10&11:qInv*(m1-m2)
+     */
+    sec_dsa_mexp_mont(size, c, crtCfg->dP, crtCfg->p, crtCfg->invR_p, crtCfg->primeN_p, m1);
+    sec_dsa_mexp_mont(size, c, crtCfg->dQ, crtCfg->q, crtCfg->invR_q, crtCfg->primeN_q, m2);
+
+    Sec_Eng_PKA_Write_Data(nregType, 4, (uint32_t *)m1, dataSize, 0);
+    Sec_Eng_PKA_Write_Data(nregType, 5, (uint32_t *)m2, dataSize, 0);
+    Sec_Eng_PKA_Write_Data(nregType, 6, (uint32_t *)crtCfg->qInv, dataSize, 0);
+    Sec_Eng_PKA_Write_Data(nregType, 7, (uint32_t *)crtCfg->p, dataSize, 0);
+    Sec_Eng_PKA_Write_Data(nregType, 8, (uint32_t *)crtCfg->q, dataSize, 0);
+
+    /*(m1 - m2)%p*/
+    Sec_Eng_PKA_MSUB(nregType, 4, nregType, 4, nregType, 5, nregType, 7, 1);
+#ifdef DSA_DBG
+    Sec_Eng_PKA_Read_Data(nregType, 4, (uint32_t *)pka_tmp, dataSize);
+    MSG("m1 - m2:\r\n");
+    bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*/);
+#endif
+    /* (qInv * (m1 - m2)) % p*/
+    Sec_Eng_PKA_CREG(nregType, 10, dataSize, 1);
+    Sec_Eng_PKA_CREG(nregType, 11, dataSize, 1);
+    Sec_Eng_PKA_LMUL(lregType, 5, nregType, 6, nregType, 4, 1);
+#ifdef DSA_DBG
+    Sec_Eng_PKA_Read_Data(lregType, 5, (uint32_t *)pka_tmp, dataSize * 2);
+    MSG("qInv * (m1 - m2):\r\n");
+    bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*2*/);
+#endif
+    Sec_Eng_PKA_MREM(nregType, 9, lregType, 5, nregType, 7, 1);
+#ifdef DSA_DBG
+    Sec_Eng_PKA_Read_Data(nregType, 9, (uint32_t *)pka_tmp, dataSize);
+    MSG("h:\r\n");
+    bflb_platform_dump(pka_tmp, dataSize * 4);
+#endif
+
+    /* h*q */
+    Sec_Eng_PKA_CREG(nregType, 10, dataSize, 1);
+    Sec_Eng_PKA_CREG(nregType, 11, dataSize, 1);
+    Sec_Eng_PKA_LMUL(lregType, 5, nregType, 9, nregType, 8, 1);
+#ifdef DSA_DBG
+    Sec_Eng_PKA_Read_Data(lregType, 5, (uint32_t *)pka_tmp, dataSize * 2);
+    MSG("h*q:\r\n");
+    bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*2*/);
+#endif
+    /* m2 + h*q*/
+    Sec_Eng_PKA_LADD(lregType, 5, lregType, 5, nregType, 5, 1);
+
+    Sec_Eng_PKA_Read_Data(lregType, 5, (uint32_t *)r, dataSize * 2);
+#ifdef DSA_DBG
+    MSG("r:\r\n");
+    bflb_platform_dump(r, dataSize * 4 * 2);
+#endif
+    return 0;
+}
+
+int sec_dsa_init(sec_dsa_handle_t *handle, uint32_t size)
+{
+    Sec_Eng_PKA_Reset();
+    Sec_Eng_PKA_BigEndian_Enable();
+
+    memset(handle, 0, sizeof(sec_dsa_handle_t));
+    handle->size = size;
+    handle->crtSize = (size >> 1);
+
+    return 0;
+}
+
+int sec_dsa_sign(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *s)
+{
+    uint32_t dsa_tmp[64] = { 0 };
+
+    Sec_Eng_PKA_Reset();
+    Sec_Eng_PKA_BigEndian_Enable();
+
+    memcpy(dsa_tmp + ((handle->crtSize >> 3) >> 2) - hashLenInWord, hash, hashLenInWord * 4);
+
+    if (0 == sec_dsa_decrypt_crt(handle->crtSize, dsa_tmp, &handle->crtCfg, handle->d, s)) {
+        return 0;
+    } else {
+        return -1;
+    }
+}
+
+/**
+ */
+int sec_dsa_verify(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *s)
+{
+    uint32_t dsa_tmp[64];
+    uint8_t i = 0;
+    uint8_t resultOffset = 0;
+
+    Sec_Eng_PKA_Reset();
+    Sec_Eng_PKA_BigEndian_Enable();
+
+    if (0 == sec_dsa_mexp_binary(handle->size, s, handle->e, handle->n, dsa_tmp)) {
+        resultOffset = (handle->size >> 5) - hashLenInWord;
+
+        for (i = 0; i < hashLenInWord; i++) {
+            if (dsa_tmp[resultOffset + i] != hash[i]) {
+                return -1;
+            }
+        }
+
+        return 0;
+    } else {
+        return -1;
+    }
+}
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_ecdsa.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_ecdsa.c
new file mode 100644
index 00000000..8ba150f5
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_ecdsa.c
@@ -0,0 +1,1450 @@
+#include "hal_sec_ecdsa.h"
+#include "bl702_sec_eng.h"
+
+#define ECP_SECP256R1_REG_TYPE           SEC_ENG_PKA_REG_SIZE_32
+#define ECP_SECP256R1_N_REG_INDEX        0
+#define ECP_SECP256R1_NPRIME_N_REG_INDEX 1
+#define ECP_SECP256R1_INVR_N_REG_INDEX   2
+#define ECP_SECP256R1_NPRIME_P_REG_INDEX 3
+#define ECP_SECP256R1_INVR_P_REG_INDEX   4
+#define ECP_SECP256R1_SIZE               32
+/* Used in verify */
+#define ECP_SECP256R1_S_REG_INDEX     5
+#define ECP_SECP256R1_BAR_S_REG_INDEX 6
+#define ECP_SECP256R1_HASH_REG_INDEX  6 //use ECP_SECP256R1_BAR_S_REG_INDEX since it's temp
+#define ECP_SECP256R1_U1_REG_INDEX    7
+#define ECP_SECP256R1_LT_REG_TYPE     SEC_ENG_PKA_REG_SIZE_64
+#define ECP_SECP256R1_LT_REG_INDEX    7
+#define ECP_SECP256R1_SLT_REG_TYPE    SEC_ENG_PKA_REG_SIZE_128
+#define ECP_SECP256R1_SLT_REG_INDEX   3
+
+//#define ECDSA_DBG                                   1
+//#define ECDSA_DBG_DETAIL                            1
+
+#define secp256r1
+#define secp256k1
+#define SEC_ECC_POINT_MUL_PARAM_CFG(G) sec_ecc_point_mul_cfg( \
+    (uint32_t *)G##P,                                         \
+    (uint32_t *)G##PrimeN_P,                                  \
+    (uint32_t *)G##_1,                                        \
+    (uint32_t *)G##_BAR2,                                     \
+    (uint32_t *)G##_BAR3,                                     \
+    (uint32_t *)G##_BAR4,                                     \
+    (uint32_t *)G##_BAR8,                                     \
+    (uint32_t *)G##_1P1,                                      \
+    (uint32_t *)G##_1M1)
+
+#define SEC_ECC_BASIC_PARAM_CFG(G) sec_ecc_basic_parameter_cfg( \
+    (uint32_t *)G##N,                                           \
+    (uint32_t *)G##PrimeN_N,                                    \
+    (uint32_t *)G##InvR_N)
+
+void bflb_platform_dump(uint8_t *data, uint32_t len);
+
+#if (defined(ECDSA_DBG) || defined(ECDSA_DBG_DETAIL))
+uint32_t pka_tmp[32] = { 0 };
+#endif
+/********************************************** secp256r1 *******************************************/
+const uint8_t secp256r1P[32] ALIGN4 = {
+    0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+};
+const uint8_t secp256r1B[32] ALIGN4 = {
+    0x5a, 0xc6, 0x35, 0xd8, 0xaa, 0x3a, 0x93, 0xe7, 0xb3, 0xeb, 0xbd, 0x55, 0x76, 0x98, 0x86, 0xbc,
+    0x65, 0x1d, 0x06, 0xb0, 0xcc, 0x53, 0xb0, 0xf6, 0x3b, 0xce, 0x3c, 0x3e, 0x27, 0xd2, 0x60, 0x4b
+};
+const uint8_t secp256r1Gx[32] ALIGN4 = {
+    0x6b, 0x17, 0xd1, 0xf2, 0xe1, 0x2c, 0x42, 0x47, 0xf8, 0xbc, 0xe6, 0xe5, 0x63, 0xa4, 0x40, 0xf2,
+    0x77, 0x03, 0x7d, 0x81, 0x2d, 0xeb, 0x33, 0xa0, 0xf4, 0xa1, 0x39, 0x45, 0xd8, 0x98, 0xc2, 0x96
+};
+const uint8_t secp256r1Gy[32] ALIGN4 = {
+    0x4f, 0xe3, 0x42, 0xe2, 0xfe, 0x1a, 0x7f, 0x9b, 0x8e, 0xe7, 0xeb, 0x4a, 0x7c, 0x0f, 0x9e, 0x16,
+    0x2b, 0xce, 0x33, 0x57, 0x6b, 0x31, 0x5e, 0xce, 0xcb, 0xb6, 0x40, 0x68, 0x37, 0xbf, 0x51, 0xf5
+};
+const uint8_t secp256r1N[32] ALIGN4 = {
+    0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xbc, 0xe6, 0xfa, 0xad, 0xa7, 0x17, 0x9e, 0x84, 0xf3, 0xb9, 0xca, 0xc2, 0xfc, 0x63, 0x25, 0x51
+};
+const uint8_t secp256r1PrimeN_N[32] ALIGN4 = {
+    0x60, 0xd0, 0x66, 0x33, 0xa9, 0xd6, 0x28, 0x1c, 0x50, 0xfe, 0x77, 0xec, 0xc5, 0x88, 0xc6, 0xf6,
+    0x48, 0xc9, 0x44, 0x08, 0x7d, 0x74, 0xd2, 0xe4, 0xcc, 0xd1, 0xc8, 0xaa, 0xee, 0x00, 0xbc, 0x4f
+};
+const uint8_t secp256r1InvR_N[32] ALIGN4 = {
+    0x60, 0xd0, 0x66, 0x33, 0x49, 0x05, 0xc1, 0xe9, 0x07, 0xf8, 0xb6, 0x04, 0x1e, 0x60, 0x77, 0x25,
+    0xba, 0xde, 0xf3, 0xe2, 0x43, 0x56, 0x6f, 0xaf, 0xce, 0x1b, 0xc8, 0xf7, 0x9c, 0x19, 0x7c, 0x79
+};
+const uint8_t secp256r1PrimeN_P[32] ALIGN4 = {
+    0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01
+};
+const uint8_t secp256r1InvR_P[32] ALIGN4 = {
+    0xff, 0xff, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x03, 0xff, 0xff, 0xff, 0xfd, 0x00, 0x00, 0x00, 0x02,
+    0x00, 0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00
+};
+const uint8_t secp256r1_1[32] ALIGN4 = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01
+};
+const uint8_t secp256r1_BAR2[32] ALIGN4 = {
+    0x00, 0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0xfd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02
+};
+const uint8_t secp256r1_BAR3[32] ALIGN4 = {
+    0x00, 0x00, 0x00, 0x02, 0xff, 0xff, 0xff, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xfd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03
+};
+const uint8_t secp256r1_BAR4[32] ALIGN4 = {
+    0x00, 0x00, 0x00, 0x03, 0xff, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04
+};
+const uint8_t secp256r1_BAR8[32] ALIGN4 = {
+    0x00, 0x00, 0x00, 0x07, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08
+};
+const uint8_t secp256r1_1P1[32] ALIGN4 = {
+    0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02
+};
+const uint8_t secp256r1_1M1[32] ALIGN4 = {
+    0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+const uint8_t secp256r1_Zerox[32] ALIGN4 = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+const uint8_t secp256r1_Zeroy[32] ALIGN4 = {
+    0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01
+};
+const uint8_t secp256r1_Gx[32] ALIGN4 = {
+    0x18, 0x90, 0x5f, 0x76, 0xa5, 0x37, 0x55, 0xc6, 0x79, 0xfb, 0x73, 0x2b, 0x77, 0x62, 0x25, 0x10,
+    0x75, 0xba, 0x95, 0xfc, 0x5f, 0xed, 0xb6, 0x01, 0x79, 0xe7, 0x30, 0xd4, 0x18, 0xa9, 0x14, 0x3c
+};
+const uint8_t secp256r1_Gy[32] ALIGN4 = {
+    0x85, 0x71, 0xff, 0x18, 0x25, 0x88, 0x5d, 0x85, 0xd2, 0xe8, 0x86, 0x88, 0xdd, 0x21, 0xf3, 0x25,
+    0x8b, 0x4a, 0xb8, 0xe4, 0xba, 0x19, 0xe4, 0x5c, 0xdd, 0xf2, 0x53, 0x57, 0xce, 0x95, 0x56, 0x0a
+};
+
+/********************************************** secp256k1 *******************************************/
+const uint8_t secp256k1P[32] ALIGN4 = {
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFC, 0x2F
+};
+const uint8_t secp256k1B[32] ALIGN4 = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07
+};
+const uint8_t secp256k1Gx[32] ALIGN4 = {
+    0x79, 0xBE, 0x66, 0x7E, 0xF9, 0xDC, 0xBB, 0xAC, 0x55, 0xA0, 0x62, 0x95, 0xCE, 0x87, 0x0B, 0x07,
+    0x02, 0x9B, 0xFC, 0xDB, 0x2D, 0xCE, 0x28, 0xD9, 0x59, 0xF2, 0x81, 0x5B, 0x16, 0xF8, 0x17, 0x98
+};
+const uint8_t secp256k1Gy[32] ALIGN4 = {
+    0x4f, 0xe3, 0x42, 0xe2, 0xfe, 0x1a, 0x7f, 0x9b, 0x8e, 0xe7, 0xeb, 0x4a, 0x7c, 0x0f, 0x9e, 0x16,
+    0x2b, 0xce, 0x33, 0x57, 0x6b, 0x31, 0x5e, 0xce, 0xcb, 0xb6, 0x40, 0x68, 0x37, 0xbf, 0x51, 0xf5
+};
+const uint8_t secp256k1N[32] ALIGN4 = {
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE,
+    0xBA, 0xAE, 0xDC, 0xE6, 0xAF, 0x48, 0xA0, 0x3B, 0xBF, 0xD2, 0x5E, 0x8C, 0xD0, 0x36, 0x41, 0x41
+};
+const uint8_t secp256k1PrimeN_N[32] ALIGN4 = {
+    0xd9, 0xe8, 0x89, 0xd, 0x64, 0x94, 0xef, 0x93, 0x89, 0x7f, 0x30, 0xc1, 0x27, 0xcf, 0xab, 0x5e,
+    0x50, 0xa5, 0x1a, 0xc8, 0x34, 0xb9, 0xec, 0x24, 0x4b, 0xd, 0xff, 0x66, 0x55, 0x88, 0xb1, 0x3f
+};
+const uint8_t secp256k1InvR_N[32] ALIGN4 = {
+    0xd9, 0xe8, 0x89, 0xd, 0x64, 0x94, 0xef, 0x93, 0x89, 0x7f, 0x30, 0xc1, 0x27, 0xcf, 0xab, 0x5d,
+    0x3b, 0xbb, 0xd4, 0x56, 0x7f, 0xa5, 0xc, 0x3c, 0x80, 0xfd, 0x22, 0x93, 0x80, 0x97, 0xc0, 0x16
+};
+const uint8_t secp256k1PrimeN_P[32] ALIGN4 = {
+    0xc9, 0xbd, 0x19, 0x5, 0x15, 0x53, 0x83, 0x99, 0x9c, 0x46, 0xc2, 0xc2, 0x95, 0xf2, 0xb7, 0x61,
+    0xbc, 0xb2, 0x23, 0xfe, 0xdc, 0x24, 0xa0, 0x59, 0xd8, 0x38, 0x9, 0x1d, 0xd2, 0x25, 0x35, 0x31
+};
+const uint8_t secp256k1InvR_P[32] ALIGN4 = {
+    0xc9, 0xbd, 0x19, 0x5, 0x15, 0x53, 0x83, 0x99, 0x9c, 0x46, 0xc2, 0xc2, 0x95, 0xf2, 0xb7, 0x61,
+    0xbc, 0xb2, 0x23, 0xfe, 0xdc, 0x24, 0xa0, 0x59, 0xd8, 0x38, 0x9, 0x1d, 0x8, 0x68, 0x19, 0x2a
+};
+const uint8_t secp256k1_1[32] ALIGN4 = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01
+};
+const uint8_t secp256k1_BAR2[32] ALIGN4 = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x07, 0xa2
+};
+const uint8_t secp256k1_BAR3[32] ALIGN4 = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0b, 0x73
+};
+const uint8_t secp256k1_BAR4[32] ALIGN4 = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x0f, 0x44
+};
+const uint8_t secp256k1_BAR8[32] ALIGN4 = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x1e, 0x88
+};
+const uint8_t secp256k1_1P1[32] ALIGN4 = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x03, 0xd2
+};
+const uint8_t secp256k1_1M1[32] ALIGN4 = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x03, 0xd0
+};
+const uint8_t secp256k1_Zerox[32] ALIGN4 = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+const uint8_t secp256k1_Zeroy[32] ALIGN4 = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x03, 0xd1
+};
+const uint8_t secp256k1_Gx[32] ALIGN4 = {
+    0x99, 0x81, 0xe6, 0x43, 0xe9, 0x08, 0x9f, 0x48, 0x97, 0x9f, 0x48, 0xc0, 0x33, 0xfd, 0x12, 0x9c,
+    0x23, 0x1e, 0x29, 0x53, 0x29, 0xbc, 0x66, 0xdb, 0xd7, 0x36, 0x2e, 0x5a, 0x48, 0x7e, 0x20, 0x97
+};
+const uint8_t secp256k1_Gy[32] ALIGN4 = {
+    0xcf, 0x3f, 0x85, 0x1f, 0xd4, 0xa5, 0x82, 0xd6, 0x70, 0xb6, 0xb5, 0x9a, 0xac, 0x19, 0xc1, 0x36,
+    0x8d, 0xfc, 0x5d, 0x5d, 0x1f, 0x1d, 0xc6, 0x4d, 0xb1, 0x5e, 0xa6, 0xd2, 0xd3, 0xdb, 0xab, 0xe2
+};
+
+static BL_Err_Type sec_ecc_basic_parameter_cfg(uint32_t *n, uint32_t *prime_n, uint32_t *invr_n)
+{
+    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)n, ECP_SECP256R1_SIZE / 4, 0);
+    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_NPRIME_N_REG_INDEX, (uint32_t *)prime_n, ECP_SECP256R1_SIZE / 4, 0);
+    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_INVR_N_REG_INDEX, (uint32_t *)invr_n, ECP_SECP256R1_SIZE / 4, 0);
+    return SUCCESS;
+}
+static BL_Err_Type sec_ecc_basic_parameter_init(uint8_t id)
+{
+    if (id >= ECP_TYPE_MAX) {
+        return ERROR;
+    }
+
+    if (id == ECP_SECP256R1) {
+        SEC_ECC_BASIC_PARAM_CFG(secp256r1);
+    } else if (id == ECP_SECP256K1) {
+        SEC_ECC_BASIC_PARAM_CFG(secp256k1);
+    }
+
+    return SUCCESS;
+}
+
+static BL_Err_Type sec_ecc_point_mul_cfg(uint32_t *p, uint32_t *primeN_p, uint32_t *ori_1, uint32_t *bar2,
+                                         uint32_t *bar3, uint32_t *bar4, uint32_t *bar8, uint32_t *bar1p1, uint32_t *bar1m1)
+{
+    Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 0, (uint32_t *)p, ECP_SECP256R1_SIZE / 4, 0);
+    Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 1, (uint32_t *)primeN_p, ECP_SECP256R1_SIZE / 4, 0);
+    Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 8, (uint32_t *)ori_1, ECP_SECP256R1_SIZE / 4, 0);
+    Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 9, (uint32_t *)bar2, ECP_SECP256R1_SIZE / 4, 0);
+    Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 10, (uint32_t *)bar3, ECP_SECP256R1_SIZE / 4, 0);
+    Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 11, (uint32_t *)bar4, ECP_SECP256R1_SIZE / 4, 0);
+    Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 12, (uint32_t *)bar8, ECP_SECP256R1_SIZE / 4, 0);
+    Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 19, (uint32_t *)bar1p1, ECP_SECP256R1_SIZE / 4, 0);
+    Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 20, (uint32_t *)bar1m1, ECP_SECP256R1_SIZE / 4, 0);
+
+    return SUCCESS;
+}
+
+static int sec_ecc_point_mul_init(uint8_t id)
+{
+    if (id >= ECP_TYPE_MAX) {
+        return ERROR;
+    }
+
+    if (id == ECP_SECP256R1) {
+        SEC_ECC_POINT_MUL_PARAM_CFG(secp256r1);
+    } else if (id == ECP_SECP256K1) {
+        SEC_ECC_POINT_MUL_PARAM_CFG(secp256k1);
+    }
+
+    return SUCCESS;
+}
+
+static void sec_ecdsa_point_add_inf_check(uint8_t *pka_p1_eq_inf, uint8_t *pka_p2_eq_inf)
+{
+    uint8_t res[4];
+
+    /* index 2:BAR_Zero_x
+     * index 3:BAR_Zero_y
+     * index 4:BAR_Zero_z
+     * index 5:BAR_G_x
+     * index 6:BAR_G_y
+     * index 7:BAR_G_z
+     * index 8:1
+     * index 9:2
+     * index 10:3
+     * index 11:4
+     * index 12:8
+     * index 19:1P1
+     * index 20:1m1*/
+
+    //cout = 1 if X1 = 0
+    Sec_Eng_PKA_LCMP(res, 3, 2, 3, 8); //s0 < s1 => cout = 1
+    //cout = 1 if Y1 < Bar_1p1
+    Sec_Eng_PKA_LCMP(res + 1, 3, 3, 3, 19);
+    //cout=1 if Y1 > Bar_1m1
+    Sec_Eng_PKA_LCMP(res + 2, 3, 20, 3, 3);
+    //cout =1 if Z1 = 0
+    Sec_Eng_PKA_LCMP(res + 3, 3, 4, 3, 8);
+    *pka_p1_eq_inf = res[0] & res[1] & res[2] & res[3];
+
+    //cout = 1 if X2 = 0
+    Sec_Eng_PKA_LCMP(res, 3, 5, 3, 8);
+    // cout = 1 if Y2 < Bar_1p1
+    Sec_Eng_PKA_LCMP(res + 1, 3, 6, 3, 19);
+    //cout = 1 if Y2 > Bar_1m1
+    Sec_Eng_PKA_LCMP(res + 2, 3, 20, 3, 6);
+    //cout = 1 if Z2 = 0
+    Sec_Eng_PKA_LCMP(res + 3, 3, 7, 3, 8);
+    *pka_p2_eq_inf = res[0] & res[1] & res[2] & res[3];
+}
+
+static void sec_ecdsa_copy_x2_to_x1(uint8_t id)
+{
+    //X2->X1
+    Sec_Eng_PKA_Move_Data(3, 2, 3, 5, 0);
+    //Y2->Y1
+    Sec_Eng_PKA_Move_Data(3, 3, 3, 6, 0);
+    //Z2->Z1
+    Sec_Eng_PKA_Move_Data(3, 4, 3, 7, 1); //Caution!!! wait movdat ready to execute next command
+}
+
+static void sec_ecdsa_point_add(uint8_t id)
+{
+    /* index 2:BAR_Zero_x
+     * index 3:BAR_Zero_y
+     * index 4:BAR_Zero_z
+     * index 5:BAR_G_x
+     * index 6:BAR_G_y
+     * index 7:BAR_G_z
+     * index 8:1
+     * index 9:2
+     * index 10:3
+     * index 11:4
+     * index 12:8
+     * index 19:1P1
+     * index 20:1m1*/
+
+    //U1 = Y2*Z1
+    //PKA_MMUL(0,3,13,3, 6,3, 4,3,0);//d_reg_type,d_reg_idx,s0_reg_type,s0_reg_idx,s1_reg_type,s1_reg_idx,s2_reg_type,s2_reg_idx
+    Sec_Eng_PKA_MMUL(3, 13, 3, 6, 3, 4, 3, 0, 0);
+
+    //U2 = Y1*Z2
+    //PKA_MMUL(0,3,14,3, 3,3, 7,3,0);
+    Sec_Eng_PKA_MMUL(3, 14, 3, 3, 3, 7, 3, 0, 0);
+
+    //V1 = X2*Z1
+    //PKA_MMUL(0,3,15,3, 5,3, 4,3,0);
+    Sec_Eng_PKA_MMUL(3, 15, 3, 5, 3, 4, 3, 0, 0);
+
+    //V2 = X1*Z2
+    //PKA_MMUL(0,3,16,3, 2,3, 7,3,0);
+    Sec_Eng_PKA_MMUL(3, 16, 3, 2, 3, 7, 3, 0, 0);
+
+    //U = U1-U2
+    //PKA_MSUB(0,3,13,3,13,3,14,3,0);
+    Sec_Eng_PKA_MSUB(3, 13, 3, 13, 3, 14, 3, 0, 0);
+
+    //V = V1-V2
+    //PKA_MSUB(0,3,15,3,15,3,16,3,0);
+    Sec_Eng_PKA_MSUB(3, 15, 3, 15, 3, 16, 3, 0, 0);
+
+    //W = Z1*Z2
+    //PKA_MMUL(0,3, 2,3, 4,3, 7,3,0);
+    Sec_Eng_PKA_MMUL(3, 2, 3, 4, 3, 7, 3, 0, 0);
+
+    //V^2
+    //PKA_MMUL(0,3, 3,3,15,3,15,3,0);
+    Sec_Eng_PKA_MMUL(3, 3, 3, 15, 3, 15, 3, 0, 0);
+
+    //V^3
+    //PKA_MMUL(0,3, 4,3, 3,3,15,3,0);
+    Sec_Eng_PKA_MMUL(3, 4, 3, 3, 3, 15, 3, 0, 0);
+
+    //U^2
+    //PKA_MMUL(0,3,17,3,13,3,13,3,0);
+    Sec_Eng_PKA_MMUL(3, 17, 3, 13, 3, 13, 3, 0, 0);
+
+    //U^2*W
+    //PKA_MMUL(0,3,17,3,17,3, 2,3,0);
+    Sec_Eng_PKA_MMUL(3, 17, 3, 17, 3, 2, 3, 0, 0);
+
+    //U^2*W-V^3
+    //PKA_MSUB(0,3,17,3,17,3, 4,3,0);
+    Sec_Eng_PKA_MSUB(3, 17, 3, 17, 3, 4, 3, 0, 0);
+
+    //2*V^2
+    //PKA_MMUL(0,3,18,3, 9,3, 3,3,0);
+    Sec_Eng_PKA_MMUL(3, 18, 3, 9, 3, 3, 3, 0, 0);
+
+    //2*V^2*V2
+    //PKA_MMUL(0,3,18,3,18,3,16,3,0);
+    Sec_Eng_PKA_MMUL(3, 18, 3, 18, 3, 16, 3, 0, 0);
+
+    //A = U^2*W-V^3-2*V^2*V2
+    //PKA_MSUB(0,3,18,3,17,3,18,3,0);
+    Sec_Eng_PKA_MSUB(3, 18, 3, 17, 3, 18, 3, 0, 0);
+
+    //V^2*V2
+    //PKA_MMUL(0,3, 3,3, 3,3,16,3,0);
+    Sec_Eng_PKA_MMUL(3, 3, 3, 3, 3, 16, 3, 0, 0);
+
+    //V^3*U2
+    //PKA_MMUL(0,3,14,3, 4,3,14,3,0);
+    Sec_Eng_PKA_MMUL(3, 14, 3, 4, 3, 14, 3, 0, 0);
+
+    //Z3 = V^3*W
+    //PKA_MMUL(0,3, 4,3, 4,3, 2,3,0);
+    Sec_Eng_PKA_MMUL(3, 4, 3, 4, 3, 2, 3, 0, 0);
+
+    //X3 = V*A
+    //PKA_MMUL(0,3, 2,3,15,3,18,3,0);
+    Sec_Eng_PKA_MMUL(3, 2, 3, 15, 3, 18, 3, 0, 0);
+
+    //V^2*V2-A
+    //PKA_MSUB(0,3, 3,3, 3,3,18,3,0);
+    Sec_Eng_PKA_MSUB(3, 3, 3, 3, 3, 18, 3, 0, 0);
+
+    //U*(V^2*V2-A)
+    //PKA_MMUL(0,3, 3,3,13,3, 3,3,0);
+    Sec_Eng_PKA_MMUL(3, 3, 3, 13, 3, 3, 3, 0, 0);
+
+    //Y3 = U*(V^2*V2-A)-V^3*U2
+    //PKA_MSUB(1,3, 3,3, 3,3,14,3,0);
+    Sec_Eng_PKA_MSUB(3, 3, 3, 3, 3, 14, 3, 0, 1);
+}
+/**
+ * @brief calculate secp256r1's W
+ *
+ * @note index 13:W = 3X^2-3Z^2
+ */
+static void sec_ecdsa_cal_secp256r1_w(void)
+{
+    //X1^2
+    //PKA_MMUL(0,3,13,3, 5,3, 5,3,0);//d_reg_type,d_reg_idx,s0_reg_type,s0_reg_idx,s1_reg_type,s1_reg_idx,s2_reg_type,s2_reg_idx
+    Sec_Eng_PKA_MMUL(3, 13, 3, 5, 3, 5, 3, 0, 0);
+
+    //Z1^2
+    //PKA_MMUL(0,3,14,3, 7,3, 7,3,0);
+    Sec_Eng_PKA_MMUL(3, 14, 3, 7, 3, 7, 3, 0, 0);
+
+    //X1^2-Z1^2
+    //PKA_MSUB(0,3,13,3,13,3,14,3,0);
+    Sec_Eng_PKA_MSUB(3, 13, 3, 13, 3, 14, 3, 0, 0);
+
+    //W = 3*(X1^2-Z1^2)
+    //PKA_MMUL(0,3,13,3,10,3,13,3,0);
+    Sec_Eng_PKA_MMUL(3, 13, 3, 10, 3, 13, 3, 0, 0);
+}
+
+/**
+ * @brief calculate secp256k1's W
+ *
+ * @note index 13:W = 3X^2
+ */
+static void sec_ecdsa_cal_secp256k1_w(void)
+{
+    //X1^2
+    Sec_Eng_PKA_MMUL(3, 13, 3, 5, 3, 5, 3, 0, 0);
+
+    //W = 3* (X1^2)
+    Sec_Eng_PKA_MMUL(3, 13, 3, 10, 3, 13, 3, 0, 0);
+}
+
+static BL_Err_Type sec_ecdsa_point_double(sec_ecp_type id)
+{
+    /* index 2:BAR_Zero_x
+     * index 3:BAR_Zero_y
+     * index 4:BAR_Zero_z
+     * index 5:BAR_G_x
+     * index 6:BAR_G_y
+     * index 7:BAR_G_z
+     * index 8:1
+     * index 9:2
+     * index 10:3
+     * index 11:4
+     * index 12:8
+     * index 19:1P1
+     * index 20:1m1*/
+
+    if (id >= ECP_TYPE_MAX) {
+        return ERROR;
+    }
+
+    if (id == ECP_SECP256R1) {
+        sec_ecdsa_cal_secp256r1_w();
+    } else if (id == ECP_SECP256K1) {
+        sec_ecdsa_cal_secp256k1_w();
+    }
+
+    //S = Y1*Z1
+    //PKA_MMUL(0,3,14,3, 6,3, 7,3,0);
+    Sec_Eng_PKA_MMUL(3, 14, 3, 6, 3, 7, 3, 0, 0);
+
+    //X1*Y1
+    //PKA_MMUL(0,3,15,3, 5,3, 6,3,0);
+    Sec_Eng_PKA_MMUL(3, 15, 3, 5, 3, 6, 3, 0, 0);
+
+    //W^2
+    //PKA_MMUL(0,3, 7,3,13,3,13,3,0);
+    Sec_Eng_PKA_MMUL(3, 7, 3, 13, 3, 13, 3, 0, 0);
+
+    //B = X1*Y1*S
+    //PKA_MMUL(0,3,15,3,15,3,14,3,0);
+    Sec_Eng_PKA_MMUL(3, 15, 3, 15, 3, 14, 3, 0, 0);
+
+    //8*B
+    //PKA_MMUL(0,3, 5,3,12,3,15,3,0);
+    Sec_Eng_PKA_MMUL(3, 5, 3, 12, 3, 15, 3, 0, 0);
+
+    //H = W^2-8*B
+    //PKA_MSUB(0,3, 7,3, 7,3, 5,3,0);
+    Sec_Eng_PKA_MSUB(3, 7, 3, 7, 3, 5, 3, 0, 0);
+
+    //2*H
+    //PKA_MMUL(0,3, 5,3, 9,3, 7,3,0);
+    Sec_Eng_PKA_MMUL(3, 5, 3, 9, 3, 7, 3, 0, 0);
+
+    //X2 = 2*H*S
+    //PKA_MMUL(0,3, 5,3, 5,3,14,3,0);
+    Sec_Eng_PKA_MMUL(3, 5, 3, 5, 3, 14, 3, 0, 0);
+
+    //4*B
+    //PKA_MMUL(0,3,15,3,11,3,15,3,0);
+    Sec_Eng_PKA_MMUL(3, 15, 3, 11, 3, 15, 3, 0, 0);
+
+    //S^2
+    //PKA_MMUL(0,3,16,3,14,3,14,3,0);
+    Sec_Eng_PKA_MMUL(3, 16, 3, 14, 3, 14, 3, 0, 0);
+
+    //4*B-H
+    //PKA_MSUB(0,3,15,3,15,3, 7,3,0);
+    Sec_Eng_PKA_MSUB(3, 15, 3, 15, 3, 7, 3, 0, 0);
+
+    //Y1^2
+    //PKA_MMUL(0,3, 6,3, 6,3, 6,3,0);
+    Sec_Eng_PKA_MMUL(3, 6, 3, 6, 3, 6, 3, 0, 0);
+
+    //W*(4*B-H)
+    //PKA_MMUL(0,3,15,3,15,3,13,3,0);
+    Sec_Eng_PKA_MMUL(3, 15, 3, 15, 3, 13, 3, 0, 0);
+
+    //8*Y1^2
+    //PKA_MMUL(0,3, 6,3,12,3, 6,3,0);
+    Sec_Eng_PKA_MMUL(3, 6, 3, 12, 3, 6, 3, 0, 0);
+
+    //8*Y1^2*S^2
+    //PKA_MMUL(0,3, 6,3, 6,3,16,3,0);
+    Sec_Eng_PKA_MMUL(3, 6, 3, 6, 3, 16, 3, 0, 0);
+
+    //Y2 = W*(4*B-H)-8*Y1^2*S^2
+    //PKA_MSUB(0,3, 6,3,15,3, 6,3,0);
+    Sec_Eng_PKA_MSUB(3, 6, 3, 15, 3, 6, 3, 0, 0);
+
+    //S^3
+    //PKA_MMUL(0,3, 7,3,14,3,16,3,0);
+    Sec_Eng_PKA_MMUL(3, 7, 3, 14, 3, 16, 3, 0, 0);
+
+    //Z2 = 8*S^3
+    //PKA_MMUL(1,3, 7,3,12,3, 7,3,0);
+    Sec_Eng_PKA_MMUL(3, 7, 3, 12, 3, 7, 3, 0, 1);
+
+    return SUCCESS;
+}
+#ifdef ECDSA_DBG_DETAIL
+static void sec_ecdsa_dump_temp_result()
+{
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
+    MSG("2=\r\n");
+    bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
+    MSG("3=\r\n");
+    bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
+    MSG("4=\r\n");
+    bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
+
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
+    MSG("5=\r\n");
+    bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
+    MSG("6=\r\n");
+    bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 7, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
+    MSG("7=\r\n");
+    bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
+}
+#endif
+static int sec_ecdsa_verify_point_mul(uint8_t id, const uint32_t *m)
+{
+    uint32_t i, j, k;
+    uint32_t tmp;
+    uint32_t isOne = 0;
+    uint8_t *p = (uint8_t *)m;
+    uint8_t pka_p1_eq_inf, pka_p2_eq_inf;
+
+    /* Remove zeros bytes*/
+    k = 0;
+
+    while (p[k] == 0 && k < 31) {
+        k++;
+    }
+
+    i = 31;
+
+    for (; i >= k; i--) {
+        tmp = p[i];
+        j = 0;
+
+        for (j = 0; j < 8; j++) {
+            isOne = tmp & (1 << j);
+
+            if (isOne) {
+                sec_ecdsa_point_add_inf_check(&pka_p1_eq_inf, &pka_p2_eq_inf);
+
+                if (pka_p1_eq_inf == 1 && pka_p2_eq_inf == 0) {
+                    //sum = X2
+                    sec_ecdsa_copy_x2_to_x1(id);
+#ifdef ECDSA_DBG_DETAIL
+                    MSG("sum = X2\r\n");
+                    sec_ecdsa_dump_temp_result();
+#endif
+                } else if (pka_p1_eq_inf == 0 && pka_p2_eq_inf == 1) {
+                    //sum = X1
+                    //MSG("sum = X1\r\n");
+                } else if (pka_p1_eq_inf == 0 && pka_p2_eq_inf == 0) {
+                    //sum = X1 + X2
+                    sec_ecdsa_point_add(id);
+#ifdef ECDSA_DBG_DETAIL
+                    MSG("sum = X1+X2\r\n");
+                    sec_ecdsa_dump_temp_result();
+#endif
+                } else {
+                    //MSG("Error! infinite point + infinite point\r\n");
+                    return -1;
+                }
+            }
+
+            sec_ecdsa_point_double(id);
+#ifdef ECDSA_DBG_DETAIL
+            sec_ecdsa_dump_temp_result();
+#endif
+        }
+
+        if (i == 0) {
+            break;
+        }
+    }
+
+    return 0;
+}
+
+/*cal d*G if pkX(pky)==NULL
+ * cal d(bG) if pkX(pky)!=NULL */
+static int32_t sec_ecdh_get_scalar_point(uint8_t id, const uint32_t *pkX, const uint32_t *pkY, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy)
+{
+#ifdef ECDSA_DBG
+    uint32_t pk_z[8];
+#endif
+
+    if (id >= ECP_TYPE_MAX) {
+        return ERROR;
+    }
+
+    /* Pointer check */
+    if (private_key == NULL) {
+        return -1;
+    }
+
+    Sec_Eng_PKA_Reset();
+    Sec_Eng_PKA_BigEndian_Enable();
+
+    sec_ecc_basic_parameter_init(id);
+
+    //Clear D[7]
+    //PKA_CREG(1,4, 7,0);
+    Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE, 7, ECP_SECP256R1_SIZE / 4, 1);
+
+    sec_ecc_point_mul_init(id);
+
+    if (id == ECP_SECP256R1) {
+        //X1
+        //PKA_CTREG(3, 2,8,bar_Zero_x);
+        Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256r1_Zerox, ECP_SECP256R1_SIZE / 4, 0);
+        //Y1
+        //PKA_CTREG(3, 3,8,bar_Zero_y);
+        Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256r1_Zeroy, ECP_SECP256R1_SIZE / 4, 0);
+    } else if (id == ECP_SECP256K1) {
+        //X1
+        Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256k1_Zerox, ECP_SECP256R1_SIZE / 4, 0);
+        //Y1
+        Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256k1_Zeroy, ECP_SECP256R1_SIZE / 4, 0);
+    }
+    //Z1
+    //PKA_CTREG(3, 4,8,bar_Zero_z);
+    //PKA_MOVDAT(1,3, 4,3, 2);
+    Sec_Eng_PKA_Move_Data(3, 4, 3, 2, 1);
+
+    if (pkX == NULL) {
+        if (id == ECP_SECP256R1) {
+            //X2
+            //PKA_CTREG(3, 5,8,bar_G_x);
+            Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)secp256r1_Gx, ECP_SECP256R1_SIZE / 4, 0);
+            //Y2
+            //PKA_CTREG(3, 6,8,bar_G_y);
+            Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1_Gy, ECP_SECP256R1_SIZE / 4, 0);
+        } else if (id == ECP_SECP256K1) {
+            //X2
+            Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)secp256k1_Gx, ECP_SECP256R1_SIZE / 4, 0);
+            //Y2
+            Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256k1_Gy, ECP_SECP256R1_SIZE / 4, 0);
+        }
+    } else {
+        /* chaneg peer's public key to mont domain*/
+        //PUB_x
+        //PKA_CTREG(3, 5,8,PUB_x);
+        Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pkX, ECP_SECP256R1_SIZE / 4, 0);
+        //bar_pub_x
+        //PKA_GF2MONT(3, 5,3, 5);
+        /* Change s to Mont domain,remember to clear temp register and index 0 is P256*/
+        /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/
+        Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1);
+        Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1);
+        Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, 256,
+                            ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);
+#ifdef ECDSA_DBG
+        Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
+        MSG("PK.x in Mont:\r\n");
+        bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
+#endif
+
+        //PUB_y
+        //PKA_CTREG(3, 6,8,PUB_y);
+        Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)pkY, ECP_SECP256R1_SIZE / 4, 0);
+        //bar_pub_y
+        //PKA_GF2MONT(3, 6,3, 6);
+        Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1);
+        Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1);
+        Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 6, 256,
+                            ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);
+#ifdef ECDSA_DBG
+        Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
+        MSG("PK.y in Mont:\r\n");
+        bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
+#endif
+    }
+
+    //Z2
+    //PKA_CTREG(3, 7,8,bar_G_z);
+    //PKA_MOVDAT(1,3, 7,3, 3);
+    Sec_Eng_PKA_Move_Data(3, 7, 3, 3, 1);
+    /* Clear temp register since it's used in point-mul*/
+    Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE, 7, ECP_SECP256R1_SIZE / 4, 1);
+
+    sec_ecdsa_verify_point_mul(id, private_key);
+    //get bar_u1_x
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pRx, ECP_SECP256R1_SIZE / 4);
+#ifdef ECDSA_DBG
+    MSG("bar_u1_x\r\n");
+    bflb_platform_dump(pRx, ECP_SECP256R1_SIZE);
+#endif
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pRy, ECP_SECP256R1_SIZE / 4);
+#ifdef ECDSA_DBG
+    MSG("bar_u1_y\r\n");
+    bflb_platform_dump(pRy, ECP_SECP256R1_SIZE);
+#endif
+#ifdef ECDSA_DBG
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)pk_z, ECP_SECP256R1_SIZE / 4);
+    MSG("bar_u1_z\r\n");
+    bflb_platform_dump(pk_z, ECP_SECP256R1_SIZE);
+#endif
+
+    //get R.x
+    //R.z ^ -1
+    Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_REG_TYPE, 0, 1);
+    if (id == ECP_SECP256R1) {
+        //inv_r
+        //PKA_CTREG(3, 6,8,inv_r);
+        Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1InvR_P, ECP_SECP256R1_SIZE / 4, 0);
+    } else if (id == ECP_SECP256K1) {
+        Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256k1InvR_P, ECP_SECP256R1_SIZE / 4, 0);
+    }
+    //R.z ^ -1
+    Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1);
+    Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1);
+    //PKA_MONT2GF(3, 5,3, 5,3, 6);
+    Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6,
+                        ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);
+
+    //R.x (Montgomery to GF)
+    //PKA_MONT2GF(3, 6,3, 2,3, 6);
+    Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 6,
+                        ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);
+
+    //R.x (GF to Affine domain)
+    //PKA_MONT2GF(3, 2,3, 5,3, 6);
+    Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6,
+                        ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pRx, ECP_SECP256R1_SIZE / 4);
+#ifdef ECDSA_DBG
+    MSG("R.x=\r\n");
+    bflb_platform_dump(pRx, ECP_SECP256R1_SIZE);
+#endif
+    if (id == ECP_SECP256R1) {
+        Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0);
+    } else if (id == ECP_SECP256K1) {
+        Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256k1N, ECP_SECP256R1_SIZE / 4, 0);
+    }
+
+    Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 2,
+                     ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1);
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pRx, ECP_SECP256R1_SIZE / 4);
+#ifdef ECDSA_DBG
+    MSG("R.x%n=\r\n");
+    bflb_platform_dump(pRx, ECP_SECP256R1_SIZE);
+#endif
+    if (id == ECP_SECP256R1) {
+        /*after %n,re write p*/
+        Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 0, (uint32_t *)secp256r1P, ECP_SECP256R1_SIZE / 4, 0);
+    } else if (id == ECP_SECP256K1) {
+        Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 0, (uint32_t *)secp256k1P, ECP_SECP256R1_SIZE / 4, 0);
+    }
+
+    //get R.y
+    //R.z ^ -1
+    Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_REG_TYPE, 0, 1);
+    //inv_r
+    //PKA_CTREG(3, 6,8,inv_r);
+    if (id == ECP_SECP256R1) {
+        Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1InvR_P, ECP_SECP256R1_SIZE / 4, 0);
+    } else if (id == ECP_SECP256K1) {
+        Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256k1InvR_P, ECP_SECP256R1_SIZE / 4, 0);
+    }
+    //R.z ^ -1
+    Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1);
+    Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1);
+    //PKA_MONT2GF(3, 5,3, 5,3, 6);
+    Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6,
+                        ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);
+    //R.x (Montgomery to GF)
+    //PKA_MONT2GF(3, 6,3, 2,3, 6);
+    Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 3, ECP_SECP256R1_REG_TYPE, 6,
+                        ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);
+
+    //R.x (GF to Affine domain)
+    //PKA_MONT2GF(3, 2,3, 5,3, 6);
+    Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 3, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6,
+                        ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pRy, ECP_SECP256R1_SIZE / 4);
+#ifdef ECDSA_DBG
+    MSG("R.y=\r\n");
+    bflb_platform_dump(pRy, ECP_SECP256R1_SIZE);
+#endif
+    if (id == ECP_SECP256R1) {
+        Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0);
+    } else if (id == ECP_SECP256K1) {
+        Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256k1N, ECP_SECP256R1_SIZE / 4, 0);
+    }
+    Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, 3, ECP_SECP256R1_REG_TYPE, 3,
+                     ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1);
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pRy, ECP_SECP256R1_SIZE / 4);
+#ifdef ECDSA_DBG
+    MSG("R.y%n=\r\n");
+    bflb_platform_dump(pRy, ECP_SECP256R1_SIZE);
+#endif
+    return 0;
+}
+
+static int32_t sec_ecc_is_zero(uint8_t *a, uint32_t len)
+{
+    uint32_t i = 0;
+
+    for (i = 0; i < len; i++) {
+        if (a[i] != 0) {
+            return 0;
+        }
+    }
+
+    return 1;
+}
+
+static int32_t sec_ecc_cmp(uint8_t *a, uint8_t *b, uint32_t len)
+{
+    uint32_t i = 0, j = 0;
+
+    for (i = 0; i < len; i++) {
+        if (a[i] != 0) {
+            break;
+        }
+    }
+
+    for (j = 0; j < len; j++) {
+        if (b[j] != 0) {
+            break;
+        }
+    }
+
+    if (i == len && j == len) {
+        return (0);
+    }
+
+    if (i > j) {
+        return (-1);
+    }
+
+    if (j > i) {
+        return (1);
+    }
+
+    for (; i < len; i++) {
+        if (a[i] > b[i]) {
+            return (1);
+        }
+
+        if (a[i] < b[i]) {
+            return (-1);
+        }
+    }
+
+    return 0;
+}
+
+int sec_ecdsa_init(sec_ecdsa_handle_t *handle, sec_ecp_type id)
+{
+    Sec_Eng_PKA_Reset();
+    Sec_Eng_PKA_BigEndian_Enable();
+    Sec_Eng_Trng_Enable();
+
+    handle->ecpId = id;
+
+    return 0;
+}
+
+int sec_ecdsa_deinit(sec_ecdsa_handle_t *handle)
+{
+    Sec_Eng_PKA_Reset();
+
+    return 0;
+}
+
+int sec_ecdsa_verify(sec_ecdsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *r, const uint32_t *s)
+{
+    uint32_t bar_u1_x[8];
+    uint32_t bar_u1_y[8];
+    uint32_t bar_u1_z[8];
+    uint32_t bar_u2_x[8];
+    uint32_t bar_u2_y[8];
+    uint32_t bar_u2_z[8];
+    uint32_t pka_u1[8] = { 0 };
+    uint32_t pka_u2[8] = { 0 };
+    uint32_t i = 0;
+
+    /* Pointer check */
+    if (hash == NULL || handle->publicKeyx == NULL || handle->publicKeyy == NULL || r == NULL || s == NULL) {
+        return -1;
+    }
+
+    Sec_Eng_PKA_Reset();
+    Sec_Eng_PKA_BigEndian_Enable();
+
+    /*Step 0: make sure r and s are in range 1..n-1*/
+
+    /* r and s should not be 0*/
+    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)r, ECP_SECP256R1_SIZE / 4, 0);
+    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 8, (uint32_t *)secp256r1_1, ECP_SECP256R1_SIZE / 4, 0);
+    //cout = 1 if r = 0
+    Sec_Eng_PKA_LCMP((uint8_t *)&i, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, 8); //s0 < s1 => cout = 1
+
+    if (i == 1) {
+        return -1;
+    }
+
+    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)s, ECP_SECP256R1_SIZE / 4, 0);
+    //cout = 1 if r = 0
+    Sec_Eng_PKA_LCMP((uint8_t *)&i, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, 8); //s0 < s1 => cout = 1
+
+    if (i == 1) {
+        return -1;
+    }
+
+    sec_ecc_basic_parameter_init(handle->ecpId);
+
+    /* r and s should not be 0*/
+    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)r, ECP_SECP256R1_SIZE / 4, 0);
+    //cout = 1 if r < N
+    Sec_Eng_PKA_LCMP((uint8_t *)&i, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX);
+
+    if (i != 1) {
+        return -1;
+    }
+
+    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)s, ECP_SECP256R1_SIZE / 4, 0);
+    //cout = 1 if r < N
+    Sec_Eng_PKA_LCMP((uint8_t *)&i, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX);
+
+    if (i != 1) {
+        return -1;
+    }
+
+    /* u1 = e / s mod n, u2 = r / s mod n
+     * R = u1 G + u2 Q*/
+
+    /* Step1: Get S^-1*/
+    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)s, ECP_SECP256R1_SIZE / 4, 0);
+    /* Change s to Mont domain */
+    /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/
+    Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1);
+    Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1);
+    Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, 256,
+                        ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX);
+#ifdef ECDSA_DBG
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
+    MSG("GF2Mont Result of s:\r\n");
+    bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
+#endif
+
+    /* Get S^-1 in Mont domain */
+    Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_BAR_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX,
+                     ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1);
+#ifdef ECDSA_DBG
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_BAR_S_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
+    MSG("s^-1 in Mont:\r\n");
+    bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
+#endif
+
+    /* Change S^-1 into GF domain,now  ECP_SECP256R1_S_REG_INDEX store s^-1*/
+    /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/
+    Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_BAR_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_INVR_N_REG_INDEX,
+                        ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX);
+#ifdef ECDSA_DBG
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
+    MSG("S^-1:\r\n");
+    bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
+#endif
+
+    /* Step2: Get u1*/
+    //u1=hash(e)*s^-1;
+    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_HASH_REG_INDEX, (uint32_t *)hash, ECP_SECP256R1_SIZE / 4, 0);
+    Sec_Eng_PKA_LMUL(ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_HASH_REG_INDEX,
+                     ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, 0);
+    Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_U1_REG_INDEX, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX,
+                     ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1);
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_U1_REG_INDEX, (uint32_t *)pka_u1, ECP_SECP256R1_SIZE / 4);
+#ifdef ECDSA_DBG
+    MSG("u1:\r\n");
+    bflb_platform_dump(pka_u1, ECP_SECP256R1_SIZE);
+#endif
+
+    /* Step3: Get u2*/
+    //u2=r*s^-1;
+    // use hash and u1 temp register
+    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_HASH_REG_INDEX, (uint32_t *)r, ECP_SECP256R1_SIZE / 4, 0);
+    Sec_Eng_PKA_LMUL(ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_HASH_REG_INDEX,
+                     ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, 0);
+    Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_U1_REG_INDEX, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX,
+                     ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1);
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_U1_REG_INDEX, (uint32_t *)pka_u2, ECP_SECP256R1_SIZE / 4);
+#ifdef ECDSA_DBG
+    MSG("u2:\r\n");
+    bflb_platform_dump(pka_u2, ECP_SECP256R1_SIZE);
+#endif
+
+    /* Step4: Get u1*G*/
+
+    //Clear D[7]
+    //PKA_CREG(1,4, 7,0);
+    Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE, 7, ECP_SECP256R1_SIZE / 4, 1);
+
+    sec_ecc_point_mul_init(handle->ecpId);
+
+    //X1
+    //PKA_CTREG(3, 2,8,bar_Zero_x);
+    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256r1_Zerox, ECP_SECP256R1_SIZE / 4, 0);
+    //Y1
+    //PKA_CTREG(3, 3,8,bar_Zero_y);
+    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256r1_Zeroy, ECP_SECP256R1_SIZE / 4, 0);
+    //Z1
+    //PKA_CTREG(3, 4,8,bar_Zero_z);
+    //PKA_MOVDAT(1,3, 4,3, 2);
+    Sec_Eng_PKA_Move_Data(3, 4, 3, 2, 1);
+
+    //X2
+    //PKA_CTREG(3, 5,8,bar_G_x);
+    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)secp256r1_Gx, ECP_SECP256R1_SIZE / 4, 0);
+    //Y2
+    //PKA_CTREG(3, 6,8,bar_G_y);
+    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1_Gy, ECP_SECP256R1_SIZE / 4, 0);
+    //Z2
+    //PKA_CTREG(3, 7,8,bar_G_z);
+    //PKA_MOVDAT(1,3, 7,3, 3);
+    Sec_Eng_PKA_Move_Data(3, 7, 3, 3, 1);
+
+    sec_ecdsa_verify_point_mul(handle->ecpId, pka_u1);
+    //get bar_u1_x
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)bar_u1_x, ECP_SECP256R1_SIZE / 4);
+#ifdef ECDSA_DBG
+    MSG("bar_u1_x\r\n");
+    bflb_platform_dump(bar_u1_x, ECP_SECP256R1_SIZE);
+#endif
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)bar_u1_y, ECP_SECP256R1_SIZE / 4);
+#ifdef ECDSA_DBG
+    MSG("bar_u1_y\r\n");
+    bflb_platform_dump(bar_u1_y, ECP_SECP256R1_SIZE);
+#endif
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)bar_u1_z, ECP_SECP256R1_SIZE / 4);
+#ifdef ECDSA_DBG
+    MSG("bar_u1_z\r\n");
+    bflb_platform_dump(bar_u1_z, ECP_SECP256R1_SIZE);
+#endif
+
+    /* Step4: Get u2*Q*/
+    //X1
+    //PKA_CTREG(3, 2,8,bar_Zero_x);
+    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256r1_Zerox, ECP_SECP256R1_SIZE / 4, 0);
+    //Y1
+    //PKA_CTREG(3, 3,8,bar_Zero_y);
+    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256r1_Zeroy, ECP_SECP256R1_SIZE / 4, 0);
+    //Z1
+    //PKA_CTREG(3, 4,8,bar_Zero_z);
+    //PKA_MOVDAT(1,3, 4,3, 2);
+    Sec_Eng_PKA_Move_Data(3, 4, 3, 2, 1);
+
+    //PUB_x
+    //PKA_CTREG(3, 5,8,PUB_x);
+    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)handle->publicKeyx, ECP_SECP256R1_SIZE / 4, 0);
+    //bar_pub_x
+    //PKA_GF2MONT(3, 5,3, 5);
+    /* Change s to Mont domain,remember to clear temp register and index 0 is P256*/
+    /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/
+    Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1);
+    Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1);
+    Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, 256,
+                        ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);
+#ifdef ECDSA_DBG
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
+    MSG("PK.x in Mont:\r\n");
+    bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
+#endif
+
+    //PUB_y
+    //PKA_CTREG(3, 6,8,PUB_y);
+    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)handle->publicKeyy, ECP_SECP256R1_SIZE / 4, 0);
+    //bar_pub_y
+    //PKA_GF2MONT(3, 6,3, 6);
+    Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1);
+    Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1);
+    Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 6, 256,
+                        ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);
+#ifdef ECDSA_DBG
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
+    MSG("PK.y in Mont:\r\n");
+    bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
+#endif
+
+    //bar_pub_z
+    //PKA_CTREG(3, 7,8,PUB_z);
+    //PKA_MOVDAT(1,3, 7,3, 3);
+    Sec_Eng_PKA_Move_Data(3, 7, 3, 3, 1);
+
+    /* Clear temp register since it's used in point-mul*/
+    Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE, 7, ECP_SECP256R1_SIZE / 4, 1);
+
+    sec_ecdsa_verify_point_mul(handle->ecpId, pka_u2);
+    //get bar_u1_x
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)bar_u2_x, ECP_SECP256R1_SIZE / 4);
+#ifdef ECDSA_DBG
+    MSG("bar_u2_x\r\n");
+    bflb_platform_dump(bar_u2_x, ECP_SECP256R1_SIZE);
+#endif
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)bar_u2_y, ECP_SECP256R1_SIZE / 4);
+#ifdef ECDSA_DBG
+    MSG("bar_u2_y\r\n");
+    bflb_platform_dump(bar_u2_y, ECP_SECP256R1_SIZE);
+#endif
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)bar_u2_z, ECP_SECP256R1_SIZE / 4);
+#ifdef ECDSA_DBG
+    MSG("bar_u2_z\r\n");
+    bflb_platform_dump(bar_u2_z, ECP_SECP256R1_SIZE);
+#endif
+
+    /* Step5: Get u1*G+u2*Q*/
+    //move bar_u2_x
+    //PKA_MOVDAT(0,3, 5,3, 2);
+    Sec_Eng_PKA_Move_Data(3, 5, 3, 2, 0);
+    //move bar_u2_y
+    //PKA_MOVDAT(0,3, 6,3, 3);
+    Sec_Eng_PKA_Move_Data(3, 6, 3, 3, 0);
+    //move bar_u2_z
+    //PKA_MOVDAT(1,3, 7,3, 4);
+    Sec_Eng_PKA_Move_Data(3, 7, 3, 4, 1);
+
+    //bar_u1_x
+    //PKA_CTREG(3, 2,8,bar_u1_x);
+    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)bar_u1_x, ECP_SECP256R1_SIZE / 4, 0);
+    //bar_u1_y
+    //PKA_CTREG(3, 3,8,bar_u1_y);
+    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)bar_u1_y, ECP_SECP256R1_SIZE / 4, 0);
+    //bar_u1_z
+    //PKA_CTREG(3, 4,8,bar_u1_z);
+    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)bar_u1_z, ECP_SECP256R1_SIZE / 4, 0);
+
+    //R = u1 * G + u2 * PUB
+    //PKA_POINT_ADDITION();
+    sec_ecdsa_point_add(handle->ecpId);
+
+    /* Step6 Get R.x(R=u1G+u2P)*/
+    //R.z ^ -1
+    //PKA_MINV(0,3, 5,3, 4,3, 0);
+    Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_REG_TYPE, 0, 1);
+    //inv_r
+    //PKA_CTREG(3, 6,8,inv_r);
+    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1InvR_P, ECP_SECP256R1_SIZE / 4, 0);
+    //R.z ^ -1
+    Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1);
+    Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1);
+    //PKA_MONT2GF(3, 5,3, 5,3, 6);
+    Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6,
+                        ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);
+
+    //R.x (Montgomery to GF)
+    //PKA_MONT2GF(3, 6,3, 2,3, 6);
+    Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 6,
+                        ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);
+
+    //R.x (GF to Affine domain)
+    //PKA_MONT2GF(3, 2,3, 5,3, 6);
+    Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6,
+                        ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);
+    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)bar_u2_x, ECP_SECP256R1_SIZE / 4);
+#ifdef ECDSA_DBG
+    MSG("R.x=\r\n");
+    bflb_platform_dump(bar_u2_x, ECP_SECP256R1_SIZE);
+#endif
+
+    /* Step7 check R.x=r*/
+    /* Check Result */
+    for (i = 0; i < 8; i++) {
+        if (bar_u2_x[i] != r[i]) {
+            return -1;
+        }
+    }
+
+#ifdef ECDSA_DBG
+    MSG("Verify success\r\n");
+#endif
+    return 0;
+}
+
+int sec_ecdsa_sign(sec_ecdsa_handle_t *handle, const uint32_t *random_k, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *r, uint32_t *s)
+{
+    uint32_t k[8];
+    uint32_t Rx[8];
+    uint32_t Ry[8];
+    uint32_t KInvert[8];
+    uint32_t maxTry1 = 100;
+
+    /* Pointer check */
+    if (handle->privateKey == NULL || hash == NULL || r == NULL || s == NULL) {
+        return -1;
+    }
+
+    Sec_Eng_PKA_Reset();
+    Sec_Eng_PKA_BigEndian_Enable();
+    Sec_Eng_Trng_Enable();
+
+    while (maxTry1--) {
+        /* step 1 ,get random k*/
+        if (random_k == NULL) {
+            if (sec_ecc_get_random_value(k, (uint32_t *)secp256r1N, 32) < 0) {
+                return -1;
+            }
+        } else {
+            memcpy(k, random_k, 32);
+        }
+
+#ifdef ECDSA_DBG
+        MSG("Random k:\r\n");
+        bflb_platform_dump(k, ECP_SECP256R1_SIZE);
+#endif
+
+        /*step 2, calc R=kG*/
+        if (sec_ecdsa_get_public_key(handle, k, Rx, Ry) < 0) {
+            return -1;
+        }
+
+        if (sec_ecc_is_zero((uint8_t *)Rx, 32)) {
+            continue;
+        }
+
+        memcpy(r, Rx, 32);
+#ifdef ECDSA_DBG
+        MSG("r:\r\n");
+        bflb_platform_dump(r, ECP_SECP256R1_SIZE);
+#endif
+        sec_ecc_basic_parameter_init(handle->ecpId);
+        /* step 3,get k^-1*/
+        Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)k, ECP_SECP256R1_SIZE / 4, 0);
+        Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0);
+        /* Change k to Mont domain */
+        /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/
+        Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1);
+        Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1);
+        Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, 256,
+                            ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX);
+#ifdef ECDSA_DBG
+        Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
+        MSG("GF2Mont Result of k:\r\n");
+        bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
+#endif
+
+        /* Get k^-1 in Mont domain */
+        Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 5,
+                         ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1);
+#ifdef ECDSA_DBG
+        Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)KInvert, ECP_SECP256R1_SIZE / 4);
+        MSG("k^-1 in Mont:\r\n");
+        bflb_platform_dump(KInvert, ECP_SECP256R1_SIZE);
+#endif
+
+        /* Change k^-1 into GF domain,now  ECP_SECP256R1_S_REG_INDEX store k^-1*/
+        /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/
+        Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_INVR_N_REG_INDEX,
+                            ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX);
+        Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)KInvert, ECP_SECP256R1_SIZE / 4);
+#ifdef ECDSA_DBG
+        MSG("k^-1:\r\n");
+        bflb_platform_dump(KInvert, ECP_SECP256R1_SIZE);
+#endif
+
+        /* Step 4,r*d     ((e + r * d) / k) */
+        Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)handle->privateKey, ECP_SECP256R1_SIZE / 4, 0);
+        Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)r, ECP_SECP256R1_SIZE / 4, 0);
+        Sec_Eng_PKA_LMUL(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 4,
+                         ECP_SECP256R1_REG_TYPE, 5, 1);
+#ifdef ECDSA_DBG
+        Sec_Eng_PKA_Read_Data(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 2);
+        MSG("r*d:\r\n");
+        bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE * 2);
+#endif
+
+        /* Step 5,e+r*d   ((e + r * d) / k) */
+        Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)hash, ECP_SECP256R1_SIZE / 4, 0);
+        Sec_Eng_PKA_LADD(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX,
+                         ECP_SECP256R1_REG_TYPE, 5, 1);
+#ifdef ECDSA_DBG
+        Sec_Eng_PKA_Read_Data(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 2);
+        MSG("e+r*d:\r\n");
+        bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE * 2);
+#endif
+
+        /* Step 6,(e+r*d)*k^-1   ((e + r * d) / k) */
+        Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)KInvert, ECP_SECP256R1_SIZE / 4, 0);
+        Sec_Eng_PKA_LMUL(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX,
+                         ECP_SECP256R1_REG_TYPE, 5, 1);
+#ifdef ECDSA_DBG
+        Sec_Eng_PKA_Read_Data(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 2);
+        MSG("(e+r*d)*k^-1:\r\n");
+        bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE * 2);
+#endif
+        /*N write only this time,add following operation will not change this register*/
+        Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0);
+        Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX,
+                         ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1);
+        Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)s, ECP_SECP256R1_SIZE / 4);
+#ifdef ECDSA_DBG
+        MSG("s:\r\n");
+        bflb_platform_dump(s, ECP_SECP256R1_SIZE);
+#endif
+
+        /* Check s zero*/
+        if (sec_ecc_is_zero((uint8_t *)s, 32)) {
+            continue;
+        }
+
+        return 0;
+    }
+
+    return -1;
+}
+
+int sec_ecdsa_get_private_key(sec_ecdsa_handle_t *handle, uint32_t *private_key)
+{
+    if (sec_ecc_get_random_value(private_key, (uint32_t *)secp256r1N, 32) < 0) {
+        return -1;
+    }
+
+    return 0;
+}
+
+int sec_ecdsa_get_public_key(sec_ecdsa_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy)
+{
+    return sec_ecdh_get_scalar_point(handle->ecpId, NULL, NULL, private_key, pRx, pRy);
+}
+
+int sec_ecc_get_random_value(uint32_t *randomData, uint32_t *maxRef, uint32_t size)
+{
+    uint32_t maxTry = 100;
+    int32_t ret = 0;
+
+    while (maxTry--) {
+        ret = Sec_Eng_Trng_Get_Random((uint8_t *)randomData, size);
+
+        if (ret < 0) {
+            return -1;
+        }
+
+        if (maxRef != NULL) {
+            if (sec_ecc_cmp((uint8_t *)maxRef, (uint8_t *)randomData, size) > 0) {
+                return 0;
+            }
+        } else {
+            return 0;
+        }
+    }
+
+    return -1;
+}
+
+int sec_eng_trng_enable(void)
+{
+    return Sec_Eng_Trng_Enable();
+}
+
+void sec_eng_trng_disable(void)
+{
+    Sec_Eng_Trng_Disable();
+}
+
+int sec_eng_trng_read(uint8_t data[32])
+{
+    return Sec_Eng_Trng_Read(data);
+}
+
+int sec_ecdh_init(sec_ecdh_handle_t *handle, sec_ecp_type id)
+{
+    Sec_Eng_PKA_Reset();
+    Sec_Eng_PKA_BigEndian_Enable();
+    Sec_Eng_Trng_Enable();
+
+    handle->ecpId = id;
+
+    return 0;
+}
+
+int sec_ecdh_deinit(sec_ecdh_handle_t *handle)
+{
+    Sec_Eng_PKA_Reset();
+
+    return 0;
+}
+
+int sec_ecdh_get_encrypt_key(sec_ecdh_handle_t *handle, const uint32_t *pkX, const uint32_t *pkY, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy)
+{
+    return sec_ecdh_get_scalar_point(handle->ecpId, pkX, pkY, private_key, pRx, pRy);
+}
+
+int sec_ecdh_get_public_key(sec_ecdh_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy)
+{
+    return sec_ecdh_get_scalar_point(handle->ecpId, NULL, NULL, private_key, pRx, pRy);
+}
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_hash.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_hash.c
new file mode 100644
index 00000000..736c0811
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_hash.c
@@ -0,0 +1,387 @@
+/**
+ * @file hal_sec_hash.c
+ * @brief
+ *
+ * Copyright 2019-2030 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "hal_sec_hash.h"
+#include "bl702_sec_eng.h"
+
+void SEC_SHA_IRQHandler(void);
+
+static sec_hash_device_t sec_hashx_device[SEC_HASH_MAX_INDEX] = {
+    0
+};
+
+static SEC_Eng_SHA256_Ctx shaCtx;
+
+static SEC_Eng_SHA256_Ctx sha256Ctx;
+
+/**
+ * @brief
+ *
+ * @param dev
+ * @param oflag
+ * @return int
+ */
+int sec_hash_open(struct device *dev, uint16_t oflag)
+{
+    sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev;
+    int ret = 0;
+
+    switch (sec_hash_device->type) {
+        case SEC_HASH_SHA1:
+            ret = -1;
+            break;
+
+        case SEC_HASH_SHA224:
+            Sec_Eng_SHA256_Init(&shaCtx, SEC_ENG_SHA_ID0, SEC_ENG_SHA224, sec_hash_device->shaBuf, sec_hash_device->shaPadding);
+            Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0);
+            break;
+
+        case SEC_HASH_SHA256:
+            Sec_Eng_SHA256_Init(&shaCtx, SEC_ENG_SHA_ID0, SEC_ENG_SHA256, sec_hash_device->shaBuf, sec_hash_device->shaPadding);
+            Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0);
+            break;
+
+        case SEC_HASH_SHA384:
+        case SEC_HASH_SHA512:
+            ret = -1;
+            break;
+
+        default:
+            ret = -1;
+            break;
+    }
+
+    return ret;
+}
+/**
+ * @brief
+ *
+ * @param dev
+ * @return int
+ */
+int sec_hash_close(struct device *dev)
+{
+    //sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev;
+    //memset(sec_hash_device, 0, sizeof(sec_hash_device_t)); //will cause crash
+    return 0;
+}
+/**
+ * @brief
+ *
+ * @param dev
+ * @param cmd
+ * @param args
+ * @return int
+ */
+int sec_hash_control(struct device *dev, int cmd, void *args)
+{
+    return 0;
+}
+
+/**
+ * @brief
+ *
+ * @param dev
+ * @param pos
+ * @param buffer
+ * @param size
+ * @return int
+ */
+int sec_hash_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
+{
+    sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev;
+    int ret = 0;
+
+    switch (sec_hash_device->type) {
+        case SEC_HASH_SHA1:
+            ret = -1;
+            break;
+
+        case SEC_HASH_SHA224:
+            Sec_Eng_SHA256_Update(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer, size);
+            break;
+
+        case SEC_HASH_SHA256:
+            Sec_Eng_SHA256_Update(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer, size);
+            break;
+
+        case SEC_HASH_SHA384:
+        case SEC_HASH_SHA512:
+            ret = -1;
+            break;
+
+        default:
+            ret = -1;
+            break;
+    }
+
+    return ret;
+}
+
+/**
+ * @brief
+ *
+ * @param dev
+ * @param pos
+ * @param buffer
+ * @param size
+ * @return int
+ */
+int sec_hash_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
+{
+    sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev;
+    int ret = 0;
+
+    switch (sec_hash_device->type) {
+        case SEC_HASH_SHA1:
+            ret = -1;
+            break;
+
+        case SEC_HASH_SHA224:
+            Sec_Eng_SHA256_Finish(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer);
+            ret = 28;
+            break;
+
+        case SEC_HASH_SHA256:
+            Sec_Eng_SHA256_Finish(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer);
+            ret = 32;
+            break;
+
+        case SEC_HASH_SHA384:
+        case SEC_HASH_SHA512:
+            ret = -1;
+            break;
+
+        default:
+            ret = -1;
+            break;
+    }
+
+    return ret;
+}
+
+/**
+ * @brief
+ *
+ * @param handle
+ * @param type
+ * @return int
+ */
+int sec_hash_init(sec_hash_handle_t *handle, uint8_t type)
+{
+    int ret = 0;
+
+    switch (type) {
+        case SEC_HASH_SHA1:
+            ret = -1;
+            break;
+
+        case SEC_HASH_SHA224:
+            handle->type = type;
+            Sec_Eng_SHA256_Init(&sha256Ctx, SEC_ENG_SHA_ID0, SEC_ENG_SHA224, handle->shaBuf, handle->shaPadding);
+            Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0);
+            break;
+
+        case SEC_HASH_SHA256:
+            handle->type = type;
+            Sec_Eng_SHA256_Init(&sha256Ctx, SEC_ENG_SHA_ID0, SEC_ENG_SHA256, handle->shaBuf, handle->shaPadding);
+            Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0);
+            break;
+
+        case SEC_HASH_SHA384:
+        case SEC_HASH_SHA512:
+            ret = -1;
+            break;
+
+        default:
+            ret = -1;
+            break;
+    }
+
+    return ret;
+}
+/**
+ * @brief
+ *
+ * @param handle
+ * @return int
+ */
+int sec_hash_deinit(sec_hash_handle_t *handle)
+{
+    memset(handle->shaBuf, 0, sizeof(handle->shaBuf));
+    memset(handle->shaPadding, 0, sizeof(handle->shaPadding));
+
+    return 0;
+}
+
+/**
+ * @brief
+ *
+ * @param handle
+ * @param buffer
+ * @param size
+ * @return int
+ */
+int sec_hash_update(sec_hash_handle_t *handle, const void *buffer, uint32_t size)
+{
+    int ret = 0;
+
+    switch (handle->type) {
+        case SEC_HASH_SHA1:
+            ret = -1;
+            break;
+
+        case SEC_HASH_SHA224:
+            Sec_Eng_SHA256_Update(&sha256Ctx, SEC_ENG_SHA_ID0, (uint8_t *)buffer, size);
+            break;
+
+        case SEC_HASH_SHA256:
+            Sec_Eng_SHA256_Update(&sha256Ctx, SEC_ENG_SHA_ID0, (uint8_t *)buffer, size);
+            break;
+
+        case SEC_HASH_SHA384:
+        case SEC_HASH_SHA512:
+            ret = -1;
+            break;
+
+        default:
+            ret = -1;
+            break;
+    }
+
+    return ret;
+}
+
+/**
+ * @brief
+ *
+ * @param handle
+ * @param buffer
+ * @return int
+ */
+int sec_hash_finish(sec_hash_handle_t *handle, void *buffer)
+{
+    int ret = 0;
+
+    switch (handle->type) {
+        case SEC_HASH_SHA1:
+            ret = -1;
+            break;
+
+        case SEC_HASH_SHA224:
+            Sec_Eng_SHA256_Finish(&sha256Ctx, SEC_ENG_SHA_ID0, (uint8_t *)buffer);
+            ret = 28;
+            break;
+
+        case SEC_HASH_SHA256:
+            Sec_Eng_SHA256_Finish(&sha256Ctx, SEC_ENG_SHA_ID0, (uint8_t *)buffer);
+            ret = 32;
+            break;
+
+        case SEC_HASH_SHA384:
+        case SEC_HASH_SHA512:
+            ret = -1;
+            break;
+
+        default:
+            ret = -1;
+            break;
+    }
+
+    return ret;
+}
+
+/**
+ * @brief
+ *
+ * @param index
+ * @param type
+ * @param name
+ * @param flag
+ * @return int
+ */
+static int sec_hash_sha_register(enum sec_hash_index_type index, enum sec_hash_type type, const char *name)
+{
+    struct device *dev;
+
+    if (SEC_HASH_MAX_INDEX == 0) {
+        return -DEVICE_EINVAL;
+    }
+
+    dev = &(sec_hashx_device[index].parent);
+    sec_hashx_device[index].type = type;
+
+    dev->open = sec_hash_open;
+    dev->close = sec_hash_close;
+    dev->control = sec_hash_control;
+    dev->write = sec_hash_write;
+    dev->read = sec_hash_read;
+
+    dev->type = DEVICE_CLASS_SEC_HASH;
+    dev->handle = NULL;
+
+    return device_register(dev, name);
+}
+
+/**
+ * @brief
+ *
+ * @param index
+ * @param name
+ * @param flag
+ * @return int
+ */
+int sec_hash_sha256_register(enum sec_hash_index_type index, const char *name)
+{
+    return sec_hash_sha_register(index, SEC_HASH_SHA256, name);
+}
+
+/**
+ * @brief
+ *
+ * @param index
+ * @param name
+ * @param flag
+ * @return int
+ */
+int sec_hash_sha224_register(enum sec_hash_index_type index, const char *name)
+{
+    return sec_hash_sha_register(index, SEC_HASH_SHA224, name);
+}
+
+/**
+ * @brief
+ *
+ * @param handle
+ */
+void sec_hash_isr(void)
+{
+}
+
+/**
+ * @brief
+ *
+ */
+void SEC_SHA_IRQ(void)
+{
+    sec_hash_isr();
+}
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_uart.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_uart.c
new file mode 100644
index 00000000..26dbe0bb
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_uart.c
@@ -0,0 +1,442 @@
+/**
+ * @file hal_uart.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "hal_uart.h"
+#include "hal_dma.h"
+#include "hal_clock.h"
+#include "bl702_uart.h"
+#include "bl702_glb.h"
+#include "uart_config.h"
+
+#ifdef BSP_USING_UART0
+static void UART0_IRQ(void);
+#endif
+#ifdef BSP_USING_UART1
+static void UART1_IRQ(void);
+#endif
+
+static uart_device_t uartx_device[UART_MAX_INDEX] = {
+#ifdef BSP_USING_UART0
+    UART0_CONFIG,
+#endif
+#ifdef BSP_USING_UART1
+    UART1_CONFIG,
+#endif
+};
+/**
+ * @brief
+ *
+ * @param dev
+ * @param oflag
+ * @return int
+ */
+int uart_open(struct device *dev, uint16_t oflag)
+{
+    uart_device_t *uart_device = (uart_device_t *)dev;
+    UART_FifoCfg_Type fifoCfg = { 0 };
+    UART_CFG_Type uart_cfg = { 0 };
+
+    /* disable all interrupt */
+    UART_IntMask(uart_device->id, UART_INT_ALL, MASK);
+    /* disable uart before config */
+    UART_Disable(uart_device->id, UART_TXRX);
+
+    uint32_t uart_clk = peripheral_clock_get(PERIPHERAL_CLOCK_UART);
+    uart_cfg.baudRate = uart_device->baudrate;
+    uart_cfg.dataBits = uart_device->databits;
+    uart_cfg.stopBits = uart_device->stopbits;
+    uart_cfg.parity = uart_device->parity;
+    uart_cfg.uartClk = uart_clk;
+    uart_cfg.ctsFlowControl = UART_CTS_FLOWCONTROL_ENABLE;
+    uart_cfg.rtsSoftwareControl = UART_RTS_FLOWCONTROL_ENABLE;
+    uart_cfg.byteBitInverse = UART_MSB_FIRST_ENABLE;
+    uart_cfg.txSoftwareControl = UART_TX_SWCONTROL_ENABLE;
+    uart_cfg.txLinMode = UART_TX_LINMODE_ENABLE;
+    uart_cfg.rxLinMode = UART_RX_LINMODE_ENABLE;
+    uart_cfg.txBreakBitCnt = UART_TX_BREAKBIT_CNT;
+    uart_cfg.rxDeglitch = ENABLE;
+
+    /* uart init with default configuration */
+    UART_Init(uart_device->id, &uart_cfg);
+
+    /* Enable tx free run mode */
+    UART_TxFreeRun(uart_device->id, ENABLE);
+    /*set de-glitch function cycle count value*/
+    UART_SetDeglitchCount(uart_device->id, 2);
+
+    /* Set rx time-out value */
+    UART_SetRxTimeoutValue(uart_device->id, UART_DEFAULT_RTO_TIMEOUT);
+
+    fifoCfg.txFifoDmaThreshold = uart_device->fifo_threshold;
+    fifoCfg.txFifoDmaEnable = DISABLE;
+    fifoCfg.rxFifoDmaThreshold = uart_device->fifo_threshold;
+    fifoCfg.rxFifoDmaEnable = DISABLE;
+
+    if (oflag & DEVICE_OFLAG_STREAM_TX) {
+    }
+    if ((oflag & DEVICE_OFLAG_INT_TX) || (oflag & DEVICE_OFLAG_INT_RX)) {
+#ifdef BSP_USING_UART0
+        if (uart_device->id == UART0_ID)
+            Interrupt_Handler_Register(UART0_IRQn, UART0_IRQ);
+#endif
+#ifdef BSP_USING_UART1
+        if (uart_device->id == UART1_ID)
+            Interrupt_Handler_Register(UART1_IRQn, UART1_IRQ);
+#endif
+    }
+    if (oflag & DEVICE_OFLAG_DMA_TX) {
+        fifoCfg.txFifoDmaEnable = ENABLE;
+    }
+    if (oflag & DEVICE_OFLAG_DMA_RX) {
+        fifoCfg.rxFifoDmaEnable = ENABLE;
+    }
+
+    UART_FifoConfig(uart_device->id, &fifoCfg);
+    /* enable uart */
+    UART_Enable(uart_device->id, UART_TXRX);
+    return 0;
+}
+/**
+ * @brief
+ *
+ * @param dev
+ * @return int
+ */
+int uart_close(struct device *dev)
+{
+    uart_device_t *uart_device = (uart_device_t *)dev;
+
+    UART_Disable(uart_device->id, UART_TXRX);
+    if (uart_device->id == 0) {
+        GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART0);
+    } else if (uart_device->id == 1) {
+        GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART1);
+    }
+    return 0;
+}
+/**
+ * @brief
+ *
+ * @param dev
+ * @param cmd
+ * @param args
+ * @return int
+ */
+int uart_control(struct device *dev, int cmd, void *args)
+{
+    uart_device_t *uart_device = (uart_device_t *)dev;
+
+    switch (cmd) {
+        case DEVICE_CTRL_SET_INT /* constant-expression */: {
+            uint32_t offset = __builtin_ctz((uint32_t)args);
+            while (offset < 9) {
+                if ((uint32_t)args & (1 << offset)) {
+                    UART_IntMask(uart_device->id, offset, UNMASK);
+                }
+                offset++;
+            }
+            if (uart_device->id == UART0_ID)
+                CPU_Interrupt_Enable(UART0_IRQn);
+            else if (uart_device->id == UART1_ID)
+                CPU_Interrupt_Enable(UART1_IRQn);
+
+            break;
+        }
+        case DEVICE_CTRL_CLR_INT /* constant-expression */: {
+            uint32_t offset = __builtin_ctz((uint32_t)args);
+            while (offset < 9) {
+                if ((uint32_t)args & (1 << offset)) {
+                    UART_IntMask(uart_device->id, offset, MASK);
+                }
+                offset++;
+            }
+            if (uart_device->id == UART0_ID)
+                CPU_Interrupt_Disable(UART0_IRQn);
+            else if (uart_device->id == UART1_ID)
+                CPU_Interrupt_Disable(UART1_IRQn);
+
+            break;
+        }
+        case DEVICE_CTRL_GET_INT /* constant-expression */:
+            /* code */
+            break;
+        case DEVICE_CTRL_RESUME /* constant-expression */:
+            UART_Enable(uart_device->id, UART_TXRX);
+            break;
+        case DEVICE_CTRL_SUSPEND /* constant-expression */:
+            UART_Disable(uart_device->id, UART_TXRX);
+            break;
+        case DEVICE_CTRL_CONFIG /* constant-expression */: {
+            uart_param_cfg_t *cfg = (uart_param_cfg_t *)args;
+            UART_CFG_Type uart_cfg;
+
+            uint32_t uart_clk = peripheral_clock_get(PERIPHERAL_CLOCK_UART);
+
+            uart_cfg.uartClk = uart_clk;
+            uart_cfg.baudRate = cfg->baudrate;
+            uart_cfg.stopBits = cfg->stopbits;
+            uart_cfg.parity = cfg->parity;
+            uart_cfg.dataBits = cfg->databits;
+            uart_cfg.ctsFlowControl = UART_CTS_FLOWCONTROL_ENABLE;
+            uart_cfg.rtsSoftwareControl = UART_RTS_FLOWCONTROL_ENABLE;
+            uart_cfg.byteBitInverse = UART_MSB_FIRST_ENABLE;
+            uart_cfg.txSoftwareControl = UART_TX_SWCONTROL_ENABLE;
+            uart_cfg.txLinMode = UART_TX_LINMODE_ENABLE;
+            uart_cfg.rxLinMode = UART_RX_LINMODE_ENABLE;
+            uart_cfg.txBreakBitCnt = UART_TX_BREAKBIT_CNT;
+            uart_cfg.rxDeglitch = ENABLE;
+            UART_Init(uart_device->id, &uart_cfg);
+            /*set de-glitch function cycle count value*/
+            UART_SetDeglitchCount(uart_device->id, 2);
+            break;
+        }
+        case DEVICE_CTRL_GET_CONFIG /* constant-expression */:
+            break;
+        case DEVICE_CTRL_ATTACH_TX_DMA /* constant-expression */:
+            uart_device->tx_dma = (struct device *)args;
+            break;
+        case DEVICE_CTRL_ATTACH_RX_DMA /* constant-expression */:
+            uart_device->rx_dma = (struct device *)args;
+            break;
+        case DEVICE_CTRL_TX_DMA_SUSPEND: {
+            uint32_t tmpVal = BL_RD_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_TX_EN);
+            BL_WR_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0, tmpVal);
+            dev->oflag &= ~DEVICE_OFLAG_DMA_TX;
+            break;
+        }
+        case DEVICE_CTRL_RX_DMA_SUSPEND: {
+            uint32_t tmpVal = BL_RD_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_RX_EN);
+            BL_WR_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0, tmpVal);
+            dev->oflag &= ~DEVICE_OFLAG_DMA_RX;
+            break;
+        }
+        case DEVICE_CTRL_TX_DMA_RESUME: {
+            uint32_t tmpVal = BL_RD_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0);
+            tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_TX_EN);
+            BL_WR_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0, tmpVal);
+            dev->oflag |= DEVICE_OFLAG_DMA_TX;
+            break;
+        }
+        case DEVICE_CTRL_RX_DMA_RESUME: {
+            uint32_t tmpVal = BL_RD_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0);
+            tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_RX_EN);
+            BL_WR_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0, tmpVal);
+            dev->oflag |= DEVICE_OFLAG_DMA_RX;
+            break;
+        }
+        case DEVICE_CTRL_UART_GET_TX_FIFO /* constant-expression */:
+            return UART_GetTxFifoCount(uart_device->id);
+        case DEVICE_CTRL_UART_GET_RX_FIFO /* constant-expression */:
+            return UART_GetRxFifoCount(uart_device->id);
+        case DEVICE_CTRL_UART_CLEAR_TX_FIFO /* constant-expression */:
+            return UART_TxFifoClear(uart_device->id);
+        case DEVICE_CTRL_UART_CLEAR_RX_FIFO /* constant-expression */:
+            return UART_RxFifoClear(uart_device->id);
+        default:
+            break;
+    }
+
+    return 0;
+}
+/**
+ * @brief
+ *
+ * @param dev
+ * @param pos
+ * @param buffer
+ * @param size
+ * @return int
+ */
+int uart_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
+{
+    int ret = 0;
+    uart_device_t *uart_device = (uart_device_t *)dev;
+    if (dev->oflag & DEVICE_OFLAG_DMA_TX) {
+        struct device *dma_ch = (struct device *)uart_device->tx_dma;
+        if (!dma_ch)
+            return -1;
+
+        if (uart_device->id == 0) {
+            ret = dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_UART0_TDR, size);
+            dma_channel_start(dma_ch);
+        } else if (uart_device->id == 1) {
+            ret = dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_UART1_TDR, size);
+            dma_channel_start(dma_ch);
+        }
+        return ret;
+    } else if (dev->oflag & DEVICE_OFLAG_INT_TX) {
+        return -2;
+    } else
+        return UART_SendData(uart_device->id, (uint8_t *)buffer, size);
+}
+/**
+ * @brief
+ *
+ * @param dev
+ * @param pos
+ * @param buffer
+ * @param size
+ * @return int
+ */
+int uart_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
+{
+    int ret = -1;
+    uart_device_t *uart_device = (uart_device_t *)dev;
+    if (dev->oflag & DEVICE_OFLAG_DMA_RX) {
+        struct device *dma_ch = (struct device *)uart_device->rx_dma;
+        if (!dma_ch)
+            return -1;
+
+        if (uart_device->id == 0) {
+            ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_UART0_RDR, (uint32_t)buffer, size);
+            dma_channel_start(dma_ch);
+        } else if (uart_device->id == 1) {
+            ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_UART1_RDR, (uint32_t)buffer, size);
+            dma_channel_start(dma_ch);
+        }
+        return ret;
+    } else if (dev->oflag & DEVICE_OFLAG_INT_RX) {
+        return -2;
+    } else {
+        return UART_ReceiveData(uart_device->id, (uint8_t *)buffer, size);
+    }
+}
+/**
+ * @brief
+ *
+ * @param index
+ * @param name
+ * @param flag
+ * @return int
+ */
+int uart_register(enum uart_index_type index, const char *name)
+{
+    struct device *dev;
+
+    if (UART_MAX_INDEX == 0)
+        return -DEVICE_EINVAL;
+
+    dev = &(uartx_device[index].parent);
+
+    dev->open = uart_open;
+    dev->close = uart_close;
+    dev->control = uart_control;
+    dev->write = uart_write;
+    dev->read = uart_read;
+
+    dev->type = DEVICE_CLASS_UART;
+    dev->handle = NULL;
+
+    return device_register(dev, name);
+}
+/**
+ * @brief
+ *
+ * @param handle
+ */
+void uart_isr(uart_device_t *handle)
+{
+    uint32_t tmpVal = 0;
+    uint32_t maskVal = 0;
+    uint32_t UARTx = (UART0_BASE + handle->id * 0x100);
+
+    tmpVal = BL_RD_REG(UARTx, UART_INT_STS);
+    maskVal = BL_RD_REG(UARTx, UART_INT_MASK);
+
+    if (!handle->parent.callback)
+        return;
+
+    /* Length of uart tx data transfer arrived interrupt */
+    if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_END_MASK)) {
+        BL_WR_REG(UARTx, UART_INT_CLEAR, 0x1);
+        handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_TX_END);
+    }
+
+    /* Length of uart rx data transfer arrived interrupt */
+    if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_END_MASK)) {
+        BL_WR_REG(UARTx, UART_INT_CLEAR, 0x2);
+        handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_RX_END);
+    }
+
+    /* Tx fifo ready interrupt,auto-cleared when data is pushed */
+    if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FIFO_MASK)) {
+        handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_TX_FIFO);
+    }
+
+    /* Rx fifo ready interrupt,auto-cleared when data is popped */
+    if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FIFO_MASK)) {
+        uint8_t buffer[UART_FIFO_MAX_LEN];
+        uint8_t len = UART_ReceiveData(handle->id, buffer, UART_FIFO_MAX_LEN);
+        if (len) {
+            handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RX_FIFO);
+        }
+    }
+
+    /* Rx time-out interrupt */
+    if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_RTO_MASK)) {
+        BL_WR_REG(UARTx, UART_INT_CLEAR, 0x10);
+        uint8_t buffer[UART_FIFO_MAX_LEN];
+        uint8_t len = UART_ReceiveData(handle->id, buffer, UART_FIFO_MAX_LEN);
+        if (len) {
+            handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RTO);
+        }
+    }
+
+    /* Rx parity check error interrupt */
+    if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_PCE_MASK)) {
+        BL_WR_REG(UARTx, UART_INT_CLEAR, 0x20);
+        handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_PCE);
+    }
+
+    /* Tx fifo overflow/underflow error interrupt */
+    if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FER_MASK)) {
+        handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_TX_FER);
+    }
+
+    /* Rx fifo overflow/underflow error interrupt */
+    if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FER_MASK)) {
+        handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_RX_FER);
+    }
+}
+
+#ifdef BSP_USING_UART0
+/**
+ * @brief
+ *
+ */
+void UART0_IRQ(void)
+{
+    uart_isr(&uartx_device[UART0_INDEX]);
+}
+#endif
+#ifdef BSP_USING_UART1
+/**
+ * @brief
+ *
+ */
+void UART1_IRQ(void)
+{
+    uart_isr(&uartx_device[UART1_INDEX]);
+}
+#endif
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_usb.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_usb.c
new file mode 100644
index 00000000..6e925f2a
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_usb.c
@@ -0,0 +1,1173 @@
+/**
+ * @file hal_usb.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "hal_usb.h"
+#include "hal_dma.h"
+#include "hal_mtimer.h"
+#include "bl702_usb.h"
+#include "bl702_glb.h"
+
+#define USE_INTERNAL_TRANSCEIVER
+//#define ENABLE_LPM_INT
+//#define ENABLE_SOF3MS_INT
+//#define ENABLE_ERROR_INT
+
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+
+#define USB_DC_LOG_WRN(a, ...) //bflb_platform_printf(a, ##__VA_ARGS__)
+#define USB_DC_LOG_DBG(a, ...)
+#define USB_DC_LOG_ERR(a, ...) //bflb_platform_printf(a, ##__VA_ARGS__)
+#define USB_DC_LOG(a, ...)
+
+static usb_dc_device_t usb_fs_device;
+static void USB_FS_IRQ(void);
+
+static dma_lli_ctrl_t usb_lli_list = {
+    .src_addr = 0,
+    .dst_addr = 0,
+    .nextlli = 0,
+    .cfg.bits.fix_cnt = 0,
+    .cfg.bits.dst_min_mode = 0,
+    .cfg.bits.dst_add_mode = 0,
+    .cfg.bits.SI = 0,
+    .cfg.bits.DI = 0,
+    .cfg.bits.SWidth = DMA_TRANSFER_WIDTH_8BIT,
+    .cfg.bits.DWidth = DMA_TRANSFER_WIDTH_8BIT,
+    .cfg.bits.SBSize = 0,
+    .cfg.bits.DBSize = 0,
+    .cfg.bits.I = 0,
+    .cfg.bits.TransferSize = 0
+};
+
+static void usb_set_power_up(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_USB);
+    BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal);
+}
+
+static void usb_set_power_off(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_USB);
+    BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal);
+}
+
+static uint8_t usb_ep_is_enabled(uint8_t ep)
+{
+    uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+    /* Check if ep enabled */
+    if ((USB_EP_DIR_IS_OUT(ep)) &&
+        usb_fs_device.out_ep[ep_idx].ep_ena) {
+        return 1;
+    } else if ((USB_EP_DIR_IS_IN(ep)) &&
+               usb_fs_device.in_ep[ep_idx].ep_ena) {
+        return 1;
+    }
+
+    return 0;
+}
+
+static void usb_xcvr_config(BL_Fun_Type NewState)
+{
+    uint32_t tmpVal = 0;
+
+    if (NewState != DISABLE) {
+#if defined(USE_EXTERNAL_TRANSCEIVER)
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR_CONFIG);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_USB_USE_XCVR, 0); //use external tranceiver
+        BL_WR_REG(GLB_BASE, GLB_USB_XCVR_CONFIG, tmpVal);
+#elif defined(USE_INTERNAL_TRANSCEIVER)
+#if 1
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_USB, 1);
+        BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal);
+
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SUS, 0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SPD, 1); //0 for 1.1 ls,1 for 1.1 fs
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_DATA_CONVERT, 0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_OEB_SEL, 0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ROUT_PMOS, 3);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ROUT_NMOS, 3);
+        BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal);
+
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR_CONFIG);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SLEWRATE_P_RISE, 2); //1 for 1.1 ls
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SLEWRATE_P_FALL, 2); //1 for 1.1 ls
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SLEWRATE_M_RISE, 2); //1 for 1.1 ls
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SLEWRATE_M_FALL, 2); //1 for 1.1 ls
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_RES_PULLUP_TUNE, 5);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_USB_USE_XCVR, 1);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_BD_VTH, 1);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_V_HYS_P, 2);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_V_HYS_M, 2);
+        BL_WR_REG(GLB_BASE, GLB_USB_XCVR_CONFIG, tmpVal);
+
+        ///* force BD=1, not use */
+        //tmpVal=BL_RD_REG(GLB_BASE,GLB_USB_XCVR);
+        //tmpVal=BL_SET_REG_BIT(tmpVal,GLB_PU_USB_LDO);
+        //BL_WR_REG(GLB_BASE,GLB_USB_XCVR,tmpVal);
+
+        /* BD_voltage_thresdhold=2.8V */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR_CONFIG);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_BD_VTH, 7);
+        BL_WR_REG(GLB_BASE, GLB_USB_XCVR_CONFIG, tmpVal);
+
+#else
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_USB, 1);
+        BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal);
+
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SUS, 0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SPD, 0); //0 for 1.1 ls,1 for 1.1 fs
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_DATA_CONVERT, 0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_OEB_SEL, 0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ROUT_PMOS, 3);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ROUT_NMOS, 3);
+        BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal);
+
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR_CONFIG);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SLEWRATE_P_RISE, 1); //4 for 1.1 fs
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SLEWRATE_P_FALL, 1); //3 for 1.1 fs
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SLEWRATE_M_RISE, 1); //4 for 1.1 fs
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SLEWRATE_M_FALL, 1); //3 for 1.1 fs
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_RES_PULLUP_TUNE, 5);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_USB_USE_XCVR, 1);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_BD_VTH, 1);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_V_HYS_P, 2);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_V_HYS_M, 2);
+        BL_WR_REG(GLB_BASE, GLB_USB_XCVR_CONFIG, tmpVal);
+#endif
+
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ENUM, 1);
+        BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal);
+#endif
+    } else {
+#ifdef USE_INTERNAL_TRANSCEIVER
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ENUM, 0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_USB, 0);
+        BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal);
+
+        ///* force BD=1, not use */
+        //tmpVal=BL_RD_REG(GLB_BASE,GLB_USB_XCVR);
+        //tmpVal=BL_SET_REG_BIT(tmpVal,GLB_PU_USB_LDO);
+        //BL_WR_REG(GLB_BASE,GLB_USB_XCVR,tmpVal);
+
+        /* BD_voltage_thresdhold=2.8V */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR_CONFIG);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_BD_VTH, 7);
+        BL_WR_REG(GLB_BASE, GLB_USB_XCVR_CONFIG, tmpVal);
+
+#else
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR_CONFIG);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_USB_USE_XCVR, 1); //use internal tranceiver
+        BL_WR_REG(GLB_BASE, GLB_USB_XCVR_CONFIG, tmpVal);
+
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ENUM, 0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_USB, 1);
+        BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal);
+#endif
+    }
+}
+
+/**
+ * @brief
+ *
+ * @param dev
+ * @param oflag
+ * @return int
+ */
+int usb_open(struct device *dev, uint16_t oflag)
+{
+    USB_Config_Type usbCfg = { 0 };
+
+    usb_set_power_off();
+    mtimer_delay_ms(10);
+    usb_set_power_up();
+
+    usb_xcvr_config(DISABLE);
+    usb_xcvr_config(ENABLE);
+
+    CPU_Interrupt_Disable(USB_IRQn);
+
+    usbCfg.DeviceAddress = 0;
+    usbCfg.EnumInEn = ENABLE;
+    usbCfg.EnumOutEn = ENABLE;
+    usbCfg.RomBaseDescriptorUsed = 0;
+    usbCfg.SoftwareCtrl = 1;
+    usbCfg.EnumMaxPacketSize = USB_CTRL_EP_MPS;
+
+    /* Init Device */
+    USB_Set_Config(DISABLE, &usbCfg);
+
+    usb_fs_device.out_ep[0].ep_ena = 1U;
+    usb_fs_device.in_ep[0].ep_ena = 1U;
+    usb_fs_device.out_ep[0].ep_cfg.ep_mps = USB_CTRL_EP_MPS;
+    usb_fs_device.out_ep[0].ep_cfg.ep_type = USBD_EP_TYPE_CTRL;
+    usb_fs_device.in_ep[0].ep_cfg.ep_mps = USB_CTRL_EP_MPS;
+    usb_fs_device.in_ep[0].ep_cfg.ep_type = USBD_EP_TYPE_CTRL;
+
+    /* USB interrupt enable config */
+    BL_WR_REG(USB_BASE, USB_INT_EN, 0);
+    USB_IntEn(USB_INT_RESET, ENABLE);          //1
+    USB_IntEn(USB_INT_EP0_SETUP_DONE, ENABLE); //5
+    USB_IntEn(USB_INT_EP0_IN_DONE, ENABLE);    //7
+    USB_IntEn(USB_INT_EP0_OUT_DONE, ENABLE);   //9
+    USB_IntEn(USB_INT_RESET_END, ENABLE);      //27
+
+    /* USB interrupt mask config */
+    BL_WR_REG(USB_BASE, USB_INT_MASK, 0xffffffff);
+    USB_IntMask(USB_INT_RESET, UNMASK);          //1
+    USB_IntMask(USB_INT_EP0_SETUP_DONE, UNMASK); //5
+    USB_IntMask(USB_INT_EP0_IN_DONE, UNMASK);    //7
+    USB_IntMask(USB_INT_EP0_OUT_DONE, UNMASK);   //9
+    USB_IntMask(USB_INT_RESET_END, UNMASK);      //27
+
+#ifdef ENABLE_LPM_INT
+    USB_IntEn(USB_INT_LPM_PACKET, ENABLE);
+    USB_IntEn(USB_INT_LPM_WAKEUP, ENABLE);
+    USB_IntMask(USB_INT_LPM_PACKET, UNMASK);
+    USB_IntMask(USB_INT_LPM_WAKEUP, UNMASK);
+
+    USB_LPM_Enable();
+    USB_Set_LPM_Default_Response(USB_LPM_DEFAULT_RESP_ACK);
+
+#endif
+
+#ifdef ENABLE_SOF3MS_INT
+    /* disable sof3ms until reset_end */
+    USB_IntEn(USB_INT_LOST_SOF_3_TIMES, DISABLE);
+    USB_IntMask(USB_INT_LOST_SOF_3_TIMES, MASK);
+
+    /* recommended enable sof3ms after reset_end */
+    USB_IntEn(USB_INT_LOST_SOF_3_TIMES, ENABLE);
+    USB_IntMask(USB_INT_LOST_SOF_3_TIMES, UNMASK);
+#endif
+
+#ifdef ENABLE_ERROR_INT
+    USB_IntEn(USB_INT_ERROR, ENABLE);
+    USB_IntMask(USB_INT_ERROR, UNMASK);
+#endif
+    /*Clear pending interrupts*/
+    USB_Clr_IntStatus(USB_INT_ALL);
+
+    Interrupt_Handler_Register(USB_IRQn, USB_FS_IRQ);
+    CPU_Interrupt_Enable(USB_IRQn);
+    USB_Enable();
+
+    return 0;
+}
+/**
+ * @brief
+ *
+ * @param dev
+ * @return int
+ */
+int usb_close(struct device *dev)
+{
+    /* disable all interrupts and force USB reset */
+    CPU_Interrupt_Disable(USB_IRQn);
+    USB_IntMask(USB_INT_LPM_WAKEUP, MASK);
+    USB_IntMask(USB_INT_LPM_PACKET, MASK);
+
+    USB_Disable();
+
+    /* clear interrupt status register */
+    USB_Clr_IntStatus(USB_INT_ALL);
+
+    usb_set_power_off();
+
+    usb_xcvr_config(DISABLE);
+    GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_USB);
+    return 0;
+}
+/**
+ * @brief
+ *
+ * @param dev
+ * @param cmd
+ * @param args
+ * @return int
+ */
+int usb_control(struct device *dev, int cmd, void *args)
+{
+    struct usb_dc_device *usb_device = (struct usb_dc_device *)dev;
+
+    switch (cmd) {
+        case DEVICE_CTRL_SET_INT /* constant-expression */: {
+            uint32_t offset = __builtin_ctz((uint32_t)args);
+
+            while (offset < 24) {
+                if ((uint32_t)args & (1 << offset)) {
+                    USB_IntEn(offset, ENABLE);
+                    USB_IntMask(offset, UNMASK);
+                }
+
+                offset++;
+            }
+            break;
+        }
+        case DEVICE_CTRL_CLR_INT /* constant-expression */: {
+            uint32_t offset = __builtin_ctz((uint32_t)args);
+
+            while (offset < 24) {
+                if ((uint32_t)args & (1 << offset)) {
+                    USB_IntEn(offset, DISABLE);
+                    USB_IntMask(offset, MASK);
+                }
+
+                offset++;
+            }
+            break;
+        }
+        case DEVICE_CTRL_USB_DC_SET_ACK /* constant-expression */:
+            USB_Set_EPx_Status(USB_EP_GET_IDX(((uint32_t)args) & 0x7f), USB_EP_STATUS_ACK);
+            return 0;
+        case DEVICE_CTRL_USB_DC_ENUM_ON: {
+            uint32_t tmpVal;
+            tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ENUM, 1);
+            BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal);
+            return 0;
+        }
+        case DEVICE_CTRL_USB_DC_ENUM_OFF: {
+            uint32_t tmpVal;
+            tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ENUM, 0);
+            BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal);
+            return 0;
+        }
+        case DEVICE_CTRL_USB_DC_GET_EP_TX_FIFO_CNT:
+            return USB_Get_EPx_TX_FIFO_CNT(((uint32_t)args) & 0x7f);
+
+        case DEVICE_CTRL_USB_DC_GET_EP_RX_FIFO_CNT:
+            return USB_Get_EPx_RX_FIFO_CNT(((uint32_t)args) & 0x7f);
+        case DEVICE_CTRL_ATTACH_TX_DMA /* constant-expression */:
+            usb_device->tx_dma = (struct device *)args;
+            break;
+
+        case DEVICE_CTRL_ATTACH_RX_DMA /* constant-expression */:
+            usb_device->rx_dma = (struct device *)args;
+            break;
+
+        case DEVICE_CTRL_USB_DC_SET_TX_DMA /* constant-expression */:
+            USB_Set_EPx_TX_DMA_Interface_Config(((uint32_t)args) & 0x7f, ENABLE);
+            break;
+
+        case DEVICE_CTRL_USB_DC_SET_RX_DMA /* constant-expression */:
+            USB_Set_EPx_RX_DMA_Interface_Config(((uint32_t)args) & 0x7f, ENABLE);
+            break;
+
+        default:
+            break;
+    }
+
+    return 0;
+}
+
+int usb_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
+{
+    struct usb_dc_device *usb_device = (struct usb_dc_device *)dev;
+    uint8_t ep_idx = USB_EP_GET_IDX(pos);
+
+    if (usb_device->in_ep[ep_idx].ep_cfg.ep_type == USBD_EP_TYPE_ISOC) {
+        uint32_t usb_ep_addr = USB_BASE + 0x308 + ep_idx * 0x10;
+
+        dma_channel_stop(usb_device->tx_dma);
+        usb_lli_list.src_addr = (uint32_t)buffer;
+        usb_lli_list.dst_addr = usb_ep_addr;
+        usb_lli_list.cfg.bits.TransferSize = size;
+        usb_lli_list.cfg.bits.DI = 0;
+        usb_lli_list.cfg.bits.SI = 1;
+        usb_lli_list.cfg.bits.SBSize = DMA_BURST_16BYTE;
+        usb_lli_list.cfg.bits.DBSize = DMA_BURST_1BYTE;
+        dma_channel_update(usb_device->tx_dma, (void *)((uint32_t)&usb_lli_list));
+        dma_channel_start(usb_device->tx_dma);
+        return 0;
+    } else {
+    }
+
+    return -1;
+}
+
+int usb_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
+{
+    struct usb_dc_device *usb_device = (struct usb_dc_device *)dev;
+    uint8_t ep_idx = USB_EP_GET_IDX(pos);
+
+    if (usb_device->out_ep[ep_idx].ep_cfg.ep_type == USBD_EP_TYPE_ISOC) {
+        uint32_t usb_ep_addr = USB_BASE + 0x308 + ep_idx * 0x1c;
+
+        dma_channel_stop(usb_device->tx_dma);
+        usb_lli_list.src_addr = usb_ep_addr;
+        usb_lli_list.dst_addr = (uint32_t)buffer;
+        usb_lli_list.cfg.bits.TransferSize = size;
+        usb_lli_list.cfg.bits.DI = 1;
+        usb_lli_list.cfg.bits.SI = 0;
+        usb_lli_list.cfg.bits.SBSize = DMA_BURST_1BYTE;
+        usb_lli_list.cfg.bits.DBSize = DMA_BURST_16BYTE;
+        dma_channel_update(usb_device->rx_dma, (void *)((uint32_t)&usb_lli_list));
+        dma_channel_start(usb_device->rx_dma);
+        return 0;
+    } else {
+    }
+
+    return -1;
+}
+
+/**
+ * @brief
+ *
+ * @param index
+ * @param name
+ * @param flag
+ * @return int
+ */
+int usb_dc_register(enum usb_index_type index, const char *name)
+{
+    struct device *dev;
+
+    if (USB_MAX_INDEX == 0) {
+        return -DEVICE_EINVAL;
+    }
+
+    dev = &(usb_fs_device.parent);
+
+    dev->open = usb_open;
+    dev->close = usb_close;
+    dev->control = usb_control;
+    dev->write = usb_write;
+    dev->read = usb_read;
+
+    dev->type = DEVICE_CLASS_USB;
+    dev->handle = NULL;
+
+    return device_register(dev, name);
+}
+
+/**
+ * @brief Set USB device address
+ *
+ * @param[in] addr Device address
+ *
+ * @return 0 on success, negative errno code on fail.
+ */
+int usb_dc_set_dev_address(const uint8_t addr)
+{
+    USB_Set_Device_Addr(addr);
+    return 0;
+}
+
+/**
+ * @brief configure and enable endpoint
+ * This function sets endpoint configuration according to one specified in USB
+ * endpoint descriptor and then enables it for data transfers.
+ *
+ * @param dev
+ * @param ep_cfg  ep_cfg Endpoint
+ * @return int
+ */
+int usb_dc_ep_open(struct device *dev, const struct usb_dc_ep_cfg *ep_cfg)
+{
+    uint8_t ep;
+    EP_Config_Type epCfg;
+
+    if (!ep_cfg) {
+        return -1;
+    }
+
+    ep = ep_cfg->ep_addr;
+
+    uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+    USB_DC_LOG_DBG("%s ep %x, mps %d, type %d\r\n", __func__, ep, ep_cfg->ep_mps, ep_cfg->ep_type);
+
+    if (ep_idx == 0) {
+        return 0;
+    }
+
+    if (USB_EP_DIR_IS_OUT(ep)) {
+        epCfg.dir = EP_OUT;
+        epCfg.EPMaxPacketSize = ep_cfg->ep_mps;
+        usb_fs_device.out_ep[ep_idx].ep_cfg.ep_mps = ep_cfg->ep_mps;
+        usb_fs_device.out_ep[ep_idx].ep_cfg.ep_type = ep_cfg->ep_type;
+    } else {
+        epCfg.dir = EP_IN;
+        epCfg.EPMaxPacketSize = ep_cfg->ep_mps;
+        usb_fs_device.in_ep[ep_idx].ep_cfg.ep_mps = ep_cfg->ep_mps;
+        usb_fs_device.in_ep[ep_idx].ep_cfg.ep_type = ep_cfg->ep_type;
+    }
+
+    switch (ep_cfg->ep_type) {
+        case USBD_EP_TYPE_CTRL:
+            epCfg.type = USB_DC_EP_TYPE_CTRL;
+            break;
+
+        case USBD_EP_TYPE_ISOC:
+            epCfg.type = USB_DC_EP_TYPE_ISOC;
+            break;
+
+        case USBD_EP_TYPE_BULK:
+            epCfg.type = USB_DC_EP_TYPE_BULK;
+            break;
+
+        case USBD_EP_TYPE_INTR:
+            epCfg.type = USB_DC_EP_TYPE_INTR;
+            break;
+
+        default:
+            return -1;
+    }
+
+    USB_Set_EPx_Config(ep_idx, &epCfg);
+
+    if (USB_EP_DIR_IS_OUT(ep)) {
+        /* Clear NAK and enable ep */
+        USB_Set_EPx_Status(USB_EP_GET_IDX(ep), USB_EP_STATUS_ACK);
+        usb_fs_device.out_ep[ep_idx].ep_ena = 1U;
+    } else {
+        //USB_Set_EPx_Status(USB_EP_GET_IDX(ep), USB_EP_STATUS_ACK);
+        USB_Set_EPx_Status(USB_EP_GET_IDX(ep), USB_EP_STATUS_NACK);
+        usb_fs_device.in_ep[ep_idx].ep_ena = 1U;
+    }
+
+    return 0;
+}
+
+int usb_dc_ep_close(const uint8_t ep)
+{
+    return 0;
+}
+
+/**
+ * @brief Set stall condition for the selected endpoint
+ *
+ * @param[in] ep Endpoint address corresponding to the one
+ *               listed in the device configuration table
+ *
+ * @return 0 on success, negative errno code on fail.
+ */
+int usb_dc_ep_set_stall(const uint8_t ep)
+{
+    uint32_t tmpVal = 0;
+    uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+    if (USB_EP_DIR_IS_OUT(ep)) {
+        usb_fs_device.out_ep[ep_idx].is_stalled = 1U;
+    } else {
+        usb_fs_device.in_ep[ep_idx].is_stalled = 1U;
+    }
+
+    switch (ep_idx) {
+        case 0:
+            tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_STALL);
+            BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
+            break;
+        case 1:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_STALL);
+            BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
+            break;
+        case 2:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_STALL);
+            BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
+            break;
+        case 3:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_STALL);
+            BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
+            break;
+        case 4:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_STALL);
+            BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
+            break;
+        case 5:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_STALL);
+            BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
+            break;
+        case 6:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_STALL);
+            BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
+            break;
+        case 7:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_STALL);
+            BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
+            break;
+
+        default:
+            break;
+    }
+    return 0;
+}
+/**
+ * @brief Clear stall condition for the selected endpoint
+ *
+ * @param[in] ep Endpoint address corresponding to the one
+ *               listed in the device configuration table
+ *
+ * @return 0 on success, negative errno code on fail.
+ */
+int usb_dc_ep_clear_stall(const uint8_t ep)
+{
+    uint8_t ep_idx = USB_EP_GET_IDX(ep);
+    uint32_t tmpVal = 0;
+    if (USB_EP_DIR_IS_OUT(ep)) {
+        usb_fs_device.out_ep[ep_idx].is_stalled = 0;
+    } else {
+        usb_fs_device.in_ep[ep_idx].is_stalled = 0;
+    }
+    switch (ep_idx) {
+        case 0:
+            break;
+        case 1:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_RDY);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_NACK);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP1_STALL);
+            BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
+            break;
+        case 2:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_RDY);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_NACK);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP2_STALL);
+            BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
+            break;
+        case 3:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_RDY);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_NACK);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP3_STALL);
+            BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
+            break;
+        case 4:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_RDY);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_NACK);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP4_STALL);
+            BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
+            break;
+        case 5:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_RDY);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_NACK);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP5_STALL);
+            BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
+            break;
+        case 6:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_RDY);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_NACK);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP6_STALL);
+            BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
+            break;
+        case 7:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_RDY);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_NACK);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP7_STALL);
+            BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
+            break;
+
+        default:
+            break;
+    }
+    return 0;
+}
+
+/**
+ * @brief Check if the selected endpoint is stalled
+ *
+ * @param dev usb device
+ * @param[in]  ep       Endpoint address corresponding to the one
+ *                      listed in the device configuration table
+ * @param[out] stalled  Endpoint stall status
+ *
+ * @return 0 on success, negative errno code on fail.
+ */
+int usb_dc_ep_is_stalled(struct device *dev, const uint8_t ep, uint8_t *stalled)
+{
+    uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+    if (!stalled) {
+        return -1;
+    }
+
+    *stalled = 0U;
+
+    if (USB_EP_DIR_IS_OUT(ep)) {
+        if ((USB_Get_EPx_Status(ep_idx) & USB_EP_STATUS_STALL) && usb_fs_device.out_ep[ep_idx].is_stalled) {
+            *stalled = 1U;
+        }
+    } else {
+        if ((USB_Get_EPx_Status(ep_idx) & USB_EP_STATUS_STALL) && usb_fs_device.in_ep[ep_idx].is_stalled) {
+            *stalled = 1U;
+        }
+    }
+
+    return 0;
+}
+
+/**
+ * @brief Write data to the specified endpoint
+ *
+ * This function is called to write data to the specified endpoint. The
+ * supplied usbd_endpoint_callback function will be called when data is transmitted
+ * out.
+ *
+ * @param dev
+ * @param[in]  ep        Endpoint address corresponding to the one
+ *                       listed in the device configuration table
+ * @param[in]  data      Pointer to data to write
+ * @param[in]  data_len  Length of the data requested to write. This may
+ *                       be zero for a zero length status packet.
+ * @param[out] ret_bytes Bytes scheduled for transmission. This value
+ *                       may be NULL if the application expects all
+ *                       bytes to be written
+ *
+ * @return 0 on success, negative errno code on fail.
+ */
+int usb_dc_ep_write(struct device *dev, const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes)
+{
+    uint8_t ep_idx;
+    uint32_t timeout = 0x00FFFFFF;
+    uint32_t ep_tx_fifo_addr;
+
+    ep_idx = USB_EP_GET_IDX(ep);
+
+    /* Check if IN ep */
+    if (USB_EP_GET_DIR(ep) != USB_EP_DIR_IN) {
+        return -USB_DC_EP_DIR_ERR;
+    }
+
+    /* Check if ep enabled */
+    if (!usb_ep_is_enabled(ep)) {
+        return -USB_DC_EP_EN_ERR;
+    }
+
+    if (!data && data_len) {
+        USB_DC_LOG_ERR("data is null\r\n");
+        return -USB_DC_ADDR_ERR;
+    }
+
+    /* Check if ep free */
+    while (!USB_Is_EPx_RDY_Free(ep_idx) && (usb_fs_device.in_ep[ep_idx].ep_cfg.ep_type != USBD_EP_TYPE_ISOC)) {
+        timeout--;
+
+        if (!timeout) {
+            USB_DC_LOG_ERR("ep%d wait free timeout\r\n", ep);
+            return -USB_DC_EP_TIMEOUT_ERR;
+        }
+    }
+
+    if (!data_len) {
+        /* Zero length packet */
+        if ((USB_EP_GET_IDX(ep) != 0)) {
+            /* Clear NAK and enable ep */
+            USB_Set_EPx_Rdy(USB_EP_GET_IDX(ep));
+            return USB_DC_OK;
+        }
+        return USB_DC_OK;
+    }
+
+    if (data_len > usb_fs_device.in_ep[ep_idx].ep_cfg.ep_mps) {
+        /* Check if transfer len is too big */
+        data_len = usb_fs_device.in_ep[ep_idx].ep_cfg.ep_mps;
+    }
+
+    /* Wait for FIFO space available */
+    do {
+        uint32_t avail_space = USB_Get_EPx_TX_FIFO_CNT(ep_idx);
+
+        if (avail_space >= usb_fs_device.in_ep[ep_idx].ep_cfg.ep_mps) {
+            break;
+        }
+
+        //USB_DC_LOG_ERR("EP%d have remain data\r\n", ep_idx);
+    } while (1);
+
+    /*
+     * Write data to FIFO, make sure that we are protected against
+     * other USB register accesses.  According to "DesignWare Cores
+     * USB 1.1/2.0 Device Subsystem-AHB/VCI Databook": "During FIFO
+     * access, the application must not access the UDC/Subsystem
+     * registers or vendor registers (for ULPI mode). After starting
+     * to access a FIFO, the application must complete the transaction
+     * before accessing the register."
+     */
+    ep_tx_fifo_addr = USB_BASE + USB_EP0_TX_FIFO_WDATA_OFFSET + ep_idx * 0x10;
+
+    if ((data_len == 1) && (ep_idx == 0)) {
+        USB_Set_EPx_Xfer_Size(EP_ID0, 1);
+    } else if (ep_idx == 0) {
+        USB_Set_EPx_Xfer_Size(EP_ID0, 64);
+    }
+
+    memcopy_to_fifo((void *)ep_tx_fifo_addr, (uint8_t *)data, data_len);
+    /* Clear NAK and enable ep */
+    if (USB_EP_GET_IDX(ep) != 0)
+        USB_Set_EPx_Rdy(USB_EP_GET_IDX(ep));
+    USB_DC_LOG_DBG("EP%d write %u bytes\r\n", ep_idx, data_len);
+
+    if (ret_bytes) {
+        *ret_bytes = data_len;
+    }
+
+    return USB_DC_OK;
+}
+
+/**
+ * @brief Read data from the specified endpoint
+ *
+ * This is similar to usb_dc_ep_read, the difference being that, it doesn't
+ * clear the endpoint NAKs so that the consumer is not bogged down by further
+ * upcalls till he is done with the processing of the data. The caller should
+ * reactivate ep by invoking usb_dc_ep_read_continue() do so.
+ *
+ * @param dev
+ * @param[in]  ep           Endpoint address corresponding to the one
+ *                          listed in the device configuration table
+ * @param[in]  data         Pointer to data buffer to write to
+ * @param[in]  max_data_len Max length of data to read
+ * @param[out] read_bytes   Number of bytes read. If data is NULL and
+ *                          max_data_len is 0 the number of bytes
+ *                          available for read should be returned.
+ *
+ * @return 0 on success, negative errno code on fail.
+ */
+int usb_dc_ep_read(struct device *dev, const uint8_t ep, uint8_t *data, uint32_t data_len, uint32_t *read_bytes)
+{
+    uint8_t ep_idx = USB_EP_GET_IDX(ep);
+    uint32_t read_count;
+    uint32_t ep_rx_fifo_addr;
+    uint32_t timeout = 0x00FFFFFF;
+
+    /* Check if OUT ep */
+    if (USB_EP_GET_DIR(ep) != USB_EP_DIR_OUT) {
+        USB_DC_LOG_ERR("Wrong endpoint direction\r\n");
+        return -USB_DC_EP_DIR_ERR;
+    }
+
+    /* Check if ep enabled */
+    if (!usb_ep_is_enabled(ep)) {
+        USB_DC_LOG_ERR("Not enabled endpoint\r\n");
+        return -USB_DC_EP_EN_ERR;
+    }
+
+    if (!data && data_len) {
+        USB_DC_LOG_ERR("data is null\r\n");
+        return -USB_DC_ADDR_ERR;
+    }
+
+    /* Check if ep free */
+    while (!USB_Is_EPx_RDY_Free(ep_idx) && (usb_fs_device.out_ep[ep_idx].ep_cfg.ep_type != USBD_EP_TYPE_ISOC)) {
+        timeout--;
+
+        if (!timeout) {
+            USB_DC_LOG_ERR("ep%d wait free timeout\r\n", ep);
+            return -USB_DC_EP_TIMEOUT_ERR;
+        }
+    }
+
+    if (!data_len) {
+        if ((USB_EP_GET_IDX(ep) != 0)) {
+            /* Clear NAK and enable ep */
+            USB_Set_EPx_Rdy(USB_EP_GET_IDX(ep));
+            return USB_DC_OK;
+        }
+    }
+
+    read_count = USB_Get_EPx_RX_FIFO_CNT(ep_idx);
+    read_count = MIN(read_count, data_len);
+
+    /* Data in the FIFOs is always stored per 8-bit word*/
+    ep_rx_fifo_addr = (USB_BASE + USB_EP0_RX_FIFO_RDATA_OFFSET + ep_idx * 0x10);
+    fifocopy_to_mem((void *)ep_rx_fifo_addr, data, read_count);
+    USB_DC_LOG_DBG("Read EP%d, req %d, read %d bytes\r\n", ep, data_len, read_count);
+
+    if (read_bytes) {
+        *read_bytes = read_count;
+    }
+
+    return USB_DC_OK;
+}
+/**
+ * @brief
+ *
+ * @param dev
+ * @param rb
+ * @param ep
+ * @return int
+ */
+int usb_dc_receive_to_ringbuffer(struct device *dev, Ring_Buffer_Type *rb, uint8_t ep)
+{
+    uint8_t ep_idx;
+    uint8_t recv_len;
+    static bool overflow_flag = false;
+
+    /* Check if OUT ep */
+    if (USB_EP_GET_DIR(ep) != USB_EP_DIR_OUT) {
+        USB_DC_LOG_ERR("Wrong endpoint direction\r\n");
+        return -USB_DC_EP_DIR_ERR;
+    }
+
+    /* Check if ep enabled */
+    if (!usb_ep_is_enabled(ep)) {
+        return -USB_DC_EP_EN_ERR;
+    }
+
+    ep_idx = USB_EP_GET_IDX(ep);
+
+    recv_len = USB_Get_EPx_RX_FIFO_CNT(ep_idx);
+
+    /*if rx fifo count equal 0,it means last is send nack and ringbuffer is smaller than 64,
+    * so,if ringbuffer is larger than 64,set ack to recv next data.
+    */
+    if (overflow_flag && (Ring_Buffer_Get_Empty_Length(rb) > 64) && (!recv_len)) {
+        overflow_flag = false;
+        USB_Set_EPx_Rdy(ep_idx);
+        return 0;
+    } else {
+        uint32_t addr = USB_BASE + 0x11C + (ep_idx - 1) * 0x10;
+        Ring_Buffer_Write_Callback(rb, recv_len, fifocopy_to_mem, (void *)addr);
+
+        if (Ring_Buffer_Get_Empty_Length(rb) < 64) {
+            overflow_flag = true;
+            return -USB_DC_RB_SIZE_SMALL_ERR;
+        }
+
+        USB_Set_EPx_Rdy(ep_idx);
+        return 0;
+    }
+}
+/**
+ * @brief
+ *
+ * @param dev
+ * @param rb
+ * @param ep
+ * @return int
+ */
+int usb_dc_send_from_ringbuffer(struct device *dev, Ring_Buffer_Type *rb, uint8_t ep)
+{
+    uint8_t ep_idx;
+    static bool zlp_flag = false;
+    static uint32_t send_total_len = 0;
+
+    ep_idx = USB_EP_GET_IDX(ep);
+
+    /* Check if IN ep */
+    if (USB_EP_GET_DIR(ep) != USB_EP_DIR_IN) {
+        return -USB_DC_EP_DIR_ERR;
+    }
+
+    /* Check if ep enabled */
+    if (!usb_ep_is_enabled(ep)) {
+        return -USB_DC_EP_EN_ERR;
+    }
+
+    uint32_t addr = USB_BASE + 0x118 + (ep_idx - 1) * 0x10;
+
+    if (zlp_flag == false) {
+        if ((USB_Get_EPx_TX_FIFO_CNT(ep_idx) == USB_FS_MAX_PACKET_SIZE) && Ring_Buffer_Get_Length(rb)) {
+            uint32_t actual_len = Ring_Buffer_Read_Callback(rb, USB_FS_MAX_PACKET_SIZE, memcopy_to_fifo, (void *)addr);
+            send_total_len += actual_len;
+
+            if (!Ring_Buffer_Get_Length(rb) && (!(send_total_len % 64))) {
+                zlp_flag = true;
+            }
+
+            USB_Set_EPx_Rdy(ep_idx);
+            return 0;
+        } else {
+            return -USB_DC_RB_SIZE_SMALL_ERR;
+        }
+    } else {
+        zlp_flag = false;
+        send_total_len = 0;
+        USB_Set_EPx_Rdy(ep_idx);
+        return -USB_DC_ZLP_ERR;
+    }
+}
+
+/**
+ * @brief
+ *
+ * @param device
+ */
+void usb_dc_isr(usb_dc_device_t *device)
+{
+    USB_EP_ID epnum = EP_ID0;
+
+    /* EP1_DONE -> EP2_DONE -> ...... -> EP7_DONE*/
+    for (USB_INT_Type epint = USB_INT_EP1_DONE; epint <= USB_INT_EP7_DONE; epint += 2) {
+        if (USB_Get_IntStatus(epint)) {
+            epnum = (epint - USB_INT_EP0_OUT_CMD) >> 1;
+            if (!USB_Is_EPx_RDY_Free(epnum) && (device->out_ep[epnum].ep_cfg.ep_type != USBD_EP_TYPE_ISOC)) {
+                USB_DC_LOG_ERR("ep%d out busy\r\n", epnum);
+                continue;
+            }
+            USB_Clr_IntStatus(epint);
+            device->parent.callback(&device->parent, (void *)((uint32_t)USB_SET_EP_OUT(epnum)), 0, USB_DC_EVENT_EP_OUT_NOTIFY);
+        }
+    }
+
+    /* EP1_CMD -> EP2_CMD -> ...... -> EP7_CMD*/
+    for (USB_INT_Type epint = USB_INT_EP1_CMD; epint <= USB_INT_EP7_CMD; epint += 2) {
+        if (USB_Get_IntStatus(epint)) {
+            epnum = (epint - USB_INT_EP0_OUT_CMD) >> 1;
+            if (!USB_Is_EPx_RDY_Free(epnum) && (device->in_ep[epnum].ep_cfg.ep_type != USBD_EP_TYPE_ISOC)) {
+                USB_DC_LOG_DBG("ep%d in busy\r\n", epnum);
+                continue;
+            }
+            USB_Clr_IntStatus(epint);
+            device->parent.callback(&device->parent, (void *)((uint32_t)USB_SET_EP_IN(epnum)), 0, USB_DC_EVENT_EP_IN_NOTIFY);
+        }
+    }
+
+    /* EP0 setup done */
+    if (USB_Get_IntStatus(USB_INT_EP0_SETUP_DONE)) {
+        if (!USB_Is_EPx_RDY_Free(0)) {
+            USB_DC_LOG_DBG("ep0 setup busy\r\n");
+            return;
+        }
+        USB_Clr_IntStatus(USB_INT_EP0_SETUP_DONE);
+        device->parent.callback(&device->parent, NULL, 0, USB_DC_EVENT_SETUP_NOTIFY);
+        USB_Set_EPx_Rdy(EP_ID0);
+        return;
+    }
+
+    /* EP0 in done */
+    if (USB_Get_IntStatus(USB_INT_EP0_IN_DONE)) {
+        if (!USB_Is_EPx_RDY_Free(0)) {
+            USB_DC_LOG_DBG("ep0 in busy\r\n");
+            return;
+        }
+        USB_Clr_IntStatus(USB_INT_EP0_IN_DONE);
+        device->parent.callback(&device->parent, (void *)0x80, 0, USB_DC_EVENT_EP0_IN_NOTIFY);
+        USB_Set_EPx_Rdy(EP_ID0);
+        return;
+    }
+
+    /* EP0 out done */
+    if (USB_Get_IntStatus(USB_INT_EP0_OUT_DONE)) {
+        if (!USB_Is_EPx_RDY_Free(0)) {
+            USB_DC_LOG_DBG("ep0 out busy\r\n");
+            return;
+        }
+        USB_Clr_IntStatus(USB_INT_EP0_OUT_DONE);
+        device->parent.callback(&device->parent, (void *)0x00, 0, USB_DC_EVENT_EP0_OUT_NOTIFY);
+        USB_Set_EPx_Rdy(EP_ID0);
+        return;
+    }
+
+    /* sof */
+    if (USB_Get_IntStatus(USB_INT_SOF)) {
+        USB_Clr_IntStatus(USB_INT_SOF);
+        device->parent.callback(&device->parent, NULL, 0, USB_DC_EVENT_SOF);
+        return;
+    }
+
+    /* reset */
+    if (USB_Get_IntStatus(USB_INT_RESET)) {
+        USB_Clr_IntStatus(USB_INT_RESET);
+        device->parent.callback(&device->parent, NULL, 0, USB_DC_EVENT_RESET);
+        return;
+    }
+
+    /* reset end */
+    if (USB_Get_IntStatus(USB_INT_RESET_END)) {
+        USB_Clr_IntStatus(USB_INT_RESET_END);
+        USB_Set_EPx_Rdy(EP_ID0);
+        return;
+    }
+
+    /* vbus toggle */
+    if (USB_Get_IntStatus(USB_INT_VBUS_TGL)) {
+        USB_Clr_IntStatus(USB_INT_VBUS_TGL);
+        return;
+    }
+#ifdef ENABLE_LPM_INT
+    /* LPM wakeup */
+    if (USB_Get_IntStatus(USB_INT_LPM_WAKEUP)) {
+        USB_Clr_IntStatus(USB_INT_LPM_WAKEUP);
+        return;
+    }
+
+    /* LPM packet */
+    if (USB_Get_IntStatus(USB_INT_LPM_PACKET)) {
+        /*************************************/
+        /* Force low-power mode in the macrocell */
+        if (USB_Get_IntStatus(USB_INT_LPM_WAKEUP) == 0) {
+        }
+
+        /*************************************/
+        USB_Clr_IntStatus(USB_INT_LPM_PACKET);
+        return;
+    }
+#endif
+#ifdef ENABLE_SOF3MS_INT
+    /* lost 3 SOF */
+    if (USB_Get_IntStatus(USB_INT_LOST_SOF_3_TIMES)) {
+        USB_DC_LOG_ERR("Lost 3 SOFs\r\n");
+        /*************************************/
+        /*************************************/
+        USB_Clr_IntStatus(USB_INT_LOST_SOF_3_TIMES);
+        return;
+    }
+#endif
+#ifdef ENABLE_ERROR_INT
+    /* error */
+    if (USB_Get_IntStatus(USB_INT_ERROR)) {
+        USB_DC_LOG("USB bus error 0x%08x; EP2 fifo status 0x%08x\r\n", *(volatile uint32_t *)(0x4000D81C), *(volatile uint32_t *)(0x4000D920));
+        /*************************************/
+        /*************************************/
+        device->parent.callback(&device->parent, NULL, 0, USB_DC_EVENT_ERROR);
+        USB_Clr_IntStatus(USB_INT_ERROR);
+        return;
+    }
+#endif
+}
+/**
+ * @brief
+ *
+ */
+void USB_FS_IRQ(void)
+{
+    usb_dc_isr(&usb_fs_device);
+}
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_wdt.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_wdt.c
new file mode 100644
index 00000000..8b9ace43
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_wdt.c
@@ -0,0 +1,179 @@
+/**
+ * @file hal_wdt.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "hal_wdt.h"
+#include "bl702_timer.h"
+
+#ifdef BSP_USING_WDT
+void WDT_IRQ(void);
+#endif
+
+static wdt_device_t wdtx_device[WDT_MAX_INDEX] = {
+#ifdef BSP_USING_WDT
+    WDT_CONFIG,
+#endif
+};
+
+int wdt_open(struct device *dev, uint16_t oflag)
+{
+    // uint32_t tmpval;
+
+    /* watchdog timer disable*/
+    // tmpval = BL_RD_REG(TIMER_BASE, TIMER_WMER);
+    // BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_CLR_REG_BIT(tmpval, TIMER_WE));
+    // // MSG("wdt timeout %d \r\n", wdt_device->wdt_timeout);
+    // /* Set watchdog timer match register value */
+    // BL_WR_REG(TIMER_BASE, TIMER_WMR, (uint16_t)wdt_device->wdt_timeout);
+
+    if (oflag & DEVICE_OFLAG_INT_TX) {
+#ifdef BSP_USING_WDT
+        wdt_device_t *wdt_device = (wdt_device_t *)dev;
+        // WDT_IntMask(WDT_INT, UNMASK);
+        if (wdt_device->id == 0) {
+            Interrupt_Handler_Register(TIMER_WDT_IRQn, WDT_IRQ);
+        }
+#endif
+    } else {
+        WDT_IntMask(WDT_INT, MASK);
+    }
+
+    // /* enable watchdog timer */
+    WDT_Enable();
+    return 0;
+}
+
+int wdt_close(struct device *dev)
+{
+    // wdt_device_t *wdt_device = (wdt_device_t *)(dev);
+    WDT_Disable();
+    return 0;
+}
+
+int wdt_control(struct device *dev, int cmd, void *args)
+{
+    // wdt_device_t *wdt_device = (wdt_device_t *)dev;
+
+    switch (cmd) {
+        case DEVICE_CTRL_SET_INT: {
+            WDT_IntMask(WDT_INT, UNMASK);
+            CPU_Interrupt_Pending_Clear(TIMER_WDT_IRQn);
+            CPU_Interrupt_Enable(TIMER_WDT_IRQn);
+            break;
+        }
+        case DEVICE_CTRL_CLR_INT: {
+            WDT_IntMask(WDT_INT, MASK);
+            CPU_Interrupt_Disable(TIMER_WDT_IRQn);
+            break;
+        }
+        case DEVICE_CTRL_CONFIG: {
+            break;
+        }
+        case DEVICE_CTRL_RESUME: {
+            WDT_Enable();
+            break;
+        }
+        case DEVICE_CTRL_SUSPEND: {
+            WDT_Disable();
+            break;
+        }
+        case DEVICE_CTRL_GET_WDT_COUNTER: {
+            return WDT_GetCounterValue();
+            break;
+        }
+        case DEVICE_CTRL_RST_WDT_COUNTER: {
+            WDT_ResetCounterValue();
+            break;
+        }
+        case DEVICE_CTRL_GET_RST_STATUS: {
+            return WDT_GetResetStatus();
+            break;
+        }
+        case DEVICE_CTRL_CLR_RST_STATUS: {
+            WDT_ClearResetStatus();
+            break;
+        }
+        default:
+            break;
+    }
+
+    return 0;
+}
+
+int wdt_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
+{
+    // wdt_device_t *wdt_device = (wdt_device_t *)dev;
+    uint16_t wdt_timeout = (uint16_t)(uint32_t)buffer;
+
+    WDT_Disable();
+    WDT_SetCompValue(wdt_timeout);
+    WDT_Enable();
+
+    return 0;
+}
+
+int wdt_register(enum wdt_index_type index, const char *name)
+{
+    struct device *dev;
+
+    if (WDT_MAX_INDEX == 0) {
+        return -DEVICE_EINVAL;
+    }
+
+    dev = &(wdtx_device[index].parent);
+
+    dev->open = wdt_open;
+    dev->close = wdt_close;
+    dev->control = wdt_control;
+    dev->write = wdt_write;
+    // dev->read = NULL;
+
+    dev->status = DEVICE_UNREGISTER;
+    dev->type = DEVICE_CLASS_TIMER;
+    dev->handle = NULL;
+
+    return device_register(dev, name);
+}
+
+void wdt_isr(wdt_device_t *handle)
+{
+    uint32_t tmpval;
+
+    if (!handle->parent.callback) {
+        return;
+    }
+
+    tmpval = BL_RD_REG(TIMER_BASE, TIMER_WICR);
+    BL_WR_REG(TIMER_BASE, TIMER_WICR, BL_SET_REG_BIT(tmpval, TIMER_WICLR));
+
+    handle->parent.callback(&handle->parent, NULL, 0, WDT_EVENT);
+}
+
+#ifdef BSP_USING_WDT
+/**
+ * @brief
+ *
+ */
+void WDT_IRQ(void)
+{
+    wdt_isr(&wdtx_device[WDT_INDEX]);
+}
+#endif
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/aon_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/aon_reg.h
new file mode 100644
index 00000000..bb581832
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/aon_reg.h
@@ -0,0 +1,1579 @@
+/**
+  ******************************************************************************
+  * @file    aon_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __AON_REG_H__
+#define __AON_REG_H__
+
+#include "bl702.h"
+
+/* 0x800 : aon */
+#define AON_OFFSET                     (0x800)
+#define AON_RESV                       AON_RESV
+#define AON_RESV_POS                   (0U)
+#define AON_RESV_LEN                   (8U)
+#define AON_RESV_MSK                   (((1U << AON_RESV_LEN) - 1) << AON_RESV_POS)
+#define AON_RESV_UMSK                  (~(((1U << AON_RESV_LEN) - 1) << AON_RESV_POS))
+#define AON_PU_AON_DC_TBUF             AON_PU_AON_DC_TBUF
+#define AON_PU_AON_DC_TBUF_POS         (12U)
+#define AON_PU_AON_DC_TBUF_LEN         (1U)
+#define AON_PU_AON_DC_TBUF_MSK         (((1U << AON_PU_AON_DC_TBUF_LEN) - 1) << AON_PU_AON_DC_TBUF_POS)
+#define AON_PU_AON_DC_TBUF_UMSK        (~(((1U << AON_PU_AON_DC_TBUF_LEN) - 1) << AON_PU_AON_DC_TBUF_POS))
+#define AON_LDO11_RT_PULLDOWN          AON_LDO11_RT_PULLDOWN
+#define AON_LDO11_RT_PULLDOWN_POS      (20U)
+#define AON_LDO11_RT_PULLDOWN_LEN      (1U)
+#define AON_LDO11_RT_PULLDOWN_MSK      (((1U << AON_LDO11_RT_PULLDOWN_LEN) - 1) << AON_LDO11_RT_PULLDOWN_POS)
+#define AON_LDO11_RT_PULLDOWN_UMSK     (~(((1U << AON_LDO11_RT_PULLDOWN_LEN) - 1) << AON_LDO11_RT_PULLDOWN_POS))
+#define AON_LDO11_RT_PULLDOWN_SEL      AON_LDO11_RT_PULLDOWN_SEL
+#define AON_LDO11_RT_PULLDOWN_SEL_POS  (21U)
+#define AON_LDO11_RT_PULLDOWN_SEL_LEN  (1U)
+#define AON_LDO11_RT_PULLDOWN_SEL_MSK  (((1U << AON_LDO11_RT_PULLDOWN_SEL_LEN) - 1) << AON_LDO11_RT_PULLDOWN_SEL_POS)
+#define AON_LDO11_RT_PULLDOWN_SEL_UMSK (~(((1U << AON_LDO11_RT_PULLDOWN_SEL_LEN) - 1) << AON_LDO11_RT_PULLDOWN_SEL_POS))
+#define AON_SW_PU_LDO11_RT             AON_SW_PU_LDO11_RT
+#define AON_SW_PU_LDO11_RT_POS         (22U)
+#define AON_SW_PU_LDO11_RT_LEN         (1U)
+#define AON_SW_PU_LDO11_RT_MSK         (((1U << AON_SW_PU_LDO11_RT_LEN) - 1) << AON_SW_PU_LDO11_RT_POS)
+#define AON_SW_PU_LDO11_RT_UMSK        (~(((1U << AON_SW_PU_LDO11_RT_LEN) - 1) << AON_SW_PU_LDO11_RT_POS))
+
+/* 0x804 : aon_common */
+#define AON_COMMON_OFFSET         (0x804)
+#define AON_TMUX_AON              AON_TMUX_AON
+#define AON_TMUX_AON_POS          (0U)
+#define AON_TMUX_AON_LEN          (3U)
+#define AON_TMUX_AON_MSK          (((1U << AON_TMUX_AON_LEN) - 1) << AON_TMUX_AON_POS)
+#define AON_TMUX_AON_UMSK         (~(((1U << AON_TMUX_AON_LEN) - 1) << AON_TMUX_AON_POS))
+#define AON_TEN_AON               AON_TEN_AON
+#define AON_TEN_AON_POS           (4U)
+#define AON_TEN_AON_LEN           (1U)
+#define AON_TEN_AON_MSK           (((1U << AON_TEN_AON_LEN) - 1) << AON_TEN_AON_POS)
+#define AON_TEN_AON_UMSK          (~(((1U << AON_TEN_AON_LEN) - 1) << AON_TEN_AON_POS))
+#define AON_DTEN_XTAL32K          AON_DTEN_XTAL32K
+#define AON_DTEN_XTAL32K_POS      (5U)
+#define AON_DTEN_XTAL32K_LEN      (1U)
+#define AON_DTEN_XTAL32K_MSK      (((1U << AON_DTEN_XTAL32K_LEN) - 1) << AON_DTEN_XTAL32K_POS)
+#define AON_DTEN_XTAL32K_UMSK     (~(((1U << AON_DTEN_XTAL32K_LEN) - 1) << AON_DTEN_XTAL32K_POS))
+#define AON_TEN_XTAL32K           AON_TEN_XTAL32K
+#define AON_TEN_XTAL32K_POS       (6U)
+#define AON_TEN_XTAL32K_LEN       (1U)
+#define AON_TEN_XTAL32K_MSK       (((1U << AON_TEN_XTAL32K_LEN) - 1) << AON_TEN_XTAL32K_POS)
+#define AON_TEN_XTAL32K_UMSK      (~(((1U << AON_TEN_XTAL32K_LEN) - 1) << AON_TEN_XTAL32K_POS))
+#define AON_TEN_VDDCORE_AON       AON_TEN_VDDCORE_AON
+#define AON_TEN_VDDCORE_AON_POS   (8U)
+#define AON_TEN_VDDCORE_AON_LEN   (1U)
+#define AON_TEN_VDDCORE_AON_MSK   (((1U << AON_TEN_VDDCORE_AON_LEN) - 1) << AON_TEN_VDDCORE_AON_POS)
+#define AON_TEN_VDDCORE_AON_UMSK  (~(((1U << AON_TEN_VDDCORE_AON_LEN) - 1) << AON_TEN_VDDCORE_AON_POS))
+#define AON_TEN_LDO11SOC_AON      AON_TEN_LDO11SOC_AON
+#define AON_TEN_LDO11SOC_AON_POS  (9U)
+#define AON_TEN_LDO11SOC_AON_LEN  (1U)
+#define AON_TEN_LDO11SOC_AON_MSK  (((1U << AON_TEN_LDO11SOC_AON_LEN) - 1) << AON_TEN_LDO11SOC_AON_POS)
+#define AON_TEN_LDO11SOC_AON_UMSK (~(((1U << AON_TEN_LDO11SOC_AON_LEN) - 1) << AON_TEN_LDO11SOC_AON_POS))
+#define AON_TEN_DCDC18_0_AON      AON_TEN_DCDC18_0_AON
+#define AON_TEN_DCDC18_0_AON_POS  (10U)
+#define AON_TEN_DCDC18_0_AON_LEN  (1U)
+#define AON_TEN_DCDC18_0_AON_MSK  (((1U << AON_TEN_DCDC18_0_AON_LEN) - 1) << AON_TEN_DCDC18_0_AON_POS)
+#define AON_TEN_DCDC18_0_AON_UMSK (~(((1U << AON_TEN_DCDC18_0_AON_LEN) - 1) << AON_TEN_DCDC18_0_AON_POS))
+#define AON_TEN_DCDC18_1_AON      AON_TEN_DCDC18_1_AON
+#define AON_TEN_DCDC18_1_AON_POS  (11U)
+#define AON_TEN_DCDC18_1_AON_LEN  (1U)
+#define AON_TEN_DCDC18_1_AON_MSK  (((1U << AON_TEN_DCDC18_1_AON_LEN) - 1) << AON_TEN_DCDC18_1_AON_POS)
+#define AON_TEN_DCDC18_1_AON_UMSK (~(((1U << AON_TEN_DCDC18_1_AON_LEN) - 1) << AON_TEN_DCDC18_1_AON_POS))
+#define AON_TEN_BG_SYS_AON        AON_TEN_BG_SYS_AON
+#define AON_TEN_BG_SYS_AON_POS    (12U)
+#define AON_TEN_BG_SYS_AON_LEN    (1U)
+#define AON_TEN_BG_SYS_AON_MSK    (((1U << AON_TEN_BG_SYS_AON_LEN) - 1) << AON_TEN_BG_SYS_AON_POS)
+#define AON_TEN_BG_SYS_AON_UMSK   (~(((1U << AON_TEN_BG_SYS_AON_LEN) - 1) << AON_TEN_BG_SYS_AON_POS))
+#define AON_TEN_LDO15RF_AON       AON_TEN_LDO15RF_AON
+#define AON_TEN_LDO15RF_AON_POS   (16U)
+#define AON_TEN_LDO15RF_AON_LEN   (1U)
+#define AON_TEN_LDO15RF_AON_MSK   (((1U << AON_TEN_LDO15RF_AON_LEN) - 1) << AON_TEN_LDO15RF_AON_POS)
+#define AON_TEN_LDO15RF_AON_UMSK  (~(((1U << AON_TEN_LDO15RF_AON_LEN) - 1) << AON_TEN_LDO15RF_AON_POS))
+#define AON_TEN_XTAL_AON          AON_TEN_XTAL_AON
+#define AON_TEN_XTAL_AON_POS      (17U)
+#define AON_TEN_XTAL_AON_LEN      (1U)
+#define AON_TEN_XTAL_AON_MSK      (((1U << AON_TEN_XTAL_AON_LEN) - 1) << AON_TEN_XTAL_AON_POS)
+#define AON_TEN_XTAL_AON_UMSK     (~(((1U << AON_TEN_XTAL_AON_LEN) - 1) << AON_TEN_XTAL_AON_POS))
+#define AON_DTEN_XTAL_AON         AON_DTEN_XTAL_AON
+#define AON_DTEN_XTAL_AON_POS     (18U)
+#define AON_DTEN_XTAL_AON_LEN     (1U)
+#define AON_DTEN_XTAL_AON_MSK     (((1U << AON_DTEN_XTAL_AON_LEN) - 1) << AON_DTEN_XTAL_AON_POS)
+#define AON_DTEN_XTAL_AON_UMSK    (~(((1U << AON_DTEN_XTAL_AON_LEN) - 1) << AON_DTEN_XTAL_AON_POS))
+#define AON_TEN_MBG_AON           AON_TEN_MBG_AON
+#define AON_TEN_MBG_AON_POS       (19U)
+#define AON_TEN_MBG_AON_LEN       (1U)
+#define AON_TEN_MBG_AON_MSK       (((1U << AON_TEN_MBG_AON_LEN) - 1) << AON_TEN_MBG_AON_POS)
+#define AON_TEN_MBG_AON_UMSK      (~(((1U << AON_TEN_MBG_AON_LEN) - 1) << AON_TEN_MBG_AON_POS))
+#define AON_TEN_CIP_MISC_AON      AON_TEN_CIP_MISC_AON
+#define AON_TEN_CIP_MISC_AON_POS  (20U)
+#define AON_TEN_CIP_MISC_AON_LEN  (1U)
+#define AON_TEN_CIP_MISC_AON_MSK  (((1U << AON_TEN_CIP_MISC_AON_LEN) - 1) << AON_TEN_CIP_MISC_AON_POS)
+#define AON_TEN_CIP_MISC_AON_UMSK (~(((1U << AON_TEN_CIP_MISC_AON_LEN) - 1) << AON_TEN_CIP_MISC_AON_POS))
+
+/* 0x808 : aon_misc */
+#define AON_MISC_OFFSET        (0x808)
+#define AON_SW_SOC_EN_AON      AON_SW_SOC_EN_AON
+#define AON_SW_SOC_EN_AON_POS  (0U)
+#define AON_SW_SOC_EN_AON_LEN  (1U)
+#define AON_SW_SOC_EN_AON_MSK  (((1U << AON_SW_SOC_EN_AON_LEN) - 1) << AON_SW_SOC_EN_AON_POS)
+#define AON_SW_SOC_EN_AON_UMSK (~(((1U << AON_SW_SOC_EN_AON_LEN) - 1) << AON_SW_SOC_EN_AON_POS))
+#define AON_SW_BZ_EN_AON       AON_SW_BZ_EN_AON
+#define AON_SW_BZ_EN_AON_POS   (1U)
+#define AON_SW_BZ_EN_AON_LEN   (1U)
+#define AON_SW_BZ_EN_AON_MSK   (((1U << AON_SW_BZ_EN_AON_LEN) - 1) << AON_SW_BZ_EN_AON_POS)
+#define AON_SW_BZ_EN_AON_UMSK  (~(((1U << AON_SW_BZ_EN_AON_LEN) - 1) << AON_SW_BZ_EN_AON_POS))
+
+/* 0x810 : bg_sys_top */
+#define AON_BG_SYS_TOP_OFFSET          (0x810)
+#define AON_PMIP_RESV                  AON_PMIP_RESV
+#define AON_PMIP_RESV_POS              (0U)
+#define AON_PMIP_RESV_LEN              (8U)
+#define AON_PMIP_RESV_MSK              (((1U << AON_PMIP_RESV_LEN) - 1) << AON_PMIP_RESV_POS)
+#define AON_PMIP_RESV_UMSK             (~(((1U << AON_PMIP_RESV_LEN) - 1) << AON_PMIP_RESV_POS))
+#define AON_PU_BG_SYS_AON              AON_PU_BG_SYS_AON
+#define AON_PU_BG_SYS_AON_POS          (8U)
+#define AON_PU_BG_SYS_AON_LEN          (1U)
+#define AON_PU_BG_SYS_AON_MSK          (((1U << AON_PU_BG_SYS_AON_LEN) - 1) << AON_PU_BG_SYS_AON_POS)
+#define AON_PU_BG_SYS_AON_UMSK         (~(((1U << AON_PU_BG_SYS_AON_LEN) - 1) << AON_PU_BG_SYS_AON_POS))
+#define AON_BG_SYS_START_CTRL_AON      AON_BG_SYS_START_CTRL_AON
+#define AON_BG_SYS_START_CTRL_AON_POS  (12U)
+#define AON_BG_SYS_START_CTRL_AON_LEN  (1U)
+#define AON_BG_SYS_START_CTRL_AON_MSK  (((1U << AON_BG_SYS_START_CTRL_AON_LEN) - 1) << AON_BG_SYS_START_CTRL_AON_POS)
+#define AON_BG_SYS_START_CTRL_AON_UMSK (~(((1U << AON_BG_SYS_START_CTRL_AON_LEN) - 1) << AON_BG_SYS_START_CTRL_AON_POS))
+
+/* 0x814 : dcdc18_top_0 */
+#define AON_DCDC18_TOP_0_OFFSET            (0x814)
+#define AON_DCDC18_VOUT_SEL_AON            AON_DCDC18_VOUT_SEL_AON
+#define AON_DCDC18_VOUT_SEL_AON_POS        (1U)
+#define AON_DCDC18_VOUT_SEL_AON_LEN        (5U)
+#define AON_DCDC18_VOUT_SEL_AON_MSK        (((1U << AON_DCDC18_VOUT_SEL_AON_LEN) - 1) << AON_DCDC18_VOUT_SEL_AON_POS)
+#define AON_DCDC18_VOUT_SEL_AON_UMSK       (~(((1U << AON_DCDC18_VOUT_SEL_AON_LEN) - 1) << AON_DCDC18_VOUT_SEL_AON_POS))
+#define AON_DCDC18_VPFM_AON                AON_DCDC18_VPFM_AON
+#define AON_DCDC18_VPFM_AON_POS            (8U)
+#define AON_DCDC18_VPFM_AON_LEN            (4U)
+#define AON_DCDC18_VPFM_AON_MSK            (((1U << AON_DCDC18_VPFM_AON_LEN) - 1) << AON_DCDC18_VPFM_AON_POS)
+#define AON_DCDC18_VPFM_AON_UMSK           (~(((1U << AON_DCDC18_VPFM_AON_LEN) - 1) << AON_DCDC18_VPFM_AON_POS))
+#define AON_DCDC18_OSC_2M_MODE_AON         AON_DCDC18_OSC_2M_MODE_AON
+#define AON_DCDC18_OSC_2M_MODE_AON_POS     (12U)
+#define AON_DCDC18_OSC_2M_MODE_AON_LEN     (1U)
+#define AON_DCDC18_OSC_2M_MODE_AON_MSK     (((1U << AON_DCDC18_OSC_2M_MODE_AON_LEN) - 1) << AON_DCDC18_OSC_2M_MODE_AON_POS)
+#define AON_DCDC18_OSC_2M_MODE_AON_UMSK    (~(((1U << AON_DCDC18_OSC_2M_MODE_AON_LEN) - 1) << AON_DCDC18_OSC_2M_MODE_AON_POS))
+#define AON_DCDC18_OSC_FREQ_TRIM_AON       AON_DCDC18_OSC_FREQ_TRIM_AON
+#define AON_DCDC18_OSC_FREQ_TRIM_AON_POS   (16U)
+#define AON_DCDC18_OSC_FREQ_TRIM_AON_LEN   (4U)
+#define AON_DCDC18_OSC_FREQ_TRIM_AON_MSK   (((1U << AON_DCDC18_OSC_FREQ_TRIM_AON_LEN) - 1) << AON_DCDC18_OSC_FREQ_TRIM_AON_POS)
+#define AON_DCDC18_OSC_FREQ_TRIM_AON_UMSK  (~(((1U << AON_DCDC18_OSC_FREQ_TRIM_AON_LEN) - 1) << AON_DCDC18_OSC_FREQ_TRIM_AON_POS))
+#define AON_DCDC18_SLOPE_CURR_SEL_AON      AON_DCDC18_SLOPE_CURR_SEL_AON
+#define AON_DCDC18_SLOPE_CURR_SEL_AON_POS  (20U)
+#define AON_DCDC18_SLOPE_CURR_SEL_AON_LEN  (5U)
+#define AON_DCDC18_SLOPE_CURR_SEL_AON_MSK  (((1U << AON_DCDC18_SLOPE_CURR_SEL_AON_LEN) - 1) << AON_DCDC18_SLOPE_CURR_SEL_AON_POS)
+#define AON_DCDC18_SLOPE_CURR_SEL_AON_UMSK (~(((1U << AON_DCDC18_SLOPE_CURR_SEL_AON_LEN) - 1) << AON_DCDC18_SLOPE_CURR_SEL_AON_POS))
+#define AON_DCDC18_STOP_OSC_AON            AON_DCDC18_STOP_OSC_AON
+#define AON_DCDC18_STOP_OSC_AON_POS        (25U)
+#define AON_DCDC18_STOP_OSC_AON_LEN        (1U)
+#define AON_DCDC18_STOP_OSC_AON_MSK        (((1U << AON_DCDC18_STOP_OSC_AON_LEN) - 1) << AON_DCDC18_STOP_OSC_AON_POS)
+#define AON_DCDC18_STOP_OSC_AON_UMSK       (~(((1U << AON_DCDC18_STOP_OSC_AON_LEN) - 1) << AON_DCDC18_STOP_OSC_AON_POS))
+#define AON_DCDC18_SLOW_OSC_AON            AON_DCDC18_SLOW_OSC_AON
+#define AON_DCDC18_SLOW_OSC_AON_POS        (26U)
+#define AON_DCDC18_SLOW_OSC_AON_LEN        (1U)
+#define AON_DCDC18_SLOW_OSC_AON_MSK        (((1U << AON_DCDC18_SLOW_OSC_AON_LEN) - 1) << AON_DCDC18_SLOW_OSC_AON_POS)
+#define AON_DCDC18_SLOW_OSC_AON_UMSK       (~(((1U << AON_DCDC18_SLOW_OSC_AON_LEN) - 1) << AON_DCDC18_SLOW_OSC_AON_POS))
+#define AON_DCDC18_OSC_INHIBIT_T2_AON      AON_DCDC18_OSC_INHIBIT_T2_AON
+#define AON_DCDC18_OSC_INHIBIT_T2_AON_POS  (27U)
+#define AON_DCDC18_OSC_INHIBIT_T2_AON_LEN  (1U)
+#define AON_DCDC18_OSC_INHIBIT_T2_AON_MSK  (((1U << AON_DCDC18_OSC_INHIBIT_T2_AON_LEN) - 1) << AON_DCDC18_OSC_INHIBIT_T2_AON_POS)
+#define AON_DCDC18_OSC_INHIBIT_T2_AON_UMSK (~(((1U << AON_DCDC18_OSC_INHIBIT_T2_AON_LEN) - 1) << AON_DCDC18_OSC_INHIBIT_T2_AON_POS))
+#define AON_DCDC18_SSTART_TIME_AON         AON_DCDC18_SSTART_TIME_AON
+#define AON_DCDC18_SSTART_TIME_AON_POS     (28U)
+#define AON_DCDC18_SSTART_TIME_AON_LEN     (2U)
+#define AON_DCDC18_SSTART_TIME_AON_MSK     (((1U << AON_DCDC18_SSTART_TIME_AON_LEN) - 1) << AON_DCDC18_SSTART_TIME_AON_POS)
+#define AON_DCDC18_SSTART_TIME_AON_UMSK    (~(((1U << AON_DCDC18_SSTART_TIME_AON_LEN) - 1) << AON_DCDC18_SSTART_TIME_AON_POS))
+#define AON_DCDC18_RDY_AON                 AON_DCDC18_RDY_AON
+#define AON_DCDC18_RDY_AON_POS             (31U)
+#define AON_DCDC18_RDY_AON_LEN             (1U)
+#define AON_DCDC18_RDY_AON_MSK             (((1U << AON_DCDC18_RDY_AON_LEN) - 1) << AON_DCDC18_RDY_AON_POS)
+#define AON_DCDC18_RDY_AON_UMSK            (~(((1U << AON_DCDC18_RDY_AON_LEN) - 1) << AON_DCDC18_RDY_AON_POS))
+
+/* 0x818 : dcdc18_top_1 */
+#define AON_DCDC18_TOP_1_OFFSET           (0x818)
+#define AON_DCDC18_FORCE_CS_ZVS_AON       AON_DCDC18_FORCE_CS_ZVS_AON
+#define AON_DCDC18_FORCE_CS_ZVS_AON_POS   (0U)
+#define AON_DCDC18_FORCE_CS_ZVS_AON_LEN   (1U)
+#define AON_DCDC18_FORCE_CS_ZVS_AON_MSK   (((1U << AON_DCDC18_FORCE_CS_ZVS_AON_LEN) - 1) << AON_DCDC18_FORCE_CS_ZVS_AON_POS)
+#define AON_DCDC18_FORCE_CS_ZVS_AON_UMSK  (~(((1U << AON_DCDC18_FORCE_CS_ZVS_AON_LEN) - 1) << AON_DCDC18_FORCE_CS_ZVS_AON_POS))
+#define AON_DCDC18_CS_DELAY_AON           AON_DCDC18_CS_DELAY_AON
+#define AON_DCDC18_CS_DELAY_AON_POS       (1U)
+#define AON_DCDC18_CS_DELAY_AON_LEN       (3U)
+#define AON_DCDC18_CS_DELAY_AON_MSK       (((1U << AON_DCDC18_CS_DELAY_AON_LEN) - 1) << AON_DCDC18_CS_DELAY_AON_POS)
+#define AON_DCDC18_CS_DELAY_AON_UMSK      (~(((1U << AON_DCDC18_CS_DELAY_AON_LEN) - 1) << AON_DCDC18_CS_DELAY_AON_POS))
+#define AON_DCDC18_ZVS_TD_OPT_AON         AON_DCDC18_ZVS_TD_OPT_AON
+#define AON_DCDC18_ZVS_TD_OPT_AON_POS     (4U)
+#define AON_DCDC18_ZVS_TD_OPT_AON_LEN     (3U)
+#define AON_DCDC18_ZVS_TD_OPT_AON_MSK     (((1U << AON_DCDC18_ZVS_TD_OPT_AON_LEN) - 1) << AON_DCDC18_ZVS_TD_OPT_AON_POS)
+#define AON_DCDC18_ZVS_TD_OPT_AON_UMSK    (~(((1U << AON_DCDC18_ZVS_TD_OPT_AON_LEN) - 1) << AON_DCDC18_ZVS_TD_OPT_AON_POS))
+#define AON_DCDC18_NONOVERLAP_TD_AON      AON_DCDC18_NONOVERLAP_TD_AON
+#define AON_DCDC18_NONOVERLAP_TD_AON_POS  (8U)
+#define AON_DCDC18_NONOVERLAP_TD_AON_LEN  (5U)
+#define AON_DCDC18_NONOVERLAP_TD_AON_MSK  (((1U << AON_DCDC18_NONOVERLAP_TD_AON_LEN) - 1) << AON_DCDC18_NONOVERLAP_TD_AON_POS)
+#define AON_DCDC18_NONOVERLAP_TD_AON_UMSK (~(((1U << AON_DCDC18_NONOVERLAP_TD_AON_LEN) - 1) << AON_DCDC18_NONOVERLAP_TD_AON_POS))
+#define AON_DCDC18_RC_SEL_AON             AON_DCDC18_RC_SEL_AON
+#define AON_DCDC18_RC_SEL_AON_POS         (16U)
+#define AON_DCDC18_RC_SEL_AON_LEN         (4U)
+#define AON_DCDC18_RC_SEL_AON_MSK         (((1U << AON_DCDC18_RC_SEL_AON_LEN) - 1) << AON_DCDC18_RC_SEL_AON_POS)
+#define AON_DCDC18_RC_SEL_AON_UMSK        (~(((1U << AON_DCDC18_RC_SEL_AON_LEN) - 1) << AON_DCDC18_RC_SEL_AON_POS))
+#define AON_DCDC18_CHF_SEL_AON            AON_DCDC18_CHF_SEL_AON
+#define AON_DCDC18_CHF_SEL_AON_POS        (20U)
+#define AON_DCDC18_CHF_SEL_AON_LEN        (4U)
+#define AON_DCDC18_CHF_SEL_AON_MSK        (((1U << AON_DCDC18_CHF_SEL_AON_LEN) - 1) << AON_DCDC18_CHF_SEL_AON_POS)
+#define AON_DCDC18_CHF_SEL_AON_UMSK       (~(((1U << AON_DCDC18_CHF_SEL_AON_LEN) - 1) << AON_DCDC18_CHF_SEL_AON_POS))
+#define AON_DCDC18_CFB_SEL_AON            AON_DCDC18_CFB_SEL_AON
+#define AON_DCDC18_CFB_SEL_AON_POS        (24U)
+#define AON_DCDC18_CFB_SEL_AON_LEN        (4U)
+#define AON_DCDC18_CFB_SEL_AON_MSK        (((1U << AON_DCDC18_CFB_SEL_AON_LEN) - 1) << AON_DCDC18_CFB_SEL_AON_POS)
+#define AON_DCDC18_CFB_SEL_AON_UMSK       (~(((1U << AON_DCDC18_CFB_SEL_AON_LEN) - 1) << AON_DCDC18_CFB_SEL_AON_POS))
+#define AON_DCDC18_EN_ANTIRING_AON        AON_DCDC18_EN_ANTIRING_AON
+#define AON_DCDC18_EN_ANTIRING_AON_POS    (28U)
+#define AON_DCDC18_EN_ANTIRING_AON_LEN    (1U)
+#define AON_DCDC18_EN_ANTIRING_AON_MSK    (((1U << AON_DCDC18_EN_ANTIRING_AON_LEN) - 1) << AON_DCDC18_EN_ANTIRING_AON_POS)
+#define AON_DCDC18_EN_ANTIRING_AON_UMSK   (~(((1U << AON_DCDC18_EN_ANTIRING_AON_LEN) - 1) << AON_DCDC18_EN_ANTIRING_AON_POS))
+#define AON_DCDC18_PULLDOWN_AON           AON_DCDC18_PULLDOWN_AON
+#define AON_DCDC18_PULLDOWN_AON_POS       (29U)
+#define AON_DCDC18_PULLDOWN_AON_LEN       (1U)
+#define AON_DCDC18_PULLDOWN_AON_MSK       (((1U << AON_DCDC18_PULLDOWN_AON_LEN) - 1) << AON_DCDC18_PULLDOWN_AON_POS)
+#define AON_DCDC18_PULLDOWN_AON_UMSK      (~(((1U << AON_DCDC18_PULLDOWN_AON_LEN) - 1) << AON_DCDC18_PULLDOWN_AON_POS))
+
+/* 0x81C : ldo11soc_and_dctest */
+#define AON_LDO11SOC_AND_DCTEST_OFFSET     (0x81C)
+#define AON_PU_LDO11SOC_AON                AON_PU_LDO11SOC_AON
+#define AON_PU_LDO11SOC_AON_POS            (0U)
+#define AON_PU_LDO11SOC_AON_LEN            (1U)
+#define AON_PU_LDO11SOC_AON_MSK            (((1U << AON_PU_LDO11SOC_AON_LEN) - 1) << AON_PU_LDO11SOC_AON_POS)
+#define AON_PU_LDO11SOC_AON_UMSK           (~(((1U << AON_PU_LDO11SOC_AON_LEN) - 1) << AON_PU_LDO11SOC_AON_POS))
+#define AON_LDO11SOC_SSTART_SEL_AON        AON_LDO11SOC_SSTART_SEL_AON
+#define AON_LDO11SOC_SSTART_SEL_AON_POS    (4U)
+#define AON_LDO11SOC_SSTART_SEL_AON_LEN    (1U)
+#define AON_LDO11SOC_SSTART_SEL_AON_MSK    (((1U << AON_LDO11SOC_SSTART_SEL_AON_LEN) - 1) << AON_LDO11SOC_SSTART_SEL_AON_POS)
+#define AON_LDO11SOC_SSTART_SEL_AON_UMSK   (~(((1U << AON_LDO11SOC_SSTART_SEL_AON_LEN) - 1) << AON_LDO11SOC_SSTART_SEL_AON_POS))
+#define AON_LDO11SOC_SSTART_DELAY_AON      AON_LDO11SOC_SSTART_DELAY_AON
+#define AON_LDO11SOC_SSTART_DELAY_AON_POS  (8U)
+#define AON_LDO11SOC_SSTART_DELAY_AON_LEN  (2U)
+#define AON_LDO11SOC_SSTART_DELAY_AON_MSK  (((1U << AON_LDO11SOC_SSTART_DELAY_AON_LEN) - 1) << AON_LDO11SOC_SSTART_DELAY_AON_POS)
+#define AON_LDO11SOC_SSTART_DELAY_AON_UMSK (~(((1U << AON_LDO11SOC_SSTART_DELAY_AON_LEN) - 1) << AON_LDO11SOC_SSTART_DELAY_AON_POS))
+#define AON_LDO11SOC_PULLDOWN_AON          AON_LDO11SOC_PULLDOWN_AON
+#define AON_LDO11SOC_PULLDOWN_AON_POS      (10U)
+#define AON_LDO11SOC_PULLDOWN_AON_LEN      (1U)
+#define AON_LDO11SOC_PULLDOWN_AON_MSK      (((1U << AON_LDO11SOC_PULLDOWN_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_AON_POS)
+#define AON_LDO11SOC_PULLDOWN_AON_UMSK     (~(((1U << AON_LDO11SOC_PULLDOWN_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_AON_POS))
+#define AON_LDO11SOC_PULLDOWN_SEL_AON      AON_LDO11SOC_PULLDOWN_SEL_AON
+#define AON_LDO11SOC_PULLDOWN_SEL_AON_POS  (11U)
+#define AON_LDO11SOC_PULLDOWN_SEL_AON_LEN  (1U)
+#define AON_LDO11SOC_PULLDOWN_SEL_AON_MSK  (((1U << AON_LDO11SOC_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_SEL_AON_POS)
+#define AON_LDO11SOC_PULLDOWN_SEL_AON_UMSK (~(((1U << AON_LDO11SOC_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_SEL_AON_POS))
+#define AON_LDO11SOC_VTH_SEL_AON           AON_LDO11SOC_VTH_SEL_AON
+#define AON_LDO11SOC_VTH_SEL_AON_POS       (12U)
+#define AON_LDO11SOC_VTH_SEL_AON_LEN       (2U)
+#define AON_LDO11SOC_VTH_SEL_AON_MSK       (((1U << AON_LDO11SOC_VTH_SEL_AON_LEN) - 1) << AON_LDO11SOC_VTH_SEL_AON_POS)
+#define AON_LDO11SOC_VTH_SEL_AON_UMSK      (~(((1U << AON_LDO11SOC_VTH_SEL_AON_LEN) - 1) << AON_LDO11SOC_VTH_SEL_AON_POS))
+#define AON_LDO11SOC_CC_AON                AON_LDO11SOC_CC_AON
+#define AON_LDO11SOC_CC_AON_POS            (24U)
+#define AON_LDO11SOC_CC_AON_LEN            (2U)
+#define AON_LDO11SOC_CC_AON_MSK            (((1U << AON_LDO11SOC_CC_AON_LEN) - 1) << AON_LDO11SOC_CC_AON_POS)
+#define AON_LDO11SOC_CC_AON_UMSK           (~(((1U << AON_LDO11SOC_CC_AON_LEN) - 1) << AON_LDO11SOC_CC_AON_POS))
+#define AON_LDO11SOC_RDY_AON               AON_LDO11SOC_RDY_AON
+#define AON_LDO11SOC_RDY_AON_POS           (28U)
+#define AON_LDO11SOC_RDY_AON_LEN           (1U)
+#define AON_LDO11SOC_RDY_AON_MSK           (((1U << AON_LDO11SOC_RDY_AON_LEN) - 1) << AON_LDO11SOC_RDY_AON_POS)
+#define AON_LDO11SOC_RDY_AON_UMSK          (~(((1U << AON_LDO11SOC_RDY_AON_LEN) - 1) << AON_LDO11SOC_RDY_AON_POS))
+#define AON_LDO11SOC_POWER_GOOD_AON        AON_LDO11SOC_POWER_GOOD_AON
+#define AON_LDO11SOC_POWER_GOOD_AON_POS    (29U)
+#define AON_LDO11SOC_POWER_GOOD_AON_LEN    (1U)
+#define AON_LDO11SOC_POWER_GOOD_AON_MSK    (((1U << AON_LDO11SOC_POWER_GOOD_AON_LEN) - 1) << AON_LDO11SOC_POWER_GOOD_AON_POS)
+#define AON_LDO11SOC_POWER_GOOD_AON_UMSK   (~(((1U << AON_LDO11SOC_POWER_GOOD_AON_LEN) - 1) << AON_LDO11SOC_POWER_GOOD_AON_POS))
+#define AON_PU_VDDCORE_MISC_AON            AON_PU_VDDCORE_MISC_AON
+#define AON_PU_VDDCORE_MISC_AON_POS        (30U)
+#define AON_PU_VDDCORE_MISC_AON_LEN        (1U)
+#define AON_PU_VDDCORE_MISC_AON_MSK        (((1U << AON_PU_VDDCORE_MISC_AON_LEN) - 1) << AON_PU_VDDCORE_MISC_AON_POS)
+#define AON_PU_VDDCORE_MISC_AON_UMSK       (~(((1U << AON_PU_VDDCORE_MISC_AON_LEN) - 1) << AON_PU_VDDCORE_MISC_AON_POS))
+#define AON_PMIP_DC_TP_OUT_EN_AON          AON_PMIP_DC_TP_OUT_EN_AON
+#define AON_PMIP_DC_TP_OUT_EN_AON_POS      (31U)
+#define AON_PMIP_DC_TP_OUT_EN_AON_LEN      (1U)
+#define AON_PMIP_DC_TP_OUT_EN_AON_MSK      (((1U << AON_PMIP_DC_TP_OUT_EN_AON_LEN) - 1) << AON_PMIP_DC_TP_OUT_EN_AON_POS)
+#define AON_PMIP_DC_TP_OUT_EN_AON_UMSK     (~(((1U << AON_PMIP_DC_TP_OUT_EN_AON_LEN) - 1) << AON_PMIP_DC_TP_OUT_EN_AON_POS))
+
+/* 0x820 : psw_irrcv */
+#define AON_PSW_IRRCV_OFFSET   (0x820)
+#define AON_PU_IR_PSW_AON      AON_PU_IR_PSW_AON
+#define AON_PU_IR_PSW_AON_POS  (0U)
+#define AON_PU_IR_PSW_AON_LEN  (1U)
+#define AON_PU_IR_PSW_AON_MSK  (((1U << AON_PU_IR_PSW_AON_LEN) - 1) << AON_PU_IR_PSW_AON_POS)
+#define AON_PU_IR_PSW_AON_UMSK (~(((1U << AON_PU_IR_PSW_AON_LEN) - 1) << AON_PU_IR_PSW_AON_POS))
+
+/* 0x880 : rf_top_aon */
+#define AON_RF_TOP_AON_OFFSET             (0x880)
+#define AON_PU_MBG_AON                    AON_PU_MBG_AON
+#define AON_PU_MBG_AON_POS                (0U)
+#define AON_PU_MBG_AON_LEN                (1U)
+#define AON_PU_MBG_AON_MSK                (((1U << AON_PU_MBG_AON_LEN) - 1) << AON_PU_MBG_AON_POS)
+#define AON_PU_MBG_AON_UMSK               (~(((1U << AON_PU_MBG_AON_LEN) - 1) << AON_PU_MBG_AON_POS))
+#define AON_PU_LDO15RF_AON                AON_PU_LDO15RF_AON
+#define AON_PU_LDO15RF_AON_POS            (1U)
+#define AON_PU_LDO15RF_AON_LEN            (1U)
+#define AON_PU_LDO15RF_AON_MSK            (((1U << AON_PU_LDO15RF_AON_LEN) - 1) << AON_PU_LDO15RF_AON_POS)
+#define AON_PU_LDO15RF_AON_UMSK           (~(((1U << AON_PU_LDO15RF_AON_LEN) - 1) << AON_PU_LDO15RF_AON_POS))
+#define AON_PU_SFREG_AON                  AON_PU_SFREG_AON
+#define AON_PU_SFREG_AON_POS              (2U)
+#define AON_PU_SFREG_AON_LEN              (1U)
+#define AON_PU_SFREG_AON_MSK              (((1U << AON_PU_SFREG_AON_LEN) - 1) << AON_PU_SFREG_AON_POS)
+#define AON_PU_SFREG_AON_UMSK             (~(((1U << AON_PU_SFREG_AON_LEN) - 1) << AON_PU_SFREG_AON_POS))
+#define AON_PU_XTAL_BUF_AON               AON_PU_XTAL_BUF_AON
+#define AON_PU_XTAL_BUF_AON_POS           (4U)
+#define AON_PU_XTAL_BUF_AON_LEN           (1U)
+#define AON_PU_XTAL_BUF_AON_MSK           (((1U << AON_PU_XTAL_BUF_AON_LEN) - 1) << AON_PU_XTAL_BUF_AON_POS)
+#define AON_PU_XTAL_BUF_AON_UMSK          (~(((1U << AON_PU_XTAL_BUF_AON_LEN) - 1) << AON_PU_XTAL_BUF_AON_POS))
+#define AON_PU_XTAL_AON                   AON_PU_XTAL_AON
+#define AON_PU_XTAL_AON_POS               (5U)
+#define AON_PU_XTAL_AON_LEN               (1U)
+#define AON_PU_XTAL_AON_MSK               (((1U << AON_PU_XTAL_AON_LEN) - 1) << AON_PU_XTAL_AON_POS)
+#define AON_PU_XTAL_AON_UMSK              (~(((1U << AON_PU_XTAL_AON_LEN) - 1) << AON_PU_XTAL_AON_POS))
+#define AON_LDO15RF_SSTART_SEL_AON        AON_LDO15RF_SSTART_SEL_AON
+#define AON_LDO15RF_SSTART_SEL_AON_POS    (8U)
+#define AON_LDO15RF_SSTART_SEL_AON_LEN    (1U)
+#define AON_LDO15RF_SSTART_SEL_AON_MSK    (((1U << AON_LDO15RF_SSTART_SEL_AON_LEN) - 1) << AON_LDO15RF_SSTART_SEL_AON_POS)
+#define AON_LDO15RF_SSTART_SEL_AON_UMSK   (~(((1U << AON_LDO15RF_SSTART_SEL_AON_LEN) - 1) << AON_LDO15RF_SSTART_SEL_AON_POS))
+#define AON_LDO15RF_SSTART_DELAY_AON      AON_LDO15RF_SSTART_DELAY_AON
+#define AON_LDO15RF_SSTART_DELAY_AON_POS  (9U)
+#define AON_LDO15RF_SSTART_DELAY_AON_LEN  (2U)
+#define AON_LDO15RF_SSTART_DELAY_AON_MSK  (((1U << AON_LDO15RF_SSTART_DELAY_AON_LEN) - 1) << AON_LDO15RF_SSTART_DELAY_AON_POS)
+#define AON_LDO15RF_SSTART_DELAY_AON_UMSK (~(((1U << AON_LDO15RF_SSTART_DELAY_AON_LEN) - 1) << AON_LDO15RF_SSTART_DELAY_AON_POS))
+#define AON_LDO15RF_PULLDOWN_AON          AON_LDO15RF_PULLDOWN_AON
+#define AON_LDO15RF_PULLDOWN_AON_POS      (12U)
+#define AON_LDO15RF_PULLDOWN_AON_LEN      (1U)
+#define AON_LDO15RF_PULLDOWN_AON_MSK      (((1U << AON_LDO15RF_PULLDOWN_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_AON_POS)
+#define AON_LDO15RF_PULLDOWN_AON_UMSK     (~(((1U << AON_LDO15RF_PULLDOWN_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_AON_POS))
+#define AON_LDO15RF_PULLDOWN_SEL_AON      AON_LDO15RF_PULLDOWN_SEL_AON
+#define AON_LDO15RF_PULLDOWN_SEL_AON_POS  (13U)
+#define AON_LDO15RF_PULLDOWN_SEL_AON_LEN  (1U)
+#define AON_LDO15RF_PULLDOWN_SEL_AON_MSK  (((1U << AON_LDO15RF_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_SEL_AON_POS)
+#define AON_LDO15RF_PULLDOWN_SEL_AON_UMSK (~(((1U << AON_LDO15RF_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_SEL_AON_POS))
+#define AON_LDO15RF_VOUT_SEL_AON          AON_LDO15RF_VOUT_SEL_AON
+#define AON_LDO15RF_VOUT_SEL_AON_POS      (16U)
+#define AON_LDO15RF_VOUT_SEL_AON_LEN      (3U)
+#define AON_LDO15RF_VOUT_SEL_AON_MSK      (((1U << AON_LDO15RF_VOUT_SEL_AON_LEN) - 1) << AON_LDO15RF_VOUT_SEL_AON_POS)
+#define AON_LDO15RF_VOUT_SEL_AON_UMSK     (~(((1U << AON_LDO15RF_VOUT_SEL_AON_LEN) - 1) << AON_LDO15RF_VOUT_SEL_AON_POS))
+#define AON_LDO15RF_CC_AON                AON_LDO15RF_CC_AON
+#define AON_LDO15RF_CC_AON_POS            (24U)
+#define AON_LDO15RF_CC_AON_LEN            (2U)
+#define AON_LDO15RF_CC_AON_MSK            (((1U << AON_LDO15RF_CC_AON_LEN) - 1) << AON_LDO15RF_CC_AON_POS)
+#define AON_LDO15RF_CC_AON_UMSK           (~(((1U << AON_LDO15RF_CC_AON_LEN) - 1) << AON_LDO15RF_CC_AON_POS))
+#define AON_LDO15RF_BYPASS_AON            AON_LDO15RF_BYPASS_AON
+#define AON_LDO15RF_BYPASS_AON_POS        (28U)
+#define AON_LDO15RF_BYPASS_AON_LEN        (1U)
+#define AON_LDO15RF_BYPASS_AON_MSK        (((1U << AON_LDO15RF_BYPASS_AON_LEN) - 1) << AON_LDO15RF_BYPASS_AON_POS)
+#define AON_LDO15RF_BYPASS_AON_UMSK       (~(((1U << AON_LDO15RF_BYPASS_AON_LEN) - 1) << AON_LDO15RF_BYPASS_AON_POS))
+
+/* 0x884 : xtal_cfg */
+#define AON_XTAL_CFG_OFFSET             (0x884)
+#define AON_XTAL_BK_AON                 AON_XTAL_BK_AON
+#define AON_XTAL_BK_AON_POS             (0U)
+#define AON_XTAL_BK_AON_LEN             (2U)
+#define AON_XTAL_BK_AON_MSK             (((1U << AON_XTAL_BK_AON_LEN) - 1) << AON_XTAL_BK_AON_POS)
+#define AON_XTAL_BK_AON_UMSK            (~(((1U << AON_XTAL_BK_AON_LEN) - 1) << AON_XTAL_BK_AON_POS))
+#define AON_XTAL_CAPCODE_EXTRA_AON      AON_XTAL_CAPCODE_EXTRA_AON
+#define AON_XTAL_CAPCODE_EXTRA_AON_POS  (2U)
+#define AON_XTAL_CAPCODE_EXTRA_AON_LEN  (1U)
+#define AON_XTAL_CAPCODE_EXTRA_AON_MSK  (((1U << AON_XTAL_CAPCODE_EXTRA_AON_LEN) - 1) << AON_XTAL_CAPCODE_EXTRA_AON_POS)
+#define AON_XTAL_CAPCODE_EXTRA_AON_UMSK (~(((1U << AON_XTAL_CAPCODE_EXTRA_AON_LEN) - 1) << AON_XTAL_CAPCODE_EXTRA_AON_POS))
+#define AON_XTAL_EXT_SEL_AON            AON_XTAL_EXT_SEL_AON
+#define AON_XTAL_EXT_SEL_AON_POS        (3U)
+#define AON_XTAL_EXT_SEL_AON_LEN        (1U)
+#define AON_XTAL_EXT_SEL_AON_MSK        (((1U << AON_XTAL_EXT_SEL_AON_LEN) - 1) << AON_XTAL_EXT_SEL_AON_POS)
+#define AON_XTAL_EXT_SEL_AON_UMSK       (~(((1U << AON_XTAL_EXT_SEL_AON_LEN) - 1) << AON_XTAL_EXT_SEL_AON_POS))
+#define AON_XTAL_BUF_EN_AON             AON_XTAL_BUF_EN_AON
+#define AON_XTAL_BUF_EN_AON_POS         (4U)
+#define AON_XTAL_BUF_EN_AON_LEN         (4U)
+#define AON_XTAL_BUF_EN_AON_MSK         (((1U << AON_XTAL_BUF_EN_AON_LEN) - 1) << AON_XTAL_BUF_EN_AON_POS)
+#define AON_XTAL_BUF_EN_AON_UMSK        (~(((1U << AON_XTAL_BUF_EN_AON_LEN) - 1) << AON_XTAL_BUF_EN_AON_POS))
+#define AON_XTAL_BUF_HP_AON             AON_XTAL_BUF_HP_AON
+#define AON_XTAL_BUF_HP_AON_POS         (8U)
+#define AON_XTAL_BUF_HP_AON_LEN         (4U)
+#define AON_XTAL_BUF_HP_AON_MSK         (((1U << AON_XTAL_BUF_HP_AON_LEN) - 1) << AON_XTAL_BUF_HP_AON_POS)
+#define AON_XTAL_BUF_HP_AON_UMSK        (~(((1U << AON_XTAL_BUF_HP_AON_LEN) - 1) << AON_XTAL_BUF_HP_AON_POS))
+#define AON_XTAL_FAST_STARTUP_AON       AON_XTAL_FAST_STARTUP_AON
+#define AON_XTAL_FAST_STARTUP_AON_POS   (12U)
+#define AON_XTAL_FAST_STARTUP_AON_LEN   (1U)
+#define AON_XTAL_FAST_STARTUP_AON_MSK   (((1U << AON_XTAL_FAST_STARTUP_AON_LEN) - 1) << AON_XTAL_FAST_STARTUP_AON_POS)
+#define AON_XTAL_FAST_STARTUP_AON_UMSK  (~(((1U << AON_XTAL_FAST_STARTUP_AON_LEN) - 1) << AON_XTAL_FAST_STARTUP_AON_POS))
+#define AON_XTAL_SLEEP_AON              AON_XTAL_SLEEP_AON
+#define AON_XTAL_SLEEP_AON_POS          (13U)
+#define AON_XTAL_SLEEP_AON_LEN          (1U)
+#define AON_XTAL_SLEEP_AON_MSK          (((1U << AON_XTAL_SLEEP_AON_LEN) - 1) << AON_XTAL_SLEEP_AON_POS)
+#define AON_XTAL_SLEEP_AON_UMSK         (~(((1U << AON_XTAL_SLEEP_AON_LEN) - 1) << AON_XTAL_SLEEP_AON_POS))
+#define AON_XTAL_AMP_CTRL_AON           AON_XTAL_AMP_CTRL_AON
+#define AON_XTAL_AMP_CTRL_AON_POS       (14U)
+#define AON_XTAL_AMP_CTRL_AON_LEN       (2U)
+#define AON_XTAL_AMP_CTRL_AON_MSK       (((1U << AON_XTAL_AMP_CTRL_AON_LEN) - 1) << AON_XTAL_AMP_CTRL_AON_POS)
+#define AON_XTAL_AMP_CTRL_AON_UMSK      (~(((1U << AON_XTAL_AMP_CTRL_AON_LEN) - 1) << AON_XTAL_AMP_CTRL_AON_POS))
+#define AON_XTAL_CAPCODE_OUT_AON        AON_XTAL_CAPCODE_OUT_AON
+#define AON_XTAL_CAPCODE_OUT_AON_POS    (16U)
+#define AON_XTAL_CAPCODE_OUT_AON_LEN    (6U)
+#define AON_XTAL_CAPCODE_OUT_AON_MSK    (((1U << AON_XTAL_CAPCODE_OUT_AON_LEN) - 1) << AON_XTAL_CAPCODE_OUT_AON_POS)
+#define AON_XTAL_CAPCODE_OUT_AON_UMSK   (~(((1U << AON_XTAL_CAPCODE_OUT_AON_LEN) - 1) << AON_XTAL_CAPCODE_OUT_AON_POS))
+#define AON_XTAL_CAPCODE_IN_AON         AON_XTAL_CAPCODE_IN_AON
+#define AON_XTAL_CAPCODE_IN_AON_POS     (22U)
+#define AON_XTAL_CAPCODE_IN_AON_LEN     (6U)
+#define AON_XTAL_CAPCODE_IN_AON_MSK     (((1U << AON_XTAL_CAPCODE_IN_AON_LEN) - 1) << AON_XTAL_CAPCODE_IN_AON_POS)
+#define AON_XTAL_CAPCODE_IN_AON_UMSK    (~(((1U << AON_XTAL_CAPCODE_IN_AON_LEN) - 1) << AON_XTAL_CAPCODE_IN_AON_POS))
+#define AON_XTAL_GM_BOOST_AON           AON_XTAL_GM_BOOST_AON
+#define AON_XTAL_GM_BOOST_AON_POS       (28U)
+#define AON_XTAL_GM_BOOST_AON_LEN       (2U)
+#define AON_XTAL_GM_BOOST_AON_MSK       (((1U << AON_XTAL_GM_BOOST_AON_LEN) - 1) << AON_XTAL_GM_BOOST_AON_POS)
+#define AON_XTAL_GM_BOOST_AON_UMSK      (~(((1U << AON_XTAL_GM_BOOST_AON_LEN) - 1) << AON_XTAL_GM_BOOST_AON_POS))
+#define AON_XTAL_RDY_SEL_AON            AON_XTAL_RDY_SEL_AON
+#define AON_XTAL_RDY_SEL_AON_POS        (30U)
+#define AON_XTAL_RDY_SEL_AON_LEN        (2U)
+#define AON_XTAL_RDY_SEL_AON_MSK        (((1U << AON_XTAL_RDY_SEL_AON_LEN) - 1) << AON_XTAL_RDY_SEL_AON_POS)
+#define AON_XTAL_RDY_SEL_AON_UMSK       (~(((1U << AON_XTAL_RDY_SEL_AON_LEN) - 1) << AON_XTAL_RDY_SEL_AON_POS))
+
+/* 0x888 : tsen */
+#define AON_TSEN_OFFSET               (0x888)
+#define AON_TSEN_REFCODE_CORNER       AON_TSEN_REFCODE_CORNER
+#define AON_TSEN_REFCODE_CORNER_POS   (0U)
+#define AON_TSEN_REFCODE_CORNER_LEN   (12U)
+#define AON_TSEN_REFCODE_CORNER_MSK   (((1U << AON_TSEN_REFCODE_CORNER_LEN) - 1) << AON_TSEN_REFCODE_CORNER_POS)
+#define AON_TSEN_REFCODE_CORNER_UMSK  (~(((1U << AON_TSEN_REFCODE_CORNER_LEN) - 1) << AON_TSEN_REFCODE_CORNER_POS))
+#define AON_TSEN_REFCODE_RFCAL        AON_TSEN_REFCODE_RFCAL
+#define AON_TSEN_REFCODE_RFCAL_POS    (16U)
+#define AON_TSEN_REFCODE_RFCAL_LEN    (12U)
+#define AON_TSEN_REFCODE_RFCAL_MSK    (((1U << AON_TSEN_REFCODE_RFCAL_LEN) - 1) << AON_TSEN_REFCODE_RFCAL_POS)
+#define AON_TSEN_REFCODE_RFCAL_UMSK   (~(((1U << AON_TSEN_REFCODE_RFCAL_LEN) - 1) << AON_TSEN_REFCODE_RFCAL_POS))
+#define AON_XTAL_RDY                  AON_XTAL_RDY
+#define AON_XTAL_RDY_POS              (28U)
+#define AON_XTAL_RDY_LEN              (1U)
+#define AON_XTAL_RDY_MSK              (((1U << AON_XTAL_RDY_LEN) - 1) << AON_XTAL_RDY_POS)
+#define AON_XTAL_RDY_UMSK             (~(((1U << AON_XTAL_RDY_LEN) - 1) << AON_XTAL_RDY_POS))
+#define AON_XTAL_INN_CFG_EN_AON       AON_XTAL_INN_CFG_EN_AON
+#define AON_XTAL_INN_CFG_EN_AON_POS   (29U)
+#define AON_XTAL_INN_CFG_EN_AON_LEN   (1U)
+#define AON_XTAL_INN_CFG_EN_AON_MSK   (((1U << AON_XTAL_INN_CFG_EN_AON_LEN) - 1) << AON_XTAL_INN_CFG_EN_AON_POS)
+#define AON_XTAL_INN_CFG_EN_AON_UMSK  (~(((1U << AON_XTAL_INN_CFG_EN_AON_LEN) - 1) << AON_XTAL_INN_CFG_EN_AON_POS))
+#define AON_XTAL_RDY_INT_SEL_AON      AON_XTAL_RDY_INT_SEL_AON
+#define AON_XTAL_RDY_INT_SEL_AON_POS  (30U)
+#define AON_XTAL_RDY_INT_SEL_AON_LEN  (2U)
+#define AON_XTAL_RDY_INT_SEL_AON_MSK  (((1U << AON_XTAL_RDY_INT_SEL_AON_LEN) - 1) << AON_XTAL_RDY_INT_SEL_AON_POS)
+#define AON_XTAL_RDY_INT_SEL_AON_UMSK (~(((1U << AON_XTAL_RDY_INT_SEL_AON_LEN) - 1) << AON_XTAL_RDY_INT_SEL_AON_POS))
+
+/* 0x900 : acomp0_ctrl */
+#define AON_ACOMP0_CTRL_OFFSET    (0x900)
+#define AON_ACOMP0_EN             AON_ACOMP0_EN
+#define AON_ACOMP0_EN_POS         (0U)
+#define AON_ACOMP0_EN_LEN         (1U)
+#define AON_ACOMP0_EN_MSK         (((1U << AON_ACOMP0_EN_LEN) - 1) << AON_ACOMP0_EN_POS)
+#define AON_ACOMP0_EN_UMSK        (~(((1U << AON_ACOMP0_EN_LEN) - 1) << AON_ACOMP0_EN_POS))
+#define AON_ACOMP0_HYST_SELN      AON_ACOMP0_HYST_SELN
+#define AON_ACOMP0_HYST_SELN_POS  (4U)
+#define AON_ACOMP0_HYST_SELN_LEN  (3U)
+#define AON_ACOMP0_HYST_SELN_MSK  (((1U << AON_ACOMP0_HYST_SELN_LEN) - 1) << AON_ACOMP0_HYST_SELN_POS)
+#define AON_ACOMP0_HYST_SELN_UMSK (~(((1U << AON_ACOMP0_HYST_SELN_LEN) - 1) << AON_ACOMP0_HYST_SELN_POS))
+#define AON_ACOMP0_HYST_SELP      AON_ACOMP0_HYST_SELP
+#define AON_ACOMP0_HYST_SELP_POS  (7U)
+#define AON_ACOMP0_HYST_SELP_LEN  (3U)
+#define AON_ACOMP0_HYST_SELP_MSK  (((1U << AON_ACOMP0_HYST_SELP_LEN) - 1) << AON_ACOMP0_HYST_SELP_POS)
+#define AON_ACOMP0_HYST_SELP_UMSK (~(((1U << AON_ACOMP0_HYST_SELP_LEN) - 1) << AON_ACOMP0_HYST_SELP_POS))
+#define AON_ACOMP0_BIAS_PROG      AON_ACOMP0_BIAS_PROG
+#define AON_ACOMP0_BIAS_PROG_POS  (10U)
+#define AON_ACOMP0_BIAS_PROG_LEN  (2U)
+#define AON_ACOMP0_BIAS_PROG_MSK  (((1U << AON_ACOMP0_BIAS_PROG_LEN) - 1) << AON_ACOMP0_BIAS_PROG_POS)
+#define AON_ACOMP0_BIAS_PROG_UMSK (~(((1U << AON_ACOMP0_BIAS_PROG_LEN) - 1) << AON_ACOMP0_BIAS_PROG_POS))
+#define AON_ACOMP0_LEVEL_SEL      AON_ACOMP0_LEVEL_SEL
+#define AON_ACOMP0_LEVEL_SEL_POS  (12U)
+#define AON_ACOMP0_LEVEL_SEL_LEN  (6U)
+#define AON_ACOMP0_LEVEL_SEL_MSK  (((1U << AON_ACOMP0_LEVEL_SEL_LEN) - 1) << AON_ACOMP0_LEVEL_SEL_POS)
+#define AON_ACOMP0_LEVEL_SEL_UMSK (~(((1U << AON_ACOMP0_LEVEL_SEL_LEN) - 1) << AON_ACOMP0_LEVEL_SEL_POS))
+#define AON_ACOMP0_NEG_SEL        AON_ACOMP0_NEG_SEL
+#define AON_ACOMP0_NEG_SEL_POS    (18U)
+#define AON_ACOMP0_NEG_SEL_LEN    (4U)
+#define AON_ACOMP0_NEG_SEL_MSK    (((1U << AON_ACOMP0_NEG_SEL_LEN) - 1) << AON_ACOMP0_NEG_SEL_POS)
+#define AON_ACOMP0_NEG_SEL_UMSK   (~(((1U << AON_ACOMP0_NEG_SEL_LEN) - 1) << AON_ACOMP0_NEG_SEL_POS))
+#define AON_ACOMP0_POS_SEL        AON_ACOMP0_POS_SEL
+#define AON_ACOMP0_POS_SEL_POS    (22U)
+#define AON_ACOMP0_POS_SEL_LEN    (4U)
+#define AON_ACOMP0_POS_SEL_MSK    (((1U << AON_ACOMP0_POS_SEL_LEN) - 1) << AON_ACOMP0_POS_SEL_POS)
+#define AON_ACOMP0_POS_SEL_UMSK   (~(((1U << AON_ACOMP0_POS_SEL_LEN) - 1) << AON_ACOMP0_POS_SEL_POS))
+#define AON_ACOMP0_MUXEN          AON_ACOMP0_MUXEN
+#define AON_ACOMP0_MUXEN_POS      (26U)
+#define AON_ACOMP0_MUXEN_LEN      (1U)
+#define AON_ACOMP0_MUXEN_MSK      (((1U << AON_ACOMP0_MUXEN_LEN) - 1) << AON_ACOMP0_MUXEN_POS)
+#define AON_ACOMP0_MUXEN_UMSK     (~(((1U << AON_ACOMP0_MUXEN_LEN) - 1) << AON_ACOMP0_MUXEN_POS))
+
+/* 0x904 : acomp1_ctrl */
+#define AON_ACOMP1_CTRL_OFFSET    (0x904)
+#define AON_ACOMP1_EN             AON_ACOMP1_EN
+#define AON_ACOMP1_EN_POS         (0U)
+#define AON_ACOMP1_EN_LEN         (1U)
+#define AON_ACOMP1_EN_MSK         (((1U << AON_ACOMP1_EN_LEN) - 1) << AON_ACOMP1_EN_POS)
+#define AON_ACOMP1_EN_UMSK        (~(((1U << AON_ACOMP1_EN_LEN) - 1) << AON_ACOMP1_EN_POS))
+#define AON_ACOMP1_HYST_SELN      AON_ACOMP1_HYST_SELN
+#define AON_ACOMP1_HYST_SELN_POS  (4U)
+#define AON_ACOMP1_HYST_SELN_LEN  (3U)
+#define AON_ACOMP1_HYST_SELN_MSK  (((1U << AON_ACOMP1_HYST_SELN_LEN) - 1) << AON_ACOMP1_HYST_SELN_POS)
+#define AON_ACOMP1_HYST_SELN_UMSK (~(((1U << AON_ACOMP1_HYST_SELN_LEN) - 1) << AON_ACOMP1_HYST_SELN_POS))
+#define AON_ACOMP1_HYST_SELP      AON_ACOMP1_HYST_SELP
+#define AON_ACOMP1_HYST_SELP_POS  (7U)
+#define AON_ACOMP1_HYST_SELP_LEN  (3U)
+#define AON_ACOMP1_HYST_SELP_MSK  (((1U << AON_ACOMP1_HYST_SELP_LEN) - 1) << AON_ACOMP1_HYST_SELP_POS)
+#define AON_ACOMP1_HYST_SELP_UMSK (~(((1U << AON_ACOMP1_HYST_SELP_LEN) - 1) << AON_ACOMP1_HYST_SELP_POS))
+#define AON_ACOMP1_BIAS_PROG      AON_ACOMP1_BIAS_PROG
+#define AON_ACOMP1_BIAS_PROG_POS  (10U)
+#define AON_ACOMP1_BIAS_PROG_LEN  (2U)
+#define AON_ACOMP1_BIAS_PROG_MSK  (((1U << AON_ACOMP1_BIAS_PROG_LEN) - 1) << AON_ACOMP1_BIAS_PROG_POS)
+#define AON_ACOMP1_BIAS_PROG_UMSK (~(((1U << AON_ACOMP1_BIAS_PROG_LEN) - 1) << AON_ACOMP1_BIAS_PROG_POS))
+#define AON_ACOMP1_LEVEL_SEL      AON_ACOMP1_LEVEL_SEL
+#define AON_ACOMP1_LEVEL_SEL_POS  (12U)
+#define AON_ACOMP1_LEVEL_SEL_LEN  (6U)
+#define AON_ACOMP1_LEVEL_SEL_MSK  (((1U << AON_ACOMP1_LEVEL_SEL_LEN) - 1) << AON_ACOMP1_LEVEL_SEL_POS)
+#define AON_ACOMP1_LEVEL_SEL_UMSK (~(((1U << AON_ACOMP1_LEVEL_SEL_LEN) - 1) << AON_ACOMP1_LEVEL_SEL_POS))
+#define AON_ACOMP1_NEG_SEL        AON_ACOMP1_NEG_SEL
+#define AON_ACOMP1_NEG_SEL_POS    (18U)
+#define AON_ACOMP1_NEG_SEL_LEN    (4U)
+#define AON_ACOMP1_NEG_SEL_MSK    (((1U << AON_ACOMP1_NEG_SEL_LEN) - 1) << AON_ACOMP1_NEG_SEL_POS)
+#define AON_ACOMP1_NEG_SEL_UMSK   (~(((1U << AON_ACOMP1_NEG_SEL_LEN) - 1) << AON_ACOMP1_NEG_SEL_POS))
+#define AON_ACOMP1_POS_SEL        AON_ACOMP1_POS_SEL
+#define AON_ACOMP1_POS_SEL_POS    (22U)
+#define AON_ACOMP1_POS_SEL_LEN    (4U)
+#define AON_ACOMP1_POS_SEL_MSK    (((1U << AON_ACOMP1_POS_SEL_LEN) - 1) << AON_ACOMP1_POS_SEL_POS)
+#define AON_ACOMP1_POS_SEL_UMSK   (~(((1U << AON_ACOMP1_POS_SEL_LEN) - 1) << AON_ACOMP1_POS_SEL_POS))
+#define AON_ACOMP1_MUXEN          AON_ACOMP1_MUXEN
+#define AON_ACOMP1_MUXEN_POS      (26U)
+#define AON_ACOMP1_MUXEN_LEN      (1U)
+#define AON_ACOMP1_MUXEN_MSK      (((1U << AON_ACOMP1_MUXEN_LEN) - 1) << AON_ACOMP1_MUXEN_POS)
+#define AON_ACOMP1_MUXEN_UMSK     (~(((1U << AON_ACOMP1_MUXEN_LEN) - 1) << AON_ACOMP1_MUXEN_POS))
+
+/* 0x908 : acomp_ctrl */
+#define AON_ACOMP_CTRL_OFFSET    (0x908)
+#define AON_ACOMP1_RSTN_ANA      AON_ACOMP1_RSTN_ANA
+#define AON_ACOMP1_RSTN_ANA_POS  (0U)
+#define AON_ACOMP1_RSTN_ANA_LEN  (1U)
+#define AON_ACOMP1_RSTN_ANA_MSK  (((1U << AON_ACOMP1_RSTN_ANA_LEN) - 1) << AON_ACOMP1_RSTN_ANA_POS)
+#define AON_ACOMP1_RSTN_ANA_UMSK (~(((1U << AON_ACOMP1_RSTN_ANA_LEN) - 1) << AON_ACOMP1_RSTN_ANA_POS))
+#define AON_ACOMP0_RSTN_ANA      AON_ACOMP0_RSTN_ANA
+#define AON_ACOMP0_RSTN_ANA_POS  (1U)
+#define AON_ACOMP0_RSTN_ANA_LEN  (1U)
+#define AON_ACOMP0_RSTN_ANA_MSK  (((1U << AON_ACOMP0_RSTN_ANA_LEN) - 1) << AON_ACOMP0_RSTN_ANA_POS)
+#define AON_ACOMP0_RSTN_ANA_UMSK (~(((1U << AON_ACOMP0_RSTN_ANA_LEN) - 1) << AON_ACOMP0_RSTN_ANA_POS))
+#define AON_ACOMP1_TEST_EN       AON_ACOMP1_TEST_EN
+#define AON_ACOMP1_TEST_EN_POS   (8U)
+#define AON_ACOMP1_TEST_EN_LEN   (1U)
+#define AON_ACOMP1_TEST_EN_MSK   (((1U << AON_ACOMP1_TEST_EN_LEN) - 1) << AON_ACOMP1_TEST_EN_POS)
+#define AON_ACOMP1_TEST_EN_UMSK  (~(((1U << AON_ACOMP1_TEST_EN_LEN) - 1) << AON_ACOMP1_TEST_EN_POS))
+#define AON_ACOMP0_TEST_EN       AON_ACOMP0_TEST_EN
+#define AON_ACOMP0_TEST_EN_POS   (9U)
+#define AON_ACOMP0_TEST_EN_LEN   (1U)
+#define AON_ACOMP0_TEST_EN_MSK   (((1U << AON_ACOMP0_TEST_EN_LEN) - 1) << AON_ACOMP0_TEST_EN_POS)
+#define AON_ACOMP0_TEST_EN_UMSK  (~(((1U << AON_ACOMP0_TEST_EN_LEN) - 1) << AON_ACOMP0_TEST_EN_POS))
+#define AON_ACOMP1_TEST_SEL      AON_ACOMP1_TEST_SEL
+#define AON_ACOMP1_TEST_SEL_POS  (10U)
+#define AON_ACOMP1_TEST_SEL_LEN  (2U)
+#define AON_ACOMP1_TEST_SEL_MSK  (((1U << AON_ACOMP1_TEST_SEL_LEN) - 1) << AON_ACOMP1_TEST_SEL_POS)
+#define AON_ACOMP1_TEST_SEL_UMSK (~(((1U << AON_ACOMP1_TEST_SEL_LEN) - 1) << AON_ACOMP1_TEST_SEL_POS))
+#define AON_ACOMP0_TEST_SEL      AON_ACOMP0_TEST_SEL
+#define AON_ACOMP0_TEST_SEL_POS  (12U)
+#define AON_ACOMP0_TEST_SEL_LEN  (2U)
+#define AON_ACOMP0_TEST_SEL_MSK  (((1U << AON_ACOMP0_TEST_SEL_LEN) - 1) << AON_ACOMP0_TEST_SEL_POS)
+#define AON_ACOMP0_TEST_SEL_UMSK (~(((1U << AON_ACOMP0_TEST_SEL_LEN) - 1) << AON_ACOMP0_TEST_SEL_POS))
+#define AON_ACOMP1_OUT_RAW       AON_ACOMP1_OUT_RAW
+#define AON_ACOMP1_OUT_RAW_POS   (17U)
+#define AON_ACOMP1_OUT_RAW_LEN   (1U)
+#define AON_ACOMP1_OUT_RAW_MSK   (((1U << AON_ACOMP1_OUT_RAW_LEN) - 1) << AON_ACOMP1_OUT_RAW_POS)
+#define AON_ACOMP1_OUT_RAW_UMSK  (~(((1U << AON_ACOMP1_OUT_RAW_LEN) - 1) << AON_ACOMP1_OUT_RAW_POS))
+#define AON_ACOMP0_OUT_RAW       AON_ACOMP0_OUT_RAW
+#define AON_ACOMP0_OUT_RAW_POS   (19U)
+#define AON_ACOMP0_OUT_RAW_LEN   (1U)
+#define AON_ACOMP0_OUT_RAW_MSK   (((1U << AON_ACOMP0_OUT_RAW_LEN) - 1) << AON_ACOMP0_OUT_RAW_POS)
+#define AON_ACOMP0_OUT_RAW_UMSK  (~(((1U << AON_ACOMP0_OUT_RAW_LEN) - 1) << AON_ACOMP0_OUT_RAW_POS))
+#define AON_ACOMP_RESERVED       AON_ACOMP_RESERVED
+#define AON_ACOMP_RESERVED_POS   (24U)
+#define AON_ACOMP_RESERVED_LEN   (8U)
+#define AON_ACOMP_RESERVED_MSK   (((1U << AON_ACOMP_RESERVED_LEN) - 1) << AON_ACOMP_RESERVED_POS)
+#define AON_ACOMP_RESERVED_UMSK  (~(((1U << AON_ACOMP_RESERVED_LEN) - 1) << AON_ACOMP_RESERVED_POS))
+
+/* 0x90C : gpadc_reg_cmd */
+#define AON_GPADC_REG_CMD_OFFSET        (0x90C)
+#define AON_GPADC_GLOBAL_EN             AON_GPADC_GLOBAL_EN
+#define AON_GPADC_GLOBAL_EN_POS         (0U)
+#define AON_GPADC_GLOBAL_EN_LEN         (1U)
+#define AON_GPADC_GLOBAL_EN_MSK         (((1U << AON_GPADC_GLOBAL_EN_LEN) - 1) << AON_GPADC_GLOBAL_EN_POS)
+#define AON_GPADC_GLOBAL_EN_UMSK        (~(((1U << AON_GPADC_GLOBAL_EN_LEN) - 1) << AON_GPADC_GLOBAL_EN_POS))
+#define AON_GPADC_CONV_START            AON_GPADC_CONV_START
+#define AON_GPADC_CONV_START_POS        (1U)
+#define AON_GPADC_CONV_START_LEN        (1U)
+#define AON_GPADC_CONV_START_MSK        (((1U << AON_GPADC_CONV_START_LEN) - 1) << AON_GPADC_CONV_START_POS)
+#define AON_GPADC_CONV_START_UMSK       (~(((1U << AON_GPADC_CONV_START_LEN) - 1) << AON_GPADC_CONV_START_POS))
+#define AON_GPADC_SOFT_RST              AON_GPADC_SOFT_RST
+#define AON_GPADC_SOFT_RST_POS          (2U)
+#define AON_GPADC_SOFT_RST_LEN          (1U)
+#define AON_GPADC_SOFT_RST_MSK          (((1U << AON_GPADC_SOFT_RST_LEN) - 1) << AON_GPADC_SOFT_RST_POS)
+#define AON_GPADC_SOFT_RST_UMSK         (~(((1U << AON_GPADC_SOFT_RST_LEN) - 1) << AON_GPADC_SOFT_RST_POS))
+#define AON_GPADC_NEG_SEL               AON_GPADC_NEG_SEL
+#define AON_GPADC_NEG_SEL_POS           (3U)
+#define AON_GPADC_NEG_SEL_LEN           (5U)
+#define AON_GPADC_NEG_SEL_MSK           (((1U << AON_GPADC_NEG_SEL_LEN) - 1) << AON_GPADC_NEG_SEL_POS)
+#define AON_GPADC_NEG_SEL_UMSK          (~(((1U << AON_GPADC_NEG_SEL_LEN) - 1) << AON_GPADC_NEG_SEL_POS))
+#define AON_GPADC_POS_SEL               AON_GPADC_POS_SEL
+#define AON_GPADC_POS_SEL_POS           (8U)
+#define AON_GPADC_POS_SEL_LEN           (5U)
+#define AON_GPADC_POS_SEL_MSK           (((1U << AON_GPADC_POS_SEL_LEN) - 1) << AON_GPADC_POS_SEL_POS)
+#define AON_GPADC_POS_SEL_UMSK          (~(((1U << AON_GPADC_POS_SEL_LEN) - 1) << AON_GPADC_POS_SEL_POS))
+#define AON_GPADC_NEG_GND               AON_GPADC_NEG_GND
+#define AON_GPADC_NEG_GND_POS           (13U)
+#define AON_GPADC_NEG_GND_LEN           (1U)
+#define AON_GPADC_NEG_GND_MSK           (((1U << AON_GPADC_NEG_GND_LEN) - 1) << AON_GPADC_NEG_GND_POS)
+#define AON_GPADC_NEG_GND_UMSK          (~(((1U << AON_GPADC_NEG_GND_LEN) - 1) << AON_GPADC_NEG_GND_POS))
+#define AON_GPADC_MICBIAS_EN            AON_GPADC_MICBIAS_EN
+#define AON_GPADC_MICBIAS_EN_POS        (14U)
+#define AON_GPADC_MICBIAS_EN_LEN        (1U)
+#define AON_GPADC_MICBIAS_EN_MSK        (((1U << AON_GPADC_MICBIAS_EN_LEN) - 1) << AON_GPADC_MICBIAS_EN_POS)
+#define AON_GPADC_MICBIAS_EN_UMSK       (~(((1U << AON_GPADC_MICBIAS_EN_LEN) - 1) << AON_GPADC_MICBIAS_EN_POS))
+#define AON_GPADC_MICPGA_EN             AON_GPADC_MICPGA_EN
+#define AON_GPADC_MICPGA_EN_POS         (15U)
+#define AON_GPADC_MICPGA_EN_LEN         (1U)
+#define AON_GPADC_MICPGA_EN_MSK         (((1U << AON_GPADC_MICPGA_EN_LEN) - 1) << AON_GPADC_MICPGA_EN_POS)
+#define AON_GPADC_MICPGA_EN_UMSK        (~(((1U << AON_GPADC_MICPGA_EN_LEN) - 1) << AON_GPADC_MICPGA_EN_POS))
+#define AON_GPADC_BYP_MICBOOST          AON_GPADC_BYP_MICBOOST
+#define AON_GPADC_BYP_MICBOOST_POS      (16U)
+#define AON_GPADC_BYP_MICBOOST_LEN      (1U)
+#define AON_GPADC_BYP_MICBOOST_MSK      (((1U << AON_GPADC_BYP_MICBOOST_LEN) - 1) << AON_GPADC_BYP_MICBOOST_POS)
+#define AON_GPADC_BYP_MICBOOST_UMSK     (~(((1U << AON_GPADC_BYP_MICBOOST_LEN) - 1) << AON_GPADC_BYP_MICBOOST_POS))
+#define AON_GPADC_DWA_EN                AON_GPADC_DWA_EN
+#define AON_GPADC_DWA_EN_POS            (18U)
+#define AON_GPADC_DWA_EN_LEN            (1U)
+#define AON_GPADC_DWA_EN_MSK            (((1U << AON_GPADC_DWA_EN_LEN) - 1) << AON_GPADC_DWA_EN_POS)
+#define AON_GPADC_DWA_EN_UMSK           (~(((1U << AON_GPADC_DWA_EN_LEN) - 1) << AON_GPADC_DWA_EN_POS))
+#define AON_GPADC_MIC2_DIFF             AON_GPADC_MIC2_DIFF
+#define AON_GPADC_MIC2_DIFF_POS         (19U)
+#define AON_GPADC_MIC2_DIFF_LEN         (1U)
+#define AON_GPADC_MIC2_DIFF_MSK         (((1U << AON_GPADC_MIC2_DIFF_LEN) - 1) << AON_GPADC_MIC2_DIFF_POS)
+#define AON_GPADC_MIC2_DIFF_UMSK        (~(((1U << AON_GPADC_MIC2_DIFF_LEN) - 1) << AON_GPADC_MIC2_DIFF_POS))
+#define AON_GPADC_MIC1_DIFF             AON_GPADC_MIC1_DIFF
+#define AON_GPADC_MIC1_DIFF_POS         (20U)
+#define AON_GPADC_MIC1_DIFF_LEN         (1U)
+#define AON_GPADC_MIC1_DIFF_MSK         (((1U << AON_GPADC_MIC1_DIFF_LEN) - 1) << AON_GPADC_MIC1_DIFF_POS)
+#define AON_GPADC_MIC1_DIFF_UMSK        (~(((1U << AON_GPADC_MIC1_DIFF_LEN) - 1) << AON_GPADC_MIC1_DIFF_POS))
+#define AON_GPADC_MIC_PGA2_GAIN         AON_GPADC_MIC_PGA2_GAIN
+#define AON_GPADC_MIC_PGA2_GAIN_POS     (21U)
+#define AON_GPADC_MIC_PGA2_GAIN_LEN     (2U)
+#define AON_GPADC_MIC_PGA2_GAIN_MSK     (((1U << AON_GPADC_MIC_PGA2_GAIN_LEN) - 1) << AON_GPADC_MIC_PGA2_GAIN_POS)
+#define AON_GPADC_MIC_PGA2_GAIN_UMSK    (~(((1U << AON_GPADC_MIC_PGA2_GAIN_LEN) - 1) << AON_GPADC_MIC_PGA2_GAIN_POS))
+#define AON_GPADC_MICBOOST_32DB_EN      AON_GPADC_MICBOOST_32DB_EN
+#define AON_GPADC_MICBOOST_32DB_EN_POS  (23U)
+#define AON_GPADC_MICBOOST_32DB_EN_LEN  (1U)
+#define AON_GPADC_MICBOOST_32DB_EN_MSK  (((1U << AON_GPADC_MICBOOST_32DB_EN_LEN) - 1) << AON_GPADC_MICBOOST_32DB_EN_POS)
+#define AON_GPADC_MICBOOST_32DB_EN_UMSK (~(((1U << AON_GPADC_MICBOOST_32DB_EN_LEN) - 1) << AON_GPADC_MICBOOST_32DB_EN_POS))
+#define AON_GPADC_CHIP_SEN_PU           AON_GPADC_CHIP_SEN_PU
+#define AON_GPADC_CHIP_SEN_PU_POS       (27U)
+#define AON_GPADC_CHIP_SEN_PU_LEN       (1U)
+#define AON_GPADC_CHIP_SEN_PU_MSK       (((1U << AON_GPADC_CHIP_SEN_PU_LEN) - 1) << AON_GPADC_CHIP_SEN_PU_POS)
+#define AON_GPADC_CHIP_SEN_PU_UMSK      (~(((1U << AON_GPADC_CHIP_SEN_PU_LEN) - 1) << AON_GPADC_CHIP_SEN_PU_POS))
+#define AON_GPADC_SEN_SEL               AON_GPADC_SEN_SEL
+#define AON_GPADC_SEN_SEL_POS           (28U)
+#define AON_GPADC_SEN_SEL_LEN           (2U)
+#define AON_GPADC_SEN_SEL_MSK           (((1U << AON_GPADC_SEN_SEL_LEN) - 1) << AON_GPADC_SEN_SEL_POS)
+#define AON_GPADC_SEN_SEL_UMSK          (~(((1U << AON_GPADC_SEN_SEL_LEN) - 1) << AON_GPADC_SEN_SEL_POS))
+#define AON_GPADC_SEN_TEST_EN           AON_GPADC_SEN_TEST_EN
+#define AON_GPADC_SEN_TEST_EN_POS       (30U)
+#define AON_GPADC_SEN_TEST_EN_LEN       (1U)
+#define AON_GPADC_SEN_TEST_EN_MSK       (((1U << AON_GPADC_SEN_TEST_EN_LEN) - 1) << AON_GPADC_SEN_TEST_EN_POS)
+#define AON_GPADC_SEN_TEST_EN_UMSK      (~(((1U << AON_GPADC_SEN_TEST_EN_LEN) - 1) << AON_GPADC_SEN_TEST_EN_POS))
+
+/* 0x910 : gpadc_reg_config1 */
+#define AON_GPADC_REG_CONFIG1_OFFSET (0x910)
+#define AON_GPADC_CAL_OS_EN          AON_GPADC_CAL_OS_EN
+#define AON_GPADC_CAL_OS_EN_POS      (0U)
+#define AON_GPADC_CAL_OS_EN_LEN      (1U)
+#define AON_GPADC_CAL_OS_EN_MSK      (((1U << AON_GPADC_CAL_OS_EN_LEN) - 1) << AON_GPADC_CAL_OS_EN_POS)
+#define AON_GPADC_CAL_OS_EN_UMSK     (~(((1U << AON_GPADC_CAL_OS_EN_LEN) - 1) << AON_GPADC_CAL_OS_EN_POS))
+#define AON_GPADC_CONT_CONV_EN       AON_GPADC_CONT_CONV_EN
+#define AON_GPADC_CONT_CONV_EN_POS   (1U)
+#define AON_GPADC_CONT_CONV_EN_LEN   (1U)
+#define AON_GPADC_CONT_CONV_EN_MSK   (((1U << AON_GPADC_CONT_CONV_EN_LEN) - 1) << AON_GPADC_CONT_CONV_EN_POS)
+#define AON_GPADC_CONT_CONV_EN_UMSK  (~(((1U << AON_GPADC_CONT_CONV_EN_LEN) - 1) << AON_GPADC_CONT_CONV_EN_POS))
+#define AON_GPADC_RES_SEL            AON_GPADC_RES_SEL
+#define AON_GPADC_RES_SEL_POS        (2U)
+#define AON_GPADC_RES_SEL_LEN        (3U)
+#define AON_GPADC_RES_SEL_MSK        (((1U << AON_GPADC_RES_SEL_LEN) - 1) << AON_GPADC_RES_SEL_POS)
+#define AON_GPADC_RES_SEL_UMSK       (~(((1U << AON_GPADC_RES_SEL_LEN) - 1) << AON_GPADC_RES_SEL_POS))
+#define AON_GPADC_VCM_SEL_EN         AON_GPADC_VCM_SEL_EN
+#define AON_GPADC_VCM_SEL_EN_POS     (8U)
+#define AON_GPADC_VCM_SEL_EN_LEN     (1U)
+#define AON_GPADC_VCM_SEL_EN_MSK     (((1U << AON_GPADC_VCM_SEL_EN_LEN) - 1) << AON_GPADC_VCM_SEL_EN_POS)
+#define AON_GPADC_VCM_SEL_EN_UMSK    (~(((1U << AON_GPADC_VCM_SEL_EN_LEN) - 1) << AON_GPADC_VCM_SEL_EN_POS))
+#define AON_GPADC_VCM_HYST_SEL       AON_GPADC_VCM_HYST_SEL
+#define AON_GPADC_VCM_HYST_SEL_POS   (9U)
+#define AON_GPADC_VCM_HYST_SEL_LEN   (1U)
+#define AON_GPADC_VCM_HYST_SEL_MSK   (((1U << AON_GPADC_VCM_HYST_SEL_LEN) - 1) << AON_GPADC_VCM_HYST_SEL_POS)
+#define AON_GPADC_VCM_HYST_SEL_UMSK  (~(((1U << AON_GPADC_VCM_HYST_SEL_LEN) - 1) << AON_GPADC_VCM_HYST_SEL_POS))
+#define AON_GPADC_LOWV_DET_EN        AON_GPADC_LOWV_DET_EN
+#define AON_GPADC_LOWV_DET_EN_POS    (10U)
+#define AON_GPADC_LOWV_DET_EN_LEN    (1U)
+#define AON_GPADC_LOWV_DET_EN_MSK    (((1U << AON_GPADC_LOWV_DET_EN_LEN) - 1) << AON_GPADC_LOWV_DET_EN_POS)
+#define AON_GPADC_LOWV_DET_EN_UMSK   (~(((1U << AON_GPADC_LOWV_DET_EN_LEN) - 1) << AON_GPADC_LOWV_DET_EN_POS))
+#define AON_GPADC_CLK_ANA_INV        AON_GPADC_CLK_ANA_INV
+#define AON_GPADC_CLK_ANA_INV_POS    (17U)
+#define AON_GPADC_CLK_ANA_INV_LEN    (1U)
+#define AON_GPADC_CLK_ANA_INV_MSK    (((1U << AON_GPADC_CLK_ANA_INV_LEN) - 1) << AON_GPADC_CLK_ANA_INV_POS)
+#define AON_GPADC_CLK_ANA_INV_UMSK   (~(((1U << AON_GPADC_CLK_ANA_INV_LEN) - 1) << AON_GPADC_CLK_ANA_INV_POS))
+#define AON_GPADC_CLK_DIV_RATIO      AON_GPADC_CLK_DIV_RATIO
+#define AON_GPADC_CLK_DIV_RATIO_POS  (18U)
+#define AON_GPADC_CLK_DIV_RATIO_LEN  (3U)
+#define AON_GPADC_CLK_DIV_RATIO_MSK  (((1U << AON_GPADC_CLK_DIV_RATIO_LEN) - 1) << AON_GPADC_CLK_DIV_RATIO_POS)
+#define AON_GPADC_CLK_DIV_RATIO_UMSK (~(((1U << AON_GPADC_CLK_DIV_RATIO_LEN) - 1) << AON_GPADC_CLK_DIV_RATIO_POS))
+#define AON_GPADC_SCAN_LENGTH        AON_GPADC_SCAN_LENGTH
+#define AON_GPADC_SCAN_LENGTH_POS    (21U)
+#define AON_GPADC_SCAN_LENGTH_LEN    (4U)
+#define AON_GPADC_SCAN_LENGTH_MSK    (((1U << AON_GPADC_SCAN_LENGTH_LEN) - 1) << AON_GPADC_SCAN_LENGTH_POS)
+#define AON_GPADC_SCAN_LENGTH_UMSK   (~(((1U << AON_GPADC_SCAN_LENGTH_LEN) - 1) << AON_GPADC_SCAN_LENGTH_POS))
+#define AON_GPADC_SCAN_EN            AON_GPADC_SCAN_EN
+#define AON_GPADC_SCAN_EN_POS        (25U)
+#define AON_GPADC_SCAN_EN_LEN        (1U)
+#define AON_GPADC_SCAN_EN_MSK        (((1U << AON_GPADC_SCAN_EN_LEN) - 1) << AON_GPADC_SCAN_EN_POS)
+#define AON_GPADC_SCAN_EN_UMSK       (~(((1U << AON_GPADC_SCAN_EN_LEN) - 1) << AON_GPADC_SCAN_EN_POS))
+#define AON_GPADC_DITHER_EN          AON_GPADC_DITHER_EN
+#define AON_GPADC_DITHER_EN_POS      (26U)
+#define AON_GPADC_DITHER_EN_LEN      (1U)
+#define AON_GPADC_DITHER_EN_MSK      (((1U << AON_GPADC_DITHER_EN_LEN) - 1) << AON_GPADC_DITHER_EN_POS)
+#define AON_GPADC_DITHER_EN_UMSK     (~(((1U << AON_GPADC_DITHER_EN_LEN) - 1) << AON_GPADC_DITHER_EN_POS))
+#define AON_GPADC_V11_SEL            AON_GPADC_V11_SEL
+#define AON_GPADC_V11_SEL_POS        (27U)
+#define AON_GPADC_V11_SEL_LEN        (2U)
+#define AON_GPADC_V11_SEL_MSK        (((1U << AON_GPADC_V11_SEL_LEN) - 1) << AON_GPADC_V11_SEL_POS)
+#define AON_GPADC_V11_SEL_UMSK       (~(((1U << AON_GPADC_V11_SEL_LEN) - 1) << AON_GPADC_V11_SEL_POS))
+#define AON_GPADC_V18_SEL            AON_GPADC_V18_SEL
+#define AON_GPADC_V18_SEL_POS        (29U)
+#define AON_GPADC_V18_SEL_LEN        (2U)
+#define AON_GPADC_V18_SEL_MSK        (((1U << AON_GPADC_V18_SEL_LEN) - 1) << AON_GPADC_V18_SEL_POS)
+#define AON_GPADC_V18_SEL_UMSK       (~(((1U << AON_GPADC_V18_SEL_LEN) - 1) << AON_GPADC_V18_SEL_POS))
+
+/* 0x914 : gpadc_reg_config2 */
+#define AON_GPADC_REG_CONFIG2_OFFSET (0x914)
+#define AON_GPADC_DIFF_MODE          AON_GPADC_DIFF_MODE
+#define AON_GPADC_DIFF_MODE_POS      (2U)
+#define AON_GPADC_DIFF_MODE_LEN      (1U)
+#define AON_GPADC_DIFF_MODE_MSK      (((1U << AON_GPADC_DIFF_MODE_LEN) - 1) << AON_GPADC_DIFF_MODE_POS)
+#define AON_GPADC_DIFF_MODE_UMSK     (~(((1U << AON_GPADC_DIFF_MODE_LEN) - 1) << AON_GPADC_DIFF_MODE_POS))
+#define AON_GPADC_VREF_SEL           AON_GPADC_VREF_SEL
+#define AON_GPADC_VREF_SEL_POS       (3U)
+#define AON_GPADC_VREF_SEL_LEN       (1U)
+#define AON_GPADC_VREF_SEL_MSK       (((1U << AON_GPADC_VREF_SEL_LEN) - 1) << AON_GPADC_VREF_SEL_POS)
+#define AON_GPADC_VREF_SEL_UMSK      (~(((1U << AON_GPADC_VREF_SEL_LEN) - 1) << AON_GPADC_VREF_SEL_POS))
+#define AON_GPADC_VBAT_EN            AON_GPADC_VBAT_EN
+#define AON_GPADC_VBAT_EN_POS        (4U)
+#define AON_GPADC_VBAT_EN_LEN        (1U)
+#define AON_GPADC_VBAT_EN_MSK        (((1U << AON_GPADC_VBAT_EN_LEN) - 1) << AON_GPADC_VBAT_EN_POS)
+#define AON_GPADC_VBAT_EN_UMSK       (~(((1U << AON_GPADC_VBAT_EN_LEN) - 1) << AON_GPADC_VBAT_EN_POS))
+#define AON_GPADC_TSEXT_SEL          AON_GPADC_TSEXT_SEL
+#define AON_GPADC_TSEXT_SEL_POS      (5U)
+#define AON_GPADC_TSEXT_SEL_LEN      (1U)
+#define AON_GPADC_TSEXT_SEL_MSK      (((1U << AON_GPADC_TSEXT_SEL_LEN) - 1) << AON_GPADC_TSEXT_SEL_POS)
+#define AON_GPADC_TSEXT_SEL_UMSK     (~(((1U << AON_GPADC_TSEXT_SEL_LEN) - 1) << AON_GPADC_TSEXT_SEL_POS))
+#define AON_GPADC_TS_EN              AON_GPADC_TS_EN
+#define AON_GPADC_TS_EN_POS          (6U)
+#define AON_GPADC_TS_EN_LEN          (1U)
+#define AON_GPADC_TS_EN_MSK          (((1U << AON_GPADC_TS_EN_LEN) - 1) << AON_GPADC_TS_EN_POS)
+#define AON_GPADC_TS_EN_UMSK         (~(((1U << AON_GPADC_TS_EN_LEN) - 1) << AON_GPADC_TS_EN_POS))
+#define AON_GPADC_PGA_VCM            AON_GPADC_PGA_VCM
+#define AON_GPADC_PGA_VCM_POS        (7U)
+#define AON_GPADC_PGA_VCM_LEN        (2U)
+#define AON_GPADC_PGA_VCM_MSK        (((1U << AON_GPADC_PGA_VCM_LEN) - 1) << AON_GPADC_PGA_VCM_POS)
+#define AON_GPADC_PGA_VCM_UMSK       (~(((1U << AON_GPADC_PGA_VCM_LEN) - 1) << AON_GPADC_PGA_VCM_POS))
+#define AON_GPADC_PGA_OS_CAL         AON_GPADC_PGA_OS_CAL
+#define AON_GPADC_PGA_OS_CAL_POS     (9U)
+#define AON_GPADC_PGA_OS_CAL_LEN     (4U)
+#define AON_GPADC_PGA_OS_CAL_MSK     (((1U << AON_GPADC_PGA_OS_CAL_LEN) - 1) << AON_GPADC_PGA_OS_CAL_POS)
+#define AON_GPADC_PGA_OS_CAL_UMSK    (~(((1U << AON_GPADC_PGA_OS_CAL_LEN) - 1) << AON_GPADC_PGA_OS_CAL_POS))
+#define AON_GPADC_PGA_EN             AON_GPADC_PGA_EN
+#define AON_GPADC_PGA_EN_POS         (13U)
+#define AON_GPADC_PGA_EN_LEN         (1U)
+#define AON_GPADC_PGA_EN_MSK         (((1U << AON_GPADC_PGA_EN_LEN) - 1) << AON_GPADC_PGA_EN_POS)
+#define AON_GPADC_PGA_EN_UMSK        (~(((1U << AON_GPADC_PGA_EN_LEN) - 1) << AON_GPADC_PGA_EN_POS))
+#define AON_GPADC_PGA_VCMI_EN        AON_GPADC_PGA_VCMI_EN
+#define AON_GPADC_PGA_VCMI_EN_POS    (14U)
+#define AON_GPADC_PGA_VCMI_EN_LEN    (1U)
+#define AON_GPADC_PGA_VCMI_EN_MSK    (((1U << AON_GPADC_PGA_VCMI_EN_LEN) - 1) << AON_GPADC_PGA_VCMI_EN_POS)
+#define AON_GPADC_PGA_VCMI_EN_UMSK   (~(((1U << AON_GPADC_PGA_VCMI_EN_LEN) - 1) << AON_GPADC_PGA_VCMI_EN_POS))
+#define AON_GPADC_CHOP_MODE          AON_GPADC_CHOP_MODE
+#define AON_GPADC_CHOP_MODE_POS      (15U)
+#define AON_GPADC_CHOP_MODE_LEN      (2U)
+#define AON_GPADC_CHOP_MODE_MSK      (((1U << AON_GPADC_CHOP_MODE_LEN) - 1) << AON_GPADC_CHOP_MODE_POS)
+#define AON_GPADC_CHOP_MODE_UMSK     (~(((1U << AON_GPADC_CHOP_MODE_LEN) - 1) << AON_GPADC_CHOP_MODE_POS))
+#define AON_GPADC_BIAS_SEL           AON_GPADC_BIAS_SEL
+#define AON_GPADC_BIAS_SEL_POS       (17U)
+#define AON_GPADC_BIAS_SEL_LEN       (1U)
+#define AON_GPADC_BIAS_SEL_MSK       (((1U << AON_GPADC_BIAS_SEL_LEN) - 1) << AON_GPADC_BIAS_SEL_POS)
+#define AON_GPADC_BIAS_SEL_UMSK      (~(((1U << AON_GPADC_BIAS_SEL_LEN) - 1) << AON_GPADC_BIAS_SEL_POS))
+#define AON_GPADC_TEST_EN            AON_GPADC_TEST_EN
+#define AON_GPADC_TEST_EN_POS        (18U)
+#define AON_GPADC_TEST_EN_LEN        (1U)
+#define AON_GPADC_TEST_EN_MSK        (((1U << AON_GPADC_TEST_EN_LEN) - 1) << AON_GPADC_TEST_EN_POS)
+#define AON_GPADC_TEST_EN_UMSK       (~(((1U << AON_GPADC_TEST_EN_LEN) - 1) << AON_GPADC_TEST_EN_POS))
+#define AON_GPADC_TEST_SEL           AON_GPADC_TEST_SEL
+#define AON_GPADC_TEST_SEL_POS       (19U)
+#define AON_GPADC_TEST_SEL_LEN       (3U)
+#define AON_GPADC_TEST_SEL_MSK       (((1U << AON_GPADC_TEST_SEL_LEN) - 1) << AON_GPADC_TEST_SEL_POS)
+#define AON_GPADC_TEST_SEL_UMSK      (~(((1U << AON_GPADC_TEST_SEL_LEN) - 1) << AON_GPADC_TEST_SEL_POS))
+#define AON_GPADC_PGA2_GAIN          AON_GPADC_PGA2_GAIN
+#define AON_GPADC_PGA2_GAIN_POS      (22U)
+#define AON_GPADC_PGA2_GAIN_LEN      (3U)
+#define AON_GPADC_PGA2_GAIN_MSK      (((1U << AON_GPADC_PGA2_GAIN_LEN) - 1) << AON_GPADC_PGA2_GAIN_POS)
+#define AON_GPADC_PGA2_GAIN_UMSK     (~(((1U << AON_GPADC_PGA2_GAIN_LEN) - 1) << AON_GPADC_PGA2_GAIN_POS))
+#define AON_GPADC_PGA1_GAIN          AON_GPADC_PGA1_GAIN
+#define AON_GPADC_PGA1_GAIN_POS      (25U)
+#define AON_GPADC_PGA1_GAIN_LEN      (3U)
+#define AON_GPADC_PGA1_GAIN_MSK      (((1U << AON_GPADC_PGA1_GAIN_LEN) - 1) << AON_GPADC_PGA1_GAIN_POS)
+#define AON_GPADC_PGA1_GAIN_UMSK     (~(((1U << AON_GPADC_PGA1_GAIN_LEN) - 1) << AON_GPADC_PGA1_GAIN_POS))
+#define AON_GPADC_DLY_SEL            AON_GPADC_DLY_SEL
+#define AON_GPADC_DLY_SEL_POS        (28U)
+#define AON_GPADC_DLY_SEL_LEN        (3U)
+#define AON_GPADC_DLY_SEL_MSK        (((1U << AON_GPADC_DLY_SEL_LEN) - 1) << AON_GPADC_DLY_SEL_POS)
+#define AON_GPADC_DLY_SEL_UMSK       (~(((1U << AON_GPADC_DLY_SEL_LEN) - 1) << AON_GPADC_DLY_SEL_POS))
+#define AON_GPADC_TSVBE_LOW          AON_GPADC_TSVBE_LOW
+#define AON_GPADC_TSVBE_LOW_POS      (31U)
+#define AON_GPADC_TSVBE_LOW_LEN      (1U)
+#define AON_GPADC_TSVBE_LOW_MSK      (((1U << AON_GPADC_TSVBE_LOW_LEN) - 1) << AON_GPADC_TSVBE_LOW_POS)
+#define AON_GPADC_TSVBE_LOW_UMSK     (~(((1U << AON_GPADC_TSVBE_LOW_LEN) - 1) << AON_GPADC_TSVBE_LOW_POS))
+
+/* 0x918 : adc converation sequence 1 */
+#define AON_GPADC_REG_SCN_POS1_OFFSET (0x918)
+#define AON_GPADC_SCAN_POS_0          AON_GPADC_SCAN_POS_0
+#define AON_GPADC_SCAN_POS_0_POS      (0U)
+#define AON_GPADC_SCAN_POS_0_LEN      (5U)
+#define AON_GPADC_SCAN_POS_0_MSK      (((1U << AON_GPADC_SCAN_POS_0_LEN) - 1) << AON_GPADC_SCAN_POS_0_POS)
+#define AON_GPADC_SCAN_POS_0_UMSK     (~(((1U << AON_GPADC_SCAN_POS_0_LEN) - 1) << AON_GPADC_SCAN_POS_0_POS))
+#define AON_GPADC_SCAN_POS_1          AON_GPADC_SCAN_POS_1
+#define AON_GPADC_SCAN_POS_1_POS      (5U)
+#define AON_GPADC_SCAN_POS_1_LEN      (5U)
+#define AON_GPADC_SCAN_POS_1_MSK      (((1U << AON_GPADC_SCAN_POS_1_LEN) - 1) << AON_GPADC_SCAN_POS_1_POS)
+#define AON_GPADC_SCAN_POS_1_UMSK     (~(((1U << AON_GPADC_SCAN_POS_1_LEN) - 1) << AON_GPADC_SCAN_POS_1_POS))
+#define AON_GPADC_SCAN_POS_2          AON_GPADC_SCAN_POS_2
+#define AON_GPADC_SCAN_POS_2_POS      (10U)
+#define AON_GPADC_SCAN_POS_2_LEN      (5U)
+#define AON_GPADC_SCAN_POS_2_MSK      (((1U << AON_GPADC_SCAN_POS_2_LEN) - 1) << AON_GPADC_SCAN_POS_2_POS)
+#define AON_GPADC_SCAN_POS_2_UMSK     (~(((1U << AON_GPADC_SCAN_POS_2_LEN) - 1) << AON_GPADC_SCAN_POS_2_POS))
+#define AON_GPADC_SCAN_POS_3          AON_GPADC_SCAN_POS_3
+#define AON_GPADC_SCAN_POS_3_POS      (15U)
+#define AON_GPADC_SCAN_POS_3_LEN      (5U)
+#define AON_GPADC_SCAN_POS_3_MSK      (((1U << AON_GPADC_SCAN_POS_3_LEN) - 1) << AON_GPADC_SCAN_POS_3_POS)
+#define AON_GPADC_SCAN_POS_3_UMSK     (~(((1U << AON_GPADC_SCAN_POS_3_LEN) - 1) << AON_GPADC_SCAN_POS_3_POS))
+#define AON_GPADC_SCAN_POS_4          AON_GPADC_SCAN_POS_4
+#define AON_GPADC_SCAN_POS_4_POS      (20U)
+#define AON_GPADC_SCAN_POS_4_LEN      (5U)
+#define AON_GPADC_SCAN_POS_4_MSK      (((1U << AON_GPADC_SCAN_POS_4_LEN) - 1) << AON_GPADC_SCAN_POS_4_POS)
+#define AON_GPADC_SCAN_POS_4_UMSK     (~(((1U << AON_GPADC_SCAN_POS_4_LEN) - 1) << AON_GPADC_SCAN_POS_4_POS))
+#define AON_GPADC_SCAN_POS_5          AON_GPADC_SCAN_POS_5
+#define AON_GPADC_SCAN_POS_5_POS      (25U)
+#define AON_GPADC_SCAN_POS_5_LEN      (5U)
+#define AON_GPADC_SCAN_POS_5_MSK      (((1U << AON_GPADC_SCAN_POS_5_LEN) - 1) << AON_GPADC_SCAN_POS_5_POS)
+#define AON_GPADC_SCAN_POS_5_UMSK     (~(((1U << AON_GPADC_SCAN_POS_5_LEN) - 1) << AON_GPADC_SCAN_POS_5_POS))
+
+/* 0x91C : adc converation sequence 2 */
+#define AON_GPADC_REG_SCN_POS2_OFFSET (0x91C)
+#define AON_GPADC_SCAN_POS_6          AON_GPADC_SCAN_POS_6
+#define AON_GPADC_SCAN_POS_6_POS      (0U)
+#define AON_GPADC_SCAN_POS_6_LEN      (5U)
+#define AON_GPADC_SCAN_POS_6_MSK      (((1U << AON_GPADC_SCAN_POS_6_LEN) - 1) << AON_GPADC_SCAN_POS_6_POS)
+#define AON_GPADC_SCAN_POS_6_UMSK     (~(((1U << AON_GPADC_SCAN_POS_6_LEN) - 1) << AON_GPADC_SCAN_POS_6_POS))
+#define AON_GPADC_SCAN_POS_7          AON_GPADC_SCAN_POS_7
+#define AON_GPADC_SCAN_POS_7_POS      (5U)
+#define AON_GPADC_SCAN_POS_7_LEN      (5U)
+#define AON_GPADC_SCAN_POS_7_MSK      (((1U << AON_GPADC_SCAN_POS_7_LEN) - 1) << AON_GPADC_SCAN_POS_7_POS)
+#define AON_GPADC_SCAN_POS_7_UMSK     (~(((1U << AON_GPADC_SCAN_POS_7_LEN) - 1) << AON_GPADC_SCAN_POS_7_POS))
+#define AON_GPADC_SCAN_POS_8          AON_GPADC_SCAN_POS_8
+#define AON_GPADC_SCAN_POS_8_POS      (10U)
+#define AON_GPADC_SCAN_POS_8_LEN      (5U)
+#define AON_GPADC_SCAN_POS_8_MSK      (((1U << AON_GPADC_SCAN_POS_8_LEN) - 1) << AON_GPADC_SCAN_POS_8_POS)
+#define AON_GPADC_SCAN_POS_8_UMSK     (~(((1U << AON_GPADC_SCAN_POS_8_LEN) - 1) << AON_GPADC_SCAN_POS_8_POS))
+#define AON_GPADC_SCAN_POS_9          AON_GPADC_SCAN_POS_9
+#define AON_GPADC_SCAN_POS_9_POS      (15U)
+#define AON_GPADC_SCAN_POS_9_LEN      (5U)
+#define AON_GPADC_SCAN_POS_9_MSK      (((1U << AON_GPADC_SCAN_POS_9_LEN) - 1) << AON_GPADC_SCAN_POS_9_POS)
+#define AON_GPADC_SCAN_POS_9_UMSK     (~(((1U << AON_GPADC_SCAN_POS_9_LEN) - 1) << AON_GPADC_SCAN_POS_9_POS))
+#define AON_GPADC_SCAN_POS_10         AON_GPADC_SCAN_POS_10
+#define AON_GPADC_SCAN_POS_10_POS     (20U)
+#define AON_GPADC_SCAN_POS_10_LEN     (5U)
+#define AON_GPADC_SCAN_POS_10_MSK     (((1U << AON_GPADC_SCAN_POS_10_LEN) - 1) << AON_GPADC_SCAN_POS_10_POS)
+#define AON_GPADC_SCAN_POS_10_UMSK    (~(((1U << AON_GPADC_SCAN_POS_10_LEN) - 1) << AON_GPADC_SCAN_POS_10_POS))
+#define AON_GPADC_SCAN_POS_11         AON_GPADC_SCAN_POS_11
+#define AON_GPADC_SCAN_POS_11_POS     (25U)
+#define AON_GPADC_SCAN_POS_11_LEN     (5U)
+#define AON_GPADC_SCAN_POS_11_MSK     (((1U << AON_GPADC_SCAN_POS_11_LEN) - 1) << AON_GPADC_SCAN_POS_11_POS)
+#define AON_GPADC_SCAN_POS_11_UMSK    (~(((1U << AON_GPADC_SCAN_POS_11_LEN) - 1) << AON_GPADC_SCAN_POS_11_POS))
+
+/* 0x920 : adc converation sequence 3 */
+#define AON_GPADC_REG_SCN_NEG1_OFFSET (0x920)
+#define AON_GPADC_SCAN_NEG_0          AON_GPADC_SCAN_NEG_0
+#define AON_GPADC_SCAN_NEG_0_POS      (0U)
+#define AON_GPADC_SCAN_NEG_0_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_0_MSK      (((1U << AON_GPADC_SCAN_NEG_0_LEN) - 1) << AON_GPADC_SCAN_NEG_0_POS)
+#define AON_GPADC_SCAN_NEG_0_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_0_LEN) - 1) << AON_GPADC_SCAN_NEG_0_POS))
+#define AON_GPADC_SCAN_NEG_1          AON_GPADC_SCAN_NEG_1
+#define AON_GPADC_SCAN_NEG_1_POS      (5U)
+#define AON_GPADC_SCAN_NEG_1_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_1_MSK      (((1U << AON_GPADC_SCAN_NEG_1_LEN) - 1) << AON_GPADC_SCAN_NEG_1_POS)
+#define AON_GPADC_SCAN_NEG_1_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_1_LEN) - 1) << AON_GPADC_SCAN_NEG_1_POS))
+#define AON_GPADC_SCAN_NEG_2          AON_GPADC_SCAN_NEG_2
+#define AON_GPADC_SCAN_NEG_2_POS      (10U)
+#define AON_GPADC_SCAN_NEG_2_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_2_MSK      (((1U << AON_GPADC_SCAN_NEG_2_LEN) - 1) << AON_GPADC_SCAN_NEG_2_POS)
+#define AON_GPADC_SCAN_NEG_2_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_2_LEN) - 1) << AON_GPADC_SCAN_NEG_2_POS))
+#define AON_GPADC_SCAN_NEG_3          AON_GPADC_SCAN_NEG_3
+#define AON_GPADC_SCAN_NEG_3_POS      (15U)
+#define AON_GPADC_SCAN_NEG_3_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_3_MSK      (((1U << AON_GPADC_SCAN_NEG_3_LEN) - 1) << AON_GPADC_SCAN_NEG_3_POS)
+#define AON_GPADC_SCAN_NEG_3_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_3_LEN) - 1) << AON_GPADC_SCAN_NEG_3_POS))
+#define AON_GPADC_SCAN_NEG_4          AON_GPADC_SCAN_NEG_4
+#define AON_GPADC_SCAN_NEG_4_POS      (20U)
+#define AON_GPADC_SCAN_NEG_4_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_4_MSK      (((1U << AON_GPADC_SCAN_NEG_4_LEN) - 1) << AON_GPADC_SCAN_NEG_4_POS)
+#define AON_GPADC_SCAN_NEG_4_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_4_LEN) - 1) << AON_GPADC_SCAN_NEG_4_POS))
+#define AON_GPADC_SCAN_NEG_5          AON_GPADC_SCAN_NEG_5
+#define AON_GPADC_SCAN_NEG_5_POS      (25U)
+#define AON_GPADC_SCAN_NEG_5_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_5_MSK      (((1U << AON_GPADC_SCAN_NEG_5_LEN) - 1) << AON_GPADC_SCAN_NEG_5_POS)
+#define AON_GPADC_SCAN_NEG_5_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_5_LEN) - 1) << AON_GPADC_SCAN_NEG_5_POS))
+
+/* 0x924 : adc converation sequence 4 */
+#define AON_GPADC_REG_SCN_NEG2_OFFSET (0x924)
+#define AON_GPADC_SCAN_NEG_6          AON_GPADC_SCAN_NEG_6
+#define AON_GPADC_SCAN_NEG_6_POS      (0U)
+#define AON_GPADC_SCAN_NEG_6_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_6_MSK      (((1U << AON_GPADC_SCAN_NEG_6_LEN) - 1) << AON_GPADC_SCAN_NEG_6_POS)
+#define AON_GPADC_SCAN_NEG_6_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_6_LEN) - 1) << AON_GPADC_SCAN_NEG_6_POS))
+#define AON_GPADC_SCAN_NEG_7          AON_GPADC_SCAN_NEG_7
+#define AON_GPADC_SCAN_NEG_7_POS      (5U)
+#define AON_GPADC_SCAN_NEG_7_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_7_MSK      (((1U << AON_GPADC_SCAN_NEG_7_LEN) - 1) << AON_GPADC_SCAN_NEG_7_POS)
+#define AON_GPADC_SCAN_NEG_7_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_7_LEN) - 1) << AON_GPADC_SCAN_NEG_7_POS))
+#define AON_GPADC_SCAN_NEG_8          AON_GPADC_SCAN_NEG_8
+#define AON_GPADC_SCAN_NEG_8_POS      (10U)
+#define AON_GPADC_SCAN_NEG_8_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_8_MSK      (((1U << AON_GPADC_SCAN_NEG_8_LEN) - 1) << AON_GPADC_SCAN_NEG_8_POS)
+#define AON_GPADC_SCAN_NEG_8_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_8_LEN) - 1) << AON_GPADC_SCAN_NEG_8_POS))
+#define AON_GPADC_SCAN_NEG_9          AON_GPADC_SCAN_NEG_9
+#define AON_GPADC_SCAN_NEG_9_POS      (15U)
+#define AON_GPADC_SCAN_NEG_9_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_9_MSK      (((1U << AON_GPADC_SCAN_NEG_9_LEN) - 1) << AON_GPADC_SCAN_NEG_9_POS)
+#define AON_GPADC_SCAN_NEG_9_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_9_LEN) - 1) << AON_GPADC_SCAN_NEG_9_POS))
+#define AON_GPADC_SCAN_NEG_10         AON_GPADC_SCAN_NEG_10
+#define AON_GPADC_SCAN_NEG_10_POS     (20U)
+#define AON_GPADC_SCAN_NEG_10_LEN     (5U)
+#define AON_GPADC_SCAN_NEG_10_MSK     (((1U << AON_GPADC_SCAN_NEG_10_LEN) - 1) << AON_GPADC_SCAN_NEG_10_POS)
+#define AON_GPADC_SCAN_NEG_10_UMSK    (~(((1U << AON_GPADC_SCAN_NEG_10_LEN) - 1) << AON_GPADC_SCAN_NEG_10_POS))
+#define AON_GPADC_SCAN_NEG_11         AON_GPADC_SCAN_NEG_11
+#define AON_GPADC_SCAN_NEG_11_POS     (25U)
+#define AON_GPADC_SCAN_NEG_11_LEN     (5U)
+#define AON_GPADC_SCAN_NEG_11_MSK     (((1U << AON_GPADC_SCAN_NEG_11_LEN) - 1) << AON_GPADC_SCAN_NEG_11_POS)
+#define AON_GPADC_SCAN_NEG_11_UMSK    (~(((1U << AON_GPADC_SCAN_NEG_11_LEN) - 1) << AON_GPADC_SCAN_NEG_11_POS))
+
+/* 0x928 : gpadc_reg_status */
+#define AON_GPADC_REG_STATUS_OFFSET (0x928)
+#define AON_GPADC_DATA_RDY          AON_GPADC_DATA_RDY
+#define AON_GPADC_DATA_RDY_POS      (0U)
+#define AON_GPADC_DATA_RDY_LEN      (1U)
+#define AON_GPADC_DATA_RDY_MSK      (((1U << AON_GPADC_DATA_RDY_LEN) - 1) << AON_GPADC_DATA_RDY_POS)
+#define AON_GPADC_DATA_RDY_UMSK     (~(((1U << AON_GPADC_DATA_RDY_LEN) - 1) << AON_GPADC_DATA_RDY_POS))
+#define AON_GPADC_RESERVED          AON_GPADC_RESERVED
+#define AON_GPADC_RESERVED_POS      (16U)
+#define AON_GPADC_RESERVED_LEN      (16U)
+#define AON_GPADC_RESERVED_MSK      (((1U << AON_GPADC_RESERVED_LEN) - 1) << AON_GPADC_RESERVED_POS)
+#define AON_GPADC_RESERVED_UMSK     (~(((1U << AON_GPADC_RESERVED_LEN) - 1) << AON_GPADC_RESERVED_POS))
+
+/* 0x92C : gpadc_reg_isr */
+#define AON_GPADC_REG_ISR_OFFSET      (0x92C)
+#define AON_GPADC_NEG_SATUR           AON_GPADC_NEG_SATUR
+#define AON_GPADC_NEG_SATUR_POS       (0U)
+#define AON_GPADC_NEG_SATUR_LEN       (1U)
+#define AON_GPADC_NEG_SATUR_MSK       (((1U << AON_GPADC_NEG_SATUR_LEN) - 1) << AON_GPADC_NEG_SATUR_POS)
+#define AON_GPADC_NEG_SATUR_UMSK      (~(((1U << AON_GPADC_NEG_SATUR_LEN) - 1) << AON_GPADC_NEG_SATUR_POS))
+#define AON_GPADC_POS_SATUR           AON_GPADC_POS_SATUR
+#define AON_GPADC_POS_SATUR_POS       (1U)
+#define AON_GPADC_POS_SATUR_LEN       (1U)
+#define AON_GPADC_POS_SATUR_MSK       (((1U << AON_GPADC_POS_SATUR_LEN) - 1) << AON_GPADC_POS_SATUR_POS)
+#define AON_GPADC_POS_SATUR_UMSK      (~(((1U << AON_GPADC_POS_SATUR_LEN) - 1) << AON_GPADC_POS_SATUR_POS))
+#define AON_GPADC_NEG_SATUR_CLR       AON_GPADC_NEG_SATUR_CLR
+#define AON_GPADC_NEG_SATUR_CLR_POS   (4U)
+#define AON_GPADC_NEG_SATUR_CLR_LEN   (1U)
+#define AON_GPADC_NEG_SATUR_CLR_MSK   (((1U << AON_GPADC_NEG_SATUR_CLR_LEN) - 1) << AON_GPADC_NEG_SATUR_CLR_POS)
+#define AON_GPADC_NEG_SATUR_CLR_UMSK  (~(((1U << AON_GPADC_NEG_SATUR_CLR_LEN) - 1) << AON_GPADC_NEG_SATUR_CLR_POS))
+#define AON_GPADC_POS_SATUR_CLR       AON_GPADC_POS_SATUR_CLR
+#define AON_GPADC_POS_SATUR_CLR_POS   (5U)
+#define AON_GPADC_POS_SATUR_CLR_LEN   (1U)
+#define AON_GPADC_POS_SATUR_CLR_MSK   (((1U << AON_GPADC_POS_SATUR_CLR_LEN) - 1) << AON_GPADC_POS_SATUR_CLR_POS)
+#define AON_GPADC_POS_SATUR_CLR_UMSK  (~(((1U << AON_GPADC_POS_SATUR_CLR_LEN) - 1) << AON_GPADC_POS_SATUR_CLR_POS))
+#define AON_GPADC_NEG_SATUR_MASK      AON_GPADC_NEG_SATUR_MASK
+#define AON_GPADC_NEG_SATUR_MASK_POS  (8U)
+#define AON_GPADC_NEG_SATUR_MASK_LEN  (1U)
+#define AON_GPADC_NEG_SATUR_MASK_MSK  (((1U << AON_GPADC_NEG_SATUR_MASK_LEN) - 1) << AON_GPADC_NEG_SATUR_MASK_POS)
+#define AON_GPADC_NEG_SATUR_MASK_UMSK (~(((1U << AON_GPADC_NEG_SATUR_MASK_LEN) - 1) << AON_GPADC_NEG_SATUR_MASK_POS))
+#define AON_GPADC_POS_SATUR_MASK      AON_GPADC_POS_SATUR_MASK
+#define AON_GPADC_POS_SATUR_MASK_POS  (9U)
+#define AON_GPADC_POS_SATUR_MASK_LEN  (1U)
+#define AON_GPADC_POS_SATUR_MASK_MSK  (((1U << AON_GPADC_POS_SATUR_MASK_LEN) - 1) << AON_GPADC_POS_SATUR_MASK_POS)
+#define AON_GPADC_POS_SATUR_MASK_UMSK (~(((1U << AON_GPADC_POS_SATUR_MASK_LEN) - 1) << AON_GPADC_POS_SATUR_MASK_POS))
+
+/* 0x930 : gpadc_reg_result */
+#define AON_GPADC_REG_RESULT_OFFSET (0x930)
+#define AON_GPADC_DATA_OUT          AON_GPADC_DATA_OUT
+#define AON_GPADC_DATA_OUT_POS      (0U)
+#define AON_GPADC_DATA_OUT_LEN      (26U)
+#define AON_GPADC_DATA_OUT_MSK      (((1U << AON_GPADC_DATA_OUT_LEN) - 1) << AON_GPADC_DATA_OUT_POS)
+#define AON_GPADC_DATA_OUT_UMSK     (~(((1U << AON_GPADC_DATA_OUT_LEN) - 1) << AON_GPADC_DATA_OUT_POS))
+
+/* 0x934 : gpadc_reg_raw_result */
+#define AON_GPADC_REG_RAW_RESULT_OFFSET (0x934)
+#define AON_GPADC_RAW_DATA              AON_GPADC_RAW_DATA
+#define AON_GPADC_RAW_DATA_POS          (0U)
+#define AON_GPADC_RAW_DATA_LEN          (12U)
+#define AON_GPADC_RAW_DATA_MSK          (((1U << AON_GPADC_RAW_DATA_LEN) - 1) << AON_GPADC_RAW_DATA_POS)
+#define AON_GPADC_RAW_DATA_UMSK         (~(((1U << AON_GPADC_RAW_DATA_LEN) - 1) << AON_GPADC_RAW_DATA_POS))
+
+/* 0x938 : gpadc_reg_define */
+#define AON_GPADC_REG_DEFINE_OFFSET (0x938)
+#define AON_GPADC_OS_CAL_DATA       AON_GPADC_OS_CAL_DATA
+#define AON_GPADC_OS_CAL_DATA_POS   (0U)
+#define AON_GPADC_OS_CAL_DATA_LEN   (16U)
+#define AON_GPADC_OS_CAL_DATA_MSK   (((1U << AON_GPADC_OS_CAL_DATA_LEN) - 1) << AON_GPADC_OS_CAL_DATA_POS)
+#define AON_GPADC_OS_CAL_DATA_UMSK  (~(((1U << AON_GPADC_OS_CAL_DATA_LEN) - 1) << AON_GPADC_OS_CAL_DATA_POS))
+
+/* 0x93C : hbncore_resv0 */
+#define AON_HBNCORE_RESV0_OFFSET    (0x93C)
+#define AON_HBNCORE_RESV0_DATA      AON_HBNCORE_RESV0_DATA
+#define AON_HBNCORE_RESV0_DATA_POS  (0U)
+#define AON_HBNCORE_RESV0_DATA_LEN  (32U)
+#define AON_HBNCORE_RESV0_DATA_MSK  (((1U << AON_HBNCORE_RESV0_DATA_LEN) - 1) << AON_HBNCORE_RESV0_DATA_POS)
+#define AON_HBNCORE_RESV0_DATA_UMSK (~(((1U << AON_HBNCORE_RESV0_DATA_LEN) - 1) << AON_HBNCORE_RESV0_DATA_POS))
+
+/* 0x940 : hbncore_resv1 */
+#define AON_HBNCORE_RESV1_OFFSET    (0x940)
+#define AON_HBNCORE_RESV1_DATA      AON_HBNCORE_RESV1_DATA
+#define AON_HBNCORE_RESV1_DATA_POS  (0U)
+#define AON_HBNCORE_RESV1_DATA_LEN  (32U)
+#define AON_HBNCORE_RESV1_DATA_MSK  (((1U << AON_HBNCORE_RESV1_DATA_LEN) - 1) << AON_HBNCORE_RESV1_DATA_POS)
+#define AON_HBNCORE_RESV1_DATA_UMSK (~(((1U << AON_HBNCORE_RESV1_DATA_LEN) - 1) << AON_HBNCORE_RESV1_DATA_POS))
+
+struct aon_reg {
+    /* 0x0  reserved */
+    uint8_t RESERVED0x0[2048];
+
+    /* 0x800 : aon */
+    union {
+        struct
+        {
+            uint32_t aon_resv              : 8; /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reserved_8_11         : 4; /* [11: 8],       rsvd,        0x0 */
+            uint32_t pu_aon_dc_tbuf        : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13_19        : 7; /* [19:13],       rsvd,        0x0 */
+            uint32_t ldo11_rt_pulldown     : 1; /* [   20],        r/w,        0x0 */
+            uint32_t ldo11_rt_pulldown_sel : 1; /* [   21],        r/w,        0x0 */
+            uint32_t sw_pu_ldo11_rt        : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23_31        : 9; /* [31:23],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } aon;
+
+    /* 0x804 : aon_common */
+    union {
+        struct
+        {
+            uint32_t tmux_aon         : 3;  /* [ 2: 0],        r/w,        0x0 */
+            uint32_t reserved_3       : 1;  /* [    3],       rsvd,        0x0 */
+            uint32_t ten_aon          : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t dten_xtal32k     : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t ten_xtal32k      : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7       : 1;  /* [    7],       rsvd,        0x0 */
+            uint32_t ten_vddcore_aon  : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t ten_ldo11soc_aon : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t ten_dcdc18_0_aon : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t ten_dcdc18_1_aon : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t ten_bg_sys_aon   : 1;  /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13_15   : 3;  /* [15:13],       rsvd,        0x0 */
+            uint32_t ten_ldo15rf_aon  : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t ten_xtal_aon     : 1;  /* [   17],        r/w,        0x0 */
+            uint32_t dten_xtal_aon    : 1;  /* [   18],        r/w,        0x0 */
+            uint32_t ten_mbg_aon      : 1;  /* [   19],        r/w,        0x0 */
+            uint32_t ten_cip_misc_aon : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t reserved_21_31   : 11; /* [31:21],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } aon_common;
+
+    /* 0x808 : aon_misc */
+    union {
+        struct
+        {
+            uint32_t sw_soc_en_aon : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t sw_bz_en_aon  : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reserved_2_31 : 30; /* [31: 2],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } aon_misc;
+
+    /* 0x80c  reserved */
+    uint8_t RESERVED0x80c[4];
+
+    /* 0x810 : bg_sys_top */
+    union {
+        struct
+        {
+            uint32_t pmip_resv             : 8;  /* [ 7: 0],        r/w,        0x0 */
+            uint32_t pu_bg_sys_aon         : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t reserved_9_11         : 3;  /* [11: 9],       rsvd,        0x0 */
+            uint32_t bg_sys_start_ctrl_aon : 1;  /* [   12],        r/w,        0x1 */
+            uint32_t reserved_13_31        : 19; /* [31:13],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } bg_sys_top;
+
+    /* 0x814 : dcdc18_top_0 */
+    union {
+        struct
+        {
+            uint32_t reserved_0                : 1; /* [    0],       rsvd,        0x0 */
+            uint32_t dcdc18_vout_sel_aon       : 5; /* [ 5: 1],        r/w,       0x1b */
+            uint32_t reserved_6_7              : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t dcdc18_vpfm_aon           : 4; /* [11: 8],        r/w,        0x7 */
+            uint32_t dcdc18_osc_2m_mode_aon    : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13_15            : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t dcdc18_osc_freq_trim_aon  : 4; /* [19:16],        r/w,        0x8 */
+            uint32_t dcdc18_slope_curr_sel_aon : 5; /* [24:20],        r/w,        0x5 */
+            uint32_t dcdc18_stop_osc_aon       : 1; /* [   25],        r/w,        0x1 */
+            uint32_t dcdc18_slow_osc_aon       : 1; /* [   26],        r/w,        0x0 */
+            uint32_t dcdc18_osc_inhibit_t2_aon : 1; /* [   27],        r/w,        0x1 */
+            uint32_t dcdc18_sstart_time_aon    : 2; /* [29:28],        r/w,        0x0 */
+            uint32_t reserved_30               : 1; /* [   30],       rsvd,        0x0 */
+            uint32_t dcdc18_rdy_aon            : 1; /* [   31],          r,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } dcdc18_top_0;
+
+    /* 0x818 : dcdc18_top_1 */
+    union {
+        struct
+        {
+            uint32_t dcdc18_force_cs_zvs_aon  : 1; /* [    0],        r/w,        0x0 */
+            uint32_t dcdc18_cs_delay_aon      : 3; /* [ 3: 1],        r/w,        0x4 */
+            uint32_t dcdc18_zvs_td_opt_aon    : 3; /* [ 6: 4],        r/w,        0x4 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t dcdc18_nonoverlap_td_aon : 5; /* [12: 8],        r/w,        0x0 */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t dcdc18_rc_sel_aon        : 4; /* [19:16],        r/w,        0x8 */
+            uint32_t dcdc18_chf_sel_aon       : 4; /* [23:20],        r/w,        0x1 */
+            uint32_t dcdc18_cfb_sel_aon       : 4; /* [27:24],        r/w,        0x8 */
+            uint32_t dcdc18_en_antiring_aon   : 1; /* [   28],        r/w,        0x1 */
+            uint32_t dcdc18_pulldown_aon      : 1; /* [   29],        r/w,        0x0 */
+            uint32_t reserved_30_31           : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dcdc18_top_1;
+
+    /* 0x81C : ldo11soc_and_dctest */
+    union {
+        struct
+        {
+            uint32_t pu_ldo11soc_aon           : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reserved_1_3              : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t ldo11soc_sstart_sel_aon   : 1;  /* [    4],        r/w,        0x1 */
+            uint32_t reserved_5_7              : 3;  /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t ldo11soc_sstart_delay_aon : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t ldo11soc_pulldown_aon     : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t ldo11soc_pulldown_sel_aon : 1;  /* [   11],        r/w,        0x1 */
+            uint32_t ldo11soc_vth_sel_aon      : 2;  /* [13:12],        r/w,        0x1 */
+            uint32_t reserved_14_23            : 10; /* [23:14],       rsvd,        0x0 */
+            uint32_t ldo11soc_cc_aon           : 2;  /* [25:24],        r/w,        0x0 */
+            uint32_t reserved_26_27            : 2;  /* [27:26],       rsvd,        0x0 */
+            uint32_t ldo11soc_rdy_aon          : 1;  /* [   28],          r,        0x1 */
+            uint32_t ldo11soc_power_good_aon   : 1;  /* [   29],          r,        0x1 */
+            uint32_t pu_vddcore_misc_aon       : 1;  /* [   30],        r/w,        0x1 */
+            uint32_t pmip_dc_tp_out_en_aon     : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ldo11soc_and_dctest;
+
+    /* 0x820 : psw_irrcv */
+    union {
+        struct
+        {
+            uint32_t pu_ir_psw_aon : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_31 : 31; /* [31: 1],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psw_irrcv;
+
+    /* 0x824  reserved */
+    uint8_t RESERVED0x824[92];
+
+    /* 0x880 : rf_top_aon */
+    union {
+        struct
+        {
+            uint32_t pu_mbg_aon               : 1; /* [    0],        r/w,        0x1 */
+            uint32_t pu_ldo15rf_aon           : 1; /* [    1],        r/w,        0x1 */
+            uint32_t pu_sfreg_aon             : 1; /* [    2],        r/w,        0x1 */
+            uint32_t reserved_3               : 1; /* [    3],       rsvd,        0x0 */
+            uint32_t pu_xtal_buf_aon          : 1; /* [    4],        r/w,        0x1 */
+            uint32_t pu_xtal_aon              : 1; /* [    5],        r/w,        0x1 */
+            uint32_t reserved_6_7             : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t ldo15rf_sstart_sel_aon   : 1; /* [    8],        r/w,        0x1 */
+            uint32_t ldo15rf_sstart_delay_aon : 2; /* [10: 9],        r/w,        0x0 */
+            uint32_t reserved_11              : 1; /* [   11],       rsvd,        0x0 */
+            uint32_t ldo15rf_pulldown_aon     : 1; /* [   12],        r/w,        0x0 */
+            uint32_t ldo15rf_pulldown_sel_aon : 1; /* [   13],        r/w,        0x0 */
+            uint32_t reserved_14_15           : 2; /* [15:14],       rsvd,        0x0 */
+            uint32_t ldo15rf_vout_sel_aon     : 3; /* [18:16],        r/w,        0x2 */
+            uint32_t reserved_19_23           : 5; /* [23:19],       rsvd,        0x0 */
+            uint32_t ldo15rf_cc_aon           : 2; /* [25:24],        r/w,        0x0 */
+            uint32_t reserved_26_27           : 2; /* [27:26],       rsvd,        0x0 */
+            uint32_t ldo15rf_bypass_aon       : 1; /* [   28],        r/w,        0x0 */
+            uint32_t reserved_29_31           : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } rf_top_aon;
+
+    /* 0x884 : xtal_cfg */
+    union {
+        struct
+        {
+            uint32_t xtal_bk_aon            : 2; /* [ 1: 0],        r/w,        0x0 */
+            uint32_t xtal_capcode_extra_aon : 1; /* [    2],        r/w,        0x0 */
+            uint32_t xtal_ext_sel_aon       : 1; /* [    3],        r/w,        0x0 */
+            uint32_t xtal_buf_en_aon        : 4; /* [ 7: 4],        r/w,        0xf */
+            uint32_t xtal_buf_hp_aon        : 4; /* [11: 8],        r/w,        0x0 */
+            uint32_t xtal_fast_startup_aon  : 1; /* [   12],        r/w,        0x1 */
+            uint32_t xtal_sleep_aon         : 1; /* [   13],        r/w,        0x1 */
+            uint32_t xtal_amp_ctrl_aon      : 2; /* [15:14],        r/w,        0x3 */
+            uint32_t xtal_capcode_out_aon   : 6; /* [21:16],        r/w,       0x10 */
+            uint32_t xtal_capcode_in_aon    : 6; /* [27:22],        r/w,       0x10 */
+            uint32_t xtal_gm_boost_aon      : 2; /* [29:28],        r/w,        0x3 */
+            uint32_t xtal_rdy_sel_aon       : 2; /* [31:30],        r/w,        0x2 */
+        } BF;
+        uint32_t WORD;
+    } xtal_cfg;
+
+    /* 0x888 : tsen */
+    union {
+        struct
+        {
+            uint32_t tsen_refcode_corner  : 12; /* [11: 0],        r/w,      0x8ff */
+            uint32_t reserved_12_15       : 4;  /* [15:12],       rsvd,        0x0 */
+            uint32_t tsen_refcode_rfcal   : 12; /* [27:16],        r/w,      0x8ff */
+            uint32_t xtal_rdy             : 1;  /* [   28],          r,        0x1 */
+            uint32_t xtal_inn_cfg_en_aon  : 1;  /* [   29],        r/w,        0x1 */
+            uint32_t xtal_rdy_int_sel_aon : 2;  /* [31:30],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } tsen;
+
+    /* 0x88c  reserved */
+    uint8_t RESERVED0x88c[116];
+
+    /* 0x900 : acomp0_ctrl */
+    union {
+        struct
+        {
+            uint32_t acomp0_en        : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3     : 3; /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t acomp0_hyst_seln : 3; /* [ 6: 4],        r/w,        0x0 */
+            uint32_t acomp0_hyst_selp : 3; /* [ 9: 7],        r/w,        0x0 */
+            uint32_t acomp0_bias_prog : 2; /* [11:10],        r/w,        0x0 */
+            uint32_t acomp0_level_sel : 6; /* [17:12],        r/w,        0x0 */
+            uint32_t acomp0_neg_sel   : 4; /* [21:18],        r/w,        0x0 */
+            uint32_t acomp0_pos_sel   : 4; /* [25:22],        r/w,        0x0 */
+            uint32_t acomp0_muxen     : 1; /* [   26],        r/w,        0x0 */
+            uint32_t reserved_27_31   : 5; /* [31:27],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } acomp0_ctrl;
+
+    /* 0x904 : acomp1_ctrl */
+    union {
+        struct
+        {
+            uint32_t acomp1_en        : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3     : 3; /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t acomp1_hyst_seln : 3; /* [ 6: 4],        r/w,        0x0 */
+            uint32_t acomp1_hyst_selp : 3; /* [ 9: 7],        r/w,        0x0 */
+            uint32_t acomp1_bias_prog : 2; /* [11:10],        r/w,        0x0 */
+            uint32_t acomp1_level_sel : 6; /* [17:12],        r/w,        0x0 */
+            uint32_t acomp1_neg_sel   : 4; /* [21:18],        r/w,        0x0 */
+            uint32_t acomp1_pos_sel   : 4; /* [25:22],        r/w,        0x0 */
+            uint32_t acomp1_muxen     : 1; /* [   26],        r/w,        0x0 */
+            uint32_t reserved_27_31   : 5; /* [31:27],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } acomp1_ctrl;
+
+    /* 0x908 : acomp_ctrl */
+    union {
+        struct
+        {
+            uint32_t acomp1_rstn_ana : 1; /* [    0],        r/w,        0x1 */
+            uint32_t acomp0_rstn_ana : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reserved_2_7    : 6; /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t acomp1_test_en  : 1; /* [    8],        r/w,        0x0 */
+            uint32_t acomp0_test_en  : 1; /* [    9],        r/w,        0x0 */
+            uint32_t acomp1_test_sel : 2; /* [11:10],        r/w,        0x0 */
+            uint32_t acomp0_test_sel : 2; /* [13:12],        r/w,        0x0 */
+            uint32_t reserved_14_16  : 3; /* [16:14],       rsvd,        0x0 */
+            uint32_t acomp1_out_raw  : 1; /* [   17],          r,        0x0 */
+            uint32_t reserved_18     : 1; /* [   18],       rsvd,        0x0 */
+            uint32_t acomp0_out_raw  : 1; /* [   19],          r,        0x0 */
+            uint32_t reserved_20_23  : 4; /* [23:20],       rsvd,        0x0 */
+            uint32_t acomp_reserved  : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } acomp_ctrl;
+
+    /* 0x90C : gpadc_reg_cmd */
+    union {
+        struct
+        {
+            uint32_t gpadc_global_en        : 1; /* [    0],        r/w,        0x0 */
+            uint32_t gpadc_conv_start       : 1; /* [    1],        r/w,        0x0 */
+            uint32_t gpadc_soft_rst         : 1; /* [    2],        r/w,        0x0 */
+            uint32_t gpadc_neg_sel          : 5; /* [ 7: 3],        r/w,        0xf */
+            uint32_t gpadc_pos_sel          : 5; /* [12: 8],        r/w,        0xf */
+            uint32_t gpadc_neg_gnd          : 1; /* [   13],        r/w,        0x0 */
+            uint32_t gpadc_micbias_en       : 1; /* [   14],        r/w,        0x0 */
+            uint32_t gpadc_micpga_en        : 1; /* [   15],        r/w,        0x0 */
+            uint32_t gpadc_byp_micboost     : 1; /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17            : 1; /* [   17],       rsvd,        0x0 */
+            uint32_t gpadc_dwa_en           : 1; /* [   18],        r/w,        0x0 */
+            uint32_t gpadc_mic2_diff        : 1; /* [   19],        r/w,        0x0 */
+            uint32_t gpadc_mic1_diff        : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpadc_mic_pga2_gain    : 2; /* [22:21],        r/w,        0x0 */
+            uint32_t gpadc_micboost_32db_en : 1; /* [   23],        r/w,        0x0 */
+            uint32_t reserved_24_26         : 3; /* [26:24],       rsvd,        0x0 */
+            uint32_t gpadc_chip_sen_pu      : 1; /* [   27],        r/w,        0x0 */
+            uint32_t gpadc_sen_sel          : 2; /* [29:28],        r/w,        0x0 */
+            uint32_t gpadc_sen_test_en      : 1; /* [   30],        r/w,        0x0 */
+            uint32_t reserved_31            : 1; /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_cmd;
+
+    /* 0x910 : gpadc_reg_config1 */
+    union {
+        struct
+        {
+            uint32_t gpadc_cal_os_en     : 1; /* [    0],        r/w,        0x0 */
+            uint32_t gpadc_cont_conv_en  : 1; /* [    1],        r/w,        0x1 */
+            uint32_t gpadc_res_sel       : 3; /* [ 4: 2],        r/w,        0x0 */
+            uint32_t reserved_5_7        : 3; /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t gpadc_vcm_sel_en    : 1; /* [    8],        r/w,        0x0 */
+            uint32_t gpadc_vcm_hyst_sel  : 1; /* [    9],        r/w,        0x0 */
+            uint32_t gpadc_lowv_det_en   : 1; /* [   10],        r/w,        0x0 */
+            uint32_t reserved_11_16      : 6; /* [16:11],       rsvd,        0x0 */
+            uint32_t gpadc_clk_ana_inv   : 1; /* [   17],        r/w,        0x0 */
+            uint32_t gpadc_clk_div_ratio : 3; /* [20:18],        r/w,        0x3 */
+            uint32_t gpadc_scan_length   : 4; /* [24:21],        r/w,        0x0 */
+            uint32_t gpadc_scan_en       : 1; /* [   25],        r/w,        0x0 */
+            uint32_t gpadc_dither_en     : 1; /* [   26],        r/w,        0x0 */
+            uint32_t gpadc_v11_sel       : 2; /* [28:27],        r/w,        0x0 */
+            uint32_t gpadc_v18_sel       : 2; /* [30:29],        r/w,        0x0 */
+            uint32_t reserved_31         : 1; /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_config1;
+
+    /* 0x914 : gpadc_reg_config2 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_1      : 2; /* [ 1: 0],       rsvd,        0x0 */
+            uint32_t gpadc_diff_mode   : 1; /* [    2],        r/w,        0x0 */
+            uint32_t gpadc_vref_sel    : 1; /* [    3],        r/w,        0x0 */
+            uint32_t gpadc_vbat_en     : 1; /* [    4],        r/w,        0x0 */
+            uint32_t gpadc_tsext_sel   : 1; /* [    5],        r/w,        0x0 */
+            uint32_t gpadc_ts_en       : 1; /* [    6],        r/w,        0x0 */
+            uint32_t gpadc_pga_vcm     : 2; /* [ 8: 7],        r/w,        0x2 */
+            uint32_t gpadc_pga_os_cal  : 4; /* [12: 9],        r/w,        0x8 */
+            uint32_t gpadc_pga_en      : 1; /* [   13],        r/w,        0x0 */
+            uint32_t gpadc_pga_vcmi_en : 1; /* [   14],        r/w,        0x0 */
+            uint32_t gpadc_chop_mode   : 2; /* [16:15],        r/w,        0x3 */
+            uint32_t gpadc_bias_sel    : 1; /* [   17],        r/w,        0x0 */
+            uint32_t gpadc_test_en     : 1; /* [   18],        r/w,        0x0 */
+            uint32_t gpadc_test_sel    : 3; /* [21:19],        r/w,        0x0 */
+            uint32_t gpadc_pga2_gain   : 3; /* [24:22],        r/w,        0x0 */
+            uint32_t gpadc_pga1_gain   : 3; /* [27:25],        r/w,        0x0 */
+            uint32_t gpadc_dly_sel     : 3; /* [30:28],        r/w,        0x0 */
+            uint32_t gpadc_tsvbe_low   : 1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_config2;
+
+    /* 0x918 : adc converation sequence 1 */
+    union {
+        struct
+        {
+            uint32_t gpadc_scan_pos_0 : 5; /* [ 4: 0],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_1 : 5; /* [ 9: 5],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_2 : 5; /* [14:10],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_3 : 5; /* [19:15],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_4 : 5; /* [24:20],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_5 : 5; /* [29:25],        r/w,        0xf */
+            uint32_t reserved_30_31   : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_scn_pos1;
+
+    /* 0x91C : adc converation sequence 2 */
+    union {
+        struct
+        {
+            uint32_t gpadc_scan_pos_6  : 5; /* [ 4: 0],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_7  : 5; /* [ 9: 5],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_8  : 5; /* [14:10],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_9  : 5; /* [19:15],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_10 : 5; /* [24:20],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_11 : 5; /* [29:25],        r/w,        0xf */
+            uint32_t reserved_30_31    : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_scn_pos2;
+
+    /* 0x920 : adc converation sequence 3 */
+    union {
+        struct
+        {
+            uint32_t gpadc_scan_neg_0 : 5; /* [ 4: 0],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_1 : 5; /* [ 9: 5],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_2 : 5; /* [14:10],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_3 : 5; /* [19:15],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_4 : 5; /* [24:20],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_5 : 5; /* [29:25],        r/w,        0xf */
+            uint32_t reserved_30_31   : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_scn_neg1;
+
+    /* 0x924 : adc converation sequence 4 */
+    union {
+        struct
+        {
+            uint32_t gpadc_scan_neg_6  : 5; /* [ 4: 0],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_7  : 5; /* [ 9: 5],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_8  : 5; /* [14:10],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_9  : 5; /* [19:15],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_10 : 5; /* [24:20],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_11 : 5; /* [29:25],        r/w,        0xf */
+            uint32_t reserved_30_31    : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_scn_neg2;
+
+    /* 0x928 : gpadc_reg_status */
+    union {
+        struct
+        {
+            uint32_t gpadc_data_rdy : 1;  /* [    0],          r,        0x0 */
+            uint32_t reserved_1_15  : 15; /* [15: 1],       rsvd,        0x0 */
+            uint32_t gpadc_reserved : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_status;
+
+    /* 0x92C : gpadc_reg_isr */
+    union {
+        struct
+        {
+            uint32_t gpadc_neg_satur      : 1;  /* [    0],          r,        0x0 */
+            uint32_t gpadc_pos_satur      : 1;  /* [    1],          r,        0x0 */
+            uint32_t reserved_2_3         : 2;  /* [ 3: 2],       rsvd,        0x0 */
+            uint32_t gpadc_neg_satur_clr  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t gpadc_pos_satur_clr  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2;  /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t gpadc_neg_satur_mask : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t gpadc_pos_satur_mask : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t reserved_10_31       : 22; /* [31:10],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_isr;
+
+    /* 0x930 : gpadc_reg_result */
+    union {
+        struct
+        {
+            uint32_t gpadc_data_out : 26; /* [25: 0],          r,  0x1ef0000 */
+            uint32_t reserved_26_31 : 6;  /* [31:26],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_result;
+
+    /* 0x934 : gpadc_reg_raw_result */
+    union {
+        struct
+        {
+            uint32_t gpadc_raw_data : 12; /* [11: 0],          r,        0x0 */
+            uint32_t reserved_12_31 : 20; /* [31:12],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_raw_result;
+
+    /* 0x938 : gpadc_reg_define */
+    union {
+        struct
+        {
+            uint32_t gpadc_os_cal_data : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31    : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_define;
+
+    /* 0x93C : hbncore_resv0 */
+    union {
+        struct
+        {
+            uint32_t hbncore_resv0_data : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } hbncore_resv0;
+
+    /* 0x940 : hbncore_resv1 */
+    union {
+        struct
+        {
+            uint32_t hbncore_resv1_data : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } hbncore_resv1;
+};
+
+typedef volatile struct aon_reg aon_reg_t;
+
+#endif /* __AON_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/bl702.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/bl702.h
new file mode 100644
index 00000000..237d18a1
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/bl702.h
@@ -0,0 +1,307 @@
+#ifndef __BL702_H__
+#define __BL702_H__
+
+/* This file had been modified, add USB_IRQn=43 for temp test, the irq value 43 should be checked after all. */
+
+/** @addtogroup Configuration_section_for_RISCV
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Processor and Core Peripherals
+ */
+
+/* fix 57.6M */
+#define SystemCoreClockSet(val)                 \
+  if ((int)val == (int)(57.6000 * 1000)) {      \
+    BL_WR_WORD(0x4000F108, 57.6 * 1000 * 1000); \
+  } else {                                      \
+    BL_WR_WORD(0x4000F108, val);                \
+  }
+#define SystemCoreClockGet(val) BL_RD_WORD(0x4000F108)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+#ifdef ARCH_ARM
+#define IRQ_NUM_BASE 0
+#endif
+
+#ifdef ARCH_RISCV
+#define IRQ_NUM_BASE 16
+#endif
+/**
+ * @brief BL702 Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+typedef enum {
+#ifdef ARCH_ARM
+  /******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+  NonMaskableInt_IRQn   = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt                                */
+  HardFault_IRQn        = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt                                  */
+  MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt                           */
+  BusFault_IRQn         = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
+  UsageFault_IRQn       = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
+  SVCall_IRQn           = -5,  /*!< 11 Cortex-M4 SV Call Interrupt                                    */
+  DebugMonitor_IRQn     = -4,  /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
+  PendSV_IRQn           = -2,  /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
+  SysTick_IRQn          = -1,  /*!< 15 Cortex-M4 System Tick Interrupt                                */
+#endif
+#ifdef ARCH_RISCV
+  MSOFT_IRQn          = 3,  /*!< 3 RISCV machine software Interrupt                                */
+  MTIME_IRQn          = 7,  /*!< 7 RISCV machine time Interrupt                                    */
+  MEXT_IRQn           = 11, /*!< 11 RISCV external  Interrupt                                      */
+  CLIC_SOFT_PEND_IRQn = 12, /*!< 12 RISCV CLIC software pending  Interrupt                         */
+#endif
+  /******  BL702 specific Interrupt Numbers **********************************************************************/
+  BMX_ERR_IRQn          = IRQ_NUM_BASE + 0,  /*!< BMX Error Interrupt                                               */
+  BMX_TO_IRQn           = IRQ_NUM_BASE + 1,  /*!< BMX Timeout Interrupt                                             */
+  L1C_BMX_ERR_IRQn      = IRQ_NUM_BASE + 2,  /*!< L1C BMX Error Interrupt                                           */
+  L1C_BMX_TO_IRQn       = IRQ_NUM_BASE + 3,  /*!< L1C BMX Timeout Interrupt                                         */
+  SEC_BMX_ERR_IRQn      = IRQ_NUM_BASE + 4,  /*!< SEC BMX Error Interrupt                                           */
+  RF_TOP_INT0_IRQn      = IRQ_NUM_BASE + 5,  /*!< RF_TOP_INT0 Interrupt                                             */
+  RF_TOP_INT1_IRQn      = IRQ_NUM_BASE + 6,  /*!< RF_TOP_INT1 Interrupt                                             */
+  RESERVED0             = IRQ_NUM_BASE + 7,  /*!< RESERVED Interrupt                                                */
+  DMA_BMX_ERR_IRQn      = IRQ_NUM_BASE + 8,  /*!< DMA BMX Error Interrupt                                           */
+  SEC_GMAC_IRQn         = IRQ_NUM_BASE + 9,  /*!< SEC_ENG_GMAC_INT Interrupt                                        */
+  SEC_CDET_IRQn         = IRQ_NUM_BASE + 10, /*!< SEC_ENG_CDET_INT Interrupt                                        */
+  SEC_PKA_IRQn          = IRQ_NUM_BASE + 11, /*!< SEC_ENG_PKA_INT  Interrupt                                        */
+  SEC_TRNG_IRQn         = IRQ_NUM_BASE + 12, /*!< SEC_ENG_TRNG_INT Interrupt                                        */
+  SEC_AES_IRQn          = IRQ_NUM_BASE + 13, /*!< SEC_ENG_AES_INT  Interrupt                                        */
+  SEC_SHA_IRQn          = IRQ_NUM_BASE + 14, /*!< SEC_ENG_SHA_INT  Interrupt                                        */
+  DMA_ALL_IRQn          = IRQ_NUM_BASE + 15, /*!< DMA ALL Interrupt                                                 */
+  MJPEG_IRQn            = IRQ_NUM_BASE + 16, /*!< MJPEG Interrupt                                                   */
+  CAM_IRQn              = IRQ_NUM_BASE + 17, /*!< CAM Interrupt                                                     */
+  I2S_IRQn              = IRQ_NUM_BASE + 18, /*!< I2S Interrupt                                                     */
+  IRTX_IRQn             = IRQ_NUM_BASE + 19, /*!< IR TX Interrupt                                                   */
+  IRRX_IRQn             = IRQ_NUM_BASE + 20, /*!< IR RX Interrupt                                                   */
+  USB_IRQn              = IRQ_NUM_BASE + 21, /*!< USB Interrupt                                                     */
+  EMAC_IRQn             = IRQ_NUM_BASE + 22, /*!< EMAC  Interrupt                                                   */
+  SF_CTRL_IRQn          = IRQ_NUM_BASE + 23, /*!< SF_CTRL   Interrupt                                               */
+  RESERVED1             = IRQ_NUM_BASE + 24, /*!< RESERVED  Interrupt                                               */
+  GPADC_DMA_IRQn        = IRQ_NUM_BASE + 25, /*!< GPADC_DMA Interrupt                                               */
+  EFUSE_IRQn            = IRQ_NUM_BASE + 26, /*!< Efuse Interrupt                                                   */
+  SPI_IRQn              = IRQ_NUM_BASE + 27, /*!< SPI   Interrupt                                                   */
+  RESERVED2             = IRQ_NUM_BASE + 28, /*!< RESERVED Interrupt                                                */
+  UART0_IRQn            = IRQ_NUM_BASE + 29, /*!< UART  Interrupt                                                   */
+  UART1_IRQn            = IRQ_NUM_BASE + 30, /*!< UART1 Interrupt                                                   */
+  RESERVED3             = IRQ_NUM_BASE + 31, /*!< RESERVED Interrupt                                                */
+  I2C_IRQn              = IRQ_NUM_BASE + 32, /*!< I2C   Interrupt                                                   */
+  RESERVED4             = IRQ_NUM_BASE + 33, /*!< RESERVED Interrupt                                                */
+  PWM_IRQn              = IRQ_NUM_BASE + 34, /*!< PWM   Interrupt                                                   */
+  RESERVED5             = IRQ_NUM_BASE + 35, /*!< RESERVED Interrupt                                                */
+  TIMER_CH0_IRQn        = IRQ_NUM_BASE + 36, /*!< Timer Channel 0 Interrupt                                         */
+  TIMER_CH1_IRQn        = IRQ_NUM_BASE + 37, /*!< Timer Channel 1 Interrupt                                         */
+  TIMER_WDT_IRQn        = IRQ_NUM_BASE + 38, /*!< Timer Watch Dog Interrupt                                         */
+  KYS_IRQn              = IRQ_NUM_BASE + 39, /*!< KYS Interrupt                                                     */
+  QDEC0_IRQn            = IRQ_NUM_BASE + 40, /*!< QDEC0 Interrupt                                                   */
+  QDEC1_IRQn            = IRQ_NUM_BASE + 41, /*!< QDEC1 Interrupt                                                   */
+  QDEC2_IRQn            = IRQ_NUM_BASE + 42, /*!< QDEC2 Interrupt                                                   */
+  RESERVED6             = IRQ_NUM_BASE + 43, /*!< RESERVED Interrupt                                                */
+  GPIO_INT0_IRQn        = IRQ_NUM_BASE + 44, /*!< GPIO_INT0 Interrupt                                               */
+  TOUCH_IRQn            = IRQ_NUM_BASE + 45, /*!< TOUCH Interrupt                                                   */
+  RESERVED7             = IRQ_NUM_BASE + 46, /*!< RESERVED Interrupt                                                */
+  M154_REQ_ENH_ACK_IRQn = IRQ_NUM_BASE + 47, /*!< M154_REQ Interrupt                                                */
+  M154_IRQn             = IRQ_NUM_BASE + 48, /*!< M154 Interrupt                                                    */
+  M154_AES_IRQn         = IRQ_NUM_BASE + 49, /*!< M154_AES Interrupt                                                */
+  PDS_WAKEUP_IRQn       = IRQ_NUM_BASE + 50, /*!< PDS Wakeup Interrupt                                              */
+  HBN_OUT0_IRQn         = IRQ_NUM_BASE + 51, /*!< Hibernate out 0 Interrupt                                         */
+  HBN_OUT1_IRQn         = IRQ_NUM_BASE + 52, /*!< Hibernate out 1 Interrupt                                         */
+  BOR_IRQn              = IRQ_NUM_BASE + 53, /*!< BOR Interrupt                                                     */
+  WIFI_IRQn             = IRQ_NUM_BASE + 54, /*!< WIFI To CPU Interrupt                                             */
+  BZ_PHY_IRQn           = IRQ_NUM_BASE + 55, /*!< BZ_PHY Interrupt                                                  */
+  BLE_IRQn              = IRQ_NUM_BASE + 56, /*!< BLE Interrupt                                                     */
+  MAC_TXRX_TIMER_IRQn   = IRQ_NUM_BASE + 57, /*!< mac_int_tx_rx_timer Interrupt                                     */
+  MAC_TXRX_MISC_IRQn    = IRQ_NUM_BASE + 58, /*!< mac_int_tx_rx_misc Interrupt                                      */
+  MAC_RX_TRG_IRQn       = IRQ_NUM_BASE + 59, /*!< mac_int_rx_trigger Interrupt                                      */
+  MAC_TX_TRG_IRQn       = IRQ_NUM_BASE + 60, /*!< mac_int_tx_trigger Interrupt                                      */
+  MAC_GEN_IRQn          = IRQ_NUM_BASE + 61, /*!< mac_int_gen Interrupt                                             */
+  MAC_PORT_TRG_IRQn     = IRQ_NUM_BASE + 62, /*!< mac_int_port_trigger Interrupt                                    */
+  WIFI_IPC_PUBLIC_IRQn  = IRQ_NUM_BASE + 63, /*!< wifi IPC public Interrupt                                         */
+  IRQn_LAST,
+} IRQn_Type;
+
+/**
+ * @brief BL702 Memory Map Definitions
+ */
+#define BL702_FLASH_XIP_BASE        0x23000000
+#define BL702_FLASH_XIP_END         (0x23000000 + 16 * 1024 * 1024)
+#define BL702_FLASH_XIP_REMAP0_BASE 0x33000000
+#define BL702_FLASH_XIP_REMAP0_END  (0x33000000 + 16 * 1024 * 1024)
+#define BL702_FLASH_XIP_REMAP1_BASE 0x43000000
+#define BL702_FLASH_XIP_REMAP1_END  (0x43000000 + 16 * 1024 * 1024)
+#define BL702_FLASH_XIP_REMAP2_BASE 0x53000000
+#define BL702_FLASH_XIP_REMAP2_END  (0x53000000 + 16 * 1024 * 1024)
+
+#define BL702_PSRAM_XIP_BASE        0x24000000
+#define BL702_PSRAM_XIP_END         (0x24000000 + 16 * 1024 * 1024)
+#define BL702_PSRAM_XIP_REMAP0_BASE 0x34000000
+#define BL702_PSRAM_XIP_REMAP0_END  (0x34000000 + 16 * 1024 * 1024)
+#define BL702_PSRAM_XIP_REMAP1_BASE 0x44000000
+#define BL702_PSRAM_XIP_REMAP1_END  (0x44000000 + 16 * 1024 * 1024)
+#define BL702_PSRAM_XIP_REMAP2_BASE 0x54000000
+#define BL702_PSRAM_XIP_REMAP2_END  (0x54000000 + 16 * 1024 * 1024)
+
+#define BL702_WRAM_BASE        0x42020000
+#define BL702_WRAM_END         (0x42020000 + 56 * 1024)
+#define BL702_WRAM_REMAP0_BASE 0x22020000
+#define BL702_WRAM_REMAP0_END  (0x22020000 + 56 * 1024)
+#define BL702_WRAM_REMAP1_BASE 0x32020000
+#define BL702_WRAM_REMAP1_END  (0x32020000 + 56 * 1024)
+#define BL702_WRAM_REMAP2_BASE 0x52020000
+#define BL702_WRAM_REMAP2_END  (0x52020000 + 56 * 1024)
+
+#define BL702_TCM_BASE        0x22010000
+#define BL702_TCM_END         (0x22010000 + (16 + 48) * 1024)
+#define BL702_TCM_REMAP0_BASE 0x32010000
+#define BL702_TCM_REMAP0_END  (0x32010000 + (16 + 48) * 1024)
+#define BL702_TCM_REMAP1_BASE 0x42010000
+#define BL702_TCM_REMAP1_END  (0x42010000 + (16 + 48) * 1024)
+#define BL702_TCM_REMAP2_BASE 0x52010000
+#define BL702_TCM_REMAP2_END  (0x52010000 + (16 + 48) * 1024)
+/*@} end of group Memory_Map_Section */
+
+/* BL702 peripherals base address */
+#define GLB_BASE         ((uint32_t)0x40000000)
+#define RF_BASE          ((uint32_t)0x40001000)
+#define BZ_PHY_BASE      ((uint32_t)0x40001000)
+#define BZ_PHY_AGC_BASE  ((uint32_t)0x40001000)
+#define GPIP_BASE        ((uint32_t)0x40002000) /*!< AUX module base address */
+#define SEC_DBG_BASE     ((uint32_t)0x40003000) /*!< Security Debug module base address */
+#define SEC_ENG_BASE     ((uint32_t)0x40004000) /*!< Security Engine module base address */
+#define TZC_SEC_BASE     ((uint32_t)0x40005000) /*!< Trustzone control security base address */
+#define TZC_NSEC_BASE    ((uint32_t)0x40006000) /*!< Trustzone control none-security base address */
+#define EF_DATA_BASE     ((uint32_t)0x40007000)
+#define EF_CTRL_BASE     ((uint32_t)0x40007000)
+#define CCI_BASE         ((uint32_t)0x40008000)
+#define L1C_BASE         ((uint32_t)0x40009000) /*!< L1 cache config base address */
+#define UART0_BASE       ((uint32_t)0x4000A000)
+#define UART1_BASE       ((uint32_t)0x4000A100)
+#define SPI_BASE         ((uint32_t)0x4000A200)
+#define I2C_BASE         ((uint32_t)0x4000A300)
+#define PWM_BASE         ((uint32_t)0x4000A400)
+#define TIMER_BASE       ((uint32_t)0x4000A500)
+#define IR_BASE          ((uint32_t)0x4000A600)
+#define CKS_BASE         ((uint32_t)0x4000A700)
+#define QDEC0_BASE       ((uint32_t)0x4000A800)
+#define QDEC1_BASE       ((uint32_t)0x4000A840)
+#define QDEC2_BASE       ((uint32_t)0x4000A880)
+#define KYS_BASE         ((uint32_t)0x4000A900)
+#define I2S_BASE         ((uint32_t)0x4000AA00)
+#define CAM_BASE         ((uint32_t)0x4000AD00)
+#define MJPEG_BASE       ((uint32_t)0x4000AE00)
+#define SF_CTRL_BASE     ((uint32_t)0x4000B000)
+#define SF_CTRL_BUF_BASE ((uint32_t)0x4000B700)
+#define DMA_BASE         ((uint32_t)0x4000C000)
+#define EMAC_BASE        ((uint32_t)0x4000D000)
+#define USB_BASE         ((uint32_t)0x4000D800)
+#define PDS_BASE         ((uint32_t)0x4000E000) /*!< Power down sleep module base address */
+#define HBN_BASE         ((uint32_t)0x4000F000) /*!< Hibernate module base address */
+#define AON_BASE         ((uint32_t)0x4000F000) /*!< Always on module base address */
+#define MAC154_BASE      ((uint32_t)0x4C000000) /*!< MAC154 module base address */
+
+#define HBN_RAM_BASE ((uint32_t)0x40010000)
+
+typedef enum {
+  BL_AHB_SLAVE1_GLB                = 0x00,
+  BL_AHB_SLAVE1_MIX                = 0x01,
+  BL_AHB_SLAVE1_GPIP               = 0x02,
+  BL_AHB_SLAVE1_SEC_DBG            = 0x03,
+  BL_AHB_SLAVE1_SEC                = 0x04,
+  BL_AHB_SLAVE1_TZ1                = 0x05,
+  BL_AHB_SLAVE1_TZ2                = 0x06,
+  BL_AHB_SLAVE1_EFUSE              = 0x07,
+  BL_AHB_SLAVE1_CCI                = 0x08,
+  BL_AHB_SLAVE1_L1C                = 0x09,
+  BL_AHB_SLAVE1_S1A_ALL            = 0x0A,
+  BL_AHB_SLAVE1_SFC                = 0x0B,
+  BL_AHB_SLAVE1_DMA                = 0x0C,
+  BL_AHB_SLAVE1_EMAC               = 0x0D,
+  BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM = 0x0E,
+  BL_AHB_SLAVE1_RSVD0F             = 0x0F,
+  BL_AHB_SLAVE1_UART0              = 0x10,
+  BL_AHB_SLAVE1_UART1              = 0x11,
+  BL_AHB_SLAVE1_SPI                = 0x12,
+  BL_AHB_SLAVE1_I2C                = 0x13,
+  BL_AHB_SLAVE1_PWM                = 0x14,
+  BL_AHB_SLAVE1_TMR                = 0x15,
+  BL_AHB_SLAVE1_IRR                = 0x16,
+  BL_AHB_SLAVE1_CKS                = 0x17,
+  BL_AHB_SLAVE1_QDEC               = 0x18,
+  BL_AHB_SLAVE1_KYS                = 0x19,
+  BL_AHB_SLAVE1_I2S                = 0x1A,
+  BL_AHB_SLAVE1_RSVD1B             = 0x1B,
+  BL_AHB_SLAVE1_USB                = 0x1C,
+  BL_AHB_SLAVE1_CAM                = 0x1D,
+  BL_AHB_SLAVE1_MJPEG              = 0x1E,
+  BL_AHB_SLAVE1_MAX                = 0x1F,
+} BL_AHB_Slave1_Type;
+
+typedef enum {
+  BL_AHB_SEC_ENG_AES0 = 0,
+  BL_AHB_SEC_ENG_AES1,
+  BL_AHB_SEC_ENG_SHA0,
+  BL_AHB_SEC_ENG_SHA1,
+} BL_AHB_Sec_Eng_Type;
+
+typedef enum {
+  BL_AHB_DMA0_CH0 = 0,
+  BL_AHB_DMA0_CH1,
+  BL_AHB_DMA0_CH2,
+  BL_AHB_DMA0_CH3,
+  BL_AHB_DMA0_CH4,
+  BL_AHB_DMA0_CH5,
+  BL_AHB_DMA0_CH6,
+  BL_AHB_DMA0_CH7,
+} BL_AHB_DMA0_CHNL_Type;
+
+typedef enum {
+  BL_AHB_SLAVE2_WIFI_CFG = 0,
+  BL_AHB_SLAVE2_MAX,
+} BL_AHB_Slave2_Type;
+
+typedef enum {
+  BL_AHB_SLAVE3_BLE = 0,
+  BL_AHB_SLAVE3_MAX,
+} BL_AHB_Slave3_Type;
+
+typedef enum {
+  BL_CORE_MASTER_IBUS_CPU = 0,
+  BL_CORE_MASTER_DBUS_CPU,
+  BL_CORE_MASTER_BUS_S2F,
+  BL_CORE_MASTER_MAX,
+} BL_Core_Master_Type;
+
+typedef enum {
+  BL_CORE_SLAVE0_DTCM_CPU = 0,
+  BL_CORE_SLAVE0_MAX,
+} BL_Core_Slave0_Type;
+
+typedef enum {
+  BL_CORE_SLAVE1_XIP_CPU = 0,
+  BL_CORE_SLAVE1_ITCM_CPU,
+  BL_CORE_SLAVE1_ROM,
+  BL_CORE_SLAVE1_MAX,
+} BL_Core_Slave1_Type;
+
+typedef enum {
+  BL_CORE_SLAVE2_F2S = 0,
+  BL_CORE_SLAVE2_MAX,
+} BL_Core_Slave2_Type;
+
+/**
+ * @}
+ */
+#include 
+#include 
+
+/**
+ * @}
+ */
+
+#endif
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/bl70x_reg.svc b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/bl70x_reg.svc
new file mode 100644
index 00000000..21a68c83
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/bl70x_reg.svc
@@ -0,0 +1,4968 @@
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+
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/cam_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/cam_reg.h
new file mode 100644
index 00000000..92613df8
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/cam_reg.h
@@ -0,0 +1,1203 @@
+/**
+  ******************************************************************************
+  * @file    cam_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __CAM_REG_H__
+#define __CAM_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : dvp2axi_configue */
+#define CAM_DVP2AXI_CONFIGUE_OFFSET (0x0)
+#define CAM_REG_DVP_ENABLE          CAM_REG_DVP_ENABLE
+#define CAM_REG_DVP_ENABLE_POS      (0U)
+#define CAM_REG_DVP_ENABLE_LEN      (1U)
+#define CAM_REG_DVP_ENABLE_MSK      (((1U << CAM_REG_DVP_ENABLE_LEN) - 1) << CAM_REG_DVP_ENABLE_POS)
+#define CAM_REG_DVP_ENABLE_UMSK     (~(((1U << CAM_REG_DVP_ENABLE_LEN) - 1) << CAM_REG_DVP_ENABLE_POS))
+#define CAM_REG_SW_MODE             CAM_REG_SW_MODE
+#define CAM_REG_SW_MODE_POS         (1U)
+#define CAM_REG_SW_MODE_LEN         (1U)
+#define CAM_REG_SW_MODE_MSK         (((1U << CAM_REG_SW_MODE_LEN) - 1) << CAM_REG_SW_MODE_POS)
+#define CAM_REG_SW_MODE_UMSK        (~(((1U << CAM_REG_SW_MODE_LEN) - 1) << CAM_REG_SW_MODE_POS))
+#define CAM_REG_FRAM_VLD_POL        CAM_REG_FRAM_VLD_POL
+#define CAM_REG_FRAM_VLD_POL_POS    (2U)
+#define CAM_REG_FRAM_VLD_POL_LEN    (1U)
+#define CAM_REG_FRAM_VLD_POL_MSK    (((1U << CAM_REG_FRAM_VLD_POL_LEN) - 1) << CAM_REG_FRAM_VLD_POL_POS)
+#define CAM_REG_FRAM_VLD_POL_UMSK   (~(((1U << CAM_REG_FRAM_VLD_POL_LEN) - 1) << CAM_REG_FRAM_VLD_POL_POS))
+#define CAM_REG_LINE_VLD_POL        CAM_REG_LINE_VLD_POL
+#define CAM_REG_LINE_VLD_POL_POS    (3U)
+#define CAM_REG_LINE_VLD_POL_LEN    (1U)
+#define CAM_REG_LINE_VLD_POL_MSK    (((1U << CAM_REG_LINE_VLD_POL_LEN) - 1) << CAM_REG_LINE_VLD_POL_POS)
+#define CAM_REG_LINE_VLD_POL_UMSK   (~(((1U << CAM_REG_LINE_VLD_POL_LEN) - 1) << CAM_REG_LINE_VLD_POL_POS))
+#define CAM_REG_HBURST              CAM_REG_HBURST
+#define CAM_REG_HBURST_POS          (4U)
+#define CAM_REG_HBURST_LEN          (2U)
+#define CAM_REG_HBURST_MSK          (((1U << CAM_REG_HBURST_LEN) - 1) << CAM_REG_HBURST_POS)
+#define CAM_REG_HBURST_UMSK         (~(((1U << CAM_REG_HBURST_LEN) - 1) << CAM_REG_HBURST_POS))
+#define CAM_REG_DVP_MODE            CAM_REG_DVP_MODE
+#define CAM_REG_DVP_MODE_POS        (8U)
+#define CAM_REG_DVP_MODE_LEN        (3U)
+#define CAM_REG_DVP_MODE_MSK        (((1U << CAM_REG_DVP_MODE_LEN) - 1) << CAM_REG_DVP_MODE_POS)
+#define CAM_REG_DVP_MODE_UMSK       (~(((1U << CAM_REG_DVP_MODE_LEN) - 1) << CAM_REG_DVP_MODE_POS))
+#define CAM_REG_HW_MODE_FWRAP       CAM_REG_HW_MODE_FWRAP
+#define CAM_REG_HW_MODE_FWRAP_POS   (11U)
+#define CAM_REG_HW_MODE_FWRAP_LEN   (1U)
+#define CAM_REG_HW_MODE_FWRAP_MSK   (((1U << CAM_REG_HW_MODE_FWRAP_LEN) - 1) << CAM_REG_HW_MODE_FWRAP_POS)
+#define CAM_REG_HW_MODE_FWRAP_UMSK  (~(((1U << CAM_REG_HW_MODE_FWRAP_LEN) - 1) << CAM_REG_HW_MODE_FWRAP_POS))
+#define CAM_REG_DROP_EN             CAM_REG_DROP_EN
+#define CAM_REG_DROP_EN_POS         (12U)
+#define CAM_REG_DROP_EN_LEN         (1U)
+#define CAM_REG_DROP_EN_MSK         (((1U << CAM_REG_DROP_EN_LEN) - 1) << CAM_REG_DROP_EN_POS)
+#define CAM_REG_DROP_EN_UMSK        (~(((1U << CAM_REG_DROP_EN_LEN) - 1) << CAM_REG_DROP_EN_POS))
+#define CAM_REG_DROP_EVEN           CAM_REG_DROP_EVEN
+#define CAM_REG_DROP_EVEN_POS       (13U)
+#define CAM_REG_DROP_EVEN_LEN       (1U)
+#define CAM_REG_DROP_EVEN_MSK       (((1U << CAM_REG_DROP_EVEN_LEN) - 1) << CAM_REG_DROP_EVEN_POS)
+#define CAM_REG_DROP_EVEN_UMSK      (~(((1U << CAM_REG_DROP_EVEN_LEN) - 1) << CAM_REG_DROP_EVEN_POS))
+#define CAM_REG_SUBSAMPLE_EN        CAM_REG_SUBSAMPLE_EN
+#define CAM_REG_SUBSAMPLE_EN_POS    (14U)
+#define CAM_REG_SUBSAMPLE_EN_LEN    (1U)
+#define CAM_REG_SUBSAMPLE_EN_MSK    (((1U << CAM_REG_SUBSAMPLE_EN_LEN) - 1) << CAM_REG_SUBSAMPLE_EN_POS)
+#define CAM_REG_SUBSAMPLE_EN_UMSK   (~(((1U << CAM_REG_SUBSAMPLE_EN_LEN) - 1) << CAM_REG_SUBSAMPLE_EN_POS))
+#define CAM_REG_SUBSAMPLE_EVEN      CAM_REG_SUBSAMPLE_EVEN
+#define CAM_REG_SUBSAMPLE_EVEN_POS  (15U)
+#define CAM_REG_SUBSAMPLE_EVEN_LEN  (1U)
+#define CAM_REG_SUBSAMPLE_EVEN_MSK  (((1U << CAM_REG_SUBSAMPLE_EVEN_LEN) - 1) << CAM_REG_SUBSAMPLE_EVEN_POS)
+#define CAM_REG_SUBSAMPLE_EVEN_UMSK (~(((1U << CAM_REG_SUBSAMPLE_EVEN_LEN) - 1) << CAM_REG_SUBSAMPLE_EVEN_POS))
+#define CAM_REG_INTERLV_MODE        CAM_REG_INTERLV_MODE
+#define CAM_REG_INTERLV_MODE_POS    (16U)
+#define CAM_REG_INTERLV_MODE_LEN    (1U)
+#define CAM_REG_INTERLV_MODE_MSK    (((1U << CAM_REG_INTERLV_MODE_LEN) - 1) << CAM_REG_INTERLV_MODE_POS)
+#define CAM_REG_INTERLV_MODE_UMSK   (~(((1U << CAM_REG_INTERLV_MODE_LEN) - 1) << CAM_REG_INTERLV_MODE_POS))
+#define CAM_REG_DVP_PIX_CLK_CG      CAM_REG_DVP_PIX_CLK_CG
+#define CAM_REG_DVP_PIX_CLK_CG_POS  (20U)
+#define CAM_REG_DVP_PIX_CLK_CG_LEN  (1U)
+#define CAM_REG_DVP_PIX_CLK_CG_MSK  (((1U << CAM_REG_DVP_PIX_CLK_CG_LEN) - 1) << CAM_REG_DVP_PIX_CLK_CG_POS)
+#define CAM_REG_DVP_PIX_CLK_CG_UMSK (~(((1U << CAM_REG_DVP_PIX_CLK_CG_LEN) - 1) << CAM_REG_DVP_PIX_CLK_CG_POS))
+#define CAM_REG_DVP_WAIT_CYCLE      CAM_REG_DVP_WAIT_CYCLE
+#define CAM_REG_DVP_WAIT_CYCLE_POS  (24U)
+#define CAM_REG_DVP_WAIT_CYCLE_LEN  (8U)
+#define CAM_REG_DVP_WAIT_CYCLE_MSK  (((1U << CAM_REG_DVP_WAIT_CYCLE_LEN) - 1) << CAM_REG_DVP_WAIT_CYCLE_POS)
+#define CAM_REG_DVP_WAIT_CYCLE_UMSK (~(((1U << CAM_REG_DVP_WAIT_CYCLE_LEN) - 1) << CAM_REG_DVP_WAIT_CYCLE_POS))
+
+/* 0x4 : dvp2ahb_addr_start_0 */
+#define CAM_DVP2AHB_ADDR_START_0_OFFSET (0x4)
+#define CAM_REG_ADDR_START_0            CAM_REG_ADDR_START_0
+#define CAM_REG_ADDR_START_0_POS        (0U)
+#define CAM_REG_ADDR_START_0_LEN        (32U)
+#define CAM_REG_ADDR_START_0_MSK        (((1U << CAM_REG_ADDR_START_0_LEN) - 1) << CAM_REG_ADDR_START_0_POS)
+#define CAM_REG_ADDR_START_0_UMSK       (~(((1U << CAM_REG_ADDR_START_0_LEN) - 1) << CAM_REG_ADDR_START_0_POS))
+
+/* 0x8 : dvp2ahb_mem_bcnt_0 */
+#define CAM_DVP2AHB_MEM_BCNT_0_OFFSET (0x8)
+#define CAM_REG_MEM_BURST_CNT_0       CAM_REG_MEM_BURST_CNT_0
+#define CAM_REG_MEM_BURST_CNT_0_POS   (0U)
+#define CAM_REG_MEM_BURST_CNT_0_LEN   (32U)
+#define CAM_REG_MEM_BURST_CNT_0_MSK   (((1U << CAM_REG_MEM_BURST_CNT_0_LEN) - 1) << CAM_REG_MEM_BURST_CNT_0_POS)
+#define CAM_REG_MEM_BURST_CNT_0_UMSK  (~(((1U << CAM_REG_MEM_BURST_CNT_0_LEN) - 1) << CAM_REG_MEM_BURST_CNT_0_POS))
+
+/* 0xC : dvp2ahb_frame_bcnt_0 */
+#define CAM_DVP2AHB_FRAME_BCNT_0_OFFSET (0xC)
+#define CAM_REG_FRAME_BURST_CNT_0       CAM_REG_FRAME_BURST_CNT_0
+#define CAM_REG_FRAME_BURST_CNT_0_POS   (0U)
+#define CAM_REG_FRAME_BURST_CNT_0_LEN   (32U)
+#define CAM_REG_FRAME_BURST_CNT_0_MSK   (((1U << CAM_REG_FRAME_BURST_CNT_0_LEN) - 1) << CAM_REG_FRAME_BURST_CNT_0_POS)
+#define CAM_REG_FRAME_BURST_CNT_0_UMSK  (~(((1U << CAM_REG_FRAME_BURST_CNT_0_LEN) - 1) << CAM_REG_FRAME_BURST_CNT_0_POS))
+
+/* 0x10 : dvp2ahb_addr_start_1 */
+#define CAM_DVP2AHB_ADDR_START_1_OFFSET (0x10)
+#define CAM_REG_ADDR_START_1            CAM_REG_ADDR_START_1
+#define CAM_REG_ADDR_START_1_POS        (0U)
+#define CAM_REG_ADDR_START_1_LEN        (32U)
+#define CAM_REG_ADDR_START_1_MSK        (((1U << CAM_REG_ADDR_START_1_LEN) - 1) << CAM_REG_ADDR_START_1_POS)
+#define CAM_REG_ADDR_START_1_UMSK       (~(((1U << CAM_REG_ADDR_START_1_LEN) - 1) << CAM_REG_ADDR_START_1_POS))
+
+/* 0x14 : dvp2ahb_mem_bcnt_1 */
+#define CAM_DVP2AHB_MEM_BCNT_1_OFFSET (0x14)
+#define CAM_REG_MEM_BURST_CNT_1       CAM_REG_MEM_BURST_CNT_1
+#define CAM_REG_MEM_BURST_CNT_1_POS   (0U)
+#define CAM_REG_MEM_BURST_CNT_1_LEN   (32U)
+#define CAM_REG_MEM_BURST_CNT_1_MSK   (((1U << CAM_REG_MEM_BURST_CNT_1_LEN) - 1) << CAM_REG_MEM_BURST_CNT_1_POS)
+#define CAM_REG_MEM_BURST_CNT_1_UMSK  (~(((1U << CAM_REG_MEM_BURST_CNT_1_LEN) - 1) << CAM_REG_MEM_BURST_CNT_1_POS))
+
+/* 0x18 : dvp2ahb_frame_bcnt_1 */
+#define CAM_DVP2AHB_FRAME_BCNT_1_OFFSET (0x18)
+#define CAM_REG_FRAME_BURST_CNT_1       CAM_REG_FRAME_BURST_CNT_1
+#define CAM_REG_FRAME_BURST_CNT_1_POS   (0U)
+#define CAM_REG_FRAME_BURST_CNT_1_LEN   (32U)
+#define CAM_REG_FRAME_BURST_CNT_1_MSK   (((1U << CAM_REG_FRAME_BURST_CNT_1_LEN) - 1) << CAM_REG_FRAME_BURST_CNT_1_POS)
+#define CAM_REG_FRAME_BURST_CNT_1_UMSK  (~(((1U << CAM_REG_FRAME_BURST_CNT_1_LEN) - 1) << CAM_REG_FRAME_BURST_CNT_1_POS))
+
+/* 0x1C : dvp_status_and_error */
+#define CAM_DVP_STATUS_AND_ERROR_OFFSET (0x1C)
+#define CAM_STS_NORMAL_INT_0            CAM_STS_NORMAL_INT_0
+#define CAM_STS_NORMAL_INT_0_POS        (0U)
+#define CAM_STS_NORMAL_INT_0_LEN        (1U)
+#define CAM_STS_NORMAL_INT_0_MSK        (((1U << CAM_STS_NORMAL_INT_0_LEN) - 1) << CAM_STS_NORMAL_INT_0_POS)
+#define CAM_STS_NORMAL_INT_0_UMSK       (~(((1U << CAM_STS_NORMAL_INT_0_LEN) - 1) << CAM_STS_NORMAL_INT_0_POS))
+#define CAM_STS_NORMAL_INT_1            CAM_STS_NORMAL_INT_1
+#define CAM_STS_NORMAL_INT_1_POS        (1U)
+#define CAM_STS_NORMAL_INT_1_LEN        (1U)
+#define CAM_STS_NORMAL_INT_1_MSK        (((1U << CAM_STS_NORMAL_INT_1_LEN) - 1) << CAM_STS_NORMAL_INT_1_POS)
+#define CAM_STS_NORMAL_INT_1_UMSK       (~(((1U << CAM_STS_NORMAL_INT_1_LEN) - 1) << CAM_STS_NORMAL_INT_1_POS))
+#define CAM_STS_MEM_INT_0               CAM_STS_MEM_INT_0
+#define CAM_STS_MEM_INT_0_POS           (2U)
+#define CAM_STS_MEM_INT_0_LEN           (1U)
+#define CAM_STS_MEM_INT_0_MSK           (((1U << CAM_STS_MEM_INT_0_LEN) - 1) << CAM_STS_MEM_INT_0_POS)
+#define CAM_STS_MEM_INT_0_UMSK          (~(((1U << CAM_STS_MEM_INT_0_LEN) - 1) << CAM_STS_MEM_INT_0_POS))
+#define CAM_STS_MEM_INT_1               CAM_STS_MEM_INT_1
+#define CAM_STS_MEM_INT_1_POS           (3U)
+#define CAM_STS_MEM_INT_1_LEN           (1U)
+#define CAM_STS_MEM_INT_1_MSK           (((1U << CAM_STS_MEM_INT_1_LEN) - 1) << CAM_STS_MEM_INT_1_POS)
+#define CAM_STS_MEM_INT_1_UMSK          (~(((1U << CAM_STS_MEM_INT_1_LEN) - 1) << CAM_STS_MEM_INT_1_POS))
+#define CAM_STS_FRAME_INT_0             CAM_STS_FRAME_INT_0
+#define CAM_STS_FRAME_INT_0_POS         (4U)
+#define CAM_STS_FRAME_INT_0_LEN         (1U)
+#define CAM_STS_FRAME_INT_0_MSK         (((1U << CAM_STS_FRAME_INT_0_LEN) - 1) << CAM_STS_FRAME_INT_0_POS)
+#define CAM_STS_FRAME_INT_0_UMSK        (~(((1U << CAM_STS_FRAME_INT_0_LEN) - 1) << CAM_STS_FRAME_INT_0_POS))
+#define CAM_STS_FRAME_INT_1             CAM_STS_FRAME_INT_1
+#define CAM_STS_FRAME_INT_1_POS         (5U)
+#define CAM_STS_FRAME_INT_1_LEN         (1U)
+#define CAM_STS_FRAME_INT_1_MSK         (((1U << CAM_STS_FRAME_INT_1_LEN) - 1) << CAM_STS_FRAME_INT_1_POS)
+#define CAM_STS_FRAME_INT_1_UMSK        (~(((1U << CAM_STS_FRAME_INT_1_LEN) - 1) << CAM_STS_FRAME_INT_1_POS))
+#define CAM_STS_FIFO_INT_0              CAM_STS_FIFO_INT_0
+#define CAM_STS_FIFO_INT_0_POS          (6U)
+#define CAM_STS_FIFO_INT_0_LEN          (1U)
+#define CAM_STS_FIFO_INT_0_MSK          (((1U << CAM_STS_FIFO_INT_0_LEN) - 1) << CAM_STS_FIFO_INT_0_POS)
+#define CAM_STS_FIFO_INT_0_UMSK         (~(((1U << CAM_STS_FIFO_INT_0_LEN) - 1) << CAM_STS_FIFO_INT_0_POS))
+#define CAM_STS_FIFO_INT_1              CAM_STS_FIFO_INT_1
+#define CAM_STS_FIFO_INT_1_POS          (7U)
+#define CAM_STS_FIFO_INT_1_LEN          (1U)
+#define CAM_STS_FIFO_INT_1_MSK          (((1U << CAM_STS_FIFO_INT_1_LEN) - 1) << CAM_STS_FIFO_INT_1_POS)
+#define CAM_STS_FIFO_INT_1_UMSK         (~(((1U << CAM_STS_FIFO_INT_1_LEN) - 1) << CAM_STS_FIFO_INT_1_POS))
+#define CAM_STS_HCNT_INT                CAM_STS_HCNT_INT
+#define CAM_STS_HCNT_INT_POS            (8U)
+#define CAM_STS_HCNT_INT_LEN            (1U)
+#define CAM_STS_HCNT_INT_MSK            (((1U << CAM_STS_HCNT_INT_LEN) - 1) << CAM_STS_HCNT_INT_POS)
+#define CAM_STS_HCNT_INT_UMSK           (~(((1U << CAM_STS_HCNT_INT_LEN) - 1) << CAM_STS_HCNT_INT_POS))
+#define CAM_STS_VCNT_INT                CAM_STS_VCNT_INT
+#define CAM_STS_VCNT_INT_POS            (9U)
+#define CAM_STS_VCNT_INT_LEN            (1U)
+#define CAM_STS_VCNT_INT_MSK            (((1U << CAM_STS_VCNT_INT_LEN) - 1) << CAM_STS_VCNT_INT_POS)
+#define CAM_STS_VCNT_INT_UMSK           (~(((1U << CAM_STS_VCNT_INT_LEN) - 1) << CAM_STS_VCNT_INT_POS))
+#define CAM_AHB_IDLE_0                  CAM_AHB_IDLE_0
+#define CAM_AHB_IDLE_0_POS              (16U)
+#define CAM_AHB_IDLE_0_LEN              (1U)
+#define CAM_AHB_IDLE_0_MSK              (((1U << CAM_AHB_IDLE_0_LEN) - 1) << CAM_AHB_IDLE_0_POS)
+#define CAM_AHB_IDLE_0_UMSK             (~(((1U << CAM_AHB_IDLE_0_LEN) - 1) << CAM_AHB_IDLE_0_POS))
+#define CAM_AHB_IDLE_1                  CAM_AHB_IDLE_1
+#define CAM_AHB_IDLE_1_POS              (17U)
+#define CAM_AHB_IDLE_1_LEN              (1U)
+#define CAM_AHB_IDLE_1_MSK              (((1U << CAM_AHB_IDLE_1_LEN) - 1) << CAM_AHB_IDLE_1_POS)
+#define CAM_AHB_IDLE_1_UMSK             (~(((1U << CAM_AHB_IDLE_1_LEN) - 1) << CAM_AHB_IDLE_1_POS))
+#define CAM_ST_DVP_IDLE                 CAM_ST_DVP_IDLE
+#define CAM_ST_DVP_IDLE_POS             (19U)
+#define CAM_ST_DVP_IDLE_LEN             (1U)
+#define CAM_ST_DVP_IDLE_MSK             (((1U << CAM_ST_DVP_IDLE_LEN) - 1) << CAM_ST_DVP_IDLE_POS)
+#define CAM_ST_DVP_IDLE_UMSK            (~(((1U << CAM_ST_DVP_IDLE_LEN) - 1) << CAM_ST_DVP_IDLE_POS))
+#define CAM_FRAME_VALID_CNT_0           CAM_FRAME_VALID_CNT_0
+#define CAM_FRAME_VALID_CNT_0_POS       (20U)
+#define CAM_FRAME_VALID_CNT_0_LEN       (4U)
+#define CAM_FRAME_VALID_CNT_0_MSK       (((1U << CAM_FRAME_VALID_CNT_0_LEN) - 1) << CAM_FRAME_VALID_CNT_0_POS)
+#define CAM_FRAME_VALID_CNT_0_UMSK      (~(((1U << CAM_FRAME_VALID_CNT_0_LEN) - 1) << CAM_FRAME_VALID_CNT_0_POS))
+#define CAM_FRAME_VALID_CNT_1           CAM_FRAME_VALID_CNT_1
+#define CAM_FRAME_VALID_CNT_1_POS       (24U)
+#define CAM_FRAME_VALID_CNT_1_LEN       (4U)
+#define CAM_FRAME_VALID_CNT_1_MSK       (((1U << CAM_FRAME_VALID_CNT_1_LEN) - 1) << CAM_FRAME_VALID_CNT_1_POS)
+#define CAM_FRAME_VALID_CNT_1_UMSK      (~(((1U << CAM_FRAME_VALID_CNT_1_LEN) - 1) << CAM_FRAME_VALID_CNT_1_POS))
+#define CAM_ST_BUS_IDLE                 CAM_ST_BUS_IDLE
+#define CAM_ST_BUS_IDLE_POS             (28U)
+#define CAM_ST_BUS_IDLE_LEN             (1U)
+#define CAM_ST_BUS_IDLE_MSK             (((1U << CAM_ST_BUS_IDLE_LEN) - 1) << CAM_ST_BUS_IDLE_POS)
+#define CAM_ST_BUS_IDLE_UMSK            (~(((1U << CAM_ST_BUS_IDLE_LEN) - 1) << CAM_ST_BUS_IDLE_POS))
+#define CAM_ST_BUS_FUNC                 CAM_ST_BUS_FUNC
+#define CAM_ST_BUS_FUNC_POS             (29U)
+#define CAM_ST_BUS_FUNC_LEN             (1U)
+#define CAM_ST_BUS_FUNC_MSK             (((1U << CAM_ST_BUS_FUNC_LEN) - 1) << CAM_ST_BUS_FUNC_POS)
+#define CAM_ST_BUS_FUNC_UMSK            (~(((1U << CAM_ST_BUS_FUNC_LEN) - 1) << CAM_ST_BUS_FUNC_POS))
+#define CAM_ST_BUS_WAIT                 CAM_ST_BUS_WAIT
+#define CAM_ST_BUS_WAIT_POS             (30U)
+#define CAM_ST_BUS_WAIT_LEN             (1U)
+#define CAM_ST_BUS_WAIT_MSK             (((1U << CAM_ST_BUS_WAIT_LEN) - 1) << CAM_ST_BUS_WAIT_POS)
+#define CAM_ST_BUS_WAIT_UMSK            (~(((1U << CAM_ST_BUS_WAIT_LEN) - 1) << CAM_ST_BUS_WAIT_POS))
+#define CAM_ST_BUS_FLSH                 CAM_ST_BUS_FLSH
+#define CAM_ST_BUS_FLSH_POS             (31U)
+#define CAM_ST_BUS_FLSH_LEN             (1U)
+#define CAM_ST_BUS_FLSH_MSK             (((1U << CAM_ST_BUS_FLSH_LEN) - 1) << CAM_ST_BUS_FLSH_POS)
+#define CAM_ST_BUS_FLSH_UMSK            (~(((1U << CAM_ST_BUS_FLSH_LEN) - 1) << CAM_ST_BUS_FLSH_POS))
+
+/* 0x20 : dvp_frame_fifo_pop */
+#define CAM_DVP_FRAME_FIFO_POP_OFFSET (0x20)
+#define CAM_RFIFO_POP_0               CAM_RFIFO_POP_0
+#define CAM_RFIFO_POP_0_POS           (0U)
+#define CAM_RFIFO_POP_0_LEN           (1U)
+#define CAM_RFIFO_POP_0_MSK           (((1U << CAM_RFIFO_POP_0_LEN) - 1) << CAM_RFIFO_POP_0_POS)
+#define CAM_RFIFO_POP_0_UMSK          (~(((1U << CAM_RFIFO_POP_0_LEN) - 1) << CAM_RFIFO_POP_0_POS))
+#define CAM_RFIFO_POP_1               CAM_RFIFO_POP_1
+#define CAM_RFIFO_POP_1_POS           (1U)
+#define CAM_RFIFO_POP_1_LEN           (1U)
+#define CAM_RFIFO_POP_1_MSK           (((1U << CAM_RFIFO_POP_1_LEN) - 1) << CAM_RFIFO_POP_1_POS)
+#define CAM_RFIFO_POP_1_UMSK          (~(((1U << CAM_RFIFO_POP_1_LEN) - 1) << CAM_RFIFO_POP_1_POS))
+#define CAM_REG_INT_NORMAL_CLR_0      CAM_REG_INT_NORMAL_CLR_0
+#define CAM_REG_INT_NORMAL_CLR_0_POS  (4U)
+#define CAM_REG_INT_NORMAL_CLR_0_LEN  (1U)
+#define CAM_REG_INT_NORMAL_CLR_0_MSK  (((1U << CAM_REG_INT_NORMAL_CLR_0_LEN) - 1) << CAM_REG_INT_NORMAL_CLR_0_POS)
+#define CAM_REG_INT_NORMAL_CLR_0_UMSK (~(((1U << CAM_REG_INT_NORMAL_CLR_0_LEN) - 1) << CAM_REG_INT_NORMAL_CLR_0_POS))
+#define CAM_REG_INT_MEM_CLR_0         CAM_REG_INT_MEM_CLR_0
+#define CAM_REG_INT_MEM_CLR_0_POS     (5U)
+#define CAM_REG_INT_MEM_CLR_0_LEN     (1U)
+#define CAM_REG_INT_MEM_CLR_0_MSK     (((1U << CAM_REG_INT_MEM_CLR_0_LEN) - 1) << CAM_REG_INT_MEM_CLR_0_POS)
+#define CAM_REG_INT_MEM_CLR_0_UMSK    (~(((1U << CAM_REG_INT_MEM_CLR_0_LEN) - 1) << CAM_REG_INT_MEM_CLR_0_POS))
+#define CAM_REG_INT_FRAME_CLR_0       CAM_REG_INT_FRAME_CLR_0
+#define CAM_REG_INT_FRAME_CLR_0_POS   (6U)
+#define CAM_REG_INT_FRAME_CLR_0_LEN   (1U)
+#define CAM_REG_INT_FRAME_CLR_0_MSK   (((1U << CAM_REG_INT_FRAME_CLR_0_LEN) - 1) << CAM_REG_INT_FRAME_CLR_0_POS)
+#define CAM_REG_INT_FRAME_CLR_0_UMSK  (~(((1U << CAM_REG_INT_FRAME_CLR_0_LEN) - 1) << CAM_REG_INT_FRAME_CLR_0_POS))
+#define CAM_REG_INT_FIFO_CLR_0        CAM_REG_INT_FIFO_CLR_0
+#define CAM_REG_INT_FIFO_CLR_0_POS    (7U)
+#define CAM_REG_INT_FIFO_CLR_0_LEN    (1U)
+#define CAM_REG_INT_FIFO_CLR_0_MSK    (((1U << CAM_REG_INT_FIFO_CLR_0_LEN) - 1) << CAM_REG_INT_FIFO_CLR_0_POS)
+#define CAM_REG_INT_FIFO_CLR_0_UMSK   (~(((1U << CAM_REG_INT_FIFO_CLR_0_LEN) - 1) << CAM_REG_INT_FIFO_CLR_0_POS))
+#define CAM_REG_INT_HCNT_CLR_0        CAM_REG_INT_HCNT_CLR_0
+#define CAM_REG_INT_HCNT_CLR_0_POS    (8U)
+#define CAM_REG_INT_HCNT_CLR_0_LEN    (1U)
+#define CAM_REG_INT_HCNT_CLR_0_MSK    (((1U << CAM_REG_INT_HCNT_CLR_0_LEN) - 1) << CAM_REG_INT_HCNT_CLR_0_POS)
+#define CAM_REG_INT_HCNT_CLR_0_UMSK   (~(((1U << CAM_REG_INT_HCNT_CLR_0_LEN) - 1) << CAM_REG_INT_HCNT_CLR_0_POS))
+#define CAM_REG_INT_VCNT_CLR_0        CAM_REG_INT_VCNT_CLR_0
+#define CAM_REG_INT_VCNT_CLR_0_POS    (9U)
+#define CAM_REG_INT_VCNT_CLR_0_LEN    (1U)
+#define CAM_REG_INT_VCNT_CLR_0_MSK    (((1U << CAM_REG_INT_VCNT_CLR_0_LEN) - 1) << CAM_REG_INT_VCNT_CLR_0_POS)
+#define CAM_REG_INT_VCNT_CLR_0_UMSK   (~(((1U << CAM_REG_INT_VCNT_CLR_0_LEN) - 1) << CAM_REG_INT_VCNT_CLR_0_POS))
+#define CAM_REG_INT_NORMAL_CLR_1      CAM_REG_INT_NORMAL_CLR_1
+#define CAM_REG_INT_NORMAL_CLR_1_POS  (16U)
+#define CAM_REG_INT_NORMAL_CLR_1_LEN  (1U)
+#define CAM_REG_INT_NORMAL_CLR_1_MSK  (((1U << CAM_REG_INT_NORMAL_CLR_1_LEN) - 1) << CAM_REG_INT_NORMAL_CLR_1_POS)
+#define CAM_REG_INT_NORMAL_CLR_1_UMSK (~(((1U << CAM_REG_INT_NORMAL_CLR_1_LEN) - 1) << CAM_REG_INT_NORMAL_CLR_1_POS))
+#define CAM_REG_INT_MEM_CLR_1         CAM_REG_INT_MEM_CLR_1
+#define CAM_REG_INT_MEM_CLR_1_POS     (17U)
+#define CAM_REG_INT_MEM_CLR_1_LEN     (1U)
+#define CAM_REG_INT_MEM_CLR_1_MSK     (((1U << CAM_REG_INT_MEM_CLR_1_LEN) - 1) << CAM_REG_INT_MEM_CLR_1_POS)
+#define CAM_REG_INT_MEM_CLR_1_UMSK    (~(((1U << CAM_REG_INT_MEM_CLR_1_LEN) - 1) << CAM_REG_INT_MEM_CLR_1_POS))
+#define CAM_REG_INT_FRAME_CLR_1       CAM_REG_INT_FRAME_CLR_1
+#define CAM_REG_INT_FRAME_CLR_1_POS   (18U)
+#define CAM_REG_INT_FRAME_CLR_1_LEN   (1U)
+#define CAM_REG_INT_FRAME_CLR_1_MSK   (((1U << CAM_REG_INT_FRAME_CLR_1_LEN) - 1) << CAM_REG_INT_FRAME_CLR_1_POS)
+#define CAM_REG_INT_FRAME_CLR_1_UMSK  (~(((1U << CAM_REG_INT_FRAME_CLR_1_LEN) - 1) << CAM_REG_INT_FRAME_CLR_1_POS))
+#define CAM_REG_INT_FIFO_CLR_1        CAM_REG_INT_FIFO_CLR_1
+#define CAM_REG_INT_FIFO_CLR_1_POS    (19U)
+#define CAM_REG_INT_FIFO_CLR_1_LEN    (1U)
+#define CAM_REG_INT_FIFO_CLR_1_MSK    (((1U << CAM_REG_INT_FIFO_CLR_1_LEN) - 1) << CAM_REG_INT_FIFO_CLR_1_POS)
+#define CAM_REG_INT_FIFO_CLR_1_UMSK   (~(((1U << CAM_REG_INT_FIFO_CLR_1_LEN) - 1) << CAM_REG_INT_FIFO_CLR_1_POS))
+
+/* 0x24 : snsr_control */
+#define CAM_SNSR_CONTROL_OFFSET (0x24)
+#define CAM_REG_CAM_RST         CAM_REG_CAM_RST
+#define CAM_REG_CAM_RST_POS     (0U)
+#define CAM_REG_CAM_RST_LEN     (1U)
+#define CAM_REG_CAM_RST_MSK     (((1U << CAM_REG_CAM_RST_LEN) - 1) << CAM_REG_CAM_RST_POS)
+#define CAM_REG_CAM_RST_UMSK    (~(((1U << CAM_REG_CAM_RST_LEN) - 1) << CAM_REG_CAM_RST_POS))
+#define CAM_REG_CAM_PWDN        CAM_REG_CAM_PWDN
+#define CAM_REG_CAM_PWDN_POS    (1U)
+#define CAM_REG_CAM_PWDN_LEN    (1U)
+#define CAM_REG_CAM_PWDN_MSK    (((1U << CAM_REG_CAM_PWDN_LEN) - 1) << CAM_REG_CAM_PWDN_POS)
+#define CAM_REG_CAM_PWDN_UMSK   (~(((1U << CAM_REG_CAM_PWDN_LEN) - 1) << CAM_REG_CAM_PWDN_POS))
+
+/* 0x28 : int_control */
+#define CAM_INT_CONTROL_OFFSET          (0x28)
+#define CAM_REG_INT_NORMAL_0_EN         CAM_REG_INT_NORMAL_0_EN
+#define CAM_REG_INT_NORMAL_0_EN_POS     (0U)
+#define CAM_REG_INT_NORMAL_0_EN_LEN     (1U)
+#define CAM_REG_INT_NORMAL_0_EN_MSK     (((1U << CAM_REG_INT_NORMAL_0_EN_LEN) - 1) << CAM_REG_INT_NORMAL_0_EN_POS)
+#define CAM_REG_INT_NORMAL_0_EN_UMSK    (~(((1U << CAM_REG_INT_NORMAL_0_EN_LEN) - 1) << CAM_REG_INT_NORMAL_0_EN_POS))
+#define CAM_REG_INT_NORMAL_1_EN         CAM_REG_INT_NORMAL_1_EN
+#define CAM_REG_INT_NORMAL_1_EN_POS     (1U)
+#define CAM_REG_INT_NORMAL_1_EN_LEN     (1U)
+#define CAM_REG_INT_NORMAL_1_EN_MSK     (((1U << CAM_REG_INT_NORMAL_1_EN_LEN) - 1) << CAM_REG_INT_NORMAL_1_EN_POS)
+#define CAM_REG_INT_NORMAL_1_EN_UMSK    (~(((1U << CAM_REG_INT_NORMAL_1_EN_LEN) - 1) << CAM_REG_INT_NORMAL_1_EN_POS))
+#define CAM_REG_INT_MEM_EN              CAM_REG_INT_MEM_EN
+#define CAM_REG_INT_MEM_EN_POS          (2U)
+#define CAM_REG_INT_MEM_EN_LEN          (1U)
+#define CAM_REG_INT_MEM_EN_MSK          (((1U << CAM_REG_INT_MEM_EN_LEN) - 1) << CAM_REG_INT_MEM_EN_POS)
+#define CAM_REG_INT_MEM_EN_UMSK         (~(((1U << CAM_REG_INT_MEM_EN_LEN) - 1) << CAM_REG_INT_MEM_EN_POS))
+#define CAM_REG_INT_FRAME_EN            CAM_REG_INT_FRAME_EN
+#define CAM_REG_INT_FRAME_EN_POS        (3U)
+#define CAM_REG_INT_FRAME_EN_LEN        (1U)
+#define CAM_REG_INT_FRAME_EN_MSK        (((1U << CAM_REG_INT_FRAME_EN_LEN) - 1) << CAM_REG_INT_FRAME_EN_POS)
+#define CAM_REG_INT_FRAME_EN_UMSK       (~(((1U << CAM_REG_INT_FRAME_EN_LEN) - 1) << CAM_REG_INT_FRAME_EN_POS))
+#define CAM_REG_INT_FIFO_EN             CAM_REG_INT_FIFO_EN
+#define CAM_REG_INT_FIFO_EN_POS         (4U)
+#define CAM_REG_INT_FIFO_EN_LEN         (1U)
+#define CAM_REG_INT_FIFO_EN_MSK         (((1U << CAM_REG_INT_FIFO_EN_LEN) - 1) << CAM_REG_INT_FIFO_EN_POS)
+#define CAM_REG_INT_FIFO_EN_UMSK        (~(((1U << CAM_REG_INT_FIFO_EN_LEN) - 1) << CAM_REG_INT_FIFO_EN_POS))
+#define CAM_REG_INT_HCNT_EN             CAM_REG_INT_HCNT_EN
+#define CAM_REG_INT_HCNT_EN_POS         (5U)
+#define CAM_REG_INT_HCNT_EN_LEN         (1U)
+#define CAM_REG_INT_HCNT_EN_MSK         (((1U << CAM_REG_INT_HCNT_EN_LEN) - 1) << CAM_REG_INT_HCNT_EN_POS)
+#define CAM_REG_INT_HCNT_EN_UMSK        (~(((1U << CAM_REG_INT_HCNT_EN_LEN) - 1) << CAM_REG_INT_HCNT_EN_POS))
+#define CAM_REG_INT_VCNT_EN             CAM_REG_INT_VCNT_EN
+#define CAM_REG_INT_VCNT_EN_POS         (6U)
+#define CAM_REG_INT_VCNT_EN_LEN         (1U)
+#define CAM_REG_INT_VCNT_EN_MSK         (((1U << CAM_REG_INT_VCNT_EN_LEN) - 1) << CAM_REG_INT_VCNT_EN_POS)
+#define CAM_REG_INT_VCNT_EN_UMSK        (~(((1U << CAM_REG_INT_VCNT_EN_LEN) - 1) << CAM_REG_INT_VCNT_EN_POS))
+#define CAM_REG_FRAME_CNT_TRGR_INT      CAM_REG_FRAME_CNT_TRGR_INT
+#define CAM_REG_FRAME_CNT_TRGR_INT_POS  (28U)
+#define CAM_REG_FRAME_CNT_TRGR_INT_LEN  (4U)
+#define CAM_REG_FRAME_CNT_TRGR_INT_MSK  (((1U << CAM_REG_FRAME_CNT_TRGR_INT_LEN) - 1) << CAM_REG_FRAME_CNT_TRGR_INT_POS)
+#define CAM_REG_FRAME_CNT_TRGR_INT_UMSK (~(((1U << CAM_REG_FRAME_CNT_TRGR_INT_LEN) - 1) << CAM_REG_FRAME_CNT_TRGR_INT_POS))
+
+/* 0x30 : hsync_control */
+#define CAM_HSYNC_CONTROL_OFFSET     (0x30)
+#define CAM_REG_HSYNC_ACT_END        CAM_REG_HSYNC_ACT_END
+#define CAM_REG_HSYNC_ACT_END_POS    (0U)
+#define CAM_REG_HSYNC_ACT_END_LEN    (16U)
+#define CAM_REG_HSYNC_ACT_END_MSK    (((1U << CAM_REG_HSYNC_ACT_END_LEN) - 1) << CAM_REG_HSYNC_ACT_END_POS)
+#define CAM_REG_HSYNC_ACT_END_UMSK   (~(((1U << CAM_REG_HSYNC_ACT_END_LEN) - 1) << CAM_REG_HSYNC_ACT_END_POS))
+#define CAM_REG_HSYNC_ACT_START      CAM_REG_HSYNC_ACT_START
+#define CAM_REG_HSYNC_ACT_START_POS  (16U)
+#define CAM_REG_HSYNC_ACT_START_LEN  (16U)
+#define CAM_REG_HSYNC_ACT_START_MSK  (((1U << CAM_REG_HSYNC_ACT_START_LEN) - 1) << CAM_REG_HSYNC_ACT_START_POS)
+#define CAM_REG_HSYNC_ACT_START_UMSK (~(((1U << CAM_REG_HSYNC_ACT_START_LEN) - 1) << CAM_REG_HSYNC_ACT_START_POS))
+
+/* 0x34 : vsync_control */
+#define CAM_VSYNC_CONTROL_OFFSET     (0x34)
+#define CAM_REG_VSYNC_ACT_END        CAM_REG_VSYNC_ACT_END
+#define CAM_REG_VSYNC_ACT_END_POS    (0U)
+#define CAM_REG_VSYNC_ACT_END_LEN    (16U)
+#define CAM_REG_VSYNC_ACT_END_MSK    (((1U << CAM_REG_VSYNC_ACT_END_LEN) - 1) << CAM_REG_VSYNC_ACT_END_POS)
+#define CAM_REG_VSYNC_ACT_END_UMSK   (~(((1U << CAM_REG_VSYNC_ACT_END_LEN) - 1) << CAM_REG_VSYNC_ACT_END_POS))
+#define CAM_REG_VSYNC_ACT_START      CAM_REG_VSYNC_ACT_START
+#define CAM_REG_VSYNC_ACT_START_POS  (16U)
+#define CAM_REG_VSYNC_ACT_START_LEN  (16U)
+#define CAM_REG_VSYNC_ACT_START_MSK  (((1U << CAM_REG_VSYNC_ACT_START_LEN) - 1) << CAM_REG_VSYNC_ACT_START_POS)
+#define CAM_REG_VSYNC_ACT_START_UMSK (~(((1U << CAM_REG_VSYNC_ACT_START_LEN) - 1) << CAM_REG_VSYNC_ACT_START_POS))
+
+/* 0x38 : frame_size_control */
+#define CAM_FRAME_SIZE_CONTROL_OFFSET (0x38)
+#define CAM_REG_TOTAL_HCNT            CAM_REG_TOTAL_HCNT
+#define CAM_REG_TOTAL_HCNT_POS        (0U)
+#define CAM_REG_TOTAL_HCNT_LEN        (16U)
+#define CAM_REG_TOTAL_HCNT_MSK        (((1U << CAM_REG_TOTAL_HCNT_LEN) - 1) << CAM_REG_TOTAL_HCNT_POS)
+#define CAM_REG_TOTAL_HCNT_UMSK       (~(((1U << CAM_REG_TOTAL_HCNT_LEN) - 1) << CAM_REG_TOTAL_HCNT_POS))
+#define CAM_REG_TOTAL_VCNT            CAM_REG_TOTAL_VCNT
+#define CAM_REG_TOTAL_VCNT_POS        (16U)
+#define CAM_REG_TOTAL_VCNT_LEN        (16U)
+#define CAM_REG_TOTAL_VCNT_MSK        (((1U << CAM_REG_TOTAL_VCNT_LEN) - 1) << CAM_REG_TOTAL_VCNT_POS)
+#define CAM_REG_TOTAL_VCNT_UMSK       (~(((1U << CAM_REG_TOTAL_VCNT_LEN) - 1) << CAM_REG_TOTAL_VCNT_POS))
+
+/* 0x40 : frame_start_addr0_0 */
+#define CAM_FRAME_START_ADDR0_0_OFFSET (0x40)
+#define CAM_FRAME_START_ADDR_0_0       CAM_FRAME_START_ADDR_0_0
+#define CAM_FRAME_START_ADDR_0_0_POS   (0U)
+#define CAM_FRAME_START_ADDR_0_0_LEN   (32U)
+#define CAM_FRAME_START_ADDR_0_0_MSK   (((1U << CAM_FRAME_START_ADDR_0_0_LEN) - 1) << CAM_FRAME_START_ADDR_0_0_POS)
+#define CAM_FRAME_START_ADDR_0_0_UMSK  (~(((1U << CAM_FRAME_START_ADDR_0_0_LEN) - 1) << CAM_FRAME_START_ADDR_0_0_POS))
+
+/* 0x44 : frame_byte_cnt0_0 */
+#define CAM_FRAME_BYTE_CNT0_0_OFFSET (0x44)
+#define CAM_FRAME_BYTE_CNT_0_0       CAM_FRAME_BYTE_CNT_0_0
+#define CAM_FRAME_BYTE_CNT_0_0_POS   (0U)
+#define CAM_FRAME_BYTE_CNT_0_0_LEN   (32U)
+#define CAM_FRAME_BYTE_CNT_0_0_MSK   (((1U << CAM_FRAME_BYTE_CNT_0_0_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_0_POS)
+#define CAM_FRAME_BYTE_CNT_0_0_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_0_0_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_0_POS))
+
+/* 0x48 : frame_start_addr0_1 */
+#define CAM_FRAME_START_ADDR0_1_OFFSET (0x48)
+#define CAM_FRAME_START_ADDR_0_1       CAM_FRAME_START_ADDR_0_1
+#define CAM_FRAME_START_ADDR_0_1_POS   (0U)
+#define CAM_FRAME_START_ADDR_0_1_LEN   (32U)
+#define CAM_FRAME_START_ADDR_0_1_MSK   (((1U << CAM_FRAME_START_ADDR_0_1_LEN) - 1) << CAM_FRAME_START_ADDR_0_1_POS)
+#define CAM_FRAME_START_ADDR_0_1_UMSK  (~(((1U << CAM_FRAME_START_ADDR_0_1_LEN) - 1) << CAM_FRAME_START_ADDR_0_1_POS))
+
+/* 0x4C : frame_byte_cnt0_1 */
+#define CAM_FRAME_BYTE_CNT0_1_OFFSET (0x4C)
+#define CAM_FRAME_BYTE_CNT_0_1       CAM_FRAME_BYTE_CNT_0_1
+#define CAM_FRAME_BYTE_CNT_0_1_POS   (0U)
+#define CAM_FRAME_BYTE_CNT_0_1_LEN   (32U)
+#define CAM_FRAME_BYTE_CNT_0_1_MSK   (((1U << CAM_FRAME_BYTE_CNT_0_1_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_1_POS)
+#define CAM_FRAME_BYTE_CNT_0_1_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_0_1_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_1_POS))
+
+/* 0x50 : frame_start_addr0_2 */
+#define CAM_FRAME_START_ADDR0_2_OFFSET (0x50)
+#define CAM_FRAME_START_ADDR_0_2       CAM_FRAME_START_ADDR_0_2
+#define CAM_FRAME_START_ADDR_0_2_POS   (0U)
+#define CAM_FRAME_START_ADDR_0_2_LEN   (32U)
+#define CAM_FRAME_START_ADDR_0_2_MSK   (((1U << CAM_FRAME_START_ADDR_0_2_LEN) - 1) << CAM_FRAME_START_ADDR_0_2_POS)
+#define CAM_FRAME_START_ADDR_0_2_UMSK  (~(((1U << CAM_FRAME_START_ADDR_0_2_LEN) - 1) << CAM_FRAME_START_ADDR_0_2_POS))
+
+/* 0x54 : frame_byte_cnt0_2 */
+#define CAM_FRAME_BYTE_CNT0_2_OFFSET (0x54)
+#define CAM_FRAME_BYTE_CNT_0_2       CAM_FRAME_BYTE_CNT_0_2
+#define CAM_FRAME_BYTE_CNT_0_2_POS   (0U)
+#define CAM_FRAME_BYTE_CNT_0_2_LEN   (32U)
+#define CAM_FRAME_BYTE_CNT_0_2_MSK   (((1U << CAM_FRAME_BYTE_CNT_0_2_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_2_POS)
+#define CAM_FRAME_BYTE_CNT_0_2_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_0_2_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_2_POS))
+
+/* 0x58 : frame_start_addr0_3 */
+#define CAM_FRAME_START_ADDR0_3_OFFSET (0x58)
+#define CAM_FRAME_START_ADDR_0_3       CAM_FRAME_START_ADDR_0_3
+#define CAM_FRAME_START_ADDR_0_3_POS   (0U)
+#define CAM_FRAME_START_ADDR_0_3_LEN   (32U)
+#define CAM_FRAME_START_ADDR_0_3_MSK   (((1U << CAM_FRAME_START_ADDR_0_3_LEN) - 1) << CAM_FRAME_START_ADDR_0_3_POS)
+#define CAM_FRAME_START_ADDR_0_3_UMSK  (~(((1U << CAM_FRAME_START_ADDR_0_3_LEN) - 1) << CAM_FRAME_START_ADDR_0_3_POS))
+
+/* 0x5C : frame_byte_cnt0_3 */
+#define CAM_FRAME_BYTE_CNT0_3_OFFSET (0x5C)
+#define CAM_FRAME_BYTE_CNT_0_3       CAM_FRAME_BYTE_CNT_0_3
+#define CAM_FRAME_BYTE_CNT_0_3_POS   (0U)
+#define CAM_FRAME_BYTE_CNT_0_3_LEN   (32U)
+#define CAM_FRAME_BYTE_CNT_0_3_MSK   (((1U << CAM_FRAME_BYTE_CNT_0_3_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_3_POS)
+#define CAM_FRAME_BYTE_CNT_0_3_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_0_3_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_3_POS))
+
+/* 0x60 : frame_start_addr0_4 */
+#define CAM_FRAME_START_ADDR0_4_OFFSET (0x60)
+#define CAM_FRAME_START_ADDR_0_4       CAM_FRAME_START_ADDR_0_4
+#define CAM_FRAME_START_ADDR_0_4_POS   (0U)
+#define CAM_FRAME_START_ADDR_0_4_LEN   (32U)
+#define CAM_FRAME_START_ADDR_0_4_MSK   (((1U << CAM_FRAME_START_ADDR_0_4_LEN) - 1) << CAM_FRAME_START_ADDR_0_4_POS)
+#define CAM_FRAME_START_ADDR_0_4_UMSK  (~(((1U << CAM_FRAME_START_ADDR_0_4_LEN) - 1) << CAM_FRAME_START_ADDR_0_4_POS))
+
+/* 0x64 : frame_byte_cnt0_4 */
+#define CAM_FRAME_BYTE_CNT0_4_OFFSET (0x64)
+#define CAM_FRAME_BYTE_CNT_0_4       CAM_FRAME_BYTE_CNT_0_4
+#define CAM_FRAME_BYTE_CNT_0_4_POS   (0U)
+#define CAM_FRAME_BYTE_CNT_0_4_LEN   (32U)
+#define CAM_FRAME_BYTE_CNT_0_4_MSK   (((1U << CAM_FRAME_BYTE_CNT_0_4_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_4_POS)
+#define CAM_FRAME_BYTE_CNT_0_4_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_0_4_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_4_POS))
+
+/* 0x68 : frame_start_addr0_5 */
+#define CAM_FRAME_START_ADDR0_5_OFFSET (0x68)
+#define CAM_FRAME_START_ADDR_0_5       CAM_FRAME_START_ADDR_0_5
+#define CAM_FRAME_START_ADDR_0_5_POS   (0U)
+#define CAM_FRAME_START_ADDR_0_5_LEN   (32U)
+#define CAM_FRAME_START_ADDR_0_5_MSK   (((1U << CAM_FRAME_START_ADDR_0_5_LEN) - 1) << CAM_FRAME_START_ADDR_0_5_POS)
+#define CAM_FRAME_START_ADDR_0_5_UMSK  (~(((1U << CAM_FRAME_START_ADDR_0_5_LEN) - 1) << CAM_FRAME_START_ADDR_0_5_POS))
+
+/* 0x6C : frame_byte_cnt0_5 */
+#define CAM_FRAME_BYTE_CNT0_5_OFFSET (0x6C)
+#define CAM_FRAME_BYTE_CNT_0_5       CAM_FRAME_BYTE_CNT_0_5
+#define CAM_FRAME_BYTE_CNT_0_5_POS   (0U)
+#define CAM_FRAME_BYTE_CNT_0_5_LEN   (32U)
+#define CAM_FRAME_BYTE_CNT_0_5_MSK   (((1U << CAM_FRAME_BYTE_CNT_0_5_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_5_POS)
+#define CAM_FRAME_BYTE_CNT_0_5_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_0_5_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_5_POS))
+
+/* 0x70 : frame_start_addr0_6 */
+#define CAM_FRAME_START_ADDR0_6_OFFSET (0x70)
+#define CAM_FRAME_START_ADDR_0_6       CAM_FRAME_START_ADDR_0_6
+#define CAM_FRAME_START_ADDR_0_6_POS   (0U)
+#define CAM_FRAME_START_ADDR_0_6_LEN   (32U)
+#define CAM_FRAME_START_ADDR_0_6_MSK   (((1U << CAM_FRAME_START_ADDR_0_6_LEN) - 1) << CAM_FRAME_START_ADDR_0_6_POS)
+#define CAM_FRAME_START_ADDR_0_6_UMSK  (~(((1U << CAM_FRAME_START_ADDR_0_6_LEN) - 1) << CAM_FRAME_START_ADDR_0_6_POS))
+
+/* 0x74 : frame_byte_cnt0_6 */
+#define CAM_FRAME_BYTE_CNT0_6_OFFSET (0x74)
+#define CAM_FRAME_BYTE_CNT_0_6       CAM_FRAME_BYTE_CNT_0_6
+#define CAM_FRAME_BYTE_CNT_0_6_POS   (0U)
+#define CAM_FRAME_BYTE_CNT_0_6_LEN   (32U)
+#define CAM_FRAME_BYTE_CNT_0_6_MSK   (((1U << CAM_FRAME_BYTE_CNT_0_6_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_6_POS)
+#define CAM_FRAME_BYTE_CNT_0_6_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_0_6_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_6_POS))
+
+/* 0x78 : frame_start_addr0_7 */
+#define CAM_FRAME_START_ADDR0_7_OFFSET (0x78)
+#define CAM_FRAME_START_ADDR_0_7       CAM_FRAME_START_ADDR_0_7
+#define CAM_FRAME_START_ADDR_0_7_POS   (0U)
+#define CAM_FRAME_START_ADDR_0_7_LEN   (32U)
+#define CAM_FRAME_START_ADDR_0_7_MSK   (((1U << CAM_FRAME_START_ADDR_0_7_LEN) - 1) << CAM_FRAME_START_ADDR_0_7_POS)
+#define CAM_FRAME_START_ADDR_0_7_UMSK  (~(((1U << CAM_FRAME_START_ADDR_0_7_LEN) - 1) << CAM_FRAME_START_ADDR_0_7_POS))
+
+/* 0x7C : frame_byte_cnt0_7 */
+#define CAM_FRAME_BYTE_CNT0_7_OFFSET (0x7C)
+#define CAM_FRAME_BYTE_CNT_0_7       CAM_FRAME_BYTE_CNT_0_7
+#define CAM_FRAME_BYTE_CNT_0_7_POS   (0U)
+#define CAM_FRAME_BYTE_CNT_0_7_LEN   (32U)
+#define CAM_FRAME_BYTE_CNT_0_7_MSK   (((1U << CAM_FRAME_BYTE_CNT_0_7_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_7_POS)
+#define CAM_FRAME_BYTE_CNT_0_7_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_0_7_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_7_POS))
+
+/* 0x80 : frame_start_addr1_0 */
+#define CAM_FRAME_START_ADDR1_0_OFFSET (0x80)
+#define CAM_FRAME_START_ADDR_1_0       CAM_FRAME_START_ADDR_1_0
+#define CAM_FRAME_START_ADDR_1_0_POS   (0U)
+#define CAM_FRAME_START_ADDR_1_0_LEN   (32U)
+#define CAM_FRAME_START_ADDR_1_0_MSK   (((1U << CAM_FRAME_START_ADDR_1_0_LEN) - 1) << CAM_FRAME_START_ADDR_1_0_POS)
+#define CAM_FRAME_START_ADDR_1_0_UMSK  (~(((1U << CAM_FRAME_START_ADDR_1_0_LEN) - 1) << CAM_FRAME_START_ADDR_1_0_POS))
+
+/* 0x84 : frame_byte_cnt1_0 */
+#define CAM_FRAME_BYTE_CNT1_0_OFFSET (0x84)
+#define CAM_FRAME_BYTE_CNT_1_0       CAM_FRAME_BYTE_CNT_1_0
+#define CAM_FRAME_BYTE_CNT_1_0_POS   (0U)
+#define CAM_FRAME_BYTE_CNT_1_0_LEN   (32U)
+#define CAM_FRAME_BYTE_CNT_1_0_MSK   (((1U << CAM_FRAME_BYTE_CNT_1_0_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_0_POS)
+#define CAM_FRAME_BYTE_CNT_1_0_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_1_0_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_0_POS))
+
+/* 0x88 : frame_start_addr1_1 */
+#define CAM_FRAME_START_ADDR1_1_OFFSET (0x88)
+#define CAM_FRAME_START_ADDR_1_1       CAM_FRAME_START_ADDR_1_1
+#define CAM_FRAME_START_ADDR_1_1_POS   (0U)
+#define CAM_FRAME_START_ADDR_1_1_LEN   (32U)
+#define CAM_FRAME_START_ADDR_1_1_MSK   (((1U << CAM_FRAME_START_ADDR_1_1_LEN) - 1) << CAM_FRAME_START_ADDR_1_1_POS)
+#define CAM_FRAME_START_ADDR_1_1_UMSK  (~(((1U << CAM_FRAME_START_ADDR_1_1_LEN) - 1) << CAM_FRAME_START_ADDR_1_1_POS))
+
+/* 0x8C : frame_byte_cnt1_1 */
+#define CAM_FRAME_BYTE_CNT1_1_OFFSET (0x8C)
+#define CAM_FRAME_BYTE_CNT_1_1       CAM_FRAME_BYTE_CNT_1_1
+#define CAM_FRAME_BYTE_CNT_1_1_POS   (0U)
+#define CAM_FRAME_BYTE_CNT_1_1_LEN   (32U)
+#define CAM_FRAME_BYTE_CNT_1_1_MSK   (((1U << CAM_FRAME_BYTE_CNT_1_1_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_1_POS)
+#define CAM_FRAME_BYTE_CNT_1_1_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_1_1_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_1_POS))
+
+/* 0x90 : frame_start_addr1_2 */
+#define CAM_FRAME_START_ADDR1_2_OFFSET (0x90)
+#define CAM_FRAME_START_ADDR_1_2       CAM_FRAME_START_ADDR_1_2
+#define CAM_FRAME_START_ADDR_1_2_POS   (0U)
+#define CAM_FRAME_START_ADDR_1_2_LEN   (32U)
+#define CAM_FRAME_START_ADDR_1_2_MSK   (((1U << CAM_FRAME_START_ADDR_1_2_LEN) - 1) << CAM_FRAME_START_ADDR_1_2_POS)
+#define CAM_FRAME_START_ADDR_1_2_UMSK  (~(((1U << CAM_FRAME_START_ADDR_1_2_LEN) - 1) << CAM_FRAME_START_ADDR_1_2_POS))
+
+/* 0x94 : frame_byte_cnt1_2 */
+#define CAM_FRAME_BYTE_CNT1_2_OFFSET (0x94)
+#define CAM_FRAME_BYTE_CNT_1_2       CAM_FRAME_BYTE_CNT_1_2
+#define CAM_FRAME_BYTE_CNT_1_2_POS   (0U)
+#define CAM_FRAME_BYTE_CNT_1_2_LEN   (32U)
+#define CAM_FRAME_BYTE_CNT_1_2_MSK   (((1U << CAM_FRAME_BYTE_CNT_1_2_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_2_POS)
+#define CAM_FRAME_BYTE_CNT_1_2_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_1_2_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_2_POS))
+
+/* 0x98 : frame_start_addr1_3 */
+#define CAM_FRAME_START_ADDR1_3_OFFSET (0x98)
+#define CAM_FRAME_START_ADDR_1_3       CAM_FRAME_START_ADDR_1_3
+#define CAM_FRAME_START_ADDR_1_3_POS   (0U)
+#define CAM_FRAME_START_ADDR_1_3_LEN   (32U)
+#define CAM_FRAME_START_ADDR_1_3_MSK   (((1U << CAM_FRAME_START_ADDR_1_3_LEN) - 1) << CAM_FRAME_START_ADDR_1_3_POS)
+#define CAM_FRAME_START_ADDR_1_3_UMSK  (~(((1U << CAM_FRAME_START_ADDR_1_3_LEN) - 1) << CAM_FRAME_START_ADDR_1_3_POS))
+
+/* 0x9C : frame_byte_cnt1_3 */
+#define CAM_FRAME_BYTE_CNT1_3_OFFSET (0x9C)
+#define CAM_FRAME_BYTE_CNT_1_3       CAM_FRAME_BYTE_CNT_1_3
+#define CAM_FRAME_BYTE_CNT_1_3_POS   (0U)
+#define CAM_FRAME_BYTE_CNT_1_3_LEN   (32U)
+#define CAM_FRAME_BYTE_CNT_1_3_MSK   (((1U << CAM_FRAME_BYTE_CNT_1_3_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_3_POS)
+#define CAM_FRAME_BYTE_CNT_1_3_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_1_3_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_3_POS))
+
+/* 0xA0 : frame_start_addr1_4 */
+#define CAM_FRAME_START_ADDR1_4_OFFSET (0xA0)
+#define CAM_FRAME_START_ADDR_1_4       CAM_FRAME_START_ADDR_1_4
+#define CAM_FRAME_START_ADDR_1_4_POS   (0U)
+#define CAM_FRAME_START_ADDR_1_4_LEN   (32U)
+#define CAM_FRAME_START_ADDR_1_4_MSK   (((1U << CAM_FRAME_START_ADDR_1_4_LEN) - 1) << CAM_FRAME_START_ADDR_1_4_POS)
+#define CAM_FRAME_START_ADDR_1_4_UMSK  (~(((1U << CAM_FRAME_START_ADDR_1_4_LEN) - 1) << CAM_FRAME_START_ADDR_1_4_POS))
+
+/* 0xA4 : frame_byte_cnt1_4 */
+#define CAM_FRAME_BYTE_CNT1_4_OFFSET (0xA4)
+#define CAM_FRAME_BYTE_CNT_1_4       CAM_FRAME_BYTE_CNT_1_4
+#define CAM_FRAME_BYTE_CNT_1_4_POS   (0U)
+#define CAM_FRAME_BYTE_CNT_1_4_LEN   (32U)
+#define CAM_FRAME_BYTE_CNT_1_4_MSK   (((1U << CAM_FRAME_BYTE_CNT_1_4_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_4_POS)
+#define CAM_FRAME_BYTE_CNT_1_4_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_1_4_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_4_POS))
+
+/* 0xA8 : frame_start_addr1_5 */
+#define CAM_FRAME_START_ADDR1_5_OFFSET (0xA8)
+#define CAM_FRAME_START_ADDR_1_5       CAM_FRAME_START_ADDR_1_5
+#define CAM_FRAME_START_ADDR_1_5_POS   (0U)
+#define CAM_FRAME_START_ADDR_1_5_LEN   (32U)
+#define CAM_FRAME_START_ADDR_1_5_MSK   (((1U << CAM_FRAME_START_ADDR_1_5_LEN) - 1) << CAM_FRAME_START_ADDR_1_5_POS)
+#define CAM_FRAME_START_ADDR_1_5_UMSK  (~(((1U << CAM_FRAME_START_ADDR_1_5_LEN) - 1) << CAM_FRAME_START_ADDR_1_5_POS))
+
+/* 0xAC : frame_byte_cnt1_5 */
+#define CAM_FRAME_BYTE_CNT1_5_OFFSET (0xAC)
+#define CAM_FRAME_BYTE_CNT_1_5       CAM_FRAME_BYTE_CNT_1_5
+#define CAM_FRAME_BYTE_CNT_1_5_POS   (0U)
+#define CAM_FRAME_BYTE_CNT_1_5_LEN   (32U)
+#define CAM_FRAME_BYTE_CNT_1_5_MSK   (((1U << CAM_FRAME_BYTE_CNT_1_5_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_5_POS)
+#define CAM_FRAME_BYTE_CNT_1_5_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_1_5_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_5_POS))
+
+/* 0xB0 : frame_start_addr1_6 */
+#define CAM_FRAME_START_ADDR1_6_OFFSET (0xB0)
+#define CAM_FRAME_START_ADDR_1_6       CAM_FRAME_START_ADDR_1_6
+#define CAM_FRAME_START_ADDR_1_6_POS   (0U)
+#define CAM_FRAME_START_ADDR_1_6_LEN   (32U)
+#define CAM_FRAME_START_ADDR_1_6_MSK   (((1U << CAM_FRAME_START_ADDR_1_6_LEN) - 1) << CAM_FRAME_START_ADDR_1_6_POS)
+#define CAM_FRAME_START_ADDR_1_6_UMSK  (~(((1U << CAM_FRAME_START_ADDR_1_6_LEN) - 1) << CAM_FRAME_START_ADDR_1_6_POS))
+
+/* 0xB4 : frame_byte_cnt1_6 */
+#define CAM_FRAME_BYTE_CNT1_6_OFFSET (0xB4)
+#define CAM_FRAME_BYTE_CNT_1_6       CAM_FRAME_BYTE_CNT_1_6
+#define CAM_FRAME_BYTE_CNT_1_6_POS   (0U)
+#define CAM_FRAME_BYTE_CNT_1_6_LEN   (32U)
+#define CAM_FRAME_BYTE_CNT_1_6_MSK   (((1U << CAM_FRAME_BYTE_CNT_1_6_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_6_POS)
+#define CAM_FRAME_BYTE_CNT_1_6_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_1_6_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_6_POS))
+
+/* 0xB8 : frame_start_addr1_7 */
+#define CAM_FRAME_START_ADDR1_7_OFFSET (0xB8)
+#define CAM_FRAME_START_ADDR_1_7       CAM_FRAME_START_ADDR_1_7
+#define CAM_FRAME_START_ADDR_1_7_POS   (0U)
+#define CAM_FRAME_START_ADDR_1_7_LEN   (32U)
+#define CAM_FRAME_START_ADDR_1_7_MSK   (((1U << CAM_FRAME_START_ADDR_1_7_LEN) - 1) << CAM_FRAME_START_ADDR_1_7_POS)
+#define CAM_FRAME_START_ADDR_1_7_UMSK  (~(((1U << CAM_FRAME_START_ADDR_1_7_LEN) - 1) << CAM_FRAME_START_ADDR_1_7_POS))
+
+/* 0xBC : frame_byte_cnt1_7 */
+#define CAM_FRAME_BYTE_CNT1_7_OFFSET (0xBC)
+#define CAM_FRAME_BYTE_CNT_1_7       CAM_FRAME_BYTE_CNT_1_7
+#define CAM_FRAME_BYTE_CNT_1_7_POS   (0U)
+#define CAM_FRAME_BYTE_CNT_1_7_LEN   (32U)
+#define CAM_FRAME_BYTE_CNT_1_7_MSK   (((1U << CAM_FRAME_BYTE_CNT_1_7_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_7_POS)
+#define CAM_FRAME_BYTE_CNT_1_7_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_1_7_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_7_POS))
+
+/* 0xFF0 : dvp_debug */
+#define CAM_DVP_DEBUG_OFFSET     (0xFF0)
+#define CAM_REG_DVP_DBG_EN       CAM_REG_DVP_DBG_EN
+#define CAM_REG_DVP_DBG_EN_POS   (0U)
+#define CAM_REG_DVP_DBG_EN_LEN   (1U)
+#define CAM_REG_DVP_DBG_EN_MSK   (((1U << CAM_REG_DVP_DBG_EN_LEN) - 1) << CAM_REG_DVP_DBG_EN_POS)
+#define CAM_REG_DVP_DBG_EN_UMSK  (~(((1U << CAM_REG_DVP_DBG_EN_LEN) - 1) << CAM_REG_DVP_DBG_EN_POS))
+#define CAM_REG_DVP_DBG_SEL      CAM_REG_DVP_DBG_SEL
+#define CAM_REG_DVP_DBG_SEL_POS  (1U)
+#define CAM_REG_DVP_DBG_SEL_LEN  (3U)
+#define CAM_REG_DVP_DBG_SEL_MSK  (((1U << CAM_REG_DVP_DBG_SEL_LEN) - 1) << CAM_REG_DVP_DBG_SEL_POS)
+#define CAM_REG_DVP_DBG_SEL_UMSK (~(((1U << CAM_REG_DVP_DBG_SEL_LEN) - 1) << CAM_REG_DVP_DBG_SEL_POS))
+
+/* 0xFFC : dvp_dummy_reg */
+#define CAM_DVP_DUMMY_REG_OFFSET (0xFFC)
+
+struct cam_reg {
+    /* 0x0 : dvp2axi_configue */
+    union {
+        struct
+        {
+            uint32_t reg_dvp_enable     : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_sw_mode        : 1; /* [    1],        r/w,        0x0 */
+            uint32_t reg_fram_vld_pol   : 1; /* [    2],        r/w,        0x1 */
+            uint32_t reg_line_vld_pol   : 1; /* [    3],        r/w,        0x1 */
+            uint32_t reg_hburst         : 2; /* [ 5: 4],        r/w,        0x3 */
+            uint32_t reserved_6_7       : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_dvp_mode       : 3; /* [10: 8],        r/w,        0x0 */
+            uint32_t reg_hw_mode_fwrap  : 1; /* [   11],        r/w,        0x1 */
+            uint32_t reg_drop_en        : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reg_drop_even      : 1; /* [   13],        r/w,        0x0 */
+            uint32_t reg_subsample_en   : 1; /* [   14],        r/w,        0x0 */
+            uint32_t reg_subsample_even : 1; /* [   15],        r/w,        0x0 */
+            uint32_t reg_interlv_mode   : 1; /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17_19     : 3; /* [19:17],       rsvd,        0x0 */
+            uint32_t reg_dvp_pix_clk_cg : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reserved_21_23     : 3; /* [23:21],       rsvd,        0x0 */
+            uint32_t reg_dvp_wait_cycle : 8; /* [31:24],        r/w,       0x40 */
+        } BF;
+        uint32_t WORD;
+    } dvp2axi_configue;
+
+    /* 0x4 : dvp2ahb_addr_start_0 */
+    union {
+        struct
+        {
+            uint32_t reg_addr_start_0 : 32; /* [31: 0],        r/w, 0x80000000L */
+        } BF;
+        uint32_t WORD;
+    } dvp2ahb_addr_start_0;
+
+    /* 0x8 : dvp2ahb_mem_bcnt_0 */
+    union {
+        struct
+        {
+            uint32_t reg_mem_burst_cnt_0 : 32; /* [31: 0],        r/w,     0xc000 */
+        } BF;
+        uint32_t WORD;
+    } dvp2ahb_mem_bcnt_0;
+
+    /* 0xC : dvp2ahb_frame_bcnt_0 */
+    union {
+        struct
+        {
+            uint32_t reg_frame_burst_cnt_0 : 32; /* [31: 0],        r/w,     0xc000 */
+        } BF;
+        uint32_t WORD;
+    } dvp2ahb_frame_bcnt_0;
+
+    /* 0x10 : dvp2ahb_addr_start_1 */
+    union {
+        struct
+        {
+            uint32_t reg_addr_start_1 : 32; /* [31: 0],        r/w, 0x80000000L */
+        } BF;
+        uint32_t WORD;
+    } dvp2ahb_addr_start_1;
+
+    /* 0x14 : dvp2ahb_mem_bcnt_1 */
+    union {
+        struct
+        {
+            uint32_t reg_mem_burst_cnt_1 : 32; /* [31: 0],        r/w,     0xc000 */
+        } BF;
+        uint32_t WORD;
+    } dvp2ahb_mem_bcnt_1;
+
+    /* 0x18 : dvp2ahb_frame_bcnt_1 */
+    union {
+        struct
+        {
+            uint32_t reg_frame_burst_cnt_1 : 32; /* [31: 0],        r/w,     0xc000 */
+        } BF;
+        uint32_t WORD;
+    } dvp2ahb_frame_bcnt_1;
+
+    /* 0x1C : dvp_status_and_error */
+    union {
+        struct
+        {
+            uint32_t sts_normal_int_0  : 1; /* [    0],          r,        0x0 */
+            uint32_t sts_normal_int_1  : 1; /* [    1],          r,        0x0 */
+            uint32_t sts_mem_int_0     : 1; /* [    2],          r,        0x0 */
+            uint32_t sts_mem_int_1     : 1; /* [    3],          r,        0x0 */
+            uint32_t sts_frame_int_0   : 1; /* [    4],          r,        0x0 */
+            uint32_t sts_frame_int_1   : 1; /* [    5],          r,        0x0 */
+            uint32_t sts_fifo_int_0    : 1; /* [    6],          r,        0x0 */
+            uint32_t sts_fifo_int_1    : 1; /* [    7],          r,        0x0 */
+            uint32_t sts_hcnt_int      : 1; /* [    8],          r,        0x0 */
+            uint32_t sts_vcnt_int      : 1; /* [    9],          r,        0x0 */
+            uint32_t reserved_10_15    : 6; /* [15:10],       rsvd,        0x0 */
+            uint32_t ahb_idle_0        : 1; /* [   16],          r,        0x1 */
+            uint32_t ahb_idle_1        : 1; /* [   17],          r,        0x1 */
+            uint32_t reserved_18       : 1; /* [   18],       rsvd,        0x0 */
+            uint32_t st_dvp_idle       : 1; /* [   19],          r,        0x1 */
+            uint32_t frame_valid_cnt_0 : 4; /* [23:20],          r,        0x0 */
+            uint32_t frame_valid_cnt_1 : 4; /* [27:24],          r,        0x0 */
+            uint32_t st_bus_idle       : 1; /* [   28],          r,        0x1 */
+            uint32_t st_bus_func       : 1; /* [   29],          r,        0x0 */
+            uint32_t st_bus_wait       : 1; /* [   30],          r,        0x0 */
+            uint32_t st_bus_flsh       : 1; /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dvp_status_and_error;
+
+    /* 0x20 : dvp_frame_fifo_pop */
+    union {
+        struct
+        {
+            uint32_t rfifo_pop_0          : 1;  /* [    0],        w1p,        0x0 */
+            uint32_t rfifo_pop_1          : 1;  /* [    1],        w1p,        0x0 */
+            uint32_t reserved_2_3         : 2;  /* [ 3: 2],       rsvd,        0x0 */
+            uint32_t reg_int_normal_clr_0 : 1;  /* [    4],        w1p,        0x0 */
+            uint32_t reg_int_mem_clr_0    : 1;  /* [    5],        w1p,        0x0 */
+            uint32_t reg_int_frame_clr_0  : 1;  /* [    6],        w1p,        0x0 */
+            uint32_t reg_int_fifo_clr_0   : 1;  /* [    7],        w1p,        0x0 */
+            uint32_t reg_int_hcnt_clr_0   : 1;  /* [    8],        w1p,        0x0 */
+            uint32_t reg_int_vcnt_clr_0   : 1;  /* [    9],        w1p,        0x0 */
+            uint32_t reserved_10_15       : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t reg_int_normal_clr_1 : 1;  /* [   16],        w1p,        0x0 */
+            uint32_t reg_int_mem_clr_1    : 1;  /* [   17],        w1p,        0x0 */
+            uint32_t reg_int_frame_clr_1  : 1;  /* [   18],        w1p,        0x0 */
+            uint32_t reg_int_fifo_clr_1   : 1;  /* [   19],        w1p,        0x0 */
+            uint32_t reserved_20_31       : 12; /* [31:20],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dvp_frame_fifo_pop;
+
+    /* 0x24 : snsr_control */
+    union {
+        struct
+        {
+            uint32_t reg_cam_rst   : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reg_cam_pwdn  : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reserved_2_31 : 30; /* [31: 2],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } snsr_control;
+
+    /* 0x28 : int_control */
+    union {
+        struct
+        {
+            uint32_t reg_int_normal_0_en    : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_int_normal_1_en    : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reg_int_mem_en         : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reg_int_frame_en       : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t reg_int_fifo_en        : 1;  /* [    4],        r/w,        0x1 */
+            uint32_t reg_int_hcnt_en        : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reg_int_vcnt_en        : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7_27          : 21; /* [27: 7],       rsvd,        0x0 */
+            uint32_t reg_frame_cnt_trgr_int : 4;  /* [31:28],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } int_control;
+
+    /* 0x2c  reserved */
+    uint8_t RESERVED0x2c[4];
+
+    /* 0x30 : hsync_control */
+    union {
+        struct
+        {
+            uint32_t reg_hsync_act_end   : 16; /* [15: 0],        r/w,     0xffff */
+            uint32_t reg_hsync_act_start : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } hsync_control;
+
+    /* 0x34 : vsync_control */
+    union {
+        struct
+        {
+            uint32_t reg_vsync_act_end   : 16; /* [15: 0],        r/w,     0xffff */
+            uint32_t reg_vsync_act_start : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } vsync_control;
+
+    /* 0x38 : frame_size_control */
+    union {
+        struct
+        {
+            uint32_t reg_total_hcnt : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reg_total_vcnt : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_size_control;
+
+    /* 0x3c  reserved */
+    uint8_t RESERVED0x3c[4];
+
+    /* 0x40 : frame_start_addr0_0 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_0_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_start_addr0_0;
+
+    /* 0x44 : frame_byte_cnt0_0 */
+    union {
+        struct
+        {
+            uint32_t frame_byte_cnt_0_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_byte_cnt0_0;
+
+    /* 0x48 : frame_start_addr0_1 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_0_1 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_start_addr0_1;
+
+    /* 0x4C : frame_byte_cnt0_1 */
+    union {
+        struct
+        {
+            uint32_t frame_byte_cnt_0_1 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_byte_cnt0_1;
+
+    /* 0x50 : frame_start_addr0_2 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_0_2 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_start_addr0_2;
+
+    /* 0x54 : frame_byte_cnt0_2 */
+    union {
+        struct
+        {
+            uint32_t frame_byte_cnt_0_2 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_byte_cnt0_2;
+
+    /* 0x58 : frame_start_addr0_3 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_0_3 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_start_addr0_3;
+
+    /* 0x5C : frame_byte_cnt0_3 */
+    union {
+        struct
+        {
+            uint32_t frame_byte_cnt_0_3 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_byte_cnt0_3;
+
+    /* 0x60 : frame_start_addr0_4 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_0_4 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_start_addr0_4;
+
+    /* 0x64 : frame_byte_cnt0_4 */
+    union {
+        struct
+        {
+            uint32_t frame_byte_cnt_0_4 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_byte_cnt0_4;
+
+    /* 0x68 : frame_start_addr0_5 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_0_5 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_start_addr0_5;
+
+    /* 0x6C : frame_byte_cnt0_5 */
+    union {
+        struct
+        {
+            uint32_t frame_byte_cnt_0_5 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_byte_cnt0_5;
+
+    /* 0x70 : frame_start_addr0_6 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_0_6 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_start_addr0_6;
+
+    /* 0x74 : frame_byte_cnt0_6 */
+    union {
+        struct
+        {
+            uint32_t frame_byte_cnt_0_6 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_byte_cnt0_6;
+
+    /* 0x78 : frame_start_addr0_7 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_0_7 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_start_addr0_7;
+
+    /* 0x7C : frame_byte_cnt0_7 */
+    union {
+        struct
+        {
+            uint32_t frame_byte_cnt_0_7 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_byte_cnt0_7;
+
+    /* 0x80 : frame_start_addr1_0 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_1_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_start_addr1_0;
+
+    /* 0x84 : frame_byte_cnt1_0 */
+    union {
+        struct
+        {
+            uint32_t frame_byte_cnt_1_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_byte_cnt1_0;
+
+    /* 0x88 : frame_start_addr1_1 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_1_1 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_start_addr1_1;
+
+    /* 0x8C : frame_byte_cnt1_1 */
+    union {
+        struct
+        {
+            uint32_t frame_byte_cnt_1_1 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_byte_cnt1_1;
+
+    /* 0x90 : frame_start_addr1_2 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_1_2 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_start_addr1_2;
+
+    /* 0x94 : frame_byte_cnt1_2 */
+    union {
+        struct
+        {
+            uint32_t frame_byte_cnt_1_2 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_byte_cnt1_2;
+
+    /* 0x98 : frame_start_addr1_3 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_1_3 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_start_addr1_3;
+
+    /* 0x9C : frame_byte_cnt1_3 */
+    union {
+        struct
+        {
+            uint32_t frame_byte_cnt_1_3 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_byte_cnt1_3;
+
+    /* 0xA0 : frame_start_addr1_4 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_1_4 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_start_addr1_4;
+
+    /* 0xA4 : frame_byte_cnt1_4 */
+    union {
+        struct
+        {
+            uint32_t frame_byte_cnt_1_4 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_byte_cnt1_4;
+
+    /* 0xA8 : frame_start_addr1_5 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_1_5 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_start_addr1_5;
+
+    /* 0xAC : frame_byte_cnt1_5 */
+    union {
+        struct
+        {
+            uint32_t frame_byte_cnt_1_5 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_byte_cnt1_5;
+
+    /* 0xB0 : frame_start_addr1_6 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_1_6 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_start_addr1_6;
+
+    /* 0xB4 : frame_byte_cnt1_6 */
+    union {
+        struct
+        {
+            uint32_t frame_byte_cnt_1_6 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_byte_cnt1_6;
+
+    /* 0xB8 : frame_start_addr1_7 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_1_7 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_start_addr1_7;
+
+    /* 0xBC : frame_byte_cnt1_7 */
+    union {
+        struct
+        {
+            uint32_t frame_byte_cnt_1_7 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } frame_byte_cnt1_7;
+
+    /* 0xc0  reserved */
+    uint8_t RESERVED0xc0[3888];
+
+    /* 0xFF0 : dvp_debug */
+    union {
+        struct
+        {
+            uint32_t reg_dvp_dbg_en  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_dvp_dbg_sel : 3;  /* [ 3: 1],        r/w,        0x0 */
+            uint32_t reserved_4_31   : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dvp_debug;
+
+    /* 0xff4  reserved */
+    uint8_t RESERVED0xff4[8];
+
+    /* 0xFFC : dvp_dummy_reg */
+    union {
+        struct
+        {
+            uint32_t RESERVED_31_0 : 32; /* [31: 0],       rsvd, 0xf0f0f0f0L */
+        } BF;
+        uint32_t WORD;
+    } dvp_dummy_reg;
+};
+
+typedef volatile struct cam_reg cam_reg_t;
+
+#endif /* __CAM_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/cci_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/cci_reg.h
new file mode 100644
index 00000000..e1fe7525
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/cci_reg.h
@@ -0,0 +1,192 @@
+/**
+  ******************************************************************************
+  * @file    cci_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __CCI_REG_H__
+#define __CCI_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : cci_cfg */
+#define CCI_CFG_OFFSET              (0x0)
+#define CCI_EN                      CCI_EN
+#define CCI_EN_POS                  (0U)
+#define CCI_EN_LEN                  (1U)
+#define CCI_EN_MSK                  (((1U << CCI_EN_LEN) - 1) << CCI_EN_POS)
+#define CCI_EN_UMSK                 (~(((1U << CCI_EN_LEN) - 1) << CCI_EN_POS))
+#define CCI_SLV_SEL_CCI2            CCI_SLV_SEL_CCI2
+#define CCI_SLV_SEL_CCI2_POS        (1U)
+#define CCI_SLV_SEL_CCI2_LEN        (1U)
+#define CCI_SLV_SEL_CCI2_MSK        (((1U << CCI_SLV_SEL_CCI2_LEN) - 1) << CCI_SLV_SEL_CCI2_POS)
+#define CCI_SLV_SEL_CCI2_UMSK       (~(((1U << CCI_SLV_SEL_CCI2_LEN) - 1) << CCI_SLV_SEL_CCI2_POS))
+#define CCI_MAS_SEL_CCI2            CCI_MAS_SEL_CCI2
+#define CCI_MAS_SEL_CCI2_POS        (2U)
+#define CCI_MAS_SEL_CCI2_LEN        (1U)
+#define CCI_MAS_SEL_CCI2_MSK        (((1U << CCI_MAS_SEL_CCI2_LEN) - 1) << CCI_MAS_SEL_CCI2_POS)
+#define CCI_MAS_SEL_CCI2_UMSK       (~(((1U << CCI_MAS_SEL_CCI2_LEN) - 1) << CCI_MAS_SEL_CCI2_POS))
+#define CCI_MAS_HW_MODE             CCI_MAS_HW_MODE
+#define CCI_MAS_HW_MODE_POS         (3U)
+#define CCI_MAS_HW_MODE_LEN         (1U)
+#define CCI_MAS_HW_MODE_MSK         (((1U << CCI_MAS_HW_MODE_LEN) - 1) << CCI_MAS_HW_MODE_POS)
+#define CCI_MAS_HW_MODE_UMSK        (~(((1U << CCI_MAS_HW_MODE_LEN) - 1) << CCI_MAS_HW_MODE_POS))
+#define CCI_REG_M_CCI_SCLK_EN       CCI_REG_M_CCI_SCLK_EN
+#define CCI_REG_M_CCI_SCLK_EN_POS   (4U)
+#define CCI_REG_M_CCI_SCLK_EN_LEN   (1U)
+#define CCI_REG_M_CCI_SCLK_EN_MSK   (((1U << CCI_REG_M_CCI_SCLK_EN_LEN) - 1) << CCI_REG_M_CCI_SCLK_EN_POS)
+#define CCI_REG_M_CCI_SCLK_EN_UMSK  (~(((1U << CCI_REG_M_CCI_SCLK_EN_LEN) - 1) << CCI_REG_M_CCI_SCLK_EN_POS))
+#define CCI_REG_DIV_M_CCI_SCLK      CCI_REG_DIV_M_CCI_SCLK
+#define CCI_REG_DIV_M_CCI_SCLK_POS  (5U)
+#define CCI_REG_DIV_M_CCI_SCLK_LEN  (2U)
+#define CCI_REG_DIV_M_CCI_SCLK_MSK  (((1U << CCI_REG_DIV_M_CCI_SCLK_LEN) - 1) << CCI_REG_DIV_M_CCI_SCLK_POS)
+#define CCI_REG_DIV_M_CCI_SCLK_UMSK (~(((1U << CCI_REG_DIV_M_CCI_SCLK_LEN) - 1) << CCI_REG_DIV_M_CCI_SCLK_POS))
+#define CCI_CFG_CCI1_PRE_READ       CCI_CFG_CCI1_PRE_READ
+#define CCI_CFG_CCI1_PRE_READ_POS   (7U)
+#define CCI_CFG_CCI1_PRE_READ_LEN   (1U)
+#define CCI_CFG_CCI1_PRE_READ_MSK   (((1U << CCI_CFG_CCI1_PRE_READ_LEN) - 1) << CCI_CFG_CCI1_PRE_READ_POS)
+#define CCI_CFG_CCI1_PRE_READ_UMSK  (~(((1U << CCI_CFG_CCI1_PRE_READ_LEN) - 1) << CCI_CFG_CCI1_PRE_READ_POS))
+#define CCI_REG_SCCI_CLK_INV        CCI_REG_SCCI_CLK_INV
+#define CCI_REG_SCCI_CLK_INV_POS    (8U)
+#define CCI_REG_SCCI_CLK_INV_LEN    (1U)
+#define CCI_REG_SCCI_CLK_INV_MSK    (((1U << CCI_REG_SCCI_CLK_INV_LEN) - 1) << CCI_REG_SCCI_CLK_INV_POS)
+#define CCI_REG_SCCI_CLK_INV_UMSK   (~(((1U << CCI_REG_SCCI_CLK_INV_LEN) - 1) << CCI_REG_SCCI_CLK_INV_POS))
+#define CCI_REG_MCCI_CLK_INV        CCI_REG_MCCI_CLK_INV
+#define CCI_REG_MCCI_CLK_INV_POS    (9U)
+#define CCI_REG_MCCI_CLK_INV_LEN    (1U)
+#define CCI_REG_MCCI_CLK_INV_MSK    (((1U << CCI_REG_MCCI_CLK_INV_LEN) - 1) << CCI_REG_MCCI_CLK_INV_POS)
+#define CCI_REG_MCCI_CLK_INV_UMSK   (~(((1U << CCI_REG_MCCI_CLK_INV_LEN) - 1) << CCI_REG_MCCI_CLK_INV_POS))
+
+/* 0x4 : cci_addr */
+#define CCI_ADDR_OFFSET       (0x4)
+#define CCI_APB_CCI_ADDR      CCI_APB_CCI_ADDR
+#define CCI_APB_CCI_ADDR_POS  (0U)
+#define CCI_APB_CCI_ADDR_LEN  (32U)
+#define CCI_APB_CCI_ADDR_MSK  (((1U << CCI_APB_CCI_ADDR_LEN) - 1) << CCI_APB_CCI_ADDR_POS)
+#define CCI_APB_CCI_ADDR_UMSK (~(((1U << CCI_APB_CCI_ADDR_LEN) - 1) << CCI_APB_CCI_ADDR_POS))
+
+/* 0x8 : cci_wdata */
+#define CCI_WDATA_OFFSET       (0x8)
+#define CCI_APB_CCI_WDATA      CCI_APB_CCI_WDATA
+#define CCI_APB_CCI_WDATA_POS  (0U)
+#define CCI_APB_CCI_WDATA_LEN  (32U)
+#define CCI_APB_CCI_WDATA_MSK  (((1U << CCI_APB_CCI_WDATA_LEN) - 1) << CCI_APB_CCI_WDATA_POS)
+#define CCI_APB_CCI_WDATA_UMSK (~(((1U << CCI_APB_CCI_WDATA_LEN) - 1) << CCI_APB_CCI_WDATA_POS))
+
+/* 0xC : cci_rdata */
+#define CCI_RDATA_OFFSET       (0xC)
+#define CCI_APB_CCI_RDATA      CCI_APB_CCI_RDATA
+#define CCI_APB_CCI_RDATA_POS  (0U)
+#define CCI_APB_CCI_RDATA_LEN  (32U)
+#define CCI_APB_CCI_RDATA_MSK  (((1U << CCI_APB_CCI_RDATA_LEN) - 1) << CCI_APB_CCI_RDATA_POS)
+#define CCI_APB_CCI_RDATA_UMSK (~(((1U << CCI_APB_CCI_RDATA_LEN) - 1) << CCI_APB_CCI_RDATA_POS))
+
+/* 0x10 : cci_ctl */
+#define CCI_CTL_OFFSET      (0x10)
+#define CCI_WRITE_FLAG      CCI_WRITE_FLAG
+#define CCI_WRITE_FLAG_POS  (0U)
+#define CCI_WRITE_FLAG_LEN  (1U)
+#define CCI_WRITE_FLAG_MSK  (((1U << CCI_WRITE_FLAG_LEN) - 1) << CCI_WRITE_FLAG_POS)
+#define CCI_WRITE_FLAG_UMSK (~(((1U << CCI_WRITE_FLAG_LEN) - 1) << CCI_WRITE_FLAG_POS))
+#define CCI_READ_FLAG       CCI_READ_FLAG
+#define CCI_READ_FLAG_POS   (1U)
+#define CCI_READ_FLAG_LEN   (1U)
+#define CCI_READ_FLAG_MSK   (((1U << CCI_READ_FLAG_LEN) - 1) << CCI_READ_FLAG_POS)
+#define CCI_READ_FLAG_UMSK  (~(((1U << CCI_READ_FLAG_LEN) - 1) << CCI_READ_FLAG_POS))
+#define CCI_AHB_STATE       CCI_AHB_STATE
+#define CCI_AHB_STATE_POS   (2U)
+#define CCI_AHB_STATE_LEN   (2U)
+#define CCI_AHB_STATE_MSK   (((1U << CCI_AHB_STATE_LEN) - 1) << CCI_AHB_STATE_POS)
+#define CCI_AHB_STATE_UMSK  (~(((1U << CCI_AHB_STATE_LEN) - 1) << CCI_AHB_STATE_POS))
+
+struct cci_reg {
+    /* 0x0 : cci_cfg */
+    union {
+        struct
+        {
+            uint32_t cci_en             : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t cci_slv_sel_cci2   : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t cci_mas_sel_cci2   : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t cci_mas_hw_mode    : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t reg_m_cci_sclk_en  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_div_m_cci_sclk : 2;  /* [ 6: 5],        r/w,        0x1 */
+            uint32_t cfg_cci1_pre_read  : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t reg_scci_clk_inv   : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t reg_mcci_clk_inv   : 1;  /* [    9],        r/w,        0x1 */
+            uint32_t reserved_10_31     : 22; /* [31:10],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cci_cfg;
+
+    /* 0x4 : cci_addr */
+    union {
+        struct
+        {
+            uint32_t apb_cci_addr : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cci_addr;
+
+    /* 0x8 : cci_wdata */
+    union {
+        struct
+        {
+            uint32_t apb_cci_wdata : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cci_wdata;
+
+    /* 0xC : cci_rdata */
+    union {
+        struct
+        {
+            uint32_t apb_cci_rdata : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cci_rdata;
+
+    /* 0x10 : cci_ctl */
+    union {
+        struct
+        {
+            uint32_t cci_write_flag : 1;  /* [    0],          r,        0x0 */
+            uint32_t cci_read_flag  : 1;  /* [    1],          r,        0x0 */
+            uint32_t ahb_state      : 2;  /* [ 3: 2],          r,        0x0 */
+            uint32_t reserved_4_31  : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cci_ctl;
+};
+
+typedef volatile struct cci_reg cci_reg_t;
+
+#endif /* __CCI_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/cks_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/cks_reg.h
new file mode 100644
index 00000000..0a7ed1b2
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/cks_reg.h
@@ -0,0 +1,105 @@
+/**
+  ******************************************************************************
+  * @file    cks_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __CKS_REG_H__
+#define __CKS_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : cks_config */
+#define CKS_CONFIG_OFFSET         (0x0)
+#define CKS_CR_CKS_CLR            CKS_CR_CKS_CLR
+#define CKS_CR_CKS_CLR_POS        (0U)
+#define CKS_CR_CKS_CLR_LEN        (1U)
+#define CKS_CR_CKS_CLR_MSK        (((1U << CKS_CR_CKS_CLR_LEN) - 1) << CKS_CR_CKS_CLR_POS)
+#define CKS_CR_CKS_CLR_UMSK       (~(((1U << CKS_CR_CKS_CLR_LEN) - 1) << CKS_CR_CKS_CLR_POS))
+#define CKS_CR_CKS_BYTE_SWAP      CKS_CR_CKS_BYTE_SWAP
+#define CKS_CR_CKS_BYTE_SWAP_POS  (1U)
+#define CKS_CR_CKS_BYTE_SWAP_LEN  (1U)
+#define CKS_CR_CKS_BYTE_SWAP_MSK  (((1U << CKS_CR_CKS_BYTE_SWAP_LEN) - 1) << CKS_CR_CKS_BYTE_SWAP_POS)
+#define CKS_CR_CKS_BYTE_SWAP_UMSK (~(((1U << CKS_CR_CKS_BYTE_SWAP_LEN) - 1) << CKS_CR_CKS_BYTE_SWAP_POS))
+
+/* 0x4 : data_in */
+#define CKS_DATA_IN_OFFSET (0x4)
+#define CKS_DATA_IN        CKS_DATA_IN
+#define CKS_DATA_IN_POS    (0U)
+#define CKS_DATA_IN_LEN    (8U)
+#define CKS_DATA_IN_MSK    (((1U << CKS_DATA_IN_LEN) - 1) << CKS_DATA_IN_POS)
+#define CKS_DATA_IN_UMSK   (~(((1U << CKS_DATA_IN_LEN) - 1) << CKS_DATA_IN_POS))
+
+/* 0x8 : cks_out */
+#define CKS_OUT_OFFSET (0x8)
+#define CKS_OUT        CKS_OUT
+#define CKS_OUT_POS    (0U)
+#define CKS_OUT_LEN    (16U)
+#define CKS_OUT_MSK    (((1U << CKS_OUT_LEN) - 1) << CKS_OUT_POS)
+#define CKS_OUT_UMSK   (~(((1U << CKS_OUT_LEN) - 1) << CKS_OUT_POS))
+
+struct cks_reg {
+    /* 0x0 : cks_config */
+    union {
+        struct
+        {
+            uint32_t cr_cks_clr       : 1;  /* [    0],        w1c,        0x0 */
+            uint32_t cr_cks_byte_swap : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_31    : 30; /* [31: 2],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cks_config;
+
+    /* 0x4 : data_in */
+    union {
+        struct
+        {
+            uint32_t data_in       : 8;  /* [ 7: 0],          w,          x */
+            uint32_t reserved_8_31 : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } data_in;
+
+    /* 0x8 : cks_out */
+    union {
+        struct
+        {
+            uint32_t cks_out        : 16; /* [15: 0],          r,     0xffff */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cks_out;
+};
+
+typedef volatile struct cks_reg cks_reg_t;
+
+#endif /* __CKS_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/dma_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/dma_reg.h
new file mode 100644
index 00000000..30438181
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/dma_reg.h
@@ -0,0 +1,2232 @@
+/**
+  ******************************************************************************
+  * @file    dma_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __DMA_REG_H__
+#define __DMA_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : DMA_IntStatus */
+#define DMA_INTSTATUS_OFFSET (0x0)
+#define DMA_INTSTATUS        DMA_INTSTATUS
+#define DMA_INTSTATUS_POS    (0U)
+#define DMA_INTSTATUS_LEN    (8U)
+#define DMA_INTSTATUS_MSK    (((1U << DMA_INTSTATUS_LEN) - 1) << DMA_INTSTATUS_POS)
+#define DMA_INTSTATUS_UMSK   (~(((1U << DMA_INTSTATUS_LEN) - 1) << DMA_INTSTATUS_POS))
+
+/* 0x4 : DMA_IntTCStatus */
+#define DMA_INTTCSTATUS_OFFSET (0x4)
+#define DMA_INTTCSTATUS        DMA_INTTCSTATUS
+#define DMA_INTTCSTATUS_POS    (0U)
+#define DMA_INTTCSTATUS_LEN    (8U)
+#define DMA_INTTCSTATUS_MSK    (((1U << DMA_INTTCSTATUS_LEN) - 1) << DMA_INTTCSTATUS_POS)
+#define DMA_INTTCSTATUS_UMSK   (~(((1U << DMA_INTTCSTATUS_LEN) - 1) << DMA_INTTCSTATUS_POS))
+
+/* 0x8 : DMA_IntTCClear */
+#define DMA_INTTCCLEAR_OFFSET (0x8)
+#define DMA_INTTCCLEAR        DMA_INTTCCLEAR
+#define DMA_INTTCCLEAR_POS    (0U)
+#define DMA_INTTCCLEAR_LEN    (8U)
+#define DMA_INTTCCLEAR_MSK    (((1U << DMA_INTTCCLEAR_LEN) - 1) << DMA_INTTCCLEAR_POS)
+#define DMA_INTTCCLEAR_UMSK   (~(((1U << DMA_INTTCCLEAR_LEN) - 1) << DMA_INTTCCLEAR_POS))
+
+/* 0xC : DMA_IntErrorStatus */
+#define DMA_INTERRORSTATUS_OFFSET (0xC)
+#define DMA_INTERRORSTATUS        DMA_INTERRORSTATUS
+#define DMA_INTERRORSTATUS_POS    (0U)
+#define DMA_INTERRORSTATUS_LEN    (8U)
+#define DMA_INTERRORSTATUS_MSK    (((1U << DMA_INTERRORSTATUS_LEN) - 1) << DMA_INTERRORSTATUS_POS)
+#define DMA_INTERRORSTATUS_UMSK   (~(((1U << DMA_INTERRORSTATUS_LEN) - 1) << DMA_INTERRORSTATUS_POS))
+
+/* 0x10 : DMA_IntErrClr */
+#define DMA_INTERRCLR_OFFSET (0x10)
+#define DMA_INTERRCLR        DMA_INTERRCLR
+#define DMA_INTERRCLR_POS    (0U)
+#define DMA_INTERRCLR_LEN    (8U)
+#define DMA_INTERRCLR_MSK    (((1U << DMA_INTERRCLR_LEN) - 1) << DMA_INTERRCLR_POS)
+#define DMA_INTERRCLR_UMSK   (~(((1U << DMA_INTERRCLR_LEN) - 1) << DMA_INTERRCLR_POS))
+
+/* 0x14 : DMA_RawIntTCStatus */
+#define DMA_RAWINTTCSTATUS_OFFSET (0x14)
+#define DMA_RAWINTTCSTATUS        DMA_RAWINTTCSTATUS
+#define DMA_RAWINTTCSTATUS_POS    (0U)
+#define DMA_RAWINTTCSTATUS_LEN    (8U)
+#define DMA_RAWINTTCSTATUS_MSK    (((1U << DMA_RAWINTTCSTATUS_LEN) - 1) << DMA_RAWINTTCSTATUS_POS)
+#define DMA_RAWINTTCSTATUS_UMSK   (~(((1U << DMA_RAWINTTCSTATUS_LEN) - 1) << DMA_RAWINTTCSTATUS_POS))
+
+/* 0x18 : DMA_RawIntErrorStatus */
+#define DMA_RAWINTERRORSTATUS_OFFSET (0x18)
+#define DMA_RAWINTERRORSTATUS        DMA_RAWINTERRORSTATUS
+#define DMA_RAWINTERRORSTATUS_POS    (0U)
+#define DMA_RAWINTERRORSTATUS_LEN    (8U)
+#define DMA_RAWINTERRORSTATUS_MSK    (((1U << DMA_RAWINTERRORSTATUS_LEN) - 1) << DMA_RAWINTERRORSTATUS_POS)
+#define DMA_RAWINTERRORSTATUS_UMSK   (~(((1U << DMA_RAWINTERRORSTATUS_LEN) - 1) << DMA_RAWINTERRORSTATUS_POS))
+
+/* 0x1C : DMA_EnbldChns */
+#define DMA_ENBLDCHNS_OFFSET     (0x1C)
+#define DMA_ENABLEDCHANNELS      DMA_ENABLEDCHANNELS
+#define DMA_ENABLEDCHANNELS_POS  (0U)
+#define DMA_ENABLEDCHANNELS_LEN  (8U)
+#define DMA_ENABLEDCHANNELS_MSK  (((1U << DMA_ENABLEDCHANNELS_LEN) - 1) << DMA_ENABLEDCHANNELS_POS)
+#define DMA_ENABLEDCHANNELS_UMSK (~(((1U << DMA_ENABLEDCHANNELS_LEN) - 1) << DMA_ENABLEDCHANNELS_POS))
+
+/* 0x20 : DMA_SoftBReq */
+#define DMA_SOFTBREQ_OFFSET (0x20)
+#define DMA_SOFTBREQ        DMA_SOFTBREQ
+#define DMA_SOFTBREQ_POS    (0U)
+#define DMA_SOFTBREQ_LEN    (32U)
+#define DMA_SOFTBREQ_MSK    (((1U << DMA_SOFTBREQ_LEN) - 1) << DMA_SOFTBREQ_POS)
+#define DMA_SOFTBREQ_UMSK   (~(((1U << DMA_SOFTBREQ_LEN) - 1) << DMA_SOFTBREQ_POS))
+
+/* 0x24 : DMA_SoftSReq */
+#define DMA_SOFTSREQ_OFFSET (0x24)
+#define DMA_SOFTSREQ        DMA_SOFTSREQ
+#define DMA_SOFTSREQ_POS    (0U)
+#define DMA_SOFTSREQ_LEN    (32U)
+#define DMA_SOFTSREQ_MSK    (((1U << DMA_SOFTSREQ_LEN) - 1) << DMA_SOFTSREQ_POS)
+#define DMA_SOFTSREQ_UMSK   (~(((1U << DMA_SOFTSREQ_LEN) - 1) << DMA_SOFTSREQ_POS))
+
+/* 0x28 : DMA_SoftLBReq */
+#define DMA_SOFTLBREQ_OFFSET (0x28)
+#define DMA_SOFTLBREQ        DMA_SOFTLBREQ
+#define DMA_SOFTLBREQ_POS    (0U)
+#define DMA_SOFTLBREQ_LEN    (32U)
+#define DMA_SOFTLBREQ_MSK    (((1U << DMA_SOFTLBREQ_LEN) - 1) << DMA_SOFTLBREQ_POS)
+#define DMA_SOFTLBREQ_UMSK   (~(((1U << DMA_SOFTLBREQ_LEN) - 1) << DMA_SOFTLBREQ_POS))
+
+/* 0x2C : DMA_SoftLSReq */
+#define DMA_SOFTLSREQ_OFFSET (0x2C)
+#define DMA_SOFTLSREQ        DMA_SOFTLSREQ
+#define DMA_SOFTLSREQ_POS    (0U)
+#define DMA_SOFTLSREQ_LEN    (32U)
+#define DMA_SOFTLSREQ_MSK    (((1U << DMA_SOFTLSREQ_LEN) - 1) << DMA_SOFTLSREQ_POS)
+#define DMA_SOFTLSREQ_UMSK   (~(((1U << DMA_SOFTLSREQ_LEN) - 1) << DMA_SOFTLSREQ_POS))
+
+/* 0x30 : DMA_Top_Config */
+#define DMA_TOP_CONFIG_OFFSET (0x30)
+#define DMA_E                 DMA_E
+#define DMA_E_POS             (0U)
+#define DMA_E_LEN             (1U)
+#define DMA_E_MSK             (((1U << DMA_E_LEN) - 1) << DMA_E_POS)
+#define DMA_E_UMSK            (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS))
+#define DMA_M                 DMA_M
+#define DMA_M_POS             (1U)
+#define DMA_M_LEN             (1U)
+#define DMA_M_MSK             (((1U << DMA_M_LEN) - 1) << DMA_M_POS)
+#define DMA_M_UMSK            (~(((1U << DMA_M_LEN) - 1) << DMA_M_POS))
+
+/* 0x34 : DMA_Sync */
+#define DMA_SYNC_OFFSET (0x34)
+#define DMA_SYNC        DMA_SYNC
+#define DMA_SYNC_POS    (0U)
+#define DMA_SYNC_LEN    (32U)
+#define DMA_SYNC_MSK    (((1U << DMA_SYNC_LEN) - 1) << DMA_SYNC_POS)
+#define DMA_SYNC_UMSK   (~(((1U << DMA_SYNC_LEN) - 1) << DMA_SYNC_POS))
+
+#if 0
+/* 0x100 : DMA_C0SrcAddr */
+#define DMA_C0SRCADDR_OFFSET   (0x100)
+#define DMA_SRCADDR            DMA_SRCADDR
+#define DMA_SRCADDR_POS        (0U)
+#define DMA_SRCADDR_LEN        (32U)
+#define DMA_SRCADDR_MSK        (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)
+#define DMA_SRCADDR_UMSK       (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS))
+
+/* 0x104 : DMA_C0DstAddr */
+#define DMA_C0DSTADDR_OFFSET   (0x104)
+#define DMA_DSTADDR            DMA_DSTADDR
+#define DMA_DSTADDR_POS        (0U)
+#define DMA_DSTADDR_LEN        (32U)
+#define DMA_DSTADDR_MSK        (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)
+#define DMA_DSTADDR_UMSK       (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS))
+
+/* 0x108 : DMA_C0LLI */
+#define DMA_C0LLI_OFFSET       (0x108)
+#define DMA_LLI                DMA_LLI
+#define DMA_LLI_POS            (0U)
+#define DMA_LLI_LEN            (32U)
+#define DMA_LLI_MSK            (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)
+#define DMA_LLI_UMSK           (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS))
+
+/* 0x10C : DMA_C0Control */
+#define DMA_C0CONTROL_OFFSET   (0x10C)
+#define DMA_TRANSFERSIZE       DMA_TRANSFERSIZE
+#define DMA_TRANSFERSIZE_POS   (0U)
+#define DMA_TRANSFERSIZE_LEN   (12U)
+#define DMA_TRANSFERSIZE_MSK   (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)
+#define DMA_TRANSFERSIZE_UMSK  (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS))
+#define DMA_SBSIZE             DMA_SBSIZE
+#define DMA_SBSIZE_POS         (12U)
+#define DMA_SBSIZE_LEN         (2U)
+#define DMA_SBSIZE_MSK         (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)
+#define DMA_SBSIZE_UMSK        (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS))
+#define DMA_DST_MIN_MODE       DMA_DST_MIN_MODE
+#define DMA_DST_MIN_MODE_POS   (14U)
+#define DMA_DST_MIN_MODE_LEN   (1U)
+#define DMA_DST_MIN_MODE_MSK   (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)
+#define DMA_DST_MIN_MODE_UMSK  (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS))
+#define DMA_DBSIZE             DMA_DBSIZE
+#define DMA_DBSIZE_POS         (15U)
+#define DMA_DBSIZE_LEN         (2U)
+#define DMA_DBSIZE_MSK         (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)
+#define DMA_DBSIZE_UMSK        (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS))
+#define DMA_DST_ADD_MODE       DMA_DST_ADD_MODE
+#define DMA_DST_ADD_MODE_POS   (17U)
+#define DMA_DST_ADD_MODE_LEN   (1U)
+#define DMA_DST_ADD_MODE_MSK   (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)
+#define DMA_DST_ADD_MODE_UMSK  (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS))
+#define DMA_SWIDTH             DMA_SWIDTH
+#define DMA_SWIDTH_POS         (18U)
+#define DMA_SWIDTH_LEN         (2U)
+#define DMA_SWIDTH_MSK         (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)
+#define DMA_SWIDTH_UMSK        (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS))
+#define DMA_DWIDTH             DMA_DWIDTH
+#define DMA_DWIDTH_POS         (21U)
+#define DMA_DWIDTH_LEN         (2U)
+#define DMA_DWIDTH_MSK         (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)
+#define DMA_DWIDTH_UMSK        (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS))
+#define DMA_FIX_CNT            DMA_FIX_CNT
+#define DMA_FIX_CNT_POS        (23U)
+#define DMA_FIX_CNT_LEN        (2U)
+#define DMA_FIX_CNT_MSK        (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)
+#define DMA_FIX_CNT_UMSK       (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS))
+#define DMA_SLARGERD           DMA_SLARGERD
+#define DMA_SLARGERD_POS       (25U)
+#define DMA_SLARGERD_LEN       (1U)
+#define DMA_SLARGERD_MSK       (((1U << DMA_SLARGERD_LEN) - 1) << DMA_SLARGERD_POS)
+#define DMA_SLARGERD_UMSK      (~(((1U << DMA_SLARGERD_LEN) - 1) << DMA_SLARGERD_POS))
+#define DMA_SI                 DMA_SI
+#define DMA_SI_POS             (26U)
+#define DMA_SI_LEN             (1U)
+#define DMA_SI_MSK             (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)
+#define DMA_SI_UMSK            (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS))
+#define DMA_DI                 DMA_DI
+#define DMA_DI_POS             (27U)
+#define DMA_DI_LEN             (1U)
+#define DMA_DI_MSK             (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)
+#define DMA_DI_UMSK            (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS))
+#define DMA_PROT               DMA_PROT
+#define DMA_PROT_POS           (28U)
+#define DMA_PROT_LEN           (3U)
+#define DMA_PROT_MSK           (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)
+#define DMA_PROT_UMSK          (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS))
+#define DMA_I                  DMA_I
+#define DMA_I_POS              (31U)
+#define DMA_I_LEN              (1U)
+#define DMA_I_MSK              (((1U << DMA_I_LEN) - 1) << DMA_I_POS)
+#define DMA_I_UMSK             (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS))
+
+/* 0x110 : DMA_C0Config */
+#define DMA_C0CONFIG_OFFSET    (0x110)
+#define DMA_E                  DMA_E
+#define DMA_E_POS              (0U)
+#define DMA_E_LEN              (1U)
+#define DMA_E_MSK              (((1U << DMA_E_LEN) - 1) << DMA_E_POS)
+#define DMA_E_UMSK             (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS))
+#define DMA_SRCPERIPHERAL      DMA_SRCPERIPHERAL
+#define DMA_SRCPERIPHERAL_POS  (1U)
+#define DMA_SRCPERIPHERAL_LEN  (5U)
+#define DMA_SRCPERIPHERAL_MSK  (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)
+#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS))
+#define DMA_DSTPERIPHERAL      DMA_DSTPERIPHERAL
+#define DMA_DSTPERIPHERAL_POS  (6U)
+#define DMA_DSTPERIPHERAL_LEN  (5U)
+#define DMA_DSTPERIPHERAL_MSK  (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)
+#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS))
+#define DMA_FLOWCNTRL          DMA_FLOWCNTRL
+#define DMA_FLOWCNTRL_POS      (11U)
+#define DMA_FLOWCNTRL_LEN      (3U)
+#define DMA_FLOWCNTRL_MSK      (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)
+#define DMA_FLOWCNTRL_UMSK     (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS))
+#define DMA_IE                 DMA_IE
+#define DMA_IE_POS             (14U)
+#define DMA_IE_LEN             (1U)
+#define DMA_IE_MSK             (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)
+#define DMA_IE_UMSK            (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS))
+#define DMA_ITC                DMA_ITC
+#define DMA_ITC_POS            (15U)
+#define DMA_ITC_LEN            (1U)
+#define DMA_ITC_MSK            (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)
+#define DMA_ITC_UMSK           (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS))
+#define DMA_L                  DMA_L
+#define DMA_L_POS              (16U)
+#define DMA_L_LEN              (1U)
+#define DMA_L_MSK              (((1U << DMA_L_LEN) - 1) << DMA_L_POS)
+#define DMA_L_UMSK             (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS))
+#define DMA_A                  DMA_A
+#define DMA_A_POS              (17U)
+#define DMA_A_LEN              (1U)
+#define DMA_A_MSK              (((1U << DMA_A_LEN) - 1) << DMA_A_POS)
+#define DMA_A_UMSK             (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS))
+#define DMA_H                  DMA_H
+#define DMA_H_POS              (18U)
+#define DMA_H_LEN              (1U)
+#define DMA_H_MSK              (((1U << DMA_H_LEN) - 1) << DMA_H_POS)
+#define DMA_H_UMSK             (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS))
+#define DMA_LLICOUNTER         DMA_LLICOUNTER
+#define DMA_LLICOUNTER_POS     (20U)
+#define DMA_LLICOUNTER_LEN     (10U)
+#define DMA_LLICOUNTER_MSK     (((1U << DMA_LLICOUNTER_LEN) - 1) << DMA_LLICOUNTER_POS)
+#define DMA_LLICOUNTER_UMSK    (~(((1U << DMA_LLICOUNTER_LEN) - 1) << DMA_LLICOUNTER_POS))
+
+/* 0x200 : DMA_C1SrcAddr */
+#define DMA_C1SRCADDR_OFFSET   (0x200)
+#define DMA_SRCADDR            DMA_SRCADDR
+#define DMA_SRCADDR_POS        (0U)
+#define DMA_SRCADDR_LEN        (32U)
+#define DMA_SRCADDR_MSK        (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)
+#define DMA_SRCADDR_UMSK       (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS))
+
+/* 0x204 : DMA_C1DstAddr */
+#define DMA_C1DSTADDR_OFFSET   (0x204)
+#define DMA_DSTADDR            DMA_DSTADDR
+#define DMA_DSTADDR_POS        (0U)
+#define DMA_DSTADDR_LEN        (32U)
+#define DMA_DSTADDR_MSK        (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)
+#define DMA_DSTADDR_UMSK       (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS))
+
+/* 0x208 : DMA_C1LLI */
+#define DMA_C1LLI_OFFSET       (0x208)
+#define DMA_LLI                DMA_LLI
+#define DMA_LLI_POS            (0U)
+#define DMA_LLI_LEN            (32U)
+#define DMA_LLI_MSK            (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)
+#define DMA_LLI_UMSK           (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS))
+
+/* 0x20C : DMA_C1Control */
+#define DMA_C1CONTROL_OFFSET   (0x20C)
+#define DMA_TRANSFERSIZE       DMA_TRANSFERSIZE
+#define DMA_TRANSFERSIZE_POS   (0U)
+#define DMA_TRANSFERSIZE_LEN   (12U)
+#define DMA_TRANSFERSIZE_MSK   (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)
+#define DMA_TRANSFERSIZE_UMSK  (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS))
+#define DMA_SBSIZE             DMA_SBSIZE
+#define DMA_SBSIZE_POS         (12U)
+#define DMA_SBSIZE_LEN         (2U)
+#define DMA_SBSIZE_MSK         (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)
+#define DMA_SBSIZE_UMSK        (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS))
+#define DMA_DST_MIN_MODE       DMA_DST_MIN_MODE
+#define DMA_DST_MIN_MODE_POS   (14U)
+#define DMA_DST_MIN_MODE_LEN   (1U)
+#define DMA_DST_MIN_MODE_MSK   (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)
+#define DMA_DST_MIN_MODE_UMSK  (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS))
+#define DMA_DBSIZE             DMA_DBSIZE
+#define DMA_DBSIZE_POS         (15U)
+#define DMA_DBSIZE_LEN         (2U)
+#define DMA_DBSIZE_MSK         (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)
+#define DMA_DBSIZE_UMSK        (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS))
+#define DMA_DST_ADD_MODE       DMA_DST_ADD_MODE
+#define DMA_DST_ADD_MODE_POS   (17U)
+#define DMA_DST_ADD_MODE_LEN   (1U)
+#define DMA_DST_ADD_MODE_MSK   (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)
+#define DMA_DST_ADD_MODE_UMSK  (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS))
+#define DMA_SWIDTH             DMA_SWIDTH
+#define DMA_SWIDTH_POS         (18U)
+#define DMA_SWIDTH_LEN         (3U)
+#define DMA_SWIDTH_MSK         (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)
+#define DMA_SWIDTH_UMSK        (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS))
+#define DMA_DWIDTH             DMA_DWIDTH
+#define DMA_DWIDTH_POS         (21U)
+#define DMA_DWIDTH_LEN         (3U)
+#define DMA_DWIDTH_MSK         (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)
+#define DMA_DWIDTH_UMSK        (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS))
+#define DMA_FIX_CNT            DMA_FIX_CNT
+#define DMA_FIX_CNT_POS        (23U)
+#define DMA_FIX_CNT_LEN        (2U)
+#define DMA_FIX_CNT_MSK        (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)
+#define DMA_FIX_CNT_UMSK       (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS))
+#define DMA_SI                 DMA_SI
+#define DMA_SI_POS             (26U)
+#define DMA_SI_LEN             (1U)
+#define DMA_SI_MSK             (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)
+#define DMA_SI_UMSK            (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS))
+#define DMA_DI                 DMA_DI
+#define DMA_DI_POS             (27U)
+#define DMA_DI_LEN             (1U)
+#define DMA_DI_MSK             (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)
+#define DMA_DI_UMSK            (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS))
+#define DMA_PROT               DMA_PROT
+#define DMA_PROT_POS           (28U)
+#define DMA_PROT_LEN           (3U)
+#define DMA_PROT_MSK           (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)
+#define DMA_PROT_UMSK          (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS))
+#define DMA_I                  DMA_I
+#define DMA_I_POS              (31U)
+#define DMA_I_LEN              (1U)
+#define DMA_I_MSK              (((1U << DMA_I_LEN) - 1) << DMA_I_POS)
+#define DMA_I_UMSK             (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS))
+
+/* 0x210 : DMA_C1Config */
+#define DMA_C1CONFIG_OFFSET    (0x210)
+#define DMA_E                  DMA_E
+#define DMA_E_POS              (0U)
+#define DMA_E_LEN              (1U)
+#define DMA_E_MSK              (((1U << DMA_E_LEN) - 1) << DMA_E_POS)
+#define DMA_E_UMSK             (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS))
+#define DMA_SRCPERIPHERAL      DMA_SRCPERIPHERAL
+#define DMA_SRCPERIPHERAL_POS  (1U)
+#define DMA_SRCPERIPHERAL_LEN  (5U)
+#define DMA_SRCPERIPHERAL_MSK  (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)
+#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS))
+#define DMA_DSTPERIPHERAL      DMA_DSTPERIPHERAL
+#define DMA_DSTPERIPHERAL_POS  (6U)
+#define DMA_DSTPERIPHERAL_LEN  (5U)
+#define DMA_DSTPERIPHERAL_MSK  (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)
+#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS))
+#define DMA_FLOWCNTRL          DMA_FLOWCNTRL
+#define DMA_FLOWCNTRL_POS      (11U)
+#define DMA_FLOWCNTRL_LEN      (3U)
+#define DMA_FLOWCNTRL_MSK      (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)
+#define DMA_FLOWCNTRL_UMSK     (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS))
+#define DMA_IE                 DMA_IE
+#define DMA_IE_POS             (14U)
+#define DMA_IE_LEN             (1U)
+#define DMA_IE_MSK             (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)
+#define DMA_IE_UMSK            (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS))
+#define DMA_ITC                DMA_ITC
+#define DMA_ITC_POS            (15U)
+#define DMA_ITC_LEN            (1U)
+#define DMA_ITC_MSK            (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)
+#define DMA_ITC_UMSK           (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS))
+#define DMA_L                  DMA_L
+#define DMA_L_POS              (16U)
+#define DMA_L_LEN              (1U)
+#define DMA_L_MSK              (((1U << DMA_L_LEN) - 1) << DMA_L_POS)
+#define DMA_L_UMSK             (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS))
+#define DMA_A                  DMA_A
+#define DMA_A_POS              (17U)
+#define DMA_A_LEN              (1U)
+#define DMA_A_MSK              (((1U << DMA_A_LEN) - 1) << DMA_A_POS)
+#define DMA_A_UMSK             (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS))
+#define DMA_H                  DMA_H
+#define DMA_H_POS              (18U)
+#define DMA_H_LEN              (1U)
+#define DMA_H_MSK              (((1U << DMA_H_LEN) - 1) << DMA_H_POS)
+#define DMA_H_UMSK             (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS))
+
+/* 0x300 : DMA_C2SrcAddr */
+#define DMA_C2SRCADDR_OFFSET   (0x300)
+#define DMA_SRCADDR            DMA_SRCADDR
+#define DMA_SRCADDR_POS        (0U)
+#define DMA_SRCADDR_LEN        (32U)
+#define DMA_SRCADDR_MSK        (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)
+#define DMA_SRCADDR_UMSK       (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS))
+
+/* 0x304 : DMA_C2DstAddr */
+#define DMA_C2DSTADDR_OFFSET   (0x304)
+#define DMA_DSTADDR            DMA_DSTADDR
+#define DMA_DSTADDR_POS        (0U)
+#define DMA_DSTADDR_LEN        (32U)
+#define DMA_DSTADDR_MSK        (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)
+#define DMA_DSTADDR_UMSK       (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS))
+
+/* 0x308 : DMA_C2LLI */
+#define DMA_C2LLI_OFFSET       (0x308)
+#define DMA_LLI                DMA_LLI
+#define DMA_LLI_POS            (0U)
+#define DMA_LLI_LEN            (32U)
+#define DMA_LLI_MSK            (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)
+#define DMA_LLI_UMSK           (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS))
+
+/* 0x30C : DMA_C2Control */
+#define DMA_C2CONTROL_OFFSET   (0x30C)
+#define DMA_TRANSFERSIZE       DMA_TRANSFERSIZE
+#define DMA_TRANSFERSIZE_POS   (0U)
+#define DMA_TRANSFERSIZE_LEN   (12U)
+#define DMA_TRANSFERSIZE_MSK   (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)
+#define DMA_TRANSFERSIZE_UMSK  (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS))
+#define DMA_SBSIZE             DMA_SBSIZE
+#define DMA_SBSIZE_POS         (12U)
+#define DMA_SBSIZE_LEN         (2U)
+#define DMA_SBSIZE_MSK         (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)
+#define DMA_SBSIZE_UMSK        (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS))
+#define DMA_DST_MIN_MODE       DMA_DST_MIN_MODE
+#define DMA_DST_MIN_MODE_POS   (14U)
+#define DMA_DST_MIN_MODE_LEN   (1U)
+#define DMA_DST_MIN_MODE_MSK   (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)
+#define DMA_DST_MIN_MODE_UMSK  (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS))
+#define DMA_DBSIZE             DMA_DBSIZE
+#define DMA_DBSIZE_POS         (15U)
+#define DMA_DBSIZE_LEN         (2U)
+#define DMA_DBSIZE_MSK         (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)
+#define DMA_DBSIZE_UMSK        (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS))
+#define DMA_DST_ADD_MODE       DMA_DST_ADD_MODE
+#define DMA_DST_ADD_MODE_POS   (17U)
+#define DMA_DST_ADD_MODE_LEN   (1U)
+#define DMA_DST_ADD_MODE_MSK   (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)
+#define DMA_DST_ADD_MODE_UMSK  (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS))
+#define DMA_SWIDTH             DMA_SWIDTH
+#define DMA_SWIDTH_POS         (18U)
+#define DMA_SWIDTH_LEN         (3U)
+#define DMA_SWIDTH_MSK         (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)
+#define DMA_SWIDTH_UMSK        (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS))
+#define DMA_DWIDTH             DMA_DWIDTH
+#define DMA_DWIDTH_POS         (21U)
+#define DMA_DWIDTH_LEN         (3U)
+#define DMA_DWIDTH_MSK         (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)
+#define DMA_DWIDTH_UMSK        (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS))
+#define DMA_FIX_CNT            DMA_FIX_CNT
+#define DMA_FIX_CNT_POS        (23U)
+#define DMA_FIX_CNT_LEN        (2U)
+#define DMA_FIX_CNT_MSK        (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)
+#define DMA_FIX_CNT_UMSK       (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS))
+#define DMA_SI                 DMA_SI
+#define DMA_SI_POS             (26U)
+#define DMA_SI_LEN             (1U)
+#define DMA_SI_MSK             (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)
+#define DMA_SI_UMSK            (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS))
+#define DMA_DI                 DMA_DI
+#define DMA_DI_POS             (27U)
+#define DMA_DI_LEN             (1U)
+#define DMA_DI_MSK             (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)
+#define DMA_DI_UMSK            (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS))
+#define DMA_PROT               DMA_PROT
+#define DMA_PROT_POS           (28U)
+#define DMA_PROT_LEN           (3U)
+#define DMA_PROT_MSK           (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)
+#define DMA_PROT_UMSK          (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS))
+#define DMA_I                  DMA_I
+#define DMA_I_POS              (31U)
+#define DMA_I_LEN              (1U)
+#define DMA_I_MSK              (((1U << DMA_I_LEN) - 1) << DMA_I_POS)
+#define DMA_I_UMSK             (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS))
+
+/* 0x310 : DMA_C2Config */
+#define DMA_C2CONFIG_OFFSET    (0x310)
+#define DMA_E                  DMA_E
+#define DMA_E_POS              (0U)
+#define DMA_E_LEN              (1U)
+#define DMA_E_MSK              (((1U << DMA_E_LEN) - 1) << DMA_E_POS)
+#define DMA_E_UMSK             (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS))
+#define DMA_SRCPERIPHERAL      DMA_SRCPERIPHERAL
+#define DMA_SRCPERIPHERAL_POS  (1U)
+#define DMA_SRCPERIPHERAL_LEN  (5U)
+#define DMA_SRCPERIPHERAL_MSK  (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)
+#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS))
+#define DMA_DSTPERIPHERAL      DMA_DSTPERIPHERAL
+#define DMA_DSTPERIPHERAL_POS  (6U)
+#define DMA_DSTPERIPHERAL_LEN  (5U)
+#define DMA_DSTPERIPHERAL_MSK  (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)
+#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS))
+#define DMA_FLOWCNTRL          DMA_FLOWCNTRL
+#define DMA_FLOWCNTRL_POS      (11U)
+#define DMA_FLOWCNTRL_LEN      (3U)
+#define DMA_FLOWCNTRL_MSK      (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)
+#define DMA_FLOWCNTRL_UMSK     (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS))
+#define DMA_IE                 DMA_IE
+#define DMA_IE_POS             (14U)
+#define DMA_IE_LEN             (1U)
+#define DMA_IE_MSK             (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)
+#define DMA_IE_UMSK            (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS))
+#define DMA_ITC                DMA_ITC
+#define DMA_ITC_POS            (15U)
+#define DMA_ITC_LEN            (1U)
+#define DMA_ITC_MSK            (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)
+#define DMA_ITC_UMSK           (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS))
+#define DMA_L                  DMA_L
+#define DMA_L_POS              (16U)
+#define DMA_L_LEN              (1U)
+#define DMA_L_MSK              (((1U << DMA_L_LEN) - 1) << DMA_L_POS)
+#define DMA_L_UMSK             (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS))
+#define DMA_A                  DMA_A
+#define DMA_A_POS              (17U)
+#define DMA_A_LEN              (1U)
+#define DMA_A_MSK              (((1U << DMA_A_LEN) - 1) << DMA_A_POS)
+#define DMA_A_UMSK             (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS))
+#define DMA_H                  DMA_H
+#define DMA_H_POS              (18U)
+#define DMA_H_LEN              (1U)
+#define DMA_H_MSK              (((1U << DMA_H_LEN) - 1) << DMA_H_POS)
+#define DMA_H_UMSK             (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS))
+
+/* 0x400 : DMA_C3SrcAddr */
+#define DMA_C3SRCADDR_OFFSET   (0x400)
+#define DMA_SRCADDR            DMA_SRCADDR
+#define DMA_SRCADDR_POS        (0U)
+#define DMA_SRCADDR_LEN        (32U)
+#define DMA_SRCADDR_MSK        (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)
+#define DMA_SRCADDR_UMSK       (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS))
+
+/* 0x404 : DMA_C3DstAddr */
+#define DMA_C3DSTADDR_OFFSET   (0x404)
+#define DMA_DSTADDR            DMA_DSTADDR
+#define DMA_DSTADDR_POS        (0U)
+#define DMA_DSTADDR_LEN        (32U)
+#define DMA_DSTADDR_MSK        (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)
+#define DMA_DSTADDR_UMSK       (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS))
+
+/* 0x408 : DMA_C3LLI */
+#define DMA_C3LLI_OFFSET       (0x408)
+#define DMA_LLI_POS            (0U)
+#define DMA_LLI_LEN            (32U)
+#define DMA_LLI_MSK            (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)
+#define DMA_LLI_UMSK           (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS))
+
+/* 0x40C : DMA_C3Control */
+#define DMA_C3CONTROL_OFFSET   (0x40C)
+#define DMA_TRANSFERSIZE       DMA_TRANSFERSIZE
+#define DMA_TRANSFERSIZE_POS   (0U)
+#define DMA_TRANSFERSIZE_LEN   (12U)
+#define DMA_TRANSFERSIZE_MSK   (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)
+#define DMA_TRANSFERSIZE_UMSK  (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS))
+#define DMA_SBSIZE             DMA_SBSIZE
+#define DMA_SBSIZE_POS         (12U)
+#define DMA_SBSIZE_LEN         (2U)
+#define DMA_SBSIZE_MSK         (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)
+#define DMA_SBSIZE_UMSK        (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS))
+#define DMA_DST_MIN_MODE       DMA_DST_MIN_MODE
+#define DMA_DST_MIN_MODE_POS   (14U)
+#define DMA_DST_MIN_MODE_LEN   (1U)
+#define DMA_DST_MIN_MODE_MSK   (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)
+#define DMA_DST_MIN_MODE_UMSK  (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS))
+#define DMA_DBSIZE             DMA_DBSIZE
+#define DMA_DBSIZE_POS         (15U)
+#define DMA_DBSIZE_LEN         (2U)
+#define DMA_DBSIZE_MSK         (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)
+#define DMA_DBSIZE_UMSK        (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS))
+#define DMA_DST_ADD_MODE       DMA_DST_ADD_MODE
+#define DMA_DST_ADD_MODE_POS   (17U)
+#define DMA_DST_ADD_MODE_LEN   (1U)
+#define DMA_DST_ADD_MODE_MSK   (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)
+#define DMA_DST_ADD_MODE_UMSK  (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS))
+#define DMA_SWIDTH             DMA_SWIDTH
+#define DMA_SWIDTH_POS         (18U)
+#define DMA_SWIDTH_LEN         (3U)
+#define DMA_SWIDTH_MSK         (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)
+#define DMA_SWIDTH_UMSK        (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS))
+#define DMA_DWIDTH             DMA_DWIDTH
+#define DMA_DWIDTH_POS         (21U)
+#define DMA_DWIDTH_LEN         (3U)
+#define DMA_DWIDTH_MSK         (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)
+#define DMA_DWIDTH_UMSK        (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS))
+#define DMA_FIX_CNT            DMA_FIX_CNT
+#define DMA_FIX_CNT_POS        (23U)
+#define DMA_FIX_CNT_LEN        (2U)
+#define DMA_FIX_CNT_MSK        (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)
+#define DMA_FIX_CNT_UMSK       (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS))
+#define DMA_SI                 DMA_SI
+#define DMA_SI_POS             (26U)
+#define DMA_SI_LEN             (1U)
+#define DMA_SI_MSK             (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)
+#define DMA_SI_UMSK            (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS))
+#define DMA_DI                 DMA_DI
+#define DMA_DI_POS             (27U)
+#define DMA_DI_LEN             (1U)
+#define DMA_DI_MSK             (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)
+#define DMA_DI_UMSK            (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS))
+#define DMA_PROT               DMA_PROT
+#define DMA_PROT_POS           (28U)
+#define DMA_PROT_LEN           (3U)
+#define DMA_PROT_MSK           (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)
+#define DMA_PROT_UMSK          (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS))
+#define DMA_I                  DMA_I
+#define DMA_I_POS              (31U)
+#define DMA_I_LEN              (1U)
+#define DMA_I_MSK              (((1U << DMA_I_LEN) - 1) << DMA_I_POS)
+#define DMA_I_UMSK             (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS))
+
+/* 0x410 : DMA_C3Config */
+#define DMA_C3CONFIG_OFFSET    (0x410)
+#define DMA_E                  DMA_E
+#define DMA_E_POS              (0U)
+#define DMA_E_LEN              (1U)
+#define DMA_E_MSK              (((1U << DMA_E_LEN) - 1) << DMA_E_POS)
+#define DMA_E_UMSK             (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS))
+#define DMA_SRCPERIPHERAL      DMA_SRCPERIPHERAL
+#define DMA_SRCPERIPHERAL_POS  (1U)
+#define DMA_SRCPERIPHERAL_LEN  (5U)
+#define DMA_SRCPERIPHERAL_MSK  (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)
+#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS))
+#define DMA_DSTPERIPHERAL      DMA_DSTPERIPHERAL
+#define DMA_DSTPERIPHERAL_POS  (6U)
+#define DMA_DSTPERIPHERAL_LEN  (5U)
+#define DMA_DSTPERIPHERAL_MSK  (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)
+#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS))
+#define DMA_FLOWCNTRL          DMA_FLOWCNTRL
+#define DMA_FLOWCNTRL_POS      (11U)
+#define DMA_FLOWCNTRL_LEN      (3U)
+#define DMA_FLOWCNTRL_MSK      (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)
+#define DMA_FLOWCNTRL_UMSK     (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS))
+#define DMA_IE                 DMA_IE
+#define DMA_IE_POS             (14U)
+#define DMA_IE_LEN             (1U)
+#define DMA_IE_MSK             (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)
+#define DMA_IE_UMSK            (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS))
+#define DMA_ITC                DMA_ITC
+#define DMA_ITC_POS            (15U)
+#define DMA_ITC_LEN            (1U)
+#define DMA_ITC_MSK            (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)
+#define DMA_ITC_UMSK           (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS))
+#define DMA_L                  DMA_L
+#define DMA_L_POS              (16U)
+#define DMA_L_LEN              (1U)
+#define DMA_L_MSK              (((1U << DMA_L_LEN) - 1) << DMA_L_POS)
+#define DMA_L_UMSK             (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS))
+#define DMA_A                  DMA_A
+#define DMA_A_POS              (17U)
+#define DMA_A_LEN              (1U)
+#define DMA_A_MSK              (((1U << DMA_A_LEN) - 1) << DMA_A_POS)
+#define DMA_A_UMSK             (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS))
+#define DMA_H                  DMA_H
+#define DMA_H_POS              (18U)
+#define DMA_H_LEN              (1U)
+#define DMA_H_MSK              (((1U << DMA_H_LEN) - 1) << DMA_H_POS)
+#define DMA_H_UMSK             (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS))
+
+/* 0x500 : DMA_C4SrcAddr */
+#define DMA_C4SRCADDR_OFFSET   (0x500)
+#define DMA_SRCADDR            DMA_SRCADDR
+#define DMA_SRCADDR_POS        (0U)
+#define DMA_SRCADDR_LEN        (32U)
+#define DMA_SRCADDR_MSK        (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)
+#define DMA_SRCADDR_UMSK       (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS))
+
+/* 0x504 : DMA_C4DstAddr */
+#define DMA_C4DSTADDR_OFFSET   (0x504)
+#define DMA_DSTADDR            DMA_DSTADDR
+#define DMA_DSTADDR_POS        (0U)
+#define DMA_DSTADDR_LEN        (32U)
+#define DMA_DSTADDR_MSK        (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)
+#define DMA_DSTADDR_UMSK       (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS))
+
+/* 0x508 : DMA_C4LLI */
+#define DMA_C4LLI_OFFSET       (0x508)
+#define DMA_LLI_POS            (0U)
+#define DMA_LLI_LEN            (32U)
+#define DMA_LLI_MSK            (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)
+#define DMA_LLI_UMSK           (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS))
+
+/* 0x50C : DMA_C4Control */
+#define DMA_C4CONTROL_OFFSET   (0x50C)
+#define DMA_TRANSFERSIZE       DMA_TRANSFERSIZE
+#define DMA_TRANSFERSIZE_POS   (0U)
+#define DMA_TRANSFERSIZE_LEN   (12U)
+#define DMA_TRANSFERSIZE_MSK   (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)
+#define DMA_TRANSFERSIZE_UMSK  (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS))
+#define DMA_SBSIZE             DMA_SBSIZE
+#define DMA_SBSIZE_POS         (12U)
+#define DMA_SBSIZE_LEN         (2U)
+#define DMA_SBSIZE_MSK         (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)
+#define DMA_SBSIZE_UMSK        (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS))
+#define DMA_DST_MIN_MODE       DMA_DST_MIN_MODE
+#define DMA_DST_MIN_MODE_POS   (14U)
+#define DMA_DST_MIN_MODE_LEN   (1U)
+#define DMA_DST_MIN_MODE_MSK   (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)
+#define DMA_DST_MIN_MODE_UMSK  (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS))
+#define DMA_DBSIZE             DMA_DBSIZE
+#define DMA_DBSIZE_POS         (15U)
+#define DMA_DBSIZE_LEN         (2U)
+#define DMA_DBSIZE_MSK         (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)
+#define DMA_DBSIZE_UMSK        (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS))
+#define DMA_DST_ADD_MODE       DMA_DST_ADD_MODE
+#define DMA_DST_ADD_MODE_POS   (17U)
+#define DMA_DST_ADD_MODE_LEN   (1U)
+#define DMA_DST_ADD_MODE_MSK   (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)
+#define DMA_DST_ADD_MODE_UMSK  (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS))
+#define DMA_SWIDTH             DMA_SWIDTH
+#define DMA_SWIDTH_POS         (18U)
+#define DMA_SWIDTH_LEN         (3U)
+#define DMA_SWIDTH_MSK         (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)
+#define DMA_SWIDTH_UMSK        (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS))
+#define DMA_DWIDTH             DMA_DWIDTH
+#define DMA_DWIDTH_POS         (21U)
+#define DMA_DWIDTH_LEN         (3U)
+#define DMA_DWIDTH_MSK         (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)
+#define DMA_DWIDTH_UMSK        (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS))
+#define DMA_FIX_CNT            DMA_FIX_CNT
+#define DMA_FIX_CNT_POS        (23U)
+#define DMA_FIX_CNT_LEN        (2U)
+#define DMA_FIX_CNT_MSK        (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)
+#define DMA_FIX_CNT_UMSK       (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS))
+#define DMA_SI                 DMA_SI
+#define DMA_SI_POS             (26U)
+#define DMA_SI_LEN             (1U)
+#define DMA_SI_MSK             (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)
+#define DMA_SI_UMSK            (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS))
+#define DMA_DI                 DMA_DI
+#define DMA_DI_POS             (27U)
+#define DMA_DI_LEN             (1U)
+#define DMA_DI_MSK             (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)
+#define DMA_DI_UMSK            (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS))
+#define DMA_PROT               DMA_PROT
+#define DMA_PROT_POS           (28U)
+#define DMA_PROT_LEN           (3U)
+#define DMA_PROT_MSK           (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)
+#define DMA_PROT_UMSK          (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS))
+#define DMA_I                  DMA_I
+#define DMA_I_POS              (31U)
+#define DMA_I_LEN              (1U)
+#define DMA_I_MSK              (((1U << DMA_I_LEN) - 1) << DMA_I_POS)
+#define DMA_I_UMSK             (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS))
+
+/* 0x510 : DMA_C4Config */
+#define DMA_C4CONFIG_OFFSET    (0x510)
+#define DMA_E                  DMA_E
+#define DMA_E_POS              (0U)
+#define DMA_E_LEN              (1U)
+#define DMA_E_MSK              (((1U << DMA_E_LEN) - 1) << DMA_E_POS)
+#define DMA_E_UMSK             (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS))
+#define DMA_SRCPERIPHERAL      DMA_SRCPERIPHERAL
+#define DMA_SRCPERIPHERAL_POS  (1U)
+#define DMA_SRCPERIPHERAL_LEN  (5U)
+#define DMA_SRCPERIPHERAL_MSK  (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)
+#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS))
+#define DMA_DSTPERIPHERAL      DMA_DSTPERIPHERAL
+#define DMA_DSTPERIPHERAL_POS  (6U)
+#define DMA_DSTPERIPHERAL_LEN  (5U)
+#define DMA_DSTPERIPHERAL_MSK  (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)
+#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS))
+#define DMA_FLOWCNTRL          DMA_FLOWCNTRL
+#define DMA_FLOWCNTRL_POS      (11U)
+#define DMA_FLOWCNTRL_LEN      (3U)
+#define DMA_FLOWCNTRL_MSK      (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)
+#define DMA_FLOWCNTRL_UMSK     (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS))
+#define DMA_IE                 DMA_IE
+#define DMA_IE_POS             (14U)
+#define DMA_IE_LEN             (1U)
+#define DMA_IE_MSK             (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)
+#define DMA_IE_UMSK            (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS))
+#define DMA_ITC                DMA_ITC
+#define DMA_ITC_POS            (15U)
+#define DMA_ITC_LEN            (1U)
+#define DMA_ITC_MSK            (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)
+#define DMA_ITC_UMSK           (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS))
+#define DMA_L                  DMA_L
+#define DMA_L_POS              (16U)
+#define DMA_L_LEN              (1U)
+#define DMA_L_MSK              (((1U << DMA_L_LEN) - 1) << DMA_L_POS)
+#define DMA_L_UMSK             (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS))
+#define DMA_A                  DMA_A
+#define DMA_A_POS              (17U)
+#define DMA_A_LEN              (1U)
+#define DMA_A_MSK              (((1U << DMA_A_LEN) - 1) << DMA_A_POS)
+#define DMA_A_UMSK             (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS))
+#define DMA_H                  DMA_H
+#define DMA_H_POS              (18U)
+#define DMA_H_LEN              (1U)
+#define DMA_H_MSK              (((1U << DMA_H_LEN) - 1) << DMA_H_POS)
+#define DMA_H_UMSK             (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS))
+
+/* 0x600 : DMA_C5SrcAddr */
+#define DMA_C5SRCADDR_OFFSET   (0x600)
+#define DMA_SRCADDR            DMA_SRCADDR
+#define DMA_SRCADDR_POS        (0U)
+#define DMA_SRCADDR_LEN        (32U)
+#define DMA_SRCADDR_MSK        (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)
+#define DMA_SRCADDR_UMSK       (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS))
+
+/* 0x604 : DMA_C5DstAddr */
+#define DMA_C5DSTADDR_OFFSET   (0x604)
+#define DMA_DSTADDR            DMA_DSTADDR
+#define DMA_DSTADDR_POS        (0U)
+#define DMA_DSTADDR_LEN        (32U)
+#define DMA_DSTADDR_MSK        (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)
+#define DMA_DSTADDR_UMSK       (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS))
+
+/* 0x608 : DMA_C5LLI */
+#define DMA_C5LLI_OFFSET       (0x608)
+#define DMA_LLI_POS            (0U)
+#define DMA_LLI_LEN            (32U)
+#define DMA_LLI_MSK            (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)
+#define DMA_LLI_UMSK           (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS))
+
+/* 0x60C : DMA_C5Control */
+#define DMA_C5CONTROL_OFFSET   (0x60C)
+#define DMA_TRANSFERSIZE       DMA_TRANSFERSIZE
+#define DMA_TRANSFERSIZE_POS   (0U)
+#define DMA_TRANSFERSIZE_LEN   (12U)
+#define DMA_TRANSFERSIZE_MSK   (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)
+#define DMA_TRANSFERSIZE_UMSK  (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS))
+#define DMA_SBSIZE             DMA_SBSIZE
+#define DMA_SBSIZE_POS         (12U)
+#define DMA_SBSIZE_LEN         (2U)
+#define DMA_SBSIZE_MSK         (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)
+#define DMA_SBSIZE_UMSK        (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS))
+#define DMA_DST_MIN_MODE       DMA_DST_MIN_MODE
+#define DMA_DST_MIN_MODE_POS   (14U)
+#define DMA_DST_MIN_MODE_LEN   (1U)
+#define DMA_DST_MIN_MODE_MSK   (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)
+#define DMA_DST_MIN_MODE_UMSK  (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS))
+#define DMA_DBSIZE             DMA_DBSIZE
+#define DMA_DBSIZE_POS         (15U)
+#define DMA_DBSIZE_LEN         (2U)
+#define DMA_DBSIZE_MSK         (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)
+#define DMA_DBSIZE_UMSK        (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS))
+#define DMA_DST_ADD_MODE       DMA_DST_ADD_MODE
+#define DMA_DST_ADD_MODE_POS   (17U)
+#define DMA_DST_ADD_MODE_LEN   (1U)
+#define DMA_DST_ADD_MODE_MSK   (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)
+#define DMA_DST_ADD_MODE_UMSK  (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS))
+#define DMA_SWIDTH             DMA_SWIDTH
+#define DMA_SWIDTH_POS         (18U)
+#define DMA_SWIDTH_LEN         (3U)
+#define DMA_SWIDTH_MSK         (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)
+#define DMA_SWIDTH_UMSK        (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS))
+#define DMA_DWIDTH             DMA_DWIDTH
+#define DMA_DWIDTH_POS         (21U)
+#define DMA_DWIDTH_LEN         (3U)
+#define DMA_DWIDTH_MSK         (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)
+#define DMA_DWIDTH_UMSK        (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS))
+#define DMA_FIX_CNT            DMA_FIX_CNT
+#define DMA_FIX_CNT_POS        (23U)
+#define DMA_FIX_CNT_LEN        (2U)
+#define DMA_FIX_CNT_MSK        (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)
+#define DMA_FIX_CNT_UMSK       (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS))
+#define DMA_SI                 DMA_SI
+#define DMA_SI_POS             (26U)
+#define DMA_SI_LEN             (1U)
+#define DMA_SI_MSK             (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)
+#define DMA_SI_UMSK            (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS))
+#define DMA_DI                 DMA_DI
+#define DMA_DI_POS             (27U)
+#define DMA_DI_LEN             (1U)
+#define DMA_DI_MSK             (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)
+#define DMA_DI_UMSK            (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS))
+#define DMA_PROT               DMA_PROT
+#define DMA_PROT_POS           (28U)
+#define DMA_PROT_LEN           (3U)
+#define DMA_PROT_MSK           (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)
+#define DMA_PROT_UMSK          (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS))
+#define DMA_I                  DMA_I
+#define DMA_I_POS              (31U)
+#define DMA_I_LEN              (1U)
+#define DMA_I_MSK              (((1U << DMA_I_LEN) - 1) << DMA_I_POS)
+#define DMA_I_UMSK             (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS))
+
+/* 0x610 : DMA_C5Config */
+#define DMA_C5CONFIG_OFFSET    (0x610)
+#define DMA_E                  DMA_E
+#define DMA_E_POS              (0U)
+#define DMA_E_LEN              (1U)
+#define DMA_E_MSK              (((1U << DMA_E_LEN) - 1) << DMA_E_POS)
+#define DMA_E_UMSK             (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS))
+#define DMA_SRCPERIPHERAL      DMA_SRCPERIPHERAL
+#define DMA_SRCPERIPHERAL_POS  (1U)
+#define DMA_SRCPERIPHERAL_LEN  (5U)
+#define DMA_SRCPERIPHERAL_MSK  (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)
+#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS))
+#define DMA_DSTPERIPHERAL      DMA_DSTPERIPHERAL
+#define DMA_DSTPERIPHERAL_POS  (6U)
+#define DMA_DSTPERIPHERAL_LEN  (5U)
+#define DMA_DSTPERIPHERAL_MSK  (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)
+#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS))
+#define DMA_FLOWCNTRL          DMA_FLOWCNTRL
+#define DMA_FLOWCNTRL_POS      (11U)
+#define DMA_FLOWCNTRL_LEN      (3U)
+#define DMA_FLOWCNTRL_MSK      (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)
+#define DMA_FLOWCNTRL_UMSK     (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS))
+#define DMA_IE                 DMA_IE
+#define DMA_IE_POS             (14U)
+#define DMA_IE_LEN             (1U)
+#define DMA_IE_MSK             (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)
+#define DMA_IE_UMSK            (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS))
+#define DMA_ITC                DMA_ITC
+#define DMA_ITC_POS            (15U)
+#define DMA_ITC_LEN            (1U)
+#define DMA_ITC_MSK            (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)
+#define DMA_ITC_UMSK           (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS))
+#define DMA_L                  DMA_L
+#define DMA_L_POS              (16U)
+#define DMA_L_LEN              (1U)
+#define DMA_L_MSK              (((1U << DMA_L_LEN) - 1) << DMA_L_POS)
+#define DMA_L_UMSK             (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS))
+#define DMA_A                  DMA_A
+#define DMA_A_POS              (17U)
+#define DMA_A_LEN              (1U)
+#define DMA_A_MSK              (((1U << DMA_A_LEN) - 1) << DMA_A_POS)
+#define DMA_A_UMSK             (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS))
+#define DMA_H                  DMA_H
+#define DMA_H_POS              (18U)
+#define DMA_H_LEN              (1U)
+#define DMA_H_MSK              (((1U << DMA_H_LEN) - 1) << DMA_H_POS)
+#define DMA_H_UMSK             (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS))
+
+/* 0x700 : DMA_C6SrcAddr */
+#define DMA_C6SRCADDR_OFFSET   (0x700)
+#define DMA_SRCADDR            DMA_SRCADDR
+#define DMA_SRCADDR_POS        (0U)
+#define DMA_SRCADDR_LEN        (32U)
+#define DMA_SRCADDR_MSK        (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)
+#define DMA_SRCADDR_UMSK       (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS))
+
+/* 0x704 : DMA_C6DstAddr */
+#define DMA_C6DSTADDR_OFFSET   (0x704)
+#define DMA_DSTADDR            DMA_DSTADDR
+#define DMA_DSTADDR_POS        (0U)
+#define DMA_DSTADDR_LEN        (32U)
+#define DMA_DSTADDR_MSK        (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)
+#define DMA_DSTADDR_UMSK       (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS))
+
+/* 0x708 : DMA_C6LLI */
+#define DMA_C6LLI_OFFSET       (0x708)
+#define DMA_LLI_POS            (0U)
+#define DMA_LLI_LEN            (32U)
+#define DMA_LLI_MSK            (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)
+#define DMA_LLI_UMSK           (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS))
+
+/* 0x70C : DMA_C6Control */
+#define DMA_C6CONTROL_OFFSET   (0x70C)
+#define DMA_TRANSFERSIZE       DMA_TRANSFERSIZE
+#define DMA_TRANSFERSIZE_POS   (0U)
+#define DMA_TRANSFERSIZE_LEN   (12U)
+#define DMA_TRANSFERSIZE_MSK   (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)
+#define DMA_TRANSFERSIZE_UMSK  (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS))
+#define DMA_SBSIZE             DMA_SBSIZE
+#define DMA_SBSIZE_POS         (12U)
+#define DMA_SBSIZE_LEN         (2U)
+#define DMA_SBSIZE_MSK         (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)
+#define DMA_SBSIZE_UMSK        (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS))
+#define DMA_DST_MIN_MODE       DMA_DST_MIN_MODE
+#define DMA_DST_MIN_MODE_POS   (14U)
+#define DMA_DST_MIN_MODE_LEN   (1U)
+#define DMA_DST_MIN_MODE_MSK   (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)
+#define DMA_DST_MIN_MODE_UMSK  (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS))
+#define DMA_DBSIZE             DMA_DBSIZE
+#define DMA_DBSIZE_POS         (15U)
+#define DMA_DBSIZE_LEN         (2U)
+#define DMA_DBSIZE_MSK         (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)
+#define DMA_DBSIZE_UMSK        (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS))
+#define DMA_DST_ADD_MODE       DMA_DST_ADD_MODE
+#define DMA_DST_ADD_MODE_POS   (17U)
+#define DMA_DST_ADD_MODE_LEN   (1U)
+#define DMA_DST_ADD_MODE_MSK   (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)
+#define DMA_DST_ADD_MODE_UMSK  (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS))
+#define DMA_SWIDTH             DMA_SWIDTH
+#define DMA_SWIDTH_POS         (18U)
+#define DMA_SWIDTH_LEN         (3U)
+#define DMA_SWIDTH_MSK         (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)
+#define DMA_SWIDTH_UMSK        (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS))
+#define DMA_DWIDTH             DMA_DWIDTH
+#define DMA_DWIDTH_POS         (21U)
+#define DMA_DWIDTH_LEN         (3U)
+#define DMA_DWIDTH_MSK         (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)
+#define DMA_DWIDTH_UMSK        (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS))
+#define DMA_FIX_CNT            DMA_FIX_CNT
+#define DMA_FIX_CNT_POS        (23U)
+#define DMA_FIX_CNT_LEN        (2U)
+#define DMA_FIX_CNT_MSK        (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)
+#define DMA_FIX_CNT_UMSK       (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS))
+#define DMA_SI                 DMA_SI
+#define DMA_SI_POS             (26U)
+#define DMA_SI_LEN             (1U)
+#define DMA_SI_MSK             (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)
+#define DMA_SI_UMSK            (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS))
+#define DMA_DI                 DMA_DI
+#define DMA_DI_POS             (27U)
+#define DMA_DI_LEN             (1U)
+#define DMA_DI_MSK             (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)
+#define DMA_DI_UMSK            (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS))
+#define DMA_PROT               DMA_PROT
+#define DMA_PROT_POS           (28U)
+#define DMA_PROT_LEN           (3U)
+#define DMA_PROT_MSK           (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)
+#define DMA_PROT_UMSK          (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS))
+#define DMA_I                  DMA_I
+#define DMA_I_POS              (31U)
+#define DMA_I_LEN              (1U)
+#define DMA_I_MSK              (((1U << DMA_I_LEN) - 1) << DMA_I_POS)
+#define DMA_I_UMSK             (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS))
+
+/* 0x710 : DMA_C6Config */
+#define DMA_C6CONFIG_OFFSET    (0x710)
+#define DMA_E                  DMA_E
+#define DMA_E_POS              (0U)
+#define DMA_E_LEN              (1U)
+#define DMA_E_MSK              (((1U << DMA_E_LEN) - 1) << DMA_E_POS)
+#define DMA_E_UMSK             (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS))
+#define DMA_SRCPERIPHERAL      DMA_SRCPERIPHERAL
+#define DMA_SRCPERIPHERAL_POS  (1U)
+#define DMA_SRCPERIPHERAL_LEN  (5U)
+#define DMA_SRCPERIPHERAL_MSK  (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)
+#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS))
+#define DMA_DSTPERIPHERAL      DMA_DSTPERIPHERAL
+#define DMA_DSTPERIPHERAL_POS  (6U)
+#define DMA_DSTPERIPHERAL_LEN  (5U)
+#define DMA_DSTPERIPHERAL_MSK  (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)
+#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS))
+#define DMA_FLOWCNTRL          DMA_FLOWCNTRL
+#define DMA_FLOWCNTRL_POS      (11U)
+#define DMA_FLOWCNTRL_LEN      (3U)
+#define DMA_FLOWCNTRL_MSK      (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)
+#define DMA_FLOWCNTRL_UMSK     (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS))
+#define DMA_IE                 DMA_IE
+#define DMA_IE_POS             (14U)
+#define DMA_IE_LEN             (1U)
+#define DMA_IE_MSK             (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)
+#define DMA_IE_UMSK            (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS))
+#define DMA_ITC                DMA_ITC
+#define DMA_ITC_POS            (15U)
+#define DMA_ITC_LEN            (1U)
+#define DMA_ITC_MSK            (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)
+#define DMA_ITC_UMSK           (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS))
+#define DMA_L                  DMA_L
+#define DMA_L_POS              (16U)
+#define DMA_L_LEN              (1U)
+#define DMA_L_MSK              (((1U << DMA_L_LEN) - 1) << DMA_L_POS)
+#define DMA_L_UMSK             (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS))
+#define DMA_A                  DMA_A
+#define DMA_A_POS              (17U)
+#define DMA_A_LEN              (1U)
+#define DMA_A_MSK              (((1U << DMA_A_LEN) - 1) << DMA_A_POS)
+#define DMA_A_UMSK             (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS))
+#define DMA_H                  DMA_H
+#define DMA_H_POS              (18U)
+#define DMA_H_LEN              (1U)
+#define DMA_H_MSK              (((1U << DMA_H_LEN) - 1) << DMA_H_POS)
+#define DMA_H_UMSK             (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS))
+
+/* 0x800 : DMA_C7SrcAddr */
+#define DMA_C7SRCADDR_OFFSET   (0x800)
+#define DMA_SRCADDR            DMA_SRCADDR
+#define DMA_SRCADDR_POS        (0U)
+#define DMA_SRCADDR_LEN        (32U)
+#define DMA_SRCADDR_MSK        (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)
+#define DMA_SRCADDR_UMSK       (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS))
+
+/* 0x804 : DMA_C7DstAddr */
+#define DMA_C7DSTADDR_OFFSET   (0x804)
+#define DMA_DSTADDR            DMA_DSTADDR
+#define DMA_DSTADDR_POS        (0U)
+#define DMA_DSTADDR_LEN        (32U)
+#define DMA_DSTADDR_MSK        (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)
+#define DMA_DSTADDR_UMSK       (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS))
+
+/* 0x808 : DMA_C7LLI */
+#define DMA_C7LLI_OFFSET       (0x808)
+#define DMA_LLI_POS            (0U)
+#define DMA_LLI_LEN            (32U)
+#define DMA_LLI_MSK            (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)
+#define DMA_LLI_UMSK           (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS))
+
+/* 0x80C : DMA_C7Control */
+#define DMA_C7CONTROL_OFFSET   (0x80C)
+#define DMA_TRANSFERSIZE       DMA_TRANSFERSIZE
+#define DMA_TRANSFERSIZE_POS   (0U)
+#define DMA_TRANSFERSIZE_LEN   (12U)
+#define DMA_TRANSFERSIZE_MSK   (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)
+#define DMA_TRANSFERSIZE_UMSK  (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS))
+#define DMA_SBSIZE             DMA_SBSIZE
+#define DMA_SBSIZE_POS         (12U)
+#define DMA_SBSIZE_LEN         (2U)
+#define DMA_SBSIZE_MSK         (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)
+#define DMA_SBSIZE_UMSK        (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS))
+#define DMA_DST_MIN_MODE       DMA_DST_MIN_MODE
+#define DMA_DST_MIN_MODE_POS   (14U)
+#define DMA_DST_MIN_MODE_LEN   (1U)
+#define DMA_DST_MIN_MODE_MSK   (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)
+#define DMA_DST_MIN_MODE_UMSK  (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS))
+#define DMA_DBSIZE             DMA_DBSIZE
+#define DMA_DBSIZE_POS         (15U)
+#define DMA_DBSIZE_LEN         (2U)
+#define DMA_DBSIZE_MSK         (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)
+#define DMA_DBSIZE_UMSK        (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS))
+#define DMA_DST_ADD_MODE       DMA_DST_ADD_MODE
+#define DMA_DST_ADD_MODE_POS   (17U)
+#define DMA_DST_ADD_MODE_LEN   (1U)
+#define DMA_DST_ADD_MODE_MSK   (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)
+#define DMA_DST_ADD_MODE_UMSK  (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS))
+#define DMA_SWIDTH             DMA_SWIDTH
+#define DMA_SWIDTH_POS         (18U)
+#define DMA_SWIDTH_LEN         (3U)
+#define DMA_SWIDTH_MSK         (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)
+#define DMA_SWIDTH_UMSK        (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS))
+#define DMA_DWIDTH             DMA_DWIDTH
+#define DMA_DWIDTH_POS         (21U)
+#define DMA_DWIDTH_LEN         (3U)
+#define DMA_DWIDTH_MSK         (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)
+#define DMA_DWIDTH_UMSK        (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS))
+#define DMA_FIX_CNT            DMA_FIX_CNT
+#define DMA_FIX_CNT_POS        (23U)
+#define DMA_FIX_CNT_LEN        (2U)
+#define DMA_FIX_CNT_MSK        (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)
+#define DMA_FIX_CNT_UMSK       (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS))
+#define DMA_SI                 DMA_SI
+#define DMA_SI_POS             (26U)
+#define DMA_SI_LEN             (1U)
+#define DMA_SI_MSK             (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)
+#define DMA_SI_UMSK            (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS))
+#define DMA_DI                 DMA_DI
+#define DMA_DI_POS             (27U)
+#define DMA_DI_LEN             (1U)
+#define DMA_DI_MSK             (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)
+#define DMA_DI_UMSK            (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS))
+#define DMA_PROT               DMA_PROT
+#define DMA_PROT_POS           (28U)
+#define DMA_PROT_LEN           (3U)
+#define DMA_PROT_MSK           (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)
+#define DMA_PROT_UMSK          (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS))
+#define DMA_I                  DMA_I
+#define DMA_I_POS              (31U)
+#define DMA_I_LEN              (1U)
+#define DMA_I_MSK              (((1U << DMA_I_LEN) - 1) << DMA_I_POS)
+#define DMA_I_UMSK             (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS))
+
+/* 0x810 : DMA_C7Config */
+#define DMA_C7CONFIG_OFFSET    (0x810)
+#define DMA_E                  DMA_E
+#define DMA_E_POS              (0U)
+#define DMA_E_LEN              (1U)
+#define DMA_E_MSK              (((1U << DMA_E_LEN) - 1) << DMA_E_POS)
+#define DMA_E_UMSK             (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS))
+#define DMA_SRCPERIPHERAL      DMA_SRCPERIPHERAL
+#define DMA_SRCPERIPHERAL_POS  (1U)
+#define DMA_SRCPERIPHERAL_LEN  (5U)
+#define DMA_SRCPERIPHERAL_MSK  (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)
+#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS))
+#define DMA_DSTPERIPHERAL      DMA_DSTPERIPHERAL
+#define DMA_DSTPERIPHERAL_POS  (6U)
+#define DMA_DSTPERIPHERAL_LEN  (5U)
+#define DMA_DSTPERIPHERAL_MSK  (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)
+#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS))
+#define DMA_FLOWCNTRL          DMA_FLOWCNTRL
+#define DMA_FLOWCNTRL_POS      (11U)
+#define DMA_FLOWCNTRL_LEN      (3U)
+#define DMA_FLOWCNTRL_MSK      (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)
+#define DMA_FLOWCNTRL_UMSK     (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS))
+#define DMA_IE                 DMA_IE
+#define DMA_IE_POS             (14U)
+#define DMA_IE_LEN             (1U)
+#define DMA_IE_MSK             (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)
+#define DMA_IE_UMSK            (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS))
+#define DMA_ITC                DMA_ITC
+#define DMA_ITC_POS            (15U)
+#define DMA_ITC_LEN            (1U)
+#define DMA_ITC_MSK            (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)
+#define DMA_ITC_UMSK           (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS))
+#define DMA_L                  DMA_L
+#define DMA_L_POS              (16U)
+#define DMA_L_LEN              (1U)
+#define DMA_L_MSK              (((1U << DMA_L_LEN) - 1) << DMA_L_POS)
+#define DMA_L_UMSK             (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS))
+#define DMA_A                  DMA_A
+#define DMA_A_POS              (17U)
+#define DMA_A_LEN              (1U)
+#define DMA_A_MSK              (((1U << DMA_A_LEN) - 1) << DMA_A_POS)
+#define DMA_A_UMSK             (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS))
+#define DMA_H                  DMA_H
+#define DMA_H_POS              (18U)
+#define DMA_H_LEN              (1U)
+#define DMA_H_MSK              (((1U << DMA_H_LEN) - 1) << DMA_H_POS)
+#define DMA_H_UMSK             (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS))
+
+
+struct  dma_reg
+{
+    /* 0x0 : DMA_IntStatus */
+    union
+    {
+        struct
+        {
+            uint32_t IntStatus                      :  8; /* [ 7: 0],          r,        0x0 */
+            uint32_t reserved_8_31                  : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_IntStatus;
+
+    /* 0x4 : DMA_IntTCStatus */
+    union
+    {
+        struct
+        {
+            uint32_t IntTCStatus                    :  8; /* [ 7: 0],          r,        0x0 */
+            uint32_t reserved_8_31                  : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_IntTCStatus;
+
+    /* 0x8 : DMA_IntTCClear */
+    union
+    {
+        struct
+        {
+            uint32_t IntTCClear                     :  8; /* [ 7: 0],          w,        0x0 */
+            uint32_t reserved_8_31                  : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_IntTCClear;
+
+    /* 0xC : DMA_IntErrorStatus */
+    union
+    {
+        struct
+        {
+            uint32_t IntErrorStatus                 :  8; /* [ 7: 0],          r,        0x0 */
+            uint32_t reserved_8_31                  : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_IntErrorStatus;
+
+    /* 0x10 : DMA_IntErrClr */
+    union
+    {
+        struct
+        {
+            uint32_t IntErrClr                      :  8; /* [ 7: 0],          w,        0x0 */
+            uint32_t reserved_8_31                  : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_IntErrClr;
+
+    /* 0x14 : DMA_RawIntTCStatus */
+    union
+    {
+        struct
+        {
+            uint32_t RawIntTCStatus                 :  8; /* [ 7: 0],          r,        0x0 */
+            uint32_t reserved_8_31                  : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_RawIntTCStatus;
+
+    /* 0x18 : DMA_RawIntErrorStatus */
+    union
+    {
+        struct
+        {
+            uint32_t RawIntErrorStatus              :  8; /* [ 7: 0],          r,        0x0 */
+            uint32_t reserved_8_31                  : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_RawIntErrorStatus;
+
+    /* 0x1C : DMA_EnbldChns */
+    union
+    {
+        struct
+        {
+            uint32_t EnabledChannels                :  8; /* [ 7: 0],          r,        0x0 */
+            uint32_t reserved_8_31                  : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_EnbldChns;
+
+    /* 0x20 : DMA_SoftBReq */
+    union
+    {
+        struct
+        {
+            uint32_t SoftBReq                       : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_SoftBReq;
+
+    /* 0x24 : DMA_SoftSReq */
+    union
+    {
+        struct
+        {
+            uint32_t SoftSReq                       : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_SoftSReq;
+
+    /* 0x28 : DMA_SoftLBReq */
+    union
+    {
+        struct
+        {
+            uint32_t SoftLBReq                      : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_SoftLBReq;
+
+    /* 0x2C : DMA_SoftLSReq */
+    union
+    {
+        struct
+        {
+            uint32_t SoftLSReq                      : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_SoftLSReq;
+
+    /* 0x30 : DMA_Top_Config */
+    union
+    {
+        struct
+        {
+            uint32_t E                              :  1; /* [    0],        r/w,        0x0 */
+            uint32_t M                              :  1; /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_31                  : 30; /* [31: 2],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_Top_Config;
+
+    /* 0x34 : DMA_Sync */
+    union
+    {
+        struct
+        {
+            uint32_t DMA_Sync                       : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_Sync;
+
+    /* 0x38  reserved */
+    uint8_t RESERVED0x38[200];
+
+    /* 0x100 : DMA_C0SrcAddr */
+    union
+    {
+        struct
+        {
+            uint32_t SrcAddr                        : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C0SrcAddr;
+
+    /* 0x104 : DMA_C0DstAddr */
+    union
+    {
+        struct
+        {
+            uint32_t DstAddr                        : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C0DstAddr;
+
+    /* 0x108 : DMA_C0LLI */
+    union
+    {
+        struct
+        {
+            uint32_t LLI                            : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C0LLI;
+
+    /* 0x10C : DMA_C0Control */
+    union
+    {
+        struct
+        {
+            uint32_t TransferSize                   : 12; /* [11: 0],        r/w,        0x0 */
+            uint32_t SBSize                         :  2; /* [13:12],        r/w,        0x1 */
+            uint32_t dst_min_mode                   :  1; /* [   14],        r/w,        0x0 */
+            uint32_t DBSize                         :  2; /* [16:15],        r/w,        0x1 */
+            uint32_t dst_add_mode                   :  1; /* [   17],        r/w,        0x0 */
+            uint32_t SWidth                         :  2; /* [19:18],        r/w,        0x2 */
+            uint32_t reserved_20                    :  1; /* [   20],       rsvd,        0x0 */
+            uint32_t DWidth                         :  2; /* [22:21],        r/w,        0x2 */
+            uint32_t fix_cnt                        :  2; /* [24:23],        r/w,        0x0 */
+            uint32_t SLargerD                       :  1; /* [   25],        r/w,        0x0 */
+            uint32_t SI                             :  1; /* [   26],        r/w,        0x1 */
+            uint32_t DI                             :  1; /* [   27],        r/w,        0x1 */
+            uint32_t Prot                           :  3; /* [30:28],        r/w,        0x0 */
+            uint32_t I                              :  1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C0Control;
+
+    /* 0x110 : DMA_C0Config */
+    union
+    {
+        struct
+        {
+            uint32_t E                              :  1; /* [    0],        r/w,        0x0 */
+            uint32_t SrcPeripheral                  :  5; /* [ 5: 1],        r/w,        0x0 */
+            uint32_t DstPeripheral                  :  5; /* [10: 6],        r/w,        0x0 */
+            uint32_t FlowCntrl                      :  3; /* [13:11],        r/w,        0x0 */
+            uint32_t IE                             :  1; /* [   14],        r/w,        0x0 */
+            uint32_t ITC                            :  1; /* [   15],        r/w,        0x0 */
+            uint32_t L                              :  1; /* [   16],        r/w,        0x0 */
+            uint32_t A                              :  1; /* [   17],          r,        0x0 */
+            uint32_t H                              :  1; /* [   18],        r/w,        0x0 */
+            uint32_t reserved_19                    :  1; /* [   19],       rsvd,        0x0 */
+            uint32_t LLICounter                     : 10; /* [29:20],          r,        0x0 */
+            uint32_t reserved_30_31                 :  2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C0Config;
+
+    /* 0x114  reserved */
+    uint8_t RESERVED0x114[236];
+
+    /* 0x200 : DMA_C1SrcAddr */
+    union
+    {
+        struct
+        {
+            uint32_t SrcAddr                        : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C1SrcAddr;
+
+    /* 0x204 : DMA_C1DstAddr */
+    union
+    {
+        struct
+        {
+            uint32_t DstAddr                        : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C1DstAddr;
+
+    /* 0x208 : DMA_C1LLI */
+    union
+    {
+        struct
+        {
+            uint32_t reserved_0_1                   :  2; /* [ 1: 0],       rsvd,        0x0 */
+            uint32_t LLI                            : 30; /* [31: 2],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C1LLI;
+
+    /* 0x20C : DMA_C1Control */
+    union
+    {
+        struct
+        {
+            uint32_t TransferSize                   : 12; /* [11: 0],        r/w,        0x0 */
+            uint32_t SBSize                         :  2; /* [13:12],        r/w,        0x1 */
+            uint32_t dst_min_mode                   :  1; /* [   14],        r/w,        0x0 */
+            uint32_t DBSize                         :  2; /* [16:15],        r/w,        0x1 */
+            uint32_t dst_add_mode                   :  1; /* [   17],        r/w,        0x0 */
+            uint32_t SWidth                         :  2; /* [19:18],        r/w,        0x2 */
+            uint32_t reserved_20                    :  1; /* [   20],       rsvd,        0x0 */
+            uint32_t DWidth                         :  2; /* [22:21],        r/w,        0x2 */
+            uint32_t fix_cnt                        :  2; /* [24:23],        r/w,        0x0 */
+            uint32_t SLargerD                       :  1; /* [   25],        r/w,        0x0 */
+            uint32_t SI                             :  1; /* [   26],        r/w,        0x1 */
+            uint32_t DI                             :  1; /* [   27],        r/w,        0x1 */
+            uint32_t Prot                           :  3; /* [30:28],        r/w,        0x0 */
+            uint32_t I                              :  1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C1Control;
+
+    /* 0x210 : DMA_C1Config */
+    union
+    {
+        struct
+        {
+            uint32_t E                              :  1; /* [    0],        r/w,        0x0 */
+            uint32_t SrcPeripheral                  :  5; /* [ 5: 1],        r/w,        0x0 */
+            uint32_t DstPeripheral                  :  5; /* [10: 6],        r/w,        0x0 */
+            uint32_t FlowCntrl                      :  3; /* [13:11],        r/w,        0x0 */
+            uint32_t IE                             :  1; /* [   14],        r/w,        0x0 */
+            uint32_t ITC                            :  1; /* [   15],        r/w,        0x0 */
+            uint32_t L                              :  1; /* [   16],        r/w,        0x0 */
+            uint32_t A                              :  1; /* [   17],          r,        0x0 */
+            uint32_t H                              :  1; /* [   18],        r/w,        0x0 */
+            uint32_t reserved_19_31                 : 13; /* [31:19],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C1Config;
+
+    /* 0x214  reserved */
+    uint8_t RESERVED0x214[236];
+
+    /* 0x300 : DMA_C2SrcAddr */
+    union
+    {
+        struct
+        {
+            uint32_t SrcAddr                        : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C2SrcAddr;
+
+    /* 0x304 : DMA_C2DstAddr */
+    union
+    {
+        struct
+        {
+            uint32_t DstAddr                        : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C2DstAddr;
+
+    /* 0x308 : DMA_C2LLI */
+    union
+    {
+        struct
+        {
+            uint32_t reserved_0_1                   :  2; /* [ 1: 0],       rsvd,        0x0 */
+            uint32_t LLI                            : 30; /* [31: 2],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C2LLI;
+
+    /* 0x30C : DMA_C2Control */
+    union
+    {
+        struct
+        {
+            uint32_t TransferSize                   : 12; /* [11: 0],        r/w,        0x0 */
+            uint32_t SBSize                         :  2; /* [13:12],        r/w,        0x1 */
+            uint32_t dst_min_mode                   :  1; /* [   14],        r/w,        0x0 */
+            uint32_t DBSize                         :  2; /* [16:15],        r/w,        0x1 */
+            uint32_t dst_add_mode                   :  1; /* [   17],        r/w,        0x0 */
+            uint32_t SWidth                         :  2; /* [19:18],        r/w,        0x2 */
+            uint32_t reserved_20                    :  1; /* [   20],       rsvd,        0x0 */
+            uint32_t DWidth                         :  2; /* [22:21],        r/w,        0x2 */
+            uint32_t fix_cnt                        :  2; /* [24:23],        r/w,        0x0 */
+            uint32_t SLargerD                       :  1; /* [   25],        r/w,        0x0 */
+            uint32_t SI                             :  1; /* [   26],        r/w,        0x1 */
+            uint32_t DI                             :  1; /* [   27],        r/w,        0x1 */
+            uint32_t Prot                           :  3; /* [30:28],        r/w,        0x0 */
+            uint32_t I                              :  1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C2Control;
+
+    /* 0x310 : DMA_C2Config */
+    union
+    {
+        struct
+        {
+            uint32_t E                              :  1; /* [    0],        r/w,        0x0 */
+            uint32_t SrcPeripheral                  :  5; /* [ 5: 1],        r/w,        0x0 */
+            uint32_t DstPeripheral                  :  5; /* [10: 6],        r/w,        0x0 */
+            uint32_t FlowCntrl                      :  3; /* [13:11],        r/w,        0x0 */
+            uint32_t IE                             :  1; /* [   14],        r/w,        0x0 */
+            uint32_t ITC                            :  1; /* [   15],        r/w,        0x0 */
+            uint32_t L                              :  1; /* [   16],        r/w,        0x0 */
+            uint32_t A                              :  1; /* [   17],          r,        0x0 */
+            uint32_t H                              :  1; /* [   18],        r/w,        0x0 */
+            uint32_t reserved_19_31                 : 13; /* [31:19],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C2Config;
+
+    /* 0x314  reserved */
+    uint8_t RESERVED0x314[236];
+
+    /* 0x400 : DMA_C3SrcAddr */
+    union
+    {
+        struct
+        {
+            uint32_t SrcAddr                        : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C3SrcAddr;
+
+    /* 0x404 : DMA_C3DstAddr */
+    union
+    {
+        struct
+        {
+            uint32_t DstAddr                        : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C3DstAddr;
+
+    /* 0x408 : DMA_C3LLI */
+    union
+    {
+        struct
+        {
+            uint32_t reserved_0_1                   :  2; /* [ 1: 0],       rsvd,        0x0 */
+            uint32_t LLI                            : 30; /* [31: 2],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C3LLI;
+
+    /* 0x40C : DMA_C3Control */
+    union
+    {
+        struct
+        {
+            uint32_t TransferSize                   : 12; /* [11: 0],        r/w,        0x0 */
+            uint32_t SBSize                         :  2; /* [13:12],        r/w,        0x1 */
+            uint32_t dst_min_mode                   :  1; /* [   14],        r/w,        0x0 */
+            uint32_t DBSize                         :  2; /* [16:15],        r/w,        0x1 */
+            uint32_t dst_add_mode                   :  1; /* [   17],        r/w,        0x0 */
+            uint32_t SWidth                         :  2; /* [19:18],        r/w,        0x2 */
+            uint32_t reserved_20                    :  1; /* [   20],       rsvd,        0x0 */
+            uint32_t DWidth                         :  2; /* [22:21],        r/w,        0x2 */
+            uint32_t fix_cnt                        :  2; /* [24:23],        r/w,        0x0 */
+            uint32_t SLargerD                       :  1; /* [   25],        r/w,        0x0 */
+            uint32_t SI                             :  1; /* [   26],        r/w,        0x1 */
+            uint32_t DI                             :  1; /* [   27],        r/w,        0x1 */
+            uint32_t Prot                           :  3; /* [30:28],        r/w,        0x0 */
+            uint32_t I                              :  1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C3Control;
+
+    /* 0x410 : DMA_C3Config */
+    union
+    {
+        struct
+        {
+            uint32_t E                              :  1; /* [    0],        r/w,        0x0 */
+            uint32_t SrcPeripheral                  :  5; /* [ 5: 1],        r/w,        0x0 */
+            uint32_t DstPeripheral                  :  5; /* [10: 6],        r/w,        0x0 */
+            uint32_t FlowCntrl                      :  3; /* [13:11],        r/w,        0x0 */
+            uint32_t IE                             :  1; /* [   14],        r/w,        0x0 */
+            uint32_t ITC                            :  1; /* [   15],        r/w,        0x0 */
+            uint32_t L                              :  1; /* [   16],        r/w,        0x0 */
+            uint32_t A                              :  1; /* [   17],          r,        0x0 */
+            uint32_t H                              :  1; /* [   18],        r/w,        0x0 */
+            uint32_t reserved_19_31                 : 13; /* [31:19],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C3Config;
+
+    /* 0x414  reserved */
+    uint8_t RESERVED0x414[236];
+
+    /* 0x500 : DMA_C4SrcAddr */
+    union
+    {
+        struct
+        {
+            uint32_t SrcAddr                        : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C4SrcAddr;
+
+    /* 0x504 : DMA_C4DstAddr */
+    union
+    {
+        struct
+        {
+            uint32_t DstAddr                        : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C4DstAddr;
+
+    /* 0x508 : DMA_C4LLI */
+    union
+    {
+        struct
+        {
+            uint32_t reserved_0_1                   :  2; /* [ 1: 0],       rsvd,        0x0 */
+            uint32_t LLI                            : 30; /* [31: 2],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C4LLI;
+
+    /* 0x50C : DMA_C4Control */
+    union
+    {
+        struct
+        {
+            uint32_t TransferSize                   : 12; /* [11: 0],        r/w,        0x0 */
+            uint32_t SBSize                         :  2; /* [13:12],        r/w,        0x1 */
+            uint32_t dst_min_mode                   :  1; /* [   14],        r/w,        0x0 */
+            uint32_t DBSize                         :  2; /* [16:15],        r/w,        0x1 */
+            uint32_t dst_add_mode                   :  1; /* [   17],        r/w,        0x0 */
+            uint32_t SWidth                         :  2; /* [19:18],        r/w,        0x2 */
+            uint32_t reserved_20                    :  1; /* [   20],       rsvd,        0x0 */
+            uint32_t DWidth                         :  2; /* [22:21],        r/w,        0x2 */
+            uint32_t fix_cnt                        :  2; /* [24:23],        r/w,        0x0 */
+            uint32_t SLargerD                       :  1; /* [   25],        r/w,        0x0 */
+            uint32_t SI                             :  1; /* [   26],        r/w,        0x1 */
+            uint32_t DI                             :  1; /* [   27],        r/w,        0x1 */
+            uint32_t Prot                           :  3; /* [30:28],        r/w,        0x0 */
+            uint32_t I                              :  1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C4Control;
+
+    /* 0x510 : DMA_C4Config */
+    union
+    {
+        struct
+        {
+            uint32_t E                              :  1; /* [    0],        r/w,        0x0 */
+            uint32_t SrcPeripheral                  :  5; /* [ 5: 1],        r/w,        0x0 */
+            uint32_t DstPeripheral                  :  5; /* [10: 6],        r/w,        0x0 */
+            uint32_t FlowCntrl                      :  3; /* [13:11],        r/w,        0x0 */
+            uint32_t IE                             :  1; /* [   14],        r/w,        0x0 */
+            uint32_t ITC                            :  1; /* [   15],        r/w,        0x0 */
+            uint32_t L                              :  1; /* [   16],        r/w,        0x0 */
+            uint32_t A                              :  1; /* [   17],          r,        0x0 */
+            uint32_t H                              :  1; /* [   18],        r/w,        0x0 */
+            uint32_t reserved_19_31                 : 13; /* [31:19],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C4Config;
+
+    /* 0x514  reserved */
+    uint8_t RESERVED0x514[236];
+
+    /* 0x600 : DMA_C5SrcAddr */
+    union
+    {
+        struct
+        {
+            uint32_t SrcAddr                        : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C5SrcAddr;
+
+    /* 0x604 : DMA_C5DstAddr */
+    union
+    {
+        struct
+        {
+            uint32_t DstAddr                        : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C5DstAddr;
+
+    /* 0x608 : DMA_C5LLI */
+    union
+    {
+        struct
+        {
+            uint32_t reserved_0_1                   :  2; /* [ 1: 0],       rsvd,        0x0 */
+            uint32_t LLI                            : 30; /* [31: 2],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C5LLI;
+
+    /* 0x60C : DMA_C5Control */
+    union
+    {
+        struct
+        {
+            uint32_t TransferSize                   : 12; /* [11: 0],        r/w,        0x0 */
+            uint32_t SBSize                         :  2; /* [13:12],        r/w,        0x1 */
+            uint32_t dst_min_mode                   :  1; /* [   14],        r/w,        0x0 */
+            uint32_t DBSize                         :  2; /* [16:15],        r/w,        0x1 */
+            uint32_t dst_add_mode                   :  1; /* [   17],        r/w,        0x0 */
+            uint32_t SWidth                         :  2; /* [19:18],        r/w,        0x2 */
+            uint32_t reserved_20                    :  1; /* [   20],       rsvd,        0x0 */
+            uint32_t DWidth                         :  2; /* [22:21],        r/w,        0x2 */
+            uint32_t fix_cnt                        :  2; /* [24:23],        r/w,        0x0 */
+            uint32_t SLargerD                       :  1; /* [   25],        r/w,        0x0 */
+            uint32_t SI                             :  1; /* [   26],        r/w,        0x1 */
+            uint32_t DI                             :  1; /* [   27],        r/w,        0x1 */
+            uint32_t Prot                           :  3; /* [30:28],        r/w,        0x0 */
+            uint32_t I                              :  1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C5Control;
+
+    /* 0x610 : DMA_C5Config */
+    union
+    {
+        struct
+        {
+            uint32_t E                              :  1; /* [    0],        r/w,        0x0 */
+            uint32_t SrcPeripheral                  :  5; /* [ 5: 1],        r/w,        0x0 */
+            uint32_t DstPeripheral                  :  5; /* [10: 6],        r/w,        0x0 */
+            uint32_t FlowCntrl                      :  3; /* [13:11],        r/w,        0x0 */
+            uint32_t IE                             :  1; /* [   14],        r/w,        0x0 */
+            uint32_t ITC                            :  1; /* [   15],        r/w,        0x0 */
+            uint32_t L                              :  1; /* [   16],        r/w,        0x0 */
+            uint32_t A                              :  1; /* [   17],          r,        0x0 */
+            uint32_t H                              :  1; /* [   18],        r/w,        0x0 */
+            uint32_t reserved_19_31                 : 13; /* [31:19],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C5Config;
+
+    /* 0x614  reserved */
+    uint8_t RESERVED0x614[236];
+
+    /* 0x700 : DMA_C6SrcAddr */
+    union
+    {
+        struct
+        {
+            uint32_t SrcAddr                        : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C6SrcAddr;
+
+    /* 0x704 : DMA_C6DstAddr */
+    union
+    {
+        struct
+        {
+            uint32_t DstAddr                        : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C6DstAddr;
+
+    /* 0x708 : DMA_C6LLI */
+    union
+    {
+        struct
+        {
+            uint32_t reserved_0_1                   :  2; /* [ 1: 0],       rsvd,        0x0 */
+            uint32_t LLI                            : 30; /* [31: 2],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C6LLI;
+
+    /* 0x70C : DMA_C6Control */
+    union
+    {
+        struct
+        {
+            uint32_t TransferSize                   : 12; /* [11: 0],        r/w,        0x0 */
+            uint32_t SBSize                         :  2; /* [13:12],        r/w,        0x1 */
+            uint32_t dst_min_mode                   :  1; /* [   14],        r/w,        0x0 */
+            uint32_t DBSize                         :  2; /* [16:15],        r/w,        0x1 */
+            uint32_t dst_add_mode                   :  1; /* [   17],        r/w,        0x0 */
+            uint32_t SWidth                         :  2; /* [19:18],        r/w,        0x2 */
+            uint32_t reserved_20                    :  1; /* [   20],       rsvd,        0x0 */
+            uint32_t DWidth                         :  2; /* [22:21],        r/w,        0x2 */
+            uint32_t fix_cnt                        :  2; /* [24:23],        r/w,        0x0 */
+            uint32_t SLargerD                       :  1; /* [   25],        r/w,        0x0 */
+            uint32_t SI                             :  1; /* [   26],        r/w,        0x1 */
+            uint32_t DI                             :  1; /* [   27],        r/w,        0x1 */
+            uint32_t Prot                           :  3; /* [30:28],        r/w,        0x0 */
+            uint32_t I                              :  1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C6Control;
+
+    /* 0x710 : DMA_C6Config */
+    union
+    {
+        struct
+        {
+            uint32_t E                              :  1; /* [    0],        r/w,        0x0 */
+            uint32_t SrcPeripheral                  :  5; /* [ 5: 1],        r/w,        0x0 */
+            uint32_t DstPeripheral                  :  5; /* [10: 6],        r/w,        0x0 */
+            uint32_t FlowCntrl                      :  3; /* [13:11],        r/w,        0x0 */
+            uint32_t IE                             :  1; /* [   14],        r/w,        0x0 */
+            uint32_t ITC                            :  1; /* [   15],        r/w,        0x0 */
+            uint32_t L                              :  1; /* [   16],        r/w,        0x0 */
+            uint32_t A                              :  1; /* [   17],          r,        0x0 */
+            uint32_t H                              :  1; /* [   18],        r/w,        0x0 */
+            uint32_t reserved_19_31                 : 13; /* [31:19],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C6Config;
+
+    /* 0x714  reserved */
+    uint8_t RESERVED0x714[236];
+
+    /* 0x800 : DMA_C7SrcAddr */
+    union
+    {
+        struct
+        {
+            uint32_t SrcAddr                        : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C7SrcAddr;
+
+    /* 0x804 : DMA_C7DstAddr */
+    union
+    {
+        struct
+        {
+            uint32_t DstAddr                        : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C7DstAddr;
+
+    /* 0x808 : DMA_C7LLI */
+    union
+    {
+        struct
+        {
+            uint32_t reserved_0_1                   :  2; /* [ 1: 0],       rsvd,        0x0 */
+            uint32_t LLI                            : 30; /* [31: 2],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C7LLI;
+
+    /* 0x80C : DMA_C7Control */
+    union
+    {
+        struct
+        {
+            uint32_t TransferSize                   : 12; /* [11: 0],        r/w,        0x0 */
+            uint32_t SBSize                         :  2; /* [13:12],        r/w,        0x1 */
+            uint32_t dst_min_mode                   :  1; /* [   14],        r/w,        0x0 */
+            uint32_t DBSize                         :  2; /* [16:15],        r/w,        0x1 */
+            uint32_t dst_add_mode                   :  1; /* [   17],        r/w,        0x0 */
+            uint32_t SWidth                         :  2; /* [19:18],        r/w,        0x2 */
+            uint32_t reserved_20                    :  1; /* [   20],       rsvd,        0x0 */
+            uint32_t DWidth                         :  2; /* [22:21],        r/w,        0x2 */
+            uint32_t fix_cnt                        :  2; /* [24:23],        r/w,        0x0 */
+            uint32_t SLargerD                       :  1; /* [   25],        r/w,        0x0 */
+            uint32_t SI                             :  1; /* [   26],        r/w,        0x1 */
+            uint32_t DI                             :  1; /* [   27],        r/w,        0x1 */
+            uint32_t Prot                           :  3; /* [30:28],        r/w,        0x0 */
+            uint32_t I                              :  1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C7Control;
+
+    /* 0x810 : DMA_C7Config */
+    union
+    {
+        struct
+        {
+            uint32_t E                              :  1; /* [    0],        r/w,        0x0 */
+            uint32_t SrcPeripheral                  :  5; /* [ 5: 1],        r/w,        0x0 */
+            uint32_t DstPeripheral                  :  5; /* [10: 6],        r/w,        0x0 */
+            uint32_t FlowCntrl                      :  3; /* [13:11],        r/w,        0x0 */
+            uint32_t IE                             :  1; /* [   14],        r/w,        0x0 */
+            uint32_t ITC                            :  1; /* [   15],        r/w,        0x0 */
+            uint32_t L                              :  1; /* [   16],        r/w,        0x0 */
+            uint32_t A                              :  1; /* [   17],          r,        0x0 */
+            uint32_t H                              :  1; /* [   18],        r/w,        0x0 */
+            uint32_t reserved_19_31                 : 13; /* [31:19],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_C7Config;
+
+};
+#endif
+
+typedef volatile struct dma_reg dma_reg_t;
+
+/*Following is reg patch*/
+
+/* 0x0 : DMA_SrcAddr */
+#define DMA_SRCADDR_OFFSET (0x0)
+#define DMA_SRCADDR        DMA_SRCADDR
+#define DMA_SRCADDR_POS    (0U)
+#define DMA_SRCADDR_LEN    (32U)
+#define DMA_SRCADDR_MSK    (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)
+#define DMA_SRCADDR_UMSK   (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS))
+
+/* 0x4 : DMA_DstAddr */
+#define DMA_DSTADDR_OFFSET (0x4)
+#define DMA_DSTADDR        DMA_DSTADDR
+#define DMA_DSTADDR_POS    (0U)
+#define DMA_DSTADDR_LEN    (32U)
+#define DMA_DSTADDR_MSK    (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)
+#define DMA_DSTADDR_UMSK   (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS))
+
+/* 0x8 : DMA_LLI */
+#define DMA_LLI_OFFSET (0x8)
+#define DMA_LLI        DMA_LLI
+#define DMA_LLI_POS    (0U)
+#define DMA_LLI_LEN    (32U)
+#define DMA_LLI_MSK    (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)
+#define DMA_LLI_UMSK   (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS))
+
+/* 0xc : DMA_Control */
+#define DMA_CONTROL_OFFSET    (0xc)
+#define DMA_TRANSFERSIZE      DMA_TRANSFERSIZE
+#define DMA_TRANSFERSIZE_POS  (0U)
+#define DMA_TRANSFERSIZE_LEN  (12U)
+#define DMA_TRANSFERSIZE_MSK  (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)
+#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS))
+#define DMA_SBSIZE            DMA_SBSIZE
+#define DMA_SBSIZE_POS        (12U)
+#define DMA_SBSIZE_LEN        (2U)
+#define DMA_SBSIZE_MSK        (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)
+#define DMA_SBSIZE_UMSK       (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS))
+#define DMA_DST_MIN_MODE      DMA_DST_MIN_MODE
+#define DMA_DST_MIN_MODE_POS  (14U)
+#define DMA_DST_MIN_MODE_LEN  (1U)
+#define DMA_DST_MIN_MODE_MSK  (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)
+#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS))
+#define DMA_DBSIZE            DMA_DBSIZE
+#define DMA_DBSIZE_POS        (15U)
+#define DMA_DBSIZE_LEN        (2U)
+#define DMA_DBSIZE_MSK        (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)
+#define DMA_DBSIZE_UMSK       (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS))
+#define DMA_DST_ADD_MODE      DMA_DST_ADD_MODE
+#define DMA_DST_ADD_MODE_POS  (17U)
+#define DMA_DST_ADD_MODE_LEN  (1U)
+#define DMA_DST_ADD_MODE_MSK  (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)
+#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS))
+#define DMA_SWIDTH            DMA_SWIDTH
+#define DMA_SWIDTH_POS        (18U)
+#define DMA_SWIDTH_LEN        (2U)
+#define DMA_SWIDTH_MSK        (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)
+#define DMA_SWIDTH_UMSK       (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS))
+#define DMA_DWIDTH            DMA_DWIDTH
+#define DMA_DWIDTH_POS        (21U)
+#define DMA_DWIDTH_LEN        (2U)
+#define DMA_DWIDTH_MSK        (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)
+#define DMA_DWIDTH_UMSK       (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS))
+#define DMA_FIX_CNT           DMA_FIX_CNT
+#define DMA_FIX_CNT_POS       (23U)
+#define DMA_FIX_CNT_LEN       (2U)
+#define DMA_FIX_CNT_MSK       (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)
+#define DMA_FIX_CNT_UMSK      (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS))
+#define DMA_SLARGERD          DMA_SLARGERD
+#define DMA_SLARGERD_POS      (25U)
+#define DMA_SLARGERD_LEN      (1U)
+#define DMA_SLARGERD_MSK      (((1U << DMA_SLARGERD_LEN) - 1) << DMA_SLARGERD_POS)
+#define DMA_SLARGERD_UMSK     (~(((1U << DMA_SLARGERD_LEN) - 1) << DMA_SLARGERD_POS))
+#define DMA_SI                DMA_SI
+#define DMA_SI_POS            (26U)
+#define DMA_SI_LEN            (1U)
+#define DMA_SI_MSK            (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)
+#define DMA_SI_UMSK           (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS))
+#define DMA_DI                DMA_DI
+#define DMA_DI_POS            (27U)
+#define DMA_DI_LEN            (1U)
+#define DMA_DI_MSK            (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)
+#define DMA_DI_UMSK           (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS))
+#define DMA_PROT              DMA_PROT
+#define DMA_PROT_POS          (28U)
+#define DMA_PROT_LEN          (3U)
+#define DMA_PROT_MSK          (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)
+#define DMA_PROT_UMSK         (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS))
+#define DMA_I                 DMA_I
+#define DMA_I_POS             (31U)
+#define DMA_I_LEN             (1U)
+#define DMA_I_MSK             (((1U << DMA_I_LEN) - 1) << DMA_I_POS)
+#define DMA_I_UMSK            (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS))
+
+/* 0x10 : DMA_Config */
+#define DMA_CONFIG_OFFSET      (0x10)
+#define DMA_E                  DMA_E
+#define DMA_E_POS              (0U)
+#define DMA_E_LEN              (1U)
+#define DMA_E_MSK              (((1U << DMA_E_LEN) - 1) << DMA_E_POS)
+#define DMA_E_UMSK             (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS))
+#define DMA_SRCPERIPHERAL      DMA_SRCPERIPHERAL
+#define DMA_SRCPERIPHERAL_POS  (1U)
+#define DMA_SRCPERIPHERAL_LEN  (5U)
+#define DMA_SRCPERIPHERAL_MSK  (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)
+#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS))
+#define DMA_DSTPERIPHERAL      DMA_DSTPERIPHERAL
+#define DMA_DSTPERIPHERAL_POS  (6U)
+#define DMA_DSTPERIPHERAL_LEN  (5U)
+#define DMA_DSTPERIPHERAL_MSK  (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)
+#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS))
+#define DMA_FLOWCNTRL          DMA_FLOWCNTRL
+#define DMA_FLOWCNTRL_POS      (11U)
+#define DMA_FLOWCNTRL_LEN      (3U)
+#define DMA_FLOWCNTRL_MSK      (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)
+#define DMA_FLOWCNTRL_UMSK     (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS))
+#define DMA_IE                 DMA_IE
+#define DMA_IE_POS             (14U)
+#define DMA_IE_LEN             (1U)
+#define DMA_IE_MSK             (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)
+#define DMA_IE_UMSK            (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS))
+#define DMA_ITC                DMA_ITC
+#define DMA_ITC_POS            (15U)
+#define DMA_ITC_LEN            (1U)
+#define DMA_ITC_MSK            (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)
+#define DMA_ITC_UMSK           (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS))
+#define DMA_L                  DMA_L
+#define DMA_L_POS              (16U)
+#define DMA_L_LEN              (1U)
+#define DMA_L_MSK              (((1U << DMA_L_LEN) - 1) << DMA_L_POS)
+#define DMA_L_UMSK             (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS))
+#define DMA_A                  DMA_A
+#define DMA_A_POS              (17U)
+#define DMA_A_LEN              (1U)
+#define DMA_A_MSK              (((1U << DMA_A_LEN) - 1) << DMA_A_POS)
+#define DMA_A_UMSK             (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS))
+#define DMA_H                  DMA_H
+#define DMA_H_POS              (18U)
+#define DMA_H_LEN              (1U)
+#define DMA_H_MSK              (((1U << DMA_H_LEN) - 1) << DMA_H_POS)
+#define DMA_H_UMSK             (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS))
+#define DMA_LLICOUNTER         DMA_LLICOUNTER
+#define DMA_LLICOUNTER_POS     (20U)
+#define DMA_LLICOUNTER_LEN     (10U)
+#define DMA_LLICOUNTER_MSK     (((1U << DMA_LLICOUNTER_LEN) - 1) << DMA_LLICOUNTER_POS)
+#define DMA_LLICOUNTER_UMSK    (~(((1U << DMA_LLICOUNTER_LEN) - 1) << DMA_LLICOUNTER_POS))
+
+struct dma_channel_reg {
+    /* 0x0 : DMA_SrcAddr */
+    union {
+        struct
+        {
+            uint32_t SrcAddr : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_SrcAddr;
+
+    /* 0x4 : DMA_DstAddr */
+    union {
+        struct
+        {
+            uint32_t DstAddr : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_DstAddr;
+
+    /* 0x8 : DMA_LLI */
+    union {
+        struct
+        {
+            uint32_t LLI : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_LLI;
+
+    /* 0xc : DMA_Control */
+    union {
+        struct DMA_Control_Reg {
+            uint32_t TransferSize : 12; /* [11: 0],        r/w,        0x0 */
+            uint32_t SBSize       : 2;  /* [13:12],        r/w,        0x1 */
+            uint32_t dst_min_mode : 1;  /* [   14],        r/w,        0x0 */
+            uint32_t DBSize       : 2;  /* [16:15],        r/w,        0x1 */
+            uint32_t dst_add_mode : 1;  /* [   17],        r/w,        0x0 */
+            uint32_t SWidth       : 2;  /* [19:18],        r/w,        0x2 */
+            uint32_t reserved_20  : 1;  /* [   20],       rsvd,        0x0 */
+            uint32_t DWidth       : 2;  /* [22:21],        r/w,        0x2 */
+            uint32_t fix_cnt      : 2;  /* [24:23],        r/w,        0x0 */
+            uint32_t SLargerD     : 1;  /* [   25],        r/w,        0x0 */
+            uint32_t SI           : 1;  /* [   26],        r/w,        0x1 */
+            uint32_t DI           : 1;  /* [   27],        r/w,        0x1 */
+            uint32_t Prot         : 3;  /* [30:28],        r/w,        0x0 */
+            uint32_t I            : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_Control;
+
+    /* 0x10 : DMA_Config */
+    union {
+        struct
+        {
+            uint32_t E              : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t SrcPeripheral  : 5;  /* [ 5: 1],        r/w,        0x0 */
+            uint32_t DstPeripheral  : 5;  /* [10: 6],        r/w,        0x0 */
+            uint32_t FlowCntrl      : 3;  /* [13:11],        r/w,        0x0 */
+            uint32_t IE             : 1;  /* [   14],        r/w,        0x0 */
+            uint32_t ITC            : 1;  /* [   15],        r/w,        0x0 */
+            uint32_t L              : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t A              : 1;  /* [   17],          r,        0x0 */
+            uint32_t H              : 1;  /* [   18],        r/w,        0x0 */
+            uint32_t reserved_19    : 1;  /* [   19],       rsvd,        0x0 */
+            uint32_t LLICounter     : 10; /* [29:20],          r,        0x0 */
+            uint32_t reserved_30_31 : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DMA_Config;
+};
+
+typedef volatile struct dma_channel_reg dma_channel_reg_t;
+
+#define DMA_CHANNEL_OFFSET 0x100
+
+#endif /* __DMA_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/ef_ctrl_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/ef_ctrl_reg.h
new file mode 100644
index 00000000..b7e95371
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/ef_ctrl_reg.h
@@ -0,0 +1,812 @@
+/**
+  ******************************************************************************
+  * @file    ef_ctrl_reg.h
+  * @version V1.2
+  * @date    2020-04-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __EF_CTRL_REG_H__
+#define __EF_CTRL_REG_H__
+
+#include "bl702.h"
+
+/* 0x800 : ef_if_ctrl_0 */
+#define EF_CTRL_EF_IF_CTRL_0_OFFSET           (0x800)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE      EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS  (0U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN  (1U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_MSK  (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_UMSK (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS))
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE         EF_CTRL_EF_IF_0_AUTOLOAD_DONE
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS     (1U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN     (1U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_MSK     (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_UMSK    (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS))
+#define EF_CTRL_EF_IF_0_BUSY                  EF_CTRL_EF_IF_0_BUSY
+#define EF_CTRL_EF_IF_0_BUSY_POS              (2U)
+#define EF_CTRL_EF_IF_0_BUSY_LEN              (1U)
+#define EF_CTRL_EF_IF_0_BUSY_MSK              (((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS)
+#define EF_CTRL_EF_IF_0_BUSY_UMSK             (~(((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS))
+#define EF_CTRL_EF_IF_0_RW                    EF_CTRL_EF_IF_0_RW
+#define EF_CTRL_EF_IF_0_RW_POS                (3U)
+#define EF_CTRL_EF_IF_0_RW_LEN                (1U)
+#define EF_CTRL_EF_IF_0_RW_MSK                (((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS)
+#define EF_CTRL_EF_IF_0_RW_UMSK               (~(((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS))
+#define EF_CTRL_EF_IF_0_TRIG                  EF_CTRL_EF_IF_0_TRIG
+#define EF_CTRL_EF_IF_0_TRIG_POS              (4U)
+#define EF_CTRL_EF_IF_0_TRIG_LEN              (1U)
+#define EF_CTRL_EF_IF_0_TRIG_MSK              (((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS)
+#define EF_CTRL_EF_IF_0_TRIG_UMSK             (~(((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS))
+#define EF_CTRL_EF_IF_0_MANUAL_EN             EF_CTRL_EF_IF_0_MANUAL_EN
+#define EF_CTRL_EF_IF_0_MANUAL_EN_POS         (5U)
+#define EF_CTRL_EF_IF_0_MANUAL_EN_LEN         (1U)
+#define EF_CTRL_EF_IF_0_MANUAL_EN_MSK         (((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS)
+#define EF_CTRL_EF_IF_0_MANUAL_EN_UMSK        (~(((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS))
+#define EF_CTRL_EF_IF_0_CYC_MODIFY            EF_CTRL_EF_IF_0_CYC_MODIFY
+#define EF_CTRL_EF_IF_0_CYC_MODIFY_POS        (6U)
+#define EF_CTRL_EF_IF_0_CYC_MODIFY_LEN        (1U)
+#define EF_CTRL_EF_IF_0_CYC_MODIFY_MSK        (((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS)
+#define EF_CTRL_EF_IF_0_CYC_MODIFY_UMSK       (~(((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS))
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL          EF_CTRL_EF_CLK_SAHB_DATA_SEL
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS      (7U)
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN      (1U)
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_MSK      (((1U << EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS)
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_UMSK     (~(((1U << EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS))
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL          EF_CTRL_EF_IF_PROT_CODE_CTRL
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL_POS      (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN      (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL_MSK      (((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS)
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL_UMSK     (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS))
+#define EF_CTRL_EF_IF_POR_DIG                 EF_CTRL_EF_IF_POR_DIG
+#define EF_CTRL_EF_IF_POR_DIG_POS             (16U)
+#define EF_CTRL_EF_IF_POR_DIG_LEN             (1U)
+#define EF_CTRL_EF_IF_POR_DIG_MSK             (((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS)
+#define EF_CTRL_EF_IF_POR_DIG_UMSK            (~(((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS))
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE         EF_CTRL_EF_CLK_SAHB_DATA_GATE
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS     (17U)
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN     (1U)
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_MSK     (((1U << EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS)
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_UMSK    (~(((1U << EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS))
+#define EF_CTRL_EF_IF_AUTO_RD_EN              EF_CTRL_EF_IF_AUTO_RD_EN
+#define EF_CTRL_EF_IF_AUTO_RD_EN_POS          (18U)
+#define EF_CTRL_EF_IF_AUTO_RD_EN_LEN          (1U)
+#define EF_CTRL_EF_IF_AUTO_RD_EN_MSK          (((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS)
+#define EF_CTRL_EF_IF_AUTO_RD_EN_UMSK         (~(((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS))
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK         EF_CTRL_EF_IF_CYC_MODIFY_LOCK
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS     (19U)
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN     (1U)
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_MSK     (((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS)
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_UMSK    (~(((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS))
+#define EF_CTRL_EF_IF_0_INT                   EF_CTRL_EF_IF_0_INT
+#define EF_CTRL_EF_IF_0_INT_POS               (20U)
+#define EF_CTRL_EF_IF_0_INT_LEN               (1U)
+#define EF_CTRL_EF_IF_0_INT_MSK               (((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS)
+#define EF_CTRL_EF_IF_0_INT_UMSK              (~(((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS))
+#define EF_CTRL_EF_IF_0_INT_CLR               EF_CTRL_EF_IF_0_INT_CLR
+#define EF_CTRL_EF_IF_0_INT_CLR_POS           (21U)
+#define EF_CTRL_EF_IF_0_INT_CLR_LEN           (1U)
+#define EF_CTRL_EF_IF_0_INT_CLR_MSK           (((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS)
+#define EF_CTRL_EF_IF_0_INT_CLR_UMSK          (~(((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS))
+#define EF_CTRL_EF_IF_0_INT_SET               EF_CTRL_EF_IF_0_INT_SET
+#define EF_CTRL_EF_IF_0_INT_SET_POS           (22U)
+#define EF_CTRL_EF_IF_0_INT_SET_LEN           (1U)
+#define EF_CTRL_EF_IF_0_INT_SET_MSK           (((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS)
+#define EF_CTRL_EF_IF_0_INT_SET_UMSK          (~(((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS))
+#define EF_CTRL_EF_IF_PROT_CODE_CYC           EF_CTRL_EF_IF_PROT_CODE_CYC
+#define EF_CTRL_EF_IF_PROT_CODE_CYC_POS       (24U)
+#define EF_CTRL_EF_IF_PROT_CODE_CYC_LEN       (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_CYC_MSK       (((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS)
+#define EF_CTRL_EF_IF_PROT_CODE_CYC_UMSK      (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS))
+
+/* 0x804 : ef_if_cyc_0 */
+#define EF_CTRL_EF_IF_CYC_0_OFFSET     (0x804)
+#define EF_CTRL_EF_IF_CYC_RD_DMY       EF_CTRL_EF_IF_CYC_RD_DMY
+#define EF_CTRL_EF_IF_CYC_RD_DMY_POS   (0U)
+#define EF_CTRL_EF_IF_CYC_RD_DMY_LEN   (6U)
+#define EF_CTRL_EF_IF_CYC_RD_DMY_MSK   (((1U << EF_CTRL_EF_IF_CYC_RD_DMY_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DMY_POS)
+#define EF_CTRL_EF_IF_CYC_RD_DMY_UMSK  (~(((1U << EF_CTRL_EF_IF_CYC_RD_DMY_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DMY_POS))
+#define EF_CTRL_EF_IF_CYC_RD_DAT       EF_CTRL_EF_IF_CYC_RD_DAT
+#define EF_CTRL_EF_IF_CYC_RD_DAT_POS   (6U)
+#define EF_CTRL_EF_IF_CYC_RD_DAT_LEN   (6U)
+#define EF_CTRL_EF_IF_CYC_RD_DAT_MSK   (((1U << EF_CTRL_EF_IF_CYC_RD_DAT_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DAT_POS)
+#define EF_CTRL_EF_IF_CYC_RD_DAT_UMSK  (~(((1U << EF_CTRL_EF_IF_CYC_RD_DAT_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DAT_POS))
+#define EF_CTRL_EF_IF_CYC_RD_ADR       EF_CTRL_EF_IF_CYC_RD_ADR
+#define EF_CTRL_EF_IF_CYC_RD_ADR_POS   (12U)
+#define EF_CTRL_EF_IF_CYC_RD_ADR_LEN   (6U)
+#define EF_CTRL_EF_IF_CYC_RD_ADR_MSK   (((1U << EF_CTRL_EF_IF_CYC_RD_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_ADR_POS)
+#define EF_CTRL_EF_IF_CYC_RD_ADR_UMSK  (~(((1U << EF_CTRL_EF_IF_CYC_RD_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_ADR_POS))
+#define EF_CTRL_EF_IF_CYC_CS           EF_CTRL_EF_IF_CYC_CS
+#define EF_CTRL_EF_IF_CYC_CS_POS       (18U)
+#define EF_CTRL_EF_IF_CYC_CS_LEN       (6U)
+#define EF_CTRL_EF_IF_CYC_CS_MSK       (((1U << EF_CTRL_EF_IF_CYC_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_CS_POS)
+#define EF_CTRL_EF_IF_CYC_CS_UMSK      (~(((1U << EF_CTRL_EF_IF_CYC_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_CS_POS))
+#define EF_CTRL_EF_IF_CYC_PD_CS_S      EF_CTRL_EF_IF_CYC_PD_CS_S
+#define EF_CTRL_EF_IF_CYC_PD_CS_S_POS  (24U)
+#define EF_CTRL_EF_IF_CYC_PD_CS_S_LEN  (8U)
+#define EF_CTRL_EF_IF_CYC_PD_CS_S_MSK  (((1U << EF_CTRL_EF_IF_CYC_PD_CS_S_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_S_POS)
+#define EF_CTRL_EF_IF_CYC_PD_CS_S_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PD_CS_S_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_S_POS))
+
+/* 0x808 : ef_if_cyc_1 */
+#define EF_CTRL_EF_IF_CYC_1_OFFSET     (0x808)
+#define EF_CTRL_EF_IF_CYC_PI           EF_CTRL_EF_IF_CYC_PI
+#define EF_CTRL_EF_IF_CYC_PI_POS       (0U)
+#define EF_CTRL_EF_IF_CYC_PI_LEN       (6U)
+#define EF_CTRL_EF_IF_CYC_PI_MSK       (((1U << EF_CTRL_EF_IF_CYC_PI_LEN) - 1) << EF_CTRL_EF_IF_CYC_PI_POS)
+#define EF_CTRL_EF_IF_CYC_PI_UMSK      (~(((1U << EF_CTRL_EF_IF_CYC_PI_LEN) - 1) << EF_CTRL_EF_IF_CYC_PI_POS))
+#define EF_CTRL_EF_IF_CYC_PP           EF_CTRL_EF_IF_CYC_PP
+#define EF_CTRL_EF_IF_CYC_PP_POS       (6U)
+#define EF_CTRL_EF_IF_CYC_PP_LEN       (8U)
+#define EF_CTRL_EF_IF_CYC_PP_MSK       (((1U << EF_CTRL_EF_IF_CYC_PP_LEN) - 1) << EF_CTRL_EF_IF_CYC_PP_POS)
+#define EF_CTRL_EF_IF_CYC_PP_UMSK      (~(((1U << EF_CTRL_EF_IF_CYC_PP_LEN) - 1) << EF_CTRL_EF_IF_CYC_PP_POS))
+#define EF_CTRL_EF_IF_CYC_WR_ADR       EF_CTRL_EF_IF_CYC_WR_ADR
+#define EF_CTRL_EF_IF_CYC_WR_ADR_POS   (14U)
+#define EF_CTRL_EF_IF_CYC_WR_ADR_LEN   (6U)
+#define EF_CTRL_EF_IF_CYC_WR_ADR_MSK   (((1U << EF_CTRL_EF_IF_CYC_WR_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_WR_ADR_POS)
+#define EF_CTRL_EF_IF_CYC_WR_ADR_UMSK  (~(((1U << EF_CTRL_EF_IF_CYC_WR_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_WR_ADR_POS))
+#define EF_CTRL_EF_IF_CYC_PS_CS        EF_CTRL_EF_IF_CYC_PS_CS
+#define EF_CTRL_EF_IF_CYC_PS_CS_POS    (20U)
+#define EF_CTRL_EF_IF_CYC_PS_CS_LEN    (6U)
+#define EF_CTRL_EF_IF_CYC_PS_CS_MSK    (((1U << EF_CTRL_EF_IF_CYC_PS_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_PS_CS_POS)
+#define EF_CTRL_EF_IF_CYC_PS_CS_UMSK   (~(((1U << EF_CTRL_EF_IF_CYC_PS_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_PS_CS_POS))
+#define EF_CTRL_EF_IF_CYC_PD_CS_H      EF_CTRL_EF_IF_CYC_PD_CS_H
+#define EF_CTRL_EF_IF_CYC_PD_CS_H_POS  (26U)
+#define EF_CTRL_EF_IF_CYC_PD_CS_H_LEN  (6U)
+#define EF_CTRL_EF_IF_CYC_PD_CS_H_MSK  (((1U << EF_CTRL_EF_IF_CYC_PD_CS_H_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_H_POS)
+#define EF_CTRL_EF_IF_CYC_PD_CS_H_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PD_CS_H_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_H_POS))
+
+/* 0x80C : ef_if_0_manual */
+#define EF_CTRL_EF_IF_0_MANUAL_OFFSET       (0x80C)
+#define EF_CTRL_EF_IF_A                     EF_CTRL_EF_IF_A
+#define EF_CTRL_EF_IF_A_POS                 (0U)
+#define EF_CTRL_EF_IF_A_LEN                 (10U)
+#define EF_CTRL_EF_IF_A_MSK                 (((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS)
+#define EF_CTRL_EF_IF_A_UMSK                (~(((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS))
+#define EF_CTRL_EF_IF_PD                    EF_CTRL_EF_IF_PD
+#define EF_CTRL_EF_IF_PD_POS                (10U)
+#define EF_CTRL_EF_IF_PD_LEN                (1U)
+#define EF_CTRL_EF_IF_PD_MSK                (((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS)
+#define EF_CTRL_EF_IF_PD_UMSK               (~(((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS))
+#define EF_CTRL_EF_IF_PS                    EF_CTRL_EF_IF_PS
+#define EF_CTRL_EF_IF_PS_POS                (11U)
+#define EF_CTRL_EF_IF_PS_LEN                (1U)
+#define EF_CTRL_EF_IF_PS_MSK                (((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS)
+#define EF_CTRL_EF_IF_PS_UMSK               (~(((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS))
+#define EF_CTRL_EF_IF_STROBE                EF_CTRL_EF_IF_STROBE
+#define EF_CTRL_EF_IF_STROBE_POS            (12U)
+#define EF_CTRL_EF_IF_STROBE_LEN            (1U)
+#define EF_CTRL_EF_IF_STROBE_MSK            (((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS)
+#define EF_CTRL_EF_IF_STROBE_UMSK           (~(((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS))
+#define EF_CTRL_EF_IF_PGENB                 EF_CTRL_EF_IF_PGENB
+#define EF_CTRL_EF_IF_PGENB_POS             (13U)
+#define EF_CTRL_EF_IF_PGENB_LEN             (1U)
+#define EF_CTRL_EF_IF_PGENB_MSK             (((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS)
+#define EF_CTRL_EF_IF_PGENB_UMSK            (~(((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS))
+#define EF_CTRL_EF_IF_LOAD                  EF_CTRL_EF_IF_LOAD
+#define EF_CTRL_EF_IF_LOAD_POS              (14U)
+#define EF_CTRL_EF_IF_LOAD_LEN              (1U)
+#define EF_CTRL_EF_IF_LOAD_MSK              (((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS)
+#define EF_CTRL_EF_IF_LOAD_UMSK             (~(((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS))
+#define EF_CTRL_EF_IF_CSB                   EF_CTRL_EF_IF_CSB
+#define EF_CTRL_EF_IF_CSB_POS               (15U)
+#define EF_CTRL_EF_IF_CSB_LEN               (1U)
+#define EF_CTRL_EF_IF_CSB_MSK               (((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS)
+#define EF_CTRL_EF_IF_CSB_UMSK              (~(((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS))
+#define EF_CTRL_EF_IF_0_Q                   EF_CTRL_EF_IF_0_Q
+#define EF_CTRL_EF_IF_0_Q_POS               (16U)
+#define EF_CTRL_EF_IF_0_Q_LEN               (8U)
+#define EF_CTRL_EF_IF_0_Q_MSK               (((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS)
+#define EF_CTRL_EF_IF_0_Q_UMSK              (~(((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS))
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL      EF_CTRL_EF_IF_PROT_CODE_MANUAL
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS  (24U)
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN  (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_MSK  (((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS)
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS))
+
+/* 0x810 : ef_if_0_status */
+#define EF_CTRL_EF_IF_0_STATUS_OFFSET (0x810)
+#define EF_CTRL_EF_IF_0_STATUS        EF_CTRL_EF_IF_0_STATUS
+#define EF_CTRL_EF_IF_0_STATUS_POS    (0U)
+#define EF_CTRL_EF_IF_0_STATUS_LEN    (32U)
+#define EF_CTRL_EF_IF_0_STATUS_MSK    (((1U << EF_CTRL_EF_IF_0_STATUS_LEN) - 1) << EF_CTRL_EF_IF_0_STATUS_POS)
+#define EF_CTRL_EF_IF_0_STATUS_UMSK   (~(((1U << EF_CTRL_EF_IF_0_STATUS_LEN) - 1) << EF_CTRL_EF_IF_0_STATUS_POS))
+
+/* 0x814 : ef_if_cfg_0 */
+#define EF_CTRL_EF_IF_CFG_0_OFFSET         (0x814)
+#define EF_CTRL_EF_IF_SF_AES_MODE          EF_CTRL_EF_IF_SF_AES_MODE
+#define EF_CTRL_EF_IF_SF_AES_MODE_POS      (0U)
+#define EF_CTRL_EF_IF_SF_AES_MODE_LEN      (2U)
+#define EF_CTRL_EF_IF_SF_AES_MODE_MSK      (((1U << EF_CTRL_EF_IF_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_IF_SF_AES_MODE_POS)
+#define EF_CTRL_EF_IF_SF_AES_MODE_UMSK     (~(((1U << EF_CTRL_EF_IF_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_IF_SF_AES_MODE_POS))
+#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE      EF_CTRL_EF_IF_SBOOT_SIGN_MODE
+#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS  (2U)
+#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN  (2U)
+#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_MSK  (((1U << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS)
+#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS))
+#define EF_CTRL_EF_IF_SBOOT_EN             EF_CTRL_EF_IF_SBOOT_EN
+#define EF_CTRL_EF_IF_SBOOT_EN_POS         (4U)
+#define EF_CTRL_EF_IF_SBOOT_EN_LEN         (2U)
+#define EF_CTRL_EF_IF_SBOOT_EN_MSK         (((1U << EF_CTRL_EF_IF_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_EN_POS)
+#define EF_CTRL_EF_IF_SBOOT_EN_UMSK        (~(((1U << EF_CTRL_EF_IF_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_EN_POS))
+#define EF_CTRL_EF_IF_CPU1_ENC_EN          EF_CTRL_EF_IF_CPU1_ENC_EN
+#define EF_CTRL_EF_IF_CPU1_ENC_EN_POS      (6U)
+#define EF_CTRL_EF_IF_CPU1_ENC_EN_LEN      (1U)
+#define EF_CTRL_EF_IF_CPU1_ENC_EN_MSK      (((1U << EF_CTRL_EF_IF_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU1_ENC_EN_POS)
+#define EF_CTRL_EF_IF_CPU1_ENC_EN_UMSK     (~(((1U << EF_CTRL_EF_IF_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU1_ENC_EN_POS))
+#define EF_CTRL_EF_IF_CPU0_ENC_EN          EF_CTRL_EF_IF_CPU0_ENC_EN
+#define EF_CTRL_EF_IF_CPU0_ENC_EN_POS      (7U)
+#define EF_CTRL_EF_IF_CPU0_ENC_EN_LEN      (1U)
+#define EF_CTRL_EF_IF_CPU0_ENC_EN_MSK      (((1U << EF_CTRL_EF_IF_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU0_ENC_EN_POS)
+#define EF_CTRL_EF_IF_CPU0_ENC_EN_UMSK     (~(((1U << EF_CTRL_EF_IF_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU0_ENC_EN_POS))
+#define EF_CTRL_EF_IF_BOOT_SEL             EF_CTRL_EF_IF_BOOT_SEL
+#define EF_CTRL_EF_IF_BOOT_SEL_POS         (8U)
+#define EF_CTRL_EF_IF_BOOT_SEL_LEN         (4U)
+#define EF_CTRL_EF_IF_BOOT_SEL_MSK         (((1U << EF_CTRL_EF_IF_BOOT_SEL_LEN) - 1) << EF_CTRL_EF_IF_BOOT_SEL_POS)
+#define EF_CTRL_EF_IF_BOOT_SEL_UMSK        (~(((1U << EF_CTRL_EF_IF_BOOT_SEL_LEN) - 1) << EF_CTRL_EF_IF_BOOT_SEL_POS))
+#define EF_CTRL_EF_IF_SF_KEY_0_SEL         EF_CTRL_EF_IF_SF_KEY_0_SEL
+#define EF_CTRL_EF_IF_SF_KEY_0_SEL_POS     (12U)
+#define EF_CTRL_EF_IF_SF_KEY_0_SEL_LEN     (2U)
+#define EF_CTRL_EF_IF_SF_KEY_0_SEL_MSK     (((1U << EF_CTRL_EF_IF_SF_KEY_0_SEL_LEN) - 1) << EF_CTRL_EF_IF_SF_KEY_0_SEL_POS)
+#define EF_CTRL_EF_IF_SF_KEY_0_SEL_UMSK    (~(((1U << EF_CTRL_EF_IF_SF_KEY_0_SEL_LEN) - 1) << EF_CTRL_EF_IF_SF_KEY_0_SEL_POS))
+#define EF_CTRL_EF_IF_SDU_DIS              EF_CTRL_EF_IF_SDU_DIS
+#define EF_CTRL_EF_IF_SDU_DIS_POS          (14U)
+#define EF_CTRL_EF_IF_SDU_DIS_LEN          (1U)
+#define EF_CTRL_EF_IF_SDU_DIS_MSK          (((1U << EF_CTRL_EF_IF_SDU_DIS_LEN) - 1) << EF_CTRL_EF_IF_SDU_DIS_POS)
+#define EF_CTRL_EF_IF_SDU_DIS_UMSK         (~(((1U << EF_CTRL_EF_IF_SDU_DIS_LEN) - 1) << EF_CTRL_EF_IF_SDU_DIS_POS))
+#define EF_CTRL_EF_IF_BLE_DIS              EF_CTRL_EF_IF_BLE_DIS
+#define EF_CTRL_EF_IF_BLE_DIS_POS          (15U)
+#define EF_CTRL_EF_IF_BLE_DIS_LEN          (1U)
+#define EF_CTRL_EF_IF_BLE_DIS_MSK          (((1U << EF_CTRL_EF_IF_BLE_DIS_LEN) - 1) << EF_CTRL_EF_IF_BLE_DIS_POS)
+#define EF_CTRL_EF_IF_BLE_DIS_UMSK         (~(((1U << EF_CTRL_EF_IF_BLE_DIS_LEN) - 1) << EF_CTRL_EF_IF_BLE_DIS_POS))
+#define EF_CTRL_EF_IF_WIFI_DIS             EF_CTRL_EF_IF_WIFI_DIS
+#define EF_CTRL_EF_IF_WIFI_DIS_POS         (16U)
+#define EF_CTRL_EF_IF_WIFI_DIS_LEN         (1U)
+#define EF_CTRL_EF_IF_WIFI_DIS_MSK         (((1U << EF_CTRL_EF_IF_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_IF_WIFI_DIS_POS)
+#define EF_CTRL_EF_IF_WIFI_DIS_UMSK        (~(((1U << EF_CTRL_EF_IF_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_IF_WIFI_DIS_POS))
+#define EF_CTRL_EF_IF_0_KEY_ENC_EN         EF_CTRL_EF_IF_0_KEY_ENC_EN
+#define EF_CTRL_EF_IF_0_KEY_ENC_EN_POS     (17U)
+#define EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN     (1U)
+#define EF_CTRL_EF_IF_0_KEY_ENC_EN_MSK     (((1U << EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_0_KEY_ENC_EN_POS)
+#define EF_CTRL_EF_IF_0_KEY_ENC_EN_UMSK    (~(((1U << EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_0_KEY_ENC_EN_POS))
+#define EF_CTRL_EF_IF_CAM_DIS              EF_CTRL_EF_IF_CAM_DIS
+#define EF_CTRL_EF_IF_CAM_DIS_POS          (18U)
+#define EF_CTRL_EF_IF_CAM_DIS_LEN          (1U)
+#define EF_CTRL_EF_IF_CAM_DIS_MSK          (((1U << EF_CTRL_EF_IF_CAM_DIS_LEN) - 1) << EF_CTRL_EF_IF_CAM_DIS_POS)
+#define EF_CTRL_EF_IF_CAM_DIS_UMSK         (~(((1U << EF_CTRL_EF_IF_CAM_DIS_LEN) - 1) << EF_CTRL_EF_IF_CAM_DIS_POS))
+#define EF_CTRL_EF_IF_M154_DIS             EF_CTRL_EF_IF_M154_DIS
+#define EF_CTRL_EF_IF_M154_DIS_POS         (19U)
+#define EF_CTRL_EF_IF_M154_DIS_LEN         (1U)
+#define EF_CTRL_EF_IF_M154_DIS_MSK         (((1U << EF_CTRL_EF_IF_M154_DIS_LEN) - 1) << EF_CTRL_EF_IF_M154_DIS_POS)
+#define EF_CTRL_EF_IF_M154_DIS_UMSK        (~(((1U << EF_CTRL_EF_IF_M154_DIS_LEN) - 1) << EF_CTRL_EF_IF_M154_DIS_POS))
+#define EF_CTRL_EF_IF_CPU1_DIS             EF_CTRL_EF_IF_CPU1_DIS
+#define EF_CTRL_EF_IF_CPU1_DIS_POS         (20U)
+#define EF_CTRL_EF_IF_CPU1_DIS_LEN         (1U)
+#define EF_CTRL_EF_IF_CPU1_DIS_MSK         (((1U << EF_CTRL_EF_IF_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU1_DIS_POS)
+#define EF_CTRL_EF_IF_CPU1_DIS_UMSK        (~(((1U << EF_CTRL_EF_IF_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU1_DIS_POS))
+#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS      EF_CTRL_EF_IF_CPU_RST_DBG_DIS
+#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS  (21U)
+#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN  (1U)
+#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_MSK  (((1U << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS)
+#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS))
+#define EF_CTRL_EF_IF_SE_DBG_DIS           EF_CTRL_EF_IF_SE_DBG_DIS
+#define EF_CTRL_EF_IF_SE_DBG_DIS_POS       (22U)
+#define EF_CTRL_EF_IF_SE_DBG_DIS_LEN       (1U)
+#define EF_CTRL_EF_IF_SE_DBG_DIS_MSK       (((1U << EF_CTRL_EF_IF_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_SE_DBG_DIS_POS)
+#define EF_CTRL_EF_IF_SE_DBG_DIS_UMSK      (~(((1U << EF_CTRL_EF_IF_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_SE_DBG_DIS_POS))
+#define EF_CTRL_EF_IF_EFUSE_DBG_DIS        EF_CTRL_EF_IF_EFUSE_DBG_DIS
+#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS    (23U)
+#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN    (1U)
+#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_MSK    (((1U << EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS)
+#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_UMSK   (~(((1U << EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS))
+#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS       EF_CTRL_EF_IF_DBG_JTAG_1_DIS
+#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS   (24U)
+#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN   (2U)
+#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_MSK   (((1U << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS)
+#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_UMSK  (~(((1U << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS))
+#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS       EF_CTRL_EF_IF_DBG_JTAG_0_DIS
+#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS   (26U)
+#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN   (2U)
+#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_MSK   (((1U << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS)
+#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_UMSK  (~(((1U << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS))
+#define EF_CTRL_EF_IF_DBG_MODE             EF_CTRL_EF_IF_DBG_MODE
+#define EF_CTRL_EF_IF_DBG_MODE_POS         (28U)
+#define EF_CTRL_EF_IF_DBG_MODE_LEN         (4U)
+#define EF_CTRL_EF_IF_DBG_MODE_MSK         (((1U << EF_CTRL_EF_IF_DBG_MODE_LEN) - 1) << EF_CTRL_EF_IF_DBG_MODE_POS)
+#define EF_CTRL_EF_IF_DBG_MODE_UMSK        (~(((1U << EF_CTRL_EF_IF_DBG_MODE_LEN) - 1) << EF_CTRL_EF_IF_DBG_MODE_POS))
+
+/* 0x818 : ef_sw_cfg_0 */
+#define EF_CTRL_EF_SW_CFG_0_OFFSET         (0x818)
+#define EF_CTRL_EF_SW_SF_AES_MODE          EF_CTRL_EF_SW_SF_AES_MODE
+#define EF_CTRL_EF_SW_SF_AES_MODE_POS      (0U)
+#define EF_CTRL_EF_SW_SF_AES_MODE_LEN      (2U)
+#define EF_CTRL_EF_SW_SF_AES_MODE_MSK      (((1U << EF_CTRL_EF_SW_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_SW_SF_AES_MODE_POS)
+#define EF_CTRL_EF_SW_SF_AES_MODE_UMSK     (~(((1U << EF_CTRL_EF_SW_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_SW_SF_AES_MODE_POS))
+#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE      EF_CTRL_EF_SW_SBOOT_SIGN_MODE
+#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS  (2U)
+#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN  (2U)
+#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_MSK  (((1U << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS)
+#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS))
+#define EF_CTRL_EF_SW_SBOOT_EN             EF_CTRL_EF_SW_SBOOT_EN
+#define EF_CTRL_EF_SW_SBOOT_EN_POS         (4U)
+#define EF_CTRL_EF_SW_SBOOT_EN_LEN         (2U)
+#define EF_CTRL_EF_SW_SBOOT_EN_MSK         (((1U << EF_CTRL_EF_SW_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_EN_POS)
+#define EF_CTRL_EF_SW_SBOOT_EN_UMSK        (~(((1U << EF_CTRL_EF_SW_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_EN_POS))
+#define EF_CTRL_EF_SW_CPU1_ENC_EN          EF_CTRL_EF_SW_CPU1_ENC_EN
+#define EF_CTRL_EF_SW_CPU1_ENC_EN_POS      (6U)
+#define EF_CTRL_EF_SW_CPU1_ENC_EN_LEN      (1U)
+#define EF_CTRL_EF_SW_CPU1_ENC_EN_MSK      (((1U << EF_CTRL_EF_SW_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU1_ENC_EN_POS)
+#define EF_CTRL_EF_SW_CPU1_ENC_EN_UMSK     (~(((1U << EF_CTRL_EF_SW_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU1_ENC_EN_POS))
+#define EF_CTRL_EF_SW_CPU0_ENC_EN          EF_CTRL_EF_SW_CPU0_ENC_EN
+#define EF_CTRL_EF_SW_CPU0_ENC_EN_POS      (7U)
+#define EF_CTRL_EF_SW_CPU0_ENC_EN_LEN      (1U)
+#define EF_CTRL_EF_SW_CPU0_ENC_EN_MSK      (((1U << EF_CTRL_EF_SW_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU0_ENC_EN_POS)
+#define EF_CTRL_EF_SW_CPU0_ENC_EN_UMSK     (~(((1U << EF_CTRL_EF_SW_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU0_ENC_EN_POS))
+#define EF_CTRL_EF_SW_SF_KEY_0_SEL         EF_CTRL_EF_SW_SF_KEY_0_SEL
+#define EF_CTRL_EF_SW_SF_KEY_0_SEL_POS     (12U)
+#define EF_CTRL_EF_SW_SF_KEY_0_SEL_LEN     (2U)
+#define EF_CTRL_EF_SW_SF_KEY_0_SEL_MSK     (((1U << EF_CTRL_EF_SW_SF_KEY_0_SEL_LEN) - 1) << EF_CTRL_EF_SW_SF_KEY_0_SEL_POS)
+#define EF_CTRL_EF_SW_SF_KEY_0_SEL_UMSK    (~(((1U << EF_CTRL_EF_SW_SF_KEY_0_SEL_LEN) - 1) << EF_CTRL_EF_SW_SF_KEY_0_SEL_POS))
+#define EF_CTRL_EF_SW_SDU_DIS              EF_CTRL_EF_SW_SDU_DIS
+#define EF_CTRL_EF_SW_SDU_DIS_POS          (14U)
+#define EF_CTRL_EF_SW_SDU_DIS_LEN          (1U)
+#define EF_CTRL_EF_SW_SDU_DIS_MSK          (((1U << EF_CTRL_EF_SW_SDU_DIS_LEN) - 1) << EF_CTRL_EF_SW_SDU_DIS_POS)
+#define EF_CTRL_EF_SW_SDU_DIS_UMSK         (~(((1U << EF_CTRL_EF_SW_SDU_DIS_LEN) - 1) << EF_CTRL_EF_SW_SDU_DIS_POS))
+#define EF_CTRL_EF_SW_BLE_DIS              EF_CTRL_EF_SW_BLE_DIS
+#define EF_CTRL_EF_SW_BLE_DIS_POS          (15U)
+#define EF_CTRL_EF_SW_BLE_DIS_LEN          (1U)
+#define EF_CTRL_EF_SW_BLE_DIS_MSK          (((1U << EF_CTRL_EF_SW_BLE_DIS_LEN) - 1) << EF_CTRL_EF_SW_BLE_DIS_POS)
+#define EF_CTRL_EF_SW_BLE_DIS_UMSK         (~(((1U << EF_CTRL_EF_SW_BLE_DIS_LEN) - 1) << EF_CTRL_EF_SW_BLE_DIS_POS))
+#define EF_CTRL_EF_SW_WIFI_DIS             EF_CTRL_EF_SW_WIFI_DIS
+#define EF_CTRL_EF_SW_WIFI_DIS_POS         (16U)
+#define EF_CTRL_EF_SW_WIFI_DIS_LEN         (1U)
+#define EF_CTRL_EF_SW_WIFI_DIS_MSK         (((1U << EF_CTRL_EF_SW_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_SW_WIFI_DIS_POS)
+#define EF_CTRL_EF_SW_WIFI_DIS_UMSK        (~(((1U << EF_CTRL_EF_SW_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_SW_WIFI_DIS_POS))
+#define EF_CTRL_EF_SW_0_KEY_ENC_EN         EF_CTRL_EF_SW_0_KEY_ENC_EN
+#define EF_CTRL_EF_SW_0_KEY_ENC_EN_POS     (17U)
+#define EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN     (1U)
+#define EF_CTRL_EF_SW_0_KEY_ENC_EN_MSK     (((1U << EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_0_KEY_ENC_EN_POS)
+#define EF_CTRL_EF_SW_0_KEY_ENC_EN_UMSK    (~(((1U << EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_0_KEY_ENC_EN_POS))
+#define EF_CTRL_EF_SW_CAM_DIS              EF_CTRL_EF_SW_CAM_DIS
+#define EF_CTRL_EF_SW_CAM_DIS_POS          (18U)
+#define EF_CTRL_EF_SW_CAM_DIS_LEN          (1U)
+#define EF_CTRL_EF_SW_CAM_DIS_MSK          (((1U << EF_CTRL_EF_SW_CAM_DIS_LEN) - 1) << EF_CTRL_EF_SW_CAM_DIS_POS)
+#define EF_CTRL_EF_SW_CAM_DIS_UMSK         (~(((1U << EF_CTRL_EF_SW_CAM_DIS_LEN) - 1) << EF_CTRL_EF_SW_CAM_DIS_POS))
+#define EF_CTRL_EF_SW_M154_DIS             EF_CTRL_EF_SW_M154_DIS
+#define EF_CTRL_EF_SW_M154_DIS_POS         (19U)
+#define EF_CTRL_EF_SW_M154_DIS_LEN         (1U)
+#define EF_CTRL_EF_SW_M154_DIS_MSK         (((1U << EF_CTRL_EF_SW_M154_DIS_LEN) - 1) << EF_CTRL_EF_SW_M154_DIS_POS)
+#define EF_CTRL_EF_SW_M154_DIS_UMSK        (~(((1U << EF_CTRL_EF_SW_M154_DIS_LEN) - 1) << EF_CTRL_EF_SW_M154_DIS_POS))
+#define EF_CTRL_EF_SW_CPU1_DIS             EF_CTRL_EF_SW_CPU1_DIS
+#define EF_CTRL_EF_SW_CPU1_DIS_POS         (20U)
+#define EF_CTRL_EF_SW_CPU1_DIS_LEN         (1U)
+#define EF_CTRL_EF_SW_CPU1_DIS_MSK         (((1U << EF_CTRL_EF_SW_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU1_DIS_POS)
+#define EF_CTRL_EF_SW_CPU1_DIS_UMSK        (~(((1U << EF_CTRL_EF_SW_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU1_DIS_POS))
+#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS      EF_CTRL_EF_SW_CPU_RST_DBG_DIS
+#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS  (21U)
+#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN  (1U)
+#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_MSK  (((1U << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS)
+#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS))
+#define EF_CTRL_EF_SW_SE_DBG_DIS           EF_CTRL_EF_SW_SE_DBG_DIS
+#define EF_CTRL_EF_SW_SE_DBG_DIS_POS       (22U)
+#define EF_CTRL_EF_SW_SE_DBG_DIS_LEN       (1U)
+#define EF_CTRL_EF_SW_SE_DBG_DIS_MSK       (((1U << EF_CTRL_EF_SW_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_SE_DBG_DIS_POS)
+#define EF_CTRL_EF_SW_SE_DBG_DIS_UMSK      (~(((1U << EF_CTRL_EF_SW_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_SE_DBG_DIS_POS))
+#define EF_CTRL_EF_SW_EFUSE_DBG_DIS        EF_CTRL_EF_SW_EFUSE_DBG_DIS
+#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS    (23U)
+#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN    (1U)
+#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_MSK    (((1U << EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS)
+#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_UMSK   (~(((1U << EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS))
+#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS       EF_CTRL_EF_SW_DBG_JTAG_1_DIS
+#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS   (24U)
+#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN   (2U)
+#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_MSK   (((1U << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS)
+#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_UMSK  (~(((1U << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS))
+#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS       EF_CTRL_EF_SW_DBG_JTAG_0_DIS
+#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS   (26U)
+#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN   (2U)
+#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_MSK   (((1U << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS)
+#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_UMSK  (~(((1U << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS))
+#define EF_CTRL_EF_SW_DBG_MODE             EF_CTRL_EF_SW_DBG_MODE
+#define EF_CTRL_EF_SW_DBG_MODE_POS         (28U)
+#define EF_CTRL_EF_SW_DBG_MODE_LEN         (4U)
+#define EF_CTRL_EF_SW_DBG_MODE_MSK         (((1U << EF_CTRL_EF_SW_DBG_MODE_LEN) - 1) << EF_CTRL_EF_SW_DBG_MODE_POS)
+#define EF_CTRL_EF_SW_DBG_MODE_UMSK        (~(((1U << EF_CTRL_EF_SW_DBG_MODE_LEN) - 1) << EF_CTRL_EF_SW_DBG_MODE_POS))
+
+/* 0x81C : ef_reserved */
+#define EF_CTRL_EF_RESERVED_OFFSET (0x81C)
+#define EF_CTRL_EF_RESERVED        EF_CTRL_EF_RESERVED
+#define EF_CTRL_EF_RESERVED_POS    (0U)
+#define EF_CTRL_EF_RESERVED_LEN    (32U)
+#define EF_CTRL_EF_RESERVED_MSK    (((1U << EF_CTRL_EF_RESERVED_LEN) - 1) << EF_CTRL_EF_RESERVED_POS)
+#define EF_CTRL_EF_RESERVED_UMSK   (~(((1U << EF_CTRL_EF_RESERVED_LEN) - 1) << EF_CTRL_EF_RESERVED_POS))
+
+/* 0x820 : ef_if_ana_trim_0 */
+#define EF_CTRL_EF_IF_ANA_TRIM_0_OFFSET (0x820)
+#define EF_CTRL_EF_IF_ANA_TRIM_0        EF_CTRL_EF_IF_ANA_TRIM_0
+#define EF_CTRL_EF_IF_ANA_TRIM_0_POS    (0U)
+#define EF_CTRL_EF_IF_ANA_TRIM_0_LEN    (32U)
+#define EF_CTRL_EF_IF_ANA_TRIM_0_MSK    (((1U << EF_CTRL_EF_IF_ANA_TRIM_0_LEN) - 1) << EF_CTRL_EF_IF_ANA_TRIM_0_POS)
+#define EF_CTRL_EF_IF_ANA_TRIM_0_UMSK   (~(((1U << EF_CTRL_EF_IF_ANA_TRIM_0_LEN) - 1) << EF_CTRL_EF_IF_ANA_TRIM_0_POS))
+
+/* 0x824 : ef_if_sw_usage_0 */
+#define EF_CTRL_EF_IF_SW_USAGE_0_OFFSET (0x824)
+#define EF_CTRL_EF_IF_SW_USAGE_0        EF_CTRL_EF_IF_SW_USAGE_0
+#define EF_CTRL_EF_IF_SW_USAGE_0_POS    (0U)
+#define EF_CTRL_EF_IF_SW_USAGE_0_LEN    (32U)
+#define EF_CTRL_EF_IF_SW_USAGE_0_MSK    (((1U << EF_CTRL_EF_IF_SW_USAGE_0_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_0_POS)
+#define EF_CTRL_EF_IF_SW_USAGE_0_UMSK   (~(((1U << EF_CTRL_EF_IF_SW_USAGE_0_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_0_POS))
+
+/* 0xA00 : ef_crc_ctrl_0 */
+#define EF_CTRL_EF_CRC_CTRL_0_OFFSET    (0xA00)
+#define EF_CTRL_EF_CRC_BUSY             EF_CTRL_EF_CRC_BUSY
+#define EF_CTRL_EF_CRC_BUSY_POS         (0U)
+#define EF_CTRL_EF_CRC_BUSY_LEN         (1U)
+#define EF_CTRL_EF_CRC_BUSY_MSK         (((1U << EF_CTRL_EF_CRC_BUSY_LEN) - 1) << EF_CTRL_EF_CRC_BUSY_POS)
+#define EF_CTRL_EF_CRC_BUSY_UMSK        (~(((1U << EF_CTRL_EF_CRC_BUSY_LEN) - 1) << EF_CTRL_EF_CRC_BUSY_POS))
+#define EF_CTRL_EF_CRC_TRIG             EF_CTRL_EF_CRC_TRIG
+#define EF_CTRL_EF_CRC_TRIG_POS         (1U)
+#define EF_CTRL_EF_CRC_TRIG_LEN         (1U)
+#define EF_CTRL_EF_CRC_TRIG_MSK         (((1U << EF_CTRL_EF_CRC_TRIG_LEN) - 1) << EF_CTRL_EF_CRC_TRIG_POS)
+#define EF_CTRL_EF_CRC_TRIG_UMSK        (~(((1U << EF_CTRL_EF_CRC_TRIG_LEN) - 1) << EF_CTRL_EF_CRC_TRIG_POS))
+#define EF_CTRL_EF_CRC_EN               EF_CTRL_EF_CRC_EN
+#define EF_CTRL_EF_CRC_EN_POS           (2U)
+#define EF_CTRL_EF_CRC_EN_LEN           (1U)
+#define EF_CTRL_EF_CRC_EN_MSK           (((1U << EF_CTRL_EF_CRC_EN_LEN) - 1) << EF_CTRL_EF_CRC_EN_POS)
+#define EF_CTRL_EF_CRC_EN_UMSK          (~(((1U << EF_CTRL_EF_CRC_EN_LEN) - 1) << EF_CTRL_EF_CRC_EN_POS))
+#define EF_CTRL_EF_CRC_MODE             EF_CTRL_EF_CRC_MODE
+#define EF_CTRL_EF_CRC_MODE_POS         (3U)
+#define EF_CTRL_EF_CRC_MODE_LEN         (1U)
+#define EF_CTRL_EF_CRC_MODE_MSK         (((1U << EF_CTRL_EF_CRC_MODE_LEN) - 1) << EF_CTRL_EF_CRC_MODE_POS)
+#define EF_CTRL_EF_CRC_MODE_UMSK        (~(((1U << EF_CTRL_EF_CRC_MODE_LEN) - 1) << EF_CTRL_EF_CRC_MODE_POS))
+#define EF_CTRL_EF_CRC_ERROR            EF_CTRL_EF_CRC_ERROR
+#define EF_CTRL_EF_CRC_ERROR_POS        (4U)
+#define EF_CTRL_EF_CRC_ERROR_LEN        (1U)
+#define EF_CTRL_EF_CRC_ERROR_MSK        (((1U << EF_CTRL_EF_CRC_ERROR_LEN) - 1) << EF_CTRL_EF_CRC_ERROR_POS)
+#define EF_CTRL_EF_CRC_ERROR_UMSK       (~(((1U << EF_CTRL_EF_CRC_ERROR_LEN) - 1) << EF_CTRL_EF_CRC_ERROR_POS))
+#define EF_CTRL_EF_CRC_DOUT_INV_EN      EF_CTRL_EF_CRC_DOUT_INV_EN
+#define EF_CTRL_EF_CRC_DOUT_INV_EN_POS  (5U)
+#define EF_CTRL_EF_CRC_DOUT_INV_EN_LEN  (1U)
+#define EF_CTRL_EF_CRC_DOUT_INV_EN_MSK  (((1U << EF_CTRL_EF_CRC_DOUT_INV_EN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_INV_EN_POS)
+#define EF_CTRL_EF_CRC_DOUT_INV_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_INV_EN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_INV_EN_POS))
+#define EF_CTRL_EF_CRC_DOUT_ENDIAN      EF_CTRL_EF_CRC_DOUT_ENDIAN
+#define EF_CTRL_EF_CRC_DOUT_ENDIAN_POS  (6U)
+#define EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN  (1U)
+#define EF_CTRL_EF_CRC_DOUT_ENDIAN_MSK  (((1U << EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_ENDIAN_POS)
+#define EF_CTRL_EF_CRC_DOUT_ENDIAN_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_ENDIAN_POS))
+#define EF_CTRL_EF_CRC_DIN_ENDIAN       EF_CTRL_EF_CRC_DIN_ENDIAN
+#define EF_CTRL_EF_CRC_DIN_ENDIAN_POS   (7U)
+#define EF_CTRL_EF_CRC_DIN_ENDIAN_LEN   (1U)
+#define EF_CTRL_EF_CRC_DIN_ENDIAN_MSK   (((1U << EF_CTRL_EF_CRC_DIN_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DIN_ENDIAN_POS)
+#define EF_CTRL_EF_CRC_DIN_ENDIAN_UMSK  (~(((1U << EF_CTRL_EF_CRC_DIN_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DIN_ENDIAN_POS))
+#define EF_CTRL_EF_CRC_INT              EF_CTRL_EF_CRC_INT
+#define EF_CTRL_EF_CRC_INT_POS          (8U)
+#define EF_CTRL_EF_CRC_INT_LEN          (1U)
+#define EF_CTRL_EF_CRC_INT_MSK          (((1U << EF_CTRL_EF_CRC_INT_LEN) - 1) << EF_CTRL_EF_CRC_INT_POS)
+#define EF_CTRL_EF_CRC_INT_UMSK         (~(((1U << EF_CTRL_EF_CRC_INT_LEN) - 1) << EF_CTRL_EF_CRC_INT_POS))
+#define EF_CTRL_EF_CRC_INT_CLR          EF_CTRL_EF_CRC_INT_CLR
+#define EF_CTRL_EF_CRC_INT_CLR_POS      (9U)
+#define EF_CTRL_EF_CRC_INT_CLR_LEN      (1U)
+#define EF_CTRL_EF_CRC_INT_CLR_MSK      (((1U << EF_CTRL_EF_CRC_INT_CLR_LEN) - 1) << EF_CTRL_EF_CRC_INT_CLR_POS)
+#define EF_CTRL_EF_CRC_INT_CLR_UMSK     (~(((1U << EF_CTRL_EF_CRC_INT_CLR_LEN) - 1) << EF_CTRL_EF_CRC_INT_CLR_POS))
+#define EF_CTRL_EF_CRC_INT_SET          EF_CTRL_EF_CRC_INT_SET
+#define EF_CTRL_EF_CRC_INT_SET_POS      (10U)
+#define EF_CTRL_EF_CRC_INT_SET_LEN      (1U)
+#define EF_CTRL_EF_CRC_INT_SET_MSK      (((1U << EF_CTRL_EF_CRC_INT_SET_LEN) - 1) << EF_CTRL_EF_CRC_INT_SET_POS)
+#define EF_CTRL_EF_CRC_INT_SET_UMSK     (~(((1U << EF_CTRL_EF_CRC_INT_SET_LEN) - 1) << EF_CTRL_EF_CRC_INT_SET_POS))
+#define EF_CTRL_EF_CRC_LOCK             EF_CTRL_EF_CRC_LOCK
+#define EF_CTRL_EF_CRC_LOCK_POS         (11U)
+#define EF_CTRL_EF_CRC_LOCK_LEN         (1U)
+#define EF_CTRL_EF_CRC_LOCK_MSK         (((1U << EF_CTRL_EF_CRC_LOCK_LEN) - 1) << EF_CTRL_EF_CRC_LOCK_POS)
+#define EF_CTRL_EF_CRC_LOCK_UMSK        (~(((1U << EF_CTRL_EF_CRC_LOCK_LEN) - 1) << EF_CTRL_EF_CRC_LOCK_POS))
+#define EF_CTRL_EF_CRC_SLP_N            EF_CTRL_EF_CRC_SLP_N
+#define EF_CTRL_EF_CRC_SLP_N_POS        (16U)
+#define EF_CTRL_EF_CRC_SLP_N_LEN        (16U)
+#define EF_CTRL_EF_CRC_SLP_N_MSK        (((1U << EF_CTRL_EF_CRC_SLP_N_LEN) - 1) << EF_CTRL_EF_CRC_SLP_N_POS)
+#define EF_CTRL_EF_CRC_SLP_N_UMSK       (~(((1U << EF_CTRL_EF_CRC_SLP_N_LEN) - 1) << EF_CTRL_EF_CRC_SLP_N_POS))
+
+/* 0xA04 : ef_crc_ctrl_1 */
+#define EF_CTRL_EF_CRC_CTRL_1_OFFSET  (0xA04)
+#define EF_CTRL_EF_CRC_DATA_0_EN      EF_CTRL_EF_CRC_DATA_0_EN
+#define EF_CTRL_EF_CRC_DATA_0_EN_POS  (0U)
+#define EF_CTRL_EF_CRC_DATA_0_EN_LEN  (32U)
+#define EF_CTRL_EF_CRC_DATA_0_EN_MSK  (((1U << EF_CTRL_EF_CRC_DATA_0_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_0_EN_POS)
+#define EF_CTRL_EF_CRC_DATA_0_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DATA_0_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_0_EN_POS))
+
+/* 0xA08 : ef_crc_ctrl_2 */
+#define EF_CTRL_EF_CRC_CTRL_2_OFFSET  (0xA08)
+#define EF_CTRL_EF_CRC_DATA_1_EN      EF_CTRL_EF_CRC_DATA_1_EN
+#define EF_CTRL_EF_CRC_DATA_1_EN_POS  (0U)
+#define EF_CTRL_EF_CRC_DATA_1_EN_LEN  (32U)
+#define EF_CTRL_EF_CRC_DATA_1_EN_MSK  (((1U << EF_CTRL_EF_CRC_DATA_1_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_1_EN_POS)
+#define EF_CTRL_EF_CRC_DATA_1_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DATA_1_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_1_EN_POS))
+
+/* 0xA0C : ef_crc_ctrl_3 */
+#define EF_CTRL_EF_CRC_CTRL_3_OFFSET (0xA0C)
+#define EF_CTRL_EF_CRC_IV            EF_CTRL_EF_CRC_IV
+#define EF_CTRL_EF_CRC_IV_POS        (0U)
+#define EF_CTRL_EF_CRC_IV_LEN        (32U)
+#define EF_CTRL_EF_CRC_IV_MSK        (((1U << EF_CTRL_EF_CRC_IV_LEN) - 1) << EF_CTRL_EF_CRC_IV_POS)
+#define EF_CTRL_EF_CRC_IV_UMSK       (~(((1U << EF_CTRL_EF_CRC_IV_LEN) - 1) << EF_CTRL_EF_CRC_IV_POS))
+
+/* 0xA10 : ef_crc_ctrl_4 */
+#define EF_CTRL_EF_CRC_CTRL_4_OFFSET (0xA10)
+#define EF_CTRL_EF_CRC_GOLDEN        EF_CTRL_EF_CRC_GOLDEN
+#define EF_CTRL_EF_CRC_GOLDEN_POS    (0U)
+#define EF_CTRL_EF_CRC_GOLDEN_LEN    (32U)
+#define EF_CTRL_EF_CRC_GOLDEN_MSK    (((1U << EF_CTRL_EF_CRC_GOLDEN_LEN) - 1) << EF_CTRL_EF_CRC_GOLDEN_POS)
+#define EF_CTRL_EF_CRC_GOLDEN_UMSK   (~(((1U << EF_CTRL_EF_CRC_GOLDEN_LEN) - 1) << EF_CTRL_EF_CRC_GOLDEN_POS))
+
+/* 0xA14 : ef_crc_ctrl_5 */
+#define EF_CTRL_EF_CRC_CTRL_5_OFFSET (0xA14)
+#define EF_CTRL_EF_CRC_DOUT          EF_CTRL_EF_CRC_DOUT
+#define EF_CTRL_EF_CRC_DOUT_POS      (0U)
+#define EF_CTRL_EF_CRC_DOUT_LEN      (32U)
+#define EF_CTRL_EF_CRC_DOUT_MSK      (((1U << EF_CTRL_EF_CRC_DOUT_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_POS)
+#define EF_CTRL_EF_CRC_DOUT_UMSK     (~(((1U << EF_CTRL_EF_CRC_DOUT_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_POS))
+
+struct ef_ctrl_reg {
+    /* 0x0  reserved */
+    uint8_t RESERVED0x0[2048];
+
+    /* 0x800 : ef_if_ctrl_0 */
+    union {
+        struct
+        {
+            uint32_t ef_if_0_autoload_p1_done : 1; /* [    0],          r,        0x1 */
+            uint32_t ef_if_0_autoload_done    : 1; /* [    1],          r,        0x1 */
+            uint32_t ef_if_0_busy             : 1; /* [    2],          r,        0x0 */
+            uint32_t ef_if_0_rw               : 1; /* [    3],        r/w,        0x0 */
+            uint32_t ef_if_0_trig             : 1; /* [    4],        r/w,        0x0 */
+            uint32_t ef_if_0_manual_en        : 1; /* [    5],        r/w,        0x0 */
+            uint32_t ef_if_0_cyc_modify       : 1; /* [    6],        r/w,        0x0 */
+            uint32_t ef_clk_sahb_data_sel     : 1; /* [    7],        r/w,        0x0 */
+            uint32_t ef_if_prot_code_ctrl     : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t ef_if_por_dig            : 1; /* [   16],        r/w,        0x0 */
+            uint32_t ef_clk_sahb_data_gate    : 1; /* [   17],        r/w,        0x0 */
+            uint32_t ef_if_auto_rd_en         : 1; /* [   18],        r/w,        0x1 */
+            uint32_t ef_if_cyc_modify_lock    : 1; /* [   19],        r/w,        0x0 */
+            uint32_t ef_if_0_int              : 1; /* [   20],          r,        0x0 */
+            uint32_t ef_if_0_int_clr          : 1; /* [   21],        r/w,        0x1 */
+            uint32_t ef_if_0_int_set          : 1; /* [   22],        r/w,        0x0 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t ef_if_prot_code_cyc      : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_if_ctrl_0;
+
+    /* 0x804 : ef_if_cyc_0 */
+    union {
+        struct
+        {
+            uint32_t ef_if_cyc_rd_dmy  : 6; /* [ 5: 0],        r/w,        0x0 */
+            uint32_t ef_if_cyc_rd_dat  : 6; /* [11: 6],        r/w,        0x1 */
+            uint32_t ef_if_cyc_rd_adr  : 6; /* [17:12],        r/w,        0x0 */
+            uint32_t ef_if_cyc_cs      : 6; /* [23:18],        r/w,        0x0 */
+            uint32_t ef_if_cyc_pd_cs_s : 8; /* [31:24],        r/w,       0x16 */
+        } BF;
+        uint32_t WORD;
+    } ef_if_cyc_0;
+
+    /* 0x808 : ef_if_cyc_1 */
+    union {
+        struct
+        {
+            uint32_t ef_if_cyc_pi      : 6; /* [ 5: 0],        r/w,        0x9 */
+            uint32_t ef_if_cyc_pp      : 8; /* [13: 6],        r/w,       0x98 */
+            uint32_t ef_if_cyc_wr_adr  : 6; /* [19:14],        r/w,        0x1 */
+            uint32_t ef_if_cyc_ps_cs   : 6; /* [25:20],        r/w,        0x2 */
+            uint32_t ef_if_cyc_pd_cs_h : 6; /* [31:26],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_if_cyc_1;
+
+    /* 0x80C : ef_if_0_manual */
+    union {
+        struct
+        {
+            uint32_t ef_if_a                : 10; /* [ 9: 0],        r/w,        0x0 */
+            uint32_t ef_if_pd               : 1;  /* [   10],        r/w,        0x1 */
+            uint32_t ef_if_ps               : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t ef_if_strobe           : 1;  /* [   12],        r/w,        0x0 */
+            uint32_t ef_if_pgenb            : 1;  /* [   13],        r/w,        0x1 */
+            uint32_t ef_if_load             : 1;  /* [   14],        r/w,        0x1 */
+            uint32_t ef_if_csb              : 1;  /* [   15],        r/w,        0x1 */
+            uint32_t ef_if_0_q              : 8;  /* [23:16],          r,        0x0 */
+            uint32_t ef_if_prot_code_manual : 8;  /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_if_0_manual;
+
+    /* 0x810 : ef_if_0_status */
+    union {
+        struct
+        {
+            uint32_t ef_if_0_status : 32; /* [31: 0],          r,     0xe400 */
+        } BF;
+        uint32_t WORD;
+    } ef_if_0_status;
+
+    /* 0x814 : ef_if_cfg_0 */
+    union {
+        struct
+        {
+            uint32_t ef_if_sf_aes_mode     : 2; /* [ 1: 0],          r,        0x0 */
+            uint32_t ef_if_sboot_sign_mode : 2; /* [ 3: 2],          r,        0x0 */
+            uint32_t ef_if_sboot_en        : 2; /* [ 5: 4],          r,        0x0 */
+            uint32_t ef_if_cpu1_enc_en     : 1; /* [    6],          r,        0x0 */
+            uint32_t ef_if_cpu0_enc_en     : 1; /* [    7],          r,        0x0 */
+            uint32_t ef_if_boot_sel        : 4; /* [11: 8],          r,        0x0 */
+            uint32_t ef_if_sf_key_0_sel    : 2; /* [13:12],          r,        0x0 */
+            uint32_t ef_if_sdu_dis         : 1; /* [   14],          r,        0x0 */
+            uint32_t ef_if_ble_dis         : 1; /* [   15],          r,        0x0 */
+            uint32_t ef_if_wifi_dis        : 1; /* [   16],          r,        0x0 */
+            uint32_t ef_if_0_key_enc_en    : 1; /* [   17],          r,        0x0 */
+            uint32_t ef_if_cam_dis         : 1; /* [   18],          r,        0x0 */
+            uint32_t ef_if_m154_dis        : 1; /* [   19],          r,        0x0 */
+            uint32_t ef_if_cpu1_dis        : 1; /* [   20],          r,        0x0 */
+            uint32_t ef_if_cpu_rst_dbg_dis : 1; /* [   21],          r,        0x0 */
+            uint32_t ef_if_se_dbg_dis      : 1; /* [   22],          r,        0x0 */
+            uint32_t ef_if_efuse_dbg_dis   : 1; /* [   23],          r,        0x0 */
+            uint32_t ef_if_dbg_jtag_1_dis  : 2; /* [25:24],          r,        0x0 */
+            uint32_t ef_if_dbg_jtag_0_dis  : 2; /* [27:26],          r,        0x0 */
+            uint32_t ef_if_dbg_mode        : 4; /* [31:28],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_if_cfg_0;
+
+    /* 0x818 : ef_sw_cfg_0 */
+    union {
+        struct
+        {
+            uint32_t ef_sw_sf_aes_mode     : 2; /* [ 1: 0],        r/w,        0x0 */
+            uint32_t ef_sw_sboot_sign_mode : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t ef_sw_sboot_en        : 2; /* [ 5: 4],        r/w,        0x0 */
+            uint32_t ef_sw_cpu1_enc_en     : 1; /* [    6],        r/w,        0x0 */
+            uint32_t ef_sw_cpu0_enc_en     : 1; /* [    7],        r/w,        0x0 */
+            uint32_t reserved_8_11         : 4; /* [11: 8],       rsvd,        0x0 */
+            uint32_t ef_sw_sf_key_0_sel    : 2; /* [13:12],        r/w,        0x0 */
+            uint32_t ef_sw_sdu_dis         : 1; /* [   14],        r/w,        0x0 */
+            uint32_t ef_sw_ble_dis         : 1; /* [   15],        r/w,        0x0 */
+            uint32_t ef_sw_wifi_dis        : 1; /* [   16],        r/w,        0x0 */
+            uint32_t ef_sw_0_key_enc_en    : 1; /* [   17],        r/w,        0x0 */
+            uint32_t ef_sw_cam_dis         : 1; /* [   18],        r/w,        0x0 */
+            uint32_t ef_sw_m154_dis        : 1; /* [   19],        r/w,        0x0 */
+            uint32_t ef_sw_cpu1_dis        : 1; /* [   20],        r/w,        0x0 */
+            uint32_t ef_sw_cpu_rst_dbg_dis : 1; /* [   21],        r/w,        0x0 */
+            uint32_t ef_sw_se_dbg_dis      : 1; /* [   22],        r/w,        0x0 */
+            uint32_t ef_sw_efuse_dbg_dis   : 1; /* [   23],        r/w,        0x0 */
+            uint32_t ef_sw_dbg_jtag_1_dis  : 2; /* [25:24],        r/w,        0x0 */
+            uint32_t ef_sw_dbg_jtag_0_dis  : 2; /* [27:26],        r/w,        0x0 */
+            uint32_t ef_sw_dbg_mode        : 4; /* [31:28],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_sw_cfg_0;
+
+    /* 0x81C : ef_reserved */
+    union {
+        struct
+        {
+            uint32_t ef_reserved : 32; /* [31: 0],        r/w,     0xffff */
+        } BF;
+        uint32_t WORD;
+    } ef_reserved;
+
+    /* 0x820 : ef_if_ana_trim_0 */
+    union {
+        struct
+        {
+            uint32_t ef_if_ana_trim_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_if_ana_trim_0;
+
+    /* 0x824 : ef_if_sw_usage_0 */
+    union {
+        struct
+        {
+            uint32_t ef_if_sw_usage_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_if_sw_usage_0;
+
+    /* 0x828  reserved */
+    uint8_t RESERVED0x828[472];
+
+    /* 0xA00 : ef_crc_ctrl_0 */
+    union {
+        struct
+        {
+            uint32_t ef_crc_busy        : 1;  /* [    0],          r,        0x0 */
+            uint32_t ef_crc_trig        : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t ef_crc_en          : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t ef_crc_mode        : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t ef_crc_error       : 1;  /* [    4],          r,        0x0 */
+            uint32_t ef_crc_dout_inv_en : 1;  /* [    5],        r/w,        0x1 */
+            uint32_t ef_crc_dout_endian : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t ef_crc_din_endian  : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t ef_crc_int         : 1;  /* [    8],          r,        0x0 */
+            uint32_t ef_crc_int_clr     : 1;  /* [    9],        r/w,        0x1 */
+            uint32_t ef_crc_int_set     : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t ef_crc_lock        : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t reserved_12_15     : 4;  /* [15:12],       rsvd,        0x0 */
+            uint32_t ef_crc_slp_n       : 16; /* [31:16],        r/w,       0xff */
+        } BF;
+        uint32_t WORD;
+    } ef_crc_ctrl_0;
+
+    /* 0xA04 : ef_crc_ctrl_1 */
+    union {
+        struct
+        {
+            uint32_t ef_crc_data_0_en : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } ef_crc_ctrl_1;
+
+    /* 0xA08 : ef_crc_ctrl_2 */
+    union {
+        struct
+        {
+            uint32_t ef_crc_data_1_en : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } ef_crc_ctrl_2;
+
+    /* 0xA0C : ef_crc_ctrl_3 */
+    union {
+        struct
+        {
+            uint32_t ef_crc_iv : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } ef_crc_ctrl_3;
+
+    /* 0xA10 : ef_crc_ctrl_4 */
+    union {
+        struct
+        {
+            uint32_t ef_crc_golden : 32; /* [31: 0],        r/w, 0xc2a8fa9dL */
+        } BF;
+        uint32_t WORD;
+    } ef_crc_ctrl_4;
+
+    /* 0xA14 : ef_crc_ctrl_5 */
+    union {
+        struct
+        {
+            uint32_t ef_crc_dout : 32; /* [31: 0],          r, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } ef_crc_ctrl_5;
+};
+
+typedef volatile struct ef_ctrl_reg ef_ctrl_reg_t;
+
+#endif /* __EF_CTRL_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/ef_data_0_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/ef_data_0_reg.h
new file mode 100644
index 00000000..84dec1d3
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/ef_data_0_reg.h
@@ -0,0 +1,762 @@
+/**
+  ******************************************************************************
+  * @file    ef_data_0_reg.h
+  * @version V1.2
+  * @date    2020-04-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __EF_DATA_0_REG_H__
+#define __EF_DATA_0_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : ef_cfg_0 */
+#define EF_DATA_0_EF_CFG_0_OFFSET         (0x0)
+#define EF_DATA_0_EF_SF_AES_MODE          EF_DATA_0_EF_SF_AES_MODE
+#define EF_DATA_0_EF_SF_AES_MODE_POS      (0U)
+#define EF_DATA_0_EF_SF_AES_MODE_LEN      (2U)
+#define EF_DATA_0_EF_SF_AES_MODE_MSK      (((1U << EF_DATA_0_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_0_EF_SF_AES_MODE_POS)
+#define EF_DATA_0_EF_SF_AES_MODE_UMSK     (~(((1U << EF_DATA_0_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_0_EF_SF_AES_MODE_POS))
+#define EF_DATA_0_EF_SBOOT_SIGN_MODE      EF_DATA_0_EF_SBOOT_SIGN_MODE
+#define EF_DATA_0_EF_SBOOT_SIGN_MODE_POS  (2U)
+#define EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN  (2U)
+#define EF_DATA_0_EF_SBOOT_SIGN_MODE_MSK  (((1U << EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_0_EF_SBOOT_SIGN_MODE_POS)
+#define EF_DATA_0_EF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_0_EF_SBOOT_SIGN_MODE_POS))
+#define EF_DATA_0_EF_SBOOT_EN             EF_DATA_0_EF_SBOOT_EN
+#define EF_DATA_0_EF_SBOOT_EN_POS         (4U)
+#define EF_DATA_0_EF_SBOOT_EN_LEN         (2U)
+#define EF_DATA_0_EF_SBOOT_EN_MSK         (((1U << EF_DATA_0_EF_SBOOT_EN_LEN) - 1) << EF_DATA_0_EF_SBOOT_EN_POS)
+#define EF_DATA_0_EF_SBOOT_EN_UMSK        (~(((1U << EF_DATA_0_EF_SBOOT_EN_LEN) - 1) << EF_DATA_0_EF_SBOOT_EN_POS))
+#define EF_DATA_0_EF_CPU0_ENC_EN          EF_DATA_0_EF_CPU0_ENC_EN
+#define EF_DATA_0_EF_CPU0_ENC_EN_POS      (7U)
+#define EF_DATA_0_EF_CPU0_ENC_EN_LEN      (1U)
+#define EF_DATA_0_EF_CPU0_ENC_EN_MSK      (((1U << EF_DATA_0_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_0_EF_CPU0_ENC_EN_POS)
+#define EF_DATA_0_EF_CPU0_ENC_EN_UMSK     (~(((1U << EF_DATA_0_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_0_EF_CPU0_ENC_EN_POS))
+#define EF_DATA_0_EF_BOOT_SEL             EF_DATA_0_EF_BOOT_SEL
+#define EF_DATA_0_EF_BOOT_SEL_POS         (8U)
+#define EF_DATA_0_EF_BOOT_SEL_LEN         (4U)
+#define EF_DATA_0_EF_BOOT_SEL_MSK         (((1U << EF_DATA_0_EF_BOOT_SEL_LEN) - 1) << EF_DATA_0_EF_BOOT_SEL_POS)
+#define EF_DATA_0_EF_BOOT_SEL_UMSK        (~(((1U << EF_DATA_0_EF_BOOT_SEL_LEN) - 1) << EF_DATA_0_EF_BOOT_SEL_POS))
+#define EF_DATA_0_EF_SF_KEY_0_SEL         EF_DATA_0_EF_SF_KEY_0_SEL
+#define EF_DATA_0_EF_SF_KEY_0_SEL_POS     (12U)
+#define EF_DATA_0_EF_SF_KEY_0_SEL_LEN     (2U)
+#define EF_DATA_0_EF_SF_KEY_0_SEL_MSK     (((1U << EF_DATA_0_EF_SF_KEY_0_SEL_LEN) - 1) << EF_DATA_0_EF_SF_KEY_0_SEL_POS)
+#define EF_DATA_0_EF_SF_KEY_0_SEL_UMSK    (~(((1U << EF_DATA_0_EF_SF_KEY_0_SEL_LEN) - 1) << EF_DATA_0_EF_SF_KEY_0_SEL_POS))
+#define EF_DATA_0_EF_0_KEY_ENC_EN         EF_DATA_0_EF_0_KEY_ENC_EN
+#define EF_DATA_0_EF_0_KEY_ENC_EN_POS     (17U)
+#define EF_DATA_0_EF_0_KEY_ENC_EN_LEN     (1U)
+#define EF_DATA_0_EF_0_KEY_ENC_EN_MSK     (((1U << EF_DATA_0_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_0_EF_0_KEY_ENC_EN_POS)
+#define EF_DATA_0_EF_0_KEY_ENC_EN_UMSK    (~(((1U << EF_DATA_0_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_0_EF_0_KEY_ENC_EN_POS))
+#define EF_DATA_0_EF_DBG_JTAG_0_DIS       EF_DATA_0_EF_DBG_JTAG_0_DIS
+#define EF_DATA_0_EF_DBG_JTAG_0_DIS_POS   (26U)
+#define EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN   (2U)
+#define EF_DATA_0_EF_DBG_JTAG_0_DIS_MSK   (((1U << EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_0_DIS_POS)
+#define EF_DATA_0_EF_DBG_JTAG_0_DIS_UMSK  (~(((1U << EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_0_DIS_POS))
+#define EF_DATA_0_EF_DBG_MODE             EF_DATA_0_EF_DBG_MODE
+#define EF_DATA_0_EF_DBG_MODE_POS         (28U)
+#define EF_DATA_0_EF_DBG_MODE_LEN         (4U)
+#define EF_DATA_0_EF_DBG_MODE_MSK         (((1U << EF_DATA_0_EF_DBG_MODE_LEN) - 1) << EF_DATA_0_EF_DBG_MODE_POS)
+#define EF_DATA_0_EF_DBG_MODE_UMSK        (~(((1U << EF_DATA_0_EF_DBG_MODE_LEN) - 1) << EF_DATA_0_EF_DBG_MODE_POS))
+
+/* 0x4 : ef_dbg_pwd_low */
+#define EF_DATA_0_EF_DBG_PWD_LOW_OFFSET (0x4)
+#define EF_DATA_0_EF_DBG_PWD_LOW        EF_DATA_0_EF_DBG_PWD_LOW
+#define EF_DATA_0_EF_DBG_PWD_LOW_POS    (0U)
+#define EF_DATA_0_EF_DBG_PWD_LOW_LEN    (32U)
+#define EF_DATA_0_EF_DBG_PWD_LOW_MSK    (((1U << EF_DATA_0_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_LOW_POS)
+#define EF_DATA_0_EF_DBG_PWD_LOW_UMSK   (~(((1U << EF_DATA_0_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_LOW_POS))
+
+/* 0x8 : ef_dbg_pwd_high */
+#define EF_DATA_0_EF_DBG_PWD_HIGH_OFFSET (0x8)
+#define EF_DATA_0_EF_DBG_PWD_HIGH        EF_DATA_0_EF_DBG_PWD_HIGH
+#define EF_DATA_0_EF_DBG_PWD_HIGH_POS    (0U)
+#define EF_DATA_0_EF_DBG_PWD_HIGH_LEN    (32U)
+#define EF_DATA_0_EF_DBG_PWD_HIGH_MSK    (((1U << EF_DATA_0_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_HIGH_POS)
+#define EF_DATA_0_EF_DBG_PWD_HIGH_UMSK   (~(((1U << EF_DATA_0_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_HIGH_POS))
+
+/* 0xC : ef_ana_trim_0 */
+#define EF_DATA_0_EF_ANA_TRIM_0_OFFSET (0xC)
+#define EF_DATA_0_EF_ANA_TRIM_0        EF_DATA_0_EF_ANA_TRIM_0
+#define EF_DATA_0_EF_ANA_TRIM_0_POS    (0U)
+#define EF_DATA_0_EF_ANA_TRIM_0_LEN    (32U)
+#define EF_DATA_0_EF_ANA_TRIM_0_MSK    (((1U << EF_DATA_0_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_0_POS)
+#define EF_DATA_0_EF_ANA_TRIM_0_UMSK   (~(((1U << EF_DATA_0_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_0_POS))
+
+/* 0x10 : ef_sw_usage_0 */
+#define EF_DATA_0_EF_SW_USAGE_0_OFFSET (0x10)
+#define EF_DATA_0_EF_SW_USAGE_0        EF_DATA_0_EF_SW_USAGE_0
+#define EF_DATA_0_EF_SW_USAGE_0_POS    (0U)
+#define EF_DATA_0_EF_SW_USAGE_0_LEN    (32U)
+#define EF_DATA_0_EF_SW_USAGE_0_MSK    (((1U << EF_DATA_0_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_0_POS)
+#define EF_DATA_0_EF_SW_USAGE_0_UMSK   (~(((1U << EF_DATA_0_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_0_POS))
+
+/* 0x14 : ef_wifi_mac_low */
+#define EF_DATA_0_EF_WIFI_MAC_LOW_OFFSET (0x14)
+#define EF_DATA_0_EF_WIFI_MAC_LOW        EF_DATA_0_EF_WIFI_MAC_LOW
+#define EF_DATA_0_EF_WIFI_MAC_LOW_POS    (0U)
+#define EF_DATA_0_EF_WIFI_MAC_LOW_LEN    (32U)
+#define EF_DATA_0_EF_WIFI_MAC_LOW_MSK    (((1U << EF_DATA_0_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_LOW_POS)
+#define EF_DATA_0_EF_WIFI_MAC_LOW_UMSK   (~(((1U << EF_DATA_0_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_LOW_POS))
+
+/* 0x18 : ef_wifi_mac_high */
+#define EF_DATA_0_EF_WIFI_MAC_HIGH_OFFSET (0x18)
+#define EF_DATA_0_EF_WIFI_MAC_HIGH        EF_DATA_0_EF_WIFI_MAC_HIGH
+#define EF_DATA_0_EF_WIFI_MAC_HIGH_POS    (0U)
+#define EF_DATA_0_EF_WIFI_MAC_HIGH_LEN    (32U)
+#define EF_DATA_0_EF_WIFI_MAC_HIGH_MSK    (((1U << EF_DATA_0_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_HIGH_POS)
+#define EF_DATA_0_EF_WIFI_MAC_HIGH_UMSK   (~(((1U << EF_DATA_0_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_HIGH_POS))
+
+/* 0x1C : ef_key_slot_0_w0 */
+#define EF_DATA_0_EF_KEY_SLOT_0_W0_OFFSET (0x1C)
+#define EF_DATA_0_EF_KEY_SLOT_0_W0        EF_DATA_0_EF_KEY_SLOT_0_W0
+#define EF_DATA_0_EF_KEY_SLOT_0_W0_POS    (0U)
+#define EF_DATA_0_EF_KEY_SLOT_0_W0_LEN    (32U)
+#define EF_DATA_0_EF_KEY_SLOT_0_W0_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W0_POS)
+#define EF_DATA_0_EF_KEY_SLOT_0_W0_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W0_POS))
+
+/* 0x20 : ef_key_slot_0_w1 */
+#define EF_DATA_0_EF_KEY_SLOT_0_W1_OFFSET (0x20)
+#define EF_DATA_0_EF_KEY_SLOT_0_W1        EF_DATA_0_EF_KEY_SLOT_0_W1
+#define EF_DATA_0_EF_KEY_SLOT_0_W1_POS    (0U)
+#define EF_DATA_0_EF_KEY_SLOT_0_W1_LEN    (32U)
+#define EF_DATA_0_EF_KEY_SLOT_0_W1_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W1_POS)
+#define EF_DATA_0_EF_KEY_SLOT_0_W1_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W1_POS))
+
+/* 0x24 : ef_key_slot_0_w2 */
+#define EF_DATA_0_EF_KEY_SLOT_0_W2_OFFSET (0x24)
+#define EF_DATA_0_EF_KEY_SLOT_0_W2        EF_DATA_0_EF_KEY_SLOT_0_W2
+#define EF_DATA_0_EF_KEY_SLOT_0_W2_POS    (0U)
+#define EF_DATA_0_EF_KEY_SLOT_0_W2_LEN    (32U)
+#define EF_DATA_0_EF_KEY_SLOT_0_W2_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W2_POS)
+#define EF_DATA_0_EF_KEY_SLOT_0_W2_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W2_POS))
+
+/* 0x28 : ef_key_slot_0_w3 */
+#define EF_DATA_0_EF_KEY_SLOT_0_W3_OFFSET (0x28)
+#define EF_DATA_0_EF_KEY_SLOT_0_W3        EF_DATA_0_EF_KEY_SLOT_0_W3
+#define EF_DATA_0_EF_KEY_SLOT_0_W3_POS    (0U)
+#define EF_DATA_0_EF_KEY_SLOT_0_W3_LEN    (32U)
+#define EF_DATA_0_EF_KEY_SLOT_0_W3_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W3_POS)
+#define EF_DATA_0_EF_KEY_SLOT_0_W3_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W3_POS))
+
+/* 0x2C : ef_key_slot_1_w0 */
+#define EF_DATA_0_EF_KEY_SLOT_1_W0_OFFSET (0x2C)
+#define EF_DATA_0_EF_KEY_SLOT_1_W0        EF_DATA_0_EF_KEY_SLOT_1_W0
+#define EF_DATA_0_EF_KEY_SLOT_1_W0_POS    (0U)
+#define EF_DATA_0_EF_KEY_SLOT_1_W0_LEN    (32U)
+#define EF_DATA_0_EF_KEY_SLOT_1_W0_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W0_POS)
+#define EF_DATA_0_EF_KEY_SLOT_1_W0_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W0_POS))
+
+/* 0x30 : ef_key_slot_1_w1 */
+#define EF_DATA_0_EF_KEY_SLOT_1_W1_OFFSET (0x30)
+#define EF_DATA_0_EF_KEY_SLOT_1_W1        EF_DATA_0_EF_KEY_SLOT_1_W1
+#define EF_DATA_0_EF_KEY_SLOT_1_W1_POS    (0U)
+#define EF_DATA_0_EF_KEY_SLOT_1_W1_LEN    (32U)
+#define EF_DATA_0_EF_KEY_SLOT_1_W1_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W1_POS)
+#define EF_DATA_0_EF_KEY_SLOT_1_W1_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W1_POS))
+
+/* 0x34 : ef_key_slot_1_w2 */
+#define EF_DATA_0_EF_KEY_SLOT_1_W2_OFFSET (0x34)
+#define EF_DATA_0_EF_KEY_SLOT_1_W2        EF_DATA_0_EF_KEY_SLOT_1_W2
+#define EF_DATA_0_EF_KEY_SLOT_1_W2_POS    (0U)
+#define EF_DATA_0_EF_KEY_SLOT_1_W2_LEN    (32U)
+#define EF_DATA_0_EF_KEY_SLOT_1_W2_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W2_POS)
+#define EF_DATA_0_EF_KEY_SLOT_1_W2_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W2_POS))
+
+/* 0x38 : ef_key_slot_1_w3 */
+#define EF_DATA_0_EF_KEY_SLOT_1_W3_OFFSET (0x38)
+#define EF_DATA_0_EF_KEY_SLOT_1_W3        EF_DATA_0_EF_KEY_SLOT_1_W3
+#define EF_DATA_0_EF_KEY_SLOT_1_W3_POS    (0U)
+#define EF_DATA_0_EF_KEY_SLOT_1_W3_LEN    (32U)
+#define EF_DATA_0_EF_KEY_SLOT_1_W3_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W3_POS)
+#define EF_DATA_0_EF_KEY_SLOT_1_W3_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W3_POS))
+
+/* 0x3C : ef_key_slot_2_w0 */
+#define EF_DATA_0_EF_KEY_SLOT_2_W0_OFFSET (0x3C)
+#define EF_DATA_0_EF_KEY_SLOT_2_W0        EF_DATA_0_EF_KEY_SLOT_2_W0
+#define EF_DATA_0_EF_KEY_SLOT_2_W0_POS    (0U)
+#define EF_DATA_0_EF_KEY_SLOT_2_W0_LEN    (32U)
+#define EF_DATA_0_EF_KEY_SLOT_2_W0_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W0_POS)
+#define EF_DATA_0_EF_KEY_SLOT_2_W0_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W0_POS))
+
+/* 0x40 : ef_key_slot_2_w1 */
+#define EF_DATA_0_EF_KEY_SLOT_2_W1_OFFSET (0x40)
+#define EF_DATA_0_EF_KEY_SLOT_2_W1        EF_DATA_0_EF_KEY_SLOT_2_W1
+#define EF_DATA_0_EF_KEY_SLOT_2_W1_POS    (0U)
+#define EF_DATA_0_EF_KEY_SLOT_2_W1_LEN    (32U)
+#define EF_DATA_0_EF_KEY_SLOT_2_W1_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W1_POS)
+#define EF_DATA_0_EF_KEY_SLOT_2_W1_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W1_POS))
+
+/* 0x44 : ef_key_slot_2_w2 */
+#define EF_DATA_0_EF_KEY_SLOT_2_W2_OFFSET (0x44)
+#define EF_DATA_0_EF_KEY_SLOT_2_W2        EF_DATA_0_EF_KEY_SLOT_2_W2
+#define EF_DATA_0_EF_KEY_SLOT_2_W2_POS    (0U)
+#define EF_DATA_0_EF_KEY_SLOT_2_W2_LEN    (32U)
+#define EF_DATA_0_EF_KEY_SLOT_2_W2_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W2_POS)
+#define EF_DATA_0_EF_KEY_SLOT_2_W2_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W2_POS))
+
+/* 0x48 : ef_key_slot_2_w3 */
+#define EF_DATA_0_EF_KEY_SLOT_2_W3_OFFSET (0x48)
+#define EF_DATA_0_EF_KEY_SLOT_2_W3        EF_DATA_0_EF_KEY_SLOT_2_W3
+#define EF_DATA_0_EF_KEY_SLOT_2_W3_POS    (0U)
+#define EF_DATA_0_EF_KEY_SLOT_2_W3_LEN    (32U)
+#define EF_DATA_0_EF_KEY_SLOT_2_W3_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W3_POS)
+#define EF_DATA_0_EF_KEY_SLOT_2_W3_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W3_POS))
+
+/* 0x4C : ef_key_slot_3_w0 */
+#define EF_DATA_0_EF_KEY_SLOT_3_W0_OFFSET (0x4C)
+#define EF_DATA_0_EF_KEY_SLOT_3_W0        EF_DATA_0_EF_KEY_SLOT_3_W0
+#define EF_DATA_0_EF_KEY_SLOT_3_W0_POS    (0U)
+#define EF_DATA_0_EF_KEY_SLOT_3_W0_LEN    (32U)
+#define EF_DATA_0_EF_KEY_SLOT_3_W0_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W0_POS)
+#define EF_DATA_0_EF_KEY_SLOT_3_W0_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W0_POS))
+
+/* 0x50 : ef_key_slot_3_w1 */
+#define EF_DATA_0_EF_KEY_SLOT_3_W1_OFFSET (0x50)
+#define EF_DATA_0_EF_KEY_SLOT_3_W1        EF_DATA_0_EF_KEY_SLOT_3_W1
+#define EF_DATA_0_EF_KEY_SLOT_3_W1_POS    (0U)
+#define EF_DATA_0_EF_KEY_SLOT_3_W1_LEN    (32U)
+#define EF_DATA_0_EF_KEY_SLOT_3_W1_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W1_POS)
+#define EF_DATA_0_EF_KEY_SLOT_3_W1_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W1_POS))
+
+/* 0x54 : ef_key_slot_3_w2 */
+#define EF_DATA_0_EF_KEY_SLOT_3_W2_OFFSET (0x54)
+#define EF_DATA_0_EF_KEY_SLOT_3_W2        EF_DATA_0_EF_KEY_SLOT_3_W2
+#define EF_DATA_0_EF_KEY_SLOT_3_W2_POS    (0U)
+#define EF_DATA_0_EF_KEY_SLOT_3_W2_LEN    (32U)
+#define EF_DATA_0_EF_KEY_SLOT_3_W2_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W2_POS)
+#define EF_DATA_0_EF_KEY_SLOT_3_W2_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W2_POS))
+
+/* 0x58 : ef_key_slot_3_w3 */
+#define EF_DATA_0_EF_KEY_SLOT_3_W3_OFFSET (0x58)
+#define EF_DATA_0_EF_KEY_SLOT_3_W3        EF_DATA_0_EF_KEY_SLOT_3_W3
+#define EF_DATA_0_EF_KEY_SLOT_3_W3_POS    (0U)
+#define EF_DATA_0_EF_KEY_SLOT_3_W3_LEN    (32U)
+#define EF_DATA_0_EF_KEY_SLOT_3_W3_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W3_POS)
+#define EF_DATA_0_EF_KEY_SLOT_3_W3_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W3_POS))
+
+/* 0x5C : ef_key_slot_4_w0 */
+#define EF_DATA_0_EF_KEY_SLOT_4_W0_OFFSET (0x5C)
+#define EF_DATA_0_EF_KEY_SLOT_4_W0        EF_DATA_0_EF_KEY_SLOT_4_W0
+#define EF_DATA_0_EF_KEY_SLOT_4_W0_POS    (0U)
+#define EF_DATA_0_EF_KEY_SLOT_4_W0_LEN    (32U)
+#define EF_DATA_0_EF_KEY_SLOT_4_W0_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W0_POS)
+#define EF_DATA_0_EF_KEY_SLOT_4_W0_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W0_POS))
+
+/* 0x60 : ef_key_slot_4_w1 */
+#define EF_DATA_0_EF_KEY_SLOT_4_W1_OFFSET (0x60)
+#define EF_DATA_0_EF_KEY_SLOT_4_W1        EF_DATA_0_EF_KEY_SLOT_4_W1
+#define EF_DATA_0_EF_KEY_SLOT_4_W1_POS    (0U)
+#define EF_DATA_0_EF_KEY_SLOT_4_W1_LEN    (32U)
+#define EF_DATA_0_EF_KEY_SLOT_4_W1_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W1_POS)
+#define EF_DATA_0_EF_KEY_SLOT_4_W1_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W1_POS))
+
+/* 0x64 : ef_key_slot_4_w2 */
+#define EF_DATA_0_EF_KEY_SLOT_4_W2_OFFSET (0x64)
+#define EF_DATA_0_EF_KEY_SLOT_4_W2        EF_DATA_0_EF_KEY_SLOT_4_W2
+#define EF_DATA_0_EF_KEY_SLOT_4_W2_POS    (0U)
+#define EF_DATA_0_EF_KEY_SLOT_4_W2_LEN    (32U)
+#define EF_DATA_0_EF_KEY_SLOT_4_W2_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W2_POS)
+#define EF_DATA_0_EF_KEY_SLOT_4_W2_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W2_POS))
+
+/* 0x68 : ef_key_slot_4_w3 */
+#define EF_DATA_0_EF_KEY_SLOT_4_W3_OFFSET (0x68)
+#define EF_DATA_0_EF_KEY_SLOT_4_W3        EF_DATA_0_EF_KEY_SLOT_4_W3
+#define EF_DATA_0_EF_KEY_SLOT_4_W3_POS    (0U)
+#define EF_DATA_0_EF_KEY_SLOT_4_W3_LEN    (32U)
+#define EF_DATA_0_EF_KEY_SLOT_4_W3_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W3_POS)
+#define EF_DATA_0_EF_KEY_SLOT_4_W3_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W3_POS))
+
+/* 0x6C : ef_key_slot_5_w0 */
+#define EF_DATA_0_EF_KEY_SLOT_5_W0_OFFSET (0x6C)
+#define EF_DATA_0_EF_KEY_SLOT_5_W0        EF_DATA_0_EF_KEY_SLOT_5_W0
+#define EF_DATA_0_EF_KEY_SLOT_5_W0_POS    (0U)
+#define EF_DATA_0_EF_KEY_SLOT_5_W0_LEN    (32U)
+#define EF_DATA_0_EF_KEY_SLOT_5_W0_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W0_POS)
+#define EF_DATA_0_EF_KEY_SLOT_5_W0_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W0_POS))
+
+/* 0x70 : ef_key_slot_5_w1 */
+#define EF_DATA_0_EF_KEY_SLOT_5_W1_OFFSET (0x70)
+#define EF_DATA_0_EF_KEY_SLOT_5_W1        EF_DATA_0_EF_KEY_SLOT_5_W1
+#define EF_DATA_0_EF_KEY_SLOT_5_W1_POS    (0U)
+#define EF_DATA_0_EF_KEY_SLOT_5_W1_LEN    (32U)
+#define EF_DATA_0_EF_KEY_SLOT_5_W1_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W1_POS)
+#define EF_DATA_0_EF_KEY_SLOT_5_W1_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W1_POS))
+
+/* 0x74 : ef_key_slot_5_w2 */
+#define EF_DATA_0_EF_KEY_SLOT_5_W2_OFFSET (0x74)
+#define EF_DATA_0_EF_KEY_SLOT_5_W2        EF_DATA_0_EF_KEY_SLOT_5_W2
+#define EF_DATA_0_EF_KEY_SLOT_5_W2_POS    (0U)
+#define EF_DATA_0_EF_KEY_SLOT_5_W2_LEN    (32U)
+#define EF_DATA_0_EF_KEY_SLOT_5_W2_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W2_POS)
+#define EF_DATA_0_EF_KEY_SLOT_5_W2_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W2_POS))
+
+/* 0x78 : ef_key_slot_5_w3 */
+#define EF_DATA_0_EF_KEY_SLOT_5_W3_OFFSET (0x78)
+#define EF_DATA_0_EF_KEY_SLOT_5_W3        EF_DATA_0_EF_KEY_SLOT_5_W3
+#define EF_DATA_0_EF_KEY_SLOT_5_W3_POS    (0U)
+#define EF_DATA_0_EF_KEY_SLOT_5_W3_LEN    (32U)
+#define EF_DATA_0_EF_KEY_SLOT_5_W3_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W3_POS)
+#define EF_DATA_0_EF_KEY_SLOT_5_W3_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W3_POS))
+
+/* 0x7C : ef_data_0_lock */
+#define EF_DATA_0_LOCK_OFFSET               (0x7C)
+#define EF_DATA_0_EF_ANA_TRIM_1             EF_DATA_0_EF_ANA_TRIM_1
+#define EF_DATA_0_EF_ANA_TRIM_1_POS         (0U)
+#define EF_DATA_0_EF_ANA_TRIM_1_LEN         (13U)
+#define EF_DATA_0_EF_ANA_TRIM_1_MSK         (((1U << EF_DATA_0_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_1_POS)
+#define EF_DATA_0_EF_ANA_TRIM_1_UMSK        (~(((1U << EF_DATA_0_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_1_POS))
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L      EF_DATA_0_WR_LOCK_KEY_SLOT_4_L
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS  (13U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN  (1U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_MSK  (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS))
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L      EF_DATA_0_WR_LOCK_KEY_SLOT_5_L
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS  (14U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN  (1U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_MSK  (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS))
+#define EF_DATA_0_WR_LOCK_BOOT_MODE         EF_DATA_0_WR_LOCK_BOOT_MODE
+#define EF_DATA_0_WR_LOCK_BOOT_MODE_POS     (15U)
+#define EF_DATA_0_WR_LOCK_BOOT_MODE_LEN     (1U)
+#define EF_DATA_0_WR_LOCK_BOOT_MODE_MSK     (((1U << EF_DATA_0_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_0_WR_LOCK_BOOT_MODE_POS)
+#define EF_DATA_0_WR_LOCK_BOOT_MODE_UMSK    (~(((1U << EF_DATA_0_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_0_WR_LOCK_BOOT_MODE_POS))
+#define EF_DATA_0_WR_LOCK_DBG_PWD           EF_DATA_0_WR_LOCK_DBG_PWD
+#define EF_DATA_0_WR_LOCK_DBG_PWD_POS       (16U)
+#define EF_DATA_0_WR_LOCK_DBG_PWD_LEN       (1U)
+#define EF_DATA_0_WR_LOCK_DBG_PWD_MSK       (((1U << EF_DATA_0_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_WR_LOCK_DBG_PWD_POS)
+#define EF_DATA_0_WR_LOCK_DBG_PWD_UMSK      (~(((1U << EF_DATA_0_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_WR_LOCK_DBG_PWD_POS))
+#define EF_DATA_0_WR_LOCK_SW_USAGE_0        EF_DATA_0_WR_LOCK_SW_USAGE_0
+#define EF_DATA_0_WR_LOCK_SW_USAGE_0_POS    (17U)
+#define EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN    (1U)
+#define EF_DATA_0_WR_LOCK_SW_USAGE_0_MSK    (((1U << EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_0_POS)
+#define EF_DATA_0_WR_LOCK_SW_USAGE_0_UMSK   (~(((1U << EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_0_POS))
+#define EF_DATA_0_WR_LOCK_WIFI_MAC          EF_DATA_0_WR_LOCK_WIFI_MAC
+#define EF_DATA_0_WR_LOCK_WIFI_MAC_POS      (18U)
+#define EF_DATA_0_WR_LOCK_WIFI_MAC_LEN      (1U)
+#define EF_DATA_0_WR_LOCK_WIFI_MAC_MSK      (((1U << EF_DATA_0_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_0_WR_LOCK_WIFI_MAC_POS)
+#define EF_DATA_0_WR_LOCK_WIFI_MAC_UMSK     (~(((1U << EF_DATA_0_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_0_WR_LOCK_WIFI_MAC_POS))
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_0        EF_DATA_0_WR_LOCK_KEY_SLOT_0
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS    (19U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN    (1U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_MSK    (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_UMSK   (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS))
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_1        EF_DATA_0_WR_LOCK_KEY_SLOT_1
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS    (20U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN    (1U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_MSK    (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_UMSK   (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS))
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_2        EF_DATA_0_WR_LOCK_KEY_SLOT_2
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS    (21U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN    (1U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_MSK    (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_UMSK   (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS))
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_3        EF_DATA_0_WR_LOCK_KEY_SLOT_3
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS    (22U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN    (1U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_MSK    (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_UMSK   (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS))
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H      EF_DATA_0_WR_LOCK_KEY_SLOT_4_H
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS  (23U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN  (1U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_MSK  (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS))
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H      EF_DATA_0_WR_LOCK_KEY_SLOT_5_H
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS  (24U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN  (1U)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_MSK  (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS)
+#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS))
+#define EF_DATA_0_RD_LOCK_DBG_PWD           EF_DATA_0_RD_LOCK_DBG_PWD
+#define EF_DATA_0_RD_LOCK_DBG_PWD_POS       (25U)
+#define EF_DATA_0_RD_LOCK_DBG_PWD_LEN       (1U)
+#define EF_DATA_0_RD_LOCK_DBG_PWD_MSK       (((1U << EF_DATA_0_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_RD_LOCK_DBG_PWD_POS)
+#define EF_DATA_0_RD_LOCK_DBG_PWD_UMSK      (~(((1U << EF_DATA_0_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_RD_LOCK_DBG_PWD_POS))
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_0        EF_DATA_0_RD_LOCK_KEY_SLOT_0
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS    (26U)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN    (1U)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_MSK    (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_UMSK   (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS))
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_1        EF_DATA_0_RD_LOCK_KEY_SLOT_1
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS    (27U)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN    (1U)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_MSK    (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_UMSK   (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS))
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_2        EF_DATA_0_RD_LOCK_KEY_SLOT_2
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS    (28U)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN    (1U)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_MSK    (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_UMSK   (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS))
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_3        EF_DATA_0_RD_LOCK_KEY_SLOT_3
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS    (29U)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN    (1U)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_MSK    (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_UMSK   (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS))
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_4        EF_DATA_0_RD_LOCK_KEY_SLOT_4
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS    (30U)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN    (1U)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_MSK    (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_UMSK   (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS))
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_5        EF_DATA_0_RD_LOCK_KEY_SLOT_5
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS    (31U)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN    (1U)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_MSK    (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS)
+#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_UMSK   (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS))
+
+struct ef_data_0_reg {
+    /* 0x0 : ef_cfg_0 */
+    union {
+        struct
+        {
+            uint32_t ef_sf_aes_mode     : 2; /* [ 1: 0],        r/w,        0x0 */
+            uint32_t ef_sboot_sign_mode : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t rsvd0              : 2; /* [ 5: 4],        r/w,        0x0 */
+            uint32_t rsvd1              : 1; /* [    6],        r/w,        0x0 */
+            uint32_t ef_cpu0_enc_en     : 1; /* [    7],        r/w,        0x0 */
+            uint32_t ef_boot_sel        : 4; /* [11: 8],        r/w,        0x0 */
+            uint32_t ef_sf_key_0_sel    : 2; /* [13:12],        r/w,        0x0 */
+            uint32_t rsvd2              : 1; /* [   14],        r/w,        0x0 */
+            uint32_t rsvd3              : 1; /* [   15],        r/w,        0x0 */
+            uint32_t rsvd4              : 1; /* [   16],        r/w,        0x0 */
+            uint32_t ef_0_key_enc_en    : 1; /* [   17],        r/w,        0x0 */
+            uint32_t rsvd5              : 1; /* [   18],        r/w,        0x0 */
+            uint32_t rsvd6              : 1; /* [   19],        r/w,        0x0 */
+            uint32_t rsvd7              : 1; /* [   20],        r/w,        0x0 */
+            uint32_t rsvd8              : 1; /* [   21],        r/w,        0x0 */
+            uint32_t rsvd9              : 1; /* [   22],        r/w,        0x0 */
+            uint32_t rsvd10             : 1; /* [   23],        r/w,        0x0 */
+            uint32_t rsvd11             : 2; /* [25:24],        r/w,        0x0 */
+            uint32_t ef_dbg_jtag_0_dis  : 2; /* [27:26],        r/w,        0x0 */
+            uint32_t ef_dbg_mode        : 4; /* [31:28],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_cfg_0;
+
+    /* 0x4 : ef_dbg_pwd_low */
+    union {
+        struct
+        {
+            uint32_t ef_dbg_pwd_low : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_dbg_pwd_low;
+
+    /* 0x8 : ef_dbg_pwd_high */
+    union {
+        struct
+        {
+            uint32_t ef_dbg_pwd_high : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_dbg_pwd_high;
+
+    /* 0xC : ef_ana_trim_0 */
+    union {
+        struct
+        {
+            uint32_t ef_ana_trim_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_ana_trim_0;
+
+    /* 0x10 : ef_sw_usage_0 */
+    union {
+        struct
+        {
+            uint32_t ef_sw_usage_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_sw_usage_0;
+
+    /* 0x14 : ef_wifi_mac_low */
+    union {
+        struct
+        {
+            uint32_t ef_wifi_mac_low : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_wifi_mac_low;
+
+    /* 0x18 : ef_wifi_mac_high */
+    union {
+        struct
+        {
+            uint32_t ef_wifi_mac_high : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_wifi_mac_high;
+
+    /* 0x1C : ef_key_slot_0_w0 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_0_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_0_w0;
+
+    /* 0x20 : ef_key_slot_0_w1 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_0_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_0_w1;
+
+    /* 0x24 : ef_key_slot_0_w2 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_0_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_0_w2;
+
+    /* 0x28 : ef_key_slot_0_w3 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_0_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_0_w3;
+
+    /* 0x2C : ef_key_slot_1_w0 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_1_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_1_w0;
+
+    /* 0x30 : ef_key_slot_1_w1 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_1_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_1_w1;
+
+    /* 0x34 : ef_key_slot_1_w2 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_1_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_1_w2;
+
+    /* 0x38 : ef_key_slot_1_w3 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_1_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_1_w3;
+
+    /* 0x3C : ef_key_slot_2_w0 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_2_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_2_w0;
+
+    /* 0x40 : ef_key_slot_2_w1 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_2_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_2_w1;
+
+    /* 0x44 : ef_key_slot_2_w2 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_2_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_2_w2;
+
+    /* 0x48 : ef_key_slot_2_w3 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_2_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_2_w3;
+
+    /* 0x4C : ef_key_slot_3_w0 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_3_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_3_w0;
+
+    /* 0x50 : ef_key_slot_3_w1 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_3_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_3_w1;
+
+    /* 0x54 : ef_key_slot_3_w2 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_3_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_3_w2;
+
+    /* 0x58 : ef_key_slot_3_w3 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_3_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_3_w3;
+
+    /* 0x5C : ef_key_slot_4_w0 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_4_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_4_w0;
+
+    /* 0x60 : ef_key_slot_4_w1 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_4_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_4_w1;
+
+    /* 0x64 : ef_key_slot_4_w2 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_4_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_4_w2;
+
+    /* 0x68 : ef_key_slot_4_w3 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_4_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_4_w3;
+
+    /* 0x6C : ef_key_slot_5_w0 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_5_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_5_w0;
+
+    /* 0x70 : ef_key_slot_5_w1 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_5_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_5_w1;
+
+    /* 0x74 : ef_key_slot_5_w2 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_5_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_5_w2;
+
+    /* 0x78 : ef_key_slot_5_w3 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_5_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_5_w3;
+
+    /* 0x7C : ef_data_0_lock */
+    union {
+        struct
+        {
+            uint32_t ef_ana_trim_1        : 13; /* [12: 0],        r/w,        0x0 */
+            uint32_t wr_lock_key_slot_4_l : 1;  /* [   13],        r/w,        0x0 */
+            uint32_t wr_lock_key_slot_5_l : 1;  /* [   14],        r/w,        0x0 */
+            uint32_t wr_lock_boot_mode    : 1;  /* [   15],        r/w,        0x0 */
+            uint32_t wr_lock_dbg_pwd      : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t wr_lock_sw_usage_0   : 1;  /* [   17],        r/w,        0x0 */
+            uint32_t wr_lock_wifi_mac     : 1;  /* [   18],        r/w,        0x0 */
+            uint32_t wr_lock_key_slot_0   : 1;  /* [   19],        r/w,        0x0 */
+            uint32_t wr_lock_key_slot_1   : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t wr_lock_key_slot_2   : 1;  /* [   21],        r/w,        0x0 */
+            uint32_t wr_lock_key_slot_3   : 1;  /* [   22],        r/w,        0x0 */
+            uint32_t wr_lock_key_slot_4_h : 1;  /* [   23],        r/w,        0x0 */
+            uint32_t wr_lock_key_slot_5_h : 1;  /* [   24],        r/w,        0x0 */
+            uint32_t rd_lock_dbg_pwd      : 1;  /* [   25],        r/w,        0x0 */
+            uint32_t rd_lock_key_slot_0   : 1;  /* [   26],        r/w,        0x0 */
+            uint32_t rd_lock_key_slot_1   : 1;  /* [   27],        r/w,        0x0 */
+            uint32_t rd_lock_key_slot_2   : 1;  /* [   28],        r/w,        0x0 */
+            uint32_t rd_lock_key_slot_3   : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t rd_lock_key_slot_4   : 1;  /* [   30],        r/w,        0x0 */
+            uint32_t rd_lock_key_slot_5   : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_data_0_lock;
+};
+
+typedef volatile struct ef_data_0_reg ef_data_0_reg_t;
+
+#endif /* __EF_DATA_0_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/emac_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/emac_reg.h
new file mode 100644
index 00000000..bf32c19a
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/emac_reg.h
@@ -0,0 +1,601 @@
+/**
+  ******************************************************************************
+  * @file    emac_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __EMAC_REG_H__
+#define __EMAC_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : MODE */
+#define EMAC_MODE_OFFSET   (0x0)
+#define EMAC_RXEN          EMAC_RXEN
+#define EMAC_RXEN_POS      (0U)
+#define EMAC_RXEN_LEN      (1U)
+#define EMAC_RXEN_MSK      (((1U << EMAC_RXEN_LEN) - 1) << EMAC_RXEN_POS)
+#define EMAC_RXEN_UMSK     (~(((1U << EMAC_RXEN_LEN) - 1) << EMAC_RXEN_POS))
+#define EMAC_TXEN          EMAC_TXEN
+#define EMAC_TXEN_POS      (1U)
+#define EMAC_TXEN_LEN      (1U)
+#define EMAC_TXEN_MSK      (((1U << EMAC_TXEN_LEN) - 1) << EMAC_TXEN_POS)
+#define EMAC_TXEN_UMSK     (~(((1U << EMAC_TXEN_LEN) - 1) << EMAC_TXEN_POS))
+#define EMAC_NOPRE         EMAC_NOPRE
+#define EMAC_NOPRE_POS     (2U)
+#define EMAC_NOPRE_LEN     (1U)
+#define EMAC_NOPRE_MSK     (((1U << EMAC_NOPRE_LEN) - 1) << EMAC_NOPRE_POS)
+#define EMAC_NOPRE_UMSK    (~(((1U << EMAC_NOPRE_LEN) - 1) << EMAC_NOPRE_POS))
+#define EMAC_BRO           EMAC_BRO
+#define EMAC_BRO_POS       (3U)
+#define EMAC_BRO_LEN       (1U)
+#define EMAC_BRO_MSK       (((1U << EMAC_BRO_LEN) - 1) << EMAC_BRO_POS)
+#define EMAC_BRO_UMSK      (~(((1U << EMAC_BRO_LEN) - 1) << EMAC_BRO_POS))
+#define EMAC_PRO           EMAC_PRO
+#define EMAC_PRO_POS       (5U)
+#define EMAC_PRO_LEN       (1U)
+#define EMAC_PRO_MSK       (((1U << EMAC_PRO_LEN) - 1) << EMAC_PRO_POS)
+#define EMAC_PRO_UMSK      (~(((1U << EMAC_PRO_LEN) - 1) << EMAC_PRO_POS))
+#define EMAC_IFG           EMAC_IFG
+#define EMAC_IFG_POS       (6U)
+#define EMAC_IFG_LEN       (1U)
+#define EMAC_IFG_MSK       (((1U << EMAC_IFG_LEN) - 1) << EMAC_IFG_POS)
+#define EMAC_IFG_UMSK      (~(((1U << EMAC_IFG_LEN) - 1) << EMAC_IFG_POS))
+#define EMAC_FULLD         EMAC_FULLD
+#define EMAC_FULLD_POS     (10U)
+#define EMAC_FULLD_LEN     (1U)
+#define EMAC_FULLD_MSK     (((1U << EMAC_FULLD_LEN) - 1) << EMAC_FULLD_POS)
+#define EMAC_FULLD_UMSK    (~(((1U << EMAC_FULLD_LEN) - 1) << EMAC_FULLD_POS))
+#define EMAC_CRCEN         EMAC_CRCEN
+#define EMAC_CRCEN_POS     (13U)
+#define EMAC_CRCEN_LEN     (1U)
+#define EMAC_CRCEN_MSK     (((1U << EMAC_CRCEN_LEN) - 1) << EMAC_CRCEN_POS)
+#define EMAC_CRCEN_UMSK    (~(((1U << EMAC_CRCEN_LEN) - 1) << EMAC_CRCEN_POS))
+#define EMAC_HUGEN         EMAC_HUGEN
+#define EMAC_HUGEN_POS     (14U)
+#define EMAC_HUGEN_LEN     (1U)
+#define EMAC_HUGEN_MSK     (((1U << EMAC_HUGEN_LEN) - 1) << EMAC_HUGEN_POS)
+#define EMAC_HUGEN_UMSK    (~(((1U << EMAC_HUGEN_LEN) - 1) << EMAC_HUGEN_POS))
+#define EMAC_PAD           EMAC_PAD
+#define EMAC_PAD_POS       (15U)
+#define EMAC_PAD_LEN       (1U)
+#define EMAC_PAD_MSK       (((1U << EMAC_PAD_LEN) - 1) << EMAC_PAD_POS)
+#define EMAC_PAD_UMSK      (~(((1U << EMAC_PAD_LEN) - 1) << EMAC_PAD_POS))
+#define EMAC_RECSMALL      EMAC_RECSMALL
+#define EMAC_RECSMALL_POS  (16U)
+#define EMAC_RECSMALL_LEN  (1U)
+#define EMAC_RECSMALL_MSK  (((1U << EMAC_RECSMALL_LEN) - 1) << EMAC_RECSMALL_POS)
+#define EMAC_RECSMALL_UMSK (~(((1U << EMAC_RECSMALL_LEN) - 1) << EMAC_RECSMALL_POS))
+#define EMAC_RMII_EN       EMAC_RMII_EN
+#define EMAC_RMII_EN_POS   (17U)
+#define EMAC_RMII_EN_LEN   (1U)
+#define EMAC_RMII_EN_MSK   (((1U << EMAC_RMII_EN_LEN) - 1) << EMAC_RMII_EN_POS)
+#define EMAC_RMII_EN_UMSK  (~(((1U << EMAC_RMII_EN_LEN) - 1) << EMAC_RMII_EN_POS))
+
+/* 0x4 : INT_SOURCE */
+#define EMAC_INT_SOURCE_OFFSET (0x4)
+#define EMAC_TXB               EMAC_TXB
+#define EMAC_TXB_POS           (0U)
+#define EMAC_TXB_LEN           (1U)
+#define EMAC_TXB_MSK           (((1U << EMAC_TXB_LEN) - 1) << EMAC_TXB_POS)
+#define EMAC_TXB_UMSK          (~(((1U << EMAC_TXB_LEN) - 1) << EMAC_TXB_POS))
+#define EMAC_TXE               EMAC_TXE
+#define EMAC_TXE_POS           (1U)
+#define EMAC_TXE_LEN           (1U)
+#define EMAC_TXE_MSK           (((1U << EMAC_TXE_LEN) - 1) << EMAC_TXE_POS)
+#define EMAC_TXE_UMSK          (~(((1U << EMAC_TXE_LEN) - 1) << EMAC_TXE_POS))
+#define EMAC_RXB               EMAC_RXB
+#define EMAC_RXB_POS           (2U)
+#define EMAC_RXB_LEN           (1U)
+#define EMAC_RXB_MSK           (((1U << EMAC_RXB_LEN) - 1) << EMAC_RXB_POS)
+#define EMAC_RXB_UMSK          (~(((1U << EMAC_RXB_LEN) - 1) << EMAC_RXB_POS))
+#define EMAC_RXE               EMAC_RXE
+#define EMAC_RXE_POS           (3U)
+#define EMAC_RXE_LEN           (1U)
+#define EMAC_RXE_MSK           (((1U << EMAC_RXE_LEN) - 1) << EMAC_RXE_POS)
+#define EMAC_RXE_UMSK          (~(((1U << EMAC_RXE_LEN) - 1) << EMAC_RXE_POS))
+#define EMAC_BUSY              EMAC_BUSY
+#define EMAC_BUSY_POS          (4U)
+#define EMAC_BUSY_LEN          (1U)
+#define EMAC_BUSY_MSK          (((1U << EMAC_BUSY_LEN) - 1) << EMAC_BUSY_POS)
+#define EMAC_BUSY_UMSK         (~(((1U << EMAC_BUSY_LEN) - 1) << EMAC_BUSY_POS))
+#define EMAC_TXC               EMAC_TXC
+#define EMAC_TXC_POS           (5U)
+#define EMAC_TXC_LEN           (1U)
+#define EMAC_TXC_MSK           (((1U << EMAC_TXC_LEN) - 1) << EMAC_TXC_POS)
+#define EMAC_TXC_UMSK          (~(((1U << EMAC_TXC_LEN) - 1) << EMAC_TXC_POS))
+#define EMAC_RXC               EMAC_RXC
+#define EMAC_RXC_POS           (6U)
+#define EMAC_RXC_LEN           (1U)
+#define EMAC_RXC_MSK           (((1U << EMAC_RXC_LEN) - 1) << EMAC_RXC_POS)
+#define EMAC_RXC_UMSK          (~(((1U << EMAC_RXC_LEN) - 1) << EMAC_RXC_POS))
+
+/* 0x8 : INT_MASK */
+#define EMAC_INT_MASK_OFFSET (0x8)
+#define EMAC_TXB_M           EMAC_TXB_M
+#define EMAC_TXB_M_POS       (0U)
+#define EMAC_TXB_M_LEN       (1U)
+#define EMAC_TXB_M_MSK       (((1U << EMAC_TXB_M_LEN) - 1) << EMAC_TXB_M_POS)
+#define EMAC_TXB_M_UMSK      (~(((1U << EMAC_TXB_M_LEN) - 1) << EMAC_TXB_M_POS))
+#define EMAC_TXE_M           EMAC_TXE_M
+#define EMAC_TXE_M_POS       (1U)
+#define EMAC_TXE_M_LEN       (1U)
+#define EMAC_TXE_M_MSK       (((1U << EMAC_TXE_M_LEN) - 1) << EMAC_TXE_M_POS)
+#define EMAC_TXE_M_UMSK      (~(((1U << EMAC_TXE_M_LEN) - 1) << EMAC_TXE_M_POS))
+#define EMAC_RXB_M           EMAC_RXB_M
+#define EMAC_RXB_M_POS       (2U)
+#define EMAC_RXB_M_LEN       (1U)
+#define EMAC_RXB_M_MSK       (((1U << EMAC_RXB_M_LEN) - 1) << EMAC_RXB_M_POS)
+#define EMAC_RXB_M_UMSK      (~(((1U << EMAC_RXB_M_LEN) - 1) << EMAC_RXB_M_POS))
+#define EMAC_RXE_M           EMAC_RXE_M
+#define EMAC_RXE_M_POS       (3U)
+#define EMAC_RXE_M_LEN       (1U)
+#define EMAC_RXE_M_MSK       (((1U << EMAC_RXE_M_LEN) - 1) << EMAC_RXE_M_POS)
+#define EMAC_RXE_M_UMSK      (~(((1U << EMAC_RXE_M_LEN) - 1) << EMAC_RXE_M_POS))
+#define EMAC_BUSY_M          EMAC_BUSY_M
+#define EMAC_BUSY_M_POS      (4U)
+#define EMAC_BUSY_M_LEN      (1U)
+#define EMAC_BUSY_M_MSK      (((1U << EMAC_BUSY_M_LEN) - 1) << EMAC_BUSY_M_POS)
+#define EMAC_BUSY_M_UMSK     (~(((1U << EMAC_BUSY_M_LEN) - 1) << EMAC_BUSY_M_POS))
+#define EMAC_TXC_M           EMAC_TXC_M
+#define EMAC_TXC_M_POS       (5U)
+#define EMAC_TXC_M_LEN       (1U)
+#define EMAC_TXC_M_MSK       (((1U << EMAC_TXC_M_LEN) - 1) << EMAC_TXC_M_POS)
+#define EMAC_TXC_M_UMSK      (~(((1U << EMAC_TXC_M_LEN) - 1) << EMAC_TXC_M_POS))
+#define EMAC_RXC_M           EMAC_RXC_M
+#define EMAC_RXC_M_POS       (6U)
+#define EMAC_RXC_M_LEN       (1U)
+#define EMAC_RXC_M_MSK       (((1U << EMAC_RXC_M_LEN) - 1) << EMAC_RXC_M_POS)
+#define EMAC_RXC_M_UMSK      (~(((1U << EMAC_RXC_M_LEN) - 1) << EMAC_RXC_M_POS))
+
+/* 0xC : IPGT */
+#define EMAC_IPGT_OFFSET (0xC)
+#define EMAC_IPGT        EMAC_IPGT
+#define EMAC_IPGT_POS    (0U)
+#define EMAC_IPGT_LEN    (7U)
+#define EMAC_IPGT_MSK    (((1U << EMAC_IPGT_LEN) - 1) << EMAC_IPGT_POS)
+#define EMAC_IPGT_UMSK   (~(((1U << EMAC_IPGT_LEN) - 1) << EMAC_IPGT_POS))
+
+/* 0x18 : PACKETLEN */
+#define EMAC_PACKETLEN_OFFSET (0x18)
+#define EMAC_MAXFL            EMAC_MAXFL
+#define EMAC_MAXFL_POS        (0U)
+#define EMAC_MAXFL_LEN        (16U)
+#define EMAC_MAXFL_MSK        (((1U << EMAC_MAXFL_LEN) - 1) << EMAC_MAXFL_POS)
+#define EMAC_MAXFL_UMSK       (~(((1U << EMAC_MAXFL_LEN) - 1) << EMAC_MAXFL_POS))
+#define EMAC_MINFL            EMAC_MINFL
+#define EMAC_MINFL_POS        (16U)
+#define EMAC_MINFL_LEN        (16U)
+#define EMAC_MINFL_MSK        (((1U << EMAC_MINFL_LEN) - 1) << EMAC_MINFL_POS)
+#define EMAC_MINFL_UMSK       (~(((1U << EMAC_MINFL_LEN) - 1) << EMAC_MINFL_POS))
+
+/* 0x1C : COLLCONFIG */
+#define EMAC_COLLCONFIG_OFFSET (0x1C)
+#define EMAC_COLLVALID         EMAC_COLLVALID
+#define EMAC_COLLVALID_POS     (0U)
+#define EMAC_COLLVALID_LEN     (6U)
+#define EMAC_COLLVALID_MSK     (((1U << EMAC_COLLVALID_LEN) - 1) << EMAC_COLLVALID_POS)
+#define EMAC_COLLVALID_UMSK    (~(((1U << EMAC_COLLVALID_LEN) - 1) << EMAC_COLLVALID_POS))
+#define EMAC_MAXRET            EMAC_MAXRET
+#define EMAC_MAXRET_POS        (16U)
+#define EMAC_MAXRET_LEN        (4U)
+#define EMAC_MAXRET_MSK        (((1U << EMAC_MAXRET_LEN) - 1) << EMAC_MAXRET_POS)
+#define EMAC_MAXRET_UMSK       (~(((1U << EMAC_MAXRET_LEN) - 1) << EMAC_MAXRET_POS))
+
+/* 0x20 : TX_BD_NUM */
+#define EMAC_TX_BD_NUM_OFFSET (0x20)
+#define EMAC_TXBDNUM          EMAC_TXBDNUM
+#define EMAC_TXBDNUM_POS      (0U)
+#define EMAC_TXBDNUM_LEN      (8U)
+#define EMAC_TXBDNUM_MSK      (((1U << EMAC_TXBDNUM_LEN) - 1) << EMAC_TXBDNUM_POS)
+#define EMAC_TXBDNUM_UMSK     (~(((1U << EMAC_TXBDNUM_LEN) - 1) << EMAC_TXBDNUM_POS))
+#define EMAC_TXBDPTR          EMAC_TXBDPTR
+#define EMAC_TXBDPTR_POS      (16U)
+#define EMAC_TXBDPTR_LEN      (7U)
+#define EMAC_TXBDPTR_MSK      (((1U << EMAC_TXBDPTR_LEN) - 1) << EMAC_TXBDPTR_POS)
+#define EMAC_TXBDPTR_UMSK     (~(((1U << EMAC_TXBDPTR_LEN) - 1) << EMAC_TXBDPTR_POS))
+#define EMAC_RXBDPTR          EMAC_RXBDPTR
+#define EMAC_RXBDPTR_POS      (24U)
+#define EMAC_RXBDPTR_LEN      (7U)
+#define EMAC_RXBDPTR_MSK      (((1U << EMAC_RXBDPTR_LEN) - 1) << EMAC_RXBDPTR_POS)
+#define EMAC_RXBDPTR_UMSK     (~(((1U << EMAC_RXBDPTR_LEN) - 1) << EMAC_RXBDPTR_POS))
+
+/* 0x28 : MIIMODE */
+#define EMAC_MIIMODE_OFFSET (0x28)
+#define EMAC_CLKDIV         EMAC_CLKDIV
+#define EMAC_CLKDIV_POS     (0U)
+#define EMAC_CLKDIV_LEN     (8U)
+#define EMAC_CLKDIV_MSK     (((1U << EMAC_CLKDIV_LEN) - 1) << EMAC_CLKDIV_POS)
+#define EMAC_CLKDIV_UMSK    (~(((1U << EMAC_CLKDIV_LEN) - 1) << EMAC_CLKDIV_POS))
+#define EMAC_MIINOPRE       EMAC_MIINOPRE
+#define EMAC_MIINOPRE_POS   (8U)
+#define EMAC_MIINOPRE_LEN   (1U)
+#define EMAC_MIINOPRE_MSK   (((1U << EMAC_MIINOPRE_LEN) - 1) << EMAC_MIINOPRE_POS)
+#define EMAC_MIINOPRE_UMSK  (~(((1U << EMAC_MIINOPRE_LEN) - 1) << EMAC_MIINOPRE_POS))
+
+/* 0x2C : MIICOMMAND */
+#define EMAC_MIICOMMAND_OFFSET (0x2C)
+#define EMAC_SCANSTAT          EMAC_SCANSTAT
+#define EMAC_SCANSTAT_POS      (0U)
+#define EMAC_SCANSTAT_LEN      (1U)
+#define EMAC_SCANSTAT_MSK      (((1U << EMAC_SCANSTAT_LEN) - 1) << EMAC_SCANSTAT_POS)
+#define EMAC_SCANSTAT_UMSK     (~(((1U << EMAC_SCANSTAT_LEN) - 1) << EMAC_SCANSTAT_POS))
+#define EMAC_RSTAT             EMAC_RSTAT
+#define EMAC_RSTAT_POS         (1U)
+#define EMAC_RSTAT_LEN         (1U)
+#define EMAC_RSTAT_MSK         (((1U << EMAC_RSTAT_LEN) - 1) << EMAC_RSTAT_POS)
+#define EMAC_RSTAT_UMSK        (~(((1U << EMAC_RSTAT_LEN) - 1) << EMAC_RSTAT_POS))
+#define EMAC_WCTRLDATA         EMAC_WCTRLDATA
+#define EMAC_WCTRLDATA_POS     (2U)
+#define EMAC_WCTRLDATA_LEN     (1U)
+#define EMAC_WCTRLDATA_MSK     (((1U << EMAC_WCTRLDATA_LEN) - 1) << EMAC_WCTRLDATA_POS)
+#define EMAC_WCTRLDATA_UMSK    (~(((1U << EMAC_WCTRLDATA_LEN) - 1) << EMAC_WCTRLDATA_POS))
+
+/* 0x30 : MIIADDRESS */
+#define EMAC_MIIADDRESS_OFFSET (0x30)
+#define EMAC_FIAD              EMAC_FIAD
+#define EMAC_FIAD_POS          (0U)
+#define EMAC_FIAD_LEN          (5U)
+#define EMAC_FIAD_MSK          (((1U << EMAC_FIAD_LEN) - 1) << EMAC_FIAD_POS)
+#define EMAC_FIAD_UMSK         (~(((1U << EMAC_FIAD_LEN) - 1) << EMAC_FIAD_POS))
+#define EMAC_RGAD              EMAC_RGAD
+#define EMAC_RGAD_POS          (8U)
+#define EMAC_RGAD_LEN          (5U)
+#define EMAC_RGAD_MSK          (((1U << EMAC_RGAD_LEN) - 1) << EMAC_RGAD_POS)
+#define EMAC_RGAD_UMSK         (~(((1U << EMAC_RGAD_LEN) - 1) << EMAC_RGAD_POS))
+
+/* 0x34 : MIITX_DATA */
+#define EMAC_MIITX_DATA_OFFSET (0x34)
+#define EMAC_CTRLDATA          EMAC_CTRLDATA
+#define EMAC_CTRLDATA_POS      (0U)
+#define EMAC_CTRLDATA_LEN      (16U)
+#define EMAC_CTRLDATA_MSK      (((1U << EMAC_CTRLDATA_LEN) - 1) << EMAC_CTRLDATA_POS)
+#define EMAC_CTRLDATA_UMSK     (~(((1U << EMAC_CTRLDATA_LEN) - 1) << EMAC_CTRLDATA_POS))
+
+/* 0x38 : MIIRX_DATA */
+#define EMAC_MIIRX_DATA_OFFSET (0x38)
+#define EMAC_PRSD              EMAC_PRSD
+#define EMAC_PRSD_POS          (0U)
+#define EMAC_PRSD_LEN          (16U)
+#define EMAC_PRSD_MSK          (((1U << EMAC_PRSD_LEN) - 1) << EMAC_PRSD_POS)
+#define EMAC_PRSD_UMSK         (~(((1U << EMAC_PRSD_LEN) - 1) << EMAC_PRSD_POS))
+
+/* 0x3C : MIISTATUS */
+#define EMAC_MIISTATUS_OFFSET   (0x3C)
+#define EMAC_MIIM_LINKFAIL      EMAC_MIIM_LINKFAIL
+#define EMAC_MIIM_LINKFAIL_POS  (0U)
+#define EMAC_MIIM_LINKFAIL_LEN  (1U)
+#define EMAC_MIIM_LINKFAIL_MSK  (((1U << EMAC_MIIM_LINKFAIL_LEN) - 1) << EMAC_MIIM_LINKFAIL_POS)
+#define EMAC_MIIM_LINKFAIL_UMSK (~(((1U << EMAC_MIIM_LINKFAIL_LEN) - 1) << EMAC_MIIM_LINKFAIL_POS))
+#define EMAC_MIIM_BUSY          EMAC_MIIM_BUSY
+#define EMAC_MIIM_BUSY_POS      (1U)
+#define EMAC_MIIM_BUSY_LEN      (1U)
+#define EMAC_MIIM_BUSY_MSK      (((1U << EMAC_MIIM_BUSY_LEN) - 1) << EMAC_MIIM_BUSY_POS)
+#define EMAC_MIIM_BUSY_UMSK     (~(((1U << EMAC_MIIM_BUSY_LEN) - 1) << EMAC_MIIM_BUSY_POS))
+
+/* 0x40 : MAC_ADDR0 */
+#define EMAC_MAC_ADDR0_OFFSET (0x40)
+#define EMAC_MAC_B5           EMAC_MAC_B5
+#define EMAC_MAC_B5_POS       (0U)
+#define EMAC_MAC_B5_LEN       (8U)
+#define EMAC_MAC_B5_MSK       (((1U << EMAC_MAC_B5_LEN) - 1) << EMAC_MAC_B5_POS)
+#define EMAC_MAC_B5_UMSK      (~(((1U << EMAC_MAC_B5_LEN) - 1) << EMAC_MAC_B5_POS))
+#define EMAC_MAC_B4           EMAC_MAC_B4
+#define EMAC_MAC_B4_POS       (8U)
+#define EMAC_MAC_B4_LEN       (8U)
+#define EMAC_MAC_B4_MSK       (((1U << EMAC_MAC_B4_LEN) - 1) << EMAC_MAC_B4_POS)
+#define EMAC_MAC_B4_UMSK      (~(((1U << EMAC_MAC_B4_LEN) - 1) << EMAC_MAC_B4_POS))
+#define EMAC_MAC_B3           EMAC_MAC_B3
+#define EMAC_MAC_B3_POS       (16U)
+#define EMAC_MAC_B3_LEN       (8U)
+#define EMAC_MAC_B3_MSK       (((1U << EMAC_MAC_B3_LEN) - 1) << EMAC_MAC_B3_POS)
+#define EMAC_MAC_B3_UMSK      (~(((1U << EMAC_MAC_B3_LEN) - 1) << EMAC_MAC_B3_POS))
+#define EMAC_MAC_B2           EMAC_MAC_B2
+#define EMAC_MAC_B2_POS       (24U)
+#define EMAC_MAC_B2_LEN       (8U)
+#define EMAC_MAC_B2_MSK       (((1U << EMAC_MAC_B2_LEN) - 1) << EMAC_MAC_B2_POS)
+#define EMAC_MAC_B2_UMSK      (~(((1U << EMAC_MAC_B2_LEN) - 1) << EMAC_MAC_B2_POS))
+
+/* 0x44 : MAC_ADDR1 */
+#define EMAC_MAC_ADDR1_OFFSET (0x44)
+#define EMAC_MAC_B1           EMAC_MAC_B1
+#define EMAC_MAC_B1_POS       (0U)
+#define EMAC_MAC_B1_LEN       (8U)
+#define EMAC_MAC_B1_MSK       (((1U << EMAC_MAC_B1_LEN) - 1) << EMAC_MAC_B1_POS)
+#define EMAC_MAC_B1_UMSK      (~(((1U << EMAC_MAC_B1_LEN) - 1) << EMAC_MAC_B1_POS))
+#define EMAC_MAC_B0           EMAC_MAC_B0
+#define EMAC_MAC_B0_POS       (8U)
+#define EMAC_MAC_B0_LEN       (8U)
+#define EMAC_MAC_B0_MSK       (((1U << EMAC_MAC_B0_LEN) - 1) << EMAC_MAC_B0_POS)
+#define EMAC_MAC_B0_UMSK      (~(((1U << EMAC_MAC_B0_LEN) - 1) << EMAC_MAC_B0_POS))
+
+/* 0x48 : HASH0_ADDR */
+#define EMAC_HASH0_ADDR_OFFSET (0x48)
+#define EMAC_HASH0             EMAC_HASH0
+#define EMAC_HASH0_POS         (0U)
+#define EMAC_HASH0_LEN         (32U)
+#define EMAC_HASH0_MSK         (((1U << EMAC_HASH0_LEN) - 1) << EMAC_HASH0_POS)
+#define EMAC_HASH0_UMSK        (~(((1U << EMAC_HASH0_LEN) - 1) << EMAC_HASH0_POS))
+
+/* 0x4C : HASH1_ADDR */
+#define EMAC_HASH1_ADDR_OFFSET (0x4C)
+#define EMAC_HASH1             EMAC_HASH1
+#define EMAC_HASH1_POS         (0U)
+#define EMAC_HASH1_LEN         (32U)
+#define EMAC_HASH1_MSK         (((1U << EMAC_HASH1_LEN) - 1) << EMAC_HASH1_POS)
+#define EMAC_HASH1_UMSK        (~(((1U << EMAC_HASH1_LEN) - 1) << EMAC_HASH1_POS))
+
+/* 0x50 : TXCTRL */
+#define EMAC_TXCTRL_OFFSET  (0x50)
+#define EMAC_TXPAUSETV      EMAC_TXPAUSETV
+#define EMAC_TXPAUSETV_POS  (0U)
+#define EMAC_TXPAUSETV_LEN  (16U)
+#define EMAC_TXPAUSETV_MSK  (((1U << EMAC_TXPAUSETV_LEN) - 1) << EMAC_TXPAUSETV_POS)
+#define EMAC_TXPAUSETV_UMSK (~(((1U << EMAC_TXPAUSETV_LEN) - 1) << EMAC_TXPAUSETV_POS))
+#define EMAC_TXPAUSERQ      EMAC_TXPAUSERQ
+#define EMAC_TXPAUSERQ_POS  (16U)
+#define EMAC_TXPAUSERQ_LEN  (1U)
+#define EMAC_TXPAUSERQ_MSK  (((1U << EMAC_TXPAUSERQ_LEN) - 1) << EMAC_TXPAUSERQ_POS)
+#define EMAC_TXPAUSERQ_UMSK (~(((1U << EMAC_TXPAUSERQ_LEN) - 1) << EMAC_TXPAUSERQ_POS))
+
+struct emac_reg {
+    /* 0x0 : MODE */
+    union {
+        struct
+        {
+            uint32_t RXEN           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t TXEN           : 1; /* [    1],        r/w,        0x0 */
+            uint32_t NOPRE          : 1; /* [    2],        r/w,        0x0 */
+            uint32_t BRO            : 1; /* [    3],        r/w,        0x1 */
+            uint32_t rsvd_4         : 1; /* [    4],       rsvd,        0x0 */
+            uint32_t PRO            : 1; /* [    5],        r/w,        0x0 */
+            uint32_t IFG            : 1; /* [    6],        r/w,        0x0 */
+            uint32_t rsvd_9_7       : 3; /* [ 9: 7],       rsvd,        0x0 */
+            uint32_t FULLD          : 1; /* [   10],        r/w,        0x0 */
+            uint32_t rsvd_12_11     : 2; /* [12:11],       rsvd,        0x0 */
+            uint32_t CRCEN          : 1; /* [   13],        r/w,        0x1 */
+            uint32_t HUGEN          : 1; /* [   14],        r/w,        0x0 */
+            uint32_t PAD            : 1; /* [   15],        r/w,        0x1 */
+            uint32_t RECSMALL       : 1; /* [   16],        r/w,        0x0 */
+            uint32_t RMII_EN        : 1; /* [   17],        r/w,        0x0 */
+            uint32_t rsvd_23_18     : 6; /* [23:18],       rsvd,        0x0 */
+            uint32_t reserved_24_31 : 8; /* [31:24],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } MODE;
+
+    /* 0x4 : INT_SOURCE */
+    union {
+        struct
+        {
+            uint32_t TXB           : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t TXE           : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t RXB           : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t RXE           : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t BUSY          : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t TXC           : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t RXC           : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7_31 : 25; /* [31: 7],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } INT_SOURCE;
+
+    /* 0x8 : INT_MASK */
+    union {
+        struct
+        {
+            uint32_t TXB_M         : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t TXE_M         : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t RXB_M         : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t RXE_M         : 1;  /* [    3],        r/w,        0x1 */
+            uint32_t BUSY_M        : 1;  /* [    4],        r/w,        0x1 */
+            uint32_t TXC_M         : 1;  /* [    5],        r/w,        0x1 */
+            uint32_t RXC_M         : 1;  /* [    6],        r/w,        0x1 */
+            uint32_t reserved_7_31 : 25; /* [31: 7],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } INT_MASK;
+
+    /* 0xC : IPGT */
+    union {
+        struct
+        {
+            uint32_t IPGT          : 7;  /* [ 6: 0],        r/w,       0x18 */
+            uint32_t reserved_7_31 : 25; /* [31: 7],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } IPGT;
+
+    /* 0x10  reserved */
+    uint8_t RESERVED0x10[8];
+
+    /* 0x18 : PACKETLEN */
+    union {
+        struct
+        {
+            uint32_t MAXFL : 16; /* [15: 0],        r/w,      0x600 */
+            uint32_t MINFL : 16; /* [31:16],        r/w,       0x40 */
+        } BF;
+        uint32_t WORD;
+    } PACKETLEN;
+
+    /* 0x1C : COLLCONFIG */
+    union {
+        struct
+        {
+            uint32_t COLLVALID      : 6;  /* [ 5: 0],        r/w,       0x3f */
+            uint32_t reserved_6_15  : 10; /* [15: 6],       rsvd,        0x0 */
+            uint32_t MAXRET         : 4;  /* [19:16],        r/w,        0xf */
+            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } COLLCONFIG;
+
+    /* 0x20 : TX_BD_NUM */
+    union {
+        struct
+        {
+            uint32_t TXBDNUM       : 8; /* [ 7: 0],        r/w,       0x40 */
+            uint32_t reserved_8_15 : 8; /* [15: 8],       rsvd,        0x0 */
+            uint32_t TXBDPTR       : 7; /* [22:16],          r,        0x0 */
+            uint32_t reserved_23   : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t RXBDPTR       : 7; /* [30:24],          r,        0x0 */
+            uint32_t reserved_31   : 1; /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TX_BD_NUM;
+
+    /* 0x24  reserved */
+    uint8_t RESERVED0x24[4];
+
+    /* 0x28 : MIIMODE */
+    union {
+        struct
+        {
+            uint32_t CLKDIV        : 8;  /* [ 7: 0],        r/w,       0x64 */
+            uint32_t MIINOPRE      : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9_31 : 23; /* [31: 9],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } MIIMODE;
+
+    /* 0x2C : MIICOMMAND */
+    union {
+        struct
+        {
+            uint32_t SCANSTAT      : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t RSTAT         : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t WCTRLDATA     : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3_31 : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } MIICOMMAND;
+
+    /* 0x30 : MIIADDRESS */
+    union {
+        struct
+        {
+            uint32_t FIAD           : 5;  /* [ 4: 0],        r/w,        0x0 */
+            uint32_t reserved_5_7   : 3;  /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t RGAD           : 5;  /* [12: 8],        r/w,        0x0 */
+            uint32_t reserved_13_31 : 19; /* [31:13],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } MIIADDRESS;
+
+    /* 0x34 : MIITX_DATA */
+    union {
+        struct
+        {
+            uint32_t CTRLDATA       : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } MIITX_DATA;
+
+    /* 0x38 : MIIRX_DATA */
+    union {
+        struct
+        {
+            uint32_t PRSD           : 16; /* [15: 0],          r,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } MIIRX_DATA;
+
+    /* 0x3C : MIISTATUS */
+    union {
+        struct
+        {
+            uint32_t MIIM_LINKFAIL : 1;  /* [    0],          r,        0x0 */
+            uint32_t MIIM_BUSY     : 1;  /* [    1],          r,        0x0 */
+            uint32_t reserved_2_31 : 30; /* [31: 2],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } MIISTATUS;
+
+    /* 0x40 : MAC_ADDR0 */
+    union {
+        struct
+        {
+            uint32_t MAC_B5 : 8; /* [ 7: 0],        r/w,        0x0 */
+            uint32_t MAC_B4 : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t MAC_B3 : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t MAC_B2 : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } MAC_ADDR0;
+
+    /* 0x44 : MAC_ADDR1 */
+    union {
+        struct
+        {
+            uint32_t MAC_B1         : 8;  /* [ 7: 0],        r/w,        0x0 */
+            uint32_t MAC_B0         : 8;  /* [15: 8],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } MAC_ADDR1;
+
+    /* 0x48 : HASH0_ADDR */
+    union {
+        struct
+        {
+            uint32_t HASH0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HASH0_ADDR;
+
+    /* 0x4C : HASH1_ADDR */
+    union {
+        struct
+        {
+            uint32_t HASH1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HASH1_ADDR;
+
+    /* 0x50 : TXCTRL */
+    union {
+        struct
+        {
+            uint32_t TXPAUSETV      : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t TXPAUSERQ      : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17_31 : 15; /* [31:17],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TXCTRL;
+};
+
+typedef volatile struct emac_reg emac_reg_t;
+
+#endif /* __EMAC_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/glb_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/glb_reg.h
new file mode 100644
index 00000000..19fd12de
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/glb_reg.h
@@ -0,0 +1,5498 @@
+/**
+  ******************************************************************************
+  * @file    glb_reg.h
+  * @version V1.2
+  * @date    2020-07-08
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __GLB_REG_H__
+#define __GLB_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : clk_cfg0 */
+#define GLB_CLK_CFG0_OFFSET       (0x0)
+#define GLB_REG_PLL_EN            GLB_REG_PLL_EN
+#define GLB_REG_PLL_EN_POS        (0U)
+#define GLB_REG_PLL_EN_LEN        (1U)
+#define GLB_REG_PLL_EN_MSK        (((1U << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS)
+#define GLB_REG_PLL_EN_UMSK       (~(((1U << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS))
+#define GLB_REG_FCLK_EN           GLB_REG_FCLK_EN
+#define GLB_REG_FCLK_EN_POS       (1U)
+#define GLB_REG_FCLK_EN_LEN       (1U)
+#define GLB_REG_FCLK_EN_MSK       (((1U << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS)
+#define GLB_REG_FCLK_EN_UMSK      (~(((1U << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS))
+#define GLB_REG_HCLK_EN           GLB_REG_HCLK_EN
+#define GLB_REG_HCLK_EN_POS       (2U)
+#define GLB_REG_HCLK_EN_LEN       (1U)
+#define GLB_REG_HCLK_EN_MSK       (((1U << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS)
+#define GLB_REG_HCLK_EN_UMSK      (~(((1U << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS))
+#define GLB_REG_BCLK_EN           GLB_REG_BCLK_EN
+#define GLB_REG_BCLK_EN_POS       (3U)
+#define GLB_REG_BCLK_EN_LEN       (1U)
+#define GLB_REG_BCLK_EN_MSK       (((1U << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS)
+#define GLB_REG_BCLK_EN_UMSK      (~(((1U << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS))
+#define GLB_REG_PLL_SEL           GLB_REG_PLL_SEL
+#define GLB_REG_PLL_SEL_POS       (4U)
+#define GLB_REG_PLL_SEL_LEN       (2U)
+#define GLB_REG_PLL_SEL_MSK       (((1U << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS)
+#define GLB_REG_PLL_SEL_UMSK      (~(((1U << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS))
+#define GLB_HBN_ROOT_CLK_SEL      GLB_HBN_ROOT_CLK_SEL
+#define GLB_HBN_ROOT_CLK_SEL_POS  (6U)
+#define GLB_HBN_ROOT_CLK_SEL_LEN  (2U)
+#define GLB_HBN_ROOT_CLK_SEL_MSK  (((1U << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS)
+#define GLB_HBN_ROOT_CLK_SEL_UMSK (~(((1U << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS))
+#define GLB_REG_HCLK_DIV          GLB_REG_HCLK_DIV
+#define GLB_REG_HCLK_DIV_POS      (8U)
+#define GLB_REG_HCLK_DIV_LEN      (8U)
+#define GLB_REG_HCLK_DIV_MSK      (((1U << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS)
+#define GLB_REG_HCLK_DIV_UMSK     (~(((1U << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS))
+#define GLB_REG_BCLK_DIV          GLB_REG_BCLK_DIV
+#define GLB_REG_BCLK_DIV_POS      (16U)
+#define GLB_REG_BCLK_DIV_LEN      (8U)
+#define GLB_REG_BCLK_DIV_MSK      (((1U << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS)
+#define GLB_REG_BCLK_DIV_UMSK     (~(((1U << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS))
+#define GLB_FCLK_SW_STATE         GLB_FCLK_SW_STATE
+#define GLB_FCLK_SW_STATE_POS     (24U)
+#define GLB_FCLK_SW_STATE_LEN     (3U)
+#define GLB_FCLK_SW_STATE_MSK     (((1U << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS)
+#define GLB_FCLK_SW_STATE_UMSK    (~(((1U << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS))
+#define GLB_CHIP_RDY              GLB_CHIP_RDY
+#define GLB_CHIP_RDY_POS          (27U)
+#define GLB_CHIP_RDY_LEN          (1U)
+#define GLB_CHIP_RDY_MSK          (((1U << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS)
+#define GLB_CHIP_RDY_UMSK         (~(((1U << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS))
+#define GLB_ID                    GLB_ID
+#define GLB_ID_POS                (28U)
+#define GLB_ID_LEN                (4U)
+#define GLB_ID_MSK                (((1U << GLB_ID_LEN) - 1) << GLB_ID_POS)
+#define GLB_ID_UMSK               (~(((1U << GLB_ID_LEN) - 1) << GLB_ID_POS))
+
+/* 0x4 : clk_cfg1 */
+#define GLB_CLK_CFG1_OFFSET              (0x4)
+#define GLB_QDEC_CLK_DIV                 GLB_QDEC_CLK_DIV
+#define GLB_QDEC_CLK_DIV_POS             (0U)
+#define GLB_QDEC_CLK_DIV_LEN             (5U)
+#define GLB_QDEC_CLK_DIV_MSK             (((1U << GLB_QDEC_CLK_DIV_LEN) - 1) << GLB_QDEC_CLK_DIV_POS)
+#define GLB_QDEC_CLK_DIV_UMSK            (~(((1U << GLB_QDEC_CLK_DIV_LEN) - 1) << GLB_QDEC_CLK_DIV_POS))
+#define GLB_QDEC_CLK_SEL                 GLB_QDEC_CLK_SEL
+#define GLB_QDEC_CLK_SEL_POS             (7U)
+#define GLB_QDEC_CLK_SEL_LEN             (1U)
+#define GLB_QDEC_CLK_SEL_MSK             (((1U << GLB_QDEC_CLK_SEL_LEN) - 1) << GLB_QDEC_CLK_SEL_POS)
+#define GLB_QDEC_CLK_SEL_UMSK            (~(((1U << GLB_QDEC_CLK_SEL_LEN) - 1) << GLB_QDEC_CLK_SEL_POS))
+#define GLB_USB_CLK_EN                   GLB_USB_CLK_EN
+#define GLB_USB_CLK_EN_POS               (8U)
+#define GLB_USB_CLK_EN_LEN               (1U)
+#define GLB_USB_CLK_EN_MSK               (((1U << GLB_USB_CLK_EN_LEN) - 1) << GLB_USB_CLK_EN_POS)
+#define GLB_USB_CLK_EN_UMSK              (~(((1U << GLB_USB_CLK_EN_LEN) - 1) << GLB_USB_CLK_EN_POS))
+#define GLB_DLL_48M_DIV_EN               GLB_DLL_48M_DIV_EN
+#define GLB_DLL_48M_DIV_EN_POS           (9U)
+#define GLB_DLL_48M_DIV_EN_LEN           (1U)
+#define GLB_DLL_48M_DIV_EN_MSK           (((1U << GLB_DLL_48M_DIV_EN_LEN) - 1) << GLB_DLL_48M_DIV_EN_POS)
+#define GLB_DLL_48M_DIV_EN_UMSK          (~(((1U << GLB_DLL_48M_DIV_EN_LEN) - 1) << GLB_DLL_48M_DIV_EN_POS))
+#define GLB_REG_I2S_CLK_SEL              GLB_REG_I2S_CLK_SEL
+#define GLB_REG_I2S_CLK_SEL_POS          (12U)
+#define GLB_REG_I2S_CLK_SEL_LEN          (1U)
+#define GLB_REG_I2S_CLK_SEL_MSK          (((1U << GLB_REG_I2S_CLK_SEL_LEN) - 1) << GLB_REG_I2S_CLK_SEL_POS)
+#define GLB_REG_I2S_CLK_SEL_UMSK         (~(((1U << GLB_REG_I2S_CLK_SEL_LEN) - 1) << GLB_REG_I2S_CLK_SEL_POS))
+#define GLB_REG_I2S0_CLK_EN              GLB_REG_I2S0_CLK_EN
+#define GLB_REG_I2S0_CLK_EN_POS          (13U)
+#define GLB_REG_I2S0_CLK_EN_LEN          (1U)
+#define GLB_REG_I2S0_CLK_EN_MSK          (((1U << GLB_REG_I2S0_CLK_EN_LEN) - 1) << GLB_REG_I2S0_CLK_EN_POS)
+#define GLB_REG_I2S0_CLK_EN_UMSK         (~(((1U << GLB_REG_I2S0_CLK_EN_LEN) - 1) << GLB_REG_I2S0_CLK_EN_POS))
+#define GLB_REG_I2S_0_REF_CLK_OE         GLB_REG_I2S_0_REF_CLK_OE
+#define GLB_REG_I2S_0_REF_CLK_OE_POS     (14U)
+#define GLB_REG_I2S_0_REF_CLK_OE_LEN     (1U)
+#define GLB_REG_I2S_0_REF_CLK_OE_MSK     (((1U << GLB_REG_I2S_0_REF_CLK_OE_LEN) - 1) << GLB_REG_I2S_0_REF_CLK_OE_POS)
+#define GLB_REG_I2S_0_REF_CLK_OE_UMSK    (~(((1U << GLB_REG_I2S_0_REF_CLK_OE_LEN) - 1) << GLB_REG_I2S_0_REF_CLK_OE_POS))
+#define GLB_BLE_CLK_SEL                  GLB_BLE_CLK_SEL
+#define GLB_BLE_CLK_SEL_POS              (16U)
+#define GLB_BLE_CLK_SEL_LEN              (6U)
+#define GLB_BLE_CLK_SEL_MSK              (((1U << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS)
+#define GLB_BLE_CLK_SEL_UMSK             (~(((1U << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS))
+#define GLB_BLE_EN                       GLB_BLE_EN
+#define GLB_BLE_EN_POS                   (24U)
+#define GLB_BLE_EN_LEN                   (1U)
+#define GLB_BLE_EN_MSK                   (((1U << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS)
+#define GLB_BLE_EN_UMSK                  (~(((1U << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS))
+#define GLB_M154_ZBEN                    GLB_M154_ZBEN
+#define GLB_M154_ZBEN_POS                (25U)
+#define GLB_M154_ZBEN_LEN                (1U)
+#define GLB_M154_ZBEN_MSK                (((1U << GLB_M154_ZBEN_LEN) - 1) << GLB_M154_ZBEN_POS)
+#define GLB_M154_ZBEN_UMSK               (~(((1U << GLB_M154_ZBEN_LEN) - 1) << GLB_M154_ZBEN_POS))
+#define GLB_REG_CAM_REF_CLK_EN           GLB_REG_CAM_REF_CLK_EN
+#define GLB_REG_CAM_REF_CLK_EN_POS       (28U)
+#define GLB_REG_CAM_REF_CLK_EN_LEN       (1U)
+#define GLB_REG_CAM_REF_CLK_EN_MSK       (((1U << GLB_REG_CAM_REF_CLK_EN_LEN) - 1) << GLB_REG_CAM_REF_CLK_EN_POS)
+#define GLB_REG_CAM_REF_CLK_EN_UMSK      (~(((1U << GLB_REG_CAM_REF_CLK_EN_LEN) - 1) << GLB_REG_CAM_REF_CLK_EN_POS))
+#define GLB_REG_CAM_REF_CLK_SRC_SEL      GLB_REG_CAM_REF_CLK_SRC_SEL
+#define GLB_REG_CAM_REF_CLK_SRC_SEL_POS  (29U)
+#define GLB_REG_CAM_REF_CLK_SRC_SEL_LEN  (1U)
+#define GLB_REG_CAM_REF_CLK_SRC_SEL_MSK  (((1U << GLB_REG_CAM_REF_CLK_SRC_SEL_LEN) - 1) << GLB_REG_CAM_REF_CLK_SRC_SEL_POS)
+#define GLB_REG_CAM_REF_CLK_SRC_SEL_UMSK (~(((1U << GLB_REG_CAM_REF_CLK_SRC_SEL_LEN) - 1) << GLB_REG_CAM_REF_CLK_SRC_SEL_POS))
+#define GLB_REG_CAM_REF_CLK_DIV          GLB_REG_CAM_REF_CLK_DIV
+#define GLB_REG_CAM_REF_CLK_DIV_POS      (30U)
+#define GLB_REG_CAM_REF_CLK_DIV_LEN      (2U)
+#define GLB_REG_CAM_REF_CLK_DIV_MSK      (((1U << GLB_REG_CAM_REF_CLK_DIV_LEN) - 1) << GLB_REG_CAM_REF_CLK_DIV_POS)
+#define GLB_REG_CAM_REF_CLK_DIV_UMSK     (~(((1U << GLB_REG_CAM_REF_CLK_DIV_LEN) - 1) << GLB_REG_CAM_REF_CLK_DIV_POS))
+
+/* 0x8 : clk_cfg2 */
+#define GLB_CLK_CFG2_OFFSET       (0x8)
+#define GLB_UART_CLK_DIV          GLB_UART_CLK_DIV
+#define GLB_UART_CLK_DIV_POS      (0U)
+#define GLB_UART_CLK_DIV_LEN      (3U)
+#define GLB_UART_CLK_DIV_MSK      (((1U << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS)
+#define GLB_UART_CLK_DIV_UMSK     (~(((1U << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS))
+#define GLB_UART_CLK_EN           GLB_UART_CLK_EN
+#define GLB_UART_CLK_EN_POS       (4U)
+#define GLB_UART_CLK_EN_LEN       (1U)
+#define GLB_UART_CLK_EN_MSK       (((1U << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS)
+#define GLB_UART_CLK_EN_UMSK      (~(((1U << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS))
+#define GLB_HBN_UART_CLK_SEL      GLB_HBN_UART_CLK_SEL
+#define GLB_HBN_UART_CLK_SEL_POS  (7U)
+#define GLB_HBN_UART_CLK_SEL_LEN  (1U)
+#define GLB_HBN_UART_CLK_SEL_MSK  (((1U << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS)
+#define GLB_HBN_UART_CLK_SEL_UMSK (~(((1U << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS))
+#define GLB_SF_CLK_DIV            GLB_SF_CLK_DIV
+#define GLB_SF_CLK_DIV_POS        (8U)
+#define GLB_SF_CLK_DIV_LEN        (3U)
+#define GLB_SF_CLK_DIV_MSK        (((1U << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS)
+#define GLB_SF_CLK_DIV_UMSK       (~(((1U << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS))
+#define GLB_SF_CLK_EN             GLB_SF_CLK_EN
+#define GLB_SF_CLK_EN_POS         (11U)
+#define GLB_SF_CLK_EN_LEN         (1U)
+#define GLB_SF_CLK_EN_MSK         (((1U << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS)
+#define GLB_SF_CLK_EN_UMSK        (~(((1U << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS))
+#define GLB_SF_CLK_SEL            GLB_SF_CLK_SEL
+#define GLB_SF_CLK_SEL_POS        (12U)
+#define GLB_SF_CLK_SEL_LEN        (2U)
+#define GLB_SF_CLK_SEL_MSK        (((1U << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS)
+#define GLB_SF_CLK_SEL_UMSK       (~(((1U << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS))
+#define GLB_SF_CLK_SEL2           GLB_SF_CLK_SEL2
+#define GLB_SF_CLK_SEL2_POS       (14U)
+#define GLB_SF_CLK_SEL2_LEN       (2U)
+#define GLB_SF_CLK_SEL2_MSK       (((1U << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS)
+#define GLB_SF_CLK_SEL2_UMSK      (~(((1U << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS))
+#define GLB_IR_CLK_DIV            GLB_IR_CLK_DIV
+#define GLB_IR_CLK_DIV_POS        (16U)
+#define GLB_IR_CLK_DIV_LEN        (6U)
+#define GLB_IR_CLK_DIV_MSK        (((1U << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS)
+#define GLB_IR_CLK_DIV_UMSK       (~(((1U << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS))
+#define GLB_IR_CLK_EN             GLB_IR_CLK_EN
+#define GLB_IR_CLK_EN_POS         (23U)
+#define GLB_IR_CLK_EN_LEN         (1U)
+#define GLB_IR_CLK_EN_MSK         (((1U << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS)
+#define GLB_IR_CLK_EN_UMSK        (~(((1U << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS))
+#define GLB_DMA_CLK_EN            GLB_DMA_CLK_EN
+#define GLB_DMA_CLK_EN_POS        (24U)
+#define GLB_DMA_CLK_EN_LEN        (8U)
+#define GLB_DMA_CLK_EN_MSK        (((1U << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS)
+#define GLB_DMA_CLK_EN_UMSK       (~(((1U << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS))
+
+/* 0xC : clk_cfg3 */
+#define GLB_CLK_CFG3_OFFSET            (0xC)
+#define GLB_SPI_CLK_DIV                GLB_SPI_CLK_DIV
+#define GLB_SPI_CLK_DIV_POS            (0U)
+#define GLB_SPI_CLK_DIV_LEN            (5U)
+#define GLB_SPI_CLK_DIV_MSK            (((1U << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS)
+#define GLB_SPI_CLK_DIV_UMSK           (~(((1U << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS))
+#define GLB_CFG_SEL_ETH_REF_CLK_O      GLB_CFG_SEL_ETH_REF_CLK_O
+#define GLB_CFG_SEL_ETH_REF_CLK_O_POS  (5U)
+#define GLB_CFG_SEL_ETH_REF_CLK_O_LEN  (1U)
+#define GLB_CFG_SEL_ETH_REF_CLK_O_MSK  (((1U << GLB_CFG_SEL_ETH_REF_CLK_O_LEN) - 1) << GLB_CFG_SEL_ETH_REF_CLK_O_POS)
+#define GLB_CFG_SEL_ETH_REF_CLK_O_UMSK (~(((1U << GLB_CFG_SEL_ETH_REF_CLK_O_LEN) - 1) << GLB_CFG_SEL_ETH_REF_CLK_O_POS))
+#define GLB_CFG_INV_ETH_REF_CLK_O      GLB_CFG_INV_ETH_REF_CLK_O
+#define GLB_CFG_INV_ETH_REF_CLK_O_POS  (6U)
+#define GLB_CFG_INV_ETH_REF_CLK_O_LEN  (1U)
+#define GLB_CFG_INV_ETH_REF_CLK_O_MSK  (((1U << GLB_CFG_INV_ETH_REF_CLK_O_LEN) - 1) << GLB_CFG_INV_ETH_REF_CLK_O_POS)
+#define GLB_CFG_INV_ETH_REF_CLK_O_UMSK (~(((1U << GLB_CFG_INV_ETH_REF_CLK_O_LEN) - 1) << GLB_CFG_INV_ETH_REF_CLK_O_POS))
+#define GLB_CFG_INV_ETH_TX_CLK         GLB_CFG_INV_ETH_TX_CLK
+#define GLB_CFG_INV_ETH_TX_CLK_POS     (7U)
+#define GLB_CFG_INV_ETH_TX_CLK_LEN     (1U)
+#define GLB_CFG_INV_ETH_TX_CLK_MSK     (((1U << GLB_CFG_INV_ETH_TX_CLK_LEN) - 1) << GLB_CFG_INV_ETH_TX_CLK_POS)
+#define GLB_CFG_INV_ETH_TX_CLK_UMSK    (~(((1U << GLB_CFG_INV_ETH_TX_CLK_LEN) - 1) << GLB_CFG_INV_ETH_TX_CLK_POS))
+#define GLB_SPI_CLK_EN                 GLB_SPI_CLK_EN
+#define GLB_SPI_CLK_EN_POS             (8U)
+#define GLB_SPI_CLK_EN_LEN             (1U)
+#define GLB_SPI_CLK_EN_MSK             (((1U << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS)
+#define GLB_SPI_CLK_EN_UMSK            (~(((1U << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS))
+#define GLB_CFG_INV_RF_TEST_CLK_O      GLB_CFG_INV_RF_TEST_CLK_O
+#define GLB_CFG_INV_RF_TEST_CLK_O_POS  (9U)
+#define GLB_CFG_INV_RF_TEST_CLK_O_LEN  (1U)
+#define GLB_CFG_INV_RF_TEST_CLK_O_MSK  (((1U << GLB_CFG_INV_RF_TEST_CLK_O_LEN) - 1) << GLB_CFG_INV_RF_TEST_CLK_O_POS)
+#define GLB_CFG_INV_RF_TEST_CLK_O_UMSK (~(((1U << GLB_CFG_INV_RF_TEST_CLK_O_LEN) - 1) << GLB_CFG_INV_RF_TEST_CLK_O_POS))
+#define GLB_CFG_INV_ETH_RX_CLK         GLB_CFG_INV_ETH_RX_CLK
+#define GLB_CFG_INV_ETH_RX_CLK_POS     (10U)
+#define GLB_CFG_INV_ETH_RX_CLK_LEN     (1U)
+#define GLB_CFG_INV_ETH_RX_CLK_MSK     (((1U << GLB_CFG_INV_ETH_RX_CLK_LEN) - 1) << GLB_CFG_INV_ETH_RX_CLK_POS)
+#define GLB_CFG_INV_ETH_RX_CLK_UMSK    (~(((1U << GLB_CFG_INV_ETH_RX_CLK_LEN) - 1) << GLB_CFG_INV_ETH_RX_CLK_POS))
+#define GLB_I2C_CLK_DIV                GLB_I2C_CLK_DIV
+#define GLB_I2C_CLK_DIV_POS            (16U)
+#define GLB_I2C_CLK_DIV_LEN            (8U)
+#define GLB_I2C_CLK_DIV_MSK            (((1U << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS)
+#define GLB_I2C_CLK_DIV_UMSK           (~(((1U << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS))
+#define GLB_I2C_CLK_EN                 GLB_I2C_CLK_EN
+#define GLB_I2C_CLK_EN_POS             (24U)
+#define GLB_I2C_CLK_EN_LEN             (1U)
+#define GLB_I2C_CLK_EN_MSK             (((1U << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS)
+#define GLB_I2C_CLK_EN_UMSK            (~(((1U << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS))
+#define GLB_CHIP_CLK_OUT_0_SEL         GLB_CHIP_CLK_OUT_0_SEL
+#define GLB_CHIP_CLK_OUT_0_SEL_POS     (28U)
+#define GLB_CHIP_CLK_OUT_0_SEL_LEN     (2U)
+#define GLB_CHIP_CLK_OUT_0_SEL_MSK     (((1U << GLB_CHIP_CLK_OUT_0_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_0_SEL_POS)
+#define GLB_CHIP_CLK_OUT_0_SEL_UMSK    (~(((1U << GLB_CHIP_CLK_OUT_0_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_0_SEL_POS))
+#define GLB_CHIP_CLK_OUT_1_SEL         GLB_CHIP_CLK_OUT_1_SEL
+#define GLB_CHIP_CLK_OUT_1_SEL_POS     (30U)
+#define GLB_CHIP_CLK_OUT_1_SEL_LEN     (2U)
+#define GLB_CHIP_CLK_OUT_1_SEL_MSK     (((1U << GLB_CHIP_CLK_OUT_1_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_1_SEL_POS)
+#define GLB_CHIP_CLK_OUT_1_SEL_UMSK    (~(((1U << GLB_CHIP_CLK_OUT_1_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_1_SEL_POS))
+
+/* 0x10 : swrst_cfg0 */
+#define GLB_SWRST_CFG0_OFFSET (0x10)
+#define GLB_SWRST_S00         GLB_SWRST_S00
+#define GLB_SWRST_S00_POS     (0U)
+#define GLB_SWRST_S00_LEN     (1U)
+#define GLB_SWRST_S00_MSK     (((1U << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS)
+#define GLB_SWRST_S00_UMSK    (~(((1U << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS))
+#define GLB_SWRST_S01         GLB_SWRST_S01
+#define GLB_SWRST_S01_POS     (1U)
+#define GLB_SWRST_S01_LEN     (1U)
+#define GLB_SWRST_S01_MSK     (((1U << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS)
+#define GLB_SWRST_S01_UMSK    (~(((1U << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS))
+#define GLB_SWRST_S20         GLB_SWRST_S20
+#define GLB_SWRST_S20_POS     (4U)
+#define GLB_SWRST_S20_LEN     (1U)
+#define GLB_SWRST_S20_MSK     (((1U << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS)
+#define GLB_SWRST_S20_UMSK    (~(((1U << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS))
+#define GLB_SWRST_S30         GLB_SWRST_S30
+#define GLB_SWRST_S30_POS     (8U)
+#define GLB_SWRST_S30_LEN     (1U)
+#define GLB_SWRST_S30_MSK     (((1U << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS)
+#define GLB_SWRST_S30_UMSK    (~(((1U << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS))
+
+/* 0x14 : swrst_cfg1 */
+#define GLB_SWRST_CFG1_OFFSET (0x14)
+#define GLB_SWRST_S10         GLB_SWRST_S10
+#define GLB_SWRST_S10_POS     (0U)
+#define GLB_SWRST_S10_LEN     (1U)
+#define GLB_SWRST_S10_MSK     (((1U << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS)
+#define GLB_SWRST_S10_UMSK    (~(((1U << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS))
+#define GLB_SWRST_S11         GLB_SWRST_S11
+#define GLB_SWRST_S11_POS     (1U)
+#define GLB_SWRST_S11_LEN     (1U)
+#define GLB_SWRST_S11_MSK     (((1U << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS)
+#define GLB_SWRST_S11_UMSK    (~(((1U << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS))
+#define GLB_SWRST_S12         GLB_SWRST_S12
+#define GLB_SWRST_S12_POS     (2U)
+#define GLB_SWRST_S12_LEN     (1U)
+#define GLB_SWRST_S12_MSK     (((1U << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS)
+#define GLB_SWRST_S12_UMSK    (~(((1U << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS))
+#define GLB_SWRST_S13         GLB_SWRST_S13
+#define GLB_SWRST_S13_POS     (3U)
+#define GLB_SWRST_S13_LEN     (1U)
+#define GLB_SWRST_S13_MSK     (((1U << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS)
+#define GLB_SWRST_S13_UMSK    (~(((1U << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS))
+#define GLB_SWRST_S14         GLB_SWRST_S14
+#define GLB_SWRST_S14_POS     (4U)
+#define GLB_SWRST_S14_LEN     (1U)
+#define GLB_SWRST_S14_MSK     (((1U << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS)
+#define GLB_SWRST_S14_UMSK    (~(((1U << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS))
+#define GLB_SWRST_S15         GLB_SWRST_S15
+#define GLB_SWRST_S15_POS     (5U)
+#define GLB_SWRST_S15_LEN     (1U)
+#define GLB_SWRST_S15_MSK     (((1U << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS)
+#define GLB_SWRST_S15_UMSK    (~(((1U << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS))
+#define GLB_SWRST_S16         GLB_SWRST_S16
+#define GLB_SWRST_S16_POS     (6U)
+#define GLB_SWRST_S16_LEN     (1U)
+#define GLB_SWRST_S16_MSK     (((1U << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS)
+#define GLB_SWRST_S16_UMSK    (~(((1U << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS))
+#define GLB_SWRST_S17         GLB_SWRST_S17
+#define GLB_SWRST_S17_POS     (7U)
+#define GLB_SWRST_S17_LEN     (1U)
+#define GLB_SWRST_S17_MSK     (((1U << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS)
+#define GLB_SWRST_S17_UMSK    (~(((1U << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS))
+#define GLB_SWRST_S18         GLB_SWRST_S18
+#define GLB_SWRST_S18_POS     (8U)
+#define GLB_SWRST_S18_LEN     (1U)
+#define GLB_SWRST_S18_MSK     (((1U << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS)
+#define GLB_SWRST_S18_UMSK    (~(((1U << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS))
+#define GLB_SWRST_S19         GLB_SWRST_S19
+#define GLB_SWRST_S19_POS     (9U)
+#define GLB_SWRST_S19_LEN     (1U)
+#define GLB_SWRST_S19_MSK     (((1U << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS)
+#define GLB_SWRST_S19_UMSK    (~(((1U << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS))
+#define GLB_SWRST_S1A         GLB_SWRST_S1A
+#define GLB_SWRST_S1A_POS     (10U)
+#define GLB_SWRST_S1A_LEN     (1U)
+#define GLB_SWRST_S1A_MSK     (((1U << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS)
+#define GLB_SWRST_S1A_UMSK    (~(((1U << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS))
+#define GLB_SWRST_S1B         GLB_SWRST_S1B
+#define GLB_SWRST_S1B_POS     (11U)
+#define GLB_SWRST_S1B_LEN     (1U)
+#define GLB_SWRST_S1B_MSK     (((1U << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS)
+#define GLB_SWRST_S1B_UMSK    (~(((1U << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS))
+#define GLB_SWRST_S1C         GLB_SWRST_S1C
+#define GLB_SWRST_S1C_POS     (12U)
+#define GLB_SWRST_S1C_LEN     (1U)
+#define GLB_SWRST_S1C_MSK     (((1U << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS)
+#define GLB_SWRST_S1C_UMSK    (~(((1U << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS))
+#define GLB_SWRST_S1D         GLB_SWRST_S1D
+#define GLB_SWRST_S1D_POS     (13U)
+#define GLB_SWRST_S1D_LEN     (1U)
+#define GLB_SWRST_S1D_MSK     (((1U << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS)
+#define GLB_SWRST_S1D_UMSK    (~(((1U << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS))
+#define GLB_SWRST_S1E         GLB_SWRST_S1E
+#define GLB_SWRST_S1E_POS     (14U)
+#define GLB_SWRST_S1E_LEN     (1U)
+#define GLB_SWRST_S1E_MSK     (((1U << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS)
+#define GLB_SWRST_S1E_UMSK    (~(((1U << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS))
+#define GLB_SWRST_S1F         GLB_SWRST_S1F
+#define GLB_SWRST_S1F_POS     (15U)
+#define GLB_SWRST_S1F_LEN     (1U)
+#define GLB_SWRST_S1F_MSK     (((1U << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS)
+#define GLB_SWRST_S1F_UMSK    (~(((1U << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS))
+#define GLB_SWRST_S1A0        GLB_SWRST_S1A0
+#define GLB_SWRST_S1A0_POS    (16U)
+#define GLB_SWRST_S1A0_LEN    (1U)
+#define GLB_SWRST_S1A0_MSK    (((1U << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS)
+#define GLB_SWRST_S1A0_UMSK   (~(((1U << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS))
+#define GLB_SWRST_S1A1        GLB_SWRST_S1A1
+#define GLB_SWRST_S1A1_POS    (17U)
+#define GLB_SWRST_S1A1_LEN    (1U)
+#define GLB_SWRST_S1A1_MSK    (((1U << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS)
+#define GLB_SWRST_S1A1_UMSK   (~(((1U << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS))
+#define GLB_SWRST_S1A2        GLB_SWRST_S1A2
+#define GLB_SWRST_S1A2_POS    (18U)
+#define GLB_SWRST_S1A2_LEN    (1U)
+#define GLB_SWRST_S1A2_MSK    (((1U << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS)
+#define GLB_SWRST_S1A2_UMSK   (~(((1U << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS))
+#define GLB_SWRST_S1A3        GLB_SWRST_S1A3
+#define GLB_SWRST_S1A3_POS    (19U)
+#define GLB_SWRST_S1A3_LEN    (1U)
+#define GLB_SWRST_S1A3_MSK    (((1U << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS)
+#define GLB_SWRST_S1A3_UMSK   (~(((1U << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS))
+#define GLB_SWRST_S1A4        GLB_SWRST_S1A4
+#define GLB_SWRST_S1A4_POS    (20U)
+#define GLB_SWRST_S1A4_LEN    (1U)
+#define GLB_SWRST_S1A4_MSK    (((1U << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS)
+#define GLB_SWRST_S1A4_UMSK   (~(((1U << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS))
+#define GLB_SWRST_S1A5        GLB_SWRST_S1A5
+#define GLB_SWRST_S1A5_POS    (21U)
+#define GLB_SWRST_S1A5_LEN    (1U)
+#define GLB_SWRST_S1A5_MSK    (((1U << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS)
+#define GLB_SWRST_S1A5_UMSK   (~(((1U << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS))
+#define GLB_SWRST_S1A6        GLB_SWRST_S1A6
+#define GLB_SWRST_S1A6_POS    (22U)
+#define GLB_SWRST_S1A6_LEN    (1U)
+#define GLB_SWRST_S1A6_MSK    (((1U << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS)
+#define GLB_SWRST_S1A6_UMSK   (~(((1U << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS))
+#define GLB_SWRST_S1A7        GLB_SWRST_S1A7
+#define GLB_SWRST_S1A7_POS    (23U)
+#define GLB_SWRST_S1A7_LEN    (1U)
+#define GLB_SWRST_S1A7_MSK    (((1U << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS)
+#define GLB_SWRST_S1A7_UMSK   (~(((1U << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS))
+#define GLB_SWRST_S1A8        GLB_SWRST_S1A8
+#define GLB_SWRST_S1A8_POS    (24U)
+#define GLB_SWRST_S1A8_LEN    (1U)
+#define GLB_SWRST_S1A8_MSK    (((1U << GLB_SWRST_S1A8_LEN) - 1) << GLB_SWRST_S1A8_POS)
+#define GLB_SWRST_S1A8_UMSK   (~(((1U << GLB_SWRST_S1A8_LEN) - 1) << GLB_SWRST_S1A8_POS))
+#define GLB_SWRST_S1A9        GLB_SWRST_S1A9
+#define GLB_SWRST_S1A9_POS    (25U)
+#define GLB_SWRST_S1A9_LEN    (1U)
+#define GLB_SWRST_S1A9_MSK    (((1U << GLB_SWRST_S1A9_LEN) - 1) << GLB_SWRST_S1A9_POS)
+#define GLB_SWRST_S1A9_UMSK   (~(((1U << GLB_SWRST_S1A9_LEN) - 1) << GLB_SWRST_S1A9_POS))
+#define GLB_SWRST_S1AA        GLB_SWRST_S1AA
+#define GLB_SWRST_S1AA_POS    (26U)
+#define GLB_SWRST_S1AA_LEN    (1U)
+#define GLB_SWRST_S1AA_MSK    (((1U << GLB_SWRST_S1AA_LEN) - 1) << GLB_SWRST_S1AA_POS)
+#define GLB_SWRST_S1AA_UMSK   (~(((1U << GLB_SWRST_S1AA_LEN) - 1) << GLB_SWRST_S1AA_POS))
+#define GLB_SWRST_S1AB        GLB_SWRST_S1AB
+#define GLB_SWRST_S1AB_POS    (27U)
+#define GLB_SWRST_S1AB_LEN    (1U)
+#define GLB_SWRST_S1AB_MSK    (((1U << GLB_SWRST_S1AB_LEN) - 1) << GLB_SWRST_S1AB_POS)
+#define GLB_SWRST_S1AB_UMSK   (~(((1U << GLB_SWRST_S1AB_LEN) - 1) << GLB_SWRST_S1AB_POS))
+#define GLB_SWRST_S1AC        GLB_SWRST_S1AC
+#define GLB_SWRST_S1AC_POS    (28U)
+#define GLB_SWRST_S1AC_LEN    (1U)
+#define GLB_SWRST_S1AC_MSK    (((1U << GLB_SWRST_S1AC_LEN) - 1) << GLB_SWRST_S1AC_POS)
+#define GLB_SWRST_S1AC_UMSK   (~(((1U << GLB_SWRST_S1AC_LEN) - 1) << GLB_SWRST_S1AC_POS))
+#define GLB_SWRST_S1AD        GLB_SWRST_S1AD
+#define GLB_SWRST_S1AD_POS    (29U)
+#define GLB_SWRST_S1AD_LEN    (1U)
+#define GLB_SWRST_S1AD_MSK    (((1U << GLB_SWRST_S1AD_LEN) - 1) << GLB_SWRST_S1AD_POS)
+#define GLB_SWRST_S1AD_UMSK   (~(((1U << GLB_SWRST_S1AD_LEN) - 1) << GLB_SWRST_S1AD_POS))
+#define GLB_SWRST_S1AE        GLB_SWRST_S1AE
+#define GLB_SWRST_S1AE_POS    (30U)
+#define GLB_SWRST_S1AE_LEN    (1U)
+#define GLB_SWRST_S1AE_MSK    (((1U << GLB_SWRST_S1AE_LEN) - 1) << GLB_SWRST_S1AE_POS)
+#define GLB_SWRST_S1AE_UMSK   (~(((1U << GLB_SWRST_S1AE_LEN) - 1) << GLB_SWRST_S1AE_POS))
+
+/* 0x18 : swrst_cfg2 */
+#define GLB_SWRST_CFG2_OFFSET         (0x18)
+#define GLB_REG_CTRL_PWRON_RST        GLB_REG_CTRL_PWRON_RST
+#define GLB_REG_CTRL_PWRON_RST_POS    (0U)
+#define GLB_REG_CTRL_PWRON_RST_LEN    (1U)
+#define GLB_REG_CTRL_PWRON_RST_MSK    (((1U << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS)
+#define GLB_REG_CTRL_PWRON_RST_UMSK   (~(((1U << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS))
+#define GLB_REG_CTRL_CPU_RESET        GLB_REG_CTRL_CPU_RESET
+#define GLB_REG_CTRL_CPU_RESET_POS    (1U)
+#define GLB_REG_CTRL_CPU_RESET_LEN    (1U)
+#define GLB_REG_CTRL_CPU_RESET_MSK    (((1U << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS)
+#define GLB_REG_CTRL_CPU_RESET_UMSK   (~(((1U << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS))
+#define GLB_REG_CTRL_SYS_RESET        GLB_REG_CTRL_SYS_RESET
+#define GLB_REG_CTRL_SYS_RESET_POS    (2U)
+#define GLB_REG_CTRL_SYS_RESET_LEN    (1U)
+#define GLB_REG_CTRL_SYS_RESET_MSK    (((1U << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS)
+#define GLB_REG_CTRL_SYS_RESET_UMSK   (~(((1U << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS))
+#define GLB_REG_CTRL_RESET_DUMMY      GLB_REG_CTRL_RESET_DUMMY
+#define GLB_REG_CTRL_RESET_DUMMY_POS  (4U)
+#define GLB_REG_CTRL_RESET_DUMMY_LEN  (4U)
+#define GLB_REG_CTRL_RESET_DUMMY_MSK  (((1U << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) << GLB_REG_CTRL_RESET_DUMMY_POS)
+#define GLB_REG_CTRL_RESET_DUMMY_UMSK (~(((1U << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) << GLB_REG_CTRL_RESET_DUMMY_POS))
+#define GLB_PKA_CLK_SEL               GLB_PKA_CLK_SEL
+#define GLB_PKA_CLK_SEL_POS           (24U)
+#define GLB_PKA_CLK_SEL_LEN           (1U)
+#define GLB_PKA_CLK_SEL_MSK           (((1U << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS)
+#define GLB_PKA_CLK_SEL_UMSK          (~(((1U << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS))
+
+/* 0x1C : swrst_cfg3 */
+#define GLB_SWRST_CFG3_OFFSET (0x1C)
+
+/* 0x20 : cgen_cfg0 */
+#define GLB_CGEN_CFG0_OFFSET (0x20)
+#define GLB_CGEN_M           GLB_CGEN_M
+#define GLB_CGEN_M_POS       (0U)
+#define GLB_CGEN_M_LEN       (8U)
+#define GLB_CGEN_M_MSK       (((1U << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS)
+#define GLB_CGEN_M_UMSK      (~(((1U << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS))
+
+/* 0x24 : cgen_cfg1 */
+#define GLB_CGEN_CFG1_OFFSET (0x24)
+#define GLB_CGEN_S1          GLB_CGEN_S1
+#define GLB_CGEN_S1_POS      (0U)
+#define GLB_CGEN_S1_LEN      (16U)
+#define GLB_CGEN_S1_MSK      (((1U << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS)
+#define GLB_CGEN_S1_UMSK     (~(((1U << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS))
+#define GLB_CGEN_S1A         GLB_CGEN_S1A
+#define GLB_CGEN_S1A_POS     (16U)
+#define GLB_CGEN_S1A_LEN     (16U)
+#define GLB_CGEN_S1A_MSK     (((1U << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS)
+#define GLB_CGEN_S1A_UMSK    (~(((1U << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS))
+
+/* 0x28 : cgen_cfg2 */
+#define GLB_CGEN_CFG2_OFFSET (0x28)
+#define GLB_CGEN_S2          GLB_CGEN_S2
+#define GLB_CGEN_S2_POS      (0U)
+#define GLB_CGEN_S2_LEN      (1U)
+#define GLB_CGEN_S2_MSK      (((1U << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS)
+#define GLB_CGEN_S2_UMSK     (~(((1U << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS))
+#define GLB_CGEN_S3          GLB_CGEN_S3
+#define GLB_CGEN_S3_POS      (4U)
+#define GLB_CGEN_S3_LEN      (1U)
+#define GLB_CGEN_S3_MSK      (((1U << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS)
+#define GLB_CGEN_S3_UMSK     (~(((1U << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS))
+
+/* 0x2C : cgen_cfg3 */
+#define GLB_CGEN_CFG3_OFFSET (0x2C)
+
+/* 0x30 : MBIST_CTL */
+#define GLB_MBIST_CTL_OFFSET            (0x30)
+#define GLB_IROM_MBIST_MODE             GLB_IROM_MBIST_MODE
+#define GLB_IROM_MBIST_MODE_POS         (0U)
+#define GLB_IROM_MBIST_MODE_LEN         (1U)
+#define GLB_IROM_MBIST_MODE_MSK         (((1U << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS)
+#define GLB_IROM_MBIST_MODE_UMSK        (~(((1U << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS))
+#define GLB_HSRAM_MEM_MBIST_MODE        GLB_HSRAM_MEM_MBIST_MODE
+#define GLB_HSRAM_MEM_MBIST_MODE_POS    (1U)
+#define GLB_HSRAM_MEM_MBIST_MODE_LEN    (1U)
+#define GLB_HSRAM_MEM_MBIST_MODE_MSK    (((1U << GLB_HSRAM_MEM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MEM_MBIST_MODE_POS)
+#define GLB_HSRAM_MEM_MBIST_MODE_UMSK   (~(((1U << GLB_HSRAM_MEM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MEM_MBIST_MODE_POS))
+#define GLB_HSRAM_CACHE_MBIST_MODE      GLB_HSRAM_CACHE_MBIST_MODE
+#define GLB_HSRAM_CACHE_MBIST_MODE_POS  (2U)
+#define GLB_HSRAM_CACHE_MBIST_MODE_LEN  (1U)
+#define GLB_HSRAM_CACHE_MBIST_MODE_MSK  (((1U << GLB_HSRAM_CACHE_MBIST_MODE_LEN) - 1) << GLB_HSRAM_CACHE_MBIST_MODE_POS)
+#define GLB_HSRAM_CACHE_MBIST_MODE_UMSK (~(((1U << GLB_HSRAM_CACHE_MBIST_MODE_LEN) - 1) << GLB_HSRAM_CACHE_MBIST_MODE_POS))
+#define GLB_TAG_MBIST_MODE              GLB_TAG_MBIST_MODE
+#define GLB_TAG_MBIST_MODE_POS          (3U)
+#define GLB_TAG_MBIST_MODE_LEN          (1U)
+#define GLB_TAG_MBIST_MODE_MSK          (((1U << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS)
+#define GLB_TAG_MBIST_MODE_UMSK         (~(((1U << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS))
+#define GLB_OCRAM_MBIST_MODE            GLB_OCRAM_MBIST_MODE
+#define GLB_OCRAM_MBIST_MODE_POS        (4U)
+#define GLB_OCRAM_MBIST_MODE_LEN        (1U)
+#define GLB_OCRAM_MBIST_MODE_MSK        (((1U << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS)
+#define GLB_OCRAM_MBIST_MODE_UMSK       (~(((1U << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS))
+#define GLB_EM_RAM_MBIST_MODE           GLB_EM_RAM_MBIST_MODE
+#define GLB_EM_RAM_MBIST_MODE_POS       (5U)
+#define GLB_EM_RAM_MBIST_MODE_LEN       (1U)
+#define GLB_EM_RAM_MBIST_MODE_MSK       (((1U << GLB_EM_RAM_MBIST_MODE_LEN) - 1) << GLB_EM_RAM_MBIST_MODE_POS)
+#define GLB_EM_RAM_MBIST_MODE_UMSK      (~(((1U << GLB_EM_RAM_MBIST_MODE_LEN) - 1) << GLB_EM_RAM_MBIST_MODE_POS))
+#define GLB_REG_MBIST_RST_N             GLB_REG_MBIST_RST_N
+#define GLB_REG_MBIST_RST_N_POS         (31U)
+#define GLB_REG_MBIST_RST_N_LEN         (1U)
+#define GLB_REG_MBIST_RST_N_MSK         (((1U << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS)
+#define GLB_REG_MBIST_RST_N_UMSK        (~(((1U << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS))
+
+/* 0x34 : MBIST_STAT */
+#define GLB_MBIST_STAT_OFFSET           (0x34)
+#define GLB_IROM_MBIST_DONE             GLB_IROM_MBIST_DONE
+#define GLB_IROM_MBIST_DONE_POS         (0U)
+#define GLB_IROM_MBIST_DONE_LEN         (1U)
+#define GLB_IROM_MBIST_DONE_MSK         (((1U << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS)
+#define GLB_IROM_MBIST_DONE_UMSK        (~(((1U << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS))
+#define GLB_HSRAM_MEM_MBIST_DONE        GLB_HSRAM_MEM_MBIST_DONE
+#define GLB_HSRAM_MEM_MBIST_DONE_POS    (1U)
+#define GLB_HSRAM_MEM_MBIST_DONE_LEN    (1U)
+#define GLB_HSRAM_MEM_MBIST_DONE_MSK    (((1U << GLB_HSRAM_MEM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MEM_MBIST_DONE_POS)
+#define GLB_HSRAM_MEM_MBIST_DONE_UMSK   (~(((1U << GLB_HSRAM_MEM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MEM_MBIST_DONE_POS))
+#define GLB_HSRAM_CACHE_MBIST_DONE      GLB_HSRAM_CACHE_MBIST_DONE
+#define GLB_HSRAM_CACHE_MBIST_DONE_POS  (2U)
+#define GLB_HSRAM_CACHE_MBIST_DONE_LEN  (1U)
+#define GLB_HSRAM_CACHE_MBIST_DONE_MSK  (((1U << GLB_HSRAM_CACHE_MBIST_DONE_LEN) - 1) << GLB_HSRAM_CACHE_MBIST_DONE_POS)
+#define GLB_HSRAM_CACHE_MBIST_DONE_UMSK (~(((1U << GLB_HSRAM_CACHE_MBIST_DONE_LEN) - 1) << GLB_HSRAM_CACHE_MBIST_DONE_POS))
+#define GLB_TAG_MBIST_DONE              GLB_TAG_MBIST_DONE
+#define GLB_TAG_MBIST_DONE_POS          (3U)
+#define GLB_TAG_MBIST_DONE_LEN          (1U)
+#define GLB_TAG_MBIST_DONE_MSK          (((1U << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS)
+#define GLB_TAG_MBIST_DONE_UMSK         (~(((1U << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS))
+#define GLB_OCRAM_MBIST_DONE            GLB_OCRAM_MBIST_DONE
+#define GLB_OCRAM_MBIST_DONE_POS        (4U)
+#define GLB_OCRAM_MBIST_DONE_LEN        (1U)
+#define GLB_OCRAM_MBIST_DONE_MSK        (((1U << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS)
+#define GLB_OCRAM_MBIST_DONE_UMSK       (~(((1U << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS))
+#define GLB_EM_RAM_MBIST_DONE           GLB_EM_RAM_MBIST_DONE
+#define GLB_EM_RAM_MBIST_DONE_POS       (5U)
+#define GLB_EM_RAM_MBIST_DONE_LEN       (1U)
+#define GLB_EM_RAM_MBIST_DONE_MSK       (((1U << GLB_EM_RAM_MBIST_DONE_LEN) - 1) << GLB_EM_RAM_MBIST_DONE_POS)
+#define GLB_EM_RAM_MBIST_DONE_UMSK      (~(((1U << GLB_EM_RAM_MBIST_DONE_LEN) - 1) << GLB_EM_RAM_MBIST_DONE_POS))
+#define GLB_IROM_MBIST_FAIL             GLB_IROM_MBIST_FAIL
+#define GLB_IROM_MBIST_FAIL_POS         (16U)
+#define GLB_IROM_MBIST_FAIL_LEN         (1U)
+#define GLB_IROM_MBIST_FAIL_MSK         (((1U << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS)
+#define GLB_IROM_MBIST_FAIL_UMSK        (~(((1U << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS))
+#define GLB_HSRAM_MEM_MBIST_FAIL        GLB_HSRAM_MEM_MBIST_FAIL
+#define GLB_HSRAM_MEM_MBIST_FAIL_POS    (17U)
+#define GLB_HSRAM_MEM_MBIST_FAIL_LEN    (1U)
+#define GLB_HSRAM_MEM_MBIST_FAIL_MSK    (((1U << GLB_HSRAM_MEM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MEM_MBIST_FAIL_POS)
+#define GLB_HSRAM_MEM_MBIST_FAIL_UMSK   (~(((1U << GLB_HSRAM_MEM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MEM_MBIST_FAIL_POS))
+#define GLB_HSRAM_CACHE_MBIST_FAIL      GLB_HSRAM_CACHE_MBIST_FAIL
+#define GLB_HSRAM_CACHE_MBIST_FAIL_POS  (18U)
+#define GLB_HSRAM_CACHE_MBIST_FAIL_LEN  (1U)
+#define GLB_HSRAM_CACHE_MBIST_FAIL_MSK  (((1U << GLB_HSRAM_CACHE_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_CACHE_MBIST_FAIL_POS)
+#define GLB_HSRAM_CACHE_MBIST_FAIL_UMSK (~(((1U << GLB_HSRAM_CACHE_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_CACHE_MBIST_FAIL_POS))
+#define GLB_TAG_MBIST_FAIL              GLB_TAG_MBIST_FAIL
+#define GLB_TAG_MBIST_FAIL_POS          (19U)
+#define GLB_TAG_MBIST_FAIL_LEN          (1U)
+#define GLB_TAG_MBIST_FAIL_MSK          (((1U << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS)
+#define GLB_TAG_MBIST_FAIL_UMSK         (~(((1U << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS))
+#define GLB_OCRAM_MBIST_FAIL            GLB_OCRAM_MBIST_FAIL
+#define GLB_OCRAM_MBIST_FAIL_POS        (20U)
+#define GLB_OCRAM_MBIST_FAIL_LEN        (1U)
+#define GLB_OCRAM_MBIST_FAIL_MSK        (((1U << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS)
+#define GLB_OCRAM_MBIST_FAIL_UMSK       (~(((1U << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS))
+#define GLB_EM_RAM_MBIST_FAIL           GLB_EM_RAM_MBIST_FAIL
+#define GLB_EM_RAM_MBIST_FAIL_POS       (21U)
+#define GLB_EM_RAM_MBIST_FAIL_LEN       (1U)
+#define GLB_EM_RAM_MBIST_FAIL_MSK       (((1U << GLB_EM_RAM_MBIST_FAIL_LEN) - 1) << GLB_EM_RAM_MBIST_FAIL_POS)
+#define GLB_EM_RAM_MBIST_FAIL_UMSK      (~(((1U << GLB_EM_RAM_MBIST_FAIL_LEN) - 1) << GLB_EM_RAM_MBIST_FAIL_POS))
+
+/* 0x50 : bmx_cfg1 */
+#define GLB_BMX_CFG1_OFFSET          (0x50)
+#define GLB_BMX_TIMEOUT_EN           GLB_BMX_TIMEOUT_EN
+#define GLB_BMX_TIMEOUT_EN_POS       (0U)
+#define GLB_BMX_TIMEOUT_EN_LEN       (4U)
+#define GLB_BMX_TIMEOUT_EN_MSK       (((1U << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS)
+#define GLB_BMX_TIMEOUT_EN_UMSK      (~(((1U << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS))
+#define GLB_BMX_ARB_MODE             GLB_BMX_ARB_MODE
+#define GLB_BMX_ARB_MODE_POS         (4U)
+#define GLB_BMX_ARB_MODE_LEN         (2U)
+#define GLB_BMX_ARB_MODE_MSK         (((1U << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS)
+#define GLB_BMX_ARB_MODE_UMSK        (~(((1U << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS))
+#define GLB_BMX_ERR_EN               GLB_BMX_ERR_EN
+#define GLB_BMX_ERR_EN_POS           (8U)
+#define GLB_BMX_ERR_EN_LEN           (1U)
+#define GLB_BMX_ERR_EN_MSK           (((1U << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS)
+#define GLB_BMX_ERR_EN_UMSK          (~(((1U << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS))
+#define GLB_BMX_BUSY_OPTION_DIS      GLB_BMX_BUSY_OPTION_DIS
+#define GLB_BMX_BUSY_OPTION_DIS_POS  (9U)
+#define GLB_BMX_BUSY_OPTION_DIS_LEN  (1U)
+#define GLB_BMX_BUSY_OPTION_DIS_MSK  (((1U << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS)
+#define GLB_BMX_BUSY_OPTION_DIS_UMSK (~(((1U << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS))
+#define GLB_BMX_GATING_DIS           GLB_BMX_GATING_DIS
+#define GLB_BMX_GATING_DIS_POS       (10U)
+#define GLB_BMX_GATING_DIS_LEN       (1U)
+#define GLB_BMX_GATING_DIS_MSK       (((1U << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS)
+#define GLB_BMX_GATING_DIS_UMSK      (~(((1U << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS))
+#define GLB_HSEL_OPTION              GLB_HSEL_OPTION
+#define GLB_HSEL_OPTION_POS          (12U)
+#define GLB_HSEL_OPTION_LEN          (4U)
+#define GLB_HSEL_OPTION_MSK          (((1U << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS)
+#define GLB_HSEL_OPTION_UMSK         (~(((1U << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS))
+#define GLB_PDS_APB_CFG              GLB_PDS_APB_CFG
+#define GLB_PDS_APB_CFG_POS          (16U)
+#define GLB_PDS_APB_CFG_LEN          (8U)
+#define GLB_PDS_APB_CFG_MSK          (((1U << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS)
+#define GLB_PDS_APB_CFG_UMSK         (~(((1U << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS))
+#define GLB_HBN_APB_CFG              GLB_HBN_APB_CFG
+#define GLB_HBN_APB_CFG_POS          (24U)
+#define GLB_HBN_APB_CFG_LEN          (8U)
+#define GLB_HBN_APB_CFG_MSK          (((1U << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS)
+#define GLB_HBN_APB_CFG_UMSK         (~(((1U << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS))
+
+/* 0x54 : bmx_cfg2 */
+#define GLB_BMX_CFG2_OFFSET       (0x54)
+#define GLB_BMX_ERR_ADDR_DIS      GLB_BMX_ERR_ADDR_DIS
+#define GLB_BMX_ERR_ADDR_DIS_POS  (0U)
+#define GLB_BMX_ERR_ADDR_DIS_LEN  (1U)
+#define GLB_BMX_ERR_ADDR_DIS_MSK  (((1U << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS)
+#define GLB_BMX_ERR_ADDR_DIS_UMSK (~(((1U << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS))
+#define GLB_BMX_ERR_DEC           GLB_BMX_ERR_DEC
+#define GLB_BMX_ERR_DEC_POS       (4U)
+#define GLB_BMX_ERR_DEC_LEN       (1U)
+#define GLB_BMX_ERR_DEC_MSK       (((1U << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS)
+#define GLB_BMX_ERR_DEC_UMSK      (~(((1U << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS))
+#define GLB_BMX_ERR_TZ            GLB_BMX_ERR_TZ
+#define GLB_BMX_ERR_TZ_POS        (5U)
+#define GLB_BMX_ERR_TZ_LEN        (1U)
+#define GLB_BMX_ERR_TZ_MSK        (((1U << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS)
+#define GLB_BMX_ERR_TZ_UMSK       (~(((1U << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS))
+#define GLB_REG_W_THRE_BMX        GLB_REG_W_THRE_BMX
+#define GLB_REG_W_THRE_BMX_POS    (8U)
+#define GLB_REG_W_THRE_BMX_LEN    (2U)
+#define GLB_REG_W_THRE_BMX_MSK    (((1U << GLB_REG_W_THRE_BMX_LEN) - 1) << GLB_REG_W_THRE_BMX_POS)
+#define GLB_REG_W_THRE_BMX_UMSK   (~(((1U << GLB_REG_W_THRE_BMX_LEN) - 1) << GLB_REG_W_THRE_BMX_POS))
+#define GLB_REG_W_THRE_L1C        GLB_REG_W_THRE_L1C
+#define GLB_REG_W_THRE_L1C_POS    (10U)
+#define GLB_REG_W_THRE_L1C_LEN    (2U)
+#define GLB_REG_W_THRE_L1C_MSK    (((1U << GLB_REG_W_THRE_L1C_LEN) - 1) << GLB_REG_W_THRE_L1C_POS)
+#define GLB_REG_W_THRE_L1C_UMSK   (~(((1U << GLB_REG_W_THRE_L1C_LEN) - 1) << GLB_REG_W_THRE_L1C_POS))
+#define GLB_BMX_DBG_SEL           GLB_BMX_DBG_SEL
+#define GLB_BMX_DBG_SEL_POS       (28U)
+#define GLB_BMX_DBG_SEL_LEN       (4U)
+#define GLB_BMX_DBG_SEL_MSK       (((1U << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS)
+#define GLB_BMX_DBG_SEL_UMSK      (~(((1U << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS))
+
+/* 0x58 : bmx_err_addr */
+#define GLB_BMX_ERR_ADDR_OFFSET (0x58)
+#define GLB_BMX_ERR_ADDR        GLB_BMX_ERR_ADDR
+#define GLB_BMX_ERR_ADDR_POS    (0U)
+#define GLB_BMX_ERR_ADDR_LEN    (32U)
+#define GLB_BMX_ERR_ADDR_MSK    (((1U << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS)
+#define GLB_BMX_ERR_ADDR_UMSK   (~(((1U << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS))
+
+/* 0x5C : bmx_dbg_out */
+#define GLB_BMX_DBG_OUT_OFFSET (0x5C)
+#define GLB_BMX_DBG_OUT        GLB_BMX_DBG_OUT
+#define GLB_BMX_DBG_OUT_POS    (0U)
+#define GLB_BMX_DBG_OUT_LEN    (32U)
+#define GLB_BMX_DBG_OUT_MSK    (((1U << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS)
+#define GLB_BMX_DBG_OUT_UMSK   (~(((1U << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS))
+
+/* 0x60 : rsv0 */
+#define GLB_RSV0_OFFSET (0x60)
+
+/* 0x64 : rsv1 */
+#define GLB_RSV1_OFFSET (0x64)
+
+/* 0x68 : rsv2 */
+#define GLB_RSV2_OFFSET (0x68)
+
+/* 0x6C : rsv3 */
+#define GLB_RSV3_OFFSET (0x6C)
+
+/* 0x70 : sram_ret */
+#define GLB_SRAM_RET_OFFSET   (0x70)
+#define GLB_REG_SRAM_RET      GLB_REG_SRAM_RET
+#define GLB_REG_SRAM_RET_POS  (0U)
+#define GLB_REG_SRAM_RET_LEN  (32U)
+#define GLB_REG_SRAM_RET_MSK  (((1U << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS)
+#define GLB_REG_SRAM_RET_UMSK (~(((1U << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS))
+
+/* 0x74 : sram_slp */
+#define GLB_SRAM_SLP_OFFSET   (0x74)
+#define GLB_REG_SRAM_SLP      GLB_REG_SRAM_SLP
+#define GLB_REG_SRAM_SLP_POS  (0U)
+#define GLB_REG_SRAM_SLP_LEN  (32U)
+#define GLB_REG_SRAM_SLP_MSK  (((1U << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS)
+#define GLB_REG_SRAM_SLP_UMSK (~(((1U << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS))
+
+/* 0x78 : sram_parm */
+#define GLB_SRAM_PARM_OFFSET   (0x78)
+#define GLB_REG_SRAM_PARM      GLB_REG_SRAM_PARM
+#define GLB_REG_SRAM_PARM_POS  (0U)
+#define GLB_REG_SRAM_PARM_LEN  (32U)
+#define GLB_REG_SRAM_PARM_MSK  (((1U << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS)
+#define GLB_REG_SRAM_PARM_UMSK (~(((1U << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS))
+
+/* 0x7C : seam_misc */
+#define GLB_SEAM_MISC_OFFSET (0x7C)
+#define GLB_EM_SEL           GLB_EM_SEL
+#define GLB_EM_SEL_POS       (0U)
+#define GLB_EM_SEL_LEN       (4U)
+#define GLB_EM_SEL_MSK       (((1U << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS)
+#define GLB_EM_SEL_UMSK      (~(((1U << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS))
+
+/* 0x80 : glb_parm */
+#define GLB_PARM_OFFSET                   (0x80)
+#define GLB_JTAG_SWAP_SET                 GLB_JTAG_SWAP_SET
+#define GLB_JTAG_SWAP_SET_POS             (0U)
+#define GLB_JTAG_SWAP_SET_LEN             (8U)
+#define GLB_JTAG_SWAP_SET_MSK             (((1U << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS)
+#define GLB_JTAG_SWAP_SET_UMSK            (~(((1U << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS))
+#define GLB_CFG_SFLASH2_SWAP_IO0_IO3      GLB_CFG_SFLASH2_SWAP_IO0_IO3
+#define GLB_CFG_SFLASH2_SWAP_IO0_IO3_POS  (8U)
+#define GLB_CFG_SFLASH2_SWAP_IO0_IO3_LEN  (1U)
+#define GLB_CFG_SFLASH2_SWAP_IO0_IO3_MSK  (((1U << GLB_CFG_SFLASH2_SWAP_IO0_IO3_LEN) - 1) << GLB_CFG_SFLASH2_SWAP_IO0_IO3_POS)
+#define GLB_CFG_SFLASH2_SWAP_IO0_IO3_UMSK (~(((1U << GLB_CFG_SFLASH2_SWAP_IO0_IO3_LEN) - 1) << GLB_CFG_SFLASH2_SWAP_IO0_IO3_POS))
+#define GLB_CFG_SFLASH2_SWAP_CS_IO2       GLB_CFG_SFLASH2_SWAP_CS_IO2
+#define GLB_CFG_SFLASH2_SWAP_CS_IO2_POS   (9U)
+#define GLB_CFG_SFLASH2_SWAP_CS_IO2_LEN   (1U)
+#define GLB_CFG_SFLASH2_SWAP_CS_IO2_MSK   (((1U << GLB_CFG_SFLASH2_SWAP_CS_IO2_LEN) - 1) << GLB_CFG_SFLASH2_SWAP_CS_IO2_POS)
+#define GLB_CFG_SFLASH2_SWAP_CS_IO2_UMSK  (~(((1U << GLB_CFG_SFLASH2_SWAP_CS_IO2_LEN) - 1) << GLB_CFG_SFLASH2_SWAP_CS_IO2_POS))
+#define GLB_CFG_FLASH_SCENARIO            GLB_CFG_FLASH_SCENARIO
+#define GLB_CFG_FLASH_SCENARIO_POS        (10U)
+#define GLB_CFG_FLASH_SCENARIO_LEN        (2U)
+#define GLB_CFG_FLASH_SCENARIO_MSK        (((1U << GLB_CFG_FLASH_SCENARIO_LEN) - 1) << GLB_CFG_FLASH_SCENARIO_POS)
+#define GLB_CFG_FLASH_SCENARIO_UMSK       (~(((1U << GLB_CFG_FLASH_SCENARIO_LEN) - 1) << GLB_CFG_FLASH_SCENARIO_POS))
+#define GLB_REG_SPI_0_MASTER_MODE         GLB_REG_SPI_0_MASTER_MODE
+#define GLB_REG_SPI_0_MASTER_MODE_POS     (12U)
+#define GLB_REG_SPI_0_MASTER_MODE_LEN     (1U)
+#define GLB_REG_SPI_0_MASTER_MODE_MSK     (((1U << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) << GLB_REG_SPI_0_MASTER_MODE_POS)
+#define GLB_REG_SPI_0_MASTER_MODE_UMSK    (~(((1U << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) << GLB_REG_SPI_0_MASTER_MODE_POS))
+#define GLB_REG_SPI_0_SWAP                GLB_REG_SPI_0_SWAP
+#define GLB_REG_SPI_0_SWAP_POS            (13U)
+#define GLB_REG_SPI_0_SWAP_LEN            (1U)
+#define GLB_REG_SPI_0_SWAP_MSK            (((1U << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS)
+#define GLB_REG_SPI_0_SWAP_UMSK           (~(((1U << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS))
+#define GLB_REG_CCI_USE_JTAG_PIN          GLB_REG_CCI_USE_JTAG_PIN
+#define GLB_REG_CCI_USE_JTAG_PIN_POS      (16U)
+#define GLB_REG_CCI_USE_JTAG_PIN_LEN      (1U)
+#define GLB_REG_CCI_USE_JTAG_PIN_MSK      (((1U << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) << GLB_REG_CCI_USE_JTAG_PIN_POS)
+#define GLB_REG_CCI_USE_JTAG_PIN_UMSK     (~(((1U << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) << GLB_REG_CCI_USE_JTAG_PIN_POS))
+#define GLB_P1_ADC_TEST_WITH_CCI          GLB_P1_ADC_TEST_WITH_CCI
+#define GLB_P1_ADC_TEST_WITH_CCI_POS      (17U)
+#define GLB_P1_ADC_TEST_WITH_CCI_LEN      (1U)
+#define GLB_P1_ADC_TEST_WITH_CCI_MSK      (((1U << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) << GLB_P1_ADC_TEST_WITH_CCI_POS)
+#define GLB_P1_ADC_TEST_WITH_CCI_UMSK     (~(((1U << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) << GLB_P1_ADC_TEST_WITH_CCI_POS))
+#define GLB_P2_DAC_TEST_WITH_CCI          GLB_P2_DAC_TEST_WITH_CCI
+#define GLB_P2_DAC_TEST_WITH_CCI_POS      (18U)
+#define GLB_P2_DAC_TEST_WITH_CCI_LEN      (1U)
+#define GLB_P2_DAC_TEST_WITH_CCI_MSK      (((1U << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) << GLB_P2_DAC_TEST_WITH_CCI_POS)
+#define GLB_P2_DAC_TEST_WITH_CCI_UMSK     (~(((1U << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) << GLB_P2_DAC_TEST_WITH_CCI_POS))
+#define GLB_P3_CCI_USE_IO_0_2_7           GLB_P3_CCI_USE_IO_0_2_7
+#define GLB_P3_CCI_USE_IO_0_2_7_POS       (19U)
+#define GLB_P3_CCI_USE_IO_0_2_7_LEN       (1U)
+#define GLB_P3_CCI_USE_IO_0_2_7_MSK       (((1U << GLB_P3_CCI_USE_IO_0_2_7_LEN) - 1) << GLB_P3_CCI_USE_IO_0_2_7_POS)
+#define GLB_P3_CCI_USE_IO_0_2_7_UMSK      (~(((1U << GLB_P3_CCI_USE_IO_0_2_7_LEN) - 1) << GLB_P3_CCI_USE_IO_0_2_7_POS))
+#define GLB_P4_ADC_TEST_WITH_JTAG         GLB_P4_ADC_TEST_WITH_JTAG
+#define GLB_P4_ADC_TEST_WITH_JTAG_POS     (20U)
+#define GLB_P4_ADC_TEST_WITH_JTAG_LEN     (1U)
+#define GLB_P4_ADC_TEST_WITH_JTAG_MSK     (((1U << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) << GLB_P4_ADC_TEST_WITH_JTAG_POS)
+#define GLB_P4_ADC_TEST_WITH_JTAG_UMSK    (~(((1U << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) << GLB_P4_ADC_TEST_WITH_JTAG_POS))
+#define GLB_P5_DAC_TEST_WITH_JTAG         GLB_P5_DAC_TEST_WITH_JTAG
+#define GLB_P5_DAC_TEST_WITH_JTAG_POS     (21U)
+#define GLB_P5_DAC_TEST_WITH_JTAG_LEN     (1U)
+#define GLB_P5_DAC_TEST_WITH_JTAG_MSK     (((1U << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) << GLB_P5_DAC_TEST_WITH_JTAG_POS)
+#define GLB_P5_DAC_TEST_WITH_JTAG_UMSK    (~(((1U << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) << GLB_P5_DAC_TEST_WITH_JTAG_POS))
+#define GLB_P6_JTAG_USE_IO_0_2_7          GLB_P6_JTAG_USE_IO_0_2_7
+#define GLB_P6_JTAG_USE_IO_0_2_7_POS      (23U)
+#define GLB_P6_JTAG_USE_IO_0_2_7_LEN      (1U)
+#define GLB_P6_JTAG_USE_IO_0_2_7_MSK      (((1U << GLB_P6_JTAG_USE_IO_0_2_7_LEN) - 1) << GLB_P6_JTAG_USE_IO_0_2_7_POS)
+#define GLB_P6_JTAG_USE_IO_0_2_7_UMSK     (~(((1U << GLB_P6_JTAG_USE_IO_0_2_7_LEN) - 1) << GLB_P6_JTAG_USE_IO_0_2_7_POS))
+#define GLB_UART_SWAP_SET                 GLB_UART_SWAP_SET
+#define GLB_UART_SWAP_SET_POS             (24U)
+#define GLB_UART_SWAP_SET_LEN             (4U)
+#define GLB_UART_SWAP_SET_MSK             (((1U << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS)
+#define GLB_UART_SWAP_SET_UMSK            (~(((1U << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS))
+#define GLB_REG_KYS_DRV_VAL               GLB_REG_KYS_DRV_VAL
+#define GLB_REG_KYS_DRV_VAL_POS           (29U)
+#define GLB_REG_KYS_DRV_VAL_LEN           (1U)
+#define GLB_REG_KYS_DRV_VAL_MSK           (((1U << GLB_REG_KYS_DRV_VAL_LEN) - 1) << GLB_REG_KYS_DRV_VAL_POS)
+#define GLB_REG_KYS_DRV_VAL_UMSK          (~(((1U << GLB_REG_KYS_DRV_VAL_LEN) - 1) << GLB_REG_KYS_DRV_VAL_POS))
+#define GLB_REG_EXT_RST_SMT               GLB_REG_EXT_RST_SMT
+#define GLB_REG_EXT_RST_SMT_POS           (30U)
+#define GLB_REG_EXT_RST_SMT_LEN           (1U)
+#define GLB_REG_EXT_RST_SMT_MSK           (((1U << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS)
+#define GLB_REG_EXT_RST_SMT_UMSK          (~(((1U << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS))
+#define GLB_PIN_SEL_EMAC_CAM              GLB_PIN_SEL_EMAC_CAM
+#define GLB_PIN_SEL_EMAC_CAM_POS          (31U)
+#define GLB_PIN_SEL_EMAC_CAM_LEN          (1U)
+#define GLB_PIN_SEL_EMAC_CAM_MSK          (((1U << GLB_PIN_SEL_EMAC_CAM_LEN) - 1) << GLB_PIN_SEL_EMAC_CAM_POS)
+#define GLB_PIN_SEL_EMAC_CAM_UMSK         (~(((1U << GLB_PIN_SEL_EMAC_CAM_LEN) - 1) << GLB_PIN_SEL_EMAC_CAM_POS))
+
+/* 0x84 : PDM_CLK_CTRL */
+#define GLB_PDM_CLK_CTRL_OFFSET   (0x84)
+#define GLB_REG_PDM0_CLK_DIV      GLB_REG_PDM0_CLK_DIV
+#define GLB_REG_PDM0_CLK_DIV_POS  (0U)
+#define GLB_REG_PDM0_CLK_DIV_LEN  (6U)
+#define GLB_REG_PDM0_CLK_DIV_MSK  (((1U << GLB_REG_PDM0_CLK_DIV_LEN) - 1) << GLB_REG_PDM0_CLK_DIV_POS)
+#define GLB_REG_PDM0_CLK_DIV_UMSK (~(((1U << GLB_REG_PDM0_CLK_DIV_LEN) - 1) << GLB_REG_PDM0_CLK_DIV_POS))
+#define GLB_REG_PDM0_CLK_EN       GLB_REG_PDM0_CLK_EN
+#define GLB_REG_PDM0_CLK_EN_POS   (7U)
+#define GLB_REG_PDM0_CLK_EN_LEN   (1U)
+#define GLB_REG_PDM0_CLK_EN_MSK   (((1U << GLB_REG_PDM0_CLK_EN_LEN) - 1) << GLB_REG_PDM0_CLK_EN_POS)
+#define GLB_REG_PDM0_CLK_EN_UMSK  (~(((1U << GLB_REG_PDM0_CLK_EN_LEN) - 1) << GLB_REG_PDM0_CLK_EN_POS))
+
+/* 0x88 : GPIO_USE_PSRAM__IO */
+#define GLB_GPIO_USE_PSRAM__IO_OFFSET  (0x88)
+#define GLB_CFG_GPIO_USE_PSRAM_IO      GLB_CFG_GPIO_USE_PSRAM_IO
+#define GLB_CFG_GPIO_USE_PSRAM_IO_POS  (0U)
+#define GLB_CFG_GPIO_USE_PSRAM_IO_LEN  (6U)
+#define GLB_CFG_GPIO_USE_PSRAM_IO_MSK  (((1U << GLB_CFG_GPIO_USE_PSRAM_IO_LEN) - 1) << GLB_CFG_GPIO_USE_PSRAM_IO_POS)
+#define GLB_CFG_GPIO_USE_PSRAM_IO_UMSK (~(((1U << GLB_CFG_GPIO_USE_PSRAM_IO_LEN) - 1) << GLB_CFG_GPIO_USE_PSRAM_IO_POS))
+
+/* 0x90 : CPU_CLK_CFG */
+#define GLB_CPU_CLK_CFG_OFFSET      (0x90)
+#define GLB_CPU_RTC_DIV             GLB_CPU_RTC_DIV
+#define GLB_CPU_RTC_DIV_POS         (0U)
+#define GLB_CPU_RTC_DIV_LEN         (17U)
+#define GLB_CPU_RTC_DIV_MSK         (((1U << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS)
+#define GLB_CPU_RTC_DIV_UMSK        (~(((1U << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS))
+#define GLB_CPU_RTC_EN              GLB_CPU_RTC_EN
+#define GLB_CPU_RTC_EN_POS          (18U)
+#define GLB_CPU_RTC_EN_LEN          (1U)
+#define GLB_CPU_RTC_EN_MSK          (((1U << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS)
+#define GLB_CPU_RTC_EN_UMSK         (~(((1U << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS))
+#define GLB_CPU_RTC_SEL             GLB_CPU_RTC_SEL
+#define GLB_CPU_RTC_SEL_POS         (19U)
+#define GLB_CPU_RTC_SEL_LEN         (1U)
+#define GLB_CPU_RTC_SEL_MSK         (((1U << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS)
+#define GLB_CPU_RTC_SEL_UMSK        (~(((1U << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS))
+#define GLB_DEBUG_NDRESET_GATE      GLB_DEBUG_NDRESET_GATE
+#define GLB_DEBUG_NDRESET_GATE_POS  (20U)
+#define GLB_DEBUG_NDRESET_GATE_LEN  (1U)
+#define GLB_DEBUG_NDRESET_GATE_MSK  (((1U << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS)
+#define GLB_DEBUG_NDRESET_GATE_UMSK (~(((1U << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS))
+
+/* 0xA4 : GPADC_32M_SRC_CTRL */
+#define GLB_GPADC_32M_SRC_CTRL_OFFSET (0xA4)
+#define GLB_GPADC_32M_CLK_DIV         GLB_GPADC_32M_CLK_DIV
+#define GLB_GPADC_32M_CLK_DIV_POS     (0U)
+#define GLB_GPADC_32M_CLK_DIV_LEN     (6U)
+#define GLB_GPADC_32M_CLK_DIV_MSK     (((1U << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS)
+#define GLB_GPADC_32M_CLK_DIV_UMSK    (~(((1U << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS))
+#define GLB_GPADC_32M_CLK_SEL         GLB_GPADC_32M_CLK_SEL
+#define GLB_GPADC_32M_CLK_SEL_POS     (7U)
+#define GLB_GPADC_32M_CLK_SEL_LEN     (1U)
+#define GLB_GPADC_32M_CLK_SEL_MSK     (((1U << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS)
+#define GLB_GPADC_32M_CLK_SEL_UMSK    (~(((1U << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS))
+#define GLB_GPADC_32M_DIV_EN          GLB_GPADC_32M_DIV_EN
+#define GLB_GPADC_32M_DIV_EN_POS      (8U)
+#define GLB_GPADC_32M_DIV_EN_LEN      (1U)
+#define GLB_GPADC_32M_DIV_EN_MSK      (((1U << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS)
+#define GLB_GPADC_32M_DIV_EN_UMSK     (~(((1U << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS))
+
+/* 0xA8 : DIG32K_WAKEUP_CTRL */
+#define GLB_DIG32K_WAKEUP_CTRL_OFFSET   (0xA8)
+#define GLB_DIG_32K_DIV                 GLB_DIG_32K_DIV
+#define GLB_DIG_32K_DIV_POS             (0U)
+#define GLB_DIG_32K_DIV_LEN             (11U)
+#define GLB_DIG_32K_DIV_MSK             (((1U << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS)
+#define GLB_DIG_32K_DIV_UMSK            (~(((1U << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS))
+#define GLB_DIG_32K_EN                  GLB_DIG_32K_EN
+#define GLB_DIG_32K_EN_POS              (12U)
+#define GLB_DIG_32K_EN_LEN              (1U)
+#define GLB_DIG_32K_EN_MSK              (((1U << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS)
+#define GLB_DIG_32K_EN_UMSK             (~(((1U << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS))
+#define GLB_DIG_32K_COMP                GLB_DIG_32K_COMP
+#define GLB_DIG_32K_COMP_POS            (13U)
+#define GLB_DIG_32K_COMP_LEN            (1U)
+#define GLB_DIG_32K_COMP_MSK            (((1U << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS)
+#define GLB_DIG_32K_COMP_UMSK           (~(((1U << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS))
+#define GLB_DIG_512K_DIV                GLB_DIG_512K_DIV
+#define GLB_DIG_512K_DIV_POS            (16U)
+#define GLB_DIG_512K_DIV_LEN            (7U)
+#define GLB_DIG_512K_DIV_MSK            (((1U << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS)
+#define GLB_DIG_512K_DIV_UMSK           (~(((1U << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS))
+#define GLB_DIG_512K_EN                 GLB_DIG_512K_EN
+#define GLB_DIG_512K_EN_POS             (24U)
+#define GLB_DIG_512K_EN_LEN             (1U)
+#define GLB_DIG_512K_EN_MSK             (((1U << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS)
+#define GLB_DIG_512K_EN_UMSK            (~(((1U << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS))
+#define GLB_DIG_512K_COMP               GLB_DIG_512K_COMP
+#define GLB_DIG_512K_COMP_POS           (25U)
+#define GLB_DIG_512K_COMP_LEN           (1U)
+#define GLB_DIG_512K_COMP_MSK           (((1U << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS)
+#define GLB_DIG_512K_COMP_UMSK          (~(((1U << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS))
+#define GLB_DIG_CLK_SRC_SEL             GLB_DIG_CLK_SRC_SEL
+#define GLB_DIG_CLK_SRC_SEL_POS         (28U)
+#define GLB_DIG_CLK_SRC_SEL_LEN         (2U)
+#define GLB_DIG_CLK_SRC_SEL_MSK         (((1U << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS)
+#define GLB_DIG_CLK_SRC_SEL_UMSK        (~(((1U << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS))
+#define GLB_REG_EN_PLATFORM_WAKEUP      GLB_REG_EN_PLATFORM_WAKEUP
+#define GLB_REG_EN_PLATFORM_WAKEUP_POS  (31U)
+#define GLB_REG_EN_PLATFORM_WAKEUP_LEN  (1U)
+#define GLB_REG_EN_PLATFORM_WAKEUP_MSK  (((1U << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) << GLB_REG_EN_PLATFORM_WAKEUP_POS)
+#define GLB_REG_EN_PLATFORM_WAKEUP_UMSK (~(((1U << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) << GLB_REG_EN_PLATFORM_WAKEUP_POS))
+
+/* 0xAC : WIFI_BT_COEX_CTRL */
+#define GLB_WIFI_BT_COEX_CTRL_OFFSET (0xAC)
+#define GLB_COEX_BT_CHANNEL          GLB_COEX_BT_CHANNEL
+#define GLB_COEX_BT_CHANNEL_POS      (0U)
+#define GLB_COEX_BT_CHANNEL_LEN      (7U)
+#define GLB_COEX_BT_CHANNEL_MSK      (((1U << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS)
+#define GLB_COEX_BT_CHANNEL_UMSK     (~(((1U << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS))
+#define GLB_COEX_BT_PTI              GLB_COEX_BT_PTI
+#define GLB_COEX_BT_PTI_POS          (7U)
+#define GLB_COEX_BT_PTI_LEN          (4U)
+#define GLB_COEX_BT_PTI_MSK          (((1U << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS)
+#define GLB_COEX_BT_PTI_UMSK         (~(((1U << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS))
+#define GLB_COEX_BT_BW               GLB_COEX_BT_BW
+#define GLB_COEX_BT_BW_POS           (11U)
+#define GLB_COEX_BT_BW_LEN           (1U)
+#define GLB_COEX_BT_BW_MSK           (((1U << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS)
+#define GLB_COEX_BT_BW_UMSK          (~(((1U << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS))
+#define GLB_EN_GPIO_BT_COEX          GLB_EN_GPIO_BT_COEX
+#define GLB_EN_GPIO_BT_COEX_POS      (12U)
+#define GLB_EN_GPIO_BT_COEX_LEN      (1U)
+#define GLB_EN_GPIO_BT_COEX_MSK      (((1U << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS)
+#define GLB_EN_GPIO_BT_COEX_UMSK     (~(((1U << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS))
+
+/* 0xB0 : BZ_COEX_CTRL */
+#define GLB_BZ_COEX_CTRL_OFFSET    (0xB0)
+#define GLB_COEX_EN                GLB_COEX_EN
+#define GLB_COEX_EN_POS            (0U)
+#define GLB_COEX_EN_LEN            (1U)
+#define GLB_COEX_EN_MSK            (((1U << GLB_COEX_EN_LEN) - 1) << GLB_COEX_EN_POS)
+#define GLB_COEX_EN_UMSK           (~(((1U << GLB_COEX_EN_LEN) - 1) << GLB_COEX_EN_POS))
+#define GLB_WLAN_EN                GLB_WLAN_EN
+#define GLB_WLAN_EN_POS            (1U)
+#define GLB_WLAN_EN_LEN            (1U)
+#define GLB_WLAN_EN_MSK            (((1U << GLB_WLAN_EN_LEN) - 1) << GLB_WLAN_EN_POS)
+#define GLB_WLAN_EN_UMSK           (~(((1U << GLB_WLAN_EN_LEN) - 1) << GLB_WLAN_EN_POS))
+#define GLB_BLE_RX_IGNORE          GLB_BLE_RX_IGNORE
+#define GLB_BLE_RX_IGNORE_POS      (2U)
+#define GLB_BLE_RX_IGNORE_LEN      (1U)
+#define GLB_BLE_RX_IGNORE_MSK      (((1U << GLB_BLE_RX_IGNORE_LEN) - 1) << GLB_BLE_RX_IGNORE_POS)
+#define GLB_BLE_RX_IGNORE_UMSK     (~(((1U << GLB_BLE_RX_IGNORE_LEN) - 1) << GLB_BLE_RX_IGNORE_POS))
+#define GLB_M154_RX_IGNORE         GLB_M154_RX_IGNORE
+#define GLB_M154_RX_IGNORE_POS     (3U)
+#define GLB_M154_RX_IGNORE_LEN     (1U)
+#define GLB_M154_RX_IGNORE_MSK     (((1U << GLB_M154_RX_IGNORE_LEN) - 1) << GLB_M154_RX_IGNORE_POS)
+#define GLB_M154_RX_IGNORE_UMSK    (~(((1U << GLB_M154_RX_IGNORE_LEN) - 1) << GLB_M154_RX_IGNORE_POS))
+#define GLB_BZ_PRI_THR             GLB_BZ_PRI_THR
+#define GLB_BZ_PRI_THR_POS         (4U)
+#define GLB_BZ_PRI_THR_LEN         (4U)
+#define GLB_BZ_PRI_THR_MSK         (((1U << GLB_BZ_PRI_THR_LEN) - 1) << GLB_BZ_PRI_THR_POS)
+#define GLB_BZ_PRI_THR_UMSK        (~(((1U << GLB_BZ_PRI_THR_LEN) - 1) << GLB_BZ_PRI_THR_POS))
+#define GLB_BZ_PRI_EN              GLB_BZ_PRI_EN
+#define GLB_BZ_PRI_EN_POS          (8U)
+#define GLB_BZ_PRI_EN_LEN          (1U)
+#define GLB_BZ_PRI_EN_MSK          (((1U << GLB_BZ_PRI_EN_LEN) - 1) << GLB_BZ_PRI_EN_POS)
+#define GLB_BZ_PRI_EN_UMSK         (~(((1U << GLB_BZ_PRI_EN_LEN) - 1) << GLB_BZ_PRI_EN_POS))
+#define GLB_BZ_PRI_POL             GLB_BZ_PRI_POL
+#define GLB_BZ_PRI_POL_POS         (9U)
+#define GLB_BZ_PRI_POL_LEN         (1U)
+#define GLB_BZ_PRI_POL_MSK         (((1U << GLB_BZ_PRI_POL_LEN) - 1) << GLB_BZ_PRI_POL_POS)
+#define GLB_BZ_PRI_POL_UMSK        (~(((1U << GLB_BZ_PRI_POL_LEN) - 1) << GLB_BZ_PRI_POL_POS))
+#define GLB_BZ_ACTIVE_POL          GLB_BZ_ACTIVE_POL
+#define GLB_BZ_ACTIVE_POL_POS      (10U)
+#define GLB_BZ_ACTIVE_POL_LEN      (1U)
+#define GLB_BZ_ACTIVE_POL_MSK      (((1U << GLB_BZ_ACTIVE_POL_LEN) - 1) << GLB_BZ_ACTIVE_POL_POS)
+#define GLB_BZ_ACTIVE_POL_UMSK     (~(((1U << GLB_BZ_ACTIVE_POL_LEN) - 1) << GLB_BZ_ACTIVE_POL_POS))
+#define GLB_BZ_ABORT_POL           GLB_BZ_ABORT_POL
+#define GLB_BZ_ABORT_POL_POS       (11U)
+#define GLB_BZ_ABORT_POL_LEN       (1U)
+#define GLB_BZ_ABORT_POL_MSK       (((1U << GLB_BZ_ABORT_POL_LEN) - 1) << GLB_BZ_ABORT_POL_POS)
+#define GLB_BZ_ABORT_POL_UMSK      (~(((1U << GLB_BZ_ABORT_POL_LEN) - 1) << GLB_BZ_ABORT_POL_POS))
+#define GLB_COEX_PRI               GLB_COEX_PRI
+#define GLB_COEX_PRI_POS           (12U)
+#define GLB_COEX_PRI_LEN           (1U)
+#define GLB_COEX_PRI_MSK           (((1U << GLB_COEX_PRI_LEN) - 1) << GLB_COEX_PRI_POS)
+#define GLB_COEX_PRI_UMSK          (~(((1U << GLB_COEX_PRI_LEN) - 1) << GLB_COEX_PRI_POS))
+#define GLB_FORCE_M154_WIN         GLB_FORCE_M154_WIN
+#define GLB_FORCE_M154_WIN_POS     (13U)
+#define GLB_FORCE_M154_WIN_LEN     (1U)
+#define GLB_FORCE_M154_WIN_MSK     (((1U << GLB_FORCE_M154_WIN_LEN) - 1) << GLB_FORCE_M154_WIN_POS)
+#define GLB_FORCE_M154_WIN_UMSK    (~(((1U << GLB_FORCE_M154_WIN_LEN) - 1) << GLB_FORCE_M154_WIN_POS))
+#define GLB_FORCE_BLE_WIN          GLB_FORCE_BLE_WIN
+#define GLB_FORCE_BLE_WIN_POS      (14U)
+#define GLB_FORCE_BLE_WIN_LEN      (1U)
+#define GLB_FORCE_BLE_WIN_MSK      (((1U << GLB_FORCE_BLE_WIN_LEN) - 1) << GLB_FORCE_BLE_WIN_POS)
+#define GLB_FORCE_BLE_WIN_UMSK     (~(((1U << GLB_FORCE_BLE_WIN_LEN) - 1) << GLB_FORCE_BLE_WIN_POS))
+#define GLB_COEX_OPTION            GLB_COEX_OPTION
+#define GLB_COEX_OPTION_POS        (15U)
+#define GLB_COEX_OPTION_LEN        (1U)
+#define GLB_COEX_OPTION_MSK        (((1U << GLB_COEX_OPTION_LEN) - 1) << GLB_COEX_OPTION_POS)
+#define GLB_COEX_OPTION_UMSK       (~(((1U << GLB_COEX_OPTION_LEN) - 1) << GLB_COEX_OPTION_POS))
+#define GLB_COEX_FORCE_CH          GLB_COEX_FORCE_CH
+#define GLB_COEX_FORCE_CH_POS      (16U)
+#define GLB_COEX_FORCE_CH_LEN      (7U)
+#define GLB_COEX_FORCE_CH_MSK      (((1U << GLB_COEX_FORCE_CH_LEN) - 1) << GLB_COEX_FORCE_CH_POS)
+#define GLB_COEX_FORCE_CH_UMSK     (~(((1U << GLB_COEX_FORCE_CH_LEN) - 1) << GLB_COEX_FORCE_CH_POS))
+#define GLB_M154_RX_ABORT_DIS      GLB_M154_RX_ABORT_DIS
+#define GLB_M154_RX_ABORT_DIS_POS  (24U)
+#define GLB_M154_RX_ABORT_DIS_LEN  (1U)
+#define GLB_M154_RX_ABORT_DIS_MSK  (((1U << GLB_M154_RX_ABORT_DIS_LEN) - 1) << GLB_M154_RX_ABORT_DIS_POS)
+#define GLB_M154_RX_ABORT_DIS_UMSK (~(((1U << GLB_M154_RX_ABORT_DIS_LEN) - 1) << GLB_M154_RX_ABORT_DIS_POS))
+#define GLB_M154_TX_ABORT_DIS      GLB_M154_TX_ABORT_DIS
+#define GLB_M154_TX_ABORT_DIS_POS  (25U)
+#define GLB_M154_TX_ABORT_DIS_LEN  (1U)
+#define GLB_M154_TX_ABORT_DIS_MSK  (((1U << GLB_M154_TX_ABORT_DIS_LEN) - 1) << GLB_M154_TX_ABORT_DIS_POS)
+#define GLB_M154_TX_ABORT_DIS_UMSK (~(((1U << GLB_M154_TX_ABORT_DIS_LEN) - 1) << GLB_M154_TX_ABORT_DIS_POS))
+#define GLB_BLE_RX_ABORT_DIS       GLB_BLE_RX_ABORT_DIS
+#define GLB_BLE_RX_ABORT_DIS_POS   (26U)
+#define GLB_BLE_RX_ABORT_DIS_LEN   (1U)
+#define GLB_BLE_RX_ABORT_DIS_MSK   (((1U << GLB_BLE_RX_ABORT_DIS_LEN) - 1) << GLB_BLE_RX_ABORT_DIS_POS)
+#define GLB_BLE_RX_ABORT_DIS_UMSK  (~(((1U << GLB_BLE_RX_ABORT_DIS_LEN) - 1) << GLB_BLE_RX_ABORT_DIS_POS))
+#define GLB_BLE_TX_ABORT_DIS       GLB_BLE_TX_ABORT_DIS
+#define GLB_BLE_TX_ABORT_DIS_POS   (27U)
+#define GLB_BLE_TX_ABORT_DIS_LEN   (1U)
+#define GLB_BLE_TX_ABORT_DIS_MSK   (((1U << GLB_BLE_TX_ABORT_DIS_LEN) - 1) << GLB_BLE_TX_ABORT_DIS_POS)
+#define GLB_BLE_TX_ABORT_DIS_UMSK  (~(((1U << GLB_BLE_TX_ABORT_DIS_LEN) - 1) << GLB_BLE_TX_ABORT_DIS_POS))
+#define GLB_COEX_ARB               GLB_COEX_ARB
+#define GLB_COEX_ARB_POS           (28U)
+#define GLB_COEX_ARB_LEN           (4U)
+#define GLB_COEX_ARB_MSK           (((1U << GLB_COEX_ARB_LEN) - 1) << GLB_COEX_ARB_POS)
+#define GLB_COEX_ARB_UMSK          (~(((1U << GLB_COEX_ARB_LEN) - 1) << GLB_COEX_ARB_POS))
+
+/* 0xC0 : UART_SIG_SEL_0 */
+#define GLB_UART_SIG_SEL_0_OFFSET (0xC0)
+#define GLB_UART_SIG_0_SEL        GLB_UART_SIG_0_SEL
+#define GLB_UART_SIG_0_SEL_POS    (0U)
+#define GLB_UART_SIG_0_SEL_LEN    (4U)
+#define GLB_UART_SIG_0_SEL_MSK    (((1U << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS)
+#define GLB_UART_SIG_0_SEL_UMSK   (~(((1U << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS))
+#define GLB_UART_SIG_1_SEL        GLB_UART_SIG_1_SEL
+#define GLB_UART_SIG_1_SEL_POS    (4U)
+#define GLB_UART_SIG_1_SEL_LEN    (4U)
+#define GLB_UART_SIG_1_SEL_MSK    (((1U << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS)
+#define GLB_UART_SIG_1_SEL_UMSK   (~(((1U << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS))
+#define GLB_UART_SIG_2_SEL        GLB_UART_SIG_2_SEL
+#define GLB_UART_SIG_2_SEL_POS    (8U)
+#define GLB_UART_SIG_2_SEL_LEN    (4U)
+#define GLB_UART_SIG_2_SEL_MSK    (((1U << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS)
+#define GLB_UART_SIG_2_SEL_UMSK   (~(((1U << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS))
+#define GLB_UART_SIG_3_SEL        GLB_UART_SIG_3_SEL
+#define GLB_UART_SIG_3_SEL_POS    (12U)
+#define GLB_UART_SIG_3_SEL_LEN    (4U)
+#define GLB_UART_SIG_3_SEL_MSK    (((1U << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS)
+#define GLB_UART_SIG_3_SEL_UMSK   (~(((1U << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS))
+#define GLB_UART_SIG_4_SEL        GLB_UART_SIG_4_SEL
+#define GLB_UART_SIG_4_SEL_POS    (16U)
+#define GLB_UART_SIG_4_SEL_LEN    (4U)
+#define GLB_UART_SIG_4_SEL_MSK    (((1U << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS)
+#define GLB_UART_SIG_4_SEL_UMSK   (~(((1U << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS))
+#define GLB_UART_SIG_5_SEL        GLB_UART_SIG_5_SEL
+#define GLB_UART_SIG_5_SEL_POS    (20U)
+#define GLB_UART_SIG_5_SEL_LEN    (4U)
+#define GLB_UART_SIG_5_SEL_MSK    (((1U << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS)
+#define GLB_UART_SIG_5_SEL_UMSK   (~(((1U << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS))
+#define GLB_UART_SIG_6_SEL        GLB_UART_SIG_6_SEL
+#define GLB_UART_SIG_6_SEL_POS    (24U)
+#define GLB_UART_SIG_6_SEL_LEN    (4U)
+#define GLB_UART_SIG_6_SEL_MSK    (((1U << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS)
+#define GLB_UART_SIG_6_SEL_UMSK   (~(((1U << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS))
+#define GLB_UART_SIG_7_SEL        GLB_UART_SIG_7_SEL
+#define GLB_UART_SIG_7_SEL_POS    (28U)
+#define GLB_UART_SIG_7_SEL_LEN    (4U)
+#define GLB_UART_SIG_7_SEL_MSK    (((1U << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS)
+#define GLB_UART_SIG_7_SEL_UMSK   (~(((1U << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS))
+
+/* 0xD0 : DBG_SEL_LL */
+#define GLB_DBG_SEL_LL_OFFSET    (0xD0)
+#define GLB_REG_DBG_LL_CTRL      GLB_REG_DBG_LL_CTRL
+#define GLB_REG_DBG_LL_CTRL_POS  (0U)
+#define GLB_REG_DBG_LL_CTRL_LEN  (32U)
+#define GLB_REG_DBG_LL_CTRL_MSK  (((1U << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS)
+#define GLB_REG_DBG_LL_CTRL_UMSK (~(((1U << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS))
+
+/* 0xD4 : DBG_SEL_LH */
+#define GLB_DBG_SEL_LH_OFFSET    (0xD4)
+#define GLB_REG_DBG_LH_CTRL      GLB_REG_DBG_LH_CTRL
+#define GLB_REG_DBG_LH_CTRL_POS  (0U)
+#define GLB_REG_DBG_LH_CTRL_LEN  (32U)
+#define GLB_REG_DBG_LH_CTRL_MSK  (((1U << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS)
+#define GLB_REG_DBG_LH_CTRL_UMSK (~(((1U << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS))
+
+/* 0xD8 : DBG_SEL_HL */
+#define GLB_DBG_SEL_HL_OFFSET    (0xD8)
+#define GLB_REG_DBG_HL_CTRL      GLB_REG_DBG_HL_CTRL
+#define GLB_REG_DBG_HL_CTRL_POS  (0U)
+#define GLB_REG_DBG_HL_CTRL_LEN  (32U)
+#define GLB_REG_DBG_HL_CTRL_MSK  (((1U << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS)
+#define GLB_REG_DBG_HL_CTRL_UMSK (~(((1U << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS))
+
+/* 0xDC : DBG_SEL_HH */
+#define GLB_DBG_SEL_HH_OFFSET    (0xDC)
+#define GLB_REG_DBG_HH_CTRL      GLB_REG_DBG_HH_CTRL
+#define GLB_REG_DBG_HH_CTRL_POS  (0U)
+#define GLB_REG_DBG_HH_CTRL_LEN  (32U)
+#define GLB_REG_DBG_HH_CTRL_MSK  (((1U << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS)
+#define GLB_REG_DBG_HH_CTRL_UMSK (~(((1U << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS))
+
+/* 0xE0 : debug */
+#define GLB_DEBUG_OFFSET  (0xE0)
+#define GLB_DEBUG_OE      GLB_DEBUG_OE
+#define GLB_DEBUG_OE_POS  (0U)
+#define GLB_DEBUG_OE_LEN  (1U)
+#define GLB_DEBUG_OE_MSK  (((1U << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS)
+#define GLB_DEBUG_OE_UMSK (~(((1U << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS))
+#define GLB_DEBUG_I       GLB_DEBUG_I
+#define GLB_DEBUG_I_POS   (1U)
+#define GLB_DEBUG_I_LEN   (31U)
+#define GLB_DEBUG_I_MSK   (((1U << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS)
+#define GLB_DEBUG_I_UMSK  (~(((1U << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS))
+
+/* 0x100 : GPIO_CFGCTL0 */
+#define GLB_GPIO_CFGCTL0_OFFSET      (0x100)
+#define GLB_REG_GPIO_0_IE            GLB_REG_GPIO_0_IE
+#define GLB_REG_GPIO_0_IE_POS        (0U)
+#define GLB_REG_GPIO_0_IE_LEN        (1U)
+#define GLB_REG_GPIO_0_IE_MSK        (((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)
+#define GLB_REG_GPIO_0_IE_UMSK       (~(((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS))
+#define GLB_REG_GPIO_0_SMT           GLB_REG_GPIO_0_SMT
+#define GLB_REG_GPIO_0_SMT_POS       (1U)
+#define GLB_REG_GPIO_0_SMT_LEN       (1U)
+#define GLB_REG_GPIO_0_SMT_MSK       (((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)
+#define GLB_REG_GPIO_0_SMT_UMSK      (~(((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS))
+#define GLB_REG_GPIO_0_DRV           GLB_REG_GPIO_0_DRV
+#define GLB_REG_GPIO_0_DRV_POS       (2U)
+#define GLB_REG_GPIO_0_DRV_LEN       (2U)
+#define GLB_REG_GPIO_0_DRV_MSK       (((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)
+#define GLB_REG_GPIO_0_DRV_UMSK      (~(((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS))
+#define GLB_REG_GPIO_0_PU            GLB_REG_GPIO_0_PU
+#define GLB_REG_GPIO_0_PU_POS        (4U)
+#define GLB_REG_GPIO_0_PU_LEN        (1U)
+#define GLB_REG_GPIO_0_PU_MSK        (((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)
+#define GLB_REG_GPIO_0_PU_UMSK       (~(((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS))
+#define GLB_REG_GPIO_0_PD            GLB_REG_GPIO_0_PD
+#define GLB_REG_GPIO_0_PD_POS        (5U)
+#define GLB_REG_GPIO_0_PD_LEN        (1U)
+#define GLB_REG_GPIO_0_PD_MSK        (((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)
+#define GLB_REG_GPIO_0_PD_UMSK       (~(((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS))
+#define GLB_REG_GPIO_0_FUNC_SEL      GLB_REG_GPIO_0_FUNC_SEL
+#define GLB_REG_GPIO_0_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_0_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_0_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)
+#define GLB_REG_GPIO_0_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS))
+#define GLB_REG_GPIO_1_IE            GLB_REG_GPIO_1_IE
+#define GLB_REG_GPIO_1_IE_POS        (16U)
+#define GLB_REG_GPIO_1_IE_LEN        (1U)
+#define GLB_REG_GPIO_1_IE_MSK        (((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)
+#define GLB_REG_GPIO_1_IE_UMSK       (~(((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS))
+#define GLB_REG_GPIO_1_SMT           GLB_REG_GPIO_1_SMT
+#define GLB_REG_GPIO_1_SMT_POS       (17U)
+#define GLB_REG_GPIO_1_SMT_LEN       (1U)
+#define GLB_REG_GPIO_1_SMT_MSK       (((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)
+#define GLB_REG_GPIO_1_SMT_UMSK      (~(((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS))
+#define GLB_REG_GPIO_1_DRV           GLB_REG_GPIO_1_DRV
+#define GLB_REG_GPIO_1_DRV_POS       (18U)
+#define GLB_REG_GPIO_1_DRV_LEN       (2U)
+#define GLB_REG_GPIO_1_DRV_MSK       (((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)
+#define GLB_REG_GPIO_1_DRV_UMSK      (~(((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS))
+#define GLB_REG_GPIO_1_PU            GLB_REG_GPIO_1_PU
+#define GLB_REG_GPIO_1_PU_POS        (20U)
+#define GLB_REG_GPIO_1_PU_LEN        (1U)
+#define GLB_REG_GPIO_1_PU_MSK        (((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)
+#define GLB_REG_GPIO_1_PU_UMSK       (~(((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS))
+#define GLB_REG_GPIO_1_PD            GLB_REG_GPIO_1_PD
+#define GLB_REG_GPIO_1_PD_POS        (21U)
+#define GLB_REG_GPIO_1_PD_LEN        (1U)
+#define GLB_REG_GPIO_1_PD_MSK        (((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)
+#define GLB_REG_GPIO_1_PD_UMSK       (~(((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS))
+#define GLB_REG_GPIO_1_FUNC_SEL      GLB_REG_GPIO_1_FUNC_SEL
+#define GLB_REG_GPIO_1_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_1_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_1_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)
+#define GLB_REG_GPIO_1_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS))
+
+/* 0x104 : GPIO_CFGCTL1 */
+#define GLB_GPIO_CFGCTL1_OFFSET      (0x104)
+#define GLB_REG_GPIO_2_IE            GLB_REG_GPIO_2_IE
+#define GLB_REG_GPIO_2_IE_POS        (0U)
+#define GLB_REG_GPIO_2_IE_LEN        (1U)
+#define GLB_REG_GPIO_2_IE_MSK        (((1U << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS)
+#define GLB_REG_GPIO_2_IE_UMSK       (~(((1U << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS))
+#define GLB_REG_GPIO_2_SMT           GLB_REG_GPIO_2_SMT
+#define GLB_REG_GPIO_2_SMT_POS       (1U)
+#define GLB_REG_GPIO_2_SMT_LEN       (1U)
+#define GLB_REG_GPIO_2_SMT_MSK       (((1U << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS)
+#define GLB_REG_GPIO_2_SMT_UMSK      (~(((1U << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS))
+#define GLB_REG_GPIO_2_DRV           GLB_REG_GPIO_2_DRV
+#define GLB_REG_GPIO_2_DRV_POS       (2U)
+#define GLB_REG_GPIO_2_DRV_LEN       (2U)
+#define GLB_REG_GPIO_2_DRV_MSK       (((1U << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS)
+#define GLB_REG_GPIO_2_DRV_UMSK      (~(((1U << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS))
+#define GLB_REG_GPIO_2_PU            GLB_REG_GPIO_2_PU
+#define GLB_REG_GPIO_2_PU_POS        (4U)
+#define GLB_REG_GPIO_2_PU_LEN        (1U)
+#define GLB_REG_GPIO_2_PU_MSK        (((1U << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS)
+#define GLB_REG_GPIO_2_PU_UMSK       (~(((1U << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS))
+#define GLB_REG_GPIO_2_PD            GLB_REG_GPIO_2_PD
+#define GLB_REG_GPIO_2_PD_POS        (5U)
+#define GLB_REG_GPIO_2_PD_LEN        (1U)
+#define GLB_REG_GPIO_2_PD_MSK        (((1U << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS)
+#define GLB_REG_GPIO_2_PD_UMSK       (~(((1U << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS))
+#define GLB_REG_GPIO_2_FUNC_SEL      GLB_REG_GPIO_2_FUNC_SEL
+#define GLB_REG_GPIO_2_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_2_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_2_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS)
+#define GLB_REG_GPIO_2_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS))
+#define GLB_REG_GPIO_3_IE            GLB_REG_GPIO_3_IE
+#define GLB_REG_GPIO_3_IE_POS        (16U)
+#define GLB_REG_GPIO_3_IE_LEN        (1U)
+#define GLB_REG_GPIO_3_IE_MSK        (((1U << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS)
+#define GLB_REG_GPIO_3_IE_UMSK       (~(((1U << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS))
+#define GLB_REG_GPIO_3_SMT           GLB_REG_GPIO_3_SMT
+#define GLB_REG_GPIO_3_SMT_POS       (17U)
+#define GLB_REG_GPIO_3_SMT_LEN       (1U)
+#define GLB_REG_GPIO_3_SMT_MSK       (((1U << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS)
+#define GLB_REG_GPIO_3_SMT_UMSK      (~(((1U << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS))
+#define GLB_REG_GPIO_3_DRV           GLB_REG_GPIO_3_DRV
+#define GLB_REG_GPIO_3_DRV_POS       (18U)
+#define GLB_REG_GPIO_3_DRV_LEN       (2U)
+#define GLB_REG_GPIO_3_DRV_MSK       (((1U << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS)
+#define GLB_REG_GPIO_3_DRV_UMSK      (~(((1U << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS))
+#define GLB_REG_GPIO_3_PU            GLB_REG_GPIO_3_PU
+#define GLB_REG_GPIO_3_PU_POS        (20U)
+#define GLB_REG_GPIO_3_PU_LEN        (1U)
+#define GLB_REG_GPIO_3_PU_MSK        (((1U << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS)
+#define GLB_REG_GPIO_3_PU_UMSK       (~(((1U << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS))
+#define GLB_REG_GPIO_3_PD            GLB_REG_GPIO_3_PD
+#define GLB_REG_GPIO_3_PD_POS        (21U)
+#define GLB_REG_GPIO_3_PD_LEN        (1U)
+#define GLB_REG_GPIO_3_PD_MSK        (((1U << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS)
+#define GLB_REG_GPIO_3_PD_UMSK       (~(((1U << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS))
+#define GLB_REG_GPIO_3_FUNC_SEL      GLB_REG_GPIO_3_FUNC_SEL
+#define GLB_REG_GPIO_3_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_3_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_3_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS)
+#define GLB_REG_GPIO_3_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS))
+
+/* 0x108 : GPIO_CFGCTL2 */
+#define GLB_GPIO_CFGCTL2_OFFSET      (0x108)
+#define GLB_REG_GPIO_4_IE            GLB_REG_GPIO_4_IE
+#define GLB_REG_GPIO_4_IE_POS        (0U)
+#define GLB_REG_GPIO_4_IE_LEN        (1U)
+#define GLB_REG_GPIO_4_IE_MSK        (((1U << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS)
+#define GLB_REG_GPIO_4_IE_UMSK       (~(((1U << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS))
+#define GLB_REG_GPIO_4_SMT           GLB_REG_GPIO_4_SMT
+#define GLB_REG_GPIO_4_SMT_POS       (1U)
+#define GLB_REG_GPIO_4_SMT_LEN       (1U)
+#define GLB_REG_GPIO_4_SMT_MSK       (((1U << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS)
+#define GLB_REG_GPIO_4_SMT_UMSK      (~(((1U << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS))
+#define GLB_REG_GPIO_4_DRV           GLB_REG_GPIO_4_DRV
+#define GLB_REG_GPIO_4_DRV_POS       (2U)
+#define GLB_REG_GPIO_4_DRV_LEN       (2U)
+#define GLB_REG_GPIO_4_DRV_MSK       (((1U << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS)
+#define GLB_REG_GPIO_4_DRV_UMSK      (~(((1U << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS))
+#define GLB_REG_GPIO_4_PU            GLB_REG_GPIO_4_PU
+#define GLB_REG_GPIO_4_PU_POS        (4U)
+#define GLB_REG_GPIO_4_PU_LEN        (1U)
+#define GLB_REG_GPIO_4_PU_MSK        (((1U << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS)
+#define GLB_REG_GPIO_4_PU_UMSK       (~(((1U << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS))
+#define GLB_REG_GPIO_4_PD            GLB_REG_GPIO_4_PD
+#define GLB_REG_GPIO_4_PD_POS        (5U)
+#define GLB_REG_GPIO_4_PD_LEN        (1U)
+#define GLB_REG_GPIO_4_PD_MSK        (((1U << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS)
+#define GLB_REG_GPIO_4_PD_UMSK       (~(((1U << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS))
+#define GLB_REG_GPIO_4_FUNC_SEL      GLB_REG_GPIO_4_FUNC_SEL
+#define GLB_REG_GPIO_4_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_4_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_4_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS)
+#define GLB_REG_GPIO_4_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS))
+#define GLB_REG_GPIO_5_IE            GLB_REG_GPIO_5_IE
+#define GLB_REG_GPIO_5_IE_POS        (16U)
+#define GLB_REG_GPIO_5_IE_LEN        (1U)
+#define GLB_REG_GPIO_5_IE_MSK        (((1U << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS)
+#define GLB_REG_GPIO_5_IE_UMSK       (~(((1U << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS))
+#define GLB_REG_GPIO_5_SMT           GLB_REG_GPIO_5_SMT
+#define GLB_REG_GPIO_5_SMT_POS       (17U)
+#define GLB_REG_GPIO_5_SMT_LEN       (1U)
+#define GLB_REG_GPIO_5_SMT_MSK       (((1U << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS)
+#define GLB_REG_GPIO_5_SMT_UMSK      (~(((1U << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS))
+#define GLB_REG_GPIO_5_DRV           GLB_REG_GPIO_5_DRV
+#define GLB_REG_GPIO_5_DRV_POS       (18U)
+#define GLB_REG_GPIO_5_DRV_LEN       (2U)
+#define GLB_REG_GPIO_5_DRV_MSK       (((1U << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS)
+#define GLB_REG_GPIO_5_DRV_UMSK      (~(((1U << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS))
+#define GLB_REG_GPIO_5_PU            GLB_REG_GPIO_5_PU
+#define GLB_REG_GPIO_5_PU_POS        (20U)
+#define GLB_REG_GPIO_5_PU_LEN        (1U)
+#define GLB_REG_GPIO_5_PU_MSK        (((1U << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS)
+#define GLB_REG_GPIO_5_PU_UMSK       (~(((1U << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS))
+#define GLB_REG_GPIO_5_PD            GLB_REG_GPIO_5_PD
+#define GLB_REG_GPIO_5_PD_POS        (21U)
+#define GLB_REG_GPIO_5_PD_LEN        (1U)
+#define GLB_REG_GPIO_5_PD_MSK        (((1U << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS)
+#define GLB_REG_GPIO_5_PD_UMSK       (~(((1U << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS))
+#define GLB_REG_GPIO_5_FUNC_SEL      GLB_REG_GPIO_5_FUNC_SEL
+#define GLB_REG_GPIO_5_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_5_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_5_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS)
+#define GLB_REG_GPIO_5_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS))
+
+/* 0x10C : GPIO_CFGCTL3 */
+#define GLB_GPIO_CFGCTL3_OFFSET      (0x10C)
+#define GLB_REG_GPIO_6_IE            GLB_REG_GPIO_6_IE
+#define GLB_REG_GPIO_6_IE_POS        (0U)
+#define GLB_REG_GPIO_6_IE_LEN        (1U)
+#define GLB_REG_GPIO_6_IE_MSK        (((1U << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS)
+#define GLB_REG_GPIO_6_IE_UMSK       (~(((1U << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS))
+#define GLB_REG_GPIO_6_SMT           GLB_REG_GPIO_6_SMT
+#define GLB_REG_GPIO_6_SMT_POS       (1U)
+#define GLB_REG_GPIO_6_SMT_LEN       (1U)
+#define GLB_REG_GPIO_6_SMT_MSK       (((1U << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS)
+#define GLB_REG_GPIO_6_SMT_UMSK      (~(((1U << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS))
+#define GLB_REG_GPIO_6_DRV           GLB_REG_GPIO_6_DRV
+#define GLB_REG_GPIO_6_DRV_POS       (2U)
+#define GLB_REG_GPIO_6_DRV_LEN       (2U)
+#define GLB_REG_GPIO_6_DRV_MSK       (((1U << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS)
+#define GLB_REG_GPIO_6_DRV_UMSK      (~(((1U << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS))
+#define GLB_REG_GPIO_6_PU            GLB_REG_GPIO_6_PU
+#define GLB_REG_GPIO_6_PU_POS        (4U)
+#define GLB_REG_GPIO_6_PU_LEN        (1U)
+#define GLB_REG_GPIO_6_PU_MSK        (((1U << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS)
+#define GLB_REG_GPIO_6_PU_UMSK       (~(((1U << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS))
+#define GLB_REG_GPIO_6_PD            GLB_REG_GPIO_6_PD
+#define GLB_REG_GPIO_6_PD_POS        (5U)
+#define GLB_REG_GPIO_6_PD_LEN        (1U)
+#define GLB_REG_GPIO_6_PD_MSK        (((1U << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS)
+#define GLB_REG_GPIO_6_PD_UMSK       (~(((1U << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS))
+#define GLB_REG_GPIO_6_FUNC_SEL      GLB_REG_GPIO_6_FUNC_SEL
+#define GLB_REG_GPIO_6_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_6_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_6_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS)
+#define GLB_REG_GPIO_6_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS))
+#define GLB_REG_GPIO_7_IE            GLB_REG_GPIO_7_IE
+#define GLB_REG_GPIO_7_IE_POS        (16U)
+#define GLB_REG_GPIO_7_IE_LEN        (1U)
+#define GLB_REG_GPIO_7_IE_MSK        (((1U << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS)
+#define GLB_REG_GPIO_7_IE_UMSK       (~(((1U << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS))
+#define GLB_REG_GPIO_7_SMT           GLB_REG_GPIO_7_SMT
+#define GLB_REG_GPIO_7_SMT_POS       (17U)
+#define GLB_REG_GPIO_7_SMT_LEN       (1U)
+#define GLB_REG_GPIO_7_SMT_MSK       (((1U << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS)
+#define GLB_REG_GPIO_7_SMT_UMSK      (~(((1U << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS))
+#define GLB_REG_GPIO_7_DRV           GLB_REG_GPIO_7_DRV
+#define GLB_REG_GPIO_7_DRV_POS       (18U)
+#define GLB_REG_GPIO_7_DRV_LEN       (2U)
+#define GLB_REG_GPIO_7_DRV_MSK       (((1U << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS)
+#define GLB_REG_GPIO_7_DRV_UMSK      (~(((1U << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS))
+#define GLB_REG_GPIO_7_PU            GLB_REG_GPIO_7_PU
+#define GLB_REG_GPIO_7_PU_POS        (20U)
+#define GLB_REG_GPIO_7_PU_LEN        (1U)
+#define GLB_REG_GPIO_7_PU_MSK        (((1U << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS)
+#define GLB_REG_GPIO_7_PU_UMSK       (~(((1U << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS))
+#define GLB_REG_GPIO_7_PD            GLB_REG_GPIO_7_PD
+#define GLB_REG_GPIO_7_PD_POS        (21U)
+#define GLB_REG_GPIO_7_PD_LEN        (1U)
+#define GLB_REG_GPIO_7_PD_MSK        (((1U << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS)
+#define GLB_REG_GPIO_7_PD_UMSK       (~(((1U << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS))
+#define GLB_REG_GPIO_7_FUNC_SEL      GLB_REG_GPIO_7_FUNC_SEL
+#define GLB_REG_GPIO_7_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_7_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_7_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS)
+#define GLB_REG_GPIO_7_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS))
+
+/* 0x110 : GPIO_CFGCTL4 */
+#define GLB_GPIO_CFGCTL4_OFFSET      (0x110)
+#define GLB_REG_GPIO_8_IE            GLB_REG_GPIO_8_IE
+#define GLB_REG_GPIO_8_IE_POS        (0U)
+#define GLB_REG_GPIO_8_IE_LEN        (1U)
+#define GLB_REG_GPIO_8_IE_MSK        (((1U << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS)
+#define GLB_REG_GPIO_8_IE_UMSK       (~(((1U << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS))
+#define GLB_REG_GPIO_8_SMT           GLB_REG_GPIO_8_SMT
+#define GLB_REG_GPIO_8_SMT_POS       (1U)
+#define GLB_REG_GPIO_8_SMT_LEN       (1U)
+#define GLB_REG_GPIO_8_SMT_MSK       (((1U << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS)
+#define GLB_REG_GPIO_8_SMT_UMSK      (~(((1U << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS))
+#define GLB_REG_GPIO_8_DRV           GLB_REG_GPIO_8_DRV
+#define GLB_REG_GPIO_8_DRV_POS       (2U)
+#define GLB_REG_GPIO_8_DRV_LEN       (2U)
+#define GLB_REG_GPIO_8_DRV_MSK       (((1U << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS)
+#define GLB_REG_GPIO_8_DRV_UMSK      (~(((1U << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS))
+#define GLB_REG_GPIO_8_PU            GLB_REG_GPIO_8_PU
+#define GLB_REG_GPIO_8_PU_POS        (4U)
+#define GLB_REG_GPIO_8_PU_LEN        (1U)
+#define GLB_REG_GPIO_8_PU_MSK        (((1U << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS)
+#define GLB_REG_GPIO_8_PU_UMSK       (~(((1U << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS))
+#define GLB_REG_GPIO_8_PD            GLB_REG_GPIO_8_PD
+#define GLB_REG_GPIO_8_PD_POS        (5U)
+#define GLB_REG_GPIO_8_PD_LEN        (1U)
+#define GLB_REG_GPIO_8_PD_MSK        (((1U << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS)
+#define GLB_REG_GPIO_8_PD_UMSK       (~(((1U << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS))
+#define GLB_REG_GPIO_8_FUNC_SEL      GLB_REG_GPIO_8_FUNC_SEL
+#define GLB_REG_GPIO_8_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_8_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_8_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS)
+#define GLB_REG_GPIO_8_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS))
+#define GLB_REG_GPIO_9_IE            GLB_REG_GPIO_9_IE
+#define GLB_REG_GPIO_9_IE_POS        (16U)
+#define GLB_REG_GPIO_9_IE_LEN        (1U)
+#define GLB_REG_GPIO_9_IE_MSK        (((1U << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS)
+#define GLB_REG_GPIO_9_IE_UMSK       (~(((1U << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS))
+#define GLB_REG_GPIO_9_SMT           GLB_REG_GPIO_9_SMT
+#define GLB_REG_GPIO_9_SMT_POS       (17U)
+#define GLB_REG_GPIO_9_SMT_LEN       (1U)
+#define GLB_REG_GPIO_9_SMT_MSK       (((1U << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS)
+#define GLB_REG_GPIO_9_SMT_UMSK      (~(((1U << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS))
+#define GLB_REG_GPIO_9_DRV           GLB_REG_GPIO_9_DRV
+#define GLB_REG_GPIO_9_DRV_POS       (18U)
+#define GLB_REG_GPIO_9_DRV_LEN       (2U)
+#define GLB_REG_GPIO_9_DRV_MSK       (((1U << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS)
+#define GLB_REG_GPIO_9_DRV_UMSK      (~(((1U << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS))
+#define GLB_REG_GPIO_9_PU            GLB_REG_GPIO_9_PU
+#define GLB_REG_GPIO_9_PU_POS        (20U)
+#define GLB_REG_GPIO_9_PU_LEN        (1U)
+#define GLB_REG_GPIO_9_PU_MSK        (((1U << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS)
+#define GLB_REG_GPIO_9_PU_UMSK       (~(((1U << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS))
+#define GLB_REG_GPIO_9_PD            GLB_REG_GPIO_9_PD
+#define GLB_REG_GPIO_9_PD_POS        (21U)
+#define GLB_REG_GPIO_9_PD_LEN        (1U)
+#define GLB_REG_GPIO_9_PD_MSK        (((1U << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS)
+#define GLB_REG_GPIO_9_PD_UMSK       (~(((1U << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS))
+#define GLB_REG_GPIO_9_FUNC_SEL      GLB_REG_GPIO_9_FUNC_SEL
+#define GLB_REG_GPIO_9_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_9_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_9_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS)
+#define GLB_REG_GPIO_9_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS))
+
+/* 0x114 : GPIO_CFGCTL5 */
+#define GLB_GPIO_CFGCTL5_OFFSET       (0x114)
+#define GLB_REG_GPIO_10_IE            GLB_REG_GPIO_10_IE
+#define GLB_REG_GPIO_10_IE_POS        (0U)
+#define GLB_REG_GPIO_10_IE_LEN        (1U)
+#define GLB_REG_GPIO_10_IE_MSK        (((1U << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS)
+#define GLB_REG_GPIO_10_IE_UMSK       (~(((1U << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS))
+#define GLB_REG_GPIO_10_SMT           GLB_REG_GPIO_10_SMT
+#define GLB_REG_GPIO_10_SMT_POS       (1U)
+#define GLB_REG_GPIO_10_SMT_LEN       (1U)
+#define GLB_REG_GPIO_10_SMT_MSK       (((1U << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS)
+#define GLB_REG_GPIO_10_SMT_UMSK      (~(((1U << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS))
+#define GLB_REG_GPIO_10_DRV           GLB_REG_GPIO_10_DRV
+#define GLB_REG_GPIO_10_DRV_POS       (2U)
+#define GLB_REG_GPIO_10_DRV_LEN       (2U)
+#define GLB_REG_GPIO_10_DRV_MSK       (((1U << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS)
+#define GLB_REG_GPIO_10_DRV_UMSK      (~(((1U << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS))
+#define GLB_REG_GPIO_10_PU            GLB_REG_GPIO_10_PU
+#define GLB_REG_GPIO_10_PU_POS        (4U)
+#define GLB_REG_GPIO_10_PU_LEN        (1U)
+#define GLB_REG_GPIO_10_PU_MSK        (((1U << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS)
+#define GLB_REG_GPIO_10_PU_UMSK       (~(((1U << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS))
+#define GLB_REG_GPIO_10_PD            GLB_REG_GPIO_10_PD
+#define GLB_REG_GPIO_10_PD_POS        (5U)
+#define GLB_REG_GPIO_10_PD_LEN        (1U)
+#define GLB_REG_GPIO_10_PD_MSK        (((1U << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS)
+#define GLB_REG_GPIO_10_PD_UMSK       (~(((1U << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS))
+#define GLB_REG_GPIO_10_FUNC_SEL      GLB_REG_GPIO_10_FUNC_SEL
+#define GLB_REG_GPIO_10_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_10_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_10_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_10_FUNC_SEL_POS)
+#define GLB_REG_GPIO_10_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_10_FUNC_SEL_POS))
+#define GLB_REG_GPIO_11_IE            GLB_REG_GPIO_11_IE
+#define GLB_REG_GPIO_11_IE_POS        (16U)
+#define GLB_REG_GPIO_11_IE_LEN        (1U)
+#define GLB_REG_GPIO_11_IE_MSK        (((1U << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS)
+#define GLB_REG_GPIO_11_IE_UMSK       (~(((1U << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS))
+#define GLB_REG_GPIO_11_SMT           GLB_REG_GPIO_11_SMT
+#define GLB_REG_GPIO_11_SMT_POS       (17U)
+#define GLB_REG_GPIO_11_SMT_LEN       (1U)
+#define GLB_REG_GPIO_11_SMT_MSK       (((1U << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS)
+#define GLB_REG_GPIO_11_SMT_UMSK      (~(((1U << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS))
+#define GLB_REG_GPIO_11_DRV           GLB_REG_GPIO_11_DRV
+#define GLB_REG_GPIO_11_DRV_POS       (18U)
+#define GLB_REG_GPIO_11_DRV_LEN       (2U)
+#define GLB_REG_GPIO_11_DRV_MSK       (((1U << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS)
+#define GLB_REG_GPIO_11_DRV_UMSK      (~(((1U << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS))
+#define GLB_REG_GPIO_11_PU            GLB_REG_GPIO_11_PU
+#define GLB_REG_GPIO_11_PU_POS        (20U)
+#define GLB_REG_GPIO_11_PU_LEN        (1U)
+#define GLB_REG_GPIO_11_PU_MSK        (((1U << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS)
+#define GLB_REG_GPIO_11_PU_UMSK       (~(((1U << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS))
+#define GLB_REG_GPIO_11_PD            GLB_REG_GPIO_11_PD
+#define GLB_REG_GPIO_11_PD_POS        (21U)
+#define GLB_REG_GPIO_11_PD_LEN        (1U)
+#define GLB_REG_GPIO_11_PD_MSK        (((1U << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS)
+#define GLB_REG_GPIO_11_PD_UMSK       (~(((1U << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS))
+#define GLB_REG_GPIO_11_FUNC_SEL      GLB_REG_GPIO_11_FUNC_SEL
+#define GLB_REG_GPIO_11_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_11_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_11_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_11_FUNC_SEL_POS)
+#define GLB_REG_GPIO_11_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_11_FUNC_SEL_POS))
+
+/* 0x118 : GPIO_CFGCTL6 */
+#define GLB_GPIO_CFGCTL6_OFFSET       (0x118)
+#define GLB_REG_GPIO_12_IE            GLB_REG_GPIO_12_IE
+#define GLB_REG_GPIO_12_IE_POS        (0U)
+#define GLB_REG_GPIO_12_IE_LEN        (1U)
+#define GLB_REG_GPIO_12_IE_MSK        (((1U << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS)
+#define GLB_REG_GPIO_12_IE_UMSK       (~(((1U << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS))
+#define GLB_REG_GPIO_12_SMT           GLB_REG_GPIO_12_SMT
+#define GLB_REG_GPIO_12_SMT_POS       (1U)
+#define GLB_REG_GPIO_12_SMT_LEN       (1U)
+#define GLB_REG_GPIO_12_SMT_MSK       (((1U << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS)
+#define GLB_REG_GPIO_12_SMT_UMSK      (~(((1U << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS))
+#define GLB_REG_GPIO_12_DRV           GLB_REG_GPIO_12_DRV
+#define GLB_REG_GPIO_12_DRV_POS       (2U)
+#define GLB_REG_GPIO_12_DRV_LEN       (2U)
+#define GLB_REG_GPIO_12_DRV_MSK       (((1U << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS)
+#define GLB_REG_GPIO_12_DRV_UMSK      (~(((1U << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS))
+#define GLB_REG_GPIO_12_PU            GLB_REG_GPIO_12_PU
+#define GLB_REG_GPIO_12_PU_POS        (4U)
+#define GLB_REG_GPIO_12_PU_LEN        (1U)
+#define GLB_REG_GPIO_12_PU_MSK        (((1U << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS)
+#define GLB_REG_GPIO_12_PU_UMSK       (~(((1U << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS))
+#define GLB_REG_GPIO_12_PD            GLB_REG_GPIO_12_PD
+#define GLB_REG_GPIO_12_PD_POS        (5U)
+#define GLB_REG_GPIO_12_PD_LEN        (1U)
+#define GLB_REG_GPIO_12_PD_MSK        (((1U << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS)
+#define GLB_REG_GPIO_12_PD_UMSK       (~(((1U << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS))
+#define GLB_REG_GPIO_12_FUNC_SEL      GLB_REG_GPIO_12_FUNC_SEL
+#define GLB_REG_GPIO_12_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_12_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_12_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_12_FUNC_SEL_POS)
+#define GLB_REG_GPIO_12_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_12_FUNC_SEL_POS))
+#define GLB_REG_GPIO_13_IE            GLB_REG_GPIO_13_IE
+#define GLB_REG_GPIO_13_IE_POS        (16U)
+#define GLB_REG_GPIO_13_IE_LEN        (1U)
+#define GLB_REG_GPIO_13_IE_MSK        (((1U << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS)
+#define GLB_REG_GPIO_13_IE_UMSK       (~(((1U << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS))
+#define GLB_REG_GPIO_13_SMT           GLB_REG_GPIO_13_SMT
+#define GLB_REG_GPIO_13_SMT_POS       (17U)
+#define GLB_REG_GPIO_13_SMT_LEN       (1U)
+#define GLB_REG_GPIO_13_SMT_MSK       (((1U << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS)
+#define GLB_REG_GPIO_13_SMT_UMSK      (~(((1U << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS))
+#define GLB_REG_GPIO_13_DRV           GLB_REG_GPIO_13_DRV
+#define GLB_REG_GPIO_13_DRV_POS       (18U)
+#define GLB_REG_GPIO_13_DRV_LEN       (2U)
+#define GLB_REG_GPIO_13_DRV_MSK       (((1U << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS)
+#define GLB_REG_GPIO_13_DRV_UMSK      (~(((1U << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS))
+#define GLB_REG_GPIO_13_PU            GLB_REG_GPIO_13_PU
+#define GLB_REG_GPIO_13_PU_POS        (20U)
+#define GLB_REG_GPIO_13_PU_LEN        (1U)
+#define GLB_REG_GPIO_13_PU_MSK        (((1U << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS)
+#define GLB_REG_GPIO_13_PU_UMSK       (~(((1U << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS))
+#define GLB_REG_GPIO_13_PD            GLB_REG_GPIO_13_PD
+#define GLB_REG_GPIO_13_PD_POS        (21U)
+#define GLB_REG_GPIO_13_PD_LEN        (1U)
+#define GLB_REG_GPIO_13_PD_MSK        (((1U << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS)
+#define GLB_REG_GPIO_13_PD_UMSK       (~(((1U << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS))
+#define GLB_REG_GPIO_13_FUNC_SEL      GLB_REG_GPIO_13_FUNC_SEL
+#define GLB_REG_GPIO_13_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_13_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_13_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_13_FUNC_SEL_POS)
+#define GLB_REG_GPIO_13_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_13_FUNC_SEL_POS))
+
+/* 0x11C : GPIO_CFGCTL7 */
+#define GLB_GPIO_CFGCTL7_OFFSET       (0x11C)
+#define GLB_REG_GPIO_14_IE            GLB_REG_GPIO_14_IE
+#define GLB_REG_GPIO_14_IE_POS        (0U)
+#define GLB_REG_GPIO_14_IE_LEN        (1U)
+#define GLB_REG_GPIO_14_IE_MSK        (((1U << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS)
+#define GLB_REG_GPIO_14_IE_UMSK       (~(((1U << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS))
+#define GLB_REG_GPIO_14_SMT           GLB_REG_GPIO_14_SMT
+#define GLB_REG_GPIO_14_SMT_POS       (1U)
+#define GLB_REG_GPIO_14_SMT_LEN       (1U)
+#define GLB_REG_GPIO_14_SMT_MSK       (((1U << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS)
+#define GLB_REG_GPIO_14_SMT_UMSK      (~(((1U << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS))
+#define GLB_REG_GPIO_14_DRV           GLB_REG_GPIO_14_DRV
+#define GLB_REG_GPIO_14_DRV_POS       (2U)
+#define GLB_REG_GPIO_14_DRV_LEN       (2U)
+#define GLB_REG_GPIO_14_DRV_MSK       (((1U << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS)
+#define GLB_REG_GPIO_14_DRV_UMSK      (~(((1U << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS))
+#define GLB_REG_GPIO_14_PU            GLB_REG_GPIO_14_PU
+#define GLB_REG_GPIO_14_PU_POS        (4U)
+#define GLB_REG_GPIO_14_PU_LEN        (1U)
+#define GLB_REG_GPIO_14_PU_MSK        (((1U << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS)
+#define GLB_REG_GPIO_14_PU_UMSK       (~(((1U << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS))
+#define GLB_REG_GPIO_14_PD            GLB_REG_GPIO_14_PD
+#define GLB_REG_GPIO_14_PD_POS        (5U)
+#define GLB_REG_GPIO_14_PD_LEN        (1U)
+#define GLB_REG_GPIO_14_PD_MSK        (((1U << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS)
+#define GLB_REG_GPIO_14_PD_UMSK       (~(((1U << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS))
+#define GLB_REG_GPIO_14_FUNC_SEL      GLB_REG_GPIO_14_FUNC_SEL
+#define GLB_REG_GPIO_14_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_14_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_14_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_14_FUNC_SEL_POS)
+#define GLB_REG_GPIO_14_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_14_FUNC_SEL_POS))
+#define GLB_REG_GPIO_15_IE            GLB_REG_GPIO_15_IE
+#define GLB_REG_GPIO_15_IE_POS        (16U)
+#define GLB_REG_GPIO_15_IE_LEN        (1U)
+#define GLB_REG_GPIO_15_IE_MSK        (((1U << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS)
+#define GLB_REG_GPIO_15_IE_UMSK       (~(((1U << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS))
+#define GLB_REG_GPIO_15_SMT           GLB_REG_GPIO_15_SMT
+#define GLB_REG_GPIO_15_SMT_POS       (17U)
+#define GLB_REG_GPIO_15_SMT_LEN       (1U)
+#define GLB_REG_GPIO_15_SMT_MSK       (((1U << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS)
+#define GLB_REG_GPIO_15_SMT_UMSK      (~(((1U << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS))
+#define GLB_REG_GPIO_15_DRV           GLB_REG_GPIO_15_DRV
+#define GLB_REG_GPIO_15_DRV_POS       (18U)
+#define GLB_REG_GPIO_15_DRV_LEN       (2U)
+#define GLB_REG_GPIO_15_DRV_MSK       (((1U << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS)
+#define GLB_REG_GPIO_15_DRV_UMSK      (~(((1U << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS))
+#define GLB_REG_GPIO_15_PU            GLB_REG_GPIO_15_PU
+#define GLB_REG_GPIO_15_PU_POS        (20U)
+#define GLB_REG_GPIO_15_PU_LEN        (1U)
+#define GLB_REG_GPIO_15_PU_MSK        (((1U << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS)
+#define GLB_REG_GPIO_15_PU_UMSK       (~(((1U << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS))
+#define GLB_REG_GPIO_15_PD            GLB_REG_GPIO_15_PD
+#define GLB_REG_GPIO_15_PD_POS        (21U)
+#define GLB_REG_GPIO_15_PD_LEN        (1U)
+#define GLB_REG_GPIO_15_PD_MSK        (((1U << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS)
+#define GLB_REG_GPIO_15_PD_UMSK       (~(((1U << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS))
+#define GLB_REG_GPIO_15_FUNC_SEL      GLB_REG_GPIO_15_FUNC_SEL
+#define GLB_REG_GPIO_15_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_15_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_15_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_15_FUNC_SEL_POS)
+#define GLB_REG_GPIO_15_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_15_FUNC_SEL_POS))
+
+/* 0x120 : GPIO_CFGCTL8 */
+#define GLB_GPIO_CFGCTL8_OFFSET       (0x120)
+#define GLB_REG_GPIO_16_IE            GLB_REG_GPIO_16_IE
+#define GLB_REG_GPIO_16_IE_POS        (0U)
+#define GLB_REG_GPIO_16_IE_LEN        (1U)
+#define GLB_REG_GPIO_16_IE_MSK        (((1U << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS)
+#define GLB_REG_GPIO_16_IE_UMSK       (~(((1U << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS))
+#define GLB_REG_GPIO_16_SMT           GLB_REG_GPIO_16_SMT
+#define GLB_REG_GPIO_16_SMT_POS       (1U)
+#define GLB_REG_GPIO_16_SMT_LEN       (1U)
+#define GLB_REG_GPIO_16_SMT_MSK       (((1U << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS)
+#define GLB_REG_GPIO_16_SMT_UMSK      (~(((1U << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS))
+#define GLB_REG_GPIO_16_DRV           GLB_REG_GPIO_16_DRV
+#define GLB_REG_GPIO_16_DRV_POS       (2U)
+#define GLB_REG_GPIO_16_DRV_LEN       (2U)
+#define GLB_REG_GPIO_16_DRV_MSK       (((1U << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS)
+#define GLB_REG_GPIO_16_DRV_UMSK      (~(((1U << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS))
+#define GLB_REG_GPIO_16_PU            GLB_REG_GPIO_16_PU
+#define GLB_REG_GPIO_16_PU_POS        (4U)
+#define GLB_REG_GPIO_16_PU_LEN        (1U)
+#define GLB_REG_GPIO_16_PU_MSK        (((1U << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS)
+#define GLB_REG_GPIO_16_PU_UMSK       (~(((1U << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS))
+#define GLB_REG_GPIO_16_PD            GLB_REG_GPIO_16_PD
+#define GLB_REG_GPIO_16_PD_POS        (5U)
+#define GLB_REG_GPIO_16_PD_LEN        (1U)
+#define GLB_REG_GPIO_16_PD_MSK        (((1U << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS)
+#define GLB_REG_GPIO_16_PD_UMSK       (~(((1U << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS))
+#define GLB_REG_GPIO_16_FUNC_SEL      GLB_REG_GPIO_16_FUNC_SEL
+#define GLB_REG_GPIO_16_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_16_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_16_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_16_FUNC_SEL_POS)
+#define GLB_REG_GPIO_16_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_16_FUNC_SEL_POS))
+#define GLB_REG_GPIO_17_IE            GLB_REG_GPIO_17_IE
+#define GLB_REG_GPIO_17_IE_POS        (16U)
+#define GLB_REG_GPIO_17_IE_LEN        (1U)
+#define GLB_REG_GPIO_17_IE_MSK        (((1U << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS)
+#define GLB_REG_GPIO_17_IE_UMSK       (~(((1U << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS))
+#define GLB_REG_GPIO_17_SMT           GLB_REG_GPIO_17_SMT
+#define GLB_REG_GPIO_17_SMT_POS       (17U)
+#define GLB_REG_GPIO_17_SMT_LEN       (1U)
+#define GLB_REG_GPIO_17_SMT_MSK       (((1U << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS)
+#define GLB_REG_GPIO_17_SMT_UMSK      (~(((1U << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS))
+#define GLB_REG_GPIO_17_DRV           GLB_REG_GPIO_17_DRV
+#define GLB_REG_GPIO_17_DRV_POS       (18U)
+#define GLB_REG_GPIO_17_DRV_LEN       (2U)
+#define GLB_REG_GPIO_17_DRV_MSK       (((1U << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS)
+#define GLB_REG_GPIO_17_DRV_UMSK      (~(((1U << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS))
+#define GLB_REG_GPIO_17_PU            GLB_REG_GPIO_17_PU
+#define GLB_REG_GPIO_17_PU_POS        (20U)
+#define GLB_REG_GPIO_17_PU_LEN        (1U)
+#define GLB_REG_GPIO_17_PU_MSK        (((1U << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS)
+#define GLB_REG_GPIO_17_PU_UMSK       (~(((1U << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS))
+#define GLB_REG_GPIO_17_PD            GLB_REG_GPIO_17_PD
+#define GLB_REG_GPIO_17_PD_POS        (21U)
+#define GLB_REG_GPIO_17_PD_LEN        (1U)
+#define GLB_REG_GPIO_17_PD_MSK        (((1U << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS)
+#define GLB_REG_GPIO_17_PD_UMSK       (~(((1U << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS))
+#define GLB_REG_GPIO_17_FUNC_SEL      GLB_REG_GPIO_17_FUNC_SEL
+#define GLB_REG_GPIO_17_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_17_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_17_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_17_FUNC_SEL_POS)
+#define GLB_REG_GPIO_17_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_17_FUNC_SEL_POS))
+
+/* 0x124 : GPIO_CFGCTL9 */
+#define GLB_GPIO_CFGCTL9_OFFSET       (0x124)
+#define GLB_REG_GPIO_18_IE            GLB_REG_GPIO_18_IE
+#define GLB_REG_GPIO_18_IE_POS        (0U)
+#define GLB_REG_GPIO_18_IE_LEN        (1U)
+#define GLB_REG_GPIO_18_IE_MSK        (((1U << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS)
+#define GLB_REG_GPIO_18_IE_UMSK       (~(((1U << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS))
+#define GLB_REG_GPIO_18_SMT           GLB_REG_GPIO_18_SMT
+#define GLB_REG_GPIO_18_SMT_POS       (1U)
+#define GLB_REG_GPIO_18_SMT_LEN       (1U)
+#define GLB_REG_GPIO_18_SMT_MSK       (((1U << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS)
+#define GLB_REG_GPIO_18_SMT_UMSK      (~(((1U << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS))
+#define GLB_REG_GPIO_18_DRV           GLB_REG_GPIO_18_DRV
+#define GLB_REG_GPIO_18_DRV_POS       (2U)
+#define GLB_REG_GPIO_18_DRV_LEN       (2U)
+#define GLB_REG_GPIO_18_DRV_MSK       (((1U << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS)
+#define GLB_REG_GPIO_18_DRV_UMSK      (~(((1U << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS))
+#define GLB_REG_GPIO_18_PU            GLB_REG_GPIO_18_PU
+#define GLB_REG_GPIO_18_PU_POS        (4U)
+#define GLB_REG_GPIO_18_PU_LEN        (1U)
+#define GLB_REG_GPIO_18_PU_MSK        (((1U << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS)
+#define GLB_REG_GPIO_18_PU_UMSK       (~(((1U << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS))
+#define GLB_REG_GPIO_18_PD            GLB_REG_GPIO_18_PD
+#define GLB_REG_GPIO_18_PD_POS        (5U)
+#define GLB_REG_GPIO_18_PD_LEN        (1U)
+#define GLB_REG_GPIO_18_PD_MSK        (((1U << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS)
+#define GLB_REG_GPIO_18_PD_UMSK       (~(((1U << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS))
+#define GLB_REG_GPIO_18_FUNC_SEL      GLB_REG_GPIO_18_FUNC_SEL
+#define GLB_REG_GPIO_18_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_18_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_18_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_18_FUNC_SEL_POS)
+#define GLB_REG_GPIO_18_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_18_FUNC_SEL_POS))
+#define GLB_REG_GPIO_19_IE            GLB_REG_GPIO_19_IE
+#define GLB_REG_GPIO_19_IE_POS        (16U)
+#define GLB_REG_GPIO_19_IE_LEN        (1U)
+#define GLB_REG_GPIO_19_IE_MSK        (((1U << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS)
+#define GLB_REG_GPIO_19_IE_UMSK       (~(((1U << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS))
+#define GLB_REG_GPIO_19_SMT           GLB_REG_GPIO_19_SMT
+#define GLB_REG_GPIO_19_SMT_POS       (17U)
+#define GLB_REG_GPIO_19_SMT_LEN       (1U)
+#define GLB_REG_GPIO_19_SMT_MSK       (((1U << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS)
+#define GLB_REG_GPIO_19_SMT_UMSK      (~(((1U << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS))
+#define GLB_REG_GPIO_19_DRV           GLB_REG_GPIO_19_DRV
+#define GLB_REG_GPIO_19_DRV_POS       (18U)
+#define GLB_REG_GPIO_19_DRV_LEN       (2U)
+#define GLB_REG_GPIO_19_DRV_MSK       (((1U << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS)
+#define GLB_REG_GPIO_19_DRV_UMSK      (~(((1U << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS))
+#define GLB_REG_GPIO_19_PU            GLB_REG_GPIO_19_PU
+#define GLB_REG_GPIO_19_PU_POS        (20U)
+#define GLB_REG_GPIO_19_PU_LEN        (1U)
+#define GLB_REG_GPIO_19_PU_MSK        (((1U << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS)
+#define GLB_REG_GPIO_19_PU_UMSK       (~(((1U << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS))
+#define GLB_REG_GPIO_19_PD            GLB_REG_GPIO_19_PD
+#define GLB_REG_GPIO_19_PD_POS        (21U)
+#define GLB_REG_GPIO_19_PD_LEN        (1U)
+#define GLB_REG_GPIO_19_PD_MSK        (((1U << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS)
+#define GLB_REG_GPIO_19_PD_UMSK       (~(((1U << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS))
+#define GLB_REG_GPIO_19_FUNC_SEL      GLB_REG_GPIO_19_FUNC_SEL
+#define GLB_REG_GPIO_19_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_19_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_19_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_19_FUNC_SEL_POS)
+#define GLB_REG_GPIO_19_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_19_FUNC_SEL_POS))
+
+/* 0x128 : GPIO_CFGCTL10 */
+#define GLB_GPIO_CFGCTL10_OFFSET      (0x128)
+#define GLB_REG_GPIO_20_IE            GLB_REG_GPIO_20_IE
+#define GLB_REG_GPIO_20_IE_POS        (0U)
+#define GLB_REG_GPIO_20_IE_LEN        (1U)
+#define GLB_REG_GPIO_20_IE_MSK        (((1U << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS)
+#define GLB_REG_GPIO_20_IE_UMSK       (~(((1U << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS))
+#define GLB_REG_GPIO_20_SMT           GLB_REG_GPIO_20_SMT
+#define GLB_REG_GPIO_20_SMT_POS       (1U)
+#define GLB_REG_GPIO_20_SMT_LEN       (1U)
+#define GLB_REG_GPIO_20_SMT_MSK       (((1U << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS)
+#define GLB_REG_GPIO_20_SMT_UMSK      (~(((1U << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS))
+#define GLB_REG_GPIO_20_DRV           GLB_REG_GPIO_20_DRV
+#define GLB_REG_GPIO_20_DRV_POS       (2U)
+#define GLB_REG_GPIO_20_DRV_LEN       (2U)
+#define GLB_REG_GPIO_20_DRV_MSK       (((1U << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS)
+#define GLB_REG_GPIO_20_DRV_UMSK      (~(((1U << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS))
+#define GLB_REG_GPIO_20_PU            GLB_REG_GPIO_20_PU
+#define GLB_REG_GPIO_20_PU_POS        (4U)
+#define GLB_REG_GPIO_20_PU_LEN        (1U)
+#define GLB_REG_GPIO_20_PU_MSK        (((1U << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS)
+#define GLB_REG_GPIO_20_PU_UMSK       (~(((1U << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS))
+#define GLB_REG_GPIO_20_PD            GLB_REG_GPIO_20_PD
+#define GLB_REG_GPIO_20_PD_POS        (5U)
+#define GLB_REG_GPIO_20_PD_LEN        (1U)
+#define GLB_REG_GPIO_20_PD_MSK        (((1U << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS)
+#define GLB_REG_GPIO_20_PD_UMSK       (~(((1U << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS))
+#define GLB_REG_GPIO_20_FUNC_SEL      GLB_REG_GPIO_20_FUNC_SEL
+#define GLB_REG_GPIO_20_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_20_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_20_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_20_FUNC_SEL_POS)
+#define GLB_REG_GPIO_20_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_20_FUNC_SEL_POS))
+#define GLB_REG_GPIO_21_IE            GLB_REG_GPIO_21_IE
+#define GLB_REG_GPIO_21_IE_POS        (16U)
+#define GLB_REG_GPIO_21_IE_LEN        (1U)
+#define GLB_REG_GPIO_21_IE_MSK        (((1U << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS)
+#define GLB_REG_GPIO_21_IE_UMSK       (~(((1U << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS))
+#define GLB_REG_GPIO_21_SMT           GLB_REG_GPIO_21_SMT
+#define GLB_REG_GPIO_21_SMT_POS       (17U)
+#define GLB_REG_GPIO_21_SMT_LEN       (1U)
+#define GLB_REG_GPIO_21_SMT_MSK       (((1U << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS)
+#define GLB_REG_GPIO_21_SMT_UMSK      (~(((1U << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS))
+#define GLB_REG_GPIO_21_DRV           GLB_REG_GPIO_21_DRV
+#define GLB_REG_GPIO_21_DRV_POS       (18U)
+#define GLB_REG_GPIO_21_DRV_LEN       (2U)
+#define GLB_REG_GPIO_21_DRV_MSK       (((1U << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS)
+#define GLB_REG_GPIO_21_DRV_UMSK      (~(((1U << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS))
+#define GLB_REG_GPIO_21_PU            GLB_REG_GPIO_21_PU
+#define GLB_REG_GPIO_21_PU_POS        (20U)
+#define GLB_REG_GPIO_21_PU_LEN        (1U)
+#define GLB_REG_GPIO_21_PU_MSK        (((1U << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS)
+#define GLB_REG_GPIO_21_PU_UMSK       (~(((1U << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS))
+#define GLB_REG_GPIO_21_PD            GLB_REG_GPIO_21_PD
+#define GLB_REG_GPIO_21_PD_POS        (21U)
+#define GLB_REG_GPIO_21_PD_LEN        (1U)
+#define GLB_REG_GPIO_21_PD_MSK        (((1U << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS)
+#define GLB_REG_GPIO_21_PD_UMSK       (~(((1U << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS))
+#define GLB_REG_GPIO_21_FUNC_SEL      GLB_REG_GPIO_21_FUNC_SEL
+#define GLB_REG_GPIO_21_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_21_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_21_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_21_FUNC_SEL_POS)
+#define GLB_REG_GPIO_21_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_21_FUNC_SEL_POS))
+
+/* 0x12C : GPIO_CFGCTL11 */
+#define GLB_GPIO_CFGCTL11_OFFSET      (0x12C)
+#define GLB_REG_GPIO_22_IE            GLB_REG_GPIO_22_IE
+#define GLB_REG_GPIO_22_IE_POS        (0U)
+#define GLB_REG_GPIO_22_IE_LEN        (1U)
+#define GLB_REG_GPIO_22_IE_MSK        (((1U << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS)
+#define GLB_REG_GPIO_22_IE_UMSK       (~(((1U << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS))
+#define GLB_REG_GPIO_22_SMT           GLB_REG_GPIO_22_SMT
+#define GLB_REG_GPIO_22_SMT_POS       (1U)
+#define GLB_REG_GPIO_22_SMT_LEN       (1U)
+#define GLB_REG_GPIO_22_SMT_MSK       (((1U << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS)
+#define GLB_REG_GPIO_22_SMT_UMSK      (~(((1U << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS))
+#define GLB_REG_GPIO_22_DRV           GLB_REG_GPIO_22_DRV
+#define GLB_REG_GPIO_22_DRV_POS       (2U)
+#define GLB_REG_GPIO_22_DRV_LEN       (2U)
+#define GLB_REG_GPIO_22_DRV_MSK       (((1U << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS)
+#define GLB_REG_GPIO_22_DRV_UMSK      (~(((1U << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS))
+#define GLB_REG_GPIO_22_PU            GLB_REG_GPIO_22_PU
+#define GLB_REG_GPIO_22_PU_POS        (4U)
+#define GLB_REG_GPIO_22_PU_LEN        (1U)
+#define GLB_REG_GPIO_22_PU_MSK        (((1U << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS)
+#define GLB_REG_GPIO_22_PU_UMSK       (~(((1U << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS))
+#define GLB_REG_GPIO_22_PD            GLB_REG_GPIO_22_PD
+#define GLB_REG_GPIO_22_PD_POS        (5U)
+#define GLB_REG_GPIO_22_PD_LEN        (1U)
+#define GLB_REG_GPIO_22_PD_MSK        (((1U << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS)
+#define GLB_REG_GPIO_22_PD_UMSK       (~(((1U << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS))
+#define GLB_REG_GPIO_22_FUNC_SEL      GLB_REG_GPIO_22_FUNC_SEL
+#define GLB_REG_GPIO_22_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_22_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_22_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_22_FUNC_SEL_POS)
+#define GLB_REG_GPIO_22_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_22_FUNC_SEL_POS))
+#define GLB_REG_GPIO_23_IE            GLB_REG_GPIO_23_IE
+#define GLB_REG_GPIO_23_IE_POS        (16U)
+#define GLB_REG_GPIO_23_IE_LEN        (1U)
+#define GLB_REG_GPIO_23_IE_MSK        (((1U << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS)
+#define GLB_REG_GPIO_23_IE_UMSK       (~(((1U << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS))
+#define GLB_REG_GPIO_23_SMT           GLB_REG_GPIO_23_SMT
+#define GLB_REG_GPIO_23_SMT_POS       (17U)
+#define GLB_REG_GPIO_23_SMT_LEN       (1U)
+#define GLB_REG_GPIO_23_SMT_MSK       (((1U << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS)
+#define GLB_REG_GPIO_23_SMT_UMSK      (~(((1U << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS))
+#define GLB_REG_GPIO_23_DRV           GLB_REG_GPIO_23_DRV
+#define GLB_REG_GPIO_23_DRV_POS       (18U)
+#define GLB_REG_GPIO_23_DRV_LEN       (2U)
+#define GLB_REG_GPIO_23_DRV_MSK       (((1U << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS)
+#define GLB_REG_GPIO_23_DRV_UMSK      (~(((1U << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS))
+#define GLB_REG_GPIO_23_PU            GLB_REG_GPIO_23_PU
+#define GLB_REG_GPIO_23_PU_POS        (20U)
+#define GLB_REG_GPIO_23_PU_LEN        (1U)
+#define GLB_REG_GPIO_23_PU_MSK        (((1U << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS)
+#define GLB_REG_GPIO_23_PU_UMSK       (~(((1U << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS))
+#define GLB_REG_GPIO_23_PD            GLB_REG_GPIO_23_PD
+#define GLB_REG_GPIO_23_PD_POS        (21U)
+#define GLB_REG_GPIO_23_PD_LEN        (1U)
+#define GLB_REG_GPIO_23_PD_MSK        (((1U << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS)
+#define GLB_REG_GPIO_23_PD_UMSK       (~(((1U << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS))
+#define GLB_REG_GPIO_23_FUNC_SEL      GLB_REG_GPIO_23_FUNC_SEL
+#define GLB_REG_GPIO_23_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_23_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_23_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_23_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_23_FUNC_SEL_POS)
+#define GLB_REG_GPIO_23_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_23_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_23_FUNC_SEL_POS))
+
+/* 0x130 : GPIO_CFGCTL12 */
+#define GLB_GPIO_CFGCTL12_OFFSET      (0x130)
+#define GLB_REG_GPIO_24_IE            GLB_REG_GPIO_24_IE
+#define GLB_REG_GPIO_24_IE_POS        (0U)
+#define GLB_REG_GPIO_24_IE_LEN        (1U)
+#define GLB_REG_GPIO_24_IE_MSK        (((1U << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS)
+#define GLB_REG_GPIO_24_IE_UMSK       (~(((1U << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS))
+#define GLB_REG_GPIO_24_SMT           GLB_REG_GPIO_24_SMT
+#define GLB_REG_GPIO_24_SMT_POS       (1U)
+#define GLB_REG_GPIO_24_SMT_LEN       (1U)
+#define GLB_REG_GPIO_24_SMT_MSK       (((1U << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS)
+#define GLB_REG_GPIO_24_SMT_UMSK      (~(((1U << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS))
+#define GLB_REG_GPIO_24_DRV           GLB_REG_GPIO_24_DRV
+#define GLB_REG_GPIO_24_DRV_POS       (2U)
+#define GLB_REG_GPIO_24_DRV_LEN       (2U)
+#define GLB_REG_GPIO_24_DRV_MSK       (((1U << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS)
+#define GLB_REG_GPIO_24_DRV_UMSK      (~(((1U << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS))
+#define GLB_REG_GPIO_24_PU            GLB_REG_GPIO_24_PU
+#define GLB_REG_GPIO_24_PU_POS        (4U)
+#define GLB_REG_GPIO_24_PU_LEN        (1U)
+#define GLB_REG_GPIO_24_PU_MSK        (((1U << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS)
+#define GLB_REG_GPIO_24_PU_UMSK       (~(((1U << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS))
+#define GLB_REG_GPIO_24_PD            GLB_REG_GPIO_24_PD
+#define GLB_REG_GPIO_24_PD_POS        (5U)
+#define GLB_REG_GPIO_24_PD_LEN        (1U)
+#define GLB_REG_GPIO_24_PD_MSK        (((1U << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS)
+#define GLB_REG_GPIO_24_PD_UMSK       (~(((1U << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS))
+#define GLB_REG_GPIO_24_FUNC_SEL      GLB_REG_GPIO_24_FUNC_SEL
+#define GLB_REG_GPIO_24_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_24_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_24_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_24_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_24_FUNC_SEL_POS)
+#define GLB_REG_GPIO_24_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_24_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_24_FUNC_SEL_POS))
+#define GLB_REG_GPIO_25_IE            GLB_REG_GPIO_25_IE
+#define GLB_REG_GPIO_25_IE_POS        (16U)
+#define GLB_REG_GPIO_25_IE_LEN        (1U)
+#define GLB_REG_GPIO_25_IE_MSK        (((1U << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS)
+#define GLB_REG_GPIO_25_IE_UMSK       (~(((1U << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS))
+#define GLB_REG_GPIO_25_SMT           GLB_REG_GPIO_25_SMT
+#define GLB_REG_GPIO_25_SMT_POS       (17U)
+#define GLB_REG_GPIO_25_SMT_LEN       (1U)
+#define GLB_REG_GPIO_25_SMT_MSK       (((1U << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS)
+#define GLB_REG_GPIO_25_SMT_UMSK      (~(((1U << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS))
+#define GLB_REG_GPIO_25_DRV           GLB_REG_GPIO_25_DRV
+#define GLB_REG_GPIO_25_DRV_POS       (18U)
+#define GLB_REG_GPIO_25_DRV_LEN       (2U)
+#define GLB_REG_GPIO_25_DRV_MSK       (((1U << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS)
+#define GLB_REG_GPIO_25_DRV_UMSK      (~(((1U << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS))
+#define GLB_REG_GPIO_25_PU            GLB_REG_GPIO_25_PU
+#define GLB_REG_GPIO_25_PU_POS        (20U)
+#define GLB_REG_GPIO_25_PU_LEN        (1U)
+#define GLB_REG_GPIO_25_PU_MSK        (((1U << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS)
+#define GLB_REG_GPIO_25_PU_UMSK       (~(((1U << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS))
+#define GLB_REG_GPIO_25_PD            GLB_REG_GPIO_25_PD
+#define GLB_REG_GPIO_25_PD_POS        (21U)
+#define GLB_REG_GPIO_25_PD_LEN        (1U)
+#define GLB_REG_GPIO_25_PD_MSK        (((1U << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS)
+#define GLB_REG_GPIO_25_PD_UMSK       (~(((1U << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS))
+#define GLB_REG_GPIO_25_FUNC_SEL      GLB_REG_GPIO_25_FUNC_SEL
+#define GLB_REG_GPIO_25_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_25_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_25_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_25_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_25_FUNC_SEL_POS)
+#define GLB_REG_GPIO_25_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_25_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_25_FUNC_SEL_POS))
+
+/* 0x134 : GPIO_CFGCTL13 */
+#define GLB_GPIO_CFGCTL13_OFFSET      (0x134)
+#define GLB_REG_GPIO_26_IE            GLB_REG_GPIO_26_IE
+#define GLB_REG_GPIO_26_IE_POS        (0U)
+#define GLB_REG_GPIO_26_IE_LEN        (1U)
+#define GLB_REG_GPIO_26_IE_MSK        (((1U << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS)
+#define GLB_REG_GPIO_26_IE_UMSK       (~(((1U << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS))
+#define GLB_REG_GPIO_26_SMT           GLB_REG_GPIO_26_SMT
+#define GLB_REG_GPIO_26_SMT_POS       (1U)
+#define GLB_REG_GPIO_26_SMT_LEN       (1U)
+#define GLB_REG_GPIO_26_SMT_MSK       (((1U << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS)
+#define GLB_REG_GPIO_26_SMT_UMSK      (~(((1U << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS))
+#define GLB_REG_GPIO_26_DRV           GLB_REG_GPIO_26_DRV
+#define GLB_REG_GPIO_26_DRV_POS       (2U)
+#define GLB_REG_GPIO_26_DRV_LEN       (2U)
+#define GLB_REG_GPIO_26_DRV_MSK       (((1U << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS)
+#define GLB_REG_GPIO_26_DRV_UMSK      (~(((1U << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS))
+#define GLB_REG_GPIO_26_PU            GLB_REG_GPIO_26_PU
+#define GLB_REG_GPIO_26_PU_POS        (4U)
+#define GLB_REG_GPIO_26_PU_LEN        (1U)
+#define GLB_REG_GPIO_26_PU_MSK        (((1U << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS)
+#define GLB_REG_GPIO_26_PU_UMSK       (~(((1U << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS))
+#define GLB_REG_GPIO_26_PD            GLB_REG_GPIO_26_PD
+#define GLB_REG_GPIO_26_PD_POS        (5U)
+#define GLB_REG_GPIO_26_PD_LEN        (1U)
+#define GLB_REG_GPIO_26_PD_MSK        (((1U << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS)
+#define GLB_REG_GPIO_26_PD_UMSK       (~(((1U << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS))
+#define GLB_REG_GPIO_26_FUNC_SEL      GLB_REG_GPIO_26_FUNC_SEL
+#define GLB_REG_GPIO_26_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_26_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_26_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_26_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_26_FUNC_SEL_POS)
+#define GLB_REG_GPIO_26_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_26_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_26_FUNC_SEL_POS))
+#define GLB_REG_GPIO_27_IE            GLB_REG_GPIO_27_IE
+#define GLB_REG_GPIO_27_IE_POS        (16U)
+#define GLB_REG_GPIO_27_IE_LEN        (1U)
+#define GLB_REG_GPIO_27_IE_MSK        (((1U << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS)
+#define GLB_REG_GPIO_27_IE_UMSK       (~(((1U << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS))
+#define GLB_REG_GPIO_27_SMT           GLB_REG_GPIO_27_SMT
+#define GLB_REG_GPIO_27_SMT_POS       (17U)
+#define GLB_REG_GPIO_27_SMT_LEN       (1U)
+#define GLB_REG_GPIO_27_SMT_MSK       (((1U << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS)
+#define GLB_REG_GPIO_27_SMT_UMSK      (~(((1U << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS))
+#define GLB_REG_GPIO_27_DRV           GLB_REG_GPIO_27_DRV
+#define GLB_REG_GPIO_27_DRV_POS       (18U)
+#define GLB_REG_GPIO_27_DRV_LEN       (2U)
+#define GLB_REG_GPIO_27_DRV_MSK       (((1U << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS)
+#define GLB_REG_GPIO_27_DRV_UMSK      (~(((1U << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS))
+#define GLB_REG_GPIO_27_PU            GLB_REG_GPIO_27_PU
+#define GLB_REG_GPIO_27_PU_POS        (20U)
+#define GLB_REG_GPIO_27_PU_LEN        (1U)
+#define GLB_REG_GPIO_27_PU_MSK        (((1U << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS)
+#define GLB_REG_GPIO_27_PU_UMSK       (~(((1U << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS))
+#define GLB_REG_GPIO_27_PD            GLB_REG_GPIO_27_PD
+#define GLB_REG_GPIO_27_PD_POS        (21U)
+#define GLB_REG_GPIO_27_PD_LEN        (1U)
+#define GLB_REG_GPIO_27_PD_MSK        (((1U << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS)
+#define GLB_REG_GPIO_27_PD_UMSK       (~(((1U << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS))
+#define GLB_REG_GPIO_27_FUNC_SEL      GLB_REG_GPIO_27_FUNC_SEL
+#define GLB_REG_GPIO_27_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_27_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_27_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_27_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_27_FUNC_SEL_POS)
+#define GLB_REG_GPIO_27_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_27_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_27_FUNC_SEL_POS))
+
+/* 0x138 : GPIO_CFGCTL14 */
+#define GLB_GPIO_CFGCTL14_OFFSET      (0x138)
+#define GLB_REG_GPIO_28_IE            GLB_REG_GPIO_28_IE
+#define GLB_REG_GPIO_28_IE_POS        (0U)
+#define GLB_REG_GPIO_28_IE_LEN        (1U)
+#define GLB_REG_GPIO_28_IE_MSK        (((1U << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS)
+#define GLB_REG_GPIO_28_IE_UMSK       (~(((1U << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS))
+#define GLB_REG_GPIO_28_SMT           GLB_REG_GPIO_28_SMT
+#define GLB_REG_GPIO_28_SMT_POS       (1U)
+#define GLB_REG_GPIO_28_SMT_LEN       (1U)
+#define GLB_REG_GPIO_28_SMT_MSK       (((1U << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS)
+#define GLB_REG_GPIO_28_SMT_UMSK      (~(((1U << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS))
+#define GLB_REG_GPIO_28_DRV           GLB_REG_GPIO_28_DRV
+#define GLB_REG_GPIO_28_DRV_POS       (2U)
+#define GLB_REG_GPIO_28_DRV_LEN       (2U)
+#define GLB_REG_GPIO_28_DRV_MSK       (((1U << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS)
+#define GLB_REG_GPIO_28_DRV_UMSK      (~(((1U << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS))
+#define GLB_REG_GPIO_28_PU            GLB_REG_GPIO_28_PU
+#define GLB_REG_GPIO_28_PU_POS        (4U)
+#define GLB_REG_GPIO_28_PU_LEN        (1U)
+#define GLB_REG_GPIO_28_PU_MSK        (((1U << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS)
+#define GLB_REG_GPIO_28_PU_UMSK       (~(((1U << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS))
+#define GLB_REG_GPIO_28_PD            GLB_REG_GPIO_28_PD
+#define GLB_REG_GPIO_28_PD_POS        (5U)
+#define GLB_REG_GPIO_28_PD_LEN        (1U)
+#define GLB_REG_GPIO_28_PD_MSK        (((1U << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS)
+#define GLB_REG_GPIO_28_PD_UMSK       (~(((1U << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS))
+#define GLB_REG_GPIO_28_FUNC_SEL      GLB_REG_GPIO_28_FUNC_SEL
+#define GLB_REG_GPIO_28_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_28_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_28_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_28_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_28_FUNC_SEL_POS)
+#define GLB_REG_GPIO_28_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_28_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_28_FUNC_SEL_POS))
+#define GLB_REG_GPIO_29_IE            GLB_REG_GPIO_29_IE
+#define GLB_REG_GPIO_29_IE_POS        (16U)
+#define GLB_REG_GPIO_29_IE_LEN        (1U)
+#define GLB_REG_GPIO_29_IE_MSK        (((1U << GLB_REG_GPIO_29_IE_LEN) - 1) << GLB_REG_GPIO_29_IE_POS)
+#define GLB_REG_GPIO_29_IE_UMSK       (~(((1U << GLB_REG_GPIO_29_IE_LEN) - 1) << GLB_REG_GPIO_29_IE_POS))
+#define GLB_REG_GPIO_29_SMT           GLB_REG_GPIO_29_SMT
+#define GLB_REG_GPIO_29_SMT_POS       (17U)
+#define GLB_REG_GPIO_29_SMT_LEN       (1U)
+#define GLB_REG_GPIO_29_SMT_MSK       (((1U << GLB_REG_GPIO_29_SMT_LEN) - 1) << GLB_REG_GPIO_29_SMT_POS)
+#define GLB_REG_GPIO_29_SMT_UMSK      (~(((1U << GLB_REG_GPIO_29_SMT_LEN) - 1) << GLB_REG_GPIO_29_SMT_POS))
+#define GLB_REG_GPIO_29_DRV           GLB_REG_GPIO_29_DRV
+#define GLB_REG_GPIO_29_DRV_POS       (18U)
+#define GLB_REG_GPIO_29_DRV_LEN       (2U)
+#define GLB_REG_GPIO_29_DRV_MSK       (((1U << GLB_REG_GPIO_29_DRV_LEN) - 1) << GLB_REG_GPIO_29_DRV_POS)
+#define GLB_REG_GPIO_29_DRV_UMSK      (~(((1U << GLB_REG_GPIO_29_DRV_LEN) - 1) << GLB_REG_GPIO_29_DRV_POS))
+#define GLB_REG_GPIO_29_PU            GLB_REG_GPIO_29_PU
+#define GLB_REG_GPIO_29_PU_POS        (20U)
+#define GLB_REG_GPIO_29_PU_LEN        (1U)
+#define GLB_REG_GPIO_29_PU_MSK        (((1U << GLB_REG_GPIO_29_PU_LEN) - 1) << GLB_REG_GPIO_29_PU_POS)
+#define GLB_REG_GPIO_29_PU_UMSK       (~(((1U << GLB_REG_GPIO_29_PU_LEN) - 1) << GLB_REG_GPIO_29_PU_POS))
+#define GLB_REG_GPIO_29_PD            GLB_REG_GPIO_29_PD
+#define GLB_REG_GPIO_29_PD_POS        (21U)
+#define GLB_REG_GPIO_29_PD_LEN        (1U)
+#define GLB_REG_GPIO_29_PD_MSK        (((1U << GLB_REG_GPIO_29_PD_LEN) - 1) << GLB_REG_GPIO_29_PD_POS)
+#define GLB_REG_GPIO_29_PD_UMSK       (~(((1U << GLB_REG_GPIO_29_PD_LEN) - 1) << GLB_REG_GPIO_29_PD_POS))
+#define GLB_REG_GPIO_29_FUNC_SEL      GLB_REG_GPIO_29_FUNC_SEL
+#define GLB_REG_GPIO_29_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_29_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_29_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_29_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_29_FUNC_SEL_POS)
+#define GLB_REG_GPIO_29_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_29_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_29_FUNC_SEL_POS))
+
+/* 0x13C : GPIO_CFGCTL15 */
+#define GLB_GPIO_CFGCTL15_OFFSET      (0x13C)
+#define GLB_REG_GPIO_30_IE            GLB_REG_GPIO_30_IE
+#define GLB_REG_GPIO_30_IE_POS        (0U)
+#define GLB_REG_GPIO_30_IE_LEN        (1U)
+#define GLB_REG_GPIO_30_IE_MSK        (((1U << GLB_REG_GPIO_30_IE_LEN) - 1) << GLB_REG_GPIO_30_IE_POS)
+#define GLB_REG_GPIO_30_IE_UMSK       (~(((1U << GLB_REG_GPIO_30_IE_LEN) - 1) << GLB_REG_GPIO_30_IE_POS))
+#define GLB_REG_GPIO_30_SMT           GLB_REG_GPIO_30_SMT
+#define GLB_REG_GPIO_30_SMT_POS       (1U)
+#define GLB_REG_GPIO_30_SMT_LEN       (1U)
+#define GLB_REG_GPIO_30_SMT_MSK       (((1U << GLB_REG_GPIO_30_SMT_LEN) - 1) << GLB_REG_GPIO_30_SMT_POS)
+#define GLB_REG_GPIO_30_SMT_UMSK      (~(((1U << GLB_REG_GPIO_30_SMT_LEN) - 1) << GLB_REG_GPIO_30_SMT_POS))
+#define GLB_REG_GPIO_30_DRV           GLB_REG_GPIO_30_DRV
+#define GLB_REG_GPIO_30_DRV_POS       (2U)
+#define GLB_REG_GPIO_30_DRV_LEN       (2U)
+#define GLB_REG_GPIO_30_DRV_MSK       (((1U << GLB_REG_GPIO_30_DRV_LEN) - 1) << GLB_REG_GPIO_30_DRV_POS)
+#define GLB_REG_GPIO_30_DRV_UMSK      (~(((1U << GLB_REG_GPIO_30_DRV_LEN) - 1) << GLB_REG_GPIO_30_DRV_POS))
+#define GLB_REG_GPIO_30_PU            GLB_REG_GPIO_30_PU
+#define GLB_REG_GPIO_30_PU_POS        (4U)
+#define GLB_REG_GPIO_30_PU_LEN        (1U)
+#define GLB_REG_GPIO_30_PU_MSK        (((1U << GLB_REG_GPIO_30_PU_LEN) - 1) << GLB_REG_GPIO_30_PU_POS)
+#define GLB_REG_GPIO_30_PU_UMSK       (~(((1U << GLB_REG_GPIO_30_PU_LEN) - 1) << GLB_REG_GPIO_30_PU_POS))
+#define GLB_REG_GPIO_30_PD            GLB_REG_GPIO_30_PD
+#define GLB_REG_GPIO_30_PD_POS        (5U)
+#define GLB_REG_GPIO_30_PD_LEN        (1U)
+#define GLB_REG_GPIO_30_PD_MSK        (((1U << GLB_REG_GPIO_30_PD_LEN) - 1) << GLB_REG_GPIO_30_PD_POS)
+#define GLB_REG_GPIO_30_PD_UMSK       (~(((1U << GLB_REG_GPIO_30_PD_LEN) - 1) << GLB_REG_GPIO_30_PD_POS))
+#define GLB_REG_GPIO_30_FUNC_SEL      GLB_REG_GPIO_30_FUNC_SEL
+#define GLB_REG_GPIO_30_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_30_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_30_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_30_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_30_FUNC_SEL_POS)
+#define GLB_REG_GPIO_30_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_30_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_30_FUNC_SEL_POS))
+#define GLB_REG_GPIO_31_IE            GLB_REG_GPIO_31_IE
+#define GLB_REG_GPIO_31_IE_POS        (16U)
+#define GLB_REG_GPIO_31_IE_LEN        (1U)
+#define GLB_REG_GPIO_31_IE_MSK        (((1U << GLB_REG_GPIO_31_IE_LEN) - 1) << GLB_REG_GPIO_31_IE_POS)
+#define GLB_REG_GPIO_31_IE_UMSK       (~(((1U << GLB_REG_GPIO_31_IE_LEN) - 1) << GLB_REG_GPIO_31_IE_POS))
+#define GLB_REG_GPIO_31_SMT           GLB_REG_GPIO_31_SMT
+#define GLB_REG_GPIO_31_SMT_POS       (17U)
+#define GLB_REG_GPIO_31_SMT_LEN       (1U)
+#define GLB_REG_GPIO_31_SMT_MSK       (((1U << GLB_REG_GPIO_31_SMT_LEN) - 1) << GLB_REG_GPIO_31_SMT_POS)
+#define GLB_REG_GPIO_31_SMT_UMSK      (~(((1U << GLB_REG_GPIO_31_SMT_LEN) - 1) << GLB_REG_GPIO_31_SMT_POS))
+#define GLB_REG_GPIO_31_DRV           GLB_REG_GPIO_31_DRV
+#define GLB_REG_GPIO_31_DRV_POS       (18U)
+#define GLB_REG_GPIO_31_DRV_LEN       (2U)
+#define GLB_REG_GPIO_31_DRV_MSK       (((1U << GLB_REG_GPIO_31_DRV_LEN) - 1) << GLB_REG_GPIO_31_DRV_POS)
+#define GLB_REG_GPIO_31_DRV_UMSK      (~(((1U << GLB_REG_GPIO_31_DRV_LEN) - 1) << GLB_REG_GPIO_31_DRV_POS))
+#define GLB_REG_GPIO_31_PU            GLB_REG_GPIO_31_PU
+#define GLB_REG_GPIO_31_PU_POS        (20U)
+#define GLB_REG_GPIO_31_PU_LEN        (1U)
+#define GLB_REG_GPIO_31_PU_MSK        (((1U << GLB_REG_GPIO_31_PU_LEN) - 1) << GLB_REG_GPIO_31_PU_POS)
+#define GLB_REG_GPIO_31_PU_UMSK       (~(((1U << GLB_REG_GPIO_31_PU_LEN) - 1) << GLB_REG_GPIO_31_PU_POS))
+#define GLB_REG_GPIO_31_PD            GLB_REG_GPIO_31_PD
+#define GLB_REG_GPIO_31_PD_POS        (21U)
+#define GLB_REG_GPIO_31_PD_LEN        (1U)
+#define GLB_REG_GPIO_31_PD_MSK        (((1U << GLB_REG_GPIO_31_PD_LEN) - 1) << GLB_REG_GPIO_31_PD_POS)
+#define GLB_REG_GPIO_31_PD_UMSK       (~(((1U << GLB_REG_GPIO_31_PD_LEN) - 1) << GLB_REG_GPIO_31_PD_POS))
+#define GLB_REG_GPIO_31_FUNC_SEL      GLB_REG_GPIO_31_FUNC_SEL
+#define GLB_REG_GPIO_31_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_31_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_31_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_31_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_31_FUNC_SEL_POS)
+#define GLB_REG_GPIO_31_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_31_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_31_FUNC_SEL_POS))
+
+/* 0x140 : GPIO_CFGCTL16 */
+#define GLB_GPIO_CFGCTL16_OFFSET (0x140)
+#define GLB_REG_GPIO_32_IE       GLB_REG_GPIO_32_IE
+#define GLB_REG_GPIO_32_IE_POS   (0U)
+#define GLB_REG_GPIO_32_IE_LEN   (1U)
+#define GLB_REG_GPIO_32_IE_MSK   (((1U << GLB_REG_GPIO_32_IE_LEN) - 1) << GLB_REG_GPIO_32_IE_POS)
+#define GLB_REG_GPIO_32_IE_UMSK  (~(((1U << GLB_REG_GPIO_32_IE_LEN) - 1) << GLB_REG_GPIO_32_IE_POS))
+#define GLB_REG_GPIO_32_SMT      GLB_REG_GPIO_32_SMT
+#define GLB_REG_GPIO_32_SMT_POS  (1U)
+#define GLB_REG_GPIO_32_SMT_LEN  (1U)
+#define GLB_REG_GPIO_32_SMT_MSK  (((1U << GLB_REG_GPIO_32_SMT_LEN) - 1) << GLB_REG_GPIO_32_SMT_POS)
+#define GLB_REG_GPIO_32_SMT_UMSK (~(((1U << GLB_REG_GPIO_32_SMT_LEN) - 1) << GLB_REG_GPIO_32_SMT_POS))
+#define GLB_REG_GPIO_32_DRV      GLB_REG_GPIO_32_DRV
+#define GLB_REG_GPIO_32_DRV_POS  (2U)
+#define GLB_REG_GPIO_32_DRV_LEN  (2U)
+#define GLB_REG_GPIO_32_DRV_MSK  (((1U << GLB_REG_GPIO_32_DRV_LEN) - 1) << GLB_REG_GPIO_32_DRV_POS)
+#define GLB_REG_GPIO_32_DRV_UMSK (~(((1U << GLB_REG_GPIO_32_DRV_LEN) - 1) << GLB_REG_GPIO_32_DRV_POS))
+#define GLB_REG_GPIO_32_PU       GLB_REG_GPIO_32_PU
+#define GLB_REG_GPIO_32_PU_POS   (4U)
+#define GLB_REG_GPIO_32_PU_LEN   (1U)
+#define GLB_REG_GPIO_32_PU_MSK   (((1U << GLB_REG_GPIO_32_PU_LEN) - 1) << GLB_REG_GPIO_32_PU_POS)
+#define GLB_REG_GPIO_32_PU_UMSK  (~(((1U << GLB_REG_GPIO_32_PU_LEN) - 1) << GLB_REG_GPIO_32_PU_POS))
+#define GLB_REG_GPIO_32_PD       GLB_REG_GPIO_32_PD
+#define GLB_REG_GPIO_32_PD_POS   (5U)
+#define GLB_REG_GPIO_32_PD_LEN   (1U)
+#define GLB_REG_GPIO_32_PD_MSK   (((1U << GLB_REG_GPIO_32_PD_LEN) - 1) << GLB_REG_GPIO_32_PD_POS)
+#define GLB_REG_GPIO_32_PD_UMSK  (~(((1U << GLB_REG_GPIO_32_PD_LEN) - 1) << GLB_REG_GPIO_32_PD_POS))
+#define GLB_REG_GPIO_33_IE       GLB_REG_GPIO_33_IE
+#define GLB_REG_GPIO_33_IE_POS   (16U)
+#define GLB_REG_GPIO_33_IE_LEN   (1U)
+#define GLB_REG_GPIO_33_IE_MSK   (((1U << GLB_REG_GPIO_33_IE_LEN) - 1) << GLB_REG_GPIO_33_IE_POS)
+#define GLB_REG_GPIO_33_IE_UMSK  (~(((1U << GLB_REG_GPIO_33_IE_LEN) - 1) << GLB_REG_GPIO_33_IE_POS))
+#define GLB_REG_GPIO_33_SMT      GLB_REG_GPIO_33_SMT
+#define GLB_REG_GPIO_33_SMT_POS  (17U)
+#define GLB_REG_GPIO_33_SMT_LEN  (1U)
+#define GLB_REG_GPIO_33_SMT_MSK  (((1U << GLB_REG_GPIO_33_SMT_LEN) - 1) << GLB_REG_GPIO_33_SMT_POS)
+#define GLB_REG_GPIO_33_SMT_UMSK (~(((1U << GLB_REG_GPIO_33_SMT_LEN) - 1) << GLB_REG_GPIO_33_SMT_POS))
+#define GLB_REG_GPIO_33_DRV      GLB_REG_GPIO_33_DRV
+#define GLB_REG_GPIO_33_DRV_POS  (18U)
+#define GLB_REG_GPIO_33_DRV_LEN  (2U)
+#define GLB_REG_GPIO_33_DRV_MSK  (((1U << GLB_REG_GPIO_33_DRV_LEN) - 1) << GLB_REG_GPIO_33_DRV_POS)
+#define GLB_REG_GPIO_33_DRV_UMSK (~(((1U << GLB_REG_GPIO_33_DRV_LEN) - 1) << GLB_REG_GPIO_33_DRV_POS))
+#define GLB_REG_GPIO_33_PU       GLB_REG_GPIO_33_PU
+#define GLB_REG_GPIO_33_PU_POS   (20U)
+#define GLB_REG_GPIO_33_PU_LEN   (1U)
+#define GLB_REG_GPIO_33_PU_MSK   (((1U << GLB_REG_GPIO_33_PU_LEN) - 1) << GLB_REG_GPIO_33_PU_POS)
+#define GLB_REG_GPIO_33_PU_UMSK  (~(((1U << GLB_REG_GPIO_33_PU_LEN) - 1) << GLB_REG_GPIO_33_PU_POS))
+#define GLB_REG_GPIO_33_PD       GLB_REG_GPIO_33_PD
+#define GLB_REG_GPIO_33_PD_POS   (21U)
+#define GLB_REG_GPIO_33_PD_LEN   (1U)
+#define GLB_REG_GPIO_33_PD_MSK   (((1U << GLB_REG_GPIO_33_PD_LEN) - 1) << GLB_REG_GPIO_33_PD_POS)
+#define GLB_REG_GPIO_33_PD_UMSK  (~(((1U << GLB_REG_GPIO_33_PD_LEN) - 1) << GLB_REG_GPIO_33_PD_POS))
+
+/* 0x144 : GPIO_CFGCTL17 */
+#define GLB_GPIO_CFGCTL17_OFFSET (0x144)
+#define GLB_REG_GPIO_34_IE       GLB_REG_GPIO_34_IE
+#define GLB_REG_GPIO_34_IE_POS   (0U)
+#define GLB_REG_GPIO_34_IE_LEN   (1U)
+#define GLB_REG_GPIO_34_IE_MSK   (((1U << GLB_REG_GPIO_34_IE_LEN) - 1) << GLB_REG_GPIO_34_IE_POS)
+#define GLB_REG_GPIO_34_IE_UMSK  (~(((1U << GLB_REG_GPIO_34_IE_LEN) - 1) << GLB_REG_GPIO_34_IE_POS))
+#define GLB_REG_GPIO_34_SMT      GLB_REG_GPIO_34_SMT
+#define GLB_REG_GPIO_34_SMT_POS  (1U)
+#define GLB_REG_GPIO_34_SMT_LEN  (1U)
+#define GLB_REG_GPIO_34_SMT_MSK  (((1U << GLB_REG_GPIO_34_SMT_LEN) - 1) << GLB_REG_GPIO_34_SMT_POS)
+#define GLB_REG_GPIO_34_SMT_UMSK (~(((1U << GLB_REG_GPIO_34_SMT_LEN) - 1) << GLB_REG_GPIO_34_SMT_POS))
+#define GLB_REG_GPIO_34_DRV      GLB_REG_GPIO_34_DRV
+#define GLB_REG_GPIO_34_DRV_POS  (2U)
+#define GLB_REG_GPIO_34_DRV_LEN  (2U)
+#define GLB_REG_GPIO_34_DRV_MSK  (((1U << GLB_REG_GPIO_34_DRV_LEN) - 1) << GLB_REG_GPIO_34_DRV_POS)
+#define GLB_REG_GPIO_34_DRV_UMSK (~(((1U << GLB_REG_GPIO_34_DRV_LEN) - 1) << GLB_REG_GPIO_34_DRV_POS))
+#define GLB_REG_GPIO_34_PU       GLB_REG_GPIO_34_PU
+#define GLB_REG_GPIO_34_PU_POS   (4U)
+#define GLB_REG_GPIO_34_PU_LEN   (1U)
+#define GLB_REG_GPIO_34_PU_MSK   (((1U << GLB_REG_GPIO_34_PU_LEN) - 1) << GLB_REG_GPIO_34_PU_POS)
+#define GLB_REG_GPIO_34_PU_UMSK  (~(((1U << GLB_REG_GPIO_34_PU_LEN) - 1) << GLB_REG_GPIO_34_PU_POS))
+#define GLB_REG_GPIO_34_PD       GLB_REG_GPIO_34_PD
+#define GLB_REG_GPIO_34_PD_POS   (5U)
+#define GLB_REG_GPIO_34_PD_LEN   (1U)
+#define GLB_REG_GPIO_34_PD_MSK   (((1U << GLB_REG_GPIO_34_PD_LEN) - 1) << GLB_REG_GPIO_34_PD_POS)
+#define GLB_REG_GPIO_34_PD_UMSK  (~(((1U << GLB_REG_GPIO_34_PD_LEN) - 1) << GLB_REG_GPIO_34_PD_POS))
+#define GLB_REG_GPIO_35_IE       GLB_REG_GPIO_35_IE
+#define GLB_REG_GPIO_35_IE_POS   (16U)
+#define GLB_REG_GPIO_35_IE_LEN   (1U)
+#define GLB_REG_GPIO_35_IE_MSK   (((1U << GLB_REG_GPIO_35_IE_LEN) - 1) << GLB_REG_GPIO_35_IE_POS)
+#define GLB_REG_GPIO_35_IE_UMSK  (~(((1U << GLB_REG_GPIO_35_IE_LEN) - 1) << GLB_REG_GPIO_35_IE_POS))
+#define GLB_REG_GPIO_35_SMT      GLB_REG_GPIO_35_SMT
+#define GLB_REG_GPIO_35_SMT_POS  (17U)
+#define GLB_REG_GPIO_35_SMT_LEN  (1U)
+#define GLB_REG_GPIO_35_SMT_MSK  (((1U << GLB_REG_GPIO_35_SMT_LEN) - 1) << GLB_REG_GPIO_35_SMT_POS)
+#define GLB_REG_GPIO_35_SMT_UMSK (~(((1U << GLB_REG_GPIO_35_SMT_LEN) - 1) << GLB_REG_GPIO_35_SMT_POS))
+#define GLB_REG_GPIO_35_DRV      GLB_REG_GPIO_35_DRV
+#define GLB_REG_GPIO_35_DRV_POS  (18U)
+#define GLB_REG_GPIO_35_DRV_LEN  (2U)
+#define GLB_REG_GPIO_35_DRV_MSK  (((1U << GLB_REG_GPIO_35_DRV_LEN) - 1) << GLB_REG_GPIO_35_DRV_POS)
+#define GLB_REG_GPIO_35_DRV_UMSK (~(((1U << GLB_REG_GPIO_35_DRV_LEN) - 1) << GLB_REG_GPIO_35_DRV_POS))
+#define GLB_REG_GPIO_35_PU       GLB_REG_GPIO_35_PU
+#define GLB_REG_GPIO_35_PU_POS   (20U)
+#define GLB_REG_GPIO_35_PU_LEN   (1U)
+#define GLB_REG_GPIO_35_PU_MSK   (((1U << GLB_REG_GPIO_35_PU_LEN) - 1) << GLB_REG_GPIO_35_PU_POS)
+#define GLB_REG_GPIO_35_PU_UMSK  (~(((1U << GLB_REG_GPIO_35_PU_LEN) - 1) << GLB_REG_GPIO_35_PU_POS))
+#define GLB_REG_GPIO_35_PD       GLB_REG_GPIO_35_PD
+#define GLB_REG_GPIO_35_PD_POS   (21U)
+#define GLB_REG_GPIO_35_PD_LEN   (1U)
+#define GLB_REG_GPIO_35_PD_MSK   (((1U << GLB_REG_GPIO_35_PD_LEN) - 1) << GLB_REG_GPIO_35_PD_POS)
+#define GLB_REG_GPIO_35_PD_UMSK  (~(((1U << GLB_REG_GPIO_35_PD_LEN) - 1) << GLB_REG_GPIO_35_PD_POS))
+
+/* 0x148 : GPIO_CFGCTL18 */
+#define GLB_GPIO_CFGCTL18_OFFSET (0x148)
+#define GLB_REG_GPIO_36_IE       GLB_REG_GPIO_36_IE
+#define GLB_REG_GPIO_36_IE_POS   (0U)
+#define GLB_REG_GPIO_36_IE_LEN   (1U)
+#define GLB_REG_GPIO_36_IE_MSK   (((1U << GLB_REG_GPIO_36_IE_LEN) - 1) << GLB_REG_GPIO_36_IE_POS)
+#define GLB_REG_GPIO_36_IE_UMSK  (~(((1U << GLB_REG_GPIO_36_IE_LEN) - 1) << GLB_REG_GPIO_36_IE_POS))
+#define GLB_REG_GPIO_36_SMT      GLB_REG_GPIO_36_SMT
+#define GLB_REG_GPIO_36_SMT_POS  (1U)
+#define GLB_REG_GPIO_36_SMT_LEN  (1U)
+#define GLB_REG_GPIO_36_SMT_MSK  (((1U << GLB_REG_GPIO_36_SMT_LEN) - 1) << GLB_REG_GPIO_36_SMT_POS)
+#define GLB_REG_GPIO_36_SMT_UMSK (~(((1U << GLB_REG_GPIO_36_SMT_LEN) - 1) << GLB_REG_GPIO_36_SMT_POS))
+#define GLB_REG_GPIO_36_DRV      GLB_REG_GPIO_36_DRV
+#define GLB_REG_GPIO_36_DRV_POS  (2U)
+#define GLB_REG_GPIO_36_DRV_LEN  (2U)
+#define GLB_REG_GPIO_36_DRV_MSK  (((1U << GLB_REG_GPIO_36_DRV_LEN) - 1) << GLB_REG_GPIO_36_DRV_POS)
+#define GLB_REG_GPIO_36_DRV_UMSK (~(((1U << GLB_REG_GPIO_36_DRV_LEN) - 1) << GLB_REG_GPIO_36_DRV_POS))
+#define GLB_REG_GPIO_36_PU       GLB_REG_GPIO_36_PU
+#define GLB_REG_GPIO_36_PU_POS   (4U)
+#define GLB_REG_GPIO_36_PU_LEN   (1U)
+#define GLB_REG_GPIO_36_PU_MSK   (((1U << GLB_REG_GPIO_36_PU_LEN) - 1) << GLB_REG_GPIO_36_PU_POS)
+#define GLB_REG_GPIO_36_PU_UMSK  (~(((1U << GLB_REG_GPIO_36_PU_LEN) - 1) << GLB_REG_GPIO_36_PU_POS))
+#define GLB_REG_GPIO_36_PD       GLB_REG_GPIO_36_PD
+#define GLB_REG_GPIO_36_PD_POS   (5U)
+#define GLB_REG_GPIO_36_PD_LEN   (1U)
+#define GLB_REG_GPIO_36_PD_MSK   (((1U << GLB_REG_GPIO_36_PD_LEN) - 1) << GLB_REG_GPIO_36_PD_POS)
+#define GLB_REG_GPIO_36_PD_UMSK  (~(((1U << GLB_REG_GPIO_36_PD_LEN) - 1) << GLB_REG_GPIO_36_PD_POS))
+#define GLB_REG_GPIO_37_IE       GLB_REG_GPIO_37_IE
+#define GLB_REG_GPIO_37_IE_POS   (16U)
+#define GLB_REG_GPIO_37_IE_LEN   (1U)
+#define GLB_REG_GPIO_37_IE_MSK   (((1U << GLB_REG_GPIO_37_IE_LEN) - 1) << GLB_REG_GPIO_37_IE_POS)
+#define GLB_REG_GPIO_37_IE_UMSK  (~(((1U << GLB_REG_GPIO_37_IE_LEN) - 1) << GLB_REG_GPIO_37_IE_POS))
+#define GLB_REG_GPIO_37_SMT      GLB_REG_GPIO_37_SMT
+#define GLB_REG_GPIO_37_SMT_POS  (17U)
+#define GLB_REG_GPIO_37_SMT_LEN  (1U)
+#define GLB_REG_GPIO_37_SMT_MSK  (((1U << GLB_REG_GPIO_37_SMT_LEN) - 1) << GLB_REG_GPIO_37_SMT_POS)
+#define GLB_REG_GPIO_37_SMT_UMSK (~(((1U << GLB_REG_GPIO_37_SMT_LEN) - 1) << GLB_REG_GPIO_37_SMT_POS))
+#define GLB_REG_GPIO_37_DRV      GLB_REG_GPIO_37_DRV
+#define GLB_REG_GPIO_37_DRV_POS  (18U)
+#define GLB_REG_GPIO_37_DRV_LEN  (2U)
+#define GLB_REG_GPIO_37_DRV_MSK  (((1U << GLB_REG_GPIO_37_DRV_LEN) - 1) << GLB_REG_GPIO_37_DRV_POS)
+#define GLB_REG_GPIO_37_DRV_UMSK (~(((1U << GLB_REG_GPIO_37_DRV_LEN) - 1) << GLB_REG_GPIO_37_DRV_POS))
+#define GLB_REG_GPIO_37_PU       GLB_REG_GPIO_37_PU
+#define GLB_REG_GPIO_37_PU_POS   (20U)
+#define GLB_REG_GPIO_37_PU_LEN   (1U)
+#define GLB_REG_GPIO_37_PU_MSK   (((1U << GLB_REG_GPIO_37_PU_LEN) - 1) << GLB_REG_GPIO_37_PU_POS)
+#define GLB_REG_GPIO_37_PU_UMSK  (~(((1U << GLB_REG_GPIO_37_PU_LEN) - 1) << GLB_REG_GPIO_37_PU_POS))
+#define GLB_REG_GPIO_37_PD       GLB_REG_GPIO_37_PD
+#define GLB_REG_GPIO_37_PD_POS   (21U)
+#define GLB_REG_GPIO_37_PD_LEN   (1U)
+#define GLB_REG_GPIO_37_PD_MSK   (((1U << GLB_REG_GPIO_37_PD_LEN) - 1) << GLB_REG_GPIO_37_PD_POS)
+#define GLB_REG_GPIO_37_PD_UMSK  (~(((1U << GLB_REG_GPIO_37_PD_LEN) - 1) << GLB_REG_GPIO_37_PD_POS))
+
+/* 0x180 : GPIO_CFGCTL30 */
+#define GLB_GPIO_CFGCTL30_OFFSET (0x180)
+#define GLB_REG_GPIO_0_I         GLB_REG_GPIO_0_I
+#define GLB_REG_GPIO_0_I_POS     (0U)
+#define GLB_REG_GPIO_0_I_LEN     (1U)
+#define GLB_REG_GPIO_0_I_MSK     (((1U << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS)
+#define GLB_REG_GPIO_0_I_UMSK    (~(((1U << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS))
+#define GLB_REG_GPIO_1_I         GLB_REG_GPIO_1_I
+#define GLB_REG_GPIO_1_I_POS     (1U)
+#define GLB_REG_GPIO_1_I_LEN     (1U)
+#define GLB_REG_GPIO_1_I_MSK     (((1U << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS)
+#define GLB_REG_GPIO_1_I_UMSK    (~(((1U << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS))
+#define GLB_REG_GPIO_2_I         GLB_REG_GPIO_2_I
+#define GLB_REG_GPIO_2_I_POS     (2U)
+#define GLB_REG_GPIO_2_I_LEN     (1U)
+#define GLB_REG_GPIO_2_I_MSK     (((1U << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS)
+#define GLB_REG_GPIO_2_I_UMSK    (~(((1U << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS))
+#define GLB_REG_GPIO_3_I         GLB_REG_GPIO_3_I
+#define GLB_REG_GPIO_3_I_POS     (3U)
+#define GLB_REG_GPIO_3_I_LEN     (1U)
+#define GLB_REG_GPIO_3_I_MSK     (((1U << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS)
+#define GLB_REG_GPIO_3_I_UMSK    (~(((1U << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS))
+#define GLB_REG_GPIO_4_I         GLB_REG_GPIO_4_I
+#define GLB_REG_GPIO_4_I_POS     (4U)
+#define GLB_REG_GPIO_4_I_LEN     (1U)
+#define GLB_REG_GPIO_4_I_MSK     (((1U << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS)
+#define GLB_REG_GPIO_4_I_UMSK    (~(((1U << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS))
+#define GLB_REG_GPIO_5_I         GLB_REG_GPIO_5_I
+#define GLB_REG_GPIO_5_I_POS     (5U)
+#define GLB_REG_GPIO_5_I_LEN     (1U)
+#define GLB_REG_GPIO_5_I_MSK     (((1U << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS)
+#define GLB_REG_GPIO_5_I_UMSK    (~(((1U << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS))
+#define GLB_REG_GPIO_6_I         GLB_REG_GPIO_6_I
+#define GLB_REG_GPIO_6_I_POS     (6U)
+#define GLB_REG_GPIO_6_I_LEN     (1U)
+#define GLB_REG_GPIO_6_I_MSK     (((1U << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS)
+#define GLB_REG_GPIO_6_I_UMSK    (~(((1U << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS))
+#define GLB_REG_GPIO_7_I         GLB_REG_GPIO_7_I
+#define GLB_REG_GPIO_7_I_POS     (7U)
+#define GLB_REG_GPIO_7_I_LEN     (1U)
+#define GLB_REG_GPIO_7_I_MSK     (((1U << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS)
+#define GLB_REG_GPIO_7_I_UMSK    (~(((1U << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS))
+#define GLB_REG_GPIO_8_I         GLB_REG_GPIO_8_I
+#define GLB_REG_GPIO_8_I_POS     (8U)
+#define GLB_REG_GPIO_8_I_LEN     (1U)
+#define GLB_REG_GPIO_8_I_MSK     (((1U << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS)
+#define GLB_REG_GPIO_8_I_UMSK    (~(((1U << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS))
+#define GLB_REG_GPIO_9_I         GLB_REG_GPIO_9_I
+#define GLB_REG_GPIO_9_I_POS     (9U)
+#define GLB_REG_GPIO_9_I_LEN     (1U)
+#define GLB_REG_GPIO_9_I_MSK     (((1U << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS)
+#define GLB_REG_GPIO_9_I_UMSK    (~(((1U << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS))
+#define GLB_REG_GPIO_10_I        GLB_REG_GPIO_10_I
+#define GLB_REG_GPIO_10_I_POS    (10U)
+#define GLB_REG_GPIO_10_I_LEN    (1U)
+#define GLB_REG_GPIO_10_I_MSK    (((1U << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS)
+#define GLB_REG_GPIO_10_I_UMSK   (~(((1U << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS))
+#define GLB_REG_GPIO_11_I        GLB_REG_GPIO_11_I
+#define GLB_REG_GPIO_11_I_POS    (11U)
+#define GLB_REG_GPIO_11_I_LEN    (1U)
+#define GLB_REG_GPIO_11_I_MSK    (((1U << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS)
+#define GLB_REG_GPIO_11_I_UMSK   (~(((1U << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS))
+#define GLB_REG_GPIO_12_I        GLB_REG_GPIO_12_I
+#define GLB_REG_GPIO_12_I_POS    (12U)
+#define GLB_REG_GPIO_12_I_LEN    (1U)
+#define GLB_REG_GPIO_12_I_MSK    (((1U << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS)
+#define GLB_REG_GPIO_12_I_UMSK   (~(((1U << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS))
+#define GLB_REG_GPIO_13_I        GLB_REG_GPIO_13_I
+#define GLB_REG_GPIO_13_I_POS    (13U)
+#define GLB_REG_GPIO_13_I_LEN    (1U)
+#define GLB_REG_GPIO_13_I_MSK    (((1U << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS)
+#define GLB_REG_GPIO_13_I_UMSK   (~(((1U << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS))
+#define GLB_REG_GPIO_14_I        GLB_REG_GPIO_14_I
+#define GLB_REG_GPIO_14_I_POS    (14U)
+#define GLB_REG_GPIO_14_I_LEN    (1U)
+#define GLB_REG_GPIO_14_I_MSK    (((1U << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS)
+#define GLB_REG_GPIO_14_I_UMSK   (~(((1U << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS))
+#define GLB_REG_GPIO_15_I        GLB_REG_GPIO_15_I
+#define GLB_REG_GPIO_15_I_POS    (15U)
+#define GLB_REG_GPIO_15_I_LEN    (1U)
+#define GLB_REG_GPIO_15_I_MSK    (((1U << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS)
+#define GLB_REG_GPIO_15_I_UMSK   (~(((1U << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS))
+#define GLB_REG_GPIO_16_I        GLB_REG_GPIO_16_I
+#define GLB_REG_GPIO_16_I_POS    (16U)
+#define GLB_REG_GPIO_16_I_LEN    (1U)
+#define GLB_REG_GPIO_16_I_MSK    (((1U << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS)
+#define GLB_REG_GPIO_16_I_UMSK   (~(((1U << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS))
+#define GLB_REG_GPIO_17_I        GLB_REG_GPIO_17_I
+#define GLB_REG_GPIO_17_I_POS    (17U)
+#define GLB_REG_GPIO_17_I_LEN    (1U)
+#define GLB_REG_GPIO_17_I_MSK    (((1U << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS)
+#define GLB_REG_GPIO_17_I_UMSK   (~(((1U << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS))
+#define GLB_REG_GPIO_18_I        GLB_REG_GPIO_18_I
+#define GLB_REG_GPIO_18_I_POS    (18U)
+#define GLB_REG_GPIO_18_I_LEN    (1U)
+#define GLB_REG_GPIO_18_I_MSK    (((1U << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS)
+#define GLB_REG_GPIO_18_I_UMSK   (~(((1U << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS))
+#define GLB_REG_GPIO_19_I        GLB_REG_GPIO_19_I
+#define GLB_REG_GPIO_19_I_POS    (19U)
+#define GLB_REG_GPIO_19_I_LEN    (1U)
+#define GLB_REG_GPIO_19_I_MSK    (((1U << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS)
+#define GLB_REG_GPIO_19_I_UMSK   (~(((1U << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS))
+#define GLB_REG_GPIO_20_I        GLB_REG_GPIO_20_I
+#define GLB_REG_GPIO_20_I_POS    (20U)
+#define GLB_REG_GPIO_20_I_LEN    (1U)
+#define GLB_REG_GPIO_20_I_MSK    (((1U << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS)
+#define GLB_REG_GPIO_20_I_UMSK   (~(((1U << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS))
+#define GLB_REG_GPIO_21_I        GLB_REG_GPIO_21_I
+#define GLB_REG_GPIO_21_I_POS    (21U)
+#define GLB_REG_GPIO_21_I_LEN    (1U)
+#define GLB_REG_GPIO_21_I_MSK    (((1U << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS)
+#define GLB_REG_GPIO_21_I_UMSK   (~(((1U << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS))
+#define GLB_REG_GPIO_22_I        GLB_REG_GPIO_22_I
+#define GLB_REG_GPIO_22_I_POS    (22U)
+#define GLB_REG_GPIO_22_I_LEN    (1U)
+#define GLB_REG_GPIO_22_I_MSK    (((1U << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS)
+#define GLB_REG_GPIO_22_I_UMSK   (~(((1U << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS))
+#define GLB_REG_GPIO_23_I        GLB_REG_GPIO_23_I
+#define GLB_REG_GPIO_23_I_POS    (23U)
+#define GLB_REG_GPIO_23_I_LEN    (1U)
+#define GLB_REG_GPIO_23_I_MSK    (((1U << GLB_REG_GPIO_23_I_LEN) - 1) << GLB_REG_GPIO_23_I_POS)
+#define GLB_REG_GPIO_23_I_UMSK   (~(((1U << GLB_REG_GPIO_23_I_LEN) - 1) << GLB_REG_GPIO_23_I_POS))
+#define GLB_REG_GPIO_24_I        GLB_REG_GPIO_24_I
+#define GLB_REG_GPIO_24_I_POS    (24U)
+#define GLB_REG_GPIO_24_I_LEN    (1U)
+#define GLB_REG_GPIO_24_I_MSK    (((1U << GLB_REG_GPIO_24_I_LEN) - 1) << GLB_REG_GPIO_24_I_POS)
+#define GLB_REG_GPIO_24_I_UMSK   (~(((1U << GLB_REG_GPIO_24_I_LEN) - 1) << GLB_REG_GPIO_24_I_POS))
+#define GLB_REG_GPIO_25_I        GLB_REG_GPIO_25_I
+#define GLB_REG_GPIO_25_I_POS    (25U)
+#define GLB_REG_GPIO_25_I_LEN    (1U)
+#define GLB_REG_GPIO_25_I_MSK    (((1U << GLB_REG_GPIO_25_I_LEN) - 1) << GLB_REG_GPIO_25_I_POS)
+#define GLB_REG_GPIO_25_I_UMSK   (~(((1U << GLB_REG_GPIO_25_I_LEN) - 1) << GLB_REG_GPIO_25_I_POS))
+#define GLB_REG_GPIO_26_I        GLB_REG_GPIO_26_I
+#define GLB_REG_GPIO_26_I_POS    (26U)
+#define GLB_REG_GPIO_26_I_LEN    (1U)
+#define GLB_REG_GPIO_26_I_MSK    (((1U << GLB_REG_GPIO_26_I_LEN) - 1) << GLB_REG_GPIO_26_I_POS)
+#define GLB_REG_GPIO_26_I_UMSK   (~(((1U << GLB_REG_GPIO_26_I_LEN) - 1) << GLB_REG_GPIO_26_I_POS))
+#define GLB_REG_GPIO_27_I        GLB_REG_GPIO_27_I
+#define GLB_REG_GPIO_27_I_POS    (27U)
+#define GLB_REG_GPIO_27_I_LEN    (1U)
+#define GLB_REG_GPIO_27_I_MSK    (((1U << GLB_REG_GPIO_27_I_LEN) - 1) << GLB_REG_GPIO_27_I_POS)
+#define GLB_REG_GPIO_27_I_UMSK   (~(((1U << GLB_REG_GPIO_27_I_LEN) - 1) << GLB_REG_GPIO_27_I_POS))
+#define GLB_REG_GPIO_28_I        GLB_REG_GPIO_28_I
+#define GLB_REG_GPIO_28_I_POS    (28U)
+#define GLB_REG_GPIO_28_I_LEN    (1U)
+#define GLB_REG_GPIO_28_I_MSK    (((1U << GLB_REG_GPIO_28_I_LEN) - 1) << GLB_REG_GPIO_28_I_POS)
+#define GLB_REG_GPIO_28_I_UMSK   (~(((1U << GLB_REG_GPIO_28_I_LEN) - 1) << GLB_REG_GPIO_28_I_POS))
+#define GLB_REG_GPIO_29_I        GLB_REG_GPIO_29_I
+#define GLB_REG_GPIO_29_I_POS    (29U)
+#define GLB_REG_GPIO_29_I_LEN    (1U)
+#define GLB_REG_GPIO_29_I_MSK    (((1U << GLB_REG_GPIO_29_I_LEN) - 1) << GLB_REG_GPIO_29_I_POS)
+#define GLB_REG_GPIO_29_I_UMSK   (~(((1U << GLB_REG_GPIO_29_I_LEN) - 1) << GLB_REG_GPIO_29_I_POS))
+#define GLB_REG_GPIO_30_I        GLB_REG_GPIO_30_I
+#define GLB_REG_GPIO_30_I_POS    (30U)
+#define GLB_REG_GPIO_30_I_LEN    (1U)
+#define GLB_REG_GPIO_30_I_MSK    (((1U << GLB_REG_GPIO_30_I_LEN) - 1) << GLB_REG_GPIO_30_I_POS)
+#define GLB_REG_GPIO_30_I_UMSK   (~(((1U << GLB_REG_GPIO_30_I_LEN) - 1) << GLB_REG_GPIO_30_I_POS))
+#define GLB_REG_GPIO_31_I        GLB_REG_GPIO_31_I
+#define GLB_REG_GPIO_31_I_POS    (31U)
+#define GLB_REG_GPIO_31_I_LEN    (1U)
+#define GLB_REG_GPIO_31_I_MSK    (((1U << GLB_REG_GPIO_31_I_LEN) - 1) << GLB_REG_GPIO_31_I_POS)
+#define GLB_REG_GPIO_31_I_UMSK   (~(((1U << GLB_REG_GPIO_31_I_LEN) - 1) << GLB_REG_GPIO_31_I_POS))
+
+/* 0x184 : GPIO_CFGCTL31 */
+#define GLB_GPIO_CFGCTL31_OFFSET (0x184)
+
+/* 0x188 : GPIO_CFGCTL32 */
+#define GLB_GPIO_CFGCTL32_OFFSET (0x188)
+#define GLB_REG_GPIO_0_O         GLB_REG_GPIO_0_O
+#define GLB_REG_GPIO_0_O_POS     (0U)
+#define GLB_REG_GPIO_0_O_LEN     (1U)
+#define GLB_REG_GPIO_0_O_MSK     (((1U << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS)
+#define GLB_REG_GPIO_0_O_UMSK    (~(((1U << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS))
+#define GLB_REG_GPIO_1_O         GLB_REG_GPIO_1_O
+#define GLB_REG_GPIO_1_O_POS     (1U)
+#define GLB_REG_GPIO_1_O_LEN     (1U)
+#define GLB_REG_GPIO_1_O_MSK     (((1U << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS)
+#define GLB_REG_GPIO_1_O_UMSK    (~(((1U << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS))
+#define GLB_REG_GPIO_2_O         GLB_REG_GPIO_2_O
+#define GLB_REG_GPIO_2_O_POS     (2U)
+#define GLB_REG_GPIO_2_O_LEN     (1U)
+#define GLB_REG_GPIO_2_O_MSK     (((1U << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS)
+#define GLB_REG_GPIO_2_O_UMSK    (~(((1U << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS))
+#define GLB_REG_GPIO_3_O         GLB_REG_GPIO_3_O
+#define GLB_REG_GPIO_3_O_POS     (3U)
+#define GLB_REG_GPIO_3_O_LEN     (1U)
+#define GLB_REG_GPIO_3_O_MSK     (((1U << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS)
+#define GLB_REG_GPIO_3_O_UMSK    (~(((1U << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS))
+#define GLB_REG_GPIO_4_O         GLB_REG_GPIO_4_O
+#define GLB_REG_GPIO_4_O_POS     (4U)
+#define GLB_REG_GPIO_4_O_LEN     (1U)
+#define GLB_REG_GPIO_4_O_MSK     (((1U << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS)
+#define GLB_REG_GPIO_4_O_UMSK    (~(((1U << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS))
+#define GLB_REG_GPIO_5_O         GLB_REG_GPIO_5_O
+#define GLB_REG_GPIO_5_O_POS     (5U)
+#define GLB_REG_GPIO_5_O_LEN     (1U)
+#define GLB_REG_GPIO_5_O_MSK     (((1U << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS)
+#define GLB_REG_GPIO_5_O_UMSK    (~(((1U << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS))
+#define GLB_REG_GPIO_6_O         GLB_REG_GPIO_6_O
+#define GLB_REG_GPIO_6_O_POS     (6U)
+#define GLB_REG_GPIO_6_O_LEN     (1U)
+#define GLB_REG_GPIO_6_O_MSK     (((1U << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS)
+#define GLB_REG_GPIO_6_O_UMSK    (~(((1U << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS))
+#define GLB_REG_GPIO_7_O         GLB_REG_GPIO_7_O
+#define GLB_REG_GPIO_7_O_POS     (7U)
+#define GLB_REG_GPIO_7_O_LEN     (1U)
+#define GLB_REG_GPIO_7_O_MSK     (((1U << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS)
+#define GLB_REG_GPIO_7_O_UMSK    (~(((1U << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS))
+#define GLB_REG_GPIO_8_O         GLB_REG_GPIO_8_O
+#define GLB_REG_GPIO_8_O_POS     (8U)
+#define GLB_REG_GPIO_8_O_LEN     (1U)
+#define GLB_REG_GPIO_8_O_MSK     (((1U << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS)
+#define GLB_REG_GPIO_8_O_UMSK    (~(((1U << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS))
+#define GLB_REG_GPIO_9_O         GLB_REG_GPIO_9_O
+#define GLB_REG_GPIO_9_O_POS     (9U)
+#define GLB_REG_GPIO_9_O_LEN     (1U)
+#define GLB_REG_GPIO_9_O_MSK     (((1U << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS)
+#define GLB_REG_GPIO_9_O_UMSK    (~(((1U << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS))
+#define GLB_REG_GPIO_10_O        GLB_REG_GPIO_10_O
+#define GLB_REG_GPIO_10_O_POS    (10U)
+#define GLB_REG_GPIO_10_O_LEN    (1U)
+#define GLB_REG_GPIO_10_O_MSK    (((1U << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS)
+#define GLB_REG_GPIO_10_O_UMSK   (~(((1U << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS))
+#define GLB_REG_GPIO_11_O        GLB_REG_GPIO_11_O
+#define GLB_REG_GPIO_11_O_POS    (11U)
+#define GLB_REG_GPIO_11_O_LEN    (1U)
+#define GLB_REG_GPIO_11_O_MSK    (((1U << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS)
+#define GLB_REG_GPIO_11_O_UMSK   (~(((1U << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS))
+#define GLB_REG_GPIO_12_O        GLB_REG_GPIO_12_O
+#define GLB_REG_GPIO_12_O_POS    (12U)
+#define GLB_REG_GPIO_12_O_LEN    (1U)
+#define GLB_REG_GPIO_12_O_MSK    (((1U << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS)
+#define GLB_REG_GPIO_12_O_UMSK   (~(((1U << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS))
+#define GLB_REG_GPIO_13_O        GLB_REG_GPIO_13_O
+#define GLB_REG_GPIO_13_O_POS    (13U)
+#define GLB_REG_GPIO_13_O_LEN    (1U)
+#define GLB_REG_GPIO_13_O_MSK    (((1U << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS)
+#define GLB_REG_GPIO_13_O_UMSK   (~(((1U << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS))
+#define GLB_REG_GPIO_14_O        GLB_REG_GPIO_14_O
+#define GLB_REG_GPIO_14_O_POS    (14U)
+#define GLB_REG_GPIO_14_O_LEN    (1U)
+#define GLB_REG_GPIO_14_O_MSK    (((1U << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS)
+#define GLB_REG_GPIO_14_O_UMSK   (~(((1U << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS))
+#define GLB_REG_GPIO_15_O        GLB_REG_GPIO_15_O
+#define GLB_REG_GPIO_15_O_POS    (15U)
+#define GLB_REG_GPIO_15_O_LEN    (1U)
+#define GLB_REG_GPIO_15_O_MSK    (((1U << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS)
+#define GLB_REG_GPIO_15_O_UMSK   (~(((1U << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS))
+#define GLB_REG_GPIO_16_O        GLB_REG_GPIO_16_O
+#define GLB_REG_GPIO_16_O_POS    (16U)
+#define GLB_REG_GPIO_16_O_LEN    (1U)
+#define GLB_REG_GPIO_16_O_MSK    (((1U << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS)
+#define GLB_REG_GPIO_16_O_UMSK   (~(((1U << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS))
+#define GLB_REG_GPIO_17_O        GLB_REG_GPIO_17_O
+#define GLB_REG_GPIO_17_O_POS    (17U)
+#define GLB_REG_GPIO_17_O_LEN    (1U)
+#define GLB_REG_GPIO_17_O_MSK    (((1U << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS)
+#define GLB_REG_GPIO_17_O_UMSK   (~(((1U << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS))
+#define GLB_REG_GPIO_18_O        GLB_REG_GPIO_18_O
+#define GLB_REG_GPIO_18_O_POS    (18U)
+#define GLB_REG_GPIO_18_O_LEN    (1U)
+#define GLB_REG_GPIO_18_O_MSK    (((1U << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS)
+#define GLB_REG_GPIO_18_O_UMSK   (~(((1U << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS))
+#define GLB_REG_GPIO_19_O        GLB_REG_GPIO_19_O
+#define GLB_REG_GPIO_19_O_POS    (19U)
+#define GLB_REG_GPIO_19_O_LEN    (1U)
+#define GLB_REG_GPIO_19_O_MSK    (((1U << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS)
+#define GLB_REG_GPIO_19_O_UMSK   (~(((1U << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS))
+#define GLB_REG_GPIO_20_O        GLB_REG_GPIO_20_O
+#define GLB_REG_GPIO_20_O_POS    (20U)
+#define GLB_REG_GPIO_20_O_LEN    (1U)
+#define GLB_REG_GPIO_20_O_MSK    (((1U << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS)
+#define GLB_REG_GPIO_20_O_UMSK   (~(((1U << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS))
+#define GLB_REG_GPIO_21_O        GLB_REG_GPIO_21_O
+#define GLB_REG_GPIO_21_O_POS    (21U)
+#define GLB_REG_GPIO_21_O_LEN    (1U)
+#define GLB_REG_GPIO_21_O_MSK    (((1U << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS)
+#define GLB_REG_GPIO_21_O_UMSK   (~(((1U << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS))
+#define GLB_REG_GPIO_22_O        GLB_REG_GPIO_22_O
+#define GLB_REG_GPIO_22_O_POS    (22U)
+#define GLB_REG_GPIO_22_O_LEN    (1U)
+#define GLB_REG_GPIO_22_O_MSK    (((1U << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS)
+#define GLB_REG_GPIO_22_O_UMSK   (~(((1U << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS))
+#define GLB_REG_GPIO_23_O        GLB_REG_GPIO_23_O
+#define GLB_REG_GPIO_23_O_POS    (23U)
+#define GLB_REG_GPIO_23_O_LEN    (1U)
+#define GLB_REG_GPIO_23_O_MSK    (((1U << GLB_REG_GPIO_23_O_LEN) - 1) << GLB_REG_GPIO_23_O_POS)
+#define GLB_REG_GPIO_23_O_UMSK   (~(((1U << GLB_REG_GPIO_23_O_LEN) - 1) << GLB_REG_GPIO_23_O_POS))
+#define GLB_REG_GPIO_24_O        GLB_REG_GPIO_24_O
+#define GLB_REG_GPIO_24_O_POS    (24U)
+#define GLB_REG_GPIO_24_O_LEN    (1U)
+#define GLB_REG_GPIO_24_O_MSK    (((1U << GLB_REG_GPIO_24_O_LEN) - 1) << GLB_REG_GPIO_24_O_POS)
+#define GLB_REG_GPIO_24_O_UMSK   (~(((1U << GLB_REG_GPIO_24_O_LEN) - 1) << GLB_REG_GPIO_24_O_POS))
+#define GLB_REG_GPIO_25_O        GLB_REG_GPIO_25_O
+#define GLB_REG_GPIO_25_O_POS    (25U)
+#define GLB_REG_GPIO_25_O_LEN    (1U)
+#define GLB_REG_GPIO_25_O_MSK    (((1U << GLB_REG_GPIO_25_O_LEN) - 1) << GLB_REG_GPIO_25_O_POS)
+#define GLB_REG_GPIO_25_O_UMSK   (~(((1U << GLB_REG_GPIO_25_O_LEN) - 1) << GLB_REG_GPIO_25_O_POS))
+#define GLB_REG_GPIO_26_O        GLB_REG_GPIO_26_O
+#define GLB_REG_GPIO_26_O_POS    (26U)
+#define GLB_REG_GPIO_26_O_LEN    (1U)
+#define GLB_REG_GPIO_26_O_MSK    (((1U << GLB_REG_GPIO_26_O_LEN) - 1) << GLB_REG_GPIO_26_O_POS)
+#define GLB_REG_GPIO_26_O_UMSK   (~(((1U << GLB_REG_GPIO_26_O_LEN) - 1) << GLB_REG_GPIO_26_O_POS))
+#define GLB_REG_GPIO_27_O        GLB_REG_GPIO_27_O
+#define GLB_REG_GPIO_27_O_POS    (27U)
+#define GLB_REG_GPIO_27_O_LEN    (1U)
+#define GLB_REG_GPIO_27_O_MSK    (((1U << GLB_REG_GPIO_27_O_LEN) - 1) << GLB_REG_GPIO_27_O_POS)
+#define GLB_REG_GPIO_27_O_UMSK   (~(((1U << GLB_REG_GPIO_27_O_LEN) - 1) << GLB_REG_GPIO_27_O_POS))
+#define GLB_REG_GPIO_28_O        GLB_REG_GPIO_28_O
+#define GLB_REG_GPIO_28_O_POS    (28U)
+#define GLB_REG_GPIO_28_O_LEN    (1U)
+#define GLB_REG_GPIO_28_O_MSK    (((1U << GLB_REG_GPIO_28_O_LEN) - 1) << GLB_REG_GPIO_28_O_POS)
+#define GLB_REG_GPIO_28_O_UMSK   (~(((1U << GLB_REG_GPIO_28_O_LEN) - 1) << GLB_REG_GPIO_28_O_POS))
+#define GLB_REG_GPIO_29_O        GLB_REG_GPIO_29_O
+#define GLB_REG_GPIO_29_O_POS    (29U)
+#define GLB_REG_GPIO_29_O_LEN    (1U)
+#define GLB_REG_GPIO_29_O_MSK    (((1U << GLB_REG_GPIO_29_O_LEN) - 1) << GLB_REG_GPIO_29_O_POS)
+#define GLB_REG_GPIO_29_O_UMSK   (~(((1U << GLB_REG_GPIO_29_O_LEN) - 1) << GLB_REG_GPIO_29_O_POS))
+#define GLB_REG_GPIO_30_O        GLB_REG_GPIO_30_O
+#define GLB_REG_GPIO_30_O_POS    (30U)
+#define GLB_REG_GPIO_30_O_LEN    (1U)
+#define GLB_REG_GPIO_30_O_MSK    (((1U << GLB_REG_GPIO_30_O_LEN) - 1) << GLB_REG_GPIO_30_O_POS)
+#define GLB_REG_GPIO_30_O_UMSK   (~(((1U << GLB_REG_GPIO_30_O_LEN) - 1) << GLB_REG_GPIO_30_O_POS))
+#define GLB_REG_GPIO_31_O        GLB_REG_GPIO_31_O
+#define GLB_REG_GPIO_31_O_POS    (31U)
+#define GLB_REG_GPIO_31_O_LEN    (1U)
+#define GLB_REG_GPIO_31_O_MSK    (((1U << GLB_REG_GPIO_31_O_LEN) - 1) << GLB_REG_GPIO_31_O_POS)
+#define GLB_REG_GPIO_31_O_UMSK   (~(((1U << GLB_REG_GPIO_31_O_LEN) - 1) << GLB_REG_GPIO_31_O_POS))
+
+/* 0x18C : GPIO_CFGCTL33 */
+#define GLB_GPIO_CFGCTL33_OFFSET (0x18C)
+
+/* 0x190 : GPIO_CFGCTL34 */
+#define GLB_GPIO_CFGCTL34_OFFSET (0x190)
+#define GLB_REG_GPIO_0_OE        GLB_REG_GPIO_0_OE
+#define GLB_REG_GPIO_0_OE_POS    (0U)
+#define GLB_REG_GPIO_0_OE_LEN    (1U)
+#define GLB_REG_GPIO_0_OE_MSK    (((1U << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS)
+#define GLB_REG_GPIO_0_OE_UMSK   (~(((1U << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS))
+#define GLB_REG_GPIO_1_OE        GLB_REG_GPIO_1_OE
+#define GLB_REG_GPIO_1_OE_POS    (1U)
+#define GLB_REG_GPIO_1_OE_LEN    (1U)
+#define GLB_REG_GPIO_1_OE_MSK    (((1U << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS)
+#define GLB_REG_GPIO_1_OE_UMSK   (~(((1U << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS))
+#define GLB_REG_GPIO_2_OE        GLB_REG_GPIO_2_OE
+#define GLB_REG_GPIO_2_OE_POS    (2U)
+#define GLB_REG_GPIO_2_OE_LEN    (1U)
+#define GLB_REG_GPIO_2_OE_MSK    (((1U << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS)
+#define GLB_REG_GPIO_2_OE_UMSK   (~(((1U << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS))
+#define GLB_REG_GPIO_3_OE        GLB_REG_GPIO_3_OE
+#define GLB_REG_GPIO_3_OE_POS    (3U)
+#define GLB_REG_GPIO_3_OE_LEN    (1U)
+#define GLB_REG_GPIO_3_OE_MSK    (((1U << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS)
+#define GLB_REG_GPIO_3_OE_UMSK   (~(((1U << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS))
+#define GLB_REG_GPIO_4_OE        GLB_REG_GPIO_4_OE
+#define GLB_REG_GPIO_4_OE_POS    (4U)
+#define GLB_REG_GPIO_4_OE_LEN    (1U)
+#define GLB_REG_GPIO_4_OE_MSK    (((1U << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS)
+#define GLB_REG_GPIO_4_OE_UMSK   (~(((1U << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS))
+#define GLB_REG_GPIO_5_OE        GLB_REG_GPIO_5_OE
+#define GLB_REG_GPIO_5_OE_POS    (5U)
+#define GLB_REG_GPIO_5_OE_LEN    (1U)
+#define GLB_REG_GPIO_5_OE_MSK    (((1U << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS)
+#define GLB_REG_GPIO_5_OE_UMSK   (~(((1U << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS))
+#define GLB_REG_GPIO_6_OE        GLB_REG_GPIO_6_OE
+#define GLB_REG_GPIO_6_OE_POS    (6U)
+#define GLB_REG_GPIO_6_OE_LEN    (1U)
+#define GLB_REG_GPIO_6_OE_MSK    (((1U << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS)
+#define GLB_REG_GPIO_6_OE_UMSK   (~(((1U << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS))
+#define GLB_REG_GPIO_7_OE        GLB_REG_GPIO_7_OE
+#define GLB_REG_GPIO_7_OE_POS    (7U)
+#define GLB_REG_GPIO_7_OE_LEN    (1U)
+#define GLB_REG_GPIO_7_OE_MSK    (((1U << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS)
+#define GLB_REG_GPIO_7_OE_UMSK   (~(((1U << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS))
+#define GLB_REG_GPIO_8_OE        GLB_REG_GPIO_8_OE
+#define GLB_REG_GPIO_8_OE_POS    (8U)
+#define GLB_REG_GPIO_8_OE_LEN    (1U)
+#define GLB_REG_GPIO_8_OE_MSK    (((1U << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS)
+#define GLB_REG_GPIO_8_OE_UMSK   (~(((1U << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS))
+#define GLB_REG_GPIO_9_OE        GLB_REG_GPIO_9_OE
+#define GLB_REG_GPIO_9_OE_POS    (9U)
+#define GLB_REG_GPIO_9_OE_LEN    (1U)
+#define GLB_REG_GPIO_9_OE_MSK    (((1U << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS)
+#define GLB_REG_GPIO_9_OE_UMSK   (~(((1U << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS))
+#define GLB_REG_GPIO_10_OE       GLB_REG_GPIO_10_OE
+#define GLB_REG_GPIO_10_OE_POS   (10U)
+#define GLB_REG_GPIO_10_OE_LEN   (1U)
+#define GLB_REG_GPIO_10_OE_MSK   (((1U << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS)
+#define GLB_REG_GPIO_10_OE_UMSK  (~(((1U << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS))
+#define GLB_REG_GPIO_11_OE       GLB_REG_GPIO_11_OE
+#define GLB_REG_GPIO_11_OE_POS   (11U)
+#define GLB_REG_GPIO_11_OE_LEN   (1U)
+#define GLB_REG_GPIO_11_OE_MSK   (((1U << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS)
+#define GLB_REG_GPIO_11_OE_UMSK  (~(((1U << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS))
+#define GLB_REG_GPIO_12_OE       GLB_REG_GPIO_12_OE
+#define GLB_REG_GPIO_12_OE_POS   (12U)
+#define GLB_REG_GPIO_12_OE_LEN   (1U)
+#define GLB_REG_GPIO_12_OE_MSK   (((1U << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS)
+#define GLB_REG_GPIO_12_OE_UMSK  (~(((1U << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS))
+#define GLB_REG_GPIO_13_OE       GLB_REG_GPIO_13_OE
+#define GLB_REG_GPIO_13_OE_POS   (13U)
+#define GLB_REG_GPIO_13_OE_LEN   (1U)
+#define GLB_REG_GPIO_13_OE_MSK   (((1U << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS)
+#define GLB_REG_GPIO_13_OE_UMSK  (~(((1U << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS))
+#define GLB_REG_GPIO_14_OE       GLB_REG_GPIO_14_OE
+#define GLB_REG_GPIO_14_OE_POS   (14U)
+#define GLB_REG_GPIO_14_OE_LEN   (1U)
+#define GLB_REG_GPIO_14_OE_MSK   (((1U << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS)
+#define GLB_REG_GPIO_14_OE_UMSK  (~(((1U << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS))
+#define GLB_REG_GPIO_15_OE       GLB_REG_GPIO_15_OE
+#define GLB_REG_GPIO_15_OE_POS   (15U)
+#define GLB_REG_GPIO_15_OE_LEN   (1U)
+#define GLB_REG_GPIO_15_OE_MSK   (((1U << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS)
+#define GLB_REG_GPIO_15_OE_UMSK  (~(((1U << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS))
+#define GLB_REG_GPIO_16_OE       GLB_REG_GPIO_16_OE
+#define GLB_REG_GPIO_16_OE_POS   (16U)
+#define GLB_REG_GPIO_16_OE_LEN   (1U)
+#define GLB_REG_GPIO_16_OE_MSK   (((1U << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS)
+#define GLB_REG_GPIO_16_OE_UMSK  (~(((1U << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS))
+#define GLB_REG_GPIO_17_OE       GLB_REG_GPIO_17_OE
+#define GLB_REG_GPIO_17_OE_POS   (17U)
+#define GLB_REG_GPIO_17_OE_LEN   (1U)
+#define GLB_REG_GPIO_17_OE_MSK   (((1U << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS)
+#define GLB_REG_GPIO_17_OE_UMSK  (~(((1U << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS))
+#define GLB_REG_GPIO_18_OE       GLB_REG_GPIO_18_OE
+#define GLB_REG_GPIO_18_OE_POS   (18U)
+#define GLB_REG_GPIO_18_OE_LEN   (1U)
+#define GLB_REG_GPIO_18_OE_MSK   (((1U << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS)
+#define GLB_REG_GPIO_18_OE_UMSK  (~(((1U << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS))
+#define GLB_REG_GPIO_19_OE       GLB_REG_GPIO_19_OE
+#define GLB_REG_GPIO_19_OE_POS   (19U)
+#define GLB_REG_GPIO_19_OE_LEN   (1U)
+#define GLB_REG_GPIO_19_OE_MSK   (((1U << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS)
+#define GLB_REG_GPIO_19_OE_UMSK  (~(((1U << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS))
+#define GLB_REG_GPIO_20_OE       GLB_REG_GPIO_20_OE
+#define GLB_REG_GPIO_20_OE_POS   (20U)
+#define GLB_REG_GPIO_20_OE_LEN   (1U)
+#define GLB_REG_GPIO_20_OE_MSK   (((1U << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS)
+#define GLB_REG_GPIO_20_OE_UMSK  (~(((1U << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS))
+#define GLB_REG_GPIO_21_OE       GLB_REG_GPIO_21_OE
+#define GLB_REG_GPIO_21_OE_POS   (21U)
+#define GLB_REG_GPIO_21_OE_LEN   (1U)
+#define GLB_REG_GPIO_21_OE_MSK   (((1U << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS)
+#define GLB_REG_GPIO_21_OE_UMSK  (~(((1U << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS))
+#define GLB_REG_GPIO_22_OE       GLB_REG_GPIO_22_OE
+#define GLB_REG_GPIO_22_OE_POS   (22U)
+#define GLB_REG_GPIO_22_OE_LEN   (1U)
+#define GLB_REG_GPIO_22_OE_MSK   (((1U << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS)
+#define GLB_REG_GPIO_22_OE_UMSK  (~(((1U << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS))
+#define GLB_REG_GPIO_23_OE       GLB_REG_GPIO_23_OE
+#define GLB_REG_GPIO_23_OE_POS   (23U)
+#define GLB_REG_GPIO_23_OE_LEN   (1U)
+#define GLB_REG_GPIO_23_OE_MSK   (((1U << GLB_REG_GPIO_23_OE_LEN) - 1) << GLB_REG_GPIO_23_OE_POS)
+#define GLB_REG_GPIO_23_OE_UMSK  (~(((1U << GLB_REG_GPIO_23_OE_LEN) - 1) << GLB_REG_GPIO_23_OE_POS))
+#define GLB_REG_GPIO_24_OE       GLB_REG_GPIO_24_OE
+#define GLB_REG_GPIO_24_OE_POS   (24U)
+#define GLB_REG_GPIO_24_OE_LEN   (1U)
+#define GLB_REG_GPIO_24_OE_MSK   (((1U << GLB_REG_GPIO_24_OE_LEN) - 1) << GLB_REG_GPIO_24_OE_POS)
+#define GLB_REG_GPIO_24_OE_UMSK  (~(((1U << GLB_REG_GPIO_24_OE_LEN) - 1) << GLB_REG_GPIO_24_OE_POS))
+#define GLB_REG_GPIO_25_OE       GLB_REG_GPIO_25_OE
+#define GLB_REG_GPIO_25_OE_POS   (25U)
+#define GLB_REG_GPIO_25_OE_LEN   (1U)
+#define GLB_REG_GPIO_25_OE_MSK   (((1U << GLB_REG_GPIO_25_OE_LEN) - 1) << GLB_REG_GPIO_25_OE_POS)
+#define GLB_REG_GPIO_25_OE_UMSK  (~(((1U << GLB_REG_GPIO_25_OE_LEN) - 1) << GLB_REG_GPIO_25_OE_POS))
+#define GLB_REG_GPIO_26_OE       GLB_REG_GPIO_26_OE
+#define GLB_REG_GPIO_26_OE_POS   (26U)
+#define GLB_REG_GPIO_26_OE_LEN   (1U)
+#define GLB_REG_GPIO_26_OE_MSK   (((1U << GLB_REG_GPIO_26_OE_LEN) - 1) << GLB_REG_GPIO_26_OE_POS)
+#define GLB_REG_GPIO_26_OE_UMSK  (~(((1U << GLB_REG_GPIO_26_OE_LEN) - 1) << GLB_REG_GPIO_26_OE_POS))
+#define GLB_REG_GPIO_27_OE       GLB_REG_GPIO_27_OE
+#define GLB_REG_GPIO_27_OE_POS   (27U)
+#define GLB_REG_GPIO_27_OE_LEN   (1U)
+#define GLB_REG_GPIO_27_OE_MSK   (((1U << GLB_REG_GPIO_27_OE_LEN) - 1) << GLB_REG_GPIO_27_OE_POS)
+#define GLB_REG_GPIO_27_OE_UMSK  (~(((1U << GLB_REG_GPIO_27_OE_LEN) - 1) << GLB_REG_GPIO_27_OE_POS))
+#define GLB_REG_GPIO_28_OE       GLB_REG_GPIO_28_OE
+#define GLB_REG_GPIO_28_OE_POS   (28U)
+#define GLB_REG_GPIO_28_OE_LEN   (1U)
+#define GLB_REG_GPIO_28_OE_MSK   (((1U << GLB_REG_GPIO_28_OE_LEN) - 1) << GLB_REG_GPIO_28_OE_POS)
+#define GLB_REG_GPIO_28_OE_UMSK  (~(((1U << GLB_REG_GPIO_28_OE_LEN) - 1) << GLB_REG_GPIO_28_OE_POS))
+#define GLB_REG_GPIO_29_OE       GLB_REG_GPIO_29_OE
+#define GLB_REG_GPIO_29_OE_POS   (29U)
+#define GLB_REG_GPIO_29_OE_LEN   (1U)
+#define GLB_REG_GPIO_29_OE_MSK   (((1U << GLB_REG_GPIO_29_OE_LEN) - 1) << GLB_REG_GPIO_29_OE_POS)
+#define GLB_REG_GPIO_29_OE_UMSK  (~(((1U << GLB_REG_GPIO_29_OE_LEN) - 1) << GLB_REG_GPIO_29_OE_POS))
+#define GLB_REG_GPIO_30_OE       GLB_REG_GPIO_30_OE
+#define GLB_REG_GPIO_30_OE_POS   (30U)
+#define GLB_REG_GPIO_30_OE_LEN   (1U)
+#define GLB_REG_GPIO_30_OE_MSK   (((1U << GLB_REG_GPIO_30_OE_LEN) - 1) << GLB_REG_GPIO_30_OE_POS)
+#define GLB_REG_GPIO_30_OE_UMSK  (~(((1U << GLB_REG_GPIO_30_OE_LEN) - 1) << GLB_REG_GPIO_30_OE_POS))
+#define GLB_REG_GPIO_31_OE       GLB_REG_GPIO_31_OE
+#define GLB_REG_GPIO_31_OE_POS   (31U)
+#define GLB_REG_GPIO_31_OE_LEN   (1U)
+#define GLB_REG_GPIO_31_OE_MSK   (((1U << GLB_REG_GPIO_31_OE_LEN) - 1) << GLB_REG_GPIO_31_OE_POS)
+#define GLB_REG_GPIO_31_OE_UMSK  (~(((1U << GLB_REG_GPIO_31_OE_LEN) - 1) << GLB_REG_GPIO_31_OE_POS))
+
+/* 0x194 : GPIO_CFGCTL35 */
+#define GLB_GPIO_CFGCTL35_OFFSET (0x194)
+
+/* 0x1A0 : GPIO_INT_MASK1 */
+#define GLB_GPIO_INT_MASK1_OFFSET   (0x1A0)
+#define GLB_REG_GPIO_INT_MASK1      GLB_REG_GPIO_INT_MASK1
+#define GLB_REG_GPIO_INT_MASK1_POS  (0U)
+#define GLB_REG_GPIO_INT_MASK1_LEN  (32U)
+#define GLB_REG_GPIO_INT_MASK1_MSK  (((1U << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS)
+#define GLB_REG_GPIO_INT_MASK1_UMSK (~(((1U << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS))
+
+/* 0x1A8 : GPIO_INT_STAT1 */
+#define GLB_GPIO_INT_STAT1_OFFSET (0x1A8)
+#define GLB_GPIO_INT_STAT1        GLB_GPIO_INT_STAT1
+#define GLB_GPIO_INT_STAT1_POS    (0U)
+#define GLB_GPIO_INT_STAT1_LEN    (32U)
+#define GLB_GPIO_INT_STAT1_MSK    (((1U << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS)
+#define GLB_GPIO_INT_STAT1_UMSK   (~(((1U << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS))
+
+/* 0x1B0 : GPIO_INT_CLR1 */
+#define GLB_GPIO_INT_CLR1_OFFSET   (0x1B0)
+#define GLB_REG_GPIO_INT_CLR1      GLB_REG_GPIO_INT_CLR1
+#define GLB_REG_GPIO_INT_CLR1_POS  (0U)
+#define GLB_REG_GPIO_INT_CLR1_LEN  (32U)
+#define GLB_REG_GPIO_INT_CLR1_MSK  (((1U << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS)
+#define GLB_REG_GPIO_INT_CLR1_UMSK (~(((1U << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS))
+
+/* 0x1C0 : GPIO_INT_MODE_SET1 */
+#define GLB_GPIO_INT_MODE_SET1_OFFSET   (0x1C0)
+#define GLB_REG_GPIO_INT_MODE_SET1      GLB_REG_GPIO_INT_MODE_SET1
+#define GLB_REG_GPIO_INT_MODE_SET1_POS  (0U)
+#define GLB_REG_GPIO_INT_MODE_SET1_LEN  (30U)
+#define GLB_REG_GPIO_INT_MODE_SET1_MSK  (((1U << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET1_POS)
+#define GLB_REG_GPIO_INT_MODE_SET1_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET1_POS))
+
+/* 0x1C4 : GPIO_INT_MODE_SET2 */
+#define GLB_GPIO_INT_MODE_SET2_OFFSET   (0x1C4)
+#define GLB_REG_GPIO_INT_MODE_SET2      GLB_REG_GPIO_INT_MODE_SET2
+#define GLB_REG_GPIO_INT_MODE_SET2_POS  (0U)
+#define GLB_REG_GPIO_INT_MODE_SET2_LEN  (30U)
+#define GLB_REG_GPIO_INT_MODE_SET2_MSK  (((1U << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET2_POS)
+#define GLB_REG_GPIO_INT_MODE_SET2_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET2_POS))
+
+/* 0x1C8 : GPIO_INT_MODE_SET3 */
+#define GLB_GPIO_INT_MODE_SET3_OFFSET   (0x1C8)
+#define GLB_REG_GPIO_INT_MODE_SET3      GLB_REG_GPIO_INT_MODE_SET3
+#define GLB_REG_GPIO_INT_MODE_SET3_POS  (0U)
+#define GLB_REG_GPIO_INT_MODE_SET3_LEN  (30U)
+#define GLB_REG_GPIO_INT_MODE_SET3_MSK  (((1U << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET3_POS)
+#define GLB_REG_GPIO_INT_MODE_SET3_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET3_POS))
+
+/* 0x1CC : GPIO_INT_MODE_SET4 */
+#define GLB_GPIO_INT_MODE_SET4_OFFSET   (0x1CC)
+#define GLB_REG_GPIO_INT_MODE_SET4      GLB_REG_GPIO_INT_MODE_SET4
+#define GLB_REG_GPIO_INT_MODE_SET4_POS  (0U)
+#define GLB_REG_GPIO_INT_MODE_SET4_LEN  (6U)
+#define GLB_REG_GPIO_INT_MODE_SET4_MSK  (((1U << GLB_REG_GPIO_INT_MODE_SET4_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET4_POS)
+#define GLB_REG_GPIO_INT_MODE_SET4_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET4_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET4_POS))
+
+/* 0x1D0 : GPIO_INT2_MASK1 */
+#define GLB_GPIO_INT2_MASK1_OFFSET   (0x1D0)
+#define GLB_REG_GPIO_INT2_MASK1      GLB_REG_GPIO_INT2_MASK1
+#define GLB_REG_GPIO_INT2_MASK1_POS  (0U)
+#define GLB_REG_GPIO_INT2_MASK1_LEN  (32U)
+#define GLB_REG_GPIO_INT2_MASK1_MSK  (((1U << GLB_REG_GPIO_INT2_MASK1_LEN) - 1) << GLB_REG_GPIO_INT2_MASK1_POS)
+#define GLB_REG_GPIO_INT2_MASK1_UMSK (~(((1U << GLB_REG_GPIO_INT2_MASK1_LEN) - 1) << GLB_REG_GPIO_INT2_MASK1_POS))
+
+/* 0x1D4 : GPIO_INT2_STAT1 */
+#define GLB_GPIO_INT2_STAT1_OFFSET (0x1D4)
+#define GLB_GPIO_INT2_STAT1        GLB_GPIO_INT2_STAT1
+#define GLB_GPIO_INT2_STAT1_POS    (0U)
+#define GLB_GPIO_INT2_STAT1_LEN    (32U)
+#define GLB_GPIO_INT2_STAT1_MSK    (((1U << GLB_GPIO_INT2_STAT1_LEN) - 1) << GLB_GPIO_INT2_STAT1_POS)
+#define GLB_GPIO_INT2_STAT1_UMSK   (~(((1U << GLB_GPIO_INT2_STAT1_LEN) - 1) << GLB_GPIO_INT2_STAT1_POS))
+
+/* 0x1D8 : GPIO_INT2_CLR1 */
+#define GLB_GPIO_INT2_CLR1_OFFSET   (0x1D8)
+#define GLB_REG_GPIO_INT2_CLR1      GLB_REG_GPIO_INT2_CLR1
+#define GLB_REG_GPIO_INT2_CLR1_POS  (0U)
+#define GLB_REG_GPIO_INT2_CLR1_LEN  (32U)
+#define GLB_REG_GPIO_INT2_CLR1_MSK  (((1U << GLB_REG_GPIO_INT2_CLR1_LEN) - 1) << GLB_REG_GPIO_INT2_CLR1_POS)
+#define GLB_REG_GPIO_INT2_CLR1_UMSK (~(((1U << GLB_REG_GPIO_INT2_CLR1_LEN) - 1) << GLB_REG_GPIO_INT2_CLR1_POS))
+
+/* 0x1DC : GPIO_INT2_MODE_SET1 */
+#define GLB_GPIO_INT2_MODE_SET1_OFFSET   (0x1DC)
+#define GLB_REG_GPIO_INT2_MODE_SET1      GLB_REG_GPIO_INT2_MODE_SET1
+#define GLB_REG_GPIO_INT2_MODE_SET1_POS  (0U)
+#define GLB_REG_GPIO_INT2_MODE_SET1_LEN  (30U)
+#define GLB_REG_GPIO_INT2_MODE_SET1_MSK  (((1U << GLB_REG_GPIO_INT2_MODE_SET1_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET1_POS)
+#define GLB_REG_GPIO_INT2_MODE_SET1_UMSK (~(((1U << GLB_REG_GPIO_INT2_MODE_SET1_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET1_POS))
+
+/* 0x1E0 : GPIO_INT2_MODE_SET2 */
+#define GLB_GPIO_INT2_MODE_SET2_OFFSET   (0x1E0)
+#define GLB_REG_GPIO_INT2_MODE_SET2      GLB_REG_GPIO_INT2_MODE_SET2
+#define GLB_REG_GPIO_INT2_MODE_SET2_POS  (0U)
+#define GLB_REG_GPIO_INT2_MODE_SET2_LEN  (30U)
+#define GLB_REG_GPIO_INT2_MODE_SET2_MSK  (((1U << GLB_REG_GPIO_INT2_MODE_SET2_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET2_POS)
+#define GLB_REG_GPIO_INT2_MODE_SET2_UMSK (~(((1U << GLB_REG_GPIO_INT2_MODE_SET2_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET2_POS))
+
+/* 0x1E4 : GPIO_INT2_MODE_SET3 */
+#define GLB_GPIO_INT2_MODE_SET3_OFFSET   (0x1E4)
+#define GLB_REG_GPIO_INT2_MODE_SET3      GLB_REG_GPIO_INT2_MODE_SET3
+#define GLB_REG_GPIO_INT2_MODE_SET3_POS  (0U)
+#define GLB_REG_GPIO_INT2_MODE_SET3_LEN  (30U)
+#define GLB_REG_GPIO_INT2_MODE_SET3_MSK  (((1U << GLB_REG_GPIO_INT2_MODE_SET3_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET3_POS)
+#define GLB_REG_GPIO_INT2_MODE_SET3_UMSK (~(((1U << GLB_REG_GPIO_INT2_MODE_SET3_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET3_POS))
+
+/* 0x1E8 : GPIO_INT2_MODE_SET4 */
+#define GLB_GPIO_INT2_MODE_SET4_OFFSET   (0x1E8)
+#define GLB_REG_GPIO_INT2_MODE_SET4      GLB_REG_GPIO_INT2_MODE_SET4
+#define GLB_REG_GPIO_INT2_MODE_SET4_POS  (0U)
+#define GLB_REG_GPIO_INT2_MODE_SET4_LEN  (6U)
+#define GLB_REG_GPIO_INT2_MODE_SET4_MSK  (((1U << GLB_REG_GPIO_INT2_MODE_SET4_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET4_POS)
+#define GLB_REG_GPIO_INT2_MODE_SET4_UMSK (~(((1U << GLB_REG_GPIO_INT2_MODE_SET4_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET4_POS))
+
+/* 0x200 : dll */
+#define GLB_DLL_OFFSET               (0x200)
+#define GLB_DTEST_EN_DLL_REFCLK      GLB_DTEST_EN_DLL_REFCLK
+#define GLB_DTEST_EN_DLL_REFCLK_POS  (0U)
+#define GLB_DTEST_EN_DLL_REFCLK_LEN  (1U)
+#define GLB_DTEST_EN_DLL_REFCLK_MSK  (((1U << GLB_DTEST_EN_DLL_REFCLK_LEN) - 1) << GLB_DTEST_EN_DLL_REFCLK_POS)
+#define GLB_DTEST_EN_DLL_REFCLK_UMSK (~(((1U << GLB_DTEST_EN_DLL_REFCLK_LEN) - 1) << GLB_DTEST_EN_DLL_REFCLK_POS))
+#define GLB_DTEST_EN_DLL_OUTCLK      GLB_DTEST_EN_DLL_OUTCLK
+#define GLB_DTEST_EN_DLL_OUTCLK_POS  (1U)
+#define GLB_DTEST_EN_DLL_OUTCLK_LEN  (1U)
+#define GLB_DTEST_EN_DLL_OUTCLK_MSK  (((1U << GLB_DTEST_EN_DLL_OUTCLK_LEN) - 1) << GLB_DTEST_EN_DLL_OUTCLK_POS)
+#define GLB_DTEST_EN_DLL_OUTCLK_UMSK (~(((1U << GLB_DTEST_EN_DLL_OUTCLK_LEN) - 1) << GLB_DTEST_EN_DLL_OUTCLK_POS))
+#define GLB_TEN_DLL                  GLB_TEN_DLL
+#define GLB_TEN_DLL_POS              (2U)
+#define GLB_TEN_DLL_LEN              (1U)
+#define GLB_TEN_DLL_MSK              (((1U << GLB_TEN_DLL_LEN) - 1) << GLB_TEN_DLL_POS)
+#define GLB_TEN_DLL_UMSK             (~(((1U << GLB_TEN_DLL_LEN) - 1) << GLB_TEN_DLL_POS))
+#define GLB_DLL_CLK_MMDIV_EN         GLB_DLL_CLK_MMDIV_EN
+#define GLB_DLL_CLK_MMDIV_EN_POS     (3U)
+#define GLB_DLL_CLK_MMDIV_EN_LEN     (1U)
+#define GLB_DLL_CLK_MMDIV_EN_MSK     (((1U << GLB_DLL_CLK_MMDIV_EN_LEN) - 1) << GLB_DLL_CLK_MMDIV_EN_POS)
+#define GLB_DLL_CLK_MMDIV_EN_UMSK    (~(((1U << GLB_DLL_CLK_MMDIV_EN_LEN) - 1) << GLB_DLL_CLK_MMDIV_EN_POS))
+#define GLB_DLL_CLK_288M_EN          GLB_DLL_CLK_288M_EN
+#define GLB_DLL_CLK_288M_EN_POS      (4U)
+#define GLB_DLL_CLK_288M_EN_LEN      (1U)
+#define GLB_DLL_CLK_288M_EN_MSK      (((1U << GLB_DLL_CLK_288M_EN_LEN) - 1) << GLB_DLL_CLK_288M_EN_POS)
+#define GLB_DLL_CLK_288M_EN_UMSK     (~(((1U << GLB_DLL_CLK_288M_EN_LEN) - 1) << GLB_DLL_CLK_288M_EN_POS))
+#define GLB_DLL_CLK_144M_EN          GLB_DLL_CLK_144M_EN
+#define GLB_DLL_CLK_144M_EN_POS      (5U)
+#define GLB_DLL_CLK_144M_EN_LEN      (1U)
+#define GLB_DLL_CLK_144M_EN_MSK      (((1U << GLB_DLL_CLK_144M_EN_LEN) - 1) << GLB_DLL_CLK_144M_EN_POS)
+#define GLB_DLL_CLK_144M_EN_UMSK     (~(((1U << GLB_DLL_CLK_144M_EN_LEN) - 1) << GLB_DLL_CLK_144M_EN_POS))
+#define GLB_DLL_CLK_96M_EN           GLB_DLL_CLK_96M_EN
+#define GLB_DLL_CLK_96M_EN_POS       (6U)
+#define GLB_DLL_CLK_96M_EN_LEN       (1U)
+#define GLB_DLL_CLK_96M_EN_MSK       (((1U << GLB_DLL_CLK_96M_EN_LEN) - 1) << GLB_DLL_CLK_96M_EN_POS)
+#define GLB_DLL_CLK_96M_EN_UMSK      (~(((1U << GLB_DLL_CLK_96M_EN_LEN) - 1) << GLB_DLL_CLK_96M_EN_POS))
+#define GLB_DLL_CLK_57P6M_EN         GLB_DLL_CLK_57P6M_EN
+#define GLB_DLL_CLK_57P6M_EN_POS     (7U)
+#define GLB_DLL_CLK_57P6M_EN_LEN     (1U)
+#define GLB_DLL_CLK_57P6M_EN_MSK     (((1U << GLB_DLL_CLK_57P6M_EN_LEN) - 1) << GLB_DLL_CLK_57P6M_EN_POS)
+#define GLB_DLL_CLK_57P6M_EN_UMSK    (~(((1U << GLB_DLL_CLK_57P6M_EN_LEN) - 1) << GLB_DLL_CLK_57P6M_EN_POS))
+#define GLB_DLL_VCTRL_SEL            GLB_DLL_VCTRL_SEL
+#define GLB_DLL_VCTRL_SEL_POS        (8U)
+#define GLB_DLL_VCTRL_SEL_LEN        (3U)
+#define GLB_DLL_VCTRL_SEL_MSK        (((1U << GLB_DLL_VCTRL_SEL_LEN) - 1) << GLB_DLL_VCTRL_SEL_POS)
+#define GLB_DLL_VCTRL_SEL_UMSK       (~(((1U << GLB_DLL_VCTRL_SEL_LEN) - 1) << GLB_DLL_VCTRL_SEL_POS))
+#define GLB_DLL_PRECHG_SEL           GLB_DLL_PRECHG_SEL
+#define GLB_DLL_PRECHG_SEL_POS       (12U)
+#define GLB_DLL_PRECHG_SEL_LEN       (1U)
+#define GLB_DLL_PRECHG_SEL_MSK       (((1U << GLB_DLL_PRECHG_SEL_LEN) - 1) << GLB_DLL_PRECHG_SEL_POS)
+#define GLB_DLL_PRECHG_SEL_UMSK      (~(((1U << GLB_DLL_PRECHG_SEL_LEN) - 1) << GLB_DLL_PRECHG_SEL_POS))
+#define GLB_DLL_PRECHG_REG           GLB_DLL_PRECHG_REG
+#define GLB_DLL_PRECHG_REG_POS       (13U)
+#define GLB_DLL_PRECHG_REG_LEN       (1U)
+#define GLB_DLL_PRECHG_REG_MSK       (((1U << GLB_DLL_PRECHG_REG_LEN) - 1) << GLB_DLL_PRECHG_REG_POS)
+#define GLB_DLL_PRECHG_REG_UMSK      (~(((1U << GLB_DLL_PRECHG_REG_LEN) - 1) << GLB_DLL_PRECHG_REG_POS))
+#define GLB_DLL_PRECHG_EN            GLB_DLL_PRECHG_EN
+#define GLB_DLL_PRECHG_EN_POS        (14U)
+#define GLB_DLL_PRECHG_EN_LEN        (1U)
+#define GLB_DLL_PRECHG_EN_MSK        (((1U << GLB_DLL_PRECHG_EN_LEN) - 1) << GLB_DLL_PRECHG_EN_POS)
+#define GLB_DLL_PRECHG_EN_UMSK       (~(((1U << GLB_DLL_PRECHG_EN_LEN) - 1) << GLB_DLL_PRECHG_EN_POS))
+#define GLB_DLL_VCTRL_FORCE_EN       GLB_DLL_VCTRL_FORCE_EN
+#define GLB_DLL_VCTRL_FORCE_EN_POS   (15U)
+#define GLB_DLL_VCTRL_FORCE_EN_LEN   (1U)
+#define GLB_DLL_VCTRL_FORCE_EN_MSK   (((1U << GLB_DLL_VCTRL_FORCE_EN_LEN) - 1) << GLB_DLL_VCTRL_FORCE_EN_POS)
+#define GLB_DLL_VCTRL_FORCE_EN_UMSK  (~(((1U << GLB_DLL_VCTRL_FORCE_EN_LEN) - 1) << GLB_DLL_VCTRL_FORCE_EN_POS))
+#define GLB_DLL_POST_DIV             GLB_DLL_POST_DIV
+#define GLB_DLL_POST_DIV_POS         (16U)
+#define GLB_DLL_POST_DIV_LEN         (4U)
+#define GLB_DLL_POST_DIV_MSK         (((1U << GLB_DLL_POST_DIV_LEN) - 1) << GLB_DLL_POST_DIV_POS)
+#define GLB_DLL_POST_DIV_UMSK        (~(((1U << GLB_DLL_POST_DIV_LEN) - 1) << GLB_DLL_POST_DIV_POS))
+#define GLB_DLL_DELAY_SEL            GLB_DLL_DELAY_SEL
+#define GLB_DLL_DELAY_SEL_POS        (20U)
+#define GLB_DLL_DELAY_SEL_LEN        (2U)
+#define GLB_DLL_DELAY_SEL_MSK        (((1U << GLB_DLL_DELAY_SEL_LEN) - 1) << GLB_DLL_DELAY_SEL_POS)
+#define GLB_DLL_DELAY_SEL_UMSK       (~(((1U << GLB_DLL_DELAY_SEL_LEN) - 1) << GLB_DLL_DELAY_SEL_POS))
+#define GLB_DLL_CP_OP_EN             GLB_DLL_CP_OP_EN
+#define GLB_DLL_CP_OP_EN_POS         (22U)
+#define GLB_DLL_CP_OP_EN_LEN         (1U)
+#define GLB_DLL_CP_OP_EN_MSK         (((1U << GLB_DLL_CP_OP_EN_LEN) - 1) << GLB_DLL_CP_OP_EN_POS)
+#define GLB_DLL_CP_OP_EN_UMSK        (~(((1U << GLB_DLL_CP_OP_EN_LEN) - 1) << GLB_DLL_CP_OP_EN_POS))
+#define GLB_DLL_CP_HIZ               GLB_DLL_CP_HIZ
+#define GLB_DLL_CP_HIZ_POS           (23U)
+#define GLB_DLL_CP_HIZ_LEN           (1U)
+#define GLB_DLL_CP_HIZ_MSK           (((1U << GLB_DLL_CP_HIZ_LEN) - 1) << GLB_DLL_CP_HIZ_POS)
+#define GLB_DLL_CP_HIZ_UMSK          (~(((1U << GLB_DLL_CP_HIZ_LEN) - 1) << GLB_DLL_CP_HIZ_POS))
+#define GLB_DLL_REFCLK_SEL           GLB_DLL_REFCLK_SEL
+#define GLB_DLL_REFCLK_SEL_POS       (28U)
+#define GLB_DLL_REFCLK_SEL_LEN       (1U)
+#define GLB_DLL_REFCLK_SEL_MSK       (((1U << GLB_DLL_REFCLK_SEL_LEN) - 1) << GLB_DLL_REFCLK_SEL_POS)
+#define GLB_DLL_REFCLK_SEL_UMSK      (~(((1U << GLB_DLL_REFCLK_SEL_LEN) - 1) << GLB_DLL_REFCLK_SEL_POS))
+#define GLB_DLL_RESET                GLB_DLL_RESET
+#define GLB_DLL_RESET_POS            (29U)
+#define GLB_DLL_RESET_LEN            (1U)
+#define GLB_DLL_RESET_MSK            (((1U << GLB_DLL_RESET_LEN) - 1) << GLB_DLL_RESET_POS)
+#define GLB_DLL_RESET_UMSK           (~(((1U << GLB_DLL_RESET_LEN) - 1) << GLB_DLL_RESET_POS))
+#define GLB_PU_DLL                   GLB_PU_DLL
+#define GLB_PU_DLL_POS               (30U)
+#define GLB_PU_DLL_LEN               (1U)
+#define GLB_PU_DLL_MSK               (((1U << GLB_PU_DLL_LEN) - 1) << GLB_PU_DLL_POS)
+#define GLB_PU_DLL_UMSK              (~(((1U << GLB_PU_DLL_LEN) - 1) << GLB_PU_DLL_POS))
+#define GLB_PPU_DLL                  GLB_PPU_DLL
+#define GLB_PPU_DLL_POS              (31U)
+#define GLB_PPU_DLL_LEN              (1U)
+#define GLB_PPU_DLL_MSK              (((1U << GLB_PPU_DLL_LEN) - 1) << GLB_PPU_DLL_POS)
+#define GLB_PPU_DLL_UMSK             (~(((1U << GLB_PPU_DLL_LEN) - 1) << GLB_PPU_DLL_POS))
+
+/* 0x224 : led_driver */
+#define GLB_LED_DRIVER_OFFSET         (0x224)
+#define GLB_LED_DIN_REG               GLB_LED_DIN_REG
+#define GLB_LED_DIN_REG_POS           (0U)
+#define GLB_LED_DIN_REG_LEN           (1U)
+#define GLB_LED_DIN_REG_MSK           (((1U << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS)
+#define GLB_LED_DIN_REG_UMSK          (~(((1U << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS))
+#define GLB_LED_DIN_SEL               GLB_LED_DIN_SEL
+#define GLB_LED_DIN_SEL_POS           (1U)
+#define GLB_LED_DIN_SEL_LEN           (1U)
+#define GLB_LED_DIN_SEL_MSK           (((1U << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS)
+#define GLB_LED_DIN_SEL_UMSK          (~(((1U << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS))
+#define GLB_LED_DIN_POLARITY_SEL      GLB_LED_DIN_POLARITY_SEL
+#define GLB_LED_DIN_POLARITY_SEL_POS  (2U)
+#define GLB_LED_DIN_POLARITY_SEL_LEN  (1U)
+#define GLB_LED_DIN_POLARITY_SEL_MSK  (((1U << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) << GLB_LED_DIN_POLARITY_SEL_POS)
+#define GLB_LED_DIN_POLARITY_SEL_UMSK (~(((1U << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) << GLB_LED_DIN_POLARITY_SEL_POS))
+#define GLB_LEDDRV_IBIAS              GLB_LEDDRV_IBIAS
+#define GLB_LEDDRV_IBIAS_POS          (4U)
+#define GLB_LEDDRV_IBIAS_LEN          (4U)
+#define GLB_LEDDRV_IBIAS_MSK          (((1U << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS)
+#define GLB_LEDDRV_IBIAS_UMSK         (~(((1U << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS))
+#define GLB_IR_RX_GPIO_SEL            GLB_IR_RX_GPIO_SEL
+#define GLB_IR_RX_GPIO_SEL_POS        (8U)
+#define GLB_IR_RX_GPIO_SEL_LEN        (4U)
+#define GLB_IR_RX_GPIO_SEL_MSK        (((1U << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS)
+#define GLB_IR_RX_GPIO_SEL_UMSK       (~(((1U << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS))
+#define GLB_LEDDRV_OUT_EN             GLB_LEDDRV_OUT_EN
+#define GLB_LEDDRV_OUT_EN_POS         (28U)
+#define GLB_LEDDRV_OUT_EN_LEN         (2U)
+#define GLB_LEDDRV_OUT_EN_MSK         (((1U << GLB_LEDDRV_OUT_EN_LEN) - 1) << GLB_LEDDRV_OUT_EN_POS)
+#define GLB_LEDDRV_OUT_EN_UMSK        (~(((1U << GLB_LEDDRV_OUT_EN_LEN) - 1) << GLB_LEDDRV_OUT_EN_POS))
+#define GLB_PU_LEDDRV                 GLB_PU_LEDDRV
+#define GLB_PU_LEDDRV_POS             (31U)
+#define GLB_PU_LEDDRV_LEN             (1U)
+#define GLB_PU_LEDDRV_MSK             (((1U << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS)
+#define GLB_PU_LEDDRV_UMSK            (~(((1U << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS))
+
+/* 0x228 : usb_xcvr */
+#define GLB_USB_XCVR_OFFSET       (0x228)
+#define GLB_USB_LDO_VFB           GLB_USB_LDO_VFB
+#define GLB_USB_LDO_VFB_POS       (0U)
+#define GLB_USB_LDO_VFB_LEN       (3U)
+#define GLB_USB_LDO_VFB_MSK       (((1U << GLB_USB_LDO_VFB_LEN) - 1) << GLB_USB_LDO_VFB_POS)
+#define GLB_USB_LDO_VFB_UMSK      (~(((1U << GLB_USB_LDO_VFB_LEN) - 1) << GLB_USB_LDO_VFB_POS))
+#define GLB_PU_USB_LDO            GLB_PU_USB_LDO
+#define GLB_PU_USB_LDO_POS        (3U)
+#define GLB_PU_USB_LDO_LEN        (1U)
+#define GLB_PU_USB_LDO_MSK        (((1U << GLB_PU_USB_LDO_LEN) - 1) << GLB_PU_USB_LDO_POS)
+#define GLB_PU_USB_LDO_UMSK       (~(((1U << GLB_PU_USB_LDO_LEN) - 1) << GLB_PU_USB_LDO_POS))
+#define GLB_USB_ROUT_NMOS         GLB_USB_ROUT_NMOS
+#define GLB_USB_ROUT_NMOS_POS     (4U)
+#define GLB_USB_ROUT_NMOS_LEN     (3U)
+#define GLB_USB_ROUT_NMOS_MSK     (((1U << GLB_USB_ROUT_NMOS_LEN) - 1) << GLB_USB_ROUT_NMOS_POS)
+#define GLB_USB_ROUT_NMOS_UMSK    (~(((1U << GLB_USB_ROUT_NMOS_LEN) - 1) << GLB_USB_ROUT_NMOS_POS))
+#define GLB_USB_ROUT_PMOS         GLB_USB_ROUT_PMOS
+#define GLB_USB_ROUT_PMOS_POS     (8U)
+#define GLB_USB_ROUT_PMOS_LEN     (3U)
+#define GLB_USB_ROUT_PMOS_MSK     (((1U << GLB_USB_ROUT_PMOS_LEN) - 1) << GLB_USB_ROUT_PMOS_POS)
+#define GLB_USB_ROUT_PMOS_UMSK    (~(((1U << GLB_USB_ROUT_PMOS_LEN) - 1) << GLB_USB_ROUT_PMOS_POS))
+#define GLB_USB_OEB_SEL           GLB_USB_OEB_SEL
+#define GLB_USB_OEB_SEL_POS       (12U)
+#define GLB_USB_OEB_SEL_LEN       (1U)
+#define GLB_USB_OEB_SEL_MSK       (((1U << GLB_USB_OEB_SEL_LEN) - 1) << GLB_USB_OEB_SEL_POS)
+#define GLB_USB_OEB_SEL_UMSK      (~(((1U << GLB_USB_OEB_SEL_LEN) - 1) << GLB_USB_OEB_SEL_POS))
+#define GLB_USB_OEB_REG           GLB_USB_OEB_REG
+#define GLB_USB_OEB_REG_POS       (13U)
+#define GLB_USB_OEB_REG_LEN       (1U)
+#define GLB_USB_OEB_REG_MSK       (((1U << GLB_USB_OEB_REG_LEN) - 1) << GLB_USB_OEB_REG_POS)
+#define GLB_USB_OEB_REG_UMSK      (~(((1U << GLB_USB_OEB_REG_LEN) - 1) << GLB_USB_OEB_REG_POS))
+#define GLB_USB_OEB               GLB_USB_OEB
+#define GLB_USB_OEB_POS           (14U)
+#define GLB_USB_OEB_LEN           (1U)
+#define GLB_USB_OEB_MSK           (((1U << GLB_USB_OEB_LEN) - 1) << GLB_USB_OEB_POS)
+#define GLB_USB_OEB_UMSK          (~(((1U << GLB_USB_OEB_LEN) - 1) << GLB_USB_OEB_POS))
+#define GLB_USB_DATA_CONVERT      GLB_USB_DATA_CONVERT
+#define GLB_USB_DATA_CONVERT_POS  (16U)
+#define GLB_USB_DATA_CONVERT_LEN  (1U)
+#define GLB_USB_DATA_CONVERT_MSK  (((1U << GLB_USB_DATA_CONVERT_LEN) - 1) << GLB_USB_DATA_CONVERT_POS)
+#define GLB_USB_DATA_CONVERT_UMSK (~(((1U << GLB_USB_DATA_CONVERT_LEN) - 1) << GLB_USB_DATA_CONVERT_POS))
+#define GLB_USB_ENUM              GLB_USB_ENUM
+#define GLB_USB_ENUM_POS          (20U)
+#define GLB_USB_ENUM_LEN          (1U)
+#define GLB_USB_ENUM_MSK          (((1U << GLB_USB_ENUM_LEN) - 1) << GLB_USB_ENUM_POS)
+#define GLB_USB_ENUM_UMSK         (~(((1U << GLB_USB_ENUM_LEN) - 1) << GLB_USB_ENUM_POS))
+#define GLB_USB_SPD               GLB_USB_SPD
+#define GLB_USB_SPD_POS           (21U)
+#define GLB_USB_SPD_LEN           (1U)
+#define GLB_USB_SPD_MSK           (((1U << GLB_USB_SPD_LEN) - 1) << GLB_USB_SPD_POS)
+#define GLB_USB_SPD_UMSK          (~(((1U << GLB_USB_SPD_LEN) - 1) << GLB_USB_SPD_POS))
+#define GLB_USB_SUS               GLB_USB_SUS
+#define GLB_USB_SUS_POS           (22U)
+#define GLB_USB_SUS_LEN           (1U)
+#define GLB_USB_SUS_MSK           (((1U << GLB_USB_SUS_LEN) - 1) << GLB_USB_SUS_POS)
+#define GLB_USB_SUS_UMSK          (~(((1U << GLB_USB_SUS_LEN) - 1) << GLB_USB_SUS_POS))
+#define GLB_PU_USB                GLB_PU_USB
+#define GLB_PU_USB_POS            (23U)
+#define GLB_PU_USB_LEN            (1U)
+#define GLB_PU_USB_MSK            (((1U << GLB_PU_USB_LEN) - 1) << GLB_PU_USB_POS)
+#define GLB_PU_USB_UMSK           (~(((1U << GLB_PU_USB_LEN) - 1) << GLB_PU_USB_POS))
+#define GLB_USB_BD                GLB_USB_BD
+#define GLB_USB_BD_POS            (24U)
+#define GLB_USB_BD_LEN            (1U)
+#define GLB_USB_BD_MSK            (((1U << GLB_USB_BD_LEN) - 1) << GLB_USB_BD_POS)
+#define GLB_USB_BD_UMSK           (~(((1U << GLB_USB_BD_LEN) - 1) << GLB_USB_BD_POS))
+#define GLB_USB_VIM               GLB_USB_VIM
+#define GLB_USB_VIM_POS           (25U)
+#define GLB_USB_VIM_LEN           (1U)
+#define GLB_USB_VIM_MSK           (((1U << GLB_USB_VIM_LEN) - 1) << GLB_USB_VIM_POS)
+#define GLB_USB_VIM_UMSK          (~(((1U << GLB_USB_VIM_LEN) - 1) << GLB_USB_VIM_POS))
+#define GLB_USB_VIP               GLB_USB_VIP
+#define GLB_USB_VIP_POS           (26U)
+#define GLB_USB_VIP_LEN           (1U)
+#define GLB_USB_VIP_MSK           (((1U << GLB_USB_VIP_LEN) - 1) << GLB_USB_VIP_POS)
+#define GLB_USB_VIP_UMSK          (~(((1U << GLB_USB_VIP_LEN) - 1) << GLB_USB_VIP_POS))
+#define GLB_USB_RCV               GLB_USB_RCV
+#define GLB_USB_RCV_POS           (27U)
+#define GLB_USB_RCV_LEN           (1U)
+#define GLB_USB_RCV_MSK           (((1U << GLB_USB_RCV_LEN) - 1) << GLB_USB_RCV_POS)
+#define GLB_USB_RCV_UMSK          (~(((1U << GLB_USB_RCV_LEN) - 1) << GLB_USB_RCV_POS))
+
+/* 0x22C : usb_xcvr_config */
+#define GLB_USB_XCVR_CONFIG_OFFSET   (0x22C)
+#define GLB_USB_V_HYS_M              GLB_USB_V_HYS_M
+#define GLB_USB_V_HYS_M_POS          (0U)
+#define GLB_USB_V_HYS_M_LEN          (2U)
+#define GLB_USB_V_HYS_M_MSK          (((1U << GLB_USB_V_HYS_M_LEN) - 1) << GLB_USB_V_HYS_M_POS)
+#define GLB_USB_V_HYS_M_UMSK         (~(((1U << GLB_USB_V_HYS_M_LEN) - 1) << GLB_USB_V_HYS_M_POS))
+#define GLB_USB_V_HYS_P              GLB_USB_V_HYS_P
+#define GLB_USB_V_HYS_P_POS          (2U)
+#define GLB_USB_V_HYS_P_LEN          (2U)
+#define GLB_USB_V_HYS_P_MSK          (((1U << GLB_USB_V_HYS_P_LEN) - 1) << GLB_USB_V_HYS_P_POS)
+#define GLB_USB_V_HYS_P_UMSK         (~(((1U << GLB_USB_V_HYS_P_LEN) - 1) << GLB_USB_V_HYS_P_POS))
+#define GLB_USB_BD_VTH               GLB_USB_BD_VTH
+#define GLB_USB_BD_VTH_POS           (4U)
+#define GLB_USB_BD_VTH_LEN           (3U)
+#define GLB_USB_BD_VTH_MSK           (((1U << GLB_USB_BD_VTH_LEN) - 1) << GLB_USB_BD_VTH_POS)
+#define GLB_USB_BD_VTH_UMSK          (~(((1U << GLB_USB_BD_VTH_LEN) - 1) << GLB_USB_BD_VTH_POS))
+#define GLB_REG_USB_USE_XCVR         GLB_REG_USB_USE_XCVR
+#define GLB_REG_USB_USE_XCVR_POS     (7U)
+#define GLB_REG_USB_USE_XCVR_LEN     (1U)
+#define GLB_REG_USB_USE_XCVR_MSK     (((1U << GLB_REG_USB_USE_XCVR_LEN) - 1) << GLB_REG_USB_USE_XCVR_POS)
+#define GLB_REG_USB_USE_XCVR_UMSK    (~(((1U << GLB_REG_USB_USE_XCVR_LEN) - 1) << GLB_REG_USB_USE_XCVR_POS))
+#define GLB_USB_STR_DRV              GLB_USB_STR_DRV
+#define GLB_USB_STR_DRV_POS          (8U)
+#define GLB_USB_STR_DRV_LEN          (3U)
+#define GLB_USB_STR_DRV_MSK          (((1U << GLB_USB_STR_DRV_LEN) - 1) << GLB_USB_STR_DRV_POS)
+#define GLB_USB_STR_DRV_UMSK         (~(((1U << GLB_USB_STR_DRV_LEN) - 1) << GLB_USB_STR_DRV_POS))
+#define GLB_REG_USB_USE_CTRL         GLB_REG_USB_USE_CTRL
+#define GLB_REG_USB_USE_CTRL_POS     (11U)
+#define GLB_REG_USB_USE_CTRL_LEN     (1U)
+#define GLB_REG_USB_USE_CTRL_MSK     (((1U << GLB_REG_USB_USE_CTRL_LEN) - 1) << GLB_REG_USB_USE_CTRL_POS)
+#define GLB_REG_USB_USE_CTRL_UMSK    (~(((1U << GLB_REG_USB_USE_CTRL_LEN) - 1) << GLB_REG_USB_USE_CTRL_POS))
+#define GLB_USB_RES_PULLUP_TUNE      GLB_USB_RES_PULLUP_TUNE
+#define GLB_USB_RES_PULLUP_TUNE_POS  (12U)
+#define GLB_USB_RES_PULLUP_TUNE_LEN  (3U)
+#define GLB_USB_RES_PULLUP_TUNE_MSK  (((1U << GLB_USB_RES_PULLUP_TUNE_LEN) - 1) << GLB_USB_RES_PULLUP_TUNE_POS)
+#define GLB_USB_RES_PULLUP_TUNE_UMSK (~(((1U << GLB_USB_RES_PULLUP_TUNE_LEN) - 1) << GLB_USB_RES_PULLUP_TUNE_POS))
+#define GLB_USB_SLEWRATE_M_FALL      GLB_USB_SLEWRATE_M_FALL
+#define GLB_USB_SLEWRATE_M_FALL_POS  (16U)
+#define GLB_USB_SLEWRATE_M_FALL_LEN  (3U)
+#define GLB_USB_SLEWRATE_M_FALL_MSK  (((1U << GLB_USB_SLEWRATE_M_FALL_LEN) - 1) << GLB_USB_SLEWRATE_M_FALL_POS)
+#define GLB_USB_SLEWRATE_M_FALL_UMSK (~(((1U << GLB_USB_SLEWRATE_M_FALL_LEN) - 1) << GLB_USB_SLEWRATE_M_FALL_POS))
+#define GLB_USB_SLEWRATE_M_RISE      GLB_USB_SLEWRATE_M_RISE
+#define GLB_USB_SLEWRATE_M_RISE_POS  (20U)
+#define GLB_USB_SLEWRATE_M_RISE_LEN  (3U)
+#define GLB_USB_SLEWRATE_M_RISE_MSK  (((1U << GLB_USB_SLEWRATE_M_RISE_LEN) - 1) << GLB_USB_SLEWRATE_M_RISE_POS)
+#define GLB_USB_SLEWRATE_M_RISE_UMSK (~(((1U << GLB_USB_SLEWRATE_M_RISE_LEN) - 1) << GLB_USB_SLEWRATE_M_RISE_POS))
+#define GLB_USB_SLEWRATE_P_FALL      GLB_USB_SLEWRATE_P_FALL
+#define GLB_USB_SLEWRATE_P_FALL_POS  (24U)
+#define GLB_USB_SLEWRATE_P_FALL_LEN  (3U)
+#define GLB_USB_SLEWRATE_P_FALL_MSK  (((1U << GLB_USB_SLEWRATE_P_FALL_LEN) - 1) << GLB_USB_SLEWRATE_P_FALL_POS)
+#define GLB_USB_SLEWRATE_P_FALL_UMSK (~(((1U << GLB_USB_SLEWRATE_P_FALL_LEN) - 1) << GLB_USB_SLEWRATE_P_FALL_POS))
+#define GLB_USB_SLEWRATE_P_RISE      GLB_USB_SLEWRATE_P_RISE
+#define GLB_USB_SLEWRATE_P_RISE_POS  (28U)
+#define GLB_USB_SLEWRATE_P_RISE_LEN  (3U)
+#define GLB_USB_SLEWRATE_P_RISE_MSK  (((1U << GLB_USB_SLEWRATE_P_RISE_LEN) - 1) << GLB_USB_SLEWRATE_P_RISE_POS)
+#define GLB_USB_SLEWRATE_P_RISE_UMSK (~(((1U << GLB_USB_SLEWRATE_P_RISE_LEN) - 1) << GLB_USB_SLEWRATE_P_RISE_POS))
+
+/* 0x308 : gpdac_ctrl */
+#define GLB_GPDAC_CTRL_OFFSET    (0x308)
+#define GLB_GPDACA_RSTN_ANA      GLB_GPDACA_RSTN_ANA
+#define GLB_GPDACA_RSTN_ANA_POS  (0U)
+#define GLB_GPDACA_RSTN_ANA_LEN  (1U)
+#define GLB_GPDACA_RSTN_ANA_MSK  (((1U << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS)
+#define GLB_GPDACA_RSTN_ANA_UMSK (~(((1U << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS))
+#define GLB_GPDACB_RSTN_ANA      GLB_GPDACB_RSTN_ANA
+#define GLB_GPDACB_RSTN_ANA_POS  (1U)
+#define GLB_GPDACB_RSTN_ANA_LEN  (1U)
+#define GLB_GPDACB_RSTN_ANA_MSK  (((1U << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS)
+#define GLB_GPDACB_RSTN_ANA_UMSK (~(((1U << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS))
+#define GLB_GPDAC_TEST_EN        GLB_GPDAC_TEST_EN
+#define GLB_GPDAC_TEST_EN_POS    (7U)
+#define GLB_GPDAC_TEST_EN_LEN    (1U)
+#define GLB_GPDAC_TEST_EN_MSK    (((1U << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS)
+#define GLB_GPDAC_TEST_EN_UMSK   (~(((1U << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS))
+#define GLB_GPDAC_REF_SEL        GLB_GPDAC_REF_SEL
+#define GLB_GPDAC_REF_SEL_POS    (8U)
+#define GLB_GPDAC_REF_SEL_LEN    (1U)
+#define GLB_GPDAC_REF_SEL_MSK    (((1U << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS)
+#define GLB_GPDAC_REF_SEL_UMSK   (~(((1U << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS))
+#define GLB_GPDAC_TEST_SEL       GLB_GPDAC_TEST_SEL
+#define GLB_GPDAC_TEST_SEL_POS   (9U)
+#define GLB_GPDAC_TEST_SEL_LEN   (3U)
+#define GLB_GPDAC_TEST_SEL_MSK   (((1U << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS)
+#define GLB_GPDAC_TEST_SEL_UMSK  (~(((1U << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS))
+#define GLB_GPDAC_RESERVED       GLB_GPDAC_RESERVED
+#define GLB_GPDAC_RESERVED_POS   (24U)
+#define GLB_GPDAC_RESERVED_LEN   (8U)
+#define GLB_GPDAC_RESERVED_MSK   (((1U << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS)
+#define GLB_GPDAC_RESERVED_UMSK  (~(((1U << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS))
+
+/* 0x30C : gpdac_actrl */
+#define GLB_GPDAC_ACTRL_OFFSET  (0x30C)
+#define GLB_GPDAC_A_EN          GLB_GPDAC_A_EN
+#define GLB_GPDAC_A_EN_POS      (0U)
+#define GLB_GPDAC_A_EN_LEN      (1U)
+#define GLB_GPDAC_A_EN_MSK      (((1U << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS)
+#define GLB_GPDAC_A_EN_UMSK     (~(((1U << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS))
+#define GLB_GPDAC_IOA_EN        GLB_GPDAC_IOA_EN
+#define GLB_GPDAC_IOA_EN_POS    (1U)
+#define GLB_GPDAC_IOA_EN_LEN    (1U)
+#define GLB_GPDAC_IOA_EN_MSK    (((1U << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS)
+#define GLB_GPDAC_IOA_EN_UMSK   (~(((1U << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS))
+#define GLB_GPDAC_A_RNG         GLB_GPDAC_A_RNG
+#define GLB_GPDAC_A_RNG_POS     (18U)
+#define GLB_GPDAC_A_RNG_LEN     (2U)
+#define GLB_GPDAC_A_RNG_MSK     (((1U << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS)
+#define GLB_GPDAC_A_RNG_UMSK    (~(((1U << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS))
+#define GLB_GPDAC_A_OUTMUX      GLB_GPDAC_A_OUTMUX
+#define GLB_GPDAC_A_OUTMUX_POS  (20U)
+#define GLB_GPDAC_A_OUTMUX_LEN  (3U)
+#define GLB_GPDAC_A_OUTMUX_MSK  (((1U << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS)
+#define GLB_GPDAC_A_OUTMUX_UMSK (~(((1U << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS))
+
+/* 0x310 : gpdac_bctrl */
+#define GLB_GPDAC_BCTRL_OFFSET  (0x310)
+#define GLB_GPDAC_B_EN          GLB_GPDAC_B_EN
+#define GLB_GPDAC_B_EN_POS      (0U)
+#define GLB_GPDAC_B_EN_LEN      (1U)
+#define GLB_GPDAC_B_EN_MSK      (((1U << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS)
+#define GLB_GPDAC_B_EN_UMSK     (~(((1U << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS))
+#define GLB_GPDAC_IOB_EN        GLB_GPDAC_IOB_EN
+#define GLB_GPDAC_IOB_EN_POS    (1U)
+#define GLB_GPDAC_IOB_EN_LEN    (1U)
+#define GLB_GPDAC_IOB_EN_MSK    (((1U << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS)
+#define GLB_GPDAC_IOB_EN_UMSK   (~(((1U << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS))
+#define GLB_GPDAC_B_RNG         GLB_GPDAC_B_RNG
+#define GLB_GPDAC_B_RNG_POS     (18U)
+#define GLB_GPDAC_B_RNG_LEN     (2U)
+#define GLB_GPDAC_B_RNG_MSK     (((1U << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS)
+#define GLB_GPDAC_B_RNG_UMSK    (~(((1U << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS))
+#define GLB_GPDAC_B_OUTMUX      GLB_GPDAC_B_OUTMUX
+#define GLB_GPDAC_B_OUTMUX_POS  (20U)
+#define GLB_GPDAC_B_OUTMUX_LEN  (3U)
+#define GLB_GPDAC_B_OUTMUX_MSK  (((1U << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS)
+#define GLB_GPDAC_B_OUTMUX_UMSK (~(((1U << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS))
+
+/* 0x314 : gpdac_data */
+#define GLB_GPDAC_DATA_OFFSET (0x314)
+#define GLB_GPDAC_B_DATA      GLB_GPDAC_B_DATA
+#define GLB_GPDAC_B_DATA_POS  (0U)
+#define GLB_GPDAC_B_DATA_LEN  (10U)
+#define GLB_GPDAC_B_DATA_MSK  (((1U << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS)
+#define GLB_GPDAC_B_DATA_UMSK (~(((1U << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS))
+#define GLB_GPDAC_A_DATA      GLB_GPDAC_A_DATA
+#define GLB_GPDAC_A_DATA_POS  (16U)
+#define GLB_GPDAC_A_DATA_LEN  (10U)
+#define GLB_GPDAC_A_DATA_MSK  (((1U << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS)
+#define GLB_GPDAC_A_DATA_UMSK (~(((1U << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS))
+
+/* 0xE00 : chip_revision */
+#define GLB_CHIP_REVISION_OFFSET (0xE00)
+#define GLB_CHIP_REV             GLB_CHIP_REV
+#define GLB_CHIP_REV_POS         (0U)
+#define GLB_CHIP_REV_LEN         (4U)
+#define GLB_CHIP_REV_MSK         (((1U << GLB_CHIP_REV_LEN) - 1) << GLB_CHIP_REV_POS)
+#define GLB_CHIP_REV_UMSK        (~(((1U << GLB_CHIP_REV_LEN) - 1) << GLB_CHIP_REV_POS))
+
+/* 0xF00 : tzc_glb_ctrl_0 */
+#define GLB_TZC_GLB_CTRL_0_OFFSET             (0xF00)
+#define GLB_TZC_GLB_SWRST_S00_LOCK            GLB_TZC_GLB_SWRST_S00_LOCK
+#define GLB_TZC_GLB_SWRST_S00_LOCK_POS        (0U)
+#define GLB_TZC_GLB_SWRST_S00_LOCK_LEN        (1U)
+#define GLB_TZC_GLB_SWRST_S00_LOCK_MSK        (((1U << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S00_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S00_LOCK_UMSK       (~(((1U << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S00_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S01_LOCK            GLB_TZC_GLB_SWRST_S01_LOCK
+#define GLB_TZC_GLB_SWRST_S01_LOCK_POS        (1U)
+#define GLB_TZC_GLB_SWRST_S01_LOCK_LEN        (1U)
+#define GLB_TZC_GLB_SWRST_S01_LOCK_MSK        (((1U << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S01_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S01_LOCK_UMSK       (~(((1U << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S01_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S30_LOCK            GLB_TZC_GLB_SWRST_S30_LOCK
+#define GLB_TZC_GLB_SWRST_S30_LOCK_POS        (8U)
+#define GLB_TZC_GLB_SWRST_S30_LOCK_LEN        (1U)
+#define GLB_TZC_GLB_SWRST_S30_LOCK_MSK        (((1U << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S30_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S30_LOCK_UMSK       (~(((1U << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S30_LOCK_POS))
+#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK       GLB_TZC_GLB_CTRL_PWRON_RST_LOCK
+#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS   (12U)
+#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_MSK   (((1U << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS)
+#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS))
+#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK       GLB_TZC_GLB_CTRL_CPU_RESET_LOCK
+#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS   (13U)
+#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_MSK   (((1U << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS)
+#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS))
+#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK       GLB_TZC_GLB_CTRL_SYS_RESET_LOCK
+#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS   (14U)
+#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_MSK   (((1U << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS)
+#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS))
+#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK      GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK
+#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS  (15U)
+#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_MSK  (((1U << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS)
+#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_UMSK (~(((1U << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS))
+#define GLB_TZC_GLB_MISC_LOCK                 GLB_TZC_GLB_MISC_LOCK
+#define GLB_TZC_GLB_MISC_LOCK_POS             (25U)
+#define GLB_TZC_GLB_MISC_LOCK_LEN             (1U)
+#define GLB_TZC_GLB_MISC_LOCK_MSK             (((1U << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS)
+#define GLB_TZC_GLB_MISC_LOCK_UMSK            (~(((1U << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS))
+#define GLB_TZC_GLB_SRAM_LOCK                 GLB_TZC_GLB_SRAM_LOCK
+#define GLB_TZC_GLB_SRAM_LOCK_POS             (26U)
+#define GLB_TZC_GLB_SRAM_LOCK_LEN             (1U)
+#define GLB_TZC_GLB_SRAM_LOCK_MSK             (((1U << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS)
+#define GLB_TZC_GLB_SRAM_LOCK_UMSK            (~(((1U << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS))
+#define GLB_TZC_GLB_L2C_LOCK                  GLB_TZC_GLB_L2C_LOCK
+#define GLB_TZC_GLB_L2C_LOCK_POS              (27U)
+#define GLB_TZC_GLB_L2C_LOCK_LEN              (1U)
+#define GLB_TZC_GLB_L2C_LOCK_MSK              (((1U << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS)
+#define GLB_TZC_GLB_L2C_LOCK_UMSK             (~(((1U << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS))
+#define GLB_TZC_GLB_BMX_LOCK                  GLB_TZC_GLB_BMX_LOCK
+#define GLB_TZC_GLB_BMX_LOCK_POS              (28U)
+#define GLB_TZC_GLB_BMX_LOCK_LEN              (1U)
+#define GLB_TZC_GLB_BMX_LOCK_MSK              (((1U << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS)
+#define GLB_TZC_GLB_BMX_LOCK_UMSK             (~(((1U << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS))
+#define GLB_TZC_GLB_DBG_LOCK                  GLB_TZC_GLB_DBG_LOCK
+#define GLB_TZC_GLB_DBG_LOCK_POS              (29U)
+#define GLB_TZC_GLB_DBG_LOCK_LEN              (1U)
+#define GLB_TZC_GLB_DBG_LOCK_MSK              (((1U << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS)
+#define GLB_TZC_GLB_DBG_LOCK_UMSK             (~(((1U << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS))
+#define GLB_TZC_GLB_MBIST_LOCK                GLB_TZC_GLB_MBIST_LOCK
+#define GLB_TZC_GLB_MBIST_LOCK_POS            (30U)
+#define GLB_TZC_GLB_MBIST_LOCK_LEN            (1U)
+#define GLB_TZC_GLB_MBIST_LOCK_MSK            (((1U << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS)
+#define GLB_TZC_GLB_MBIST_LOCK_UMSK           (~(((1U << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS))
+#define GLB_TZC_GLB_CLK_LOCK                  GLB_TZC_GLB_CLK_LOCK
+#define GLB_TZC_GLB_CLK_LOCK_POS              (31U)
+#define GLB_TZC_GLB_CLK_LOCK_LEN              (1U)
+#define GLB_TZC_GLB_CLK_LOCK_MSK              (((1U << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS)
+#define GLB_TZC_GLB_CLK_LOCK_UMSK             (~(((1U << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS))
+
+/* 0xF04 : tzc_glb_ctrl_1 */
+#define GLB_TZC_GLB_CTRL_1_OFFSET       (0xF04)
+#define GLB_TZC_GLB_SWRST_S20_LOCK      GLB_TZC_GLB_SWRST_S20_LOCK
+#define GLB_TZC_GLB_SWRST_S20_LOCK_POS  (0U)
+#define GLB_TZC_GLB_SWRST_S20_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S20_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S20_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S20_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S20_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S21_LOCK      GLB_TZC_GLB_SWRST_S21_LOCK
+#define GLB_TZC_GLB_SWRST_S21_LOCK_POS  (1U)
+#define GLB_TZC_GLB_SWRST_S21_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S21_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S21_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S21_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S21_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S22_LOCK      GLB_TZC_GLB_SWRST_S22_LOCK
+#define GLB_TZC_GLB_SWRST_S22_LOCK_POS  (2U)
+#define GLB_TZC_GLB_SWRST_S22_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S22_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S22_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S22_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S22_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S23_LOCK      GLB_TZC_GLB_SWRST_S23_LOCK
+#define GLB_TZC_GLB_SWRST_S23_LOCK_POS  (3U)
+#define GLB_TZC_GLB_SWRST_S23_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S23_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S23_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S23_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S23_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S24_LOCK      GLB_TZC_GLB_SWRST_S24_LOCK
+#define GLB_TZC_GLB_SWRST_S24_LOCK_POS  (4U)
+#define GLB_TZC_GLB_SWRST_S24_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S24_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S24_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S24_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S24_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S25_LOCK      GLB_TZC_GLB_SWRST_S25_LOCK
+#define GLB_TZC_GLB_SWRST_S25_LOCK_POS  (5U)
+#define GLB_TZC_GLB_SWRST_S25_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S25_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S25_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S25_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S25_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S26_LOCK      GLB_TZC_GLB_SWRST_S26_LOCK
+#define GLB_TZC_GLB_SWRST_S26_LOCK_POS  (6U)
+#define GLB_TZC_GLB_SWRST_S26_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S26_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S26_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S26_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S26_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S27_LOCK      GLB_TZC_GLB_SWRST_S27_LOCK
+#define GLB_TZC_GLB_SWRST_S27_LOCK_POS  (7U)
+#define GLB_TZC_GLB_SWRST_S27_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S27_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S27_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S27_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S27_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S28_LOCK      GLB_TZC_GLB_SWRST_S28_LOCK
+#define GLB_TZC_GLB_SWRST_S28_LOCK_POS  (8U)
+#define GLB_TZC_GLB_SWRST_S28_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S28_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S28_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S28_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S28_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S29_LOCK      GLB_TZC_GLB_SWRST_S29_LOCK
+#define GLB_TZC_GLB_SWRST_S29_LOCK_POS  (9U)
+#define GLB_TZC_GLB_SWRST_S29_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S29_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S29_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S29_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S29_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S2A_LOCK      GLB_TZC_GLB_SWRST_S2A_LOCK
+#define GLB_TZC_GLB_SWRST_S2A_LOCK_POS  (10U)
+#define GLB_TZC_GLB_SWRST_S2A_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S2A_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2A_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S2A_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2A_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S2B_LOCK      GLB_TZC_GLB_SWRST_S2B_LOCK
+#define GLB_TZC_GLB_SWRST_S2B_LOCK_POS  (11U)
+#define GLB_TZC_GLB_SWRST_S2B_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S2B_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2B_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S2B_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2B_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S2C_LOCK      GLB_TZC_GLB_SWRST_S2C_LOCK
+#define GLB_TZC_GLB_SWRST_S2C_LOCK_POS  (12U)
+#define GLB_TZC_GLB_SWRST_S2C_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S2C_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2C_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S2C_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2C_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S2D_LOCK      GLB_TZC_GLB_SWRST_S2D_LOCK
+#define GLB_TZC_GLB_SWRST_S2D_LOCK_POS  (13U)
+#define GLB_TZC_GLB_SWRST_S2D_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S2D_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2D_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S2D_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2D_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S2E_LOCK      GLB_TZC_GLB_SWRST_S2E_LOCK
+#define GLB_TZC_GLB_SWRST_S2E_LOCK_POS  (14U)
+#define GLB_TZC_GLB_SWRST_S2E_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S2E_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2E_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S2E_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2E_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S2F_LOCK      GLB_TZC_GLB_SWRST_S2F_LOCK
+#define GLB_TZC_GLB_SWRST_S2F_LOCK_POS  (15U)
+#define GLB_TZC_GLB_SWRST_S2F_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S2F_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2F_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S2F_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2F_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S10_LOCK      GLB_TZC_GLB_SWRST_S10_LOCK
+#define GLB_TZC_GLB_SWRST_S10_LOCK_POS  (16U)
+#define GLB_TZC_GLB_SWRST_S10_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S10_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S10_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S10_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S10_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S11_LOCK      GLB_TZC_GLB_SWRST_S11_LOCK
+#define GLB_TZC_GLB_SWRST_S11_LOCK_POS  (17U)
+#define GLB_TZC_GLB_SWRST_S11_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S11_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S11_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S11_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S11_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S12_LOCK      GLB_TZC_GLB_SWRST_S12_LOCK
+#define GLB_TZC_GLB_SWRST_S12_LOCK_POS  (18U)
+#define GLB_TZC_GLB_SWRST_S12_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S12_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S12_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S12_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S12_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S13_LOCK      GLB_TZC_GLB_SWRST_S13_LOCK
+#define GLB_TZC_GLB_SWRST_S13_LOCK_POS  (19U)
+#define GLB_TZC_GLB_SWRST_S13_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S13_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S13_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S13_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S13_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S14_LOCK      GLB_TZC_GLB_SWRST_S14_LOCK
+#define GLB_TZC_GLB_SWRST_S14_LOCK_POS  (20U)
+#define GLB_TZC_GLB_SWRST_S14_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S14_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S14_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S14_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S14_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S15_LOCK      GLB_TZC_GLB_SWRST_S15_LOCK
+#define GLB_TZC_GLB_SWRST_S15_LOCK_POS  (21U)
+#define GLB_TZC_GLB_SWRST_S15_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S15_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S15_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S15_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S15_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S16_LOCK      GLB_TZC_GLB_SWRST_S16_LOCK
+#define GLB_TZC_GLB_SWRST_S16_LOCK_POS  (22U)
+#define GLB_TZC_GLB_SWRST_S16_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S16_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S16_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S16_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S16_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S17_LOCK      GLB_TZC_GLB_SWRST_S17_LOCK
+#define GLB_TZC_GLB_SWRST_S17_LOCK_POS  (23U)
+#define GLB_TZC_GLB_SWRST_S17_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S17_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S17_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S17_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S17_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S18_LOCK      GLB_TZC_GLB_SWRST_S18_LOCK
+#define GLB_TZC_GLB_SWRST_S18_LOCK_POS  (24U)
+#define GLB_TZC_GLB_SWRST_S18_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S18_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S18_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S18_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S18_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S19_LOCK      GLB_TZC_GLB_SWRST_S19_LOCK
+#define GLB_TZC_GLB_SWRST_S19_LOCK_POS  (25U)
+#define GLB_TZC_GLB_SWRST_S19_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S19_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S19_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S19_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S19_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S1A_LOCK      GLB_TZC_GLB_SWRST_S1A_LOCK
+#define GLB_TZC_GLB_SWRST_S1A_LOCK_POS  (26U)
+#define GLB_TZC_GLB_SWRST_S1A_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S1A_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1A_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S1A_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1A_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S1B_LOCK      GLB_TZC_GLB_SWRST_S1B_LOCK
+#define GLB_TZC_GLB_SWRST_S1B_LOCK_POS  (27U)
+#define GLB_TZC_GLB_SWRST_S1B_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S1B_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1B_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S1B_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1B_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S1C_LOCK      GLB_TZC_GLB_SWRST_S1C_LOCK
+#define GLB_TZC_GLB_SWRST_S1C_LOCK_POS  (28U)
+#define GLB_TZC_GLB_SWRST_S1C_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S1C_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1C_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S1C_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1C_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S1D_LOCK      GLB_TZC_GLB_SWRST_S1D_LOCK
+#define GLB_TZC_GLB_SWRST_S1D_LOCK_POS  (29U)
+#define GLB_TZC_GLB_SWRST_S1D_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S1D_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1D_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S1D_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1D_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S1E_LOCK      GLB_TZC_GLB_SWRST_S1E_LOCK
+#define GLB_TZC_GLB_SWRST_S1E_LOCK_POS  (30U)
+#define GLB_TZC_GLB_SWRST_S1E_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S1E_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1E_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S1E_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1E_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S1F_LOCK      GLB_TZC_GLB_SWRST_S1F_LOCK
+#define GLB_TZC_GLB_SWRST_S1F_LOCK_POS  (31U)
+#define GLB_TZC_GLB_SWRST_S1F_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S1F_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1F_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S1F_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1F_LOCK_POS))
+
+/* 0xF08 : tzc_glb_ctrl_2 */
+#define GLB_TZC_GLB_CTRL_2_OFFSET     (0xF08)
+#define GLB_TZC_GLB_GPIO_0_LOCK       GLB_TZC_GLB_GPIO_0_LOCK
+#define GLB_TZC_GLB_GPIO_0_LOCK_POS   (0U)
+#define GLB_TZC_GLB_GPIO_0_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_0_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_0_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_0_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_0_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_1_LOCK       GLB_TZC_GLB_GPIO_1_LOCK
+#define GLB_TZC_GLB_GPIO_1_LOCK_POS   (1U)
+#define GLB_TZC_GLB_GPIO_1_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_1_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_1_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_1_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_1_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_2_LOCK       GLB_TZC_GLB_GPIO_2_LOCK
+#define GLB_TZC_GLB_GPIO_2_LOCK_POS   (2U)
+#define GLB_TZC_GLB_GPIO_2_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_2_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_2_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_2_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_2_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_3_LOCK       GLB_TZC_GLB_GPIO_3_LOCK
+#define GLB_TZC_GLB_GPIO_3_LOCK_POS   (3U)
+#define GLB_TZC_GLB_GPIO_3_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_3_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_3_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_3_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_3_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_4_LOCK       GLB_TZC_GLB_GPIO_4_LOCK
+#define GLB_TZC_GLB_GPIO_4_LOCK_POS   (4U)
+#define GLB_TZC_GLB_GPIO_4_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_4_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_4_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_4_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_4_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_5_LOCK       GLB_TZC_GLB_GPIO_5_LOCK
+#define GLB_TZC_GLB_GPIO_5_LOCK_POS   (5U)
+#define GLB_TZC_GLB_GPIO_5_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_5_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_5_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_5_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_5_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_6_LOCK       GLB_TZC_GLB_GPIO_6_LOCK
+#define GLB_TZC_GLB_GPIO_6_LOCK_POS   (6U)
+#define GLB_TZC_GLB_GPIO_6_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_6_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_6_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_6_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_6_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_7_LOCK       GLB_TZC_GLB_GPIO_7_LOCK
+#define GLB_TZC_GLB_GPIO_7_LOCK_POS   (7U)
+#define GLB_TZC_GLB_GPIO_7_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_7_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_7_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_7_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_7_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_8_LOCK       GLB_TZC_GLB_GPIO_8_LOCK
+#define GLB_TZC_GLB_GPIO_8_LOCK_POS   (8U)
+#define GLB_TZC_GLB_GPIO_8_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_8_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_8_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_8_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_8_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_9_LOCK       GLB_TZC_GLB_GPIO_9_LOCK
+#define GLB_TZC_GLB_GPIO_9_LOCK_POS   (9U)
+#define GLB_TZC_GLB_GPIO_9_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_9_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_9_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_9_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_9_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_10_LOCK      GLB_TZC_GLB_GPIO_10_LOCK
+#define GLB_TZC_GLB_GPIO_10_LOCK_POS  (10U)
+#define GLB_TZC_GLB_GPIO_10_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_10_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_10_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_10_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_10_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_11_LOCK      GLB_TZC_GLB_GPIO_11_LOCK
+#define GLB_TZC_GLB_GPIO_11_LOCK_POS  (11U)
+#define GLB_TZC_GLB_GPIO_11_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_11_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_11_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_11_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_11_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_12_LOCK      GLB_TZC_GLB_GPIO_12_LOCK
+#define GLB_TZC_GLB_GPIO_12_LOCK_POS  (12U)
+#define GLB_TZC_GLB_GPIO_12_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_12_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_12_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_12_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_12_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_13_LOCK      GLB_TZC_GLB_GPIO_13_LOCK
+#define GLB_TZC_GLB_GPIO_13_LOCK_POS  (13U)
+#define GLB_TZC_GLB_GPIO_13_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_13_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_13_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_13_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_13_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_14_LOCK      GLB_TZC_GLB_GPIO_14_LOCK
+#define GLB_TZC_GLB_GPIO_14_LOCK_POS  (14U)
+#define GLB_TZC_GLB_GPIO_14_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_14_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_14_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_14_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_14_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_15_LOCK      GLB_TZC_GLB_GPIO_15_LOCK
+#define GLB_TZC_GLB_GPIO_15_LOCK_POS  (15U)
+#define GLB_TZC_GLB_GPIO_15_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_15_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_15_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_15_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_15_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_16_LOCK      GLB_TZC_GLB_GPIO_16_LOCK
+#define GLB_TZC_GLB_GPIO_16_LOCK_POS  (16U)
+#define GLB_TZC_GLB_GPIO_16_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_16_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_16_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_16_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_16_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_17_LOCK      GLB_TZC_GLB_GPIO_17_LOCK
+#define GLB_TZC_GLB_GPIO_17_LOCK_POS  (17U)
+#define GLB_TZC_GLB_GPIO_17_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_17_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_17_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_17_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_17_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_18_LOCK      GLB_TZC_GLB_GPIO_18_LOCK
+#define GLB_TZC_GLB_GPIO_18_LOCK_POS  (18U)
+#define GLB_TZC_GLB_GPIO_18_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_18_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_18_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_18_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_18_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_19_LOCK      GLB_TZC_GLB_GPIO_19_LOCK
+#define GLB_TZC_GLB_GPIO_19_LOCK_POS  (19U)
+#define GLB_TZC_GLB_GPIO_19_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_19_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_19_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_19_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_19_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_20_LOCK      GLB_TZC_GLB_GPIO_20_LOCK
+#define GLB_TZC_GLB_GPIO_20_LOCK_POS  (20U)
+#define GLB_TZC_GLB_GPIO_20_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_20_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_20_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_20_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_20_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_21_LOCK      GLB_TZC_GLB_GPIO_21_LOCK
+#define GLB_TZC_GLB_GPIO_21_LOCK_POS  (21U)
+#define GLB_TZC_GLB_GPIO_21_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_21_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_21_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_21_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_21_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_22_LOCK      GLB_TZC_GLB_GPIO_22_LOCK
+#define GLB_TZC_GLB_GPIO_22_LOCK_POS  (22U)
+#define GLB_TZC_GLB_GPIO_22_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_22_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_22_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_22_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_22_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_23_LOCK      GLB_TZC_GLB_GPIO_23_LOCK
+#define GLB_TZC_GLB_GPIO_23_LOCK_POS  (23U)
+#define GLB_TZC_GLB_GPIO_23_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_23_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_23_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_23_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_23_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_24_LOCK      GLB_TZC_GLB_GPIO_24_LOCK
+#define GLB_TZC_GLB_GPIO_24_LOCK_POS  (24U)
+#define GLB_TZC_GLB_GPIO_24_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_24_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_24_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_24_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_24_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_25_LOCK      GLB_TZC_GLB_GPIO_25_LOCK
+#define GLB_TZC_GLB_GPIO_25_LOCK_POS  (25U)
+#define GLB_TZC_GLB_GPIO_25_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_25_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_25_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_25_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_25_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_26_LOCK      GLB_TZC_GLB_GPIO_26_LOCK
+#define GLB_TZC_GLB_GPIO_26_LOCK_POS  (26U)
+#define GLB_TZC_GLB_GPIO_26_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_26_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_26_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_26_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_26_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_27_LOCK      GLB_TZC_GLB_GPIO_27_LOCK
+#define GLB_TZC_GLB_GPIO_27_LOCK_POS  (27U)
+#define GLB_TZC_GLB_GPIO_27_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_27_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_27_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_27_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_27_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_28_LOCK      GLB_TZC_GLB_GPIO_28_LOCK
+#define GLB_TZC_GLB_GPIO_28_LOCK_POS  (28U)
+#define GLB_TZC_GLB_GPIO_28_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_28_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_28_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_28_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_28_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_29_LOCK      GLB_TZC_GLB_GPIO_29_LOCK
+#define GLB_TZC_GLB_GPIO_29_LOCK_POS  (29U)
+#define GLB_TZC_GLB_GPIO_29_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_29_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_29_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_29_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_29_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_29_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_29_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_30_LOCK      GLB_TZC_GLB_GPIO_30_LOCK
+#define GLB_TZC_GLB_GPIO_30_LOCK_POS  (30U)
+#define GLB_TZC_GLB_GPIO_30_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_30_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_30_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_30_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_30_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_30_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_30_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_31_LOCK      GLB_TZC_GLB_GPIO_31_LOCK
+#define GLB_TZC_GLB_GPIO_31_LOCK_POS  (31U)
+#define GLB_TZC_GLB_GPIO_31_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_31_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_31_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_31_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_31_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_31_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_31_LOCK_POS))
+
+/* 0xF0C : tzc_glb_ctrl_3 */
+#define GLB_TZC_GLB_CTRL_3_OFFSET     (0xF0C)
+#define GLB_TZC_GLB_GPIO_32_LOCK      GLB_TZC_GLB_GPIO_32_LOCK
+#define GLB_TZC_GLB_GPIO_32_LOCK_POS  (0U)
+#define GLB_TZC_GLB_GPIO_32_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_32_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_32_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_32_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_32_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_32_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_32_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_33_LOCK      GLB_TZC_GLB_GPIO_33_LOCK
+#define GLB_TZC_GLB_GPIO_33_LOCK_POS  (1U)
+#define GLB_TZC_GLB_GPIO_33_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_33_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_33_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_33_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_33_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_33_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_33_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_34_LOCK      GLB_TZC_GLB_GPIO_34_LOCK
+#define GLB_TZC_GLB_GPIO_34_LOCK_POS  (2U)
+#define GLB_TZC_GLB_GPIO_34_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_34_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_34_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_34_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_34_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_34_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_34_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_35_LOCK      GLB_TZC_GLB_GPIO_35_LOCK
+#define GLB_TZC_GLB_GPIO_35_LOCK_POS  (3U)
+#define GLB_TZC_GLB_GPIO_35_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_35_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_35_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_35_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_35_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_35_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_35_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_36_LOCK      GLB_TZC_GLB_GPIO_36_LOCK
+#define GLB_TZC_GLB_GPIO_36_LOCK_POS  (4U)
+#define GLB_TZC_GLB_GPIO_36_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_36_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_36_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_36_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_36_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_36_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_36_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_37_LOCK      GLB_TZC_GLB_GPIO_37_LOCK
+#define GLB_TZC_GLB_GPIO_37_LOCK_POS  (5U)
+#define GLB_TZC_GLB_GPIO_37_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_37_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_37_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_37_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_37_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_37_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_37_LOCK_POS))
+
+struct glb_reg {
+    /* 0x0 : clk_cfg0 */
+    union {
+        struct
+        {
+            uint32_t reg_pll_en       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_fclk_en      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_hclk_en      : 1; /* [    2],        r/w,        0x1 */
+            uint32_t reg_bclk_en      : 1; /* [    3],        r/w,        0x1 */
+            uint32_t reg_pll_sel      : 2; /* [ 5: 4],        r/w,        0x0 */
+            uint32_t hbn_root_clk_sel : 2; /* [ 7: 6],          r,        0x0 */
+            uint32_t reg_hclk_div     : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t reg_bclk_div     : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t fclk_sw_state    : 3; /* [26:24],          r,        0x0 */
+            uint32_t chip_rdy         : 1; /* [   27],          r,        0x0 */
+            uint32_t glb_id           : 4; /* [31:28],          r,        0x7 */
+        } BF;
+        uint32_t WORD;
+    } clk_cfg0;
+
+    /* 0x4 : clk_cfg1 */
+    union {
+        struct
+        {
+            uint32_t qdec_clk_div            : 5; /* [ 4: 0],        r/w,       0x1f */
+            uint32_t reserved_5_6            : 2; /* [ 6: 5],       rsvd,        0x0 */
+            uint32_t qdec_clk_sel            : 1; /* [    7],        r/w,        0x0 */
+            uint32_t usb_clk_en              : 1; /* [    8],        r/w,        0x1 */
+            uint32_t dll_48m_div_en          : 1; /* [    9],        r/w,        0x1 */
+            uint32_t reserved_10_11          : 2; /* [11:10],       rsvd,        0x0 */
+            uint32_t reg_i2s_clk_sel         : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reg_i2s0_clk_en         : 1; /* [   13],        r/w,        0x0 */
+            uint32_t reg_i2s_0_ref_clk_oe    : 1; /* [   14],        r/w,        0x0 */
+            uint32_t reserved_15             : 1; /* [   15],       rsvd,        0x0 */
+            uint32_t ble_clk_sel             : 6; /* [21:16],        r/w,       0x10 */
+            uint32_t reserved_22_23          : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t ble_en                  : 1; /* [   24],        r/w,        0x1 */
+            uint32_t m154_zbEn               : 1; /* [   25],        r/w,        0x1 */
+            uint32_t reserved_26_27          : 2; /* [27:26],       rsvd,        0x0 */
+            uint32_t reg_cam_ref_clk_en      : 1; /* [   28],        r/w,        0x0 */
+            uint32_t reg_cam_ref_clk_src_sel : 1; /* [   29],        r/w,        0x0 */
+            uint32_t reg_cam_ref_clk_div     : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clk_cfg1;
+
+    /* 0x8 : clk_cfg2 */
+    union {
+        struct
+        {
+            uint32_t uart_clk_div     : 3; /* [ 2: 0],        r/w,        0x7 */
+            uint32_t reserved_3       : 1; /* [    3],       rsvd,        0x0 */
+            uint32_t uart_clk_en      : 1; /* [    4],        r/w,        0x1 */
+            uint32_t reserved_5_6     : 2; /* [ 6: 5],       rsvd,        0x0 */
+            uint32_t hbn_uart_clk_sel : 1; /* [    7],          r,        0x0 */
+            uint32_t sf_clk_div       : 3; /* [10: 8],        r/w,        0x3 */
+            uint32_t sf_clk_en        : 1; /* [   11],        r/w,        0x1 */
+            uint32_t sf_clk_sel       : 2; /* [13:12],        r/w,        0x2 */
+            uint32_t sf_clk_sel2      : 2; /* [15:14],        r/w,        0x0 */
+            uint32_t ir_clk_div       : 6; /* [21:16],        r/w,        0xf */
+            uint32_t reserved_22      : 1; /* [   22],       rsvd,        0x0 */
+            uint32_t ir_clk_en        : 1; /* [   23],        r/w,        0x1 */
+            uint32_t dma_clk_en       : 8; /* [31:24],        r/w,       0xff */
+        } BF;
+        uint32_t WORD;
+    } clk_cfg2;
+
+    /* 0xC : clk_cfg3 */
+    union {
+        struct
+        {
+            uint32_t spi_clk_div           : 5; /* [ 4: 0],        r/w,        0x3 */
+            uint32_t cfg_sel_eth_ref_clk_o : 1; /* [    5],        r/w,        0x0 */
+            uint32_t cfg_inv_eth_ref_clk_o : 1; /* [    6],        r/w,        0x1 */
+            uint32_t cfg_inv_eth_tx_clk    : 1; /* [    7],        r/w,        0x1 */
+            uint32_t spi_clk_en            : 1; /* [    8],        r/w,        0x1 */
+            uint32_t cfg_inv_rf_test_clk_o : 1; /* [    9],        r/w,        0x1 */
+            uint32_t cfg_inv_eth_rx_clk    : 1; /* [   10],        r/w,        0x1 */
+            uint32_t reserved_11_15        : 5; /* [15:11],       rsvd,        0x0 */
+            uint32_t i2c_clk_div           : 8; /* [23:16],        r/w,       0xff */
+            uint32_t i2c_clk_en            : 1; /* [   24],        r/w,        0x1 */
+            uint32_t reserved_25_27        : 3; /* [27:25],       rsvd,        0x0 */
+            uint32_t chip_clk_out_0_sel    : 2; /* [29:28],        r/w,        0x0 */
+            uint32_t chip_clk_out_1_sel    : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clk_cfg3;
+
+    /* 0x10 : swrst_cfg0 */
+    union {
+        struct
+        {
+            uint32_t swrst_s00     : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t swrst_s01     : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_3  : 2;  /* [ 3: 2],       rsvd,        0x0 */
+            uint32_t swrst_s20     : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reserved_5_7  : 3;  /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t swrst_s30     : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9_31 : 23; /* [31: 9],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } swrst_cfg0;
+
+    /* 0x14 : swrst_cfg1 */
+    union {
+        struct
+        {
+            uint32_t swrst_s10   : 1; /* [    0],        r/w,        0x0 */
+            uint32_t swrst_s11   : 1; /* [    1],        r/w,        0x0 */
+            uint32_t swrst_s12   : 1; /* [    2],        r/w,        0x0 */
+            uint32_t swrst_s13   : 1; /* [    3],        r/w,        0x0 */
+            uint32_t swrst_s14   : 1; /* [    4],        r/w,        0x0 */
+            uint32_t swrst_s15   : 1; /* [    5],        r/w,        0x0 */
+            uint32_t swrst_s16   : 1; /* [    6],        r/w,        0x0 */
+            uint32_t swrst_s17   : 1; /* [    7],        r/w,        0x0 */
+            uint32_t swrst_s18   : 1; /* [    8],        r/w,        0x0 */
+            uint32_t swrst_s19   : 1; /* [    9],        r/w,        0x0 */
+            uint32_t swrst_s1a   : 1; /* [   10],        r/w,        0x0 */
+            uint32_t swrst_s1b   : 1; /* [   11],        r/w,        0x0 */
+            uint32_t swrst_s1c   : 1; /* [   12],        r/w,        0x0 */
+            uint32_t swrst_s1d   : 1; /* [   13],        r/w,        0x0 */
+            uint32_t swrst_s1e   : 1; /* [   14],        r/w,        0x0 */
+            uint32_t swrst_s1f   : 1; /* [   15],        r/w,        0x0 */
+            uint32_t swrst_s1a0  : 1; /* [   16],        r/w,        0x0 */
+            uint32_t swrst_s1a1  : 1; /* [   17],        r/w,        0x0 */
+            uint32_t swrst_s1a2  : 1; /* [   18],        r/w,        0x0 */
+            uint32_t swrst_s1a3  : 1; /* [   19],        r/w,        0x0 */
+            uint32_t swrst_s1a4  : 1; /* [   20],        r/w,        0x0 */
+            uint32_t swrst_s1a5  : 1; /* [   21],        r/w,        0x0 */
+            uint32_t swrst_s1a6  : 1; /* [   22],        r/w,        0x0 */
+            uint32_t swrst_s1a7  : 1; /* [   23],        r/w,        0x0 */
+            uint32_t swrst_s1a8  : 1; /* [   24],        r/w,        0x0 */
+            uint32_t swrst_s1a9  : 1; /* [   25],        r/w,        0x0 */
+            uint32_t swrst_s1aa  : 1; /* [   26],        r/w,        0x0 */
+            uint32_t swrst_s1ab  : 1; /* [   27],        r/w,        0x0 */
+            uint32_t swrst_s1ac  : 1; /* [   28],        r/w,        0x0 */
+            uint32_t swrst_s1ad  : 1; /* [   29],        r/w,        0x0 */
+            uint32_t swrst_s1ae  : 1; /* [   30],        r/w,        0x0 */
+            uint32_t reserved_31 : 1; /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } swrst_cfg1;
+
+    /* 0x18 : swrst_cfg2 */
+    union {
+        struct
+        {
+            uint32_t reg_ctrl_pwron_rst   : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_ctrl_cpu_reset   : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reg_ctrl_sys_reset   : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3           : 1;  /* [    3],       rsvd,        0x0 */
+            uint32_t reg_ctrl_reset_dummy : 4;  /* [ 7: 4],        r/w,        0x0 */
+            uint32_t reserved_8_23        : 16; /* [23: 8],       rsvd,        0x0 */
+            uint32_t pka_clk_sel          : 1;  /* [   24],        r/w,        0x0 */
+            uint32_t reserved_25_31       : 7;  /* [31:25],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } swrst_cfg2;
+
+    /* 0x1C : swrst_cfg3 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } swrst_cfg3;
+
+    /* 0x20 : cgen_cfg0 */
+    union {
+        struct
+        {
+            uint32_t cgen_m        : 8;  /* [ 7: 0],        r/w,       0xff */
+            uint32_t reserved_8_31 : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cgen_cfg0;
+
+    /* 0x24 : cgen_cfg1 */
+    union {
+        struct
+        {
+            uint32_t cgen_s1  : 16; /* [15: 0],        r/w,     0xcfff */
+            uint32_t cgen_s1a : 16; /* [31:16],        r/w,     0x9b23 */
+        } BF;
+        uint32_t WORD;
+    } cgen_cfg1;
+
+    /* 0x28 : cgen_cfg2 */
+    union {
+        struct
+        {
+            uint32_t cgen_s2       : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3  : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t cgen_s3       : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reserved_5_31 : 27; /* [31: 5],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cgen_cfg2;
+
+    /* 0x2C : cgen_cfg3 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cgen_cfg3;
+
+    /* 0x30 : MBIST_CTL */
+    union {
+        struct
+        {
+            uint32_t irom_mbist_mode        : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t hsram_mem_mbist_mode   : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t hsram_cache_mbist_mode : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t tag_mbist_mode         : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t ocram_mbist_mode       : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t em_ram_mbist_mode      : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_30          : 25; /* [30: 6],       rsvd,        0x0 */
+            uint32_t reg_mbist_rst_n        : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } MBIST_CTL;
+
+    /* 0x34 : MBIST_STAT */
+    union {
+        struct
+        {
+            uint32_t irom_mbist_done        : 1;  /* [    0],          r,        0x0 */
+            uint32_t hsram_mem_mbist_done   : 1;  /* [    1],          r,        0x0 */
+            uint32_t hsram_cache_mbist_done : 1;  /* [    2],          r,        0x0 */
+            uint32_t tag_mbist_done         : 1;  /* [    3],          r,        0x0 */
+            uint32_t ocram_mbist_done       : 1;  /* [    4],          r,        0x0 */
+            uint32_t em_ram_mbist_done      : 1;  /* [    5],          r,        0x0 */
+            uint32_t reserved_6_15          : 10; /* [15: 6],       rsvd,        0x0 */
+            uint32_t irom_mbist_fail        : 1;  /* [   16],          r,        0x0 */
+            uint32_t hsram_mem_mbist_fail   : 1;  /* [   17],          r,        0x0 */
+            uint32_t hsram_cache_mbist_fail : 1;  /* [   18],          r,        0x0 */
+            uint32_t tag_mbist_fail         : 1;  /* [   19],          r,        0x0 */
+            uint32_t ocram_mbist_fail       : 1;  /* [   20],          r,        0x0 */
+            uint32_t em_ram_mbist_fail      : 1;  /* [   21],          r,        0x0 */
+            uint32_t reserved_22_31         : 10; /* [31:22],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } MBIST_STAT;
+
+    /* 0x38  reserved */
+    uint8_t RESERVED0x38[24];
+
+    /* 0x50 : bmx_cfg1 */
+    union {
+        struct
+        {
+            uint32_t bmx_timeout_en      : 4; /* [ 3: 0],        r/w,        0x0 */
+            uint32_t bmx_arb_mode        : 2; /* [ 5: 4],        r/w,        0x0 */
+            uint32_t reserved_6_7        : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t bmx_err_en          : 1; /* [    8],        r/w,        0x0 */
+            uint32_t bmx_busy_option_dis : 1; /* [    9],        r/w,        0x0 */
+            uint32_t bmx_gating_dis      : 1; /* [   10],        r/w,        0x0 */
+            uint32_t reserved_11         : 1; /* [   11],       rsvd,        0x0 */
+            uint32_t hsel_option         : 4; /* [15:12],        r/w,        0x0 */
+            uint32_t pds_apb_cfg         : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t hbn_apb_cfg         : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } bmx_cfg1;
+
+    /* 0x54 : bmx_cfg2 */
+    union {
+        struct
+        {
+            uint32_t bmx_err_addr_dis : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3     : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t bmx_err_dec      : 1;  /* [    4],          r,        0x0 */
+            uint32_t bmx_err_tz       : 1;  /* [    5],          r,        0x0 */
+            uint32_t reserved_6_7     : 2;  /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_w_thre_bmx   : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reg_w_thre_l1c   : 2;  /* [11:10],        r/w,        0x0 */
+            uint32_t reserved_12_27   : 16; /* [27:12],       rsvd,        0x0 */
+            uint32_t bmx_dbg_sel      : 4;  /* [31:28],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } bmx_cfg2;
+
+    /* 0x58 : bmx_err_addr */
+    union {
+        struct
+        {
+            uint32_t bmx_err_addr : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } bmx_err_addr;
+
+    /* 0x5C : bmx_dbg_out */
+    union {
+        struct
+        {
+            uint32_t bmx_dbg_out : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } bmx_dbg_out;
+
+    /* 0x60 : rsv0 */
+    union {
+        struct
+        {
+            uint32_t rsvd_31_0 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } rsv0;
+
+    /* 0x64 : rsv1 */
+    union {
+        struct
+        {
+            uint32_t rsvd_31_0 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } rsv1;
+
+    /* 0x68 : rsv2 */
+    union {
+        struct
+        {
+            uint32_t rsvd_31_0 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } rsv2;
+
+    /* 0x6C : rsv3 */
+    union {
+        struct
+        {
+            uint32_t rsvd_31_0 : 32; /* [31: 0],       rsvd, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } rsv3;
+
+    /* 0x70 : sram_ret */
+    union {
+        struct
+        {
+            uint32_t reg_sram_ret : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sram_ret;
+
+    /* 0x74 : sram_slp */
+    union {
+        struct
+        {
+            uint32_t reg_sram_slp : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sram_slp;
+
+    /* 0x78 : sram_parm */
+    union {
+        struct
+        {
+            uint32_t reg_sram_parm : 32; /* [31: 0],        r/w, 0x6a4c0c0c */
+        } BF;
+        uint32_t WORD;
+    } sram_parm;
+
+    /* 0x7C : seam_misc */
+    union {
+        struct
+        {
+            uint32_t em_sel        : 4;  /* [ 3: 0],        r/w,        0x3 */
+            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } seam_misc;
+
+    /* 0x80 : glb_parm */
+    union {
+        struct
+        {
+            uint32_t jtag_swap_set            : 8; /* [ 7: 0],        r/w,        0x4 */
+            uint32_t cfg_sflash2_swap_io0_io3 : 1; /* [    8],        r/w,        0x0 */
+            uint32_t cfg_sflash2_swap_cs_io2  : 1; /* [    9],        r/w,        0x0 */
+            uint32_t cfg_flash_scenario       : 2; /* [11:10],        r/w,        0x0 */
+            uint32_t reg_spi_0_master_mode    : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reg_spi_0_swap           : 1; /* [   13],        r/w,        0x0 */
+            uint32_t reserved_14_15           : 2; /* [15:14],       rsvd,        0x0 */
+            uint32_t reg_cci_use_jtag_pin     : 1; /* [   16],        r/w,        0x1 */
+            uint32_t p1_adc_test_with_cci     : 1; /* [   17],        r/w,        0x0 */
+            uint32_t p2_dac_test_with_cci     : 1; /* [   18],        r/w,        0x0 */
+            uint32_t p3_cci_use_io_0_2_7      : 1; /* [   19],        r/w,        0x0 */
+            uint32_t p4_adc_test_with_jtag    : 1; /* [   20],        r/w,        0x0 */
+            uint32_t p5_dac_test_with_jtag    : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22              : 1; /* [   22],       rsvd,        0x0 */
+            uint32_t p6_jtag_use_io_0_2_7     : 1; /* [   23],        r/w,        0x0 */
+            uint32_t uart_swap_set            : 4; /* [27:24],        r/w,        0x0 */
+            uint32_t reserved_28              : 1; /* [   28],       rsvd,        0x0 */
+            uint32_t reg_kys_drv_val          : 1; /* [   29],        r/w,        0x0 */
+            uint32_t reg_ext_rst_smt          : 1; /* [   30],        r/w,        0x0 */
+            uint32_t pin_sel_emac_cam         : 1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } glb_parm;
+
+    /* 0x84 : PDM_CLK_CTRL */
+    union {
+        struct
+        {
+            uint32_t reg_pdm0_clk_div : 6;  /* [ 5: 0],        r/w,        0x1 */
+            uint32_t reserved_6       : 1;  /* [    6],       rsvd,        0x0 */
+            uint32_t reg_pdm0_clk_en  : 1;  /* [    7],        r/w,        0x1 */
+            uint32_t reserved_8_31    : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } PDM_CLK_CTRL;
+
+    /* 0x88 : GPIO_USE_PSRAM__IO */
+    union {
+        struct
+        {
+            uint32_t cfg_gpio_use_psram_io : 6;  /* [ 5: 0],        r/w,        0x0 */
+            uint32_t reserved_6_31         : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_USE_PSRAM__IO;
+
+    /* 0x8c  reserved */
+    uint8_t RESERVED0x8c[4];
+
+    /* 0x90 : CPU_CLK_CFG */
+    union {
+        struct
+        {
+            uint32_t cpu_rtc_div        : 17; /* [16: 0],        r/w,       0x10 */
+            uint32_t reserved_17        : 1;  /* [   17],       rsvd,        0x0 */
+            uint32_t cpu_rtc_en         : 1;  /* [   18],        r/w,        0x0 */
+            uint32_t cpu_rtc_sel        : 1;  /* [   19],        r/w,        0x1 */
+            uint32_t debug_ndreset_gate : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t reserved_21_31     : 11; /* [31:21],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } CPU_CLK_CFG;
+
+    /* 0x94  reserved */
+    uint8_t RESERVED0x94[16];
+
+    /* 0xA4 : GPADC_32M_SRC_CTRL */
+    union {
+        struct
+        {
+            uint32_t gpadc_32m_clk_div : 6;  /* [ 5: 0],        r/w,        0x2 */
+            uint32_t reserved_6        : 1;  /* [    6],       rsvd,        0x0 */
+            uint32_t gpadc_32m_clk_sel : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t gpadc_32m_div_en  : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t reserved_9_31     : 23; /* [31: 9],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPADC_32M_SRC_CTRL;
+
+    /* 0xA8 : DIG32K_WAKEUP_CTRL */
+    union {
+        struct
+        {
+            uint32_t dig_32k_div            : 11; /* [10: 0],        r/w,      0x3e8 */
+            uint32_t reserved_11            : 1;  /* [   11],       rsvd,        0x0 */
+            uint32_t dig_32k_en             : 1;  /* [   12],        r/w,        0x1 */
+            uint32_t dig_32k_comp           : 1;  /* [   13],        r/w,        0x0 */
+            uint32_t reserved_14_15         : 2;  /* [15:14],       rsvd,        0x0 */
+            uint32_t dig_512k_div           : 7;  /* [22:16],        r/w,       0x3e */
+            uint32_t reserved_23            : 1;  /* [   23],       rsvd,        0x0 */
+            uint32_t dig_512k_en            : 1;  /* [   24],        r/w,        0x1 */
+            uint32_t dig_512k_comp          : 1;  /* [   25],        r/w,        0x1 */
+            uint32_t reserved_26_27         : 2;  /* [27:26],       rsvd,        0x0 */
+            uint32_t dig_clk_src_sel        : 2;  /* [29:28],        r/w,        0x0 */
+            uint32_t reserved_30            : 1;  /* [   30],       rsvd,        0x0 */
+            uint32_t reg_en_platform_wakeup : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DIG32K_WAKEUP_CTRL;
+
+    /* 0xAC : WIFI_BT_COEX_CTRL */
+    union {
+        struct
+        {
+            uint32_t coex_bt_channel : 7;  /* [ 6: 0],        r/w,        0x0 */
+            uint32_t coex_bt_pti     : 4;  /* [10: 7],        r/w,        0x0 */
+            uint32_t coex_bt_bw      : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t en_gpio_bt_coex : 1;  /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13_31  : 19; /* [31:13],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } WIFI_BT_COEX_CTRL;
+
+    /* 0xB0 : BZ_COEX_CTRL */
+    union {
+        struct
+        {
+            uint32_t coex_en           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t wlan_en           : 1; /* [    1],        r/w,        0x0 */
+            uint32_t ble_rx_ignore     : 1; /* [    2],        r/w,        0x0 */
+            uint32_t m154_rx_ignore    : 1; /* [    3],        r/w,        0x0 */
+            uint32_t bz_pri_thr        : 4; /* [ 7: 4],        r/w,        0x0 */
+            uint32_t bz_pri_en         : 1; /* [    8],        r/w,        0x1 */
+            uint32_t bz_pri_pol        : 1; /* [    9],        r/w,        0x1 */
+            uint32_t bz_active_pol     : 1; /* [   10],        r/w,        0x1 */
+            uint32_t bz_abort_pol      : 1; /* [   11],        r/w,        0x1 */
+            uint32_t coex_pri          : 1; /* [   12],        r/w,        0x0 */
+            uint32_t force_m154_win    : 1; /* [   13],        r/w,        0x0 */
+            uint32_t force_ble_win     : 1; /* [   14],        r/w,        0x0 */
+            uint32_t coex_option       : 1; /* [   15],        r/w,        0x0 */
+            uint32_t coex_force_ch     : 7; /* [22:16],        r/w,        0x4 */
+            uint32_t reserved_23       : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t m154_rx_abort_dis : 1; /* [   24],        r/w,        0x0 */
+            uint32_t m154_tx_abort_dis : 1; /* [   25],        r/w,        0x0 */
+            uint32_t ble_rx_abort_dis  : 1; /* [   26],        r/w,        0x0 */
+            uint32_t ble_tx_abort_dis  : 1; /* [   27],        r/w,        0x0 */
+            uint32_t coex_arb          : 4; /* [31:28],          r,        0x8 */
+        } BF;
+        uint32_t WORD;
+    } BZ_COEX_CTRL;
+
+    /* 0xb4  reserved */
+    uint8_t RESERVED0xb4[12];
+
+    /* 0xC0 : UART_SIG_SEL_0 */
+    union {
+        struct
+        {
+            uint32_t uart_sig_0_sel : 4; /* [ 3: 0],        r/w,        0x0 */
+            uint32_t uart_sig_1_sel : 4; /* [ 7: 4],        r/w,        0x1 */
+            uint32_t uart_sig_2_sel : 4; /* [11: 8],        r/w,        0x2 */
+            uint32_t uart_sig_3_sel : 4; /* [15:12],        r/w,        0x3 */
+            uint32_t uart_sig_4_sel : 4; /* [19:16],        r/w,        0x4 */
+            uint32_t uart_sig_5_sel : 4; /* [23:20],        r/w,        0x5 */
+            uint32_t uart_sig_6_sel : 4; /* [27:24],        r/w,        0x6 */
+            uint32_t uart_sig_7_sel : 4; /* [31:28],        r/w,        0x7 */
+        } BF;
+        uint32_t WORD;
+    } UART_SIG_SEL_0;
+
+    /* 0xc4  reserved */
+    uint8_t RESERVED0xc4[12];
+
+    /* 0xD0 : DBG_SEL_LL */
+    union {
+        struct
+        {
+            uint32_t reg_dbg_ll_ctrl : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DBG_SEL_LL;
+
+    /* 0xD4 : DBG_SEL_LH */
+    union {
+        struct
+        {
+            uint32_t reg_dbg_lh_ctrl : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DBG_SEL_LH;
+
+    /* 0xD8 : DBG_SEL_HL */
+    union {
+        struct
+        {
+            uint32_t reg_dbg_hl_ctrl : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DBG_SEL_HL;
+
+    /* 0xDC : DBG_SEL_HH */
+    union {
+        struct
+        {
+            uint32_t reg_dbg_hh_ctrl : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DBG_SEL_HH;
+
+    /* 0xE0 : debug */
+    union {
+        struct
+        {
+            uint32_t debug_oe : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t debug_i  : 31; /* [31: 1],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } debug;
+
+    /* 0xe4  reserved */
+    uint8_t RESERVED0xe4[28];
+
+    /* 0x100 : GPIO_CFGCTL0 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_0_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_0_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_0_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_0_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_0_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7        : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_0_func_sel : 5; /* [12: 8],        r/w,        0xe */
+            uint32_t reserved_13_15      : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_1_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_1_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_1_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_1_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_1_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23      : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_1_func_sel : 5; /* [28:24],        r/w,        0xe */
+            uint32_t reserved_29_31      : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL0;
+
+    /* 0x104 : GPIO_CFGCTL1 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_2_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_2_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_2_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_2_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_2_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7        : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_2_func_sel : 5; /* [12: 8],        r/w,        0xe */
+            uint32_t reserved_13_15      : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_3_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_3_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_3_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_3_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_3_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23      : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_3_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31      : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL1;
+
+    /* 0x108 : GPIO_CFGCTL2 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_4_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_4_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_4_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_4_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_4_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7        : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_4_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15      : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_5_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_5_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_5_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_5_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_5_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23      : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_5_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31      : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL2;
+
+    /* 0x10C : GPIO_CFGCTL3 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_6_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_6_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_6_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_6_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_6_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7        : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_6_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15      : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_7_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_7_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_7_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_7_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_7_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23      : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_7_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31      : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL3;
+
+    /* 0x110 : GPIO_CFGCTL4 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_8_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_8_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_8_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_8_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_8_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7        : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_8_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15      : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_9_ie       : 1; /* [   16],        r/w,        0x0 */
+            uint32_t reg_gpio_9_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_9_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_9_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_9_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23      : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_9_func_sel : 5; /* [28:24],        r/w,        0xe */
+            uint32_t reserved_29_31      : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL4;
+
+    /* 0x114 : GPIO_CFGCTL5 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_10_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_10_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_10_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_10_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_10_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_10_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_11_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_11_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_11_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_11_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_11_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_11_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL5;
+
+    /* 0x118 : GPIO_CFGCTL6 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_12_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_12_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_12_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_12_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_12_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_12_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_13_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_13_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_13_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_13_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_13_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_13_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL6;
+
+    /* 0x11C : GPIO_CFGCTL7 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_14_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_14_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_14_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_14_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_14_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_14_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_15_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_15_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_15_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_15_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_15_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_15_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL7;
+
+    /* 0x120 : GPIO_CFGCTL8 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_16_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_16_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_16_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_16_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_16_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_16_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_17_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_17_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_17_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_17_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_17_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_17_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL8;
+
+    /* 0x124 : GPIO_CFGCTL9 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_18_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_18_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_18_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_18_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_18_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_18_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_19_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_19_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_19_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_19_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_19_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_19_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL9;
+
+    /* 0x128 : GPIO_CFGCTL10 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_20_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_20_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_20_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_20_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_20_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_20_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_21_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_21_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_21_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_21_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_21_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_21_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL10;
+
+    /* 0x12C : GPIO_CFGCTL11 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_22_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_22_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_22_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_22_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_22_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_22_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_23_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_23_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_23_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_23_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_23_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_23_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL11;
+
+    /* 0x130 : GPIO_CFGCTL12 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_24_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_24_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_24_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_24_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_24_pd       : 1; /* [    5],        r/w,        0x1 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_24_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_25_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_25_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_25_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_25_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_25_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_25_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL12;
+
+    /* 0x134 : GPIO_CFGCTL13 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_26_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_26_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_26_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_26_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_26_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_26_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_27_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_27_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_27_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_27_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_27_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_27_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL13;
+
+    /* 0x138 : GPIO_CFGCTL14 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_28_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_28_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_28_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_28_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_28_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_28_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_29_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_29_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_29_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_29_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_29_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_29_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL14;
+
+    /* 0x13C : GPIO_CFGCTL15 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_30_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_30_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_30_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_30_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_30_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_30_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_31_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_31_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_31_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_31_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_31_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_31_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL15;
+
+    /* 0x140 : GPIO_CFGCTL16 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_32_ie  : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_32_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_32_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_32_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_32_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_15   : 10; /* [15: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_33_ie  : 1;  /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_33_smt : 1;  /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_33_drv : 2;  /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_33_pu  : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_33_pd  : 1;  /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_31  : 10; /* [31:22],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL16;
+
+    /* 0x144 : GPIO_CFGCTL17 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_34_ie  : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_34_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_34_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_34_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_34_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_15   : 10; /* [15: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_35_ie  : 1;  /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_35_smt : 1;  /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_35_drv : 2;  /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_35_pu  : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_35_pd  : 1;  /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_31  : 10; /* [31:22],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL17;
+
+    /* 0x148 : GPIO_CFGCTL18 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_36_ie  : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_36_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_36_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_36_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_36_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_15   : 10; /* [15: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_37_ie  : 1;  /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_37_smt : 1;  /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_37_drv : 2;  /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_37_pu  : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_37_pd  : 1;  /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_31  : 10; /* [31:22],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL18;
+
+    /* 0x14c  reserved */
+    uint8_t RESERVED0x14c[52];
+
+    /* 0x180 : GPIO_CFGCTL30 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_0_i  : 1; /* [    0],          r,        0x0 */
+            uint32_t reg_gpio_1_i  : 1; /* [    1],          r,        0x0 */
+            uint32_t reg_gpio_2_i  : 1; /* [    2],          r,        0x0 */
+            uint32_t reg_gpio_3_i  : 1; /* [    3],          r,        0x0 */
+            uint32_t reg_gpio_4_i  : 1; /* [    4],          r,        0x0 */
+            uint32_t reg_gpio_5_i  : 1; /* [    5],          r,        0x0 */
+            uint32_t reg_gpio_6_i  : 1; /* [    6],          r,        0x0 */
+            uint32_t reg_gpio_7_i  : 1; /* [    7],          r,        0x0 */
+            uint32_t reg_gpio_8_i  : 1; /* [    8],          r,        0x0 */
+            uint32_t reg_gpio_9_i  : 1; /* [    9],          r,        0x0 */
+            uint32_t reg_gpio_10_i : 1; /* [   10],          r,        0x0 */
+            uint32_t reg_gpio_11_i : 1; /* [   11],          r,        0x0 */
+            uint32_t reg_gpio_12_i : 1; /* [   12],          r,        0x0 */
+            uint32_t reg_gpio_13_i : 1; /* [   13],          r,        0x0 */
+            uint32_t reg_gpio_14_i : 1; /* [   14],          r,        0x0 */
+            uint32_t reg_gpio_15_i : 1; /* [   15],          r,        0x0 */
+            uint32_t reg_gpio_16_i : 1; /* [   16],          r,        0x0 */
+            uint32_t reg_gpio_17_i : 1; /* [   17],          r,        0x0 */
+            uint32_t reg_gpio_18_i : 1; /* [   18],          r,        0x0 */
+            uint32_t reg_gpio_19_i : 1; /* [   19],          r,        0x0 */
+            uint32_t reg_gpio_20_i : 1; /* [   20],          r,        0x0 */
+            uint32_t reg_gpio_21_i : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_22_i : 1; /* [   22],          r,        0x0 */
+            uint32_t reg_gpio_23_i : 1; /* [   23],          r,        0x0 */
+            uint32_t reg_gpio_24_i : 1; /* [   24],          r,        0x0 */
+            uint32_t reg_gpio_25_i : 1; /* [   25],          r,        0x0 */
+            uint32_t reg_gpio_26_i : 1; /* [   26],          r,        0x0 */
+            uint32_t reg_gpio_27_i : 1; /* [   27],          r,        0x0 */
+            uint32_t reg_gpio_28_i : 1; /* [   28],          r,        0x0 */
+            uint32_t reg_gpio_29_i : 1; /* [   29],          r,        0x0 */
+            uint32_t reg_gpio_30_i : 1; /* [   30],          r,        0x0 */
+            uint32_t reg_gpio_31_i : 1; /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL30;
+
+    /* 0x184 : GPIO_CFGCTL31 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL31;
+
+    /* 0x188 : GPIO_CFGCTL32 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_0_o  : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_1_o  : 1; /* [    1],        r/w,        0x0 */
+            uint32_t reg_gpio_2_o  : 1; /* [    2],        r/w,        0x0 */
+            uint32_t reg_gpio_3_o  : 1; /* [    3],        r/w,        0x0 */
+            uint32_t reg_gpio_4_o  : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_5_o  : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_6_o  : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reg_gpio_7_o  : 1; /* [    7],        r/w,        0x0 */
+            uint32_t reg_gpio_8_o  : 1; /* [    8],        r/w,        0x0 */
+            uint32_t reg_gpio_9_o  : 1; /* [    9],        r/w,        0x0 */
+            uint32_t reg_gpio_10_o : 1; /* [   10],        r/w,        0x0 */
+            uint32_t reg_gpio_11_o : 1; /* [   11],        r/w,        0x0 */
+            uint32_t reg_gpio_12_o : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reg_gpio_13_o : 1; /* [   13],        r/w,        0x0 */
+            uint32_t reg_gpio_14_o : 1; /* [   14],        r/w,        0x0 */
+            uint32_t reg_gpio_15_o : 1; /* [   15],        r/w,        0x0 */
+            uint32_t reg_gpio_16_o : 1; /* [   16],        r/w,        0x0 */
+            uint32_t reg_gpio_17_o : 1; /* [   17],        r/w,        0x0 */
+            uint32_t reg_gpio_18_o : 1; /* [   18],        r/w,        0x0 */
+            uint32_t reg_gpio_19_o : 1; /* [   19],        r/w,        0x0 */
+            uint32_t reg_gpio_20_o : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_21_o : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reg_gpio_22_o : 1; /* [   22],        r/w,        0x0 */
+            uint32_t reg_gpio_23_o : 1; /* [   23],        r/w,        0x0 */
+            uint32_t reg_gpio_24_o : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_25_o : 1; /* [   25],        r/w,        0x0 */
+            uint32_t reg_gpio_26_o : 1; /* [   26],        r/w,        0x0 */
+            uint32_t reg_gpio_27_o : 1; /* [   27],        r/w,        0x0 */
+            uint32_t reg_gpio_28_o : 1; /* [   28],        r/w,        0x0 */
+            uint32_t reg_gpio_29_o : 1; /* [   29],        r/w,        0x0 */
+            uint32_t reg_gpio_30_o : 1; /* [   30],        r/w,        0x0 */
+            uint32_t reg_gpio_31_o : 1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL32;
+
+    /* 0x18C : GPIO_CFGCTL33 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL33;
+
+    /* 0x190 : GPIO_CFGCTL34 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_0_oe  : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_1_oe  : 1; /* [    1],        r/w,        0x0 */
+            uint32_t reg_gpio_2_oe  : 1; /* [    2],        r/w,        0x0 */
+            uint32_t reg_gpio_3_oe  : 1; /* [    3],        r/w,        0x0 */
+            uint32_t reg_gpio_4_oe  : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_5_oe  : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_6_oe  : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reg_gpio_7_oe  : 1; /* [    7],        r/w,        0x0 */
+            uint32_t reg_gpio_8_oe  : 1; /* [    8],        r/w,        0x0 */
+            uint32_t reg_gpio_9_oe  : 1; /* [    9],        r/w,        0x0 */
+            uint32_t reg_gpio_10_oe : 1; /* [   10],        r/w,        0x0 */
+            uint32_t reg_gpio_11_oe : 1; /* [   11],        r/w,        0x0 */
+            uint32_t reg_gpio_12_oe : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reg_gpio_13_oe : 1; /* [   13],        r/w,        0x0 */
+            uint32_t reg_gpio_14_oe : 1; /* [   14],        r/w,        0x0 */
+            uint32_t reg_gpio_15_oe : 1; /* [   15],        r/w,        0x0 */
+            uint32_t reg_gpio_16_oe : 1; /* [   16],        r/w,        0x0 */
+            uint32_t reg_gpio_17_oe : 1; /* [   17],        r/w,        0x0 */
+            uint32_t reg_gpio_18_oe : 1; /* [   18],        r/w,        0x0 */
+            uint32_t reg_gpio_19_oe : 1; /* [   19],        r/w,        0x0 */
+            uint32_t reg_gpio_20_oe : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_21_oe : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reg_gpio_22_oe : 1; /* [   22],        r/w,        0x0 */
+            uint32_t reg_gpio_23_oe : 1; /* [   23],        r/w,        0x0 */
+            uint32_t reg_gpio_24_oe : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_25_oe : 1; /* [   25],        r/w,        0x0 */
+            uint32_t reg_gpio_26_oe : 1; /* [   26],        r/w,        0x0 */
+            uint32_t reg_gpio_27_oe : 1; /* [   27],        r/w,        0x0 */
+            uint32_t reg_gpio_28_oe : 1; /* [   28],        r/w,        0x0 */
+            uint32_t reg_gpio_29_oe : 1; /* [   29],        r/w,        0x0 */
+            uint32_t reg_gpio_30_oe : 1; /* [   30],        r/w,        0x0 */
+            uint32_t reg_gpio_31_oe : 1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL34;
+
+    /* 0x194 : GPIO_CFGCTL35 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL35;
+
+    /* 0x198  reserved */
+    uint8_t RESERVED0x198[8];
+
+    /* 0x1A0 : GPIO_INT_MASK1 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int_mask1 : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT_MASK1;
+
+    /* 0x1a4  reserved */
+    uint8_t RESERVED0x1a4[4];
+
+    /* 0x1A8 : GPIO_INT_STAT1 */
+    union {
+        struct
+        {
+            uint32_t gpio_int_stat1 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT_STAT1;
+
+    /* 0x1ac  reserved */
+    uint8_t RESERVED0x1ac[4];
+
+    /* 0x1B0 : GPIO_INT_CLR1 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int_clr1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT_CLR1;
+
+    /* 0x1b4  reserved */
+    uint8_t RESERVED0x1b4[12];
+
+    /* 0x1C0 : GPIO_INT_MODE_SET1 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int_mode_set1 : 30; /* [29: 0],        r/w,        0x0 */
+            uint32_t reserved_30_31         : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT_MODE_SET1;
+
+    /* 0x1C4 : GPIO_INT_MODE_SET2 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int_mode_set2 : 30; /* [29: 0],        r/w,        0x0 */
+            uint32_t reserved_30_31         : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT_MODE_SET2;
+
+    /* 0x1C8 : GPIO_INT_MODE_SET3 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int_mode_set3 : 30; /* [29: 0],        r/w,        0x0 */
+            uint32_t reserved_30_31         : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT_MODE_SET3;
+
+    /* 0x1CC : GPIO_INT_MODE_SET4 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int_mode_set4 : 6;  /* [ 5: 0],        r/w,        0x0 */
+            uint32_t reserved_6_31          : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT_MODE_SET4;
+
+    /* 0x1D0 : GPIO_INT2_MASK1 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int2_mask1 : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT2_MASK1;
+
+    /* 0x1D4 : GPIO_INT2_STAT1 */
+    union {
+        struct
+        {
+            uint32_t gpio_int2_stat1 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT2_STAT1;
+
+    /* 0x1D8 : GPIO_INT2_CLR1 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int2_clr1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT2_CLR1;
+
+    /* 0x1DC : GPIO_INT2_MODE_SET1 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int2_mode_set1 : 30; /* [29: 0],        r/w,        0x0 */
+            uint32_t reserved_30_31          : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT2_MODE_SET1;
+
+    /* 0x1E0 : GPIO_INT2_MODE_SET2 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int2_mode_set2 : 30; /* [29: 0],        r/w,        0x0 */
+            uint32_t reserved_30_31          : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT2_MODE_SET2;
+
+    /* 0x1E4 : GPIO_INT2_MODE_SET3 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int2_mode_set3 : 30; /* [29: 0],        r/w,        0x0 */
+            uint32_t reserved_30_31          : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT2_MODE_SET3;
+
+    /* 0x1E8 : GPIO_INT2_MODE_SET4 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int2_mode_set4 : 6;  /* [ 5: 0],        r/w,        0x0 */
+            uint32_t reserved_6_31           : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT2_MODE_SET4;
+
+    /* 0x1ec  reserved */
+    uint8_t RESERVED0x1ec[20];
+
+    /* 0x200 : dll */
+    union {
+        struct
+        {
+            uint32_t dtest_en_dll_refclk : 1; /* [    0],        r/w,        0x0 */
+            uint32_t dtest_en_dll_outclk : 1; /* [    1],        r/w,        0x0 */
+            uint32_t ten_dll             : 1; /* [    2],        r/w,        0x0 */
+            uint32_t dll_clk_mmdiv_en    : 1; /* [    3],        r/w,        0x0 */
+            uint32_t dll_clk_288M_en     : 1; /* [    4],        r/w,        0x1 */
+            uint32_t dll_clk_144M_en     : 1; /* [    5],        r/w,        0x1 */
+            uint32_t dll_clk_96M_en      : 1; /* [    6],        r/w,        0x1 */
+            uint32_t dll_clk_57p6M_en    : 1; /* [    7],        r/w,        0x1 */
+            uint32_t dll_vctrl_sel       : 3; /* [10: 8],        r/w,        0x4 */
+            uint32_t reserved_11         : 1; /* [   11],       rsvd,        0x0 */
+            uint32_t dll_prechg_sel      : 1; /* [   12],        r/w,        0x0 */
+            uint32_t dll_prechg_reg      : 1; /* [   13],        r/w,        0x1 */
+            uint32_t dll_prechg_en       : 1; /* [   14],        r/w,        0x1 */
+            uint32_t dll_vctrl_force_en  : 1; /* [   15],        r/w,        0x0 */
+            uint32_t dll_post_div        : 4; /* [19:16],        r/w,        0x2 */
+            uint32_t dll_delay_sel       : 2; /* [21:20],        r/w,        0x1 */
+            uint32_t dll_cp_op_en        : 1; /* [   22],        r/w,        0x1 */
+            uint32_t dll_cp_hiz          : 1; /* [   23],        r/w,        0x0 */
+            uint32_t reserved_24_27      : 4; /* [27:24],       rsvd,        0x0 */
+            uint32_t dll_refclk_sel      : 1; /* [   28],        r/w,        0x0 */
+            uint32_t dll_reset           : 1; /* [   29],        r/w,        0x1 */
+            uint32_t pu_dll              : 1; /* [   30],        r/w,        0x0 */
+            uint32_t ppu_dll             : 1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dll;
+
+    /* 0x204  reserved */
+    uint8_t RESERVED0x204[32];
+
+    /* 0x224 : led_driver */
+    union {
+        struct
+        {
+            uint32_t led_din_reg          : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t led_din_sel          : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t led_din_polarity_sel : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3           : 1;  /* [    3],       rsvd,        0x0 */
+            uint32_t leddrv_ibias         : 4;  /* [ 7: 4],        r/w,        0x8 */
+            uint32_t ir_rx_gpio_sel       : 4;  /* [11: 8],        r/w,        0x0 */
+            uint32_t reserved_12_27       : 16; /* [27:12],       rsvd,        0x0 */
+            uint32_t leddrv_out_en        : 2;  /* [29:28],        r/w,        0x3 */
+            uint32_t reserved_30          : 1;  /* [   30],       rsvd,        0x0 */
+            uint32_t pu_leddrv            : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } led_driver;
+
+    /* 0x228 : usb_xcvr */
+    union {
+        struct
+        {
+            uint32_t usb_ldo_vfb      : 3; /* [ 2: 0],        r/w,        0x3 */
+            uint32_t pu_usb_ldo       : 1; /* [    3],        r/w,        0x0 */
+            uint32_t usb_rout_nmos    : 3; /* [ 6: 4],        r/w,        0x3 */
+            uint32_t reserved_7       : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t usb_rout_pmos    : 3; /* [10: 8],        r/w,        0x3 */
+            uint32_t reserved_11      : 1; /* [   11],       rsvd,        0x0 */
+            uint32_t usb_oeb_sel      : 1; /* [   12],         rw,        0x0 */
+            uint32_t usb_oeb_reg      : 1; /* [   13],         rw,        0x1 */
+            uint32_t usb_oeb          : 1; /* [   14],          r,        0x1 */
+            uint32_t reserved_15      : 1; /* [   15],       rsvd,        0x0 */
+            uint32_t usb_data_convert : 1; /* [   16],         rw,        0x0 */
+            uint32_t reserved_17_19   : 3; /* [19:17],       rsvd,        0x0 */
+            uint32_t usb_enum         : 1; /* [   20],        r/w,        0x0 */
+            uint32_t usb_spd          : 1; /* [   21],        r/w,        0x1 */
+            uint32_t usb_sus          : 1; /* [   22],        r/w,        0x0 */
+            uint32_t pu_usb           : 1; /* [   23],        r/w,        0x0 */
+            uint32_t usb_bd           : 1; /* [   24],          r,        0x0 */
+            uint32_t usb_vim          : 1; /* [   25],          r,        0x0 */
+            uint32_t usb_vip          : 1; /* [   26],          r,        0x0 */
+            uint32_t usb_rcv          : 1; /* [   27],          r,        0x0 */
+            uint32_t reserved_28_31   : 4; /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } usb_xcvr;
+
+    /* 0x22C : usb_xcvr_config */
+    union {
+        struct
+        {
+            uint32_t usb_v_hys_m         : 2; /* [ 1: 0],        r/w,        0x1 */
+            uint32_t usb_v_hys_p         : 2; /* [ 3: 2],        r/w,        0x1 */
+            uint32_t usb_bd_vth          : 3; /* [ 6: 4],        r/w,        0x1 */
+            uint32_t reg_usb_use_xcvr    : 1; /* [    7],        r/w,        0x1 */
+            uint32_t usb_str_drv         : 3; /* [10: 8],        r/w,        0x0 */
+            uint32_t reg_usb_use_ctrl    : 1; /* [   11],        r/w,        0x1 */
+            uint32_t usb_res_pullup_tune : 3; /* [14:12],        r/w,        0x2 */
+            uint32_t reserved_15         : 1; /* [   15],       rsvd,        0x0 */
+            uint32_t usb_slewrate_m_fall : 3; /* [18:16],        r/w,        0x3 */
+            uint32_t reserved_19         : 1; /* [   19],       rsvd,        0x0 */
+            uint32_t usb_slewrate_m_rise : 3; /* [22:20],        r/w,        0x4 */
+            uint32_t reserved_23         : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t usb_slewrate_p_fall : 3; /* [26:24],        r/w,        0x3 */
+            uint32_t reserved_27         : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t usb_slewrate_p_rise : 3; /* [30:28],        r/w,        0x4 */
+            uint32_t reserved_31         : 1; /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } usb_xcvr_config;
+
+    /* 0x230  reserved */
+    uint8_t RESERVED0x230[216];
+
+    /* 0x308 : gpdac_ctrl */
+    union {
+        struct
+        {
+            uint32_t gpdaca_rstn_ana : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t gpdacb_rstn_ana : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reserved_2_6    : 5;  /* [ 6: 2],       rsvd,        0x0 */
+            uint32_t gpdac_test_en   : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t gpdac_ref_sel   : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t gpdac_test_sel  : 3;  /* [11: 9],        r/w,        0x0 */
+            uint32_t reserved_12_23  : 12; /* [23:12],       rsvd,        0x0 */
+            uint32_t gpdac_reserved  : 8;  /* [31:24],        r/w,        0xf */
+        } BF;
+        uint32_t WORD;
+    } gpdac_ctrl;
+
+    /* 0x30C : gpdac_actrl */
+    union {
+        struct
+        {
+            uint32_t gpdac_a_en     : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t gpdac_ioa_en   : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_17  : 16; /* [17: 2],       rsvd,        0x0 */
+            uint32_t gpdac_a_rng    : 2;  /* [19:18],        r/w,        0x3 */
+            uint32_t gpdac_a_outmux : 3;  /* [22:20],        r/w,        0x0 */
+            uint32_t reserved_23_31 : 9;  /* [31:23],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpdac_actrl;
+
+    /* 0x310 : gpdac_bctrl */
+    union {
+        struct
+        {
+            uint32_t gpdac_b_en     : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t gpdac_iob_en   : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_17  : 16; /* [17: 2],       rsvd,        0x0 */
+            uint32_t gpdac_b_rng    : 2;  /* [19:18],        r/w,        0x3 */
+            uint32_t gpdac_b_outmux : 3;  /* [22:20],        r/w,        0x0 */
+            uint32_t reserved_23_31 : 9;  /* [31:23],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpdac_bctrl;
+
+    /* 0x314 : gpdac_data */
+    union {
+        struct
+        {
+            uint32_t gpdac_b_data   : 10; /* [ 9: 0],        r/w,        0x0 */
+            uint32_t reserved_10_15 : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t gpdac_a_data   : 10; /* [25:16],        r/w,        0x0 */
+            uint32_t reserved_26_31 : 6;  /* [31:26],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpdac_data;
+
+    /* 0x318  reserved */
+    uint8_t RESERVED0x318[2792];
+
+    /* 0xE00 : chip_revision */
+    union {
+        struct
+        {
+            uint32_t chip_rev      : 4;  /* [ 3: 0],          r,        0x0 */
+            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } chip_revision;
+
+    /* 0xe04  reserved */
+    uint8_t RESERVED0xe04[252];
+
+    /* 0xF00 : tzc_glb_ctrl_0 */
+    union {
+        struct
+        {
+            uint32_t tzc_glb_swrst_s00_lock       : 1; /* [    0],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s01_lock       : 1; /* [    1],          r,        0x0 */
+            uint32_t reserved_2_7                 : 6; /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t tzc_glb_swrst_s30_lock       : 1; /* [    8],          r,        0x0 */
+            uint32_t reserved_9_11                : 3; /* [11: 9],       rsvd,        0x0 */
+            uint32_t tzc_glb_ctrl_pwron_rst_lock  : 1; /* [   12],          r,        0x0 */
+            uint32_t tzc_glb_ctrl_cpu_reset_lock  : 1; /* [   13],          r,        0x0 */
+            uint32_t tzc_glb_ctrl_sys_reset_lock  : 1; /* [   14],          r,        0x0 */
+            uint32_t tzc_glb_ctrl_ungated_ap_lock : 1; /* [   15],          r,        0x0 */
+            uint32_t reserved_16_24               : 9; /* [24:16],       rsvd,        0x0 */
+            uint32_t tzc_glb_misc_lock            : 1; /* [   25],          r,        0x0 */
+            uint32_t tzc_glb_sram_lock            : 1; /* [   26],          r,        0x0 */
+            uint32_t tzc_glb_l2c_lock             : 1; /* [   27],          r,        0x0 */
+            uint32_t tzc_glb_bmx_lock             : 1; /* [   28],          r,        0x0 */
+            uint32_t tzc_glb_dbg_lock             : 1; /* [   29],          r,        0x0 */
+            uint32_t tzc_glb_mbist_lock           : 1; /* [   30],          r,        0x0 */
+            uint32_t tzc_glb_clk_lock             : 1; /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_glb_ctrl_0;
+
+    /* 0xF04 : tzc_glb_ctrl_1 */
+    union {
+        struct
+        {
+            uint32_t tzc_glb_swrst_s20_lock : 1; /* [    0],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s21_lock : 1; /* [    1],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s22_lock : 1; /* [    2],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s23_lock : 1; /* [    3],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s24_lock : 1; /* [    4],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s25_lock : 1; /* [    5],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s26_lock : 1; /* [    6],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s27_lock : 1; /* [    7],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s28_lock : 1; /* [    8],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s29_lock : 1; /* [    9],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s2a_lock : 1; /* [   10],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s2b_lock : 1; /* [   11],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s2c_lock : 1; /* [   12],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s2d_lock : 1; /* [   13],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s2e_lock : 1; /* [   14],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s2f_lock : 1; /* [   15],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s10_lock : 1; /* [   16],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s11_lock : 1; /* [   17],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s12_lock : 1; /* [   18],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s13_lock : 1; /* [   19],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s14_lock : 1; /* [   20],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s15_lock : 1; /* [   21],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s16_lock : 1; /* [   22],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s17_lock : 1; /* [   23],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s18_lock : 1; /* [   24],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s19_lock : 1; /* [   25],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s1a_lock : 1; /* [   26],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s1b_lock : 1; /* [   27],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s1c_lock : 1; /* [   28],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s1d_lock : 1; /* [   29],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s1e_lock : 1; /* [   30],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s1f_lock : 1; /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_glb_ctrl_1;
+
+    /* 0xF08 : tzc_glb_ctrl_2 */
+    union {
+        struct
+        {
+            uint32_t tzc_glb_gpio_0_lock  : 1; /* [    0],          r,        0x0 */
+            uint32_t tzc_glb_gpio_1_lock  : 1; /* [    1],          r,        0x0 */
+            uint32_t tzc_glb_gpio_2_lock  : 1; /* [    2],          r,        0x0 */
+            uint32_t tzc_glb_gpio_3_lock  : 1; /* [    3],          r,        0x0 */
+            uint32_t tzc_glb_gpio_4_lock  : 1; /* [    4],          r,        0x0 */
+            uint32_t tzc_glb_gpio_5_lock  : 1; /* [    5],          r,        0x0 */
+            uint32_t tzc_glb_gpio_6_lock  : 1; /* [    6],          r,        0x0 */
+            uint32_t tzc_glb_gpio_7_lock  : 1; /* [    7],          r,        0x0 */
+            uint32_t tzc_glb_gpio_8_lock  : 1; /* [    8],          r,        0x0 */
+            uint32_t tzc_glb_gpio_9_lock  : 1; /* [    9],          r,        0x0 */
+            uint32_t tzc_glb_gpio_10_lock : 1; /* [   10],          r,        0x0 */
+            uint32_t tzc_glb_gpio_11_lock : 1; /* [   11],          r,        0x0 */
+            uint32_t tzc_glb_gpio_12_lock : 1; /* [   12],          r,        0x0 */
+            uint32_t tzc_glb_gpio_13_lock : 1; /* [   13],          r,        0x0 */
+            uint32_t tzc_glb_gpio_14_lock : 1; /* [   14],          r,        0x0 */
+            uint32_t tzc_glb_gpio_15_lock : 1; /* [   15],          r,        0x0 */
+            uint32_t tzc_glb_gpio_16_lock : 1; /* [   16],          r,        0x0 */
+            uint32_t tzc_glb_gpio_17_lock : 1; /* [   17],          r,        0x0 */
+            uint32_t tzc_glb_gpio_18_lock : 1; /* [   18],          r,        0x0 */
+            uint32_t tzc_glb_gpio_19_lock : 1; /* [   19],          r,        0x0 */
+            uint32_t tzc_glb_gpio_20_lock : 1; /* [   20],          r,        0x0 */
+            uint32_t tzc_glb_gpio_21_lock : 1; /* [   21],          r,        0x0 */
+            uint32_t tzc_glb_gpio_22_lock : 1; /* [   22],          r,        0x0 */
+            uint32_t tzc_glb_gpio_23_lock : 1; /* [   23],          r,        0x0 */
+            uint32_t tzc_glb_gpio_24_lock : 1; /* [   24],          r,        0x0 */
+            uint32_t tzc_glb_gpio_25_lock : 1; /* [   25],          r,        0x0 */
+            uint32_t tzc_glb_gpio_26_lock : 1; /* [   26],          r,        0x0 */
+            uint32_t tzc_glb_gpio_27_lock : 1; /* [   27],          r,        0x0 */
+            uint32_t tzc_glb_gpio_28_lock : 1; /* [   28],          r,        0x0 */
+            uint32_t tzc_glb_gpio_29_lock : 1; /* [   29],          r,        0x0 */
+            uint32_t tzc_glb_gpio_30_lock : 1; /* [   30],          r,        0x0 */
+            uint32_t tzc_glb_gpio_31_lock : 1; /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_glb_ctrl_2;
+
+    /* 0xF0C : tzc_glb_ctrl_3 */
+    union {
+        struct
+        {
+            uint32_t tzc_glb_gpio_32_lock : 1;  /* [    0],          r,        0x0 */
+            uint32_t tzc_glb_gpio_33_lock : 1;  /* [    1],          r,        0x0 */
+            uint32_t tzc_glb_gpio_34_lock : 1;  /* [    2],          r,        0x0 */
+            uint32_t tzc_glb_gpio_35_lock : 1;  /* [    3],          r,        0x0 */
+            uint32_t tzc_glb_gpio_36_lock : 1;  /* [    4],          r,        0x0 */
+            uint32_t tzc_glb_gpio_37_lock : 1;  /* [    5],          r,        0x0 */
+            uint32_t reserved_6_31        : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_glb_ctrl_3;
+};
+
+typedef volatile struct glb_reg glb_reg_t;
+
+/*Following is reg patch*/
+
+/* 0x0 : GPIO_CFGCTL */
+#define GLB_GPIO_CFGCTL_OFFSET       (0x0)
+#define GLB_REG_GPIO_0_IE            GLB_REG_GPIO_0_IE
+#define GLB_REG_GPIO_0_IE_POS        (0U)
+#define GLB_REG_GPIO_0_IE_LEN        (1U)
+#define GLB_REG_GPIO_0_IE_MSK        (((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)
+#define GLB_REG_GPIO_0_IE_UMSK       (~(((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS))
+#define GLB_REG_GPIO_0_SMT           GLB_REG_GPIO_0_SMT
+#define GLB_REG_GPIO_0_SMT_POS       (1U)
+#define GLB_REG_GPIO_0_SMT_LEN       (1U)
+#define GLB_REG_GPIO_0_SMT_MSK       (((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)
+#define GLB_REG_GPIO_0_SMT_UMSK      (~(((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS))
+#define GLB_REG_GPIO_0_DRV           GLB_REG_GPIO_0_DRV
+#define GLB_REG_GPIO_0_DRV_POS       (2U)
+#define GLB_REG_GPIO_0_DRV_LEN       (2U)
+#define GLB_REG_GPIO_0_DRV_MSK       (((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)
+#define GLB_REG_GPIO_0_DRV_UMSK      (~(((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS))
+#define GLB_REG_GPIO_0_PU            GLB_REG_GPIO_0_PU
+#define GLB_REG_GPIO_0_PU_POS        (4U)
+#define GLB_REG_GPIO_0_PU_LEN        (1U)
+#define GLB_REG_GPIO_0_PU_MSK        (((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)
+#define GLB_REG_GPIO_0_PU_UMSK       (~(((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS))
+#define GLB_REG_GPIO_0_PD            GLB_REG_GPIO_0_PD
+#define GLB_REG_GPIO_0_PD_POS        (5U)
+#define GLB_REG_GPIO_0_PD_LEN        (1U)
+#define GLB_REG_GPIO_0_PD_MSK        (((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)
+#define GLB_REG_GPIO_0_PD_UMSK       (~(((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS))
+#define GLB_REG_GPIO_0_FUNC_SEL      GLB_REG_GPIO_0_FUNC_SEL
+#define GLB_REG_GPIO_0_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_0_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_0_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)
+#define GLB_REG_GPIO_0_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS))
+#define GLB_REG_GPIO_1_IE            GLB_REG_GPIO_1_IE
+#define GLB_REG_GPIO_1_IE_POS        (16U)
+#define GLB_REG_GPIO_1_IE_LEN        (1U)
+#define GLB_REG_GPIO_1_IE_MSK        (((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)
+#define GLB_REG_GPIO_1_IE_UMSK       (~(((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS))
+#define GLB_REG_GPIO_1_SMT           GLB_REG_GPIO_1_SMT
+#define GLB_REG_GPIO_1_SMT_POS       (17U)
+#define GLB_REG_GPIO_1_SMT_LEN       (1U)
+#define GLB_REG_GPIO_1_SMT_MSK       (((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)
+#define GLB_REG_GPIO_1_SMT_UMSK      (~(((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS))
+#define GLB_REG_GPIO_1_DRV           GLB_REG_GPIO_1_DRV
+#define GLB_REG_GPIO_1_DRV_POS       (18U)
+#define GLB_REG_GPIO_1_DRV_LEN       (2U)
+#define GLB_REG_GPIO_1_DRV_MSK       (((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)
+#define GLB_REG_GPIO_1_DRV_UMSK      (~(((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS))
+#define GLB_REG_GPIO_1_PU            GLB_REG_GPIO_1_PU
+#define GLB_REG_GPIO_1_PU_POS        (20U)
+#define GLB_REG_GPIO_1_PU_LEN        (1U)
+#define GLB_REG_GPIO_1_PU_MSK        (((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)
+#define GLB_REG_GPIO_1_PU_UMSK       (~(((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS))
+#define GLB_REG_GPIO_1_PD            GLB_REG_GPIO_1_PD
+#define GLB_REG_GPIO_1_PD_POS        (21U)
+#define GLB_REG_GPIO_1_PD_LEN        (1U)
+#define GLB_REG_GPIO_1_PD_MSK        (((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)
+#define GLB_REG_GPIO_1_PD_UMSK       (~(((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS))
+#define GLB_REG_GPIO_1_FUNC_SEL      GLB_REG_GPIO_1_FUNC_SEL
+#define GLB_REG_GPIO_1_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_1_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_1_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)
+#define GLB_REG_GPIO_1_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS))
+
+struct glb_gpio_reg {
+    /* 0x0 : GPIO_CFGCTL */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_0_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_0_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_0_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_0_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_0_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7        : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_0_func_sel : 5; /* [12: 8],        r/w,        0xe */
+            uint32_t reserved_13_15      : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_1_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_1_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_1_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_1_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_1_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23      : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_1_func_sel : 5; /* [28:24],        r/w,        0xe */
+            uint32_t reserved_29_31      : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL;
+};
+
+typedef volatile struct glb_gpio_reg glb_gpio_reg_t;
+
+#define GLB_GPIO_OFFSET           0x100
+#define GLB_GPIO_INPUT_OFFSET     0x180
+#define GLB_GPIO_OUTPUT_OFFSET    0x188
+#define GLB_GPIO_OUTPUT_EN_OFFSET 0x190
+
+#endif /* __GLB_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/gpip_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/gpip_reg.h
new file mode 100644
index 00000000..13a5e892
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/gpip_reg.h
@@ -0,0 +1,317 @@
+/**
+  ******************************************************************************
+  * @file    gpip_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __GPIP_REG_H__
+#define __GPIP_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : gpadc_config */
+#define GPIP_GPADC_CONFIG_OFFSET           (0x0)
+#define GPIP_GPADC_DMA_EN                  GPIP_GPADC_DMA_EN
+#define GPIP_GPADC_DMA_EN_POS              (0U)
+#define GPIP_GPADC_DMA_EN_LEN              (1U)
+#define GPIP_GPADC_DMA_EN_MSK              (((1U << GPIP_GPADC_DMA_EN_LEN) - 1) << GPIP_GPADC_DMA_EN_POS)
+#define GPIP_GPADC_DMA_EN_UMSK             (~(((1U << GPIP_GPADC_DMA_EN_LEN) - 1) << GPIP_GPADC_DMA_EN_POS))
+#define GPIP_GPADC_FIFO_CLR                GPIP_GPADC_FIFO_CLR
+#define GPIP_GPADC_FIFO_CLR_POS            (1U)
+#define GPIP_GPADC_FIFO_CLR_LEN            (1U)
+#define GPIP_GPADC_FIFO_CLR_MSK            (((1U << GPIP_GPADC_FIFO_CLR_LEN) - 1) << GPIP_GPADC_FIFO_CLR_POS)
+#define GPIP_GPADC_FIFO_CLR_UMSK           (~(((1U << GPIP_GPADC_FIFO_CLR_LEN) - 1) << GPIP_GPADC_FIFO_CLR_POS))
+#define GPIP_GPADC_FIFO_NE                 GPIP_GPADC_FIFO_NE
+#define GPIP_GPADC_FIFO_NE_POS             (2U)
+#define GPIP_GPADC_FIFO_NE_LEN             (1U)
+#define GPIP_GPADC_FIFO_NE_MSK             (((1U << GPIP_GPADC_FIFO_NE_LEN) - 1) << GPIP_GPADC_FIFO_NE_POS)
+#define GPIP_GPADC_FIFO_NE_UMSK            (~(((1U << GPIP_GPADC_FIFO_NE_LEN) - 1) << GPIP_GPADC_FIFO_NE_POS))
+#define GPIP_GPADC_FIFO_FULL               GPIP_GPADC_FIFO_FULL
+#define GPIP_GPADC_FIFO_FULL_POS           (3U)
+#define GPIP_GPADC_FIFO_FULL_LEN           (1U)
+#define GPIP_GPADC_FIFO_FULL_MSK           (((1U << GPIP_GPADC_FIFO_FULL_LEN) - 1) << GPIP_GPADC_FIFO_FULL_POS)
+#define GPIP_GPADC_FIFO_FULL_UMSK          (~(((1U << GPIP_GPADC_FIFO_FULL_LEN) - 1) << GPIP_GPADC_FIFO_FULL_POS))
+#define GPIP_GPADC_RDY                     GPIP_GPADC_RDY
+#define GPIP_GPADC_RDY_POS                 (4U)
+#define GPIP_GPADC_RDY_LEN                 (1U)
+#define GPIP_GPADC_RDY_MSK                 (((1U << GPIP_GPADC_RDY_LEN) - 1) << GPIP_GPADC_RDY_POS)
+#define GPIP_GPADC_RDY_UMSK                (~(((1U << GPIP_GPADC_RDY_LEN) - 1) << GPIP_GPADC_RDY_POS))
+#define GPIP_GPADC_FIFO_OVERRUN            GPIP_GPADC_FIFO_OVERRUN
+#define GPIP_GPADC_FIFO_OVERRUN_POS        (5U)
+#define GPIP_GPADC_FIFO_OVERRUN_LEN        (1U)
+#define GPIP_GPADC_FIFO_OVERRUN_MSK        (((1U << GPIP_GPADC_FIFO_OVERRUN_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_POS)
+#define GPIP_GPADC_FIFO_OVERRUN_UMSK       (~(((1U << GPIP_GPADC_FIFO_OVERRUN_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_POS))
+#define GPIP_GPADC_FIFO_UNDERRUN           GPIP_GPADC_FIFO_UNDERRUN
+#define GPIP_GPADC_FIFO_UNDERRUN_POS       (6U)
+#define GPIP_GPADC_FIFO_UNDERRUN_LEN       (1U)
+#define GPIP_GPADC_FIFO_UNDERRUN_MSK       (((1U << GPIP_GPADC_FIFO_UNDERRUN_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_POS)
+#define GPIP_GPADC_FIFO_UNDERRUN_UMSK      (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_POS))
+#define GPIP_GPADC_FIFO_RDY                GPIP_GPADC_FIFO_RDY
+#define GPIP_GPADC_FIFO_RDY_POS            (7U)
+#define GPIP_GPADC_FIFO_RDY_LEN            (1U)
+#define GPIP_GPADC_FIFO_RDY_MSK            (((1U << GPIP_GPADC_FIFO_RDY_LEN) - 1) << GPIP_GPADC_FIFO_RDY_POS)
+#define GPIP_GPADC_FIFO_RDY_UMSK           (~(((1U << GPIP_GPADC_FIFO_RDY_LEN) - 1) << GPIP_GPADC_FIFO_RDY_POS))
+#define GPIP_GPADC_RDY_CLR                 GPIP_GPADC_RDY_CLR
+#define GPIP_GPADC_RDY_CLR_POS             (8U)
+#define GPIP_GPADC_RDY_CLR_LEN             (1U)
+#define GPIP_GPADC_RDY_CLR_MSK             (((1U << GPIP_GPADC_RDY_CLR_LEN) - 1) << GPIP_GPADC_RDY_CLR_POS)
+#define GPIP_GPADC_RDY_CLR_UMSK            (~(((1U << GPIP_GPADC_RDY_CLR_LEN) - 1) << GPIP_GPADC_RDY_CLR_POS))
+#define GPIP_GPADC_FIFO_OVERRUN_CLR        GPIP_GPADC_FIFO_OVERRUN_CLR
+#define GPIP_GPADC_FIFO_OVERRUN_CLR_POS    (9U)
+#define GPIP_GPADC_FIFO_OVERRUN_CLR_LEN    (1U)
+#define GPIP_GPADC_FIFO_OVERRUN_CLR_MSK    (((1U << GPIP_GPADC_FIFO_OVERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_CLR_POS)
+#define GPIP_GPADC_FIFO_OVERRUN_CLR_UMSK   (~(((1U << GPIP_GPADC_FIFO_OVERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_CLR_POS))
+#define GPIP_GPADC_FIFO_UNDERRUN_CLR       GPIP_GPADC_FIFO_UNDERRUN_CLR
+#define GPIP_GPADC_FIFO_UNDERRUN_CLR_POS   (10U)
+#define GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN   (1U)
+#define GPIP_GPADC_FIFO_UNDERRUN_CLR_MSK   (((1U << GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_CLR_POS)
+#define GPIP_GPADC_FIFO_UNDERRUN_CLR_UMSK  (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_CLR_POS))
+#define GPIP_GPADC_RDY_MASK                GPIP_GPADC_RDY_MASK
+#define GPIP_GPADC_RDY_MASK_POS            (12U)
+#define GPIP_GPADC_RDY_MASK_LEN            (1U)
+#define GPIP_GPADC_RDY_MASK_MSK            (((1U << GPIP_GPADC_RDY_MASK_LEN) - 1) << GPIP_GPADC_RDY_MASK_POS)
+#define GPIP_GPADC_RDY_MASK_UMSK           (~(((1U << GPIP_GPADC_RDY_MASK_LEN) - 1) << GPIP_GPADC_RDY_MASK_POS))
+#define GPIP_GPADC_FIFO_OVERRUN_MASK       GPIP_GPADC_FIFO_OVERRUN_MASK
+#define GPIP_GPADC_FIFO_OVERRUN_MASK_POS   (13U)
+#define GPIP_GPADC_FIFO_OVERRUN_MASK_LEN   (1U)
+#define GPIP_GPADC_FIFO_OVERRUN_MASK_MSK   (((1U << GPIP_GPADC_FIFO_OVERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_MASK_POS)
+#define GPIP_GPADC_FIFO_OVERRUN_MASK_UMSK  (~(((1U << GPIP_GPADC_FIFO_OVERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_MASK_POS))
+#define GPIP_GPADC_FIFO_UNDERRUN_MASK      GPIP_GPADC_FIFO_UNDERRUN_MASK
+#define GPIP_GPADC_FIFO_UNDERRUN_MASK_POS  (14U)
+#define GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN  (1U)
+#define GPIP_GPADC_FIFO_UNDERRUN_MASK_MSK  (((1U << GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_MASK_POS)
+#define GPIP_GPADC_FIFO_UNDERRUN_MASK_UMSK (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_MASK_POS))
+#define GPIP_GPADC_FIFO_RDY_MASK           GPIP_GPADC_FIFO_RDY_MASK
+#define GPIP_GPADC_FIFO_RDY_MASK_POS       (15U)
+#define GPIP_GPADC_FIFO_RDY_MASK_LEN       (1U)
+#define GPIP_GPADC_FIFO_RDY_MASK_MSK       (((1U << GPIP_GPADC_FIFO_RDY_MASK_LEN) - 1) << GPIP_GPADC_FIFO_RDY_MASK_POS)
+#define GPIP_GPADC_FIFO_RDY_MASK_UMSK      (~(((1U << GPIP_GPADC_FIFO_RDY_MASK_LEN) - 1) << GPIP_GPADC_FIFO_RDY_MASK_POS))
+#define GPIP_GPADC_FIFO_DATA_COUNT         GPIP_GPADC_FIFO_DATA_COUNT
+#define GPIP_GPADC_FIFO_DATA_COUNT_POS     (16U)
+#define GPIP_GPADC_FIFO_DATA_COUNT_LEN     (6U)
+#define GPIP_GPADC_FIFO_DATA_COUNT_MSK     (((1U << GPIP_GPADC_FIFO_DATA_COUNT_LEN) - 1) << GPIP_GPADC_FIFO_DATA_COUNT_POS)
+#define GPIP_GPADC_FIFO_DATA_COUNT_UMSK    (~(((1U << GPIP_GPADC_FIFO_DATA_COUNT_LEN) - 1) << GPIP_GPADC_FIFO_DATA_COUNT_POS))
+#define GPIP_GPADC_FIFO_THL                GPIP_GPADC_FIFO_THL
+#define GPIP_GPADC_FIFO_THL_POS            (22U)
+#define GPIP_GPADC_FIFO_THL_LEN            (2U)
+#define GPIP_GPADC_FIFO_THL_MSK            (((1U << GPIP_GPADC_FIFO_THL_LEN) - 1) << GPIP_GPADC_FIFO_THL_POS)
+#define GPIP_GPADC_FIFO_THL_UMSK           (~(((1U << GPIP_GPADC_FIFO_THL_LEN) - 1) << GPIP_GPADC_FIFO_THL_POS))
+
+/* 0x4 : gpadc_dma_rdata */
+#define GPIP_GPADC_DMA_RDATA_OFFSET (0x4)
+#define GPIP_GPADC_DMA_RDATA        GPIP_GPADC_DMA_RDATA
+#define GPIP_GPADC_DMA_RDATA_POS    (0U)
+#define GPIP_GPADC_DMA_RDATA_LEN    (26U)
+#define GPIP_GPADC_DMA_RDATA_MSK    (((1U << GPIP_GPADC_DMA_RDATA_LEN) - 1) << GPIP_GPADC_DMA_RDATA_POS)
+#define GPIP_GPADC_DMA_RDATA_UMSK   (~(((1U << GPIP_GPADC_DMA_RDATA_LEN) - 1) << GPIP_GPADC_DMA_RDATA_POS))
+
+/* 0x40 : gpdac_config */
+#define GPIP_GPDAC_CONFIG_OFFSET (0x40)
+#define GPIP_GPDAC_EN            GPIP_GPDAC_EN
+#define GPIP_GPDAC_EN_POS        (0U)
+#define GPIP_GPDAC_EN_LEN        (1U)
+#define GPIP_GPDAC_EN_MSK        (((1U << GPIP_GPDAC_EN_LEN) - 1) << GPIP_GPDAC_EN_POS)
+#define GPIP_GPDAC_EN_UMSK       (~(((1U << GPIP_GPDAC_EN_LEN) - 1) << GPIP_GPDAC_EN_POS))
+#define GPIP_GPDAC_EN2           GPIP_GPDAC_EN2
+#define GPIP_GPDAC_EN2_POS       (1U)
+#define GPIP_GPDAC_EN2_LEN       (1U)
+#define GPIP_GPDAC_EN2_MSK       (((1U << GPIP_GPDAC_EN2_LEN) - 1) << GPIP_GPDAC_EN2_POS)
+#define GPIP_GPDAC_EN2_UMSK      (~(((1U << GPIP_GPDAC_EN2_LEN) - 1) << GPIP_GPDAC_EN2_POS))
+#define GPIP_DSM_MODE            GPIP_DSM_MODE
+#define GPIP_DSM_MODE_POS        (4U)
+#define GPIP_DSM_MODE_LEN        (2U)
+#define GPIP_DSM_MODE_MSK        (((1U << GPIP_DSM_MODE_LEN) - 1) << GPIP_DSM_MODE_POS)
+#define GPIP_DSM_MODE_UMSK       (~(((1U << GPIP_DSM_MODE_LEN) - 1) << GPIP_DSM_MODE_POS))
+#define GPIP_GPDAC_MODE          GPIP_GPDAC_MODE
+#define GPIP_GPDAC_MODE_POS      (8U)
+#define GPIP_GPDAC_MODE_LEN      (3U)
+#define GPIP_GPDAC_MODE_MSK      (((1U << GPIP_GPDAC_MODE_LEN) - 1) << GPIP_GPDAC_MODE_POS)
+#define GPIP_GPDAC_MODE_UMSK     (~(((1U << GPIP_GPDAC_MODE_LEN) - 1) << GPIP_GPDAC_MODE_POS))
+#define GPIP_GPDAC_CH_A_SEL      GPIP_GPDAC_CH_A_SEL
+#define GPIP_GPDAC_CH_A_SEL_POS  (16U)
+#define GPIP_GPDAC_CH_A_SEL_LEN  (4U)
+#define GPIP_GPDAC_CH_A_SEL_MSK  (((1U << GPIP_GPDAC_CH_A_SEL_LEN) - 1) << GPIP_GPDAC_CH_A_SEL_POS)
+#define GPIP_GPDAC_CH_A_SEL_UMSK (~(((1U << GPIP_GPDAC_CH_A_SEL_LEN) - 1) << GPIP_GPDAC_CH_A_SEL_POS))
+#define GPIP_GPDAC_CH_B_SEL      GPIP_GPDAC_CH_B_SEL
+#define GPIP_GPDAC_CH_B_SEL_POS  (20U)
+#define GPIP_GPDAC_CH_B_SEL_LEN  (4U)
+#define GPIP_GPDAC_CH_B_SEL_MSK  (((1U << GPIP_GPDAC_CH_B_SEL_LEN) - 1) << GPIP_GPDAC_CH_B_SEL_POS)
+#define GPIP_GPDAC_CH_B_SEL_UMSK (~(((1U << GPIP_GPDAC_CH_B_SEL_LEN) - 1) << GPIP_GPDAC_CH_B_SEL_POS))
+
+/* 0x44 : gpdac_dma_config */
+#define GPIP_GPDAC_DMA_CONFIG_OFFSET (0x44)
+#define GPIP_GPDAC_DMA_TX_EN         GPIP_GPDAC_DMA_TX_EN
+#define GPIP_GPDAC_DMA_TX_EN_POS     (0U)
+#define GPIP_GPDAC_DMA_TX_EN_LEN     (1U)
+#define GPIP_GPDAC_DMA_TX_EN_MSK     (((1U << GPIP_GPDAC_DMA_TX_EN_LEN) - 1) << GPIP_GPDAC_DMA_TX_EN_POS)
+#define GPIP_GPDAC_DMA_TX_EN_UMSK    (~(((1U << GPIP_GPDAC_DMA_TX_EN_LEN) - 1) << GPIP_GPDAC_DMA_TX_EN_POS))
+#define GPIP_GPDAC_DMA_FORMAT        GPIP_GPDAC_DMA_FORMAT
+#define GPIP_GPDAC_DMA_FORMAT_POS    (4U)
+#define GPIP_GPDAC_DMA_FORMAT_LEN    (2U)
+#define GPIP_GPDAC_DMA_FORMAT_MSK    (((1U << GPIP_GPDAC_DMA_FORMAT_LEN) - 1) << GPIP_GPDAC_DMA_FORMAT_POS)
+#define GPIP_GPDAC_DMA_FORMAT_UMSK   (~(((1U << GPIP_GPDAC_DMA_FORMAT_LEN) - 1) << GPIP_GPDAC_DMA_FORMAT_POS))
+
+/* 0x48 : gpdac_dma_wdata */
+#define GPIP_GPDAC_DMA_WDATA_OFFSET (0x48)
+#define GPIP_GPDAC_DMA_WDATA        GPIP_GPDAC_DMA_WDATA
+#define GPIP_GPDAC_DMA_WDATA_POS    (0U)
+#define GPIP_GPDAC_DMA_WDATA_LEN    (32U)
+#define GPIP_GPDAC_DMA_WDATA_MSK    (((1U << GPIP_GPDAC_DMA_WDATA_LEN) - 1) << GPIP_GPDAC_DMA_WDATA_POS)
+#define GPIP_GPDAC_DMA_WDATA_UMSK   (~(((1U << GPIP_GPDAC_DMA_WDATA_LEN) - 1) << GPIP_GPDAC_DMA_WDATA_POS))
+
+/* 0x4C : gpdac_tx_fifo_status */
+#define GPIP_GPDAC_TX_FIFO_STATUS_OFFSET (0x4C)
+#define GPIP_TX_FIFO_EMPTY               GPIP_TX_FIFO_EMPTY
+#define GPIP_TX_FIFO_EMPTY_POS           (0U)
+#define GPIP_TX_FIFO_EMPTY_LEN           (1U)
+#define GPIP_TX_FIFO_EMPTY_MSK           (((1U << GPIP_TX_FIFO_EMPTY_LEN) - 1) << GPIP_TX_FIFO_EMPTY_POS)
+#define GPIP_TX_FIFO_EMPTY_UMSK          (~(((1U << GPIP_TX_FIFO_EMPTY_LEN) - 1) << GPIP_TX_FIFO_EMPTY_POS))
+#define GPIP_TX_FIFO_FULL                GPIP_TX_FIFO_FULL
+#define GPIP_TX_FIFO_FULL_POS            (1U)
+#define GPIP_TX_FIFO_FULL_LEN            (1U)
+#define GPIP_TX_FIFO_FULL_MSK            (((1U << GPIP_TX_FIFO_FULL_LEN) - 1) << GPIP_TX_FIFO_FULL_POS)
+#define GPIP_TX_FIFO_FULL_UMSK           (~(((1U << GPIP_TX_FIFO_FULL_LEN) - 1) << GPIP_TX_FIFO_FULL_POS))
+#define GPIP_TX_CS                       GPIP_TX_CS
+#define GPIP_TX_CS_POS                   (2U)
+#define GPIP_TX_CS_LEN                   (2U)
+#define GPIP_TX_CS_MSK                   (((1U << GPIP_TX_CS_LEN) - 1) << GPIP_TX_CS_POS)
+#define GPIP_TX_CS_UMSK                  (~(((1U << GPIP_TX_CS_LEN) - 1) << GPIP_TX_CS_POS))
+#define GPIP_TXFIFORDPTR                 GPIP_TXFIFORDPTR
+#define GPIP_TXFIFORDPTR_POS             (4U)
+#define GPIP_TXFIFORDPTR_LEN             (3U)
+#define GPIP_TXFIFORDPTR_MSK             (((1U << GPIP_TXFIFORDPTR_LEN) - 1) << GPIP_TXFIFORDPTR_POS)
+#define GPIP_TXFIFORDPTR_UMSK            (~(((1U << GPIP_TXFIFORDPTR_LEN) - 1) << GPIP_TXFIFORDPTR_POS))
+#define GPIP_TXFIFOWRPTR                 GPIP_TXFIFOWRPTR
+#define GPIP_TXFIFOWRPTR_POS             (8U)
+#define GPIP_TXFIFOWRPTR_LEN             (2U)
+#define GPIP_TXFIFOWRPTR_MSK             (((1U << GPIP_TXFIFOWRPTR_LEN) - 1) << GPIP_TXFIFOWRPTR_POS)
+#define GPIP_TXFIFOWRPTR_UMSK            (~(((1U << GPIP_TXFIFOWRPTR_LEN) - 1) << GPIP_TXFIFOWRPTR_POS))
+
+struct gpip_reg {
+    /* 0x0 : gpadc_config */
+    union {
+        struct
+        {
+            uint32_t gpadc_dma_en             : 1; /* [    0],        r/w,        0x0 */
+            uint32_t gpadc_fifo_clr           : 1; /* [    1],        w1c,        0x0 */
+            uint32_t gpadc_fifo_ne            : 1; /* [    2],          r,        0x0 */
+            uint32_t gpadc_fifo_full          : 1; /* [    3],          r,        0x0 */
+            uint32_t gpadc_rdy                : 1; /* [    4],          r,        0x0 */
+            uint32_t gpadc_fifo_overrun       : 1; /* [    5],          r,        0x0 */
+            uint32_t gpadc_fifo_underrun      : 1; /* [    6],          r,        0x0 */
+            uint32_t gpadc_fifo_rdy           : 1; /* [    7],          r,        0x0 */
+            uint32_t gpadc_rdy_clr            : 1; /* [    8],        w1c,        0x0 */
+            uint32_t gpadc_fifo_overrun_clr   : 1; /* [    9],        w1c,        0x0 */
+            uint32_t gpadc_fifo_underrun_clr  : 1; /* [   10],        w1c,        0x0 */
+            uint32_t reserved_11              : 1; /* [   11],       rsvd,        0x0 */
+            uint32_t gpadc_rdy_mask           : 1; /* [   12],        r/w,        0x0 */
+            uint32_t gpadc_fifo_overrun_mask  : 1; /* [   13],        r/w,        0x0 */
+            uint32_t gpadc_fifo_underrun_mask : 1; /* [   14],        r/w,        0x0 */
+            uint32_t gpadc_fifo_rdy_mask      : 1; /* [   15],        r/w,        0x1 */
+            uint32_t gpadc_fifo_data_count    : 6; /* [21:16],          r,        0x0 */
+            uint32_t gpadc_fifo_thl           : 2; /* [23:22],        r/w,        0x0 */
+            uint32_t rsvd_31_24               : 8; /* [31:24],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_config;
+
+    /* 0x4 : gpadc_dma_rdata */
+    union {
+        struct
+        {
+            uint32_t gpadc_dma_rdata : 26; /* [25: 0],          r,        0x0 */
+            uint32_t rsvd_31_26      : 6;  /* [31:26],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_dma_rdata;
+
+    /* 0x8  reserved */
+    uint8_t RESERVED0x8[56];
+
+    /* 0x40 : gpdac_config */
+    union {
+        struct
+        {
+            uint32_t gpdac_en       : 1; /* [    0],        r/w,        0x0 */
+            uint32_t gpdac_en2      : 1; /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_3   : 2; /* [ 3: 2],       rsvd,        0x0 */
+            uint32_t dsm_mode       : 2; /* [ 5: 4],        r/w,        0x0 */
+            uint32_t reserved_6_7   : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t gpdac_mode     : 3; /* [10: 8],        r/w,        0x0 */
+            uint32_t reserved_11_15 : 5; /* [15:11],       rsvd,        0x0 */
+            uint32_t gpdac_ch_a_sel : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t gpdac_ch_b_sel : 4; /* [23:20],        r/w,        0x0 */
+            uint32_t rsvd_31_24     : 8; /* [31:24],       rsvd,        0xd */
+        } BF;
+        uint32_t WORD;
+    } gpdac_config;
+
+    /* 0x44 : gpdac_dma_config */
+    union {
+        struct
+        {
+            uint32_t gpdac_dma_tx_en  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3     : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t gpdac_dma_format : 2;  /* [ 5: 4],        r/w,        0x0 */
+            uint32_t reserved_6_31    : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpdac_dma_config;
+
+    /* 0x48 : gpdac_dma_wdata */
+    union {
+        struct
+        {
+            uint32_t gpdac_dma_wdata : 32; /* [31: 0],          w,          x */
+        } BF;
+        uint32_t WORD;
+    } gpdac_dma_wdata;
+
+    /* 0x4C : gpdac_tx_fifo_status */
+    union {
+        struct
+        {
+            uint32_t tx_fifo_empty  : 1;  /* [    0],          r,        0x0 */
+            uint32_t tx_fifo_full   : 1;  /* [    1],          r,        0x0 */
+            uint32_t tx_cs          : 2;  /* [ 3: 2],          r,        0x0 */
+            uint32_t TxFifoRdPtr    : 3;  /* [ 6: 4],          r,        0x4 */
+            uint32_t reserved_7     : 1;  /* [    7],       rsvd,        0x0 */
+            uint32_t TxFifoWrPtr    : 2;  /* [ 9: 8],          r,        0x0 */
+            uint32_t reserved_10_31 : 22; /* [31:10],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpdac_tx_fifo_status;
+};
+
+typedef volatile struct gpip_reg gpip_reg_t;
+
+#endif /* __GPIP_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/hbn_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/hbn_reg.h
new file mode 100644
index 00000000..26a2158c
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/hbn_reg.h
@@ -0,0 +1,814 @@
+/**
+  ******************************************************************************
+  * @file    hbn_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __HBN_REG_H__
+#define __HBN_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : HBN_CTL */
+#define HBN_CTL_OFFSET                (0x0)
+#define HBN_RTC_CTL                   HBN_RTC_CTL
+#define HBN_RTC_CTL_POS               (0U)
+#define HBN_RTC_CTL_LEN               (7U)
+#define HBN_RTC_CTL_MSK               (((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS)
+#define HBN_RTC_CTL_UMSK              (~(((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS))
+#define HBN_MODE                      HBN_MODE
+#define HBN_MODE_POS                  (7U)
+#define HBN_MODE_LEN                  (1U)
+#define HBN_MODE_MSK                  (((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS)
+#define HBN_MODE_UMSK                 (~(((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS))
+#define HBN_TRAP_MODE                 HBN_TRAP_MODE
+#define HBN_TRAP_MODE_POS             (8U)
+#define HBN_TRAP_MODE_LEN             (1U)
+#define HBN_TRAP_MODE_MSK             (((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS)
+#define HBN_TRAP_MODE_UMSK            (~(((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS))
+#define HBN_PWRDN_HBN_CORE            HBN_PWRDN_HBN_CORE
+#define HBN_PWRDN_HBN_CORE_POS        (9U)
+#define HBN_PWRDN_HBN_CORE_LEN        (1U)
+#define HBN_PWRDN_HBN_CORE_MSK        (((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS)
+#define HBN_PWRDN_HBN_CORE_UMSK       (~(((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS))
+#define HBN_PWRDN_HBN_RTC             HBN_PWRDN_HBN_RTC
+#define HBN_PWRDN_HBN_RTC_POS         (11U)
+#define HBN_PWRDN_HBN_RTC_LEN         (1U)
+#define HBN_PWRDN_HBN_RTC_MSK         (((1U << HBN_PWRDN_HBN_RTC_LEN) - 1) << HBN_PWRDN_HBN_RTC_POS)
+#define HBN_PWRDN_HBN_RTC_UMSK        (~(((1U << HBN_PWRDN_HBN_RTC_LEN) - 1) << HBN_PWRDN_HBN_RTC_POS))
+#define HBN_SW_RST                    HBN_SW_RST
+#define HBN_SW_RST_POS                (12U)
+#define HBN_SW_RST_LEN                (1U)
+#define HBN_SW_RST_MSK                (((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS)
+#define HBN_SW_RST_UMSK               (~(((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS))
+#define HBN_DIS_PWR_OFF_LDO11         HBN_DIS_PWR_OFF_LDO11
+#define HBN_DIS_PWR_OFF_LDO11_POS     (13U)
+#define HBN_DIS_PWR_OFF_LDO11_LEN     (1U)
+#define HBN_DIS_PWR_OFF_LDO11_MSK     (((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS)
+#define HBN_DIS_PWR_OFF_LDO11_UMSK    (~(((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS))
+#define HBN_DIS_PWR_OFF_LDO11_RT      HBN_DIS_PWR_OFF_LDO11_RT
+#define HBN_DIS_PWR_OFF_LDO11_RT_POS  (14U)
+#define HBN_DIS_PWR_OFF_LDO11_RT_LEN  (1U)
+#define HBN_DIS_PWR_OFF_LDO11_RT_MSK  (((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS)
+#define HBN_DIS_PWR_OFF_LDO11_RT_UMSK (~(((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS))
+#define HBN_LDO11_RT_VOUT_SEL         HBN_LDO11_RT_VOUT_SEL
+#define HBN_LDO11_RT_VOUT_SEL_POS     (15U)
+#define HBN_LDO11_RT_VOUT_SEL_LEN     (4U)
+#define HBN_LDO11_RT_VOUT_SEL_MSK     (((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS)
+#define HBN_LDO11_RT_VOUT_SEL_UMSK    (~(((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS))
+#define HBN_LDO11_AON_VOUT_SEL        HBN_LDO11_AON_VOUT_SEL
+#define HBN_LDO11_AON_VOUT_SEL_POS    (19U)
+#define HBN_LDO11_AON_VOUT_SEL_LEN    (4U)
+#define HBN_LDO11_AON_VOUT_SEL_MSK    (((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS)
+#define HBN_LDO11_AON_VOUT_SEL_UMSK   (~(((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS))
+#define HBN_PU_DCDC18_AON             HBN_PU_DCDC18_AON
+#define HBN_PU_DCDC18_AON_POS         (23U)
+#define HBN_PU_DCDC18_AON_LEN         (1U)
+#define HBN_PU_DCDC18_AON_MSK         (((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS)
+#define HBN_PU_DCDC18_AON_UMSK        (~(((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS))
+#define HBN_RTC_DLY_OPTION            HBN_RTC_DLY_OPTION
+#define HBN_RTC_DLY_OPTION_POS        (24U)
+#define HBN_RTC_DLY_OPTION_LEN        (1U)
+#define HBN_RTC_DLY_OPTION_MSK        (((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS)
+#define HBN_RTC_DLY_OPTION_UMSK       (~(((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS))
+#define HBN_PWR_ON_OPTION             HBN_PWR_ON_OPTION
+#define HBN_PWR_ON_OPTION_POS         (25U)
+#define HBN_PWR_ON_OPTION_LEN         (1U)
+#define HBN_PWR_ON_OPTION_MSK         (((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS)
+#define HBN_PWR_ON_OPTION_UMSK        (~(((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS))
+#define HBN_SRAM_SLP_OPTION           HBN_SRAM_SLP_OPTION
+#define HBN_SRAM_SLP_OPTION_POS       (26U)
+#define HBN_SRAM_SLP_OPTION_LEN       (1U)
+#define HBN_SRAM_SLP_OPTION_MSK       (((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS)
+#define HBN_SRAM_SLP_OPTION_UMSK      (~(((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS))
+#define HBN_SRAM_SLP                  HBN_SRAM_SLP
+#define HBN_SRAM_SLP_POS              (27U)
+#define HBN_SRAM_SLP_LEN              (1U)
+#define HBN_SRAM_SLP_MSK              (((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS)
+#define HBN_SRAM_SLP_UMSK             (~(((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS))
+#define HBN_STATE                     HBN_STATE
+#define HBN_STATE_POS                 (28U)
+#define HBN_STATE_LEN                 (4U)
+#define HBN_STATE_MSK                 (((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS)
+#define HBN_STATE_UMSK                (~(((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS))
+
+/* 0x4 : HBN_TIME_L */
+#define HBN_TIME_L_OFFSET (0x4)
+#define HBN_TIME_L        HBN_TIME_L
+#define HBN_TIME_L_POS    (0U)
+#define HBN_TIME_L_LEN    (32U)
+#define HBN_TIME_L_MSK    (((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS)
+#define HBN_TIME_L_UMSK   (~(((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS))
+
+/* 0x8 : HBN_TIME_H */
+#define HBN_TIME_H_OFFSET (0x8)
+#define HBN_TIME_H        HBN_TIME_H
+#define HBN_TIME_H_POS    (0U)
+#define HBN_TIME_H_LEN    (8U)
+#define HBN_TIME_H_MSK    (((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS)
+#define HBN_TIME_H_UMSK   (~(((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS))
+
+/* 0xC : RTC_TIME_L */
+#define HBN_RTC_TIME_L_OFFSET     (0xC)
+#define HBN_RTC_TIME_LATCH_L      HBN_RTC_TIME_LATCH_L
+#define HBN_RTC_TIME_LATCH_L_POS  (0U)
+#define HBN_RTC_TIME_LATCH_L_LEN  (32U)
+#define HBN_RTC_TIME_LATCH_L_MSK  (((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS)
+#define HBN_RTC_TIME_LATCH_L_UMSK (~(((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS))
+
+/* 0x10 : RTC_TIME_H */
+#define HBN_RTC_TIME_H_OFFSET     (0x10)
+#define HBN_RTC_TIME_LATCH_H      HBN_RTC_TIME_LATCH_H
+#define HBN_RTC_TIME_LATCH_H_POS  (0U)
+#define HBN_RTC_TIME_LATCH_H_LEN  (8U)
+#define HBN_RTC_TIME_LATCH_H_MSK  (((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS)
+#define HBN_RTC_TIME_LATCH_H_UMSK (~(((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS))
+#define HBN_RTC_TIME_LATCH        HBN_RTC_TIME_LATCH
+#define HBN_RTC_TIME_LATCH_POS    (31U)
+#define HBN_RTC_TIME_LATCH_LEN    (1U)
+#define HBN_RTC_TIME_LATCH_MSK    (((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS)
+#define HBN_RTC_TIME_LATCH_UMSK   (~(((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS))
+
+/* 0x14 : HBN_IRQ_MODE */
+#define HBN_IRQ_MODE_OFFSET         (0x14)
+#define HBN_PIN_WAKEUP_MODE         HBN_PIN_WAKEUP_MODE
+#define HBN_PIN_WAKEUP_MODE_POS     (0U)
+#define HBN_PIN_WAKEUP_MODE_LEN     (3U)
+#define HBN_PIN_WAKEUP_MODE_MSK     (((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS)
+#define HBN_PIN_WAKEUP_MODE_UMSK    (~(((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS))
+#define HBN_PIN_WAKEUP_MASK         HBN_PIN_WAKEUP_MASK
+#define HBN_PIN_WAKEUP_MASK_POS     (3U)
+#define HBN_PIN_WAKEUP_MASK_LEN     (5U)
+#define HBN_PIN_WAKEUP_MASK_MSK     (((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS)
+#define HBN_PIN_WAKEUP_MASK_UMSK    (~(((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS))
+#define HBN_REG_AON_PAD_IE_SMT      HBN_REG_AON_PAD_IE_SMT
+#define HBN_REG_AON_PAD_IE_SMT_POS  (8U)
+#define HBN_REG_AON_PAD_IE_SMT_LEN  (5U)
+#define HBN_REG_AON_PAD_IE_SMT_MSK  (((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS)
+#define HBN_REG_AON_PAD_IE_SMT_UMSK (~(((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS))
+#define HBN_REG_EN_HW_PU_PD         HBN_REG_EN_HW_PU_PD
+#define HBN_REG_EN_HW_PU_PD_POS     (16U)
+#define HBN_REG_EN_HW_PU_PD_LEN     (1U)
+#define HBN_REG_EN_HW_PU_PD_MSK     (((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS)
+#define HBN_REG_EN_HW_PU_PD_UMSK    (~(((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS))
+#define HBN_IRQ_BOR_EN              HBN_IRQ_BOR_EN
+#define HBN_IRQ_BOR_EN_POS          (18U)
+#define HBN_IRQ_BOR_EN_LEN          (1U)
+#define HBN_IRQ_BOR_EN_MSK          (((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS)
+#define HBN_IRQ_BOR_EN_UMSK         (~(((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS))
+#define HBN_IRQ_ACOMP0_EN           HBN_IRQ_ACOMP0_EN
+#define HBN_IRQ_ACOMP0_EN_POS       (20U)
+#define HBN_IRQ_ACOMP0_EN_LEN       (2U)
+#define HBN_IRQ_ACOMP0_EN_MSK       (((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS)
+#define HBN_IRQ_ACOMP0_EN_UMSK      (~(((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS))
+#define HBN_IRQ_ACOMP1_EN           HBN_IRQ_ACOMP1_EN
+#define HBN_IRQ_ACOMP1_EN_POS       (22U)
+#define HBN_IRQ_ACOMP1_EN_LEN       (2U)
+#define HBN_IRQ_ACOMP1_EN_MSK       (((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS)
+#define HBN_IRQ_ACOMP1_EN_UMSK      (~(((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS))
+#define HBN_PIN_WAKEUP_SEL          HBN_PIN_WAKEUP_SEL
+#define HBN_PIN_WAKEUP_SEL_POS      (24U)
+#define HBN_PIN_WAKEUP_SEL_LEN      (3U)
+#define HBN_PIN_WAKEUP_SEL_MSK      (((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS)
+#define HBN_PIN_WAKEUP_SEL_UMSK     (~(((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS))
+#define HBN_PIN_WAKEUP_EN           HBN_PIN_WAKEUP_EN
+#define HBN_PIN_WAKEUP_EN_POS       (27U)
+#define HBN_PIN_WAKEUP_EN_LEN       (1U)
+#define HBN_PIN_WAKEUP_EN_MSK       (((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS)
+#define HBN_PIN_WAKEUP_EN_UMSK      (~(((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS))
+
+/* 0x18 : HBN_IRQ_STAT */
+#define HBN_IRQ_STAT_OFFSET (0x18)
+#define HBN_IRQ_STAT        HBN_IRQ_STAT
+#define HBN_IRQ_STAT_POS    (0U)
+#define HBN_IRQ_STAT_LEN    (32U)
+#define HBN_IRQ_STAT_MSK    (((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS)
+#define HBN_IRQ_STAT_UMSK   (~(((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS))
+
+/* 0x1C : HBN_IRQ_CLR */
+#define HBN_IRQ_CLR_OFFSET (0x1C)
+#define HBN_IRQ_CLR        HBN_IRQ_CLR
+#define HBN_IRQ_CLR_POS    (0U)
+#define HBN_IRQ_CLR_LEN    (32U)
+#define HBN_IRQ_CLR_MSK    (((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS)
+#define HBN_IRQ_CLR_UMSK   (~(((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS))
+
+/* 0x20 : HBN_PIR_CFG */
+#define HBN_PIR_CFG_OFFSET    (0x20)
+#define HBN_PIR_HPF_SEL       HBN_PIR_HPF_SEL
+#define HBN_PIR_HPF_SEL_POS   (0U)
+#define HBN_PIR_HPF_SEL_LEN   (2U)
+#define HBN_PIR_HPF_SEL_MSK   (((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS)
+#define HBN_PIR_HPF_SEL_UMSK  (~(((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS))
+#define HBN_PIR_LPF_SEL       HBN_PIR_LPF_SEL
+#define HBN_PIR_LPF_SEL_POS   (2U)
+#define HBN_PIR_LPF_SEL_LEN   (1U)
+#define HBN_PIR_LPF_SEL_MSK   (((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS)
+#define HBN_PIR_LPF_SEL_UMSK  (~(((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS))
+#define HBN_PIR_DIS           HBN_PIR_DIS
+#define HBN_PIR_DIS_POS       (4U)
+#define HBN_PIR_DIS_LEN       (2U)
+#define HBN_PIR_DIS_MSK       (((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS)
+#define HBN_PIR_DIS_UMSK      (~(((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS))
+#define HBN_PIR_EN            HBN_PIR_EN
+#define HBN_PIR_EN_POS        (7U)
+#define HBN_PIR_EN_LEN        (1U)
+#define HBN_PIR_EN_MSK        (((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS)
+#define HBN_PIR_EN_UMSK       (~(((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS))
+#define HBN_GPADC_CGEN        HBN_GPADC_CGEN
+#define HBN_GPADC_CGEN_POS    (8U)
+#define HBN_GPADC_CGEN_LEN    (1U)
+#define HBN_GPADC_CGEN_MSK    (((1U << HBN_GPADC_CGEN_LEN) - 1) << HBN_GPADC_CGEN_POS)
+#define HBN_GPADC_CGEN_UMSK   (~(((1U << HBN_GPADC_CGEN_LEN) - 1) << HBN_GPADC_CGEN_POS))
+#define HBN_GPADC_NOSYNC      HBN_GPADC_NOSYNC
+#define HBN_GPADC_NOSYNC_POS  (9U)
+#define HBN_GPADC_NOSYNC_LEN  (1U)
+#define HBN_GPADC_NOSYNC_MSK  (((1U << HBN_GPADC_NOSYNC_LEN) - 1) << HBN_GPADC_NOSYNC_POS)
+#define HBN_GPADC_NOSYNC_UMSK (~(((1U << HBN_GPADC_NOSYNC_LEN) - 1) << HBN_GPADC_NOSYNC_POS))
+
+/* 0x24 : HBN_PIR_VTH */
+#define HBN_PIR_VTH_OFFSET (0x24)
+#define HBN_PIR_VTH        HBN_PIR_VTH
+#define HBN_PIR_VTH_POS    (0U)
+#define HBN_PIR_VTH_LEN    (14U)
+#define HBN_PIR_VTH_MSK    (((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS)
+#define HBN_PIR_VTH_UMSK   (~(((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS))
+
+/* 0x28 : HBN_PIR_INTERVAL */
+#define HBN_PIR_INTERVAL_OFFSET (0x28)
+#define HBN_PIR_INTERVAL        HBN_PIR_INTERVAL
+#define HBN_PIR_INTERVAL_POS    (0U)
+#define HBN_PIR_INTERVAL_LEN    (12U)
+#define HBN_PIR_INTERVAL_MSK    (((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS)
+#define HBN_PIR_INTERVAL_UMSK   (~(((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS))
+
+/* 0x2C : HBN_MISC */
+#define HBN_MISC_OFFSET             (0x2C)
+#define HBN_BOR_SEL                 HBN_BOR_SEL
+#define HBN_BOR_SEL_POS             (0U)
+#define HBN_BOR_SEL_LEN             (1U)
+#define HBN_BOR_SEL_MSK             (((1U << HBN_BOR_SEL_LEN) - 1) << HBN_BOR_SEL_POS)
+#define HBN_BOR_SEL_UMSK            (~(((1U << HBN_BOR_SEL_LEN) - 1) << HBN_BOR_SEL_POS))
+#define HBN_BOR_VTH                 HBN_BOR_VTH
+#define HBN_BOR_VTH_POS             (1U)
+#define HBN_BOR_VTH_LEN             (1U)
+#define HBN_BOR_VTH_MSK             (((1U << HBN_BOR_VTH_LEN) - 1) << HBN_BOR_VTH_POS)
+#define HBN_BOR_VTH_UMSK            (~(((1U << HBN_BOR_VTH_LEN) - 1) << HBN_BOR_VTH_POS))
+#define HBN_PU_BOR                  HBN_PU_BOR
+#define HBN_PU_BOR_POS              (2U)
+#define HBN_PU_BOR_LEN              (1U)
+#define HBN_PU_BOR_MSK              (((1U << HBN_PU_BOR_LEN) - 1) << HBN_PU_BOR_POS)
+#define HBN_PU_BOR_UMSK             (~(((1U << HBN_PU_BOR_LEN) - 1) << HBN_PU_BOR_POS))
+#define HBN_R_BOR_OUT               HBN_R_BOR_OUT
+#define HBN_R_BOR_OUT_POS           (3U)
+#define HBN_R_BOR_OUT_LEN           (1U)
+#define HBN_R_BOR_OUT_MSK           (((1U << HBN_R_BOR_OUT_LEN) - 1) << HBN_R_BOR_OUT_POS)
+#define HBN_R_BOR_OUT_UMSK          (~(((1U << HBN_R_BOR_OUT_LEN) - 1) << HBN_R_BOR_OUT_POS))
+#define HBN_FLASH_PULLUP_AON        HBN_FLASH_PULLUP_AON
+#define HBN_FLASH_PULLUP_AON_POS    (16U)
+#define HBN_FLASH_PULLUP_AON_LEN    (6U)
+#define HBN_FLASH_PULLUP_AON_MSK    (((1U << HBN_FLASH_PULLUP_AON_LEN) - 1) << HBN_FLASH_PULLUP_AON_POS)
+#define HBN_FLASH_PULLUP_AON_UMSK   (~(((1U << HBN_FLASH_PULLUP_AON_LEN) - 1) << HBN_FLASH_PULLUP_AON_POS))
+#define HBN_FLASH_PULLDOWN_AON      HBN_FLASH_PULLDOWN_AON
+#define HBN_FLASH_PULLDOWN_AON_POS  (24U)
+#define HBN_FLASH_PULLDOWN_AON_LEN  (6U)
+#define HBN_FLASH_PULLDOWN_AON_MSK  (((1U << HBN_FLASH_PULLDOWN_AON_LEN) - 1) << HBN_FLASH_PULLDOWN_AON_POS)
+#define HBN_FLASH_PULLDOWN_AON_UMSK (~(((1U << HBN_FLASH_PULLDOWN_AON_LEN) - 1) << HBN_FLASH_PULLDOWN_AON_POS))
+
+/* 0x30 : HBN_GLB */
+#define HBN_GLB_OFFSET                    (0x30)
+#define HBN_ROOT_CLK_SEL                  HBN_ROOT_CLK_SEL
+#define HBN_ROOT_CLK_SEL_POS              (0U)
+#define HBN_ROOT_CLK_SEL_LEN              (2U)
+#define HBN_ROOT_CLK_SEL_MSK              (((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS)
+#define HBN_ROOT_CLK_SEL_UMSK             (~(((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS))
+#define HBN_UART_CLK_SEL                  HBN_UART_CLK_SEL
+#define HBN_UART_CLK_SEL_POS              (2U)
+#define HBN_UART_CLK_SEL_LEN              (1U)
+#define HBN_UART_CLK_SEL_MSK              (((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS)
+#define HBN_UART_CLK_SEL_UMSK             (~(((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS))
+#define HBN_F32K_SEL                      HBN_F32K_SEL
+#define HBN_F32K_SEL_POS                  (3U)
+#define HBN_F32K_SEL_LEN                  (2U)
+#define HBN_F32K_SEL_MSK                  (((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS)
+#define HBN_F32K_SEL_UMSK                 (~(((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS))
+#define HBN_PU_RC32K                      HBN_PU_RC32K
+#define HBN_PU_RC32K_POS                  (5U)
+#define HBN_PU_RC32K_LEN                  (1U)
+#define HBN_PU_RC32K_MSK                  (((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS)
+#define HBN_PU_RC32K_UMSK                 (~(((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS))
+#define HBN_LDO11_RT_ILOAD_SEL            HBN_LDO11_RT_ILOAD_SEL
+#define HBN_LDO11_RT_ILOAD_SEL_POS        (6U)
+#define HBN_LDO11_RT_ILOAD_SEL_LEN        (2U)
+#define HBN_LDO11_RT_ILOAD_SEL_MSK        (((1U << HBN_LDO11_RT_ILOAD_SEL_LEN) - 1) << HBN_LDO11_RT_ILOAD_SEL_POS)
+#define HBN_LDO11_RT_ILOAD_SEL_UMSK       (~(((1U << HBN_LDO11_RT_ILOAD_SEL_LEN) - 1) << HBN_LDO11_RT_ILOAD_SEL_POS))
+#define HBN_RESET_EVENT                   HBN_RESET_EVENT
+#define HBN_RESET_EVENT_POS               (8U)
+#define HBN_RESET_EVENT_LEN               (5U)
+#define HBN_RESET_EVENT_MSK               (((1U << HBN_RESET_EVENT_LEN) - 1) << HBN_RESET_EVENT_POS)
+#define HBN_RESET_EVENT_UMSK              (~(((1U << HBN_RESET_EVENT_LEN) - 1) << HBN_RESET_EVENT_POS))
+#define HBN_CLEAR_RESET_EVENT             HBN_CLEAR_RESET_EVENT
+#define HBN_CLEAR_RESET_EVENT_POS         (13U)
+#define HBN_CLEAR_RESET_EVENT_LEN         (1U)
+#define HBN_CLEAR_RESET_EVENT_MSK         (((1U << HBN_CLEAR_RESET_EVENT_LEN) - 1) << HBN_CLEAR_RESET_EVENT_POS)
+#define HBN_CLEAR_RESET_EVENT_UMSK        (~(((1U << HBN_CLEAR_RESET_EVENT_LEN) - 1) << HBN_CLEAR_RESET_EVENT_POS))
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON      HBN_SW_LDO11SOC_VOUT_SEL_AON
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON_POS  (16U)
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN  (4U)
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON_MSK  (((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS)
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON_UMSK (~(((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS))
+#define HBN_SW_LDO11_RT_VOUT_SEL          HBN_SW_LDO11_RT_VOUT_SEL
+#define HBN_SW_LDO11_RT_VOUT_SEL_POS      (24U)
+#define HBN_SW_LDO11_RT_VOUT_SEL_LEN      (4U)
+#define HBN_SW_LDO11_RT_VOUT_SEL_MSK      (((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS)
+#define HBN_SW_LDO11_RT_VOUT_SEL_UMSK     (~(((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS))
+#define HBN_SW_LDO11_AON_VOUT_SEL         HBN_SW_LDO11_AON_VOUT_SEL
+#define HBN_SW_LDO11_AON_VOUT_SEL_POS     (28U)
+#define HBN_SW_LDO11_AON_VOUT_SEL_LEN     (4U)
+#define HBN_SW_LDO11_AON_VOUT_SEL_MSK     (((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_AON_VOUT_SEL_POS)
+#define HBN_SW_LDO11_AON_VOUT_SEL_UMSK    (~(((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_AON_VOUT_SEL_POS))
+
+/* 0x34 : HBN_SRAM */
+#define HBN_SRAM_OFFSET      (0x34)
+#define HBN_RETRAM_EMA       HBN_RETRAM_EMA
+#define HBN_RETRAM_EMA_POS   (0U)
+#define HBN_RETRAM_EMA_LEN   (3U)
+#define HBN_RETRAM_EMA_MSK   (((1U << HBN_RETRAM_EMA_LEN) - 1) << HBN_RETRAM_EMA_POS)
+#define HBN_RETRAM_EMA_UMSK  (~(((1U << HBN_RETRAM_EMA_LEN) - 1) << HBN_RETRAM_EMA_POS))
+#define HBN_RETRAM_EMAW      HBN_RETRAM_EMAW
+#define HBN_RETRAM_EMAW_POS  (3U)
+#define HBN_RETRAM_EMAW_LEN  (2U)
+#define HBN_RETRAM_EMAW_MSK  (((1U << HBN_RETRAM_EMAW_LEN) - 1) << HBN_RETRAM_EMAW_POS)
+#define HBN_RETRAM_EMAW_UMSK (~(((1U << HBN_RETRAM_EMAW_LEN) - 1) << HBN_RETRAM_EMAW_POS))
+#define HBN_RETRAM_RET       HBN_RETRAM_RET
+#define HBN_RETRAM_RET_POS   (6U)
+#define HBN_RETRAM_RET_LEN   (1U)
+#define HBN_RETRAM_RET_MSK   (((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS)
+#define HBN_RETRAM_RET_UMSK  (~(((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS))
+#define HBN_RETRAM_SLP       HBN_RETRAM_SLP
+#define HBN_RETRAM_SLP_POS   (7U)
+#define HBN_RETRAM_SLP_LEN   (1U)
+#define HBN_RETRAM_SLP_MSK   (((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS)
+#define HBN_RETRAM_SLP_UMSK  (~(((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS))
+
+/* 0x100 : HBN_RSV0 */
+#define HBN_RSV0_OFFSET (0x100)
+#define HBN_RSV0        HBN_RSV0
+#define HBN_RSV0_POS    (0U)
+#define HBN_RSV0_LEN    (32U)
+#define HBN_RSV0_MSK    (((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS)
+#define HBN_RSV0_UMSK   (~(((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS))
+
+/* 0x104 : HBN_RSV1 */
+#define HBN_RSV1_OFFSET (0x104)
+#define HBN_RSV1        HBN_RSV1
+#define HBN_RSV1_POS    (0U)
+#define HBN_RSV1_LEN    (32U)
+#define HBN_RSV1_MSK    (((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS)
+#define HBN_RSV1_UMSK   (~(((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS))
+
+/* 0x108 : HBN_RSV2 */
+#define HBN_RSV2_OFFSET (0x108)
+#define HBN_RSV2        HBN_RSV2
+#define HBN_RSV2_POS    (0U)
+#define HBN_RSV2_LEN    (32U)
+#define HBN_RSV2_MSK    (((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS)
+#define HBN_RSV2_UMSK   (~(((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS))
+
+/* 0x10C : HBN_RSV3 */
+#define HBN_RSV3_OFFSET (0x10C)
+#define HBN_RSV3        HBN_RSV3
+#define HBN_RSV3_POS    (0U)
+#define HBN_RSV3_LEN    (32U)
+#define HBN_RSV3_MSK    (((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS)
+#define HBN_RSV3_UMSK   (~(((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS))
+
+/* 0x200 : rc32k_ctrl0 */
+#define HBN_RC32K_CTRL0_OFFSET         (0x200)
+#define HBN_RC32K_CAL_DONE             HBN_RC32K_CAL_DONE
+#define HBN_RC32K_CAL_DONE_POS         (0U)
+#define HBN_RC32K_CAL_DONE_LEN         (1U)
+#define HBN_RC32K_CAL_DONE_MSK         (((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS)
+#define HBN_RC32K_CAL_DONE_UMSK        (~(((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS))
+#define HBN_RC32K_RDY                  HBN_RC32K_RDY
+#define HBN_RC32K_RDY_POS              (1U)
+#define HBN_RC32K_RDY_LEN              (1U)
+#define HBN_RC32K_RDY_MSK              (((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS)
+#define HBN_RC32K_RDY_UMSK             (~(((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS))
+#define HBN_RC32K_CAL_INPROGRESS       HBN_RC32K_CAL_INPROGRESS
+#define HBN_RC32K_CAL_INPROGRESS_POS   (2U)
+#define HBN_RC32K_CAL_INPROGRESS_LEN   (1U)
+#define HBN_RC32K_CAL_INPROGRESS_MSK   (((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS)
+#define HBN_RC32K_CAL_INPROGRESS_UMSK  (~(((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS))
+#define HBN_RC32K_CAL_DIV              HBN_RC32K_CAL_DIV
+#define HBN_RC32K_CAL_DIV_POS          (3U)
+#define HBN_RC32K_CAL_DIV_LEN          (2U)
+#define HBN_RC32K_CAL_DIV_MSK          (((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS)
+#define HBN_RC32K_CAL_DIV_UMSK         (~(((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS))
+#define HBN_RC32K_CAL_PRECHARGE        HBN_RC32K_CAL_PRECHARGE
+#define HBN_RC32K_CAL_PRECHARGE_POS    (5U)
+#define HBN_RC32K_CAL_PRECHARGE_LEN    (1U)
+#define HBN_RC32K_CAL_PRECHARGE_MSK    (((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS)
+#define HBN_RC32K_CAL_PRECHARGE_UMSK   (~(((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS))
+#define HBN_RC32K_DIG_CODE_FR_CAL      HBN_RC32K_DIG_CODE_FR_CAL
+#define HBN_RC32K_DIG_CODE_FR_CAL_POS  (6U)
+#define HBN_RC32K_DIG_CODE_FR_CAL_LEN  (10U)
+#define HBN_RC32K_DIG_CODE_FR_CAL_MSK  (((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) << HBN_RC32K_DIG_CODE_FR_CAL_POS)
+#define HBN_RC32K_DIG_CODE_FR_CAL_UMSK (~(((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) << HBN_RC32K_DIG_CODE_FR_CAL_POS))
+#define HBN_RC32K_VREF_DLY             HBN_RC32K_VREF_DLY
+#define HBN_RC32K_VREF_DLY_POS         (16U)
+#define HBN_RC32K_VREF_DLY_LEN         (2U)
+#define HBN_RC32K_VREF_DLY_MSK         (((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS)
+#define HBN_RC32K_VREF_DLY_UMSK        (~(((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS))
+#define HBN_RC32K_ALLOW_CAL            HBN_RC32K_ALLOW_CAL
+#define HBN_RC32K_ALLOW_CAL_POS        (18U)
+#define HBN_RC32K_ALLOW_CAL_LEN        (1U)
+#define HBN_RC32K_ALLOW_CAL_MSK        (((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS)
+#define HBN_RC32K_ALLOW_CAL_UMSK       (~(((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS))
+#define HBN_RC32K_EXT_CODE_EN          HBN_RC32K_EXT_CODE_EN
+#define HBN_RC32K_EXT_CODE_EN_POS      (19U)
+#define HBN_RC32K_EXT_CODE_EN_LEN      (1U)
+#define HBN_RC32K_EXT_CODE_EN_MSK      (((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS)
+#define HBN_RC32K_EXT_CODE_EN_UMSK     (~(((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS))
+#define HBN_RC32K_CAL_EN               HBN_RC32K_CAL_EN
+#define HBN_RC32K_CAL_EN_POS           (20U)
+#define HBN_RC32K_CAL_EN_LEN           (1U)
+#define HBN_RC32K_CAL_EN_MSK           (((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS)
+#define HBN_RC32K_CAL_EN_UMSK          (~(((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS))
+#define HBN_RC32K_CODE_FR_EXT          HBN_RC32K_CODE_FR_EXT
+#define HBN_RC32K_CODE_FR_EXT_POS      (22U)
+#define HBN_RC32K_CODE_FR_EXT_LEN      (10U)
+#define HBN_RC32K_CODE_FR_EXT_MSK      (((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS)
+#define HBN_RC32K_CODE_FR_EXT_UMSK     (~(((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS))
+
+/* 0x204 : xtal32k */
+#define HBN_XTAL32K_OFFSET            (0x204)
+#define HBN_XTAL32K_HIZ_EN            HBN_XTAL32K_HIZ_EN
+#define HBN_XTAL32K_HIZ_EN_POS        (0U)
+#define HBN_XTAL32K_HIZ_EN_LEN        (1U)
+#define HBN_XTAL32K_HIZ_EN_MSK        (((1U << HBN_XTAL32K_HIZ_EN_LEN) - 1) << HBN_XTAL32K_HIZ_EN_POS)
+#define HBN_XTAL32K_HIZ_EN_UMSK       (~(((1U << HBN_XTAL32K_HIZ_EN_LEN) - 1) << HBN_XTAL32K_HIZ_EN_POS))
+#define HBN_XTAL32K_LOWV_EN           HBN_XTAL32K_LOWV_EN
+#define HBN_XTAL32K_LOWV_EN_POS       (1U)
+#define HBN_XTAL32K_LOWV_EN_LEN       (1U)
+#define HBN_XTAL32K_LOWV_EN_MSK       (((1U << HBN_XTAL32K_LOWV_EN_LEN) - 1) << HBN_XTAL32K_LOWV_EN_POS)
+#define HBN_XTAL32K_LOWV_EN_UMSK      (~(((1U << HBN_XTAL32K_LOWV_EN_LEN) - 1) << HBN_XTAL32K_LOWV_EN_POS))
+#define HBN_XTAL32K_EXT_SEL           HBN_XTAL32K_EXT_SEL
+#define HBN_XTAL32K_EXT_SEL_POS       (2U)
+#define HBN_XTAL32K_EXT_SEL_LEN       (1U)
+#define HBN_XTAL32K_EXT_SEL_MSK       (((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS)
+#define HBN_XTAL32K_EXT_SEL_UMSK      (~(((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS))
+#define HBN_XTAL32K_AMP_CTRL          HBN_XTAL32K_AMP_CTRL
+#define HBN_XTAL32K_AMP_CTRL_POS      (3U)
+#define HBN_XTAL32K_AMP_CTRL_LEN      (2U)
+#define HBN_XTAL32K_AMP_CTRL_MSK      (((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS)
+#define HBN_XTAL32K_AMP_CTRL_UMSK     (~(((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS))
+#define HBN_XTAL32K_REG               HBN_XTAL32K_REG
+#define HBN_XTAL32K_REG_POS           (5U)
+#define HBN_XTAL32K_REG_LEN           (2U)
+#define HBN_XTAL32K_REG_MSK           (((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS)
+#define HBN_XTAL32K_REG_UMSK          (~(((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS))
+#define HBN_XTAL32K_OUTBUF_STRE       HBN_XTAL32K_OUTBUF_STRE
+#define HBN_XTAL32K_OUTBUF_STRE_POS   (7U)
+#define HBN_XTAL32K_OUTBUF_STRE_LEN   (1U)
+#define HBN_XTAL32K_OUTBUF_STRE_MSK   (((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS)
+#define HBN_XTAL32K_OUTBUF_STRE_UMSK  (~(((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS))
+#define HBN_XTAL32K_OTF_SHORT         HBN_XTAL32K_OTF_SHORT
+#define HBN_XTAL32K_OTF_SHORT_POS     (8U)
+#define HBN_XTAL32K_OTF_SHORT_LEN     (1U)
+#define HBN_XTAL32K_OTF_SHORT_MSK     (((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS)
+#define HBN_XTAL32K_OTF_SHORT_UMSK    (~(((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS))
+#define HBN_XTAL32K_INV_STRE          HBN_XTAL32K_INV_STRE
+#define HBN_XTAL32K_INV_STRE_POS      (9U)
+#define HBN_XTAL32K_INV_STRE_LEN      (2U)
+#define HBN_XTAL32K_INV_STRE_MSK      (((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS)
+#define HBN_XTAL32K_INV_STRE_UMSK     (~(((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS))
+#define HBN_XTAL32K_CAPBANK           HBN_XTAL32K_CAPBANK
+#define HBN_XTAL32K_CAPBANK_POS       (11U)
+#define HBN_XTAL32K_CAPBANK_LEN       (6U)
+#define HBN_XTAL32K_CAPBANK_MSK       (((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS)
+#define HBN_XTAL32K_CAPBANK_UMSK      (~(((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS))
+#define HBN_XTAL32K_AC_CAP_SHORT      HBN_XTAL32K_AC_CAP_SHORT
+#define HBN_XTAL32K_AC_CAP_SHORT_POS  (17U)
+#define HBN_XTAL32K_AC_CAP_SHORT_LEN  (1U)
+#define HBN_XTAL32K_AC_CAP_SHORT_MSK  (((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS)
+#define HBN_XTAL32K_AC_CAP_SHORT_UMSK (~(((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS))
+#define HBN_PU_XTAL32K_BUF            HBN_PU_XTAL32K_BUF
+#define HBN_PU_XTAL32K_BUF_POS        (18U)
+#define HBN_PU_XTAL32K_BUF_LEN        (1U)
+#define HBN_PU_XTAL32K_BUF_MSK        (((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS)
+#define HBN_PU_XTAL32K_BUF_UMSK       (~(((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS))
+#define HBN_PU_XTAL32K                HBN_PU_XTAL32K
+#define HBN_PU_XTAL32K_POS            (19U)
+#define HBN_PU_XTAL32K_LEN            (1U)
+#define HBN_PU_XTAL32K_MSK            (((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS)
+#define HBN_PU_XTAL32K_UMSK           (~(((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS))
+
+struct hbn_reg {
+    /* 0x0 : HBN_CTL */
+    union {
+        struct
+        {
+            uint32_t rtc_ctl                  : 7; /* [ 6: 0],        r/w,        0x0 */
+            uint32_t hbn_mode                 : 1; /* [    7],          w,        0x0 */
+            uint32_t trap_mode                : 1; /* [    8],          r,        0x0 */
+            uint32_t pwrdn_hbn_core           : 1; /* [    9],        r/w,        0x0 */
+            uint32_t reserved_10              : 1; /* [   10],       rsvd,        0x0 */
+            uint32_t pwrdn_hbn_rtc            : 1; /* [   11],        r/w,        0x0 */
+            uint32_t sw_rst                   : 1; /* [   12],        r/w,        0x0 */
+            uint32_t hbn_dis_pwr_off_ldo11    : 1; /* [   13],        r/w,        0x0 */
+            uint32_t hbn_dis_pwr_off_ldo11_rt : 1; /* [   14],        r/w,        0x0 */
+            uint32_t hbn_ldo11_rt_vout_sel    : 4; /* [18:15],        r/w,        0xa */
+            uint32_t hbn_ldo11_aon_vout_sel   : 4; /* [22:19],        r/w,        0xa */
+            uint32_t pu_dcdc18_aon            : 1; /* [   23],        r/w,        0x1 */
+            uint32_t rtc_dly_option           : 1; /* [   24],        r/w,        0x0 */
+            uint32_t pwr_on_option            : 1; /* [   25],        r/w,        0x0 */
+            uint32_t sram_slp_option          : 1; /* [   26],        r/w,        0x0 */
+            uint32_t sram_slp                 : 1; /* [   27],          r,        0x0 */
+            uint32_t hbn_state                : 4; /* [31:28],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_CTL;
+
+    /* 0x4 : HBN_TIME_L */
+    union {
+        struct
+        {
+            uint32_t hbn_time_l : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_TIME_L;
+
+    /* 0x8 : HBN_TIME_H */
+    union {
+        struct
+        {
+            uint32_t hbn_time_h    : 8;  /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reserved_8_31 : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_TIME_H;
+
+    /* 0xC : RTC_TIME_L */
+    union {
+        struct
+        {
+            uint32_t rtc_time_latch_l : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } RTC_TIME_L;
+
+    /* 0x10 : RTC_TIME_H */
+    union {
+        struct
+        {
+            uint32_t rtc_time_latch_h : 8;  /* [ 7: 0],          r,        0x0 */
+            uint32_t reserved_8_30    : 23; /* [30: 8],       rsvd,        0x0 */
+            uint32_t rtc_time_latch   : 1;  /* [   31],          w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } RTC_TIME_H;
+
+    /* 0x14 : HBN_IRQ_MODE */
+    union {
+        struct
+        {
+            uint32_t hbn_pin_wakeup_mode : 3; /* [ 2: 0],        r/w,        0x5 */
+            uint32_t hbn_pin_wakeup_mask : 5; /* [ 7: 3],        r/w,        0x0 */
+            uint32_t reg_aon_pad_ie_smt  : 5; /* [12: 8],        r/w,       0x1f */
+            uint32_t reserved_13_15      : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_en_hw_pu_pd     : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reserved_17         : 1; /* [   17],       rsvd,        0x0 */
+            uint32_t irq_bor_en          : 1; /* [   18],        r/w,        0x0 */
+            uint32_t reserved_19         : 1; /* [   19],       rsvd,        0x0 */
+            uint32_t irq_acomp0_en       : 2; /* [21:20],        r/w,        0x0 */
+            uint32_t irq_acomp1_en       : 2; /* [23:22],        r/w,        0x0 */
+            uint32_t pin_wakeup_sel      : 3; /* [26:24],        r/w,        0x3 */
+            uint32_t pin_wakeup_en       : 1; /* [   27],        r/w,        0x0 */
+            uint32_t reserved_28_31      : 4; /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_IRQ_MODE;
+
+    /* 0x18 : HBN_IRQ_STAT */
+    union {
+        struct
+        {
+            uint32_t irq_stat : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_IRQ_STAT;
+
+    /* 0x1C : HBN_IRQ_CLR */
+    union {
+        struct
+        {
+            uint32_t irq_clr : 32; /* [31: 0],          w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_IRQ_CLR;
+
+    /* 0x20 : HBN_PIR_CFG */
+    union {
+        struct
+        {
+            uint32_t pir_hpf_sel    : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t pir_lpf_sel    : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3     : 1;  /* [    3],       rsvd,        0x0 */
+            uint32_t pir_dis        : 2;  /* [ 5: 4],        r/w,        0x0 */
+            uint32_t reserved_6     : 1;  /* [    6],       rsvd,        0x0 */
+            uint32_t pir_en         : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t gpadc_cgen     : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t gpadc_nosync   : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t reserved_10_31 : 22; /* [31:10],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_PIR_CFG;
+
+    /* 0x24 : HBN_PIR_VTH */
+    union {
+        struct
+        {
+            uint32_t pir_vth        : 14; /* [13: 0],        r/w,      0x3ff */
+            uint32_t reserved_14_31 : 18; /* [31:14],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_PIR_VTH;
+
+    /* 0x28 : HBN_PIR_INTERVAL */
+    union {
+        struct
+        {
+            uint32_t pir_interval   : 12; /* [11: 0],        r/w,      0xa3d */
+            uint32_t reserved_12_31 : 20; /* [31:12],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_PIR_INTERVAL;
+
+    /* 0x2C : HBN_MISC */
+    union {
+        struct
+        {
+            uint32_t bor_sel                : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t bor_vth                : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t pu_bor                 : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t r_bor_out              : 1;  /* [    3],          r,        0x0 */
+            uint32_t reserved_4_15          : 12; /* [15: 4],       rsvd,        0x0 */
+            uint32_t hbn_flash_pullup_aon   : 6;  /* [21:16],        r/w,        0x0 */
+            uint32_t reserved_22_23         : 2;  /* [23:22],       rsvd,        0x0 */
+            uint32_t hbn_flash_pulldown_aon : 6;  /* [29:24],        r/w,        0x0 */
+            uint32_t reserved_30_31         : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_MISC;
+
+    /* 0x30 : HBN_GLB */
+    union {
+        struct
+        {
+            uint32_t hbn_root_clk_sel         : 2; /* [ 1: 0],        r/w,        0x0 */
+            uint32_t hbn_uart_clk_sel         : 1; /* [    2],        r/w,        0x0 */
+            uint32_t hbn_f32k_sel             : 2; /* [ 4: 3],        r/w,        0x0 */
+            uint32_t hbn_pu_rc32k             : 1; /* [    5],        r/w,        0x1 */
+            uint32_t ldo11_rt_iload_sel       : 2; /* [ 7: 6],        r/w,        0x1 */
+            uint32_t hbn_reset_event          : 5; /* [12: 8],          r,        0x0 */
+            uint32_t hbn_clear_reset_event    : 1; /* [   13],        r/w,        0x0 */
+            uint32_t reserved_14_15           : 2; /* [15:14],       rsvd,        0x0 */
+            uint32_t sw_ldo11soc_vout_sel_aon : 4; /* [19:16],        r/w,        0xa */
+            uint32_t reserved_20_23           : 4; /* [23:20],       rsvd,        0x0 */
+            uint32_t sw_ldo11_rt_vout_sel     : 4; /* [27:24],        r/w,        0xa */
+            uint32_t sw_ldo11_aon_vout_sel    : 4; /* [31:28],        r/w,        0xa */
+        } BF;
+        uint32_t WORD;
+    } HBN_GLB;
+
+    /* 0x34 : HBN_SRAM */
+    union {
+        struct
+        {
+            uint32_t retram_ema    : 3;  /* [ 2: 0],        r/w,        0x3 */
+            uint32_t retram_emaw   : 2;  /* [ 4: 3],        r/w,        0x1 */
+            uint32_t reserved_5    : 1;  /* [    5],       rsvd,        0x0 */
+            uint32_t retram_ret    : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t retram_slp    : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t reserved_8_31 : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_SRAM;
+
+    /* 0x38  reserved */
+    uint8_t RESERVED0x38[200];
+
+    /* 0x100 : HBN_RSV0 */
+    union {
+        struct
+        {
+            uint32_t HBN_RSV0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_RSV0;
+
+    /* 0x104 : HBN_RSV1 */
+    union {
+        struct
+        {
+            uint32_t HBN_RSV1 : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } HBN_RSV1;
+
+    /* 0x108 : HBN_RSV2 */
+    union {
+        struct
+        {
+            uint32_t HBN_RSV2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_RSV2;
+
+    /* 0x10C : HBN_RSV3 */
+    union {
+        struct
+        {
+            uint32_t HBN_RSV3 : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } HBN_RSV3;
+
+    /* 0x110  reserved */
+    uint8_t RESERVED0x110[240];
+
+    /* 0x200 : rc32k_ctrl0 */
+    union {
+        struct
+        {
+            uint32_t rc32k_cal_done        : 1;  /* [    0],          r,        0x1 */
+            uint32_t rc32k_rdy             : 1;  /* [    1],          r,        0x1 */
+            uint32_t rc32k_cal_inprogress  : 1;  /* [    2],          r,        0x0 */
+            uint32_t rc32k_cal_div         : 2;  /* [ 4: 3],        r/w,        0x3 */
+            uint32_t rc32k_cal_precharge   : 1;  /* [    5],          r,        0x0 */
+            uint32_t rc32k_dig_code_fr_cal : 10; /* [15: 6],          r,      0x200 */
+            uint32_t rc32k_vref_dly        : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t rc32k_allow_cal       : 1;  /* [   18],        r/w,        0x0 */
+            uint32_t rc32k_ext_code_en     : 1;  /* [   19],        r/w,        0x1 */
+            uint32_t rc32k_cal_en          : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t reserved_21           : 1;  /* [   21],       rsvd,        0x0 */
+            uint32_t rc32k_code_fr_ext     : 10; /* [31:22],        r/w,      0x12c */
+        } BF;
+        uint32_t WORD;
+    } rc32k_ctrl0;
+
+    /* 0x204 : xtal32k */
+    union {
+        struct
+        {
+            uint32_t xtal32k_hiz_en       : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t xtal32k_lowv_en      : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t xtal32k_ext_sel      : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t xtal32k_amp_ctrl     : 2;  /* [ 4: 3],        r/w,        0x1 */
+            uint32_t xtal32k_reg          : 2;  /* [ 6: 5],        r/w,        0x1 */
+            uint32_t xtal32k_outbuf_stre  : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t xtal32k_otf_short    : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t xtal32k_inv_stre     : 2;  /* [10: 9],        r/w,        0x1 */
+            uint32_t xtal32k_capbank      : 6;  /* [16:11],        r/w,       0x20 */
+            uint32_t xtal32k_ac_cap_short : 1;  /* [   17],        r/w,        0x1 */
+            uint32_t pu_xtal32k_buf       : 1;  /* [   18],        r/w,        0x1 */
+            uint32_t pu_xtal32k           : 1;  /* [   19],        r/w,        0x1 */
+            uint32_t reserved_20_31       : 12; /* [31:20],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } xtal32k;
+};
+
+typedef volatile struct hbn_reg hbn_reg_t;
+
+#endif /* __HBN_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/i2c_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/i2c_reg.h
new file mode 100644
index 00000000..aab28de6
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/i2c_reg.h
@@ -0,0 +1,557 @@
+/**
+  ******************************************************************************
+  * @file    i2c_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __I2C_REG_H__
+#define __I2C_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : i2c_config */
+#define I2C_CONFIG_OFFSET           (0x0)
+#define I2C_CR_I2C_M_EN             I2C_CR_I2C_M_EN
+#define I2C_CR_I2C_M_EN_POS         (0U)
+#define I2C_CR_I2C_M_EN_LEN         (1U)
+#define I2C_CR_I2C_M_EN_MSK         (((1U << I2C_CR_I2C_M_EN_LEN) - 1) << I2C_CR_I2C_M_EN_POS)
+#define I2C_CR_I2C_M_EN_UMSK        (~(((1U << I2C_CR_I2C_M_EN_LEN) - 1) << I2C_CR_I2C_M_EN_POS))
+#define I2C_CR_I2C_PKT_DIR          I2C_CR_I2C_PKT_DIR
+#define I2C_CR_I2C_PKT_DIR_POS      (1U)
+#define I2C_CR_I2C_PKT_DIR_LEN      (1U)
+#define I2C_CR_I2C_PKT_DIR_MSK      (((1U << I2C_CR_I2C_PKT_DIR_LEN) - 1) << I2C_CR_I2C_PKT_DIR_POS)
+#define I2C_CR_I2C_PKT_DIR_UMSK     (~(((1U << I2C_CR_I2C_PKT_DIR_LEN) - 1) << I2C_CR_I2C_PKT_DIR_POS))
+#define I2C_CR_I2C_DEG_EN           I2C_CR_I2C_DEG_EN
+#define I2C_CR_I2C_DEG_EN_POS       (2U)
+#define I2C_CR_I2C_DEG_EN_LEN       (1U)
+#define I2C_CR_I2C_DEG_EN_MSK       (((1U << I2C_CR_I2C_DEG_EN_LEN) - 1) << I2C_CR_I2C_DEG_EN_POS)
+#define I2C_CR_I2C_DEG_EN_UMSK      (~(((1U << I2C_CR_I2C_DEG_EN_LEN) - 1) << I2C_CR_I2C_DEG_EN_POS))
+#define I2C_CR_I2C_SCL_SYNC_EN      I2C_CR_I2C_SCL_SYNC_EN
+#define I2C_CR_I2C_SCL_SYNC_EN_POS  (3U)
+#define I2C_CR_I2C_SCL_SYNC_EN_LEN  (1U)
+#define I2C_CR_I2C_SCL_SYNC_EN_MSK  (((1U << I2C_CR_I2C_SCL_SYNC_EN_LEN) - 1) << I2C_CR_I2C_SCL_SYNC_EN_POS)
+#define I2C_CR_I2C_SCL_SYNC_EN_UMSK (~(((1U << I2C_CR_I2C_SCL_SYNC_EN_LEN) - 1) << I2C_CR_I2C_SCL_SYNC_EN_POS))
+#define I2C_CR_I2C_SUB_ADDR_EN      I2C_CR_I2C_SUB_ADDR_EN
+#define I2C_CR_I2C_SUB_ADDR_EN_POS  (4U)
+#define I2C_CR_I2C_SUB_ADDR_EN_LEN  (1U)
+#define I2C_CR_I2C_SUB_ADDR_EN_MSK  (((1U << I2C_CR_I2C_SUB_ADDR_EN_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_EN_POS)
+#define I2C_CR_I2C_SUB_ADDR_EN_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_EN_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_EN_POS))
+#define I2C_CR_I2C_SUB_ADDR_BC      I2C_CR_I2C_SUB_ADDR_BC
+#define I2C_CR_I2C_SUB_ADDR_BC_POS  (5U)
+#define I2C_CR_I2C_SUB_ADDR_BC_LEN  (2U)
+#define I2C_CR_I2C_SUB_ADDR_BC_MSK  (((1U << I2C_CR_I2C_SUB_ADDR_BC_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_BC_POS)
+#define I2C_CR_I2C_SUB_ADDR_BC_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_BC_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_BC_POS))
+#define I2C_CR_I2C_SLV_ADDR         I2C_CR_I2C_SLV_ADDR
+#define I2C_CR_I2C_SLV_ADDR_POS     (8U)
+#define I2C_CR_I2C_SLV_ADDR_LEN     (7U)
+#define I2C_CR_I2C_SLV_ADDR_MSK     (((1U << I2C_CR_I2C_SLV_ADDR_LEN) - 1) << I2C_CR_I2C_SLV_ADDR_POS)
+#define I2C_CR_I2C_SLV_ADDR_UMSK    (~(((1U << I2C_CR_I2C_SLV_ADDR_LEN) - 1) << I2C_CR_I2C_SLV_ADDR_POS))
+#define I2C_CR_I2C_PKT_LEN          I2C_CR_I2C_PKT_LEN
+#define I2C_CR_I2C_PKT_LEN_POS      (16U)
+#define I2C_CR_I2C_PKT_LEN_LEN      (8U)
+#define I2C_CR_I2C_PKT_LEN_MSK      (((1U << I2C_CR_I2C_PKT_LEN_LEN) - 1) << I2C_CR_I2C_PKT_LEN_POS)
+#define I2C_CR_I2C_PKT_LEN_UMSK     (~(((1U << I2C_CR_I2C_PKT_LEN_LEN) - 1) << I2C_CR_I2C_PKT_LEN_POS))
+#define I2C_CR_I2C_DEG_CNT          I2C_CR_I2C_DEG_CNT
+#define I2C_CR_I2C_DEG_CNT_POS      (28U)
+#define I2C_CR_I2C_DEG_CNT_LEN      (4U)
+#define I2C_CR_I2C_DEG_CNT_MSK      (((1U << I2C_CR_I2C_DEG_CNT_LEN) - 1) << I2C_CR_I2C_DEG_CNT_POS)
+#define I2C_CR_I2C_DEG_CNT_UMSK     (~(((1U << I2C_CR_I2C_DEG_CNT_LEN) - 1) << I2C_CR_I2C_DEG_CNT_POS))
+
+/* 0x4 : i2c_int_sts */
+#define I2C_INT_STS_OFFSET       (0x4)
+#define I2C_END_INT              I2C_END_INT
+#define I2C_END_INT_POS          (0U)
+#define I2C_END_INT_LEN          (1U)
+#define I2C_END_INT_MSK          (((1U << I2C_END_INT_LEN) - 1) << I2C_END_INT_POS)
+#define I2C_END_INT_UMSK         (~(((1U << I2C_END_INT_LEN) - 1) << I2C_END_INT_POS))
+#define I2C_TXF_INT              I2C_TXF_INT
+#define I2C_TXF_INT_POS          (1U)
+#define I2C_TXF_INT_LEN          (1U)
+#define I2C_TXF_INT_MSK          (((1U << I2C_TXF_INT_LEN) - 1) << I2C_TXF_INT_POS)
+#define I2C_TXF_INT_UMSK         (~(((1U << I2C_TXF_INT_LEN) - 1) << I2C_TXF_INT_POS))
+#define I2C_RXF_INT              I2C_RXF_INT
+#define I2C_RXF_INT_POS          (2U)
+#define I2C_RXF_INT_LEN          (1U)
+#define I2C_RXF_INT_MSK          (((1U << I2C_RXF_INT_LEN) - 1) << I2C_RXF_INT_POS)
+#define I2C_RXF_INT_UMSK         (~(((1U << I2C_RXF_INT_LEN) - 1) << I2C_RXF_INT_POS))
+#define I2C_NAK_INT              I2C_NAK_INT
+#define I2C_NAK_INT_POS          (3U)
+#define I2C_NAK_INT_LEN          (1U)
+#define I2C_NAK_INT_MSK          (((1U << I2C_NAK_INT_LEN) - 1) << I2C_NAK_INT_POS)
+#define I2C_NAK_INT_UMSK         (~(((1U << I2C_NAK_INT_LEN) - 1) << I2C_NAK_INT_POS))
+#define I2C_ARB_INT              I2C_ARB_INT
+#define I2C_ARB_INT_POS          (4U)
+#define I2C_ARB_INT_LEN          (1U)
+#define I2C_ARB_INT_MSK          (((1U << I2C_ARB_INT_LEN) - 1) << I2C_ARB_INT_POS)
+#define I2C_ARB_INT_UMSK         (~(((1U << I2C_ARB_INT_LEN) - 1) << I2C_ARB_INT_POS))
+#define I2C_FER_INT              I2C_FER_INT
+#define I2C_FER_INT_POS          (5U)
+#define I2C_FER_INT_LEN          (1U)
+#define I2C_FER_INT_MSK          (((1U << I2C_FER_INT_LEN) - 1) << I2C_FER_INT_POS)
+#define I2C_FER_INT_UMSK         (~(((1U << I2C_FER_INT_LEN) - 1) << I2C_FER_INT_POS))
+#define I2C_CR_I2C_END_MASK      I2C_CR_I2C_END_MASK
+#define I2C_CR_I2C_END_MASK_POS  (8U)
+#define I2C_CR_I2C_END_MASK_LEN  (1U)
+#define I2C_CR_I2C_END_MASK_MSK  (((1U << I2C_CR_I2C_END_MASK_LEN) - 1) << I2C_CR_I2C_END_MASK_POS)
+#define I2C_CR_I2C_END_MASK_UMSK (~(((1U << I2C_CR_I2C_END_MASK_LEN) - 1) << I2C_CR_I2C_END_MASK_POS))
+#define I2C_CR_I2C_TXF_MASK      I2C_CR_I2C_TXF_MASK
+#define I2C_CR_I2C_TXF_MASK_POS  (9U)
+#define I2C_CR_I2C_TXF_MASK_LEN  (1U)
+#define I2C_CR_I2C_TXF_MASK_MSK  (((1U << I2C_CR_I2C_TXF_MASK_LEN) - 1) << I2C_CR_I2C_TXF_MASK_POS)
+#define I2C_CR_I2C_TXF_MASK_UMSK (~(((1U << I2C_CR_I2C_TXF_MASK_LEN) - 1) << I2C_CR_I2C_TXF_MASK_POS))
+#define I2C_CR_I2C_RXF_MASK      I2C_CR_I2C_RXF_MASK
+#define I2C_CR_I2C_RXF_MASK_POS  (10U)
+#define I2C_CR_I2C_RXF_MASK_LEN  (1U)
+#define I2C_CR_I2C_RXF_MASK_MSK  (((1U << I2C_CR_I2C_RXF_MASK_LEN) - 1) << I2C_CR_I2C_RXF_MASK_POS)
+#define I2C_CR_I2C_RXF_MASK_UMSK (~(((1U << I2C_CR_I2C_RXF_MASK_LEN) - 1) << I2C_CR_I2C_RXF_MASK_POS))
+#define I2C_CR_I2C_NAK_MASK      I2C_CR_I2C_NAK_MASK
+#define I2C_CR_I2C_NAK_MASK_POS  (11U)
+#define I2C_CR_I2C_NAK_MASK_LEN  (1U)
+#define I2C_CR_I2C_NAK_MASK_MSK  (((1U << I2C_CR_I2C_NAK_MASK_LEN) - 1) << I2C_CR_I2C_NAK_MASK_POS)
+#define I2C_CR_I2C_NAK_MASK_UMSK (~(((1U << I2C_CR_I2C_NAK_MASK_LEN) - 1) << I2C_CR_I2C_NAK_MASK_POS))
+#define I2C_CR_I2C_ARB_MASK      I2C_CR_I2C_ARB_MASK
+#define I2C_CR_I2C_ARB_MASK_POS  (12U)
+#define I2C_CR_I2C_ARB_MASK_LEN  (1U)
+#define I2C_CR_I2C_ARB_MASK_MSK  (((1U << I2C_CR_I2C_ARB_MASK_LEN) - 1) << I2C_CR_I2C_ARB_MASK_POS)
+#define I2C_CR_I2C_ARB_MASK_UMSK (~(((1U << I2C_CR_I2C_ARB_MASK_LEN) - 1) << I2C_CR_I2C_ARB_MASK_POS))
+#define I2C_CR_I2C_FER_MASK      I2C_CR_I2C_FER_MASK
+#define I2C_CR_I2C_FER_MASK_POS  (13U)
+#define I2C_CR_I2C_FER_MASK_LEN  (1U)
+#define I2C_CR_I2C_FER_MASK_MSK  (((1U << I2C_CR_I2C_FER_MASK_LEN) - 1) << I2C_CR_I2C_FER_MASK_POS)
+#define I2C_CR_I2C_FER_MASK_UMSK (~(((1U << I2C_CR_I2C_FER_MASK_LEN) - 1) << I2C_CR_I2C_FER_MASK_POS))
+#define I2C_CR_I2C_END_CLR       I2C_CR_I2C_END_CLR
+#define I2C_CR_I2C_END_CLR_POS   (16U)
+#define I2C_CR_I2C_END_CLR_LEN   (1U)
+#define I2C_CR_I2C_END_CLR_MSK   (((1U << I2C_CR_I2C_END_CLR_LEN) - 1) << I2C_CR_I2C_END_CLR_POS)
+#define I2C_CR_I2C_END_CLR_UMSK  (~(((1U << I2C_CR_I2C_END_CLR_LEN) - 1) << I2C_CR_I2C_END_CLR_POS))
+#define I2C_CR_I2C_NAK_CLR       I2C_CR_I2C_NAK_CLR
+#define I2C_CR_I2C_NAK_CLR_POS   (19U)
+#define I2C_CR_I2C_NAK_CLR_LEN   (1U)
+#define I2C_CR_I2C_NAK_CLR_MSK   (((1U << I2C_CR_I2C_NAK_CLR_LEN) - 1) << I2C_CR_I2C_NAK_CLR_POS)
+#define I2C_CR_I2C_NAK_CLR_UMSK  (~(((1U << I2C_CR_I2C_NAK_CLR_LEN) - 1) << I2C_CR_I2C_NAK_CLR_POS))
+#define I2C_CR_I2C_ARB_CLR       I2C_CR_I2C_ARB_CLR
+#define I2C_CR_I2C_ARB_CLR_POS   (20U)
+#define I2C_CR_I2C_ARB_CLR_LEN   (1U)
+#define I2C_CR_I2C_ARB_CLR_MSK   (((1U << I2C_CR_I2C_ARB_CLR_LEN) - 1) << I2C_CR_I2C_ARB_CLR_POS)
+#define I2C_CR_I2C_ARB_CLR_UMSK  (~(((1U << I2C_CR_I2C_ARB_CLR_LEN) - 1) << I2C_CR_I2C_ARB_CLR_POS))
+#define I2C_CR_I2C_END_EN        I2C_CR_I2C_END_EN
+#define I2C_CR_I2C_END_EN_POS    (24U)
+#define I2C_CR_I2C_END_EN_LEN    (1U)
+#define I2C_CR_I2C_END_EN_MSK    (((1U << I2C_CR_I2C_END_EN_LEN) - 1) << I2C_CR_I2C_END_EN_POS)
+#define I2C_CR_I2C_END_EN_UMSK   (~(((1U << I2C_CR_I2C_END_EN_LEN) - 1) << I2C_CR_I2C_END_EN_POS))
+#define I2C_CR_I2C_TXF_EN        I2C_CR_I2C_TXF_EN
+#define I2C_CR_I2C_TXF_EN_POS    (25U)
+#define I2C_CR_I2C_TXF_EN_LEN    (1U)
+#define I2C_CR_I2C_TXF_EN_MSK    (((1U << I2C_CR_I2C_TXF_EN_LEN) - 1) << I2C_CR_I2C_TXF_EN_POS)
+#define I2C_CR_I2C_TXF_EN_UMSK   (~(((1U << I2C_CR_I2C_TXF_EN_LEN) - 1) << I2C_CR_I2C_TXF_EN_POS))
+#define I2C_CR_I2C_RXF_EN        I2C_CR_I2C_RXF_EN
+#define I2C_CR_I2C_RXF_EN_POS    (26U)
+#define I2C_CR_I2C_RXF_EN_LEN    (1U)
+#define I2C_CR_I2C_RXF_EN_MSK    (((1U << I2C_CR_I2C_RXF_EN_LEN) - 1) << I2C_CR_I2C_RXF_EN_POS)
+#define I2C_CR_I2C_RXF_EN_UMSK   (~(((1U << I2C_CR_I2C_RXF_EN_LEN) - 1) << I2C_CR_I2C_RXF_EN_POS))
+#define I2C_CR_I2C_NAK_EN        I2C_CR_I2C_NAK_EN
+#define I2C_CR_I2C_NAK_EN_POS    (27U)
+#define I2C_CR_I2C_NAK_EN_LEN    (1U)
+#define I2C_CR_I2C_NAK_EN_MSK    (((1U << I2C_CR_I2C_NAK_EN_LEN) - 1) << I2C_CR_I2C_NAK_EN_POS)
+#define I2C_CR_I2C_NAK_EN_UMSK   (~(((1U << I2C_CR_I2C_NAK_EN_LEN) - 1) << I2C_CR_I2C_NAK_EN_POS))
+#define I2C_CR_I2C_ARB_EN        I2C_CR_I2C_ARB_EN
+#define I2C_CR_I2C_ARB_EN_POS    (28U)
+#define I2C_CR_I2C_ARB_EN_LEN    (1U)
+#define I2C_CR_I2C_ARB_EN_MSK    (((1U << I2C_CR_I2C_ARB_EN_LEN) - 1) << I2C_CR_I2C_ARB_EN_POS)
+#define I2C_CR_I2C_ARB_EN_UMSK   (~(((1U << I2C_CR_I2C_ARB_EN_LEN) - 1) << I2C_CR_I2C_ARB_EN_POS))
+#define I2C_CR_I2C_FER_EN        I2C_CR_I2C_FER_EN
+#define I2C_CR_I2C_FER_EN_POS    (29U)
+#define I2C_CR_I2C_FER_EN_LEN    (1U)
+#define I2C_CR_I2C_FER_EN_MSK    (((1U << I2C_CR_I2C_FER_EN_LEN) - 1) << I2C_CR_I2C_FER_EN_POS)
+#define I2C_CR_I2C_FER_EN_UMSK   (~(((1U << I2C_CR_I2C_FER_EN_LEN) - 1) << I2C_CR_I2C_FER_EN_POS))
+
+/* 0x8 : i2c_sub_addr */
+#define I2C_SUB_ADDR_OFFSET         (0x8)
+#define I2C_CR_I2C_SUB_ADDR_B0      I2C_CR_I2C_SUB_ADDR_B0
+#define I2C_CR_I2C_SUB_ADDR_B0_POS  (0U)
+#define I2C_CR_I2C_SUB_ADDR_B0_LEN  (8U)
+#define I2C_CR_I2C_SUB_ADDR_B0_MSK  (((1U << I2C_CR_I2C_SUB_ADDR_B0_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B0_POS)
+#define I2C_CR_I2C_SUB_ADDR_B0_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B0_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B0_POS))
+#define I2C_CR_I2C_SUB_ADDR_B1      I2C_CR_I2C_SUB_ADDR_B1
+#define I2C_CR_I2C_SUB_ADDR_B1_POS  (8U)
+#define I2C_CR_I2C_SUB_ADDR_B1_LEN  (8U)
+#define I2C_CR_I2C_SUB_ADDR_B1_MSK  (((1U << I2C_CR_I2C_SUB_ADDR_B1_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B1_POS)
+#define I2C_CR_I2C_SUB_ADDR_B1_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B1_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B1_POS))
+#define I2C_CR_I2C_SUB_ADDR_B2      I2C_CR_I2C_SUB_ADDR_B2
+#define I2C_CR_I2C_SUB_ADDR_B2_POS  (16U)
+#define I2C_CR_I2C_SUB_ADDR_B2_LEN  (8U)
+#define I2C_CR_I2C_SUB_ADDR_B2_MSK  (((1U << I2C_CR_I2C_SUB_ADDR_B2_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B2_POS)
+#define I2C_CR_I2C_SUB_ADDR_B2_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B2_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B2_POS))
+#define I2C_CR_I2C_SUB_ADDR_B3      I2C_CR_I2C_SUB_ADDR_B3
+#define I2C_CR_I2C_SUB_ADDR_B3_POS  (24U)
+#define I2C_CR_I2C_SUB_ADDR_B3_LEN  (8U)
+#define I2C_CR_I2C_SUB_ADDR_B3_MSK  (((1U << I2C_CR_I2C_SUB_ADDR_B3_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B3_POS)
+#define I2C_CR_I2C_SUB_ADDR_B3_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B3_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B3_POS))
+
+/* 0xC : i2c_bus_busy */
+#define I2C_BUS_BUSY_OFFSET          (0xC)
+#define I2C_STS_I2C_BUS_BUSY         I2C_STS_I2C_BUS_BUSY
+#define I2C_STS_I2C_BUS_BUSY_POS     (0U)
+#define I2C_STS_I2C_BUS_BUSY_LEN     (1U)
+#define I2C_STS_I2C_BUS_BUSY_MSK     (((1U << I2C_STS_I2C_BUS_BUSY_LEN) - 1) << I2C_STS_I2C_BUS_BUSY_POS)
+#define I2C_STS_I2C_BUS_BUSY_UMSK    (~(((1U << I2C_STS_I2C_BUS_BUSY_LEN) - 1) << I2C_STS_I2C_BUS_BUSY_POS))
+#define I2C_CR_I2C_BUS_BUSY_CLR      I2C_CR_I2C_BUS_BUSY_CLR
+#define I2C_CR_I2C_BUS_BUSY_CLR_POS  (1U)
+#define I2C_CR_I2C_BUS_BUSY_CLR_LEN  (1U)
+#define I2C_CR_I2C_BUS_BUSY_CLR_MSK  (((1U << I2C_CR_I2C_BUS_BUSY_CLR_LEN) - 1) << I2C_CR_I2C_BUS_BUSY_CLR_POS)
+#define I2C_CR_I2C_BUS_BUSY_CLR_UMSK (~(((1U << I2C_CR_I2C_BUS_BUSY_CLR_LEN) - 1) << I2C_CR_I2C_BUS_BUSY_CLR_POS))
+
+/* 0x10 : i2c_prd_start */
+#define I2C_PRD_START_OFFSET       (0x10)
+#define I2C_CR_I2C_PRD_S_PH_0      I2C_CR_I2C_PRD_S_PH_0
+#define I2C_CR_I2C_PRD_S_PH_0_POS  (0U)
+#define I2C_CR_I2C_PRD_S_PH_0_LEN  (8U)
+#define I2C_CR_I2C_PRD_S_PH_0_MSK  (((1U << I2C_CR_I2C_PRD_S_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_0_POS)
+#define I2C_CR_I2C_PRD_S_PH_0_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_0_POS))
+#define I2C_CR_I2C_PRD_S_PH_1      I2C_CR_I2C_PRD_S_PH_1
+#define I2C_CR_I2C_PRD_S_PH_1_POS  (8U)
+#define I2C_CR_I2C_PRD_S_PH_1_LEN  (8U)
+#define I2C_CR_I2C_PRD_S_PH_1_MSK  (((1U << I2C_CR_I2C_PRD_S_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_1_POS)
+#define I2C_CR_I2C_PRD_S_PH_1_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_1_POS))
+#define I2C_CR_I2C_PRD_S_PH_2      I2C_CR_I2C_PRD_S_PH_2
+#define I2C_CR_I2C_PRD_S_PH_2_POS  (16U)
+#define I2C_CR_I2C_PRD_S_PH_2_LEN  (8U)
+#define I2C_CR_I2C_PRD_S_PH_2_MSK  (((1U << I2C_CR_I2C_PRD_S_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_2_POS)
+#define I2C_CR_I2C_PRD_S_PH_2_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_2_POS))
+#define I2C_CR_I2C_PRD_S_PH_3      I2C_CR_I2C_PRD_S_PH_3
+#define I2C_CR_I2C_PRD_S_PH_3_POS  (24U)
+#define I2C_CR_I2C_PRD_S_PH_3_LEN  (8U)
+#define I2C_CR_I2C_PRD_S_PH_3_MSK  (((1U << I2C_CR_I2C_PRD_S_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_3_POS)
+#define I2C_CR_I2C_PRD_S_PH_3_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_3_POS))
+
+/* 0x14 : i2c_prd_stop */
+#define I2C_PRD_STOP_OFFSET        (0x14)
+#define I2C_CR_I2C_PRD_P_PH_0      I2C_CR_I2C_PRD_P_PH_0
+#define I2C_CR_I2C_PRD_P_PH_0_POS  (0U)
+#define I2C_CR_I2C_PRD_P_PH_0_LEN  (8U)
+#define I2C_CR_I2C_PRD_P_PH_0_MSK  (((1U << I2C_CR_I2C_PRD_P_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_0_POS)
+#define I2C_CR_I2C_PRD_P_PH_0_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_0_POS))
+#define I2C_CR_I2C_PRD_P_PH_1      I2C_CR_I2C_PRD_P_PH_1
+#define I2C_CR_I2C_PRD_P_PH_1_POS  (8U)
+#define I2C_CR_I2C_PRD_P_PH_1_LEN  (8U)
+#define I2C_CR_I2C_PRD_P_PH_1_MSK  (((1U << I2C_CR_I2C_PRD_P_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_1_POS)
+#define I2C_CR_I2C_PRD_P_PH_1_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_1_POS))
+#define I2C_CR_I2C_PRD_P_PH_2      I2C_CR_I2C_PRD_P_PH_2
+#define I2C_CR_I2C_PRD_P_PH_2_POS  (16U)
+#define I2C_CR_I2C_PRD_P_PH_2_LEN  (8U)
+#define I2C_CR_I2C_PRD_P_PH_2_MSK  (((1U << I2C_CR_I2C_PRD_P_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_2_POS)
+#define I2C_CR_I2C_PRD_P_PH_2_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_2_POS))
+#define I2C_CR_I2C_PRD_P_PH_3      I2C_CR_I2C_PRD_P_PH_3
+#define I2C_CR_I2C_PRD_P_PH_3_POS  (24U)
+#define I2C_CR_I2C_PRD_P_PH_3_LEN  (8U)
+#define I2C_CR_I2C_PRD_P_PH_3_MSK  (((1U << I2C_CR_I2C_PRD_P_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_3_POS)
+#define I2C_CR_I2C_PRD_P_PH_3_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_3_POS))
+
+/* 0x18 : i2c_prd_data */
+#define I2C_PRD_DATA_OFFSET        (0x18)
+#define I2C_CR_I2C_PRD_D_PH_0      I2C_CR_I2C_PRD_D_PH_0
+#define I2C_CR_I2C_PRD_D_PH_0_POS  (0U)
+#define I2C_CR_I2C_PRD_D_PH_0_LEN  (8U)
+#define I2C_CR_I2C_PRD_D_PH_0_MSK  (((1U << I2C_CR_I2C_PRD_D_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_0_POS)
+#define I2C_CR_I2C_PRD_D_PH_0_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_0_POS))
+#define I2C_CR_I2C_PRD_D_PH_1      I2C_CR_I2C_PRD_D_PH_1
+#define I2C_CR_I2C_PRD_D_PH_1_POS  (8U)
+#define I2C_CR_I2C_PRD_D_PH_1_LEN  (8U)
+#define I2C_CR_I2C_PRD_D_PH_1_MSK  (((1U << I2C_CR_I2C_PRD_D_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_1_POS)
+#define I2C_CR_I2C_PRD_D_PH_1_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_1_POS))
+#define I2C_CR_I2C_PRD_D_PH_2      I2C_CR_I2C_PRD_D_PH_2
+#define I2C_CR_I2C_PRD_D_PH_2_POS  (16U)
+#define I2C_CR_I2C_PRD_D_PH_2_LEN  (8U)
+#define I2C_CR_I2C_PRD_D_PH_2_MSK  (((1U << I2C_CR_I2C_PRD_D_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_2_POS)
+#define I2C_CR_I2C_PRD_D_PH_2_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_2_POS))
+#define I2C_CR_I2C_PRD_D_PH_3      I2C_CR_I2C_PRD_D_PH_3
+#define I2C_CR_I2C_PRD_D_PH_3_POS  (24U)
+#define I2C_CR_I2C_PRD_D_PH_3_LEN  (8U)
+#define I2C_CR_I2C_PRD_D_PH_3_MSK  (((1U << I2C_CR_I2C_PRD_D_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_3_POS)
+#define I2C_CR_I2C_PRD_D_PH_3_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_3_POS))
+
+/* 0x80 : i2c_fifo_config_0 */
+#define I2C_FIFO_CONFIG_0_OFFSET   (0x80)
+#define I2C_DMA_TX_EN              I2C_DMA_TX_EN
+#define I2C_DMA_TX_EN_POS          (0U)
+#define I2C_DMA_TX_EN_LEN          (1U)
+#define I2C_DMA_TX_EN_MSK          (((1U << I2C_DMA_TX_EN_LEN) - 1) << I2C_DMA_TX_EN_POS)
+#define I2C_DMA_TX_EN_UMSK         (~(((1U << I2C_DMA_TX_EN_LEN) - 1) << I2C_DMA_TX_EN_POS))
+#define I2C_DMA_RX_EN              I2C_DMA_RX_EN
+#define I2C_DMA_RX_EN_POS          (1U)
+#define I2C_DMA_RX_EN_LEN          (1U)
+#define I2C_DMA_RX_EN_MSK          (((1U << I2C_DMA_RX_EN_LEN) - 1) << I2C_DMA_RX_EN_POS)
+#define I2C_DMA_RX_EN_UMSK         (~(((1U << I2C_DMA_RX_EN_LEN) - 1) << I2C_DMA_RX_EN_POS))
+#define I2C_TX_FIFO_CLR            I2C_TX_FIFO_CLR
+#define I2C_TX_FIFO_CLR_POS        (2U)
+#define I2C_TX_FIFO_CLR_LEN        (1U)
+#define I2C_TX_FIFO_CLR_MSK        (((1U << I2C_TX_FIFO_CLR_LEN) - 1) << I2C_TX_FIFO_CLR_POS)
+#define I2C_TX_FIFO_CLR_UMSK       (~(((1U << I2C_TX_FIFO_CLR_LEN) - 1) << I2C_TX_FIFO_CLR_POS))
+#define I2C_RX_FIFO_CLR            I2C_RX_FIFO_CLR
+#define I2C_RX_FIFO_CLR_POS        (3U)
+#define I2C_RX_FIFO_CLR_LEN        (1U)
+#define I2C_RX_FIFO_CLR_MSK        (((1U << I2C_RX_FIFO_CLR_LEN) - 1) << I2C_RX_FIFO_CLR_POS)
+#define I2C_RX_FIFO_CLR_UMSK       (~(((1U << I2C_RX_FIFO_CLR_LEN) - 1) << I2C_RX_FIFO_CLR_POS))
+#define I2C_TX_FIFO_OVERFLOW       I2C_TX_FIFO_OVERFLOW
+#define I2C_TX_FIFO_OVERFLOW_POS   (4U)
+#define I2C_TX_FIFO_OVERFLOW_LEN   (1U)
+#define I2C_TX_FIFO_OVERFLOW_MSK   (((1U << I2C_TX_FIFO_OVERFLOW_LEN) - 1) << I2C_TX_FIFO_OVERFLOW_POS)
+#define I2C_TX_FIFO_OVERFLOW_UMSK  (~(((1U << I2C_TX_FIFO_OVERFLOW_LEN) - 1) << I2C_TX_FIFO_OVERFLOW_POS))
+#define I2C_TX_FIFO_UNDERFLOW      I2C_TX_FIFO_UNDERFLOW
+#define I2C_TX_FIFO_UNDERFLOW_POS  (5U)
+#define I2C_TX_FIFO_UNDERFLOW_LEN  (1U)
+#define I2C_TX_FIFO_UNDERFLOW_MSK  (((1U << I2C_TX_FIFO_UNDERFLOW_LEN) - 1) << I2C_TX_FIFO_UNDERFLOW_POS)
+#define I2C_TX_FIFO_UNDERFLOW_UMSK (~(((1U << I2C_TX_FIFO_UNDERFLOW_LEN) - 1) << I2C_TX_FIFO_UNDERFLOW_POS))
+#define I2C_RX_FIFO_OVERFLOW       I2C_RX_FIFO_OVERFLOW
+#define I2C_RX_FIFO_OVERFLOW_POS   (6U)
+#define I2C_RX_FIFO_OVERFLOW_LEN   (1U)
+#define I2C_RX_FIFO_OVERFLOW_MSK   (((1U << I2C_RX_FIFO_OVERFLOW_LEN) - 1) << I2C_RX_FIFO_OVERFLOW_POS)
+#define I2C_RX_FIFO_OVERFLOW_UMSK  (~(((1U << I2C_RX_FIFO_OVERFLOW_LEN) - 1) << I2C_RX_FIFO_OVERFLOW_POS))
+#define I2C_RX_FIFO_UNDERFLOW      I2C_RX_FIFO_UNDERFLOW
+#define I2C_RX_FIFO_UNDERFLOW_POS  (7U)
+#define I2C_RX_FIFO_UNDERFLOW_LEN  (1U)
+#define I2C_RX_FIFO_UNDERFLOW_MSK  (((1U << I2C_RX_FIFO_UNDERFLOW_LEN) - 1) << I2C_RX_FIFO_UNDERFLOW_POS)
+#define I2C_RX_FIFO_UNDERFLOW_UMSK (~(((1U << I2C_RX_FIFO_UNDERFLOW_LEN) - 1) << I2C_RX_FIFO_UNDERFLOW_POS))
+
+/* 0x84 : i2c_fifo_config_1 */
+#define I2C_FIFO_CONFIG_1_OFFSET (0x84)
+#define I2C_TX_FIFO_CNT          I2C_TX_FIFO_CNT
+#define I2C_TX_FIFO_CNT_POS      (0U)
+#define I2C_TX_FIFO_CNT_LEN      (2U)
+#define I2C_TX_FIFO_CNT_MSK      (((1U << I2C_TX_FIFO_CNT_LEN) - 1) << I2C_TX_FIFO_CNT_POS)
+#define I2C_TX_FIFO_CNT_UMSK     (~(((1U << I2C_TX_FIFO_CNT_LEN) - 1) << I2C_TX_FIFO_CNT_POS))
+#define I2C_RX_FIFO_CNT          I2C_RX_FIFO_CNT
+#define I2C_RX_FIFO_CNT_POS      (8U)
+#define I2C_RX_FIFO_CNT_LEN      (2U)
+#define I2C_RX_FIFO_CNT_MSK      (((1U << I2C_RX_FIFO_CNT_LEN) - 1) << I2C_RX_FIFO_CNT_POS)
+#define I2C_RX_FIFO_CNT_UMSK     (~(((1U << I2C_RX_FIFO_CNT_LEN) - 1) << I2C_RX_FIFO_CNT_POS))
+#define I2C_TX_FIFO_TH           I2C_TX_FIFO_TH
+#define I2C_TX_FIFO_TH_POS       (16U)
+#define I2C_TX_FIFO_TH_LEN       (1U)
+#define I2C_TX_FIFO_TH_MSK       (((1U << I2C_TX_FIFO_TH_LEN) - 1) << I2C_TX_FIFO_TH_POS)
+#define I2C_TX_FIFO_TH_UMSK      (~(((1U << I2C_TX_FIFO_TH_LEN) - 1) << I2C_TX_FIFO_TH_POS))
+#define I2C_RX_FIFO_TH           I2C_RX_FIFO_TH
+#define I2C_RX_FIFO_TH_POS       (24U)
+#define I2C_RX_FIFO_TH_LEN       (1U)
+#define I2C_RX_FIFO_TH_MSK       (((1U << I2C_RX_FIFO_TH_LEN) - 1) << I2C_RX_FIFO_TH_POS)
+#define I2C_RX_FIFO_TH_UMSK      (~(((1U << I2C_RX_FIFO_TH_LEN) - 1) << I2C_RX_FIFO_TH_POS))
+
+/* 0x88 : i2c_fifo_wdata */
+#define I2C_FIFO_WDATA_OFFSET (0x88)
+#define I2C_FIFO_WDATA        I2C_FIFO_WDATA
+#define I2C_FIFO_WDATA_POS    (0U)
+#define I2C_FIFO_WDATA_LEN    (32U)
+#define I2C_FIFO_WDATA_MSK    (((1U << I2C_FIFO_WDATA_LEN) - 1) << I2C_FIFO_WDATA_POS)
+#define I2C_FIFO_WDATA_UMSK   (~(((1U << I2C_FIFO_WDATA_LEN) - 1) << I2C_FIFO_WDATA_POS))
+
+/* 0x8C : i2c_fifo_rdata */
+#define I2C_FIFO_RDATA_OFFSET (0x8C)
+#define I2C_FIFO_RDATA        I2C_FIFO_RDATA
+#define I2C_FIFO_RDATA_POS    (0U)
+#define I2C_FIFO_RDATA_LEN    (32U)
+#define I2C_FIFO_RDATA_MSK    (((1U << I2C_FIFO_RDATA_LEN) - 1) << I2C_FIFO_RDATA_POS)
+#define I2C_FIFO_RDATA_UMSK   (~(((1U << I2C_FIFO_RDATA_LEN) - 1) << I2C_FIFO_RDATA_POS))
+
+struct i2c_reg {
+    /* 0x0 : i2c_config */
+    union {
+        struct
+        {
+            uint32_t cr_i2c_m_en        : 1; /* [    0],        r/w,        0x0 */
+            uint32_t cr_i2c_pkt_dir     : 1; /* [    1],        r/w,        0x1 */
+            uint32_t cr_i2c_deg_en      : 1; /* [    2],        r/w,        0x0 */
+            uint32_t cr_i2c_scl_sync_en : 1; /* [    3],        r/w,        0x1 */
+            uint32_t cr_i2c_sub_addr_en : 1; /* [    4],        r/w,        0x0 */
+            uint32_t cr_i2c_sub_addr_bc : 2; /* [ 6: 5],        r/w,        0x0 */
+            uint32_t reserved_7         : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t cr_i2c_slv_addr    : 7; /* [14: 8],        r/w,        0x0 */
+            uint32_t reserved_15        : 1; /* [   15],       rsvd,        0x0 */
+            uint32_t cr_i2c_pkt_len     : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t reserved_24_27     : 4; /* [27:24],       rsvd,        0x0 */
+            uint32_t cr_i2c_deg_cnt     : 4; /* [31:28],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } i2c_config;
+
+    /* 0x4 : i2c_int_sts */
+    union {
+        struct
+        {
+            uint32_t i2c_end_int     : 1; /* [    0],          r,        0x0 */
+            uint32_t i2c_txf_int     : 1; /* [    1],          r,        0x0 */
+            uint32_t i2c_rxf_int     : 1; /* [    2],          r,        0x0 */
+            uint32_t i2c_nak_int     : 1; /* [    3],          r,        0x0 */
+            uint32_t i2c_arb_int     : 1; /* [    4],          r,        0x0 */
+            uint32_t i2c_fer_int     : 1; /* [    5],          r,        0x0 */
+            uint32_t reserved_6_7    : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t cr_i2c_end_mask : 1; /* [    8],        r/w,        0x1 */
+            uint32_t cr_i2c_txf_mask : 1; /* [    9],        r/w,        0x1 */
+            uint32_t cr_i2c_rxf_mask : 1; /* [   10],        r/w,        0x1 */
+            uint32_t cr_i2c_nak_mask : 1; /* [   11],        r/w,        0x1 */
+            uint32_t cr_i2c_arb_mask : 1; /* [   12],        r/w,        0x1 */
+            uint32_t cr_i2c_fer_mask : 1; /* [   13],        r/w,        0x1 */
+            uint32_t reserved_14_15  : 2; /* [15:14],       rsvd,        0x0 */
+            uint32_t cr_i2c_end_clr  : 1; /* [   16],        w1c,        0x0 */
+            uint32_t rsvd_17         : 1; /* [   17],       rsvd,        0x0 */
+            uint32_t rsvd_18         : 1; /* [   18],       rsvd,        0x0 */
+            uint32_t cr_i2c_nak_clr  : 1; /* [   19],        w1c,        0x0 */
+            uint32_t cr_i2c_arb_clr  : 1; /* [   20],        w1c,        0x0 */
+            uint32_t rsvd_21         : 1; /* [   21],       rsvd,        0x0 */
+            uint32_t reserved_22_23  : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t cr_i2c_end_en   : 1; /* [   24],        r/w,        0x1 */
+            uint32_t cr_i2c_txf_en   : 1; /* [   25],        r/w,        0x1 */
+            uint32_t cr_i2c_rxf_en   : 1; /* [   26],        r/w,        0x1 */
+            uint32_t cr_i2c_nak_en   : 1; /* [   27],        r/w,        0x1 */
+            uint32_t cr_i2c_arb_en   : 1; /* [   28],        r/w,        0x1 */
+            uint32_t cr_i2c_fer_en   : 1; /* [   29],        r/w,        0x1 */
+            uint32_t reserved_30_31  : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } i2c_int_sts;
+
+    /* 0x8 : i2c_sub_addr */
+    union {
+        struct
+        {
+            uint32_t cr_i2c_sub_addr_b0 : 8; /* [ 7: 0],        r/w,        0x0 */
+            uint32_t cr_i2c_sub_addr_b1 : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t cr_i2c_sub_addr_b2 : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t cr_i2c_sub_addr_b3 : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } i2c_sub_addr;
+
+    /* 0xC : i2c_bus_busy */
+    union {
+        struct
+        {
+            uint32_t sts_i2c_bus_busy    : 1;  /* [    0],          r,        0x0 */
+            uint32_t cr_i2c_bus_busy_clr : 1;  /* [    1],        w1c,        0x0 */
+            uint32_t reserved_2_31       : 30; /* [31: 2],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } i2c_bus_busy;
+
+    /* 0x10 : i2c_prd_start */
+    union {
+        struct
+        {
+            uint32_t cr_i2c_prd_s_ph_0 : 8; /* [ 7: 0],        r/w,        0xf */
+            uint32_t cr_i2c_prd_s_ph_1 : 8; /* [15: 8],        r/w,        0xf */
+            uint32_t cr_i2c_prd_s_ph_2 : 8; /* [23:16],        r/w,        0xf */
+            uint32_t cr_i2c_prd_s_ph_3 : 8; /* [31:24],        r/w,        0xf */
+        } BF;
+        uint32_t WORD;
+    } i2c_prd_start;
+
+    /* 0x14 : i2c_prd_stop */
+    union {
+        struct
+        {
+            uint32_t cr_i2c_prd_p_ph_0 : 8; /* [ 7: 0],        r/w,        0xf */
+            uint32_t cr_i2c_prd_p_ph_1 : 8; /* [15: 8],        r/w,        0xf */
+            uint32_t cr_i2c_prd_p_ph_2 : 8; /* [23:16],        r/w,        0xf */
+            uint32_t cr_i2c_prd_p_ph_3 : 8; /* [31:24],        r/w,        0xf */
+        } BF;
+        uint32_t WORD;
+    } i2c_prd_stop;
+
+    /* 0x18 : i2c_prd_data */
+    union {
+        struct
+        {
+            uint32_t cr_i2c_prd_d_ph_0 : 8; /* [ 7: 0],        r/w,        0xf */
+            uint32_t cr_i2c_prd_d_ph_1 : 8; /* [15: 8],        r/w,        0xf */
+            uint32_t cr_i2c_prd_d_ph_2 : 8; /* [23:16],        r/w,        0xf */
+            uint32_t cr_i2c_prd_d_ph_3 : 8; /* [31:24],        r/w,        0xf */
+        } BF;
+        uint32_t WORD;
+    } i2c_prd_data;
+
+    /* 0x1c  reserved */
+    uint8_t RESERVED0x1c[100];
+
+    /* 0x80 : i2c_fifo_config_0 */
+    union {
+        struct
+        {
+            uint32_t i2c_dma_tx_en     : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t i2c_dma_rx_en     : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t tx_fifo_clr       : 1;  /* [    2],        w1c,        0x0 */
+            uint32_t rx_fifo_clr       : 1;  /* [    3],        w1c,        0x0 */
+            uint32_t tx_fifo_overflow  : 1;  /* [    4],          r,        0x0 */
+            uint32_t tx_fifo_underflow : 1;  /* [    5],          r,        0x0 */
+            uint32_t rx_fifo_overflow  : 1;  /* [    6],          r,        0x0 */
+            uint32_t rx_fifo_underflow : 1;  /* [    7],          r,        0x0 */
+            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } i2c_fifo_config_0;
+
+    /* 0x84 : i2c_fifo_config_1 */
+    union {
+        struct
+        {
+            uint32_t tx_fifo_cnt    : 2; /* [ 1: 0],          r,        0x2 */
+            uint32_t reserved_2_7   : 6; /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t rx_fifo_cnt    : 2; /* [ 9: 8],          r,        0x0 */
+            uint32_t reserved_10_15 : 6; /* [15:10],       rsvd,        0x0 */
+            uint32_t tx_fifo_th     : 1; /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17_23 : 7; /* [23:17],       rsvd,        0x0 */
+            uint32_t rx_fifo_th     : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reserved_25_31 : 7; /* [31:25],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } i2c_fifo_config_1;
+
+    /* 0x88 : i2c_fifo_wdata */
+    union {
+        struct
+        {
+            uint32_t i2c_fifo_wdata : 32; /* [31: 0],          w,          x */
+        } BF;
+        uint32_t WORD;
+    } i2c_fifo_wdata;
+
+    /* 0x8C : i2c_fifo_rdata */
+    union {
+        struct
+        {
+            uint32_t i2c_fifo_rdata : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } i2c_fifo_rdata;
+};
+
+typedef volatile struct i2c_reg i2c_reg_t;
+
+#endif /* __I2C_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/i2s_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/i2s_reg.h
new file mode 100644
index 00000000..342fbe28
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/i2s_reg.h
@@ -0,0 +1,455 @@
+/**
+  ******************************************************************************
+  * @file    i2s_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __I2S_REG_H__
+#define __I2S_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : i2s_config */
+#define I2S_CONFIG_OFFSET       (0x0)
+#define I2S_CR_I2S_M_EN         I2S_CR_I2S_M_EN
+#define I2S_CR_I2S_M_EN_POS     (0U)
+#define I2S_CR_I2S_M_EN_LEN     (1U)
+#define I2S_CR_I2S_M_EN_MSK     (((1U << I2S_CR_I2S_M_EN_LEN) - 1) << I2S_CR_I2S_M_EN_POS)
+#define I2S_CR_I2S_M_EN_UMSK    (~(((1U << I2S_CR_I2S_M_EN_LEN) - 1) << I2S_CR_I2S_M_EN_POS))
+#define I2S_CR_I2S_S_EN         I2S_CR_I2S_S_EN
+#define I2S_CR_I2S_S_EN_POS     (1U)
+#define I2S_CR_I2S_S_EN_LEN     (1U)
+#define I2S_CR_I2S_S_EN_MSK     (((1U << I2S_CR_I2S_S_EN_LEN) - 1) << I2S_CR_I2S_S_EN_POS)
+#define I2S_CR_I2S_S_EN_UMSK    (~(((1U << I2S_CR_I2S_S_EN_LEN) - 1) << I2S_CR_I2S_S_EN_POS))
+#define I2S_CR_I2S_TXD_EN       I2S_CR_I2S_TXD_EN
+#define I2S_CR_I2S_TXD_EN_POS   (2U)
+#define I2S_CR_I2S_TXD_EN_LEN   (1U)
+#define I2S_CR_I2S_TXD_EN_MSK   (((1U << I2S_CR_I2S_TXD_EN_LEN) - 1) << I2S_CR_I2S_TXD_EN_POS)
+#define I2S_CR_I2S_TXD_EN_UMSK  (~(((1U << I2S_CR_I2S_TXD_EN_LEN) - 1) << I2S_CR_I2S_TXD_EN_POS))
+#define I2S_CR_I2S_RXD_EN       I2S_CR_I2S_RXD_EN
+#define I2S_CR_I2S_RXD_EN_POS   (3U)
+#define I2S_CR_I2S_RXD_EN_LEN   (1U)
+#define I2S_CR_I2S_RXD_EN_MSK   (((1U << I2S_CR_I2S_RXD_EN_LEN) - 1) << I2S_CR_I2S_RXD_EN_POS)
+#define I2S_CR_I2S_RXD_EN_UMSK  (~(((1U << I2S_CR_I2S_RXD_EN_LEN) - 1) << I2S_CR_I2S_RXD_EN_POS))
+#define I2S_CR_MONO_MODE        I2S_CR_MONO_MODE
+#define I2S_CR_MONO_MODE_POS    (4U)
+#define I2S_CR_MONO_MODE_LEN    (1U)
+#define I2S_CR_MONO_MODE_MSK    (((1U << I2S_CR_MONO_MODE_LEN) - 1) << I2S_CR_MONO_MODE_POS)
+#define I2S_CR_MONO_MODE_UMSK   (~(((1U << I2S_CR_MONO_MODE_LEN) - 1) << I2S_CR_MONO_MODE_POS))
+#define I2S_CR_MUTE_MODE        I2S_CR_MUTE_MODE
+#define I2S_CR_MUTE_MODE_POS    (5U)
+#define I2S_CR_MUTE_MODE_LEN    (1U)
+#define I2S_CR_MUTE_MODE_MSK    (((1U << I2S_CR_MUTE_MODE_LEN) - 1) << I2S_CR_MUTE_MODE_POS)
+#define I2S_CR_MUTE_MODE_UMSK   (~(((1U << I2S_CR_MUTE_MODE_LEN) - 1) << I2S_CR_MUTE_MODE_POS))
+#define I2S_CR_FS_1T_MODE       I2S_CR_FS_1T_MODE
+#define I2S_CR_FS_1T_MODE_POS   (6U)
+#define I2S_CR_FS_1T_MODE_LEN   (1U)
+#define I2S_CR_FS_1T_MODE_MSK   (((1U << I2S_CR_FS_1T_MODE_LEN) - 1) << I2S_CR_FS_1T_MODE_POS)
+#define I2S_CR_FS_1T_MODE_UMSK  (~(((1U << I2S_CR_FS_1T_MODE_LEN) - 1) << I2S_CR_FS_1T_MODE_POS))
+#define I2S_CR_FS_4CH_MODE      I2S_CR_FS_4CH_MODE
+#define I2S_CR_FS_4CH_MODE_POS  (7U)
+#define I2S_CR_FS_4CH_MODE_LEN  (1U)
+#define I2S_CR_FS_4CH_MODE_MSK  (((1U << I2S_CR_FS_4CH_MODE_LEN) - 1) << I2S_CR_FS_4CH_MODE_POS)
+#define I2S_CR_FS_4CH_MODE_UMSK (~(((1U << I2S_CR_FS_4CH_MODE_LEN) - 1) << I2S_CR_FS_4CH_MODE_POS))
+#define I2S_CR_FS_3CH_MODE      I2S_CR_FS_3CH_MODE
+#define I2S_CR_FS_3CH_MODE_POS  (8U)
+#define I2S_CR_FS_3CH_MODE_LEN  (1U)
+#define I2S_CR_FS_3CH_MODE_MSK  (((1U << I2S_CR_FS_3CH_MODE_LEN) - 1) << I2S_CR_FS_3CH_MODE_POS)
+#define I2S_CR_FS_3CH_MODE_UMSK (~(((1U << I2S_CR_FS_3CH_MODE_LEN) - 1) << I2S_CR_FS_3CH_MODE_POS))
+#define I2S_CR_FRAME_SIZE       I2S_CR_FRAME_SIZE
+#define I2S_CR_FRAME_SIZE_POS   (12U)
+#define I2S_CR_FRAME_SIZE_LEN   (2U)
+#define I2S_CR_FRAME_SIZE_MSK   (((1U << I2S_CR_FRAME_SIZE_LEN) - 1) << I2S_CR_FRAME_SIZE_POS)
+#define I2S_CR_FRAME_SIZE_UMSK  (~(((1U << I2S_CR_FRAME_SIZE_LEN) - 1) << I2S_CR_FRAME_SIZE_POS))
+#define I2S_CR_DATA_SIZE        I2S_CR_DATA_SIZE
+#define I2S_CR_DATA_SIZE_POS    (14U)
+#define I2S_CR_DATA_SIZE_LEN    (2U)
+#define I2S_CR_DATA_SIZE_MSK    (((1U << I2S_CR_DATA_SIZE_LEN) - 1) << I2S_CR_DATA_SIZE_POS)
+#define I2S_CR_DATA_SIZE_UMSK   (~(((1U << I2S_CR_DATA_SIZE_LEN) - 1) << I2S_CR_DATA_SIZE_POS))
+#define I2S_CR_I2S_MODE         I2S_CR_I2S_MODE
+#define I2S_CR_I2S_MODE_POS     (16U)
+#define I2S_CR_I2S_MODE_LEN     (2U)
+#define I2S_CR_I2S_MODE_MSK     (((1U << I2S_CR_I2S_MODE_LEN) - 1) << I2S_CR_I2S_MODE_POS)
+#define I2S_CR_I2S_MODE_UMSK    (~(((1U << I2S_CR_I2S_MODE_LEN) - 1) << I2S_CR_I2S_MODE_POS))
+#define I2S_CR_ENDIAN           I2S_CR_ENDIAN
+#define I2S_CR_ENDIAN_POS       (18U)
+#define I2S_CR_ENDIAN_LEN       (1U)
+#define I2S_CR_ENDIAN_MSK       (((1U << I2S_CR_ENDIAN_LEN) - 1) << I2S_CR_ENDIAN_POS)
+#define I2S_CR_ENDIAN_UMSK      (~(((1U << I2S_CR_ENDIAN_LEN) - 1) << I2S_CR_ENDIAN_POS))
+#define I2S_CR_MONO_RX_CH       I2S_CR_MONO_RX_CH
+#define I2S_CR_MONO_RX_CH_POS   (19U)
+#define I2S_CR_MONO_RX_CH_LEN   (1U)
+#define I2S_CR_MONO_RX_CH_MSK   (((1U << I2S_CR_MONO_RX_CH_LEN) - 1) << I2S_CR_MONO_RX_CH_POS)
+#define I2S_CR_MONO_RX_CH_UMSK  (~(((1U << I2S_CR_MONO_RX_CH_LEN) - 1) << I2S_CR_MONO_RX_CH_POS))
+#define I2S_CR_OFS_CNT          I2S_CR_OFS_CNT
+#define I2S_CR_OFS_CNT_POS      (20U)
+#define I2S_CR_OFS_CNT_LEN      (5U)
+#define I2S_CR_OFS_CNT_MSK      (((1U << I2S_CR_OFS_CNT_LEN) - 1) << I2S_CR_OFS_CNT_POS)
+#define I2S_CR_OFS_CNT_UMSK     (~(((1U << I2S_CR_OFS_CNT_LEN) - 1) << I2S_CR_OFS_CNT_POS))
+#define I2S_CR_OFS_EN           I2S_CR_OFS_EN
+#define I2S_CR_OFS_EN_POS       (25U)
+#define I2S_CR_OFS_EN_LEN       (1U)
+#define I2S_CR_OFS_EN_MSK       (((1U << I2S_CR_OFS_EN_LEN) - 1) << I2S_CR_OFS_EN_POS)
+#define I2S_CR_OFS_EN_UMSK      (~(((1U << I2S_CR_OFS_EN_LEN) - 1) << I2S_CR_OFS_EN_POS))
+
+/* 0x4 : i2s_int_sts */
+#define I2S_INT_STS_OFFSET       (0x4)
+#define I2S_TXF_INT              I2S_TXF_INT
+#define I2S_TXF_INT_POS          (0U)
+#define I2S_TXF_INT_LEN          (1U)
+#define I2S_TXF_INT_MSK          (((1U << I2S_TXF_INT_LEN) - 1) << I2S_TXF_INT_POS)
+#define I2S_TXF_INT_UMSK         (~(((1U << I2S_TXF_INT_LEN) - 1) << I2S_TXF_INT_POS))
+#define I2S_RXF_INT              I2S_RXF_INT
+#define I2S_RXF_INT_POS          (1U)
+#define I2S_RXF_INT_LEN          (1U)
+#define I2S_RXF_INT_MSK          (((1U << I2S_RXF_INT_LEN) - 1) << I2S_RXF_INT_POS)
+#define I2S_RXF_INT_UMSK         (~(((1U << I2S_RXF_INT_LEN) - 1) << I2S_RXF_INT_POS))
+#define I2S_FER_INT              I2S_FER_INT
+#define I2S_FER_INT_POS          (2U)
+#define I2S_FER_INT_LEN          (1U)
+#define I2S_FER_INT_MSK          (((1U << I2S_FER_INT_LEN) - 1) << I2S_FER_INT_POS)
+#define I2S_FER_INT_UMSK         (~(((1U << I2S_FER_INT_LEN) - 1) << I2S_FER_INT_POS))
+#define I2S_CR_I2S_TXF_MASK      I2S_CR_I2S_TXF_MASK
+#define I2S_CR_I2S_TXF_MASK_POS  (8U)
+#define I2S_CR_I2S_TXF_MASK_LEN  (1U)
+#define I2S_CR_I2S_TXF_MASK_MSK  (((1U << I2S_CR_I2S_TXF_MASK_LEN) - 1) << I2S_CR_I2S_TXF_MASK_POS)
+#define I2S_CR_I2S_TXF_MASK_UMSK (~(((1U << I2S_CR_I2S_TXF_MASK_LEN) - 1) << I2S_CR_I2S_TXF_MASK_POS))
+#define I2S_CR_I2S_RXF_MASK      I2S_CR_I2S_RXF_MASK
+#define I2S_CR_I2S_RXF_MASK_POS  (9U)
+#define I2S_CR_I2S_RXF_MASK_LEN  (1U)
+#define I2S_CR_I2S_RXF_MASK_MSK  (((1U << I2S_CR_I2S_RXF_MASK_LEN) - 1) << I2S_CR_I2S_RXF_MASK_POS)
+#define I2S_CR_I2S_RXF_MASK_UMSK (~(((1U << I2S_CR_I2S_RXF_MASK_LEN) - 1) << I2S_CR_I2S_RXF_MASK_POS))
+#define I2S_CR_I2S_FER_MASK      I2S_CR_I2S_FER_MASK
+#define I2S_CR_I2S_FER_MASK_POS  (10U)
+#define I2S_CR_I2S_FER_MASK_LEN  (1U)
+#define I2S_CR_I2S_FER_MASK_MSK  (((1U << I2S_CR_I2S_FER_MASK_LEN) - 1) << I2S_CR_I2S_FER_MASK_POS)
+#define I2S_CR_I2S_FER_MASK_UMSK (~(((1U << I2S_CR_I2S_FER_MASK_LEN) - 1) << I2S_CR_I2S_FER_MASK_POS))
+#define I2S_CR_I2S_TXF_EN        I2S_CR_I2S_TXF_EN
+#define I2S_CR_I2S_TXF_EN_POS    (24U)
+#define I2S_CR_I2S_TXF_EN_LEN    (1U)
+#define I2S_CR_I2S_TXF_EN_MSK    (((1U << I2S_CR_I2S_TXF_EN_LEN) - 1) << I2S_CR_I2S_TXF_EN_POS)
+#define I2S_CR_I2S_TXF_EN_UMSK   (~(((1U << I2S_CR_I2S_TXF_EN_LEN) - 1) << I2S_CR_I2S_TXF_EN_POS))
+#define I2S_CR_I2S_RXF_EN        I2S_CR_I2S_RXF_EN
+#define I2S_CR_I2S_RXF_EN_POS    (25U)
+#define I2S_CR_I2S_RXF_EN_LEN    (1U)
+#define I2S_CR_I2S_RXF_EN_MSK    (((1U << I2S_CR_I2S_RXF_EN_LEN) - 1) << I2S_CR_I2S_RXF_EN_POS)
+#define I2S_CR_I2S_RXF_EN_UMSK   (~(((1U << I2S_CR_I2S_RXF_EN_LEN) - 1) << I2S_CR_I2S_RXF_EN_POS))
+#define I2S_CR_I2S_FER_EN        I2S_CR_I2S_FER_EN
+#define I2S_CR_I2S_FER_EN_POS    (26U)
+#define I2S_CR_I2S_FER_EN_LEN    (1U)
+#define I2S_CR_I2S_FER_EN_MSK    (((1U << I2S_CR_I2S_FER_EN_LEN) - 1) << I2S_CR_I2S_FER_EN_POS)
+#define I2S_CR_I2S_FER_EN_UMSK   (~(((1U << I2S_CR_I2S_FER_EN_LEN) - 1) << I2S_CR_I2S_FER_EN_POS))
+
+/* 0x10 : i2s_bclk_config */
+#define I2S_BCLK_CONFIG_OFFSET (0x10)
+#define I2S_CR_BCLK_DIV_L      I2S_CR_BCLK_DIV_L
+#define I2S_CR_BCLK_DIV_L_POS  (0U)
+#define I2S_CR_BCLK_DIV_L_LEN  (12U)
+#define I2S_CR_BCLK_DIV_L_MSK  (((1U << I2S_CR_BCLK_DIV_L_LEN) - 1) << I2S_CR_BCLK_DIV_L_POS)
+#define I2S_CR_BCLK_DIV_L_UMSK (~(((1U << I2S_CR_BCLK_DIV_L_LEN) - 1) << I2S_CR_BCLK_DIV_L_POS))
+#define I2S_CR_BCLK_DIV_H      I2S_CR_BCLK_DIV_H
+#define I2S_CR_BCLK_DIV_H_POS  (16U)
+#define I2S_CR_BCLK_DIV_H_LEN  (12U)
+#define I2S_CR_BCLK_DIV_H_MSK  (((1U << I2S_CR_BCLK_DIV_H_LEN) - 1) << I2S_CR_BCLK_DIV_H_POS)
+#define I2S_CR_BCLK_DIV_H_UMSK (~(((1U << I2S_CR_BCLK_DIV_H_LEN) - 1) << I2S_CR_BCLK_DIV_H_POS))
+
+/* 0x80 : i2s_fifo_config_0 */
+#define I2S_FIFO_CONFIG_0_OFFSET   (0x80)
+#define I2S_DMA_TX_EN              I2S_DMA_TX_EN
+#define I2S_DMA_TX_EN_POS          (0U)
+#define I2S_DMA_TX_EN_LEN          (1U)
+#define I2S_DMA_TX_EN_MSK          (((1U << I2S_DMA_TX_EN_LEN) - 1) << I2S_DMA_TX_EN_POS)
+#define I2S_DMA_TX_EN_UMSK         (~(((1U << I2S_DMA_TX_EN_LEN) - 1) << I2S_DMA_TX_EN_POS))
+#define I2S_DMA_RX_EN              I2S_DMA_RX_EN
+#define I2S_DMA_RX_EN_POS          (1U)
+#define I2S_DMA_RX_EN_LEN          (1U)
+#define I2S_DMA_RX_EN_MSK          (((1U << I2S_DMA_RX_EN_LEN) - 1) << I2S_DMA_RX_EN_POS)
+#define I2S_DMA_RX_EN_UMSK         (~(((1U << I2S_DMA_RX_EN_LEN) - 1) << I2S_DMA_RX_EN_POS))
+#define I2S_TX_FIFO_CLR            I2S_TX_FIFO_CLR
+#define I2S_TX_FIFO_CLR_POS        (2U)
+#define I2S_TX_FIFO_CLR_LEN        (1U)
+#define I2S_TX_FIFO_CLR_MSK        (((1U << I2S_TX_FIFO_CLR_LEN) - 1) << I2S_TX_FIFO_CLR_POS)
+#define I2S_TX_FIFO_CLR_UMSK       (~(((1U << I2S_TX_FIFO_CLR_LEN) - 1) << I2S_TX_FIFO_CLR_POS))
+#define I2S_RX_FIFO_CLR            I2S_RX_FIFO_CLR
+#define I2S_RX_FIFO_CLR_POS        (3U)
+#define I2S_RX_FIFO_CLR_LEN        (1U)
+#define I2S_RX_FIFO_CLR_MSK        (((1U << I2S_RX_FIFO_CLR_LEN) - 1) << I2S_RX_FIFO_CLR_POS)
+#define I2S_RX_FIFO_CLR_UMSK       (~(((1U << I2S_RX_FIFO_CLR_LEN) - 1) << I2S_RX_FIFO_CLR_POS))
+#define I2S_TX_FIFO_OVERFLOW       I2S_TX_FIFO_OVERFLOW
+#define I2S_TX_FIFO_OVERFLOW_POS   (4U)
+#define I2S_TX_FIFO_OVERFLOW_LEN   (1U)
+#define I2S_TX_FIFO_OVERFLOW_MSK   (((1U << I2S_TX_FIFO_OVERFLOW_LEN) - 1) << I2S_TX_FIFO_OVERFLOW_POS)
+#define I2S_TX_FIFO_OVERFLOW_UMSK  (~(((1U << I2S_TX_FIFO_OVERFLOW_LEN) - 1) << I2S_TX_FIFO_OVERFLOW_POS))
+#define I2S_TX_FIFO_UNDERFLOW      I2S_TX_FIFO_UNDERFLOW
+#define I2S_TX_FIFO_UNDERFLOW_POS  (5U)
+#define I2S_TX_FIFO_UNDERFLOW_LEN  (1U)
+#define I2S_TX_FIFO_UNDERFLOW_MSK  (((1U << I2S_TX_FIFO_UNDERFLOW_LEN) - 1) << I2S_TX_FIFO_UNDERFLOW_POS)
+#define I2S_TX_FIFO_UNDERFLOW_UMSK (~(((1U << I2S_TX_FIFO_UNDERFLOW_LEN) - 1) << I2S_TX_FIFO_UNDERFLOW_POS))
+#define I2S_RX_FIFO_OVERFLOW       I2S_RX_FIFO_OVERFLOW
+#define I2S_RX_FIFO_OVERFLOW_POS   (6U)
+#define I2S_RX_FIFO_OVERFLOW_LEN   (1U)
+#define I2S_RX_FIFO_OVERFLOW_MSK   (((1U << I2S_RX_FIFO_OVERFLOW_LEN) - 1) << I2S_RX_FIFO_OVERFLOW_POS)
+#define I2S_RX_FIFO_OVERFLOW_UMSK  (~(((1U << I2S_RX_FIFO_OVERFLOW_LEN) - 1) << I2S_RX_FIFO_OVERFLOW_POS))
+#define I2S_RX_FIFO_UNDERFLOW      I2S_RX_FIFO_UNDERFLOW
+#define I2S_RX_FIFO_UNDERFLOW_POS  (7U)
+#define I2S_RX_FIFO_UNDERFLOW_LEN  (1U)
+#define I2S_RX_FIFO_UNDERFLOW_MSK  (((1U << I2S_RX_FIFO_UNDERFLOW_LEN) - 1) << I2S_RX_FIFO_UNDERFLOW_POS)
+#define I2S_RX_FIFO_UNDERFLOW_UMSK (~(((1U << I2S_RX_FIFO_UNDERFLOW_LEN) - 1) << I2S_RX_FIFO_UNDERFLOW_POS))
+#define I2S_CR_FIFO_LR_MERGE       I2S_CR_FIFO_LR_MERGE
+#define I2S_CR_FIFO_LR_MERGE_POS   (8U)
+#define I2S_CR_FIFO_LR_MERGE_LEN   (1U)
+#define I2S_CR_FIFO_LR_MERGE_MSK   (((1U << I2S_CR_FIFO_LR_MERGE_LEN) - 1) << I2S_CR_FIFO_LR_MERGE_POS)
+#define I2S_CR_FIFO_LR_MERGE_UMSK  (~(((1U << I2S_CR_FIFO_LR_MERGE_LEN) - 1) << I2S_CR_FIFO_LR_MERGE_POS))
+#define I2S_CR_FIFO_LR_EXCHG       I2S_CR_FIFO_LR_EXCHG
+#define I2S_CR_FIFO_LR_EXCHG_POS   (9U)
+#define I2S_CR_FIFO_LR_EXCHG_LEN   (1U)
+#define I2S_CR_FIFO_LR_EXCHG_MSK   (((1U << I2S_CR_FIFO_LR_EXCHG_LEN) - 1) << I2S_CR_FIFO_LR_EXCHG_POS)
+#define I2S_CR_FIFO_LR_EXCHG_UMSK  (~(((1U << I2S_CR_FIFO_LR_EXCHG_LEN) - 1) << I2S_CR_FIFO_LR_EXCHG_POS))
+#define I2S_CR_FIFO_24B_LJ         I2S_CR_FIFO_24B_LJ
+#define I2S_CR_FIFO_24B_LJ_POS     (10U)
+#define I2S_CR_FIFO_24B_LJ_LEN     (1U)
+#define I2S_CR_FIFO_24B_LJ_MSK     (((1U << I2S_CR_FIFO_24B_LJ_LEN) - 1) << I2S_CR_FIFO_24B_LJ_POS)
+#define I2S_CR_FIFO_24B_LJ_UMSK    (~(((1U << I2S_CR_FIFO_24B_LJ_LEN) - 1) << I2S_CR_FIFO_24B_LJ_POS))
+
+/* 0x84 : i2s_fifo_config_1 */
+#define I2S_FIFO_CONFIG_1_OFFSET (0x84)
+#define I2S_TX_FIFO_CNT          I2S_TX_FIFO_CNT
+#define I2S_TX_FIFO_CNT_POS      (0U)
+#define I2S_TX_FIFO_CNT_LEN      (5U)
+#define I2S_TX_FIFO_CNT_MSK      (((1U << I2S_TX_FIFO_CNT_LEN) - 1) << I2S_TX_FIFO_CNT_POS)
+#define I2S_TX_FIFO_CNT_UMSK     (~(((1U << I2S_TX_FIFO_CNT_LEN) - 1) << I2S_TX_FIFO_CNT_POS))
+#define I2S_RX_FIFO_CNT          I2S_RX_FIFO_CNT
+#define I2S_RX_FIFO_CNT_POS      (8U)
+#define I2S_RX_FIFO_CNT_LEN      (5U)
+#define I2S_RX_FIFO_CNT_MSK      (((1U << I2S_RX_FIFO_CNT_LEN) - 1) << I2S_RX_FIFO_CNT_POS)
+#define I2S_RX_FIFO_CNT_UMSK     (~(((1U << I2S_RX_FIFO_CNT_LEN) - 1) << I2S_RX_FIFO_CNT_POS))
+#define I2S_TX_FIFO_TH           I2S_TX_FIFO_TH
+#define I2S_TX_FIFO_TH_POS       (16U)
+#define I2S_TX_FIFO_TH_LEN       (4U)
+#define I2S_TX_FIFO_TH_MSK       (((1U << I2S_TX_FIFO_TH_LEN) - 1) << I2S_TX_FIFO_TH_POS)
+#define I2S_TX_FIFO_TH_UMSK      (~(((1U << I2S_TX_FIFO_TH_LEN) - 1) << I2S_TX_FIFO_TH_POS))
+#define I2S_RX_FIFO_TH           I2S_RX_FIFO_TH
+#define I2S_RX_FIFO_TH_POS       (24U)
+#define I2S_RX_FIFO_TH_LEN       (4U)
+#define I2S_RX_FIFO_TH_MSK       (((1U << I2S_RX_FIFO_TH_LEN) - 1) << I2S_RX_FIFO_TH_POS)
+#define I2S_RX_FIFO_TH_UMSK      (~(((1U << I2S_RX_FIFO_TH_LEN) - 1) << I2S_RX_FIFO_TH_POS))
+
+/* 0x88 : i2s_fifo_wdata */
+#define I2S_FIFO_WDATA_OFFSET (0x88)
+#define I2S_FIFO_WDATA        I2S_FIFO_WDATA
+#define I2S_FIFO_WDATA_POS    (0U)
+#define I2S_FIFO_WDATA_LEN    (32U)
+#define I2S_FIFO_WDATA_MSK    (((1U << I2S_FIFO_WDATA_LEN) - 1) << I2S_FIFO_WDATA_POS)
+#define I2S_FIFO_WDATA_UMSK   (~(((1U << I2S_FIFO_WDATA_LEN) - 1) << I2S_FIFO_WDATA_POS))
+
+/* 0x8C : i2s_fifo_rdata */
+#define I2S_FIFO_RDATA_OFFSET (0x8C)
+#define I2S_FIFO_RDATA        I2S_FIFO_RDATA
+#define I2S_FIFO_RDATA_POS    (0U)
+#define I2S_FIFO_RDATA_LEN    (32U)
+#define I2S_FIFO_RDATA_MSK    (((1U << I2S_FIFO_RDATA_LEN) - 1) << I2S_FIFO_RDATA_POS)
+#define I2S_FIFO_RDATA_UMSK   (~(((1U << I2S_FIFO_RDATA_LEN) - 1) << I2S_FIFO_RDATA_POS))
+
+/* 0xFC : i2s_io_config */
+#define I2S_IO_CONFIG_OFFSET     (0xFC)
+#define I2S_CR_I2S_TXD_INV       I2S_CR_I2S_TXD_INV
+#define I2S_CR_I2S_TXD_INV_POS   (0U)
+#define I2S_CR_I2S_TXD_INV_LEN   (1U)
+#define I2S_CR_I2S_TXD_INV_MSK   (((1U << I2S_CR_I2S_TXD_INV_LEN) - 1) << I2S_CR_I2S_TXD_INV_POS)
+#define I2S_CR_I2S_TXD_INV_UMSK  (~(((1U << I2S_CR_I2S_TXD_INV_LEN) - 1) << I2S_CR_I2S_TXD_INV_POS))
+#define I2S_CR_I2S_RXD_INV       I2S_CR_I2S_RXD_INV
+#define I2S_CR_I2S_RXD_INV_POS   (1U)
+#define I2S_CR_I2S_RXD_INV_LEN   (1U)
+#define I2S_CR_I2S_RXD_INV_MSK   (((1U << I2S_CR_I2S_RXD_INV_LEN) - 1) << I2S_CR_I2S_RXD_INV_POS)
+#define I2S_CR_I2S_RXD_INV_UMSK  (~(((1U << I2S_CR_I2S_RXD_INV_LEN) - 1) << I2S_CR_I2S_RXD_INV_POS))
+#define I2S_CR_I2S_FS_INV        I2S_CR_I2S_FS_INV
+#define I2S_CR_I2S_FS_INV_POS    (2U)
+#define I2S_CR_I2S_FS_INV_LEN    (1U)
+#define I2S_CR_I2S_FS_INV_MSK    (((1U << I2S_CR_I2S_FS_INV_LEN) - 1) << I2S_CR_I2S_FS_INV_POS)
+#define I2S_CR_I2S_FS_INV_UMSK   (~(((1U << I2S_CR_I2S_FS_INV_LEN) - 1) << I2S_CR_I2S_FS_INV_POS))
+#define I2S_CR_I2S_BCLK_INV      I2S_CR_I2S_BCLK_INV
+#define I2S_CR_I2S_BCLK_INV_POS  (3U)
+#define I2S_CR_I2S_BCLK_INV_LEN  (1U)
+#define I2S_CR_I2S_BCLK_INV_MSK  (((1U << I2S_CR_I2S_BCLK_INV_LEN) - 1) << I2S_CR_I2S_BCLK_INV_POS)
+#define I2S_CR_I2S_BCLK_INV_UMSK (~(((1U << I2S_CR_I2S_BCLK_INV_LEN) - 1) << I2S_CR_I2S_BCLK_INV_POS))
+#define I2S_CR_DEG_CNT           I2S_CR_DEG_CNT
+#define I2S_CR_DEG_CNT_POS       (4U)
+#define I2S_CR_DEG_CNT_LEN       (3U)
+#define I2S_CR_DEG_CNT_MSK       (((1U << I2S_CR_DEG_CNT_LEN) - 1) << I2S_CR_DEG_CNT_POS)
+#define I2S_CR_DEG_CNT_UMSK      (~(((1U << I2S_CR_DEG_CNT_LEN) - 1) << I2S_CR_DEG_CNT_POS))
+#define I2S_CR_DEG_EN            I2S_CR_DEG_EN
+#define I2S_CR_DEG_EN_POS        (7U)
+#define I2S_CR_DEG_EN_LEN        (1U)
+#define I2S_CR_DEG_EN_MSK        (((1U << I2S_CR_DEG_EN_LEN) - 1) << I2S_CR_DEG_EN_POS)
+#define I2S_CR_DEG_EN_UMSK       (~(((1U << I2S_CR_DEG_EN_LEN) - 1) << I2S_CR_DEG_EN_POS))
+
+struct i2s_reg {
+    /* 0x0 : i2s_config */
+    union {
+        struct
+        {
+            uint32_t cr_i2s_m_en    : 1; /* [    0],        r/w,        0x0 */
+            uint32_t cr_i2s_s_en    : 1; /* [    1],        r/w,        0x0 */
+            uint32_t cr_i2s_txd_en  : 1; /* [    2],        r/w,        0x0 */
+            uint32_t cr_i2s_rxd_en  : 1; /* [    3],        r/w,        0x0 */
+            uint32_t cr_mono_mode   : 1; /* [    4],        r/w,        0x0 */
+            uint32_t cr_mute_mode   : 1; /* [    5],        r/w,        0x0 */
+            uint32_t cr_fs_1t_mode  : 1; /* [    6],        r/w,        0x0 */
+            uint32_t cr_fs_4ch_mode : 1; /* [    7],        r/w,        0x0 */
+            uint32_t cr_fs_3ch_mode : 1; /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9_11  : 3; /* [11: 9],       rsvd,        0x0 */
+            uint32_t cr_frame_size  : 2; /* [13:12],        r/w,        0x1 */
+            uint32_t cr_data_size   : 2; /* [15:14],        r/w,        0x1 */
+            uint32_t cr_i2s_mode    : 2; /* [17:16],        r/w,        0x0 */
+            uint32_t cr_endian      : 1; /* [   18],        r/w,        0x0 */
+            uint32_t cr_mono_rx_ch  : 1; /* [   19],        r/w,        0x0 */
+            uint32_t cr_ofs_cnt     : 5; /* [24:20],        r/w,        0x0 */
+            uint32_t cr_ofs_en      : 1; /* [   25],        r/w,        0x0 */
+            uint32_t reserved_26_31 : 6; /* [31:26],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } i2s_config;
+
+    /* 0x4 : i2s_int_sts */
+    union {
+        struct
+        {
+            uint32_t i2s_txf_int     : 1;  /* [    0],          r,        0x0 */
+            uint32_t i2s_rxf_int     : 1;  /* [    1],          r,        0x0 */
+            uint32_t i2s_fer_int     : 1;  /* [    2],          r,        0x0 */
+            uint32_t reserved_3_7    : 5;  /* [ 7: 3],       rsvd,        0x0 */
+            uint32_t cr_i2s_txf_mask : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t cr_i2s_rxf_mask : 1;  /* [    9],        r/w,        0x1 */
+            uint32_t cr_i2s_fer_mask : 1;  /* [   10],        r/w,        0x1 */
+            uint32_t reserved_11_23  : 13; /* [23:11],       rsvd,        0x0 */
+            uint32_t cr_i2s_txf_en   : 1;  /* [   24],        r/w,        0x1 */
+            uint32_t cr_i2s_rxf_en   : 1;  /* [   25],        r/w,        0x1 */
+            uint32_t cr_i2s_fer_en   : 1;  /* [   26],        r/w,        0x1 */
+            uint32_t reserved_27_31  : 5;  /* [31:27],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } i2s_int_sts;
+
+    /* 0x8  reserved */
+    uint8_t RESERVED0x8[8];
+
+    /* 0x10 : i2s_bclk_config */
+    union {
+        struct
+        {
+            uint32_t cr_bclk_div_l  : 12; /* [11: 0],        r/w,        0x1 */
+            uint32_t reserved_12_15 : 4;  /* [15:12],       rsvd,        0x0 */
+            uint32_t cr_bclk_div_h  : 12; /* [27:16],        r/w,        0x1 */
+            uint32_t reserved_28_31 : 4;  /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } i2s_bclk_config;
+
+    /* 0x14  reserved */
+    uint8_t RESERVED0x14[108];
+
+    /* 0x80 : i2s_fifo_config_0 */
+    union {
+        struct
+        {
+            uint32_t i2s_dma_tx_en     : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t i2s_dma_rx_en     : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t tx_fifo_clr       : 1;  /* [    2],        w1c,        0x0 */
+            uint32_t rx_fifo_clr       : 1;  /* [    3],        w1c,        0x0 */
+            uint32_t tx_fifo_overflow  : 1;  /* [    4],          r,        0x0 */
+            uint32_t tx_fifo_underflow : 1;  /* [    5],          r,        0x0 */
+            uint32_t rx_fifo_overflow  : 1;  /* [    6],          r,        0x0 */
+            uint32_t rx_fifo_underflow : 1;  /* [    7],          r,        0x0 */
+            uint32_t cr_fifo_lr_merge  : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t cr_fifo_lr_exchg  : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t cr_fifo_24b_lj    : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t reserved_11_31    : 21; /* [31:11],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } i2s_fifo_config_0;
+
+    /* 0x84 : i2s_fifo_config_1 */
+    union {
+        struct
+        {
+            uint32_t tx_fifo_cnt    : 5; /* [ 4: 0],          r,       0x10 */
+            uint32_t reserved_5_7   : 3; /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t rx_fifo_cnt    : 5; /* [12: 8],          r,        0x0 */
+            uint32_t reserved_13_15 : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t tx_fifo_th     : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reserved_20_23 : 4; /* [23:20],       rsvd,        0x0 */
+            uint32_t rx_fifo_th     : 4; /* [27:24],        r/w,        0x0 */
+            uint32_t reserved_28_31 : 4; /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } i2s_fifo_config_1;
+
+    /* 0x88 : i2s_fifo_wdata */
+    union {
+        struct
+        {
+            uint32_t i2s_fifo_wdata : 32; /* [31: 0],          w,          x */
+        } BF;
+        uint32_t WORD;
+    } i2s_fifo_wdata;
+
+    /* 0x8C : i2s_fifo_rdata */
+    union {
+        struct
+        {
+            uint32_t i2s_fifo_rdata : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } i2s_fifo_rdata;
+
+    /* 0x90  reserved */
+    uint8_t RESERVED0x90[108];
+
+    /* 0xFC : i2s_io_config */
+    union {
+        struct
+        {
+            uint32_t cr_i2s_txd_inv  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t cr_i2s_rxd_inv  : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t cr_i2s_fs_inv   : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t cr_i2s_bclk_inv : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t cr_deg_cnt      : 3;  /* [ 6: 4],        r/w,        0x0 */
+            uint32_t cr_deg_en       : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t reserved_8_31   : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } i2s_io_config;
+};
+
+typedef volatile struct i2s_reg i2s_reg_t;
+
+#endif /* __I2S_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/ir_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/ir_reg.h
new file mode 100644
index 00000000..de0cc214
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/ir_reg.h
@@ -0,0 +1,652 @@
+/**
+  ******************************************************************************
+  * @file    ir_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __IR_REG_H__
+#define __IR_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : irtx_config */
+#define IRTX_CONFIG_OFFSET            (0x0)
+#define IR_CR_IRTX_EN                 IR_CR_IRTX_EN
+#define IR_CR_IRTX_EN_POS             (0U)
+#define IR_CR_IRTX_EN_LEN             (1U)
+#define IR_CR_IRTX_EN_MSK             (((1U << IR_CR_IRTX_EN_LEN) - 1) << IR_CR_IRTX_EN_POS)
+#define IR_CR_IRTX_EN_UMSK            (~(((1U << IR_CR_IRTX_EN_LEN) - 1) << IR_CR_IRTX_EN_POS))
+#define IR_CR_IRTX_OUT_INV            IR_CR_IRTX_OUT_INV
+#define IR_CR_IRTX_OUT_INV_POS        (1U)
+#define IR_CR_IRTX_OUT_INV_LEN        (1U)
+#define IR_CR_IRTX_OUT_INV_MSK        (((1U << IR_CR_IRTX_OUT_INV_LEN) - 1) << IR_CR_IRTX_OUT_INV_POS)
+#define IR_CR_IRTX_OUT_INV_UMSK       (~(((1U << IR_CR_IRTX_OUT_INV_LEN) - 1) << IR_CR_IRTX_OUT_INV_POS))
+#define IR_CR_IRTX_MOD_EN             IR_CR_IRTX_MOD_EN
+#define IR_CR_IRTX_MOD_EN_POS         (2U)
+#define IR_CR_IRTX_MOD_EN_LEN         (1U)
+#define IR_CR_IRTX_MOD_EN_MSK         (((1U << IR_CR_IRTX_MOD_EN_LEN) - 1) << IR_CR_IRTX_MOD_EN_POS)
+#define IR_CR_IRTX_MOD_EN_UMSK        (~(((1U << IR_CR_IRTX_MOD_EN_LEN) - 1) << IR_CR_IRTX_MOD_EN_POS))
+#define IR_CR_IRTX_SWM_EN             IR_CR_IRTX_SWM_EN
+#define IR_CR_IRTX_SWM_EN_POS         (3U)
+#define IR_CR_IRTX_SWM_EN_LEN         (1U)
+#define IR_CR_IRTX_SWM_EN_MSK         (((1U << IR_CR_IRTX_SWM_EN_LEN) - 1) << IR_CR_IRTX_SWM_EN_POS)
+#define IR_CR_IRTX_SWM_EN_UMSK        (~(((1U << IR_CR_IRTX_SWM_EN_LEN) - 1) << IR_CR_IRTX_SWM_EN_POS))
+#define IR_CR_IRTX_DATA_EN            IR_CR_IRTX_DATA_EN
+#define IR_CR_IRTX_DATA_EN_POS        (4U)
+#define IR_CR_IRTX_DATA_EN_LEN        (1U)
+#define IR_CR_IRTX_DATA_EN_MSK        (((1U << IR_CR_IRTX_DATA_EN_LEN) - 1) << IR_CR_IRTX_DATA_EN_POS)
+#define IR_CR_IRTX_DATA_EN_UMSK       (~(((1U << IR_CR_IRTX_DATA_EN_LEN) - 1) << IR_CR_IRTX_DATA_EN_POS))
+#define IR_CR_IRTX_LOGIC0_HL_INV      IR_CR_IRTX_LOGIC0_HL_INV
+#define IR_CR_IRTX_LOGIC0_HL_INV_POS  (5U)
+#define IR_CR_IRTX_LOGIC0_HL_INV_LEN  (1U)
+#define IR_CR_IRTX_LOGIC0_HL_INV_MSK  (((1U << IR_CR_IRTX_LOGIC0_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC0_HL_INV_POS)
+#define IR_CR_IRTX_LOGIC0_HL_INV_UMSK (~(((1U << IR_CR_IRTX_LOGIC0_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC0_HL_INV_POS))
+#define IR_CR_IRTX_LOGIC1_HL_INV      IR_CR_IRTX_LOGIC1_HL_INV
+#define IR_CR_IRTX_LOGIC1_HL_INV_POS  (6U)
+#define IR_CR_IRTX_LOGIC1_HL_INV_LEN  (1U)
+#define IR_CR_IRTX_LOGIC1_HL_INV_MSK  (((1U << IR_CR_IRTX_LOGIC1_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC1_HL_INV_POS)
+#define IR_CR_IRTX_LOGIC1_HL_INV_UMSK (~(((1U << IR_CR_IRTX_LOGIC1_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC1_HL_INV_POS))
+#define IR_CR_IRTX_HEAD_EN            IR_CR_IRTX_HEAD_EN
+#define IR_CR_IRTX_HEAD_EN_POS        (8U)
+#define IR_CR_IRTX_HEAD_EN_LEN        (1U)
+#define IR_CR_IRTX_HEAD_EN_MSK        (((1U << IR_CR_IRTX_HEAD_EN_LEN) - 1) << IR_CR_IRTX_HEAD_EN_POS)
+#define IR_CR_IRTX_HEAD_EN_UMSK       (~(((1U << IR_CR_IRTX_HEAD_EN_LEN) - 1) << IR_CR_IRTX_HEAD_EN_POS))
+#define IR_CR_IRTX_HEAD_HL_INV        IR_CR_IRTX_HEAD_HL_INV
+#define IR_CR_IRTX_HEAD_HL_INV_POS    (9U)
+#define IR_CR_IRTX_HEAD_HL_INV_LEN    (1U)
+#define IR_CR_IRTX_HEAD_HL_INV_MSK    (((1U << IR_CR_IRTX_HEAD_HL_INV_LEN) - 1) << IR_CR_IRTX_HEAD_HL_INV_POS)
+#define IR_CR_IRTX_HEAD_HL_INV_UMSK   (~(((1U << IR_CR_IRTX_HEAD_HL_INV_LEN) - 1) << IR_CR_IRTX_HEAD_HL_INV_POS))
+#define IR_CR_IRTX_TAIL_EN            IR_CR_IRTX_TAIL_EN
+#define IR_CR_IRTX_TAIL_EN_POS        (10U)
+#define IR_CR_IRTX_TAIL_EN_LEN        (1U)
+#define IR_CR_IRTX_TAIL_EN_MSK        (((1U << IR_CR_IRTX_TAIL_EN_LEN) - 1) << IR_CR_IRTX_TAIL_EN_POS)
+#define IR_CR_IRTX_TAIL_EN_UMSK       (~(((1U << IR_CR_IRTX_TAIL_EN_LEN) - 1) << IR_CR_IRTX_TAIL_EN_POS))
+#define IR_CR_IRTX_TAIL_HL_INV        IR_CR_IRTX_TAIL_HL_INV
+#define IR_CR_IRTX_TAIL_HL_INV_POS    (11U)
+#define IR_CR_IRTX_TAIL_HL_INV_LEN    (1U)
+#define IR_CR_IRTX_TAIL_HL_INV_MSK    (((1U << IR_CR_IRTX_TAIL_HL_INV_LEN) - 1) << IR_CR_IRTX_TAIL_HL_INV_POS)
+#define IR_CR_IRTX_TAIL_HL_INV_UMSK   (~(((1U << IR_CR_IRTX_TAIL_HL_INV_LEN) - 1) << IR_CR_IRTX_TAIL_HL_INV_POS))
+#define IR_CR_IRTX_DATA_NUM           IR_CR_IRTX_DATA_NUM
+#define IR_CR_IRTX_DATA_NUM_POS       (12U)
+#define IR_CR_IRTX_DATA_NUM_LEN       (6U)
+#define IR_CR_IRTX_DATA_NUM_MSK       (((1U << IR_CR_IRTX_DATA_NUM_LEN) - 1) << IR_CR_IRTX_DATA_NUM_POS)
+#define IR_CR_IRTX_DATA_NUM_UMSK      (~(((1U << IR_CR_IRTX_DATA_NUM_LEN) - 1) << IR_CR_IRTX_DATA_NUM_POS))
+
+/* 0x4 : irtx_int_sts */
+#define IRTX_INT_STS_OFFSET      (0x4)
+#define IRTX_END_INT             IRTX_END_INT
+#define IRTX_END_INT_POS         (0U)
+#define IRTX_END_INT_LEN         (1U)
+#define IRTX_END_INT_MSK         (((1U << IRTX_END_INT_LEN) - 1) << IRTX_END_INT_POS)
+#define IRTX_END_INT_UMSK        (~(((1U << IRTX_END_INT_LEN) - 1) << IRTX_END_INT_POS))
+#define IR_CR_IRTX_END_MASK      IR_CR_IRTX_END_MASK
+#define IR_CR_IRTX_END_MASK_POS  (8U)
+#define IR_CR_IRTX_END_MASK_LEN  (1U)
+#define IR_CR_IRTX_END_MASK_MSK  (((1U << IR_CR_IRTX_END_MASK_LEN) - 1) << IR_CR_IRTX_END_MASK_POS)
+#define IR_CR_IRTX_END_MASK_UMSK (~(((1U << IR_CR_IRTX_END_MASK_LEN) - 1) << IR_CR_IRTX_END_MASK_POS))
+#define IR_CR_IRTX_END_CLR       IR_CR_IRTX_END_CLR
+#define IR_CR_IRTX_END_CLR_POS   (16U)
+#define IR_CR_IRTX_END_CLR_LEN   (1U)
+#define IR_CR_IRTX_END_CLR_MSK   (((1U << IR_CR_IRTX_END_CLR_LEN) - 1) << IR_CR_IRTX_END_CLR_POS)
+#define IR_CR_IRTX_END_CLR_UMSK  (~(((1U << IR_CR_IRTX_END_CLR_LEN) - 1) << IR_CR_IRTX_END_CLR_POS))
+#define IR_CR_IRTX_END_EN        IR_CR_IRTX_END_EN
+#define IR_CR_IRTX_END_EN_POS    (24U)
+#define IR_CR_IRTX_END_EN_LEN    (1U)
+#define IR_CR_IRTX_END_EN_MSK    (((1U << IR_CR_IRTX_END_EN_LEN) - 1) << IR_CR_IRTX_END_EN_POS)
+#define IR_CR_IRTX_END_EN_UMSK   (~(((1U << IR_CR_IRTX_END_EN_LEN) - 1) << IR_CR_IRTX_END_EN_POS))
+
+/* 0x8 : irtx_data_word0 */
+#define IRTX_DATA_WORD0_OFFSET     (0x8)
+#define IR_CR_IRTX_DATA_WORD0      IR_CR_IRTX_DATA_WORD0
+#define IR_CR_IRTX_DATA_WORD0_POS  (0U)
+#define IR_CR_IRTX_DATA_WORD0_LEN  (32U)
+#define IR_CR_IRTX_DATA_WORD0_MSK  (((1U << IR_CR_IRTX_DATA_WORD0_LEN) - 1) << IR_CR_IRTX_DATA_WORD0_POS)
+#define IR_CR_IRTX_DATA_WORD0_UMSK (~(((1U << IR_CR_IRTX_DATA_WORD0_LEN) - 1) << IR_CR_IRTX_DATA_WORD0_POS))
+
+/* 0xC : irtx_data_word1 */
+#define IRTX_DATA_WORD1_OFFSET     (0xC)
+#define IR_CR_IRTX_DATA_WORD1      IR_CR_IRTX_DATA_WORD1
+#define IR_CR_IRTX_DATA_WORD1_POS  (0U)
+#define IR_CR_IRTX_DATA_WORD1_LEN  (32U)
+#define IR_CR_IRTX_DATA_WORD1_MSK  (((1U << IR_CR_IRTX_DATA_WORD1_LEN) - 1) << IR_CR_IRTX_DATA_WORD1_POS)
+#define IR_CR_IRTX_DATA_WORD1_UMSK (~(((1U << IR_CR_IRTX_DATA_WORD1_LEN) - 1) << IR_CR_IRTX_DATA_WORD1_POS))
+
+/* 0x10 : irtx_pulse_width */
+#define IRTX_PULSE_WIDTH_OFFSET   (0x10)
+#define IR_CR_IRTX_PW_UNIT        IR_CR_IRTX_PW_UNIT
+#define IR_CR_IRTX_PW_UNIT_POS    (0U)
+#define IR_CR_IRTX_PW_UNIT_LEN    (12U)
+#define IR_CR_IRTX_PW_UNIT_MSK    (((1U << IR_CR_IRTX_PW_UNIT_LEN) - 1) << IR_CR_IRTX_PW_UNIT_POS)
+#define IR_CR_IRTX_PW_UNIT_UMSK   (~(((1U << IR_CR_IRTX_PW_UNIT_LEN) - 1) << IR_CR_IRTX_PW_UNIT_POS))
+#define IR_CR_IRTX_MOD_PH0_W      IR_CR_IRTX_MOD_PH0_W
+#define IR_CR_IRTX_MOD_PH0_W_POS  (16U)
+#define IR_CR_IRTX_MOD_PH0_W_LEN  (8U)
+#define IR_CR_IRTX_MOD_PH0_W_MSK  (((1U << IR_CR_IRTX_MOD_PH0_W_LEN) - 1) << IR_CR_IRTX_MOD_PH0_W_POS)
+#define IR_CR_IRTX_MOD_PH0_W_UMSK (~(((1U << IR_CR_IRTX_MOD_PH0_W_LEN) - 1) << IR_CR_IRTX_MOD_PH0_W_POS))
+#define IR_CR_IRTX_MOD_PH1_W      IR_CR_IRTX_MOD_PH1_W
+#define IR_CR_IRTX_MOD_PH1_W_POS  (24U)
+#define IR_CR_IRTX_MOD_PH1_W_LEN  (8U)
+#define IR_CR_IRTX_MOD_PH1_W_MSK  (((1U << IR_CR_IRTX_MOD_PH1_W_LEN) - 1) << IR_CR_IRTX_MOD_PH1_W_POS)
+#define IR_CR_IRTX_MOD_PH1_W_UMSK (~(((1U << IR_CR_IRTX_MOD_PH1_W_LEN) - 1) << IR_CR_IRTX_MOD_PH1_W_POS))
+
+/* 0x14 : irtx_pw */
+#define IRTX_PW_OFFSET               (0x14)
+#define IR_CR_IRTX_LOGIC0_PH0_W      IR_CR_IRTX_LOGIC0_PH0_W
+#define IR_CR_IRTX_LOGIC0_PH0_W_POS  (0U)
+#define IR_CR_IRTX_LOGIC0_PH0_W_LEN  (4U)
+#define IR_CR_IRTX_LOGIC0_PH0_W_MSK  (((1U << IR_CR_IRTX_LOGIC0_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH0_W_POS)
+#define IR_CR_IRTX_LOGIC0_PH0_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC0_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH0_W_POS))
+#define IR_CR_IRTX_LOGIC0_PH1_W      IR_CR_IRTX_LOGIC0_PH1_W
+#define IR_CR_IRTX_LOGIC0_PH1_W_POS  (4U)
+#define IR_CR_IRTX_LOGIC0_PH1_W_LEN  (4U)
+#define IR_CR_IRTX_LOGIC0_PH1_W_MSK  (((1U << IR_CR_IRTX_LOGIC0_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH1_W_POS)
+#define IR_CR_IRTX_LOGIC0_PH1_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC0_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH1_W_POS))
+#define IR_CR_IRTX_LOGIC1_PH0_W      IR_CR_IRTX_LOGIC1_PH0_W
+#define IR_CR_IRTX_LOGIC1_PH0_W_POS  (8U)
+#define IR_CR_IRTX_LOGIC1_PH0_W_LEN  (4U)
+#define IR_CR_IRTX_LOGIC1_PH0_W_MSK  (((1U << IR_CR_IRTX_LOGIC1_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH0_W_POS)
+#define IR_CR_IRTX_LOGIC1_PH0_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC1_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH0_W_POS))
+#define IR_CR_IRTX_LOGIC1_PH1_W      IR_CR_IRTX_LOGIC1_PH1_W
+#define IR_CR_IRTX_LOGIC1_PH1_W_POS  (12U)
+#define IR_CR_IRTX_LOGIC1_PH1_W_LEN  (4U)
+#define IR_CR_IRTX_LOGIC1_PH1_W_MSK  (((1U << IR_CR_IRTX_LOGIC1_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH1_W_POS)
+#define IR_CR_IRTX_LOGIC1_PH1_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC1_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH1_W_POS))
+#define IR_CR_IRTX_HEAD_PH0_W        IR_CR_IRTX_HEAD_PH0_W
+#define IR_CR_IRTX_HEAD_PH0_W_POS    (16U)
+#define IR_CR_IRTX_HEAD_PH0_W_LEN    (4U)
+#define IR_CR_IRTX_HEAD_PH0_W_MSK    (((1U << IR_CR_IRTX_HEAD_PH0_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH0_W_POS)
+#define IR_CR_IRTX_HEAD_PH0_W_UMSK   (~(((1U << IR_CR_IRTX_HEAD_PH0_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH0_W_POS))
+#define IR_CR_IRTX_HEAD_PH1_W        IR_CR_IRTX_HEAD_PH1_W
+#define IR_CR_IRTX_HEAD_PH1_W_POS    (20U)
+#define IR_CR_IRTX_HEAD_PH1_W_LEN    (4U)
+#define IR_CR_IRTX_HEAD_PH1_W_MSK    (((1U << IR_CR_IRTX_HEAD_PH1_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH1_W_POS)
+#define IR_CR_IRTX_HEAD_PH1_W_UMSK   (~(((1U << IR_CR_IRTX_HEAD_PH1_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH1_W_POS))
+#define IR_CR_IRTX_TAIL_PH0_W        IR_CR_IRTX_TAIL_PH0_W
+#define IR_CR_IRTX_TAIL_PH0_W_POS    (24U)
+#define IR_CR_IRTX_TAIL_PH0_W_LEN    (4U)
+#define IR_CR_IRTX_TAIL_PH0_W_MSK    (((1U << IR_CR_IRTX_TAIL_PH0_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH0_W_POS)
+#define IR_CR_IRTX_TAIL_PH0_W_UMSK   (~(((1U << IR_CR_IRTX_TAIL_PH0_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH0_W_POS))
+#define IR_CR_IRTX_TAIL_PH1_W        IR_CR_IRTX_TAIL_PH1_W
+#define IR_CR_IRTX_TAIL_PH1_W_POS    (28U)
+#define IR_CR_IRTX_TAIL_PH1_W_LEN    (4U)
+#define IR_CR_IRTX_TAIL_PH1_W_MSK    (((1U << IR_CR_IRTX_TAIL_PH1_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH1_W_POS)
+#define IR_CR_IRTX_TAIL_PH1_W_UMSK   (~(((1U << IR_CR_IRTX_TAIL_PH1_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH1_W_POS))
+
+/* 0x40 : irtx_swm_pw_0 */
+#define IRTX_SWM_PW_0_OFFSET     (0x40)
+#define IR_CR_IRTX_SWM_PW_0      IR_CR_IRTX_SWM_PW_0
+#define IR_CR_IRTX_SWM_PW_0_POS  (0U)
+#define IR_CR_IRTX_SWM_PW_0_LEN  (32U)
+#define IR_CR_IRTX_SWM_PW_0_MSK  (((1U << IR_CR_IRTX_SWM_PW_0_LEN) - 1) << IR_CR_IRTX_SWM_PW_0_POS)
+#define IR_CR_IRTX_SWM_PW_0_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_0_LEN) - 1) << IR_CR_IRTX_SWM_PW_0_POS))
+
+/* 0x44 : irtx_swm_pw_1 */
+#define IRTX_SWM_PW_1_OFFSET     (0x44)
+#define IR_CR_IRTX_SWM_PW_1      IR_CR_IRTX_SWM_PW_1
+#define IR_CR_IRTX_SWM_PW_1_POS  (0U)
+#define IR_CR_IRTX_SWM_PW_1_LEN  (32U)
+#define IR_CR_IRTX_SWM_PW_1_MSK  (((1U << IR_CR_IRTX_SWM_PW_1_LEN) - 1) << IR_CR_IRTX_SWM_PW_1_POS)
+#define IR_CR_IRTX_SWM_PW_1_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_1_LEN) - 1) << IR_CR_IRTX_SWM_PW_1_POS))
+
+/* 0x48 : irtx_swm_pw_2 */
+#define IRTX_SWM_PW_2_OFFSET     (0x48)
+#define IR_CR_IRTX_SWM_PW_2      IR_CR_IRTX_SWM_PW_2
+#define IR_CR_IRTX_SWM_PW_2_POS  (0U)
+#define IR_CR_IRTX_SWM_PW_2_LEN  (32U)
+#define IR_CR_IRTX_SWM_PW_2_MSK  (((1U << IR_CR_IRTX_SWM_PW_2_LEN) - 1) << IR_CR_IRTX_SWM_PW_2_POS)
+#define IR_CR_IRTX_SWM_PW_2_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_2_LEN) - 1) << IR_CR_IRTX_SWM_PW_2_POS))
+
+/* 0x4C : irtx_swm_pw_3 */
+#define IRTX_SWM_PW_3_OFFSET     (0x4C)
+#define IR_CR_IRTX_SWM_PW_3      IR_CR_IRTX_SWM_PW_3
+#define IR_CR_IRTX_SWM_PW_3_POS  (0U)
+#define IR_CR_IRTX_SWM_PW_3_LEN  (32U)
+#define IR_CR_IRTX_SWM_PW_3_MSK  (((1U << IR_CR_IRTX_SWM_PW_3_LEN) - 1) << IR_CR_IRTX_SWM_PW_3_POS)
+#define IR_CR_IRTX_SWM_PW_3_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_3_LEN) - 1) << IR_CR_IRTX_SWM_PW_3_POS))
+
+/* 0x50 : irtx_swm_pw_4 */
+#define IRTX_SWM_PW_4_OFFSET     (0x50)
+#define IR_CR_IRTX_SWM_PW_4      IR_CR_IRTX_SWM_PW_4
+#define IR_CR_IRTX_SWM_PW_4_POS  (0U)
+#define IR_CR_IRTX_SWM_PW_4_LEN  (32U)
+#define IR_CR_IRTX_SWM_PW_4_MSK  (((1U << IR_CR_IRTX_SWM_PW_4_LEN) - 1) << IR_CR_IRTX_SWM_PW_4_POS)
+#define IR_CR_IRTX_SWM_PW_4_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_4_LEN) - 1) << IR_CR_IRTX_SWM_PW_4_POS))
+
+/* 0x54 : irtx_swm_pw_5 */
+#define IRTX_SWM_PW_5_OFFSET     (0x54)
+#define IR_CR_IRTX_SWM_PW_5      IR_CR_IRTX_SWM_PW_5
+#define IR_CR_IRTX_SWM_PW_5_POS  (0U)
+#define IR_CR_IRTX_SWM_PW_5_LEN  (32U)
+#define IR_CR_IRTX_SWM_PW_5_MSK  (((1U << IR_CR_IRTX_SWM_PW_5_LEN) - 1) << IR_CR_IRTX_SWM_PW_5_POS)
+#define IR_CR_IRTX_SWM_PW_5_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_5_LEN) - 1) << IR_CR_IRTX_SWM_PW_5_POS))
+
+/* 0x58 : irtx_swm_pw_6 */
+#define IRTX_SWM_PW_6_OFFSET     (0x58)
+#define IR_CR_IRTX_SWM_PW_6      IR_CR_IRTX_SWM_PW_6
+#define IR_CR_IRTX_SWM_PW_6_POS  (0U)
+#define IR_CR_IRTX_SWM_PW_6_LEN  (32U)
+#define IR_CR_IRTX_SWM_PW_6_MSK  (((1U << IR_CR_IRTX_SWM_PW_6_LEN) - 1) << IR_CR_IRTX_SWM_PW_6_POS)
+#define IR_CR_IRTX_SWM_PW_6_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_6_LEN) - 1) << IR_CR_IRTX_SWM_PW_6_POS))
+
+/* 0x5C : irtx_swm_pw_7 */
+#define IRTX_SWM_PW_7_OFFSET     (0x5C)
+#define IR_CR_IRTX_SWM_PW_7      IR_CR_IRTX_SWM_PW_7
+#define IR_CR_IRTX_SWM_PW_7_POS  (0U)
+#define IR_CR_IRTX_SWM_PW_7_LEN  (32U)
+#define IR_CR_IRTX_SWM_PW_7_MSK  (((1U << IR_CR_IRTX_SWM_PW_7_LEN) - 1) << IR_CR_IRTX_SWM_PW_7_POS)
+#define IR_CR_IRTX_SWM_PW_7_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_7_LEN) - 1) << IR_CR_IRTX_SWM_PW_7_POS))
+
+/* 0x80 : irrx_config */
+#define IRRX_CONFIG_OFFSET      (0x80)
+#define IR_CR_IRRX_EN           IR_CR_IRRX_EN
+#define IR_CR_IRRX_EN_POS       (0U)
+#define IR_CR_IRRX_EN_LEN       (1U)
+#define IR_CR_IRRX_EN_MSK       (((1U << IR_CR_IRRX_EN_LEN) - 1) << IR_CR_IRRX_EN_POS)
+#define IR_CR_IRRX_EN_UMSK      (~(((1U << IR_CR_IRRX_EN_LEN) - 1) << IR_CR_IRRX_EN_POS))
+#define IR_CR_IRRX_IN_INV       IR_CR_IRRX_IN_INV
+#define IR_CR_IRRX_IN_INV_POS   (1U)
+#define IR_CR_IRRX_IN_INV_LEN   (1U)
+#define IR_CR_IRRX_IN_INV_MSK   (((1U << IR_CR_IRRX_IN_INV_LEN) - 1) << IR_CR_IRRX_IN_INV_POS)
+#define IR_CR_IRRX_IN_INV_UMSK  (~(((1U << IR_CR_IRRX_IN_INV_LEN) - 1) << IR_CR_IRRX_IN_INV_POS))
+#define IR_CR_IRRX_MODE         IR_CR_IRRX_MODE
+#define IR_CR_IRRX_MODE_POS     (2U)
+#define IR_CR_IRRX_MODE_LEN     (2U)
+#define IR_CR_IRRX_MODE_MSK     (((1U << IR_CR_IRRX_MODE_LEN) - 1) << IR_CR_IRRX_MODE_POS)
+#define IR_CR_IRRX_MODE_UMSK    (~(((1U << IR_CR_IRRX_MODE_LEN) - 1) << IR_CR_IRRX_MODE_POS))
+#define IR_CR_IRRX_DEG_EN       IR_CR_IRRX_DEG_EN
+#define IR_CR_IRRX_DEG_EN_POS   (4U)
+#define IR_CR_IRRX_DEG_EN_LEN   (1U)
+#define IR_CR_IRRX_DEG_EN_MSK   (((1U << IR_CR_IRRX_DEG_EN_LEN) - 1) << IR_CR_IRRX_DEG_EN_POS)
+#define IR_CR_IRRX_DEG_EN_UMSK  (~(((1U << IR_CR_IRRX_DEG_EN_LEN) - 1) << IR_CR_IRRX_DEG_EN_POS))
+#define IR_CR_IRRX_DEG_CNT      IR_CR_IRRX_DEG_CNT
+#define IR_CR_IRRX_DEG_CNT_POS  (8U)
+#define IR_CR_IRRX_DEG_CNT_LEN  (4U)
+#define IR_CR_IRRX_DEG_CNT_MSK  (((1U << IR_CR_IRRX_DEG_CNT_LEN) - 1) << IR_CR_IRRX_DEG_CNT_POS)
+#define IR_CR_IRRX_DEG_CNT_UMSK (~(((1U << IR_CR_IRRX_DEG_CNT_LEN) - 1) << IR_CR_IRRX_DEG_CNT_POS))
+
+/* 0x84 : irrx_int_sts */
+#define IRRX_INT_STS_OFFSET      (0x84)
+#define IRRX_END_INT             IRRX_END_INT
+#define IRRX_END_INT_POS         (0U)
+#define IRRX_END_INT_LEN         (1U)
+#define IRRX_END_INT_MSK         (((1U << IRRX_END_INT_LEN) - 1) << IRRX_END_INT_POS)
+#define IRRX_END_INT_UMSK        (~(((1U << IRRX_END_INT_LEN) - 1) << IRRX_END_INT_POS))
+#define IR_CR_IRRX_END_MASK      IR_CR_IRRX_END_MASK
+#define IR_CR_IRRX_END_MASK_POS  (8U)
+#define IR_CR_IRRX_END_MASK_LEN  (1U)
+#define IR_CR_IRRX_END_MASK_MSK  (((1U << IR_CR_IRRX_END_MASK_LEN) - 1) << IR_CR_IRRX_END_MASK_POS)
+#define IR_CR_IRRX_END_MASK_UMSK (~(((1U << IR_CR_IRRX_END_MASK_LEN) - 1) << IR_CR_IRRX_END_MASK_POS))
+#define IR_CR_IRRX_END_CLR       IR_CR_IRRX_END_CLR
+#define IR_CR_IRRX_END_CLR_POS   (16U)
+#define IR_CR_IRRX_END_CLR_LEN   (1U)
+#define IR_CR_IRRX_END_CLR_MSK   (((1U << IR_CR_IRRX_END_CLR_LEN) - 1) << IR_CR_IRRX_END_CLR_POS)
+#define IR_CR_IRRX_END_CLR_UMSK  (~(((1U << IR_CR_IRRX_END_CLR_LEN) - 1) << IR_CR_IRRX_END_CLR_POS))
+#define IR_CR_IRRX_END_EN        IR_CR_IRRX_END_EN
+#define IR_CR_IRRX_END_EN_POS    (24U)
+#define IR_CR_IRRX_END_EN_LEN    (1U)
+#define IR_CR_IRRX_END_EN_MSK    (((1U << IR_CR_IRRX_END_EN_LEN) - 1) << IR_CR_IRRX_END_EN_POS)
+#define IR_CR_IRRX_END_EN_UMSK   (~(((1U << IR_CR_IRRX_END_EN_LEN) - 1) << IR_CR_IRRX_END_EN_POS))
+
+/* 0x88 : irrx_pw_config */
+#define IRRX_PW_CONFIG_OFFSET   (0x88)
+#define IR_CR_IRRX_DATA_TH      IR_CR_IRRX_DATA_TH
+#define IR_CR_IRRX_DATA_TH_POS  (0U)
+#define IR_CR_IRRX_DATA_TH_LEN  (16U)
+#define IR_CR_IRRX_DATA_TH_MSK  (((1U << IR_CR_IRRX_DATA_TH_LEN) - 1) << IR_CR_IRRX_DATA_TH_POS)
+#define IR_CR_IRRX_DATA_TH_UMSK (~(((1U << IR_CR_IRRX_DATA_TH_LEN) - 1) << IR_CR_IRRX_DATA_TH_POS))
+#define IR_CR_IRRX_END_TH       IR_CR_IRRX_END_TH
+#define IR_CR_IRRX_END_TH_POS   (16U)
+#define IR_CR_IRRX_END_TH_LEN   (16U)
+#define IR_CR_IRRX_END_TH_MSK   (((1U << IR_CR_IRRX_END_TH_LEN) - 1) << IR_CR_IRRX_END_TH_POS)
+#define IR_CR_IRRX_END_TH_UMSK  (~(((1U << IR_CR_IRRX_END_TH_LEN) - 1) << IR_CR_IRRX_END_TH_POS))
+
+/* 0x90 : irrx_data_count */
+#define IRRX_DATA_COUNT_OFFSET    (0x90)
+#define IR_STS_IRRX_DATA_CNT      IR_STS_IRRX_DATA_CNT
+#define IR_STS_IRRX_DATA_CNT_POS  (0U)
+#define IR_STS_IRRX_DATA_CNT_LEN  (7U)
+#define IR_STS_IRRX_DATA_CNT_MSK  (((1U << IR_STS_IRRX_DATA_CNT_LEN) - 1) << IR_STS_IRRX_DATA_CNT_POS)
+#define IR_STS_IRRX_DATA_CNT_UMSK (~(((1U << IR_STS_IRRX_DATA_CNT_LEN) - 1) << IR_STS_IRRX_DATA_CNT_POS))
+
+/* 0x94 : irrx_data_word0 */
+#define IRRX_DATA_WORD0_OFFSET      (0x94)
+#define IR_STS_IRRX_DATA_WORD0      IR_STS_IRRX_DATA_WORD0
+#define IR_STS_IRRX_DATA_WORD0_POS  (0U)
+#define IR_STS_IRRX_DATA_WORD0_LEN  (32U)
+#define IR_STS_IRRX_DATA_WORD0_MSK  (((1U << IR_STS_IRRX_DATA_WORD0_LEN) - 1) << IR_STS_IRRX_DATA_WORD0_POS)
+#define IR_STS_IRRX_DATA_WORD0_UMSK (~(((1U << IR_STS_IRRX_DATA_WORD0_LEN) - 1) << IR_STS_IRRX_DATA_WORD0_POS))
+
+/* 0x98 : irrx_data_word1 */
+#define IRRX_DATA_WORD1_OFFSET      (0x98)
+#define IR_STS_IRRX_DATA_WORD1      IR_STS_IRRX_DATA_WORD1
+#define IR_STS_IRRX_DATA_WORD1_POS  (0U)
+#define IR_STS_IRRX_DATA_WORD1_LEN  (32U)
+#define IR_STS_IRRX_DATA_WORD1_MSK  (((1U << IR_STS_IRRX_DATA_WORD1_LEN) - 1) << IR_STS_IRRX_DATA_WORD1_POS)
+#define IR_STS_IRRX_DATA_WORD1_UMSK (~(((1U << IR_STS_IRRX_DATA_WORD1_LEN) - 1) << IR_STS_IRRX_DATA_WORD1_POS))
+
+/* 0xC0 : irrx_swm_fifo_config_0 */
+#define IRRX_SWM_FIFO_CONFIG_0_OFFSET (0xC0)
+#define IR_RX_FIFO_CLR                IR_RX_FIFO_CLR
+#define IR_RX_FIFO_CLR_POS            (0U)
+#define IR_RX_FIFO_CLR_LEN            (1U)
+#define IR_RX_FIFO_CLR_MSK            (((1U << IR_RX_FIFO_CLR_LEN) - 1) << IR_RX_FIFO_CLR_POS)
+#define IR_RX_FIFO_CLR_UMSK           (~(((1U << IR_RX_FIFO_CLR_LEN) - 1) << IR_RX_FIFO_CLR_POS))
+#define IR_RX_FIFO_OVERFLOW           IR_RX_FIFO_OVERFLOW
+#define IR_RX_FIFO_OVERFLOW_POS       (2U)
+#define IR_RX_FIFO_OVERFLOW_LEN       (1U)
+#define IR_RX_FIFO_OVERFLOW_MSK       (((1U << IR_RX_FIFO_OVERFLOW_LEN) - 1) << IR_RX_FIFO_OVERFLOW_POS)
+#define IR_RX_FIFO_OVERFLOW_UMSK      (~(((1U << IR_RX_FIFO_OVERFLOW_LEN) - 1) << IR_RX_FIFO_OVERFLOW_POS))
+#define IR_RX_FIFO_UNDERFLOW          IR_RX_FIFO_UNDERFLOW
+#define IR_RX_FIFO_UNDERFLOW_POS      (3U)
+#define IR_RX_FIFO_UNDERFLOW_LEN      (1U)
+#define IR_RX_FIFO_UNDERFLOW_MSK      (((1U << IR_RX_FIFO_UNDERFLOW_LEN) - 1) << IR_RX_FIFO_UNDERFLOW_POS)
+#define IR_RX_FIFO_UNDERFLOW_UMSK     (~(((1U << IR_RX_FIFO_UNDERFLOW_LEN) - 1) << IR_RX_FIFO_UNDERFLOW_POS))
+#define IR_RX_FIFO_CNT                IR_RX_FIFO_CNT
+#define IR_RX_FIFO_CNT_POS            (4U)
+#define IR_RX_FIFO_CNT_LEN            (7U)
+#define IR_RX_FIFO_CNT_MSK            (((1U << IR_RX_FIFO_CNT_LEN) - 1) << IR_RX_FIFO_CNT_POS)
+#define IR_RX_FIFO_CNT_UMSK           (~(((1U << IR_RX_FIFO_CNT_LEN) - 1) << IR_RX_FIFO_CNT_POS))
+
+/* 0xC4 : irrx_swm_fifo_rdata */
+#define IRRX_SWM_FIFO_RDATA_OFFSET (0xC4)
+#define IR_RX_FIFO_RDATA           IR_RX_FIFO_RDATA
+#define IR_RX_FIFO_RDATA_POS       (0U)
+#define IR_RX_FIFO_RDATA_LEN       (16U)
+#define IR_RX_FIFO_RDATA_MSK       (((1U << IR_RX_FIFO_RDATA_LEN) - 1) << IR_RX_FIFO_RDATA_POS)
+#define IR_RX_FIFO_RDATA_UMSK      (~(((1U << IR_RX_FIFO_RDATA_LEN) - 1) << IR_RX_FIFO_RDATA_POS))
+
+struct ir_reg {
+    /* 0x0 : irtx_config */
+    union {
+        struct
+        {
+            uint32_t cr_irtx_en            : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t cr_irtx_out_inv       : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t cr_irtx_mod_en        : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t cr_irtx_swm_en        : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t cr_irtx_data_en       : 1;  /* [    4],        r/w,        0x1 */
+            uint32_t cr_irtx_logic0_hl_inv : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t cr_irtx_logic1_hl_inv : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7            : 1;  /* [    7],       rsvd,        0x0 */
+            uint32_t cr_irtx_head_en       : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t cr_irtx_head_hl_inv   : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t cr_irtx_tail_en       : 1;  /* [   10],        r/w,        0x1 */
+            uint32_t cr_irtx_tail_hl_inv   : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t cr_irtx_data_num      : 6;  /* [17:12],        r/w,       0x1f */
+            uint32_t reserved_18_31        : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irtx_config;
+
+    /* 0x4 : irtx_int_sts */
+    union {
+        struct
+        {
+            uint32_t irtx_end_int     : 1; /* [    0],          r,        0x0 */
+            uint32_t reserved_1_7     : 7; /* [ 7: 1],       rsvd,        0x0 */
+            uint32_t cr_irtx_end_mask : 1; /* [    8],        r/w,        0x1 */
+            uint32_t reserved_9_15    : 7; /* [15: 9],       rsvd,        0x0 */
+            uint32_t cr_irtx_end_clr  : 1; /* [   16],        w1c,        0x0 */
+            uint32_t reserved_17_23   : 7; /* [23:17],       rsvd,        0x0 */
+            uint32_t cr_irtx_end_en   : 1; /* [   24],        r/w,        0x1 */
+            uint32_t reserved_25_31   : 7; /* [31:25],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irtx_int_sts;
+
+    /* 0x8 : irtx_data_word0 */
+    union {
+        struct
+        {
+            uint32_t cr_irtx_data_word0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irtx_data_word0;
+
+    /* 0xC : irtx_data_word1 */
+    union {
+        struct
+        {
+            uint32_t cr_irtx_data_word1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irtx_data_word1;
+
+    /* 0x10 : irtx_pulse_width */
+    union {
+        struct
+        {
+            uint32_t cr_irtx_pw_unit   : 12; /* [11: 0],        r/w,      0x464 */
+            uint32_t reserved_12_15    : 4;  /* [15:12],       rsvd,        0x0 */
+            uint32_t cr_irtx_mod_ph0_w : 8;  /* [23:16],        r/w,       0x11 */
+            uint32_t cr_irtx_mod_ph1_w : 8;  /* [31:24],        r/w,       0x22 */
+        } BF;
+        uint32_t WORD;
+    } irtx_pulse_width;
+
+    /* 0x14 : irtx_pw */
+    union {
+        struct
+        {
+            uint32_t cr_irtx_logic0_ph0_w : 4; /* [ 3: 0],        r/w,        0x0 */
+            uint32_t cr_irtx_logic0_ph1_w : 4; /* [ 7: 4],        r/w,        0x0 */
+            uint32_t cr_irtx_logic1_ph0_w : 4; /* [11: 8],        r/w,        0x0 */
+            uint32_t cr_irtx_logic1_ph1_w : 4; /* [15:12],        r/w,        0x2 */
+            uint32_t cr_irtx_head_ph0_w   : 4; /* [19:16],        r/w,        0xf */
+            uint32_t cr_irtx_head_ph1_w   : 4; /* [23:20],        r/w,        0x7 */
+            uint32_t cr_irtx_tail_ph0_w   : 4; /* [27:24],        r/w,        0x0 */
+            uint32_t cr_irtx_tail_ph1_w   : 4; /* [31:28],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irtx_pw;
+
+    /* 0x18  reserved */
+    uint8_t RESERVED0x18[40];
+
+    /* 0x40 : irtx_swm_pw_0 */
+    union {
+        struct
+        {
+            uint32_t cr_irtx_swm_pw_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irtx_swm_pw_0;
+
+    /* 0x44 : irtx_swm_pw_1 */
+    union {
+        struct
+        {
+            uint32_t cr_irtx_swm_pw_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irtx_swm_pw_1;
+
+    /* 0x48 : irtx_swm_pw_2 */
+    union {
+        struct
+        {
+            uint32_t cr_irtx_swm_pw_2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irtx_swm_pw_2;
+
+    /* 0x4C : irtx_swm_pw_3 */
+    union {
+        struct
+        {
+            uint32_t cr_irtx_swm_pw_3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irtx_swm_pw_3;
+
+    /* 0x50 : irtx_swm_pw_4 */
+    union {
+        struct
+        {
+            uint32_t cr_irtx_swm_pw_4 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irtx_swm_pw_4;
+
+    /* 0x54 : irtx_swm_pw_5 */
+    union {
+        struct
+        {
+            uint32_t cr_irtx_swm_pw_5 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irtx_swm_pw_5;
+
+    /* 0x58 : irtx_swm_pw_6 */
+    union {
+        struct
+        {
+            uint32_t cr_irtx_swm_pw_6 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irtx_swm_pw_6;
+
+    /* 0x5C : irtx_swm_pw_7 */
+    union {
+        struct
+        {
+            uint32_t cr_irtx_swm_pw_7 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irtx_swm_pw_7;
+
+    /* 0x60  reserved */
+    uint8_t RESERVED0x60[32];
+
+    /* 0x80 : irrx_config */
+    union {
+        struct
+        {
+            uint32_t cr_irrx_en      : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t cr_irrx_in_inv  : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t cr_irrx_mode    : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t cr_irrx_deg_en  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reserved_5_7    : 3;  /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t cr_irrx_deg_cnt : 4;  /* [11: 8],        r/w,        0x0 */
+            uint32_t reserved_12_31  : 20; /* [31:12],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irrx_config;
+
+    /* 0x84 : irrx_int_sts */
+    union {
+        struct
+        {
+            uint32_t irrx_end_int     : 1; /* [    0],          r,        0x0 */
+            uint32_t reserved_1_7     : 7; /* [ 7: 1],       rsvd,        0x0 */
+            uint32_t cr_irrx_end_mask : 1; /* [    8],        r/w,        0x1 */
+            uint32_t reserved_9_15    : 7; /* [15: 9],       rsvd,        0x0 */
+            uint32_t cr_irrx_end_clr  : 1; /* [   16],        w1c,        0x0 */
+            uint32_t reserved_17_23   : 7; /* [23:17],       rsvd,        0x0 */
+            uint32_t cr_irrx_end_en   : 1; /* [   24],        r/w,        0x1 */
+            uint32_t reserved_25_31   : 7; /* [31:25],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irrx_int_sts;
+
+    /* 0x88 : irrx_pw_config */
+    union {
+        struct
+        {
+            uint32_t cr_irrx_data_th : 16; /* [15: 0],        r/w,      0xd47 */
+            uint32_t cr_irrx_end_th  : 16; /* [31:16],        r/w,     0x2327 */
+        } BF;
+        uint32_t WORD;
+    } irrx_pw_config;
+
+    /* 0x8c  reserved */
+    uint8_t RESERVED0x8c[4];
+
+    /* 0x90 : irrx_data_count */
+    union {
+        struct
+        {
+            uint32_t sts_irrx_data_cnt : 7;  /* [ 6: 0],          r,        0x0 */
+            uint32_t reserved_7_31     : 25; /* [31: 7],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irrx_data_count;
+
+    /* 0x94 : irrx_data_word0 */
+    union {
+        struct
+        {
+            uint32_t sts_irrx_data_word0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irrx_data_word0;
+
+    /* 0x98 : irrx_data_word1 */
+    union {
+        struct
+        {
+            uint32_t sts_irrx_data_word1 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irrx_data_word1;
+
+    /* 0x9c  reserved */
+    uint8_t RESERVED0x9c[36];
+
+    /* 0xC0 : irrx_swm_fifo_config_0 */
+    union {
+        struct
+        {
+            uint32_t rx_fifo_clr       : 1;  /* [    0],        w1c,        0x0 */
+            uint32_t reserved_1        : 1;  /* [    1],       rsvd,        0x0 */
+            uint32_t rx_fifo_overflow  : 1;  /* [    2],          r,        0x0 */
+            uint32_t rx_fifo_underflow : 1;  /* [    3],          r,        0x0 */
+            uint32_t rx_fifo_cnt       : 7;  /* [10: 4],          r,        0x0 */
+            uint32_t reserved_11_31    : 21; /* [31:11],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irrx_swm_fifo_config_0;
+
+    /* 0xC4 : irrx_swm_fifo_rdata */
+    union {
+        struct
+        {
+            uint32_t rx_fifo_rdata  : 16; /* [15: 0],          r,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irrx_swm_fifo_rdata;
+};
+
+typedef volatile struct ir_reg ir_reg_t;
+
+#endif /* __IR_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/kys_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/kys_reg.h
new file mode 100644
index 00000000..b2a9890a
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/kys_reg.h
@@ -0,0 +1,194 @@
+/**
+  ******************************************************************************
+  * @file    kys_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __KYS_REG_H__
+#define __KYS_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : ks_ctrl */
+#define KYS_KS_CTRL_OFFSET (0x0)
+#define KYS_KS_EN          KYS_KS_EN
+#define KYS_KS_EN_POS      (0U)
+#define KYS_KS_EN_LEN      (1U)
+#define KYS_KS_EN_MSK      (((1U << KYS_KS_EN_LEN) - 1) << KYS_KS_EN_POS)
+#define KYS_KS_EN_UMSK     (~(((1U << KYS_KS_EN_LEN) - 1) << KYS_KS_EN_POS))
+#define KYS_GHOST_EN       KYS_GHOST_EN
+#define KYS_GHOST_EN_POS   (2U)
+#define KYS_GHOST_EN_LEN   (1U)
+#define KYS_GHOST_EN_MSK   (((1U << KYS_GHOST_EN_LEN) - 1) << KYS_GHOST_EN_POS)
+#define KYS_GHOST_EN_UMSK  (~(((1U << KYS_GHOST_EN_LEN) - 1) << KYS_GHOST_EN_POS))
+#define KYS_DEG_EN         KYS_DEG_EN
+#define KYS_DEG_EN_POS     (3U)
+#define KYS_DEG_EN_LEN     (1U)
+#define KYS_DEG_EN_MSK     (((1U << KYS_DEG_EN_LEN) - 1) << KYS_DEG_EN_POS)
+#define KYS_DEG_EN_UMSK    (~(((1U << KYS_DEG_EN_LEN) - 1) << KYS_DEG_EN_POS))
+#define KYS_DEG_CNT        KYS_DEG_CNT
+#define KYS_DEG_CNT_POS    (4U)
+#define KYS_DEG_CNT_LEN    (4U)
+#define KYS_DEG_CNT_MSK    (((1U << KYS_DEG_CNT_LEN) - 1) << KYS_DEG_CNT_POS)
+#define KYS_DEG_CNT_UMSK   (~(((1U << KYS_DEG_CNT_LEN) - 1) << KYS_DEG_CNT_POS))
+#define KYS_RC_EXT         KYS_RC_EXT
+#define KYS_RC_EXT_POS     (8U)
+#define KYS_RC_EXT_LEN     (2U)
+#define KYS_RC_EXT_MSK     (((1U << KYS_RC_EXT_LEN) - 1) << KYS_RC_EXT_POS)
+#define KYS_RC_EXT_UMSK    (~(((1U << KYS_RC_EXT_LEN) - 1) << KYS_RC_EXT_POS))
+#define KYS_ROW_NUM        KYS_ROW_NUM
+#define KYS_ROW_NUM_POS    (16U)
+#define KYS_ROW_NUM_LEN    (3U)
+#define KYS_ROW_NUM_MSK    (((1U << KYS_ROW_NUM_LEN) - 1) << KYS_ROW_NUM_POS)
+#define KYS_ROW_NUM_UMSK   (~(((1U << KYS_ROW_NUM_LEN) - 1) << KYS_ROW_NUM_POS))
+#define KYS_COL_NUM        KYS_COL_NUM
+#define KYS_COL_NUM_POS    (20U)
+#define KYS_COL_NUM_LEN    (5U)
+#define KYS_COL_NUM_MSK    (((1U << KYS_COL_NUM_LEN) - 1) << KYS_COL_NUM_POS)
+#define KYS_COL_NUM_UMSK   (~(((1U << KYS_COL_NUM_LEN) - 1) << KYS_COL_NUM_POS))
+
+/* 0x10 : ks_int_en */
+#define KYS_KS_INT_EN_OFFSET (0x10)
+#define KYS_KS_INT_EN        KYS_KS_INT_EN
+#define KYS_KS_INT_EN_POS    (0U)
+#define KYS_KS_INT_EN_LEN    (1U)
+#define KYS_KS_INT_EN_MSK    (((1U << KYS_KS_INT_EN_LEN) - 1) << KYS_KS_INT_EN_POS)
+#define KYS_KS_INT_EN_UMSK   (~(((1U << KYS_KS_INT_EN_LEN) - 1) << KYS_KS_INT_EN_POS))
+
+/* 0x14 : ks_int_sts */
+#define KYS_KS_INT_STS_OFFSET  (0x14)
+#define KYS_KEYCODE_VALID      KYS_KEYCODE_VALID
+#define KYS_KEYCODE_VALID_POS  (0U)
+#define KYS_KEYCODE_VALID_LEN  (4U)
+#define KYS_KEYCODE_VALID_MSK  (((1U << KYS_KEYCODE_VALID_LEN) - 1) << KYS_KEYCODE_VALID_POS)
+#define KYS_KEYCODE_VALID_UMSK (~(((1U << KYS_KEYCODE_VALID_LEN) - 1) << KYS_KEYCODE_VALID_POS))
+
+/* 0x18 : keycode_clr */
+#define KYS_KEYCODE_CLR_OFFSET (0x18)
+#define KYS_KEYCODE_CLR        KYS_KEYCODE_CLR
+#define KYS_KEYCODE_CLR_POS    (0U)
+#define KYS_KEYCODE_CLR_LEN    (4U)
+#define KYS_KEYCODE_CLR_MSK    (((1U << KYS_KEYCODE_CLR_LEN) - 1) << KYS_KEYCODE_CLR_POS)
+#define KYS_KEYCODE_CLR_UMSK   (~(((1U << KYS_KEYCODE_CLR_LEN) - 1) << KYS_KEYCODE_CLR_POS))
+
+/* 0x1C : keycode_value */
+#define KYS_KEYCODE_VALUE_OFFSET (0x1C)
+#define KYS_KEYCODE0             KYS_KEYCODE0
+#define KYS_KEYCODE0_POS         (0U)
+#define KYS_KEYCODE0_LEN         (8U)
+#define KYS_KEYCODE0_MSK         (((1U << KYS_KEYCODE0_LEN) - 1) << KYS_KEYCODE0_POS)
+#define KYS_KEYCODE0_UMSK        (~(((1U << KYS_KEYCODE0_LEN) - 1) << KYS_KEYCODE0_POS))
+#define KYS_KEYCODE1             KYS_KEYCODE1
+#define KYS_KEYCODE1_POS         (8U)
+#define KYS_KEYCODE1_LEN         (8U)
+#define KYS_KEYCODE1_MSK         (((1U << KYS_KEYCODE1_LEN) - 1) << KYS_KEYCODE1_POS)
+#define KYS_KEYCODE1_UMSK        (~(((1U << KYS_KEYCODE1_LEN) - 1) << KYS_KEYCODE1_POS))
+#define KYS_KEYCODE2             KYS_KEYCODE2
+#define KYS_KEYCODE2_POS         (16U)
+#define KYS_KEYCODE2_LEN         (8U)
+#define KYS_KEYCODE2_MSK         (((1U << KYS_KEYCODE2_LEN) - 1) << KYS_KEYCODE2_POS)
+#define KYS_KEYCODE2_UMSK        (~(((1U << KYS_KEYCODE2_LEN) - 1) << KYS_KEYCODE2_POS))
+#define KYS_KEYCODE3             KYS_KEYCODE3
+#define KYS_KEYCODE3_POS         (24U)
+#define KYS_KEYCODE3_LEN         (8U)
+#define KYS_KEYCODE3_MSK         (((1U << KYS_KEYCODE3_LEN) - 1) << KYS_KEYCODE3_POS)
+#define KYS_KEYCODE3_UMSK        (~(((1U << KYS_KEYCODE3_LEN) - 1) << KYS_KEYCODE3_POS))
+
+struct kys_reg {
+    /* 0x0 : ks_ctrl */
+    union {
+        struct
+        {
+            uint32_t ks_en          : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1     : 1; /* [    1],       rsvd,        0x0 */
+            uint32_t ghost_en       : 1; /* [    2],        r/w,        0x0 */
+            uint32_t deg_en         : 1; /* [    3],        r/w,        0x0 */
+            uint32_t deg_cnt        : 4; /* [ 7: 4],        r/w,        0x0 */
+            uint32_t rc_ext         : 2; /* [ 9: 8],        r/w,        0x3 */
+            uint32_t reserved_10_15 : 6; /* [15:10],       rsvd,        0x0 */
+            uint32_t row_num        : 3; /* [18:16],        r/w,        0x7 */
+            uint32_t reserved_19    : 1; /* [   19],       rsvd,        0x0 */
+            uint32_t col_num        : 5; /* [24:20],        r/w,       0x13 */
+            uint32_t reserved_25_31 : 7; /* [31:25],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ks_ctrl;
+
+    /* 0x4  reserved */
+    uint8_t RESERVED0x4[12];
+
+    /* 0x10 : ks_int_en */
+    union {
+        struct
+        {
+            uint32_t ks_int_en     : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reserved_1_31 : 31; /* [31: 1],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ks_int_en;
+
+    /* 0x14 : ks_int_sts */
+    union {
+        struct
+        {
+            uint32_t keycode_valid : 4;  /* [ 3: 0],          r,        0x0 */
+            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ks_int_sts;
+
+    /* 0x18 : keycode_clr */
+    union {
+        struct
+        {
+            uint32_t keycode_clr   : 4;  /* [ 3: 0],        w1c,        0x0 */
+            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } keycode_clr;
+
+    /* 0x1C : keycode_value */
+    union {
+        struct
+        {
+            uint32_t keycode0 : 8; /* [ 7: 0],          r,       0xff */
+            uint32_t keycode1 : 8; /* [15: 8],          r,       0xff */
+            uint32_t keycode2 : 8; /* [23:16],          r,       0xff */
+            uint32_t keycode3 : 8; /* [31:24],          r,       0xff */
+        } BF;
+        uint32_t WORD;
+    } keycode_value;
+};
+
+typedef volatile struct kys_reg kys_reg_t;
+
+#endif /* __KYS_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/l1c_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/l1c_reg.h
new file mode 100644
index 00000000..f9ae45ed
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/l1c_reg.h
@@ -0,0 +1,366 @@
+/**
+  ******************************************************************************
+  * @file    l1c_reg.h
+  * @version V1.2
+  * @date    2020-07-08
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __L1C_REG_H__
+#define __L1C_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : l1c_config */
+#define L1C_CONFIG_OFFSET            (0x0)
+#define L1C_CACHEABLE                L1C_CACHEABLE
+#define L1C_CACHEABLE_POS            (0U)
+#define L1C_CACHEABLE_LEN            (1U)
+#define L1C_CACHEABLE_MSK            (((1U << L1C_CACHEABLE_LEN) - 1) << L1C_CACHEABLE_POS)
+#define L1C_CACHEABLE_UMSK           (~(((1U << L1C_CACHEABLE_LEN) - 1) << L1C_CACHEABLE_POS))
+#define L1C_CNT_EN                   L1C_CNT_EN
+#define L1C_CNT_EN_POS               (1U)
+#define L1C_CNT_EN_LEN               (1U)
+#define L1C_CNT_EN_MSK               (((1U << L1C_CNT_EN_LEN) - 1) << L1C_CNT_EN_POS)
+#define L1C_CNT_EN_UMSK              (~(((1U << L1C_CNT_EN_LEN) - 1) << L1C_CNT_EN_POS))
+#define L1C_INVALID_EN               L1C_INVALID_EN
+#define L1C_INVALID_EN_POS           (2U)
+#define L1C_INVALID_EN_LEN           (1U)
+#define L1C_INVALID_EN_MSK           (((1U << L1C_INVALID_EN_LEN) - 1) << L1C_INVALID_EN_POS)
+#define L1C_INVALID_EN_UMSK          (~(((1U << L1C_INVALID_EN_LEN) - 1) << L1C_INVALID_EN_POS))
+#define L1C_INVALID_DONE             L1C_INVALID_DONE
+#define L1C_INVALID_DONE_POS         (3U)
+#define L1C_INVALID_DONE_LEN         (1U)
+#define L1C_INVALID_DONE_MSK         (((1U << L1C_INVALID_DONE_LEN) - 1) << L1C_INVALID_DONE_POS)
+#define L1C_INVALID_DONE_UMSK        (~(((1U << L1C_INVALID_DONE_LEN) - 1) << L1C_INVALID_DONE_POS))
+#define L1C_WT_EN                    L1C_WT_EN
+#define L1C_WT_EN_POS                (4U)
+#define L1C_WT_EN_LEN                (1U)
+#define L1C_WT_EN_MSK                (((1U << L1C_WT_EN_LEN) - 1) << L1C_WT_EN_POS)
+#define L1C_WT_EN_UMSK               (~(((1U << L1C_WT_EN_LEN) - 1) << L1C_WT_EN_POS))
+#define L1C_WB_EN                    L1C_WB_EN
+#define L1C_WB_EN_POS                (5U)
+#define L1C_WB_EN_LEN                (1U)
+#define L1C_WB_EN_MSK                (((1U << L1C_WB_EN_LEN) - 1) << L1C_WB_EN_POS)
+#define L1C_WB_EN_UMSK               (~(((1U << L1C_WB_EN_LEN) - 1) << L1C_WB_EN_POS))
+#define L1C_WA_EN                    L1C_WA_EN
+#define L1C_WA_EN_POS                (6U)
+#define L1C_WA_EN_LEN                (1U)
+#define L1C_WA_EN_MSK                (((1U << L1C_WA_EN_LEN) - 1) << L1C_WA_EN_POS)
+#define L1C_WA_EN_UMSK               (~(((1U << L1C_WA_EN_LEN) - 1) << L1C_WA_EN_POS))
+#define L1C_RANDOM_REPLACE           L1C_RANDOM_REPLACE
+#define L1C_RANDOM_REPLACE_POS       (7U)
+#define L1C_RANDOM_REPLACE_LEN       (1U)
+#define L1C_RANDOM_REPLACE_MSK       (((1U << L1C_RANDOM_REPLACE_LEN) - 1) << L1C_RANDOM_REPLACE_POS)
+#define L1C_RANDOM_REPLACE_UMSK      (~(((1U << L1C_RANDOM_REPLACE_LEN) - 1) << L1C_RANDOM_REPLACE_POS))
+#define L1C_WAY_DIS                  L1C_WAY_DIS
+#define L1C_WAY_DIS_POS              (8U)
+#define L1C_WAY_DIS_LEN              (4U)
+#define L1C_WAY_DIS_MSK              (((1U << L1C_WAY_DIS_LEN) - 1) << L1C_WAY_DIS_POS)
+#define L1C_WAY_DIS_UMSK             (~(((1U << L1C_WAY_DIS_LEN) - 1) << L1C_WAY_DIS_POS))
+#define L1C_IROM_2T_ACCESS           L1C_IROM_2T_ACCESS
+#define L1C_IROM_2T_ACCESS_POS       (12U)
+#define L1C_IROM_2T_ACCESS_LEN       (1U)
+#define L1C_IROM_2T_ACCESS_MSK       (((1U << L1C_IROM_2T_ACCESS_LEN) - 1) << L1C_IROM_2T_ACCESS_POS)
+#define L1C_IROM_2T_ACCESS_UMSK      (~(((1U << L1C_IROM_2T_ACCESS_LEN) - 1) << L1C_IROM_2T_ACCESS_POS))
+#define L1C_BYPASS                   L1C_BYPASS
+#define L1C_BYPASS_POS               (14U)
+#define L1C_BYPASS_LEN               (1U)
+#define L1C_BYPASS_MSK               (((1U << L1C_BYPASS_LEN) - 1) << L1C_BYPASS_POS)
+#define L1C_BYPASS_UMSK              (~(((1U << L1C_BYPASS_LEN) - 1) << L1C_BYPASS_POS))
+#define L1C_BMX_ERR_EN               L1C_BMX_ERR_EN
+#define L1C_BMX_ERR_EN_POS           (15U)
+#define L1C_BMX_ERR_EN_LEN           (1U)
+#define L1C_BMX_ERR_EN_MSK           (((1U << L1C_BMX_ERR_EN_LEN) - 1) << L1C_BMX_ERR_EN_POS)
+#define L1C_BMX_ERR_EN_UMSK          (~(((1U << L1C_BMX_ERR_EN_LEN) - 1) << L1C_BMX_ERR_EN_POS))
+#define L1C_BMX_ARB_MODE             L1C_BMX_ARB_MODE
+#define L1C_BMX_ARB_MODE_POS         (16U)
+#define L1C_BMX_ARB_MODE_LEN         (2U)
+#define L1C_BMX_ARB_MODE_MSK         (((1U << L1C_BMX_ARB_MODE_LEN) - 1) << L1C_BMX_ARB_MODE_POS)
+#define L1C_BMX_ARB_MODE_UMSK        (~(((1U << L1C_BMX_ARB_MODE_LEN) - 1) << L1C_BMX_ARB_MODE_POS))
+#define L1C_BMX_TIMEOUT_EN           L1C_BMX_TIMEOUT_EN
+#define L1C_BMX_TIMEOUT_EN_POS       (20U)
+#define L1C_BMX_TIMEOUT_EN_LEN       (4U)
+#define L1C_BMX_TIMEOUT_EN_MSK       (((1U << L1C_BMX_TIMEOUT_EN_LEN) - 1) << L1C_BMX_TIMEOUT_EN_POS)
+#define L1C_BMX_TIMEOUT_EN_UMSK      (~(((1U << L1C_BMX_TIMEOUT_EN_LEN) - 1) << L1C_BMX_TIMEOUT_EN_POS))
+#define L1C_BMX_BUSY_OPTION_DIS      L1C_BMX_BUSY_OPTION_DIS
+#define L1C_BMX_BUSY_OPTION_DIS_POS  (24U)
+#define L1C_BMX_BUSY_OPTION_DIS_LEN  (1U)
+#define L1C_BMX_BUSY_OPTION_DIS_MSK  (((1U << L1C_BMX_BUSY_OPTION_DIS_LEN) - 1) << L1C_BMX_BUSY_OPTION_DIS_POS)
+#define L1C_BMX_BUSY_OPTION_DIS_UMSK (~(((1U << L1C_BMX_BUSY_OPTION_DIS_LEN) - 1) << L1C_BMX_BUSY_OPTION_DIS_POS))
+#define L1C_EARLY_RESP_DIS           L1C_EARLY_RESP_DIS
+#define L1C_EARLY_RESP_DIS_POS       (25U)
+#define L1C_EARLY_RESP_DIS_LEN       (1U)
+#define L1C_EARLY_RESP_DIS_MSK       (((1U << L1C_EARLY_RESP_DIS_LEN) - 1) << L1C_EARLY_RESP_DIS_POS)
+#define L1C_EARLY_RESP_DIS_UMSK      (~(((1U << L1C_EARLY_RESP_DIS_LEN) - 1) << L1C_EARLY_RESP_DIS_POS))
+#define L1C_WRAP_DIS                 L1C_WRAP_DIS
+#define L1C_WRAP_DIS_POS             (26U)
+#define L1C_WRAP_DIS_LEN             (1U)
+#define L1C_WRAP_DIS_MSK             (((1U << L1C_WRAP_DIS_LEN) - 1) << L1C_WRAP_DIS_POS)
+#define L1C_WRAP_DIS_UMSK            (~(((1U << L1C_WRAP_DIS_LEN) - 1) << L1C_WRAP_DIS_POS))
+#define L1C_FLUSH_EN                 L1C_FLUSH_EN
+#define L1C_FLUSH_EN_POS             (28U)
+#define L1C_FLUSH_EN_LEN             (1U)
+#define L1C_FLUSH_EN_MSK             (((1U << L1C_FLUSH_EN_LEN) - 1) << L1C_FLUSH_EN_POS)
+#define L1C_FLUSH_EN_UMSK            (~(((1U << L1C_FLUSH_EN_LEN) - 1) << L1C_FLUSH_EN_POS))
+#define L1C_FLUSH_DONE               L1C_FLUSH_DONE
+#define L1C_FLUSH_DONE_POS           (29U)
+#define L1C_FLUSH_DONE_LEN           (1U)
+#define L1C_FLUSH_DONE_MSK           (((1U << L1C_FLUSH_DONE_LEN) - 1) << L1C_FLUSH_DONE_POS)
+#define L1C_FLUSH_DONE_UMSK          (~(((1U << L1C_FLUSH_DONE_LEN) - 1) << L1C_FLUSH_DONE_POS))
+
+/* 0x4 : hit_cnt_lsb */
+#define L1C_HIT_CNT_LSB_OFFSET (0x4)
+#define L1C_HIT_CNT_LSB        L1C_HIT_CNT_LSB
+#define L1C_HIT_CNT_LSB_POS    (0U)
+#define L1C_HIT_CNT_LSB_LEN    (32U)
+#define L1C_HIT_CNT_LSB_MSK    (((1U << L1C_HIT_CNT_LSB_LEN) - 1) << L1C_HIT_CNT_LSB_POS)
+#define L1C_HIT_CNT_LSB_UMSK   (~(((1U << L1C_HIT_CNT_LSB_LEN) - 1) << L1C_HIT_CNT_LSB_POS))
+
+/* 0x8 : hit_cnt_msb */
+#define L1C_HIT_CNT_MSB_OFFSET (0x8)
+#define L1C_HIT_CNT_MSB        L1C_HIT_CNT_MSB
+#define L1C_HIT_CNT_MSB_POS    (0U)
+#define L1C_HIT_CNT_MSB_LEN    (32U)
+#define L1C_HIT_CNT_MSB_MSK    (((1U << L1C_HIT_CNT_MSB_LEN) - 1) << L1C_HIT_CNT_MSB_POS)
+#define L1C_HIT_CNT_MSB_UMSK   (~(((1U << L1C_HIT_CNT_MSB_LEN) - 1) << L1C_HIT_CNT_MSB_POS))
+
+/* 0xC : miss_cnt */
+#define L1C_MISS_CNT_OFFSET (0xC)
+#define L1C_MISS_CNT        L1C_MISS_CNT
+#define L1C_MISS_CNT_POS    (0U)
+#define L1C_MISS_CNT_LEN    (32U)
+#define L1C_MISS_CNT_MSK    (((1U << L1C_MISS_CNT_LEN) - 1) << L1C_MISS_CNT_POS)
+#define L1C_MISS_CNT_UMSK   (~(((1U << L1C_MISS_CNT_LEN) - 1) << L1C_MISS_CNT_POS))
+
+/* 0x10 : l1c_misc */
+#define L1C_MISC_OFFSET (0x10)
+#define L1C_FSM         L1C_FSM
+#define L1C_FSM_POS     (28U)
+#define L1C_FSM_LEN     (3U)
+#define L1C_FSM_MSK     (((1U << L1C_FSM_LEN) - 1) << L1C_FSM_POS)
+#define L1C_FSM_UMSK    (~(((1U << L1C_FSM_LEN) - 1) << L1C_FSM_POS))
+
+/* 0x200 : l1c_bmx_err_addr_en */
+#define L1C_BMX_ERR_ADDR_EN_OFFSET (0x200)
+#define L1C_BMX_ERR_ADDR_DIS       L1C_BMX_ERR_ADDR_DIS
+#define L1C_BMX_ERR_ADDR_DIS_POS   (0U)
+#define L1C_BMX_ERR_ADDR_DIS_LEN   (1U)
+#define L1C_BMX_ERR_ADDR_DIS_MSK   (((1U << L1C_BMX_ERR_ADDR_DIS_LEN) - 1) << L1C_BMX_ERR_ADDR_DIS_POS)
+#define L1C_BMX_ERR_ADDR_DIS_UMSK  (~(((1U << L1C_BMX_ERR_ADDR_DIS_LEN) - 1) << L1C_BMX_ERR_ADDR_DIS_POS))
+#define L1C_BMX_ERR_DEC            L1C_BMX_ERR_DEC
+#define L1C_BMX_ERR_DEC_POS        (4U)
+#define L1C_BMX_ERR_DEC_LEN        (1U)
+#define L1C_BMX_ERR_DEC_MSK        (((1U << L1C_BMX_ERR_DEC_LEN) - 1) << L1C_BMX_ERR_DEC_POS)
+#define L1C_BMX_ERR_DEC_UMSK       (~(((1U << L1C_BMX_ERR_DEC_LEN) - 1) << L1C_BMX_ERR_DEC_POS))
+#define L1C_BMX_ERR_TZ             L1C_BMX_ERR_TZ
+#define L1C_BMX_ERR_TZ_POS         (5U)
+#define L1C_BMX_ERR_TZ_LEN         (1U)
+#define L1C_BMX_ERR_TZ_MSK         (((1U << L1C_BMX_ERR_TZ_LEN) - 1) << L1C_BMX_ERR_TZ_POS)
+#define L1C_BMX_ERR_TZ_UMSK        (~(((1U << L1C_BMX_ERR_TZ_LEN) - 1) << L1C_BMX_ERR_TZ_POS))
+#define L1C_HSEL_OPTION            L1C_HSEL_OPTION
+#define L1C_HSEL_OPTION_POS        (16U)
+#define L1C_HSEL_OPTION_LEN        (4U)
+#define L1C_HSEL_OPTION_MSK        (((1U << L1C_HSEL_OPTION_LEN) - 1) << L1C_HSEL_OPTION_POS)
+#define L1C_HSEL_OPTION_UMSK       (~(((1U << L1C_HSEL_OPTION_LEN) - 1) << L1C_HSEL_OPTION_POS))
+
+/* 0x204 : l1c_bmx_err_addr */
+#define L1C_BMX_ERR_ADDR_OFFSET (0x204)
+#define L1C_BMX_ERR_ADDR        L1C_BMX_ERR_ADDR
+#define L1C_BMX_ERR_ADDR_POS    (0U)
+#define L1C_BMX_ERR_ADDR_LEN    (32U)
+#define L1C_BMX_ERR_ADDR_MSK    (((1U << L1C_BMX_ERR_ADDR_LEN) - 1) << L1C_BMX_ERR_ADDR_POS)
+#define L1C_BMX_ERR_ADDR_UMSK   (~(((1U << L1C_BMX_ERR_ADDR_LEN) - 1) << L1C_BMX_ERR_ADDR_POS))
+
+/* 0x208 : irom1_misr_dataout_0 */
+#define L1C_IROM1_MISR_DATAOUT_0_OFFSET (0x208)
+#define L1C_IROM1_MISR_DATAOUT_0        L1C_IROM1_MISR_DATAOUT_0
+#define L1C_IROM1_MISR_DATAOUT_0_POS    (0U)
+#define L1C_IROM1_MISR_DATAOUT_0_LEN    (32U)
+#define L1C_IROM1_MISR_DATAOUT_0_MSK    (((1U << L1C_IROM1_MISR_DATAOUT_0_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_0_POS)
+#define L1C_IROM1_MISR_DATAOUT_0_UMSK   (~(((1U << L1C_IROM1_MISR_DATAOUT_0_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_0_POS))
+
+/* 0x20C : irom1_misr_dataout_1 */
+#define L1C_IROM1_MISR_DATAOUT_1_OFFSET (0x20C)
+#define L1C_IROM1_MISR_DATAOUT_1        L1C_IROM1_MISR_DATAOUT_1
+#define L1C_IROM1_MISR_DATAOUT_1_POS    (0U)
+#define L1C_IROM1_MISR_DATAOUT_1_LEN    (32U)
+#define L1C_IROM1_MISR_DATAOUT_1_MSK    (((1U << L1C_IROM1_MISR_DATAOUT_1_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_1_POS)
+#define L1C_IROM1_MISR_DATAOUT_1_UMSK   (~(((1U << L1C_IROM1_MISR_DATAOUT_1_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_1_POS))
+
+/* 0x210 : cpu_clk_gate */
+#define L1C_CPU_CLK_GATE_OFFSET       (0x210)
+#define L1C_FORCE_E21_CLOCK_ON_0      L1C_FORCE_E21_CLOCK_ON_0
+#define L1C_FORCE_E21_CLOCK_ON_0_POS  (0U)
+#define L1C_FORCE_E21_CLOCK_ON_0_LEN  (1U)
+#define L1C_FORCE_E21_CLOCK_ON_0_MSK  (((1U << L1C_FORCE_E21_CLOCK_ON_0_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_0_POS)
+#define L1C_FORCE_E21_CLOCK_ON_0_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_0_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_0_POS))
+#define L1C_FORCE_E21_CLOCK_ON_1      L1C_FORCE_E21_CLOCK_ON_1
+#define L1C_FORCE_E21_CLOCK_ON_1_POS  (1U)
+#define L1C_FORCE_E21_CLOCK_ON_1_LEN  (1U)
+#define L1C_FORCE_E21_CLOCK_ON_1_MSK  (((1U << L1C_FORCE_E21_CLOCK_ON_1_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_1_POS)
+#define L1C_FORCE_E21_CLOCK_ON_1_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_1_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_1_POS))
+#define L1C_FORCE_E21_CLOCK_ON_2      L1C_FORCE_E21_CLOCK_ON_2
+#define L1C_FORCE_E21_CLOCK_ON_2_POS  (2U)
+#define L1C_FORCE_E21_CLOCK_ON_2_LEN  (1U)
+#define L1C_FORCE_E21_CLOCK_ON_2_MSK  (((1U << L1C_FORCE_E21_CLOCK_ON_2_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_2_POS)
+#define L1C_FORCE_E21_CLOCK_ON_2_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_2_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_2_POS))
+
+struct l1c_reg {
+    /* 0x0 : l1c_config */
+    union {
+        struct
+        {
+            uint32_t l1c_cacheable           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t l1c_cnt_en              : 1; /* [    1],        r/w,        0x0 */
+            uint32_t l1c_invalid_en          : 1; /* [    2],        r/w,        0x0 */
+            uint32_t l1c_invalid_done        : 1; /* [    3],          r,        0x0 */
+            uint32_t l1c_wt_en               : 1; /* [    4],        r/w,        0x0 */
+            uint32_t l1c_wb_en               : 1; /* [    5],        r/w,        0x1 */
+            uint32_t l1c_wa_en               : 1; /* [    6],        r/w,        0x1 */
+            uint32_t l1c_random_replace      : 1; /* [    7],        r/w,        0x0 */
+            uint32_t l1c_way_dis             : 4; /* [11: 8],        r/w,        0xf */
+            uint32_t irom_2t_access          : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13             : 1; /* [   13],       rsvd,        0x0 */
+            uint32_t l1c_bypass              : 1; /* [   14],        r/w,        0x0 */
+            uint32_t l1c_bmx_err_en          : 1; /* [   15],        r/w,        0x0 */
+            uint32_t l1c_bmx_arb_mode        : 2; /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_19          : 2; /* [19:18],       rsvd,        0x0 */
+            uint32_t l1c_bmx_timeout_en      : 4; /* [23:20],        r/w,        0x0 */
+            uint32_t l1c_bmx_busy_option_dis : 1; /* [   24],        r/w,        0x0 */
+            uint32_t early_resp_dis          : 1; /* [   25],        r/w,        0x1 */
+            uint32_t wrap_dis                : 1; /* [   26],        r/w,        0x1 */
+            uint32_t reserved_27             : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t l1c_flush_en            : 1; /* [   28],        r/w,        0x0 */
+            uint32_t l1c_flush_done          : 1; /* [   29],          r,        0x0 */
+            uint32_t reserved_31_30          : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } l1c_config;
+
+    /* 0x4 : hit_cnt_lsb */
+    union {
+        struct
+        {
+            uint32_t hit_cnt_lsb : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } hit_cnt_lsb;
+
+    /* 0x8 : hit_cnt_msb */
+    union {
+        struct
+        {
+            uint32_t hit_cnt_msb : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } hit_cnt_msb;
+
+    /* 0xC : miss_cnt */
+    union {
+        struct
+        {
+            uint32_t miss_cnt : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } miss_cnt;
+
+    /* 0x10 : l1c_misc */
+    union {
+        struct
+        {
+            uint32_t reserved_0_27 : 28; /* [27: 0],       rsvd,        0x0 */
+            uint32_t l1c_fsm       : 3;  /* [30:28],          r,        0x0 */
+            uint32_t reserved_31   : 1;  /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } l1c_misc;
+
+    /* 0x14  reserved */
+    uint8_t RESERVED0x14[492];
+
+    /* 0x200 : l1c_bmx_err_addr_en */
+    union {
+        struct
+        {
+            uint32_t l1c_bmx_err_addr_dis : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3         : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t l1c_bmx_err_dec      : 1;  /* [    4],          r,        0x0 */
+            uint32_t l1c_bmx_err_tz       : 1;  /* [    5],          r,        0x0 */
+            uint32_t reserved_6_15        : 10; /* [15: 6],       rsvd,        0x0 */
+            uint32_t l1c_hsel_option      : 4;  /* [19:16],        r/w,        0x0 */
+            uint32_t reserved_20_31       : 12; /* [31:20],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } l1c_bmx_err_addr_en;
+
+    /* 0x204 : l1c_bmx_err_addr */
+    union {
+        struct
+        {
+            uint32_t l1c_bmx_err_addr : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } l1c_bmx_err_addr;
+
+    /* 0x208 : irom1_misr_dataout_0 */
+    union {
+        struct
+        {
+            uint32_t irom1_misr_dataout_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irom1_misr_dataout_0;
+
+    /* 0x20C : irom1_misr_dataout_1 */
+    union {
+        struct
+        {
+            uint32_t irom1_misr_dataout_1 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irom1_misr_dataout_1;
+
+    /* 0x210 : cpu_clk_gate */
+    union {
+        struct
+        {
+            uint32_t force_e21_clock_on_0 : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t force_e21_clock_on_1 : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t force_e21_clock_on_2 : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3_31        : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cpu_clk_gate;
+};
+
+typedef volatile struct l1c_reg l1c_reg_t;
+
+#endif /* __L1C_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/mjpeg_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/mjpeg_reg.h
new file mode 100644
index 00000000..078deba0
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/mjpeg_reg.h
@@ -0,0 +1,1726 @@
+/**
+  ******************************************************************************
+  * @file    mjpeg_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __MJPEG_REG_H__
+#define __MJPEG_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : mjpeg_control_1 */
+#define MJPEG_CONTROL_1_OFFSET          (0x0)
+#define MJPEG_REG_MJPEG_ENABLE          MJPEG_REG_MJPEG_ENABLE
+#define MJPEG_REG_MJPEG_ENABLE_POS      (0U)
+#define MJPEG_REG_MJPEG_ENABLE_LEN      (1U)
+#define MJPEG_REG_MJPEG_ENABLE_MSK      (((1U << MJPEG_REG_MJPEG_ENABLE_LEN) - 1) << MJPEG_REG_MJPEG_ENABLE_POS)
+#define MJPEG_REG_MJPEG_ENABLE_UMSK     (~(((1U << MJPEG_REG_MJPEG_ENABLE_LEN) - 1) << MJPEG_REG_MJPEG_ENABLE_POS))
+#define MJPEG_REG_MJPEG_BIT_ORDER       MJPEG_REG_MJPEG_BIT_ORDER
+#define MJPEG_REG_MJPEG_BIT_ORDER_POS   (1U)
+#define MJPEG_REG_MJPEG_BIT_ORDER_LEN   (1U)
+#define MJPEG_REG_MJPEG_BIT_ORDER_MSK   (((1U << MJPEG_REG_MJPEG_BIT_ORDER_LEN) - 1) << MJPEG_REG_MJPEG_BIT_ORDER_POS)
+#define MJPEG_REG_MJPEG_BIT_ORDER_UMSK  (~(((1U << MJPEG_REG_MJPEG_BIT_ORDER_LEN) - 1) << MJPEG_REG_MJPEG_BIT_ORDER_POS))
+#define MJPEG_REG_ORDER_U_EVEN          MJPEG_REG_ORDER_U_EVEN
+#define MJPEG_REG_ORDER_U_EVEN_POS      (2U)
+#define MJPEG_REG_ORDER_U_EVEN_LEN      (1U)
+#define MJPEG_REG_ORDER_U_EVEN_MSK      (((1U << MJPEG_REG_ORDER_U_EVEN_LEN) - 1) << MJPEG_REG_ORDER_U_EVEN_POS)
+#define MJPEG_REG_ORDER_U_EVEN_UMSK     (~(((1U << MJPEG_REG_ORDER_U_EVEN_LEN) - 1) << MJPEG_REG_ORDER_U_EVEN_POS))
+#define MJPEG_REG_WR_OVER_STOP          MJPEG_REG_WR_OVER_STOP
+#define MJPEG_REG_WR_OVER_STOP_POS      (3U)
+#define MJPEG_REG_WR_OVER_STOP_LEN      (1U)
+#define MJPEG_REG_WR_OVER_STOP_MSK      (((1U << MJPEG_REG_WR_OVER_STOP_LEN) - 1) << MJPEG_REG_WR_OVER_STOP_POS)
+#define MJPEG_REG_WR_OVER_STOP_UMSK     (~(((1U << MJPEG_REG_WR_OVER_STOP_LEN) - 1) << MJPEG_REG_WR_OVER_STOP_POS))
+#define MJPEG_REG_LAST_HF_WBLK_DMY      MJPEG_REG_LAST_HF_WBLK_DMY
+#define MJPEG_REG_LAST_HF_WBLK_DMY_POS  (4U)
+#define MJPEG_REG_LAST_HF_WBLK_DMY_LEN  (1U)
+#define MJPEG_REG_LAST_HF_WBLK_DMY_MSK  (((1U << MJPEG_REG_LAST_HF_WBLK_DMY_LEN) - 1) << MJPEG_REG_LAST_HF_WBLK_DMY_POS)
+#define MJPEG_REG_LAST_HF_WBLK_DMY_UMSK (~(((1U << MJPEG_REG_LAST_HF_WBLK_DMY_LEN) - 1) << MJPEG_REG_LAST_HF_WBLK_DMY_POS))
+#define MJPEG_REG_LAST_HF_HBLK_DMY      MJPEG_REG_LAST_HF_HBLK_DMY
+#define MJPEG_REG_LAST_HF_HBLK_DMY_POS  (5U)
+#define MJPEG_REG_LAST_HF_HBLK_DMY_LEN  (1U)
+#define MJPEG_REG_LAST_HF_HBLK_DMY_MSK  (((1U << MJPEG_REG_LAST_HF_HBLK_DMY_LEN) - 1) << MJPEG_REG_LAST_HF_HBLK_DMY_POS)
+#define MJPEG_REG_LAST_HF_HBLK_DMY_UMSK (~(((1U << MJPEG_REG_LAST_HF_HBLK_DMY_LEN) - 1) << MJPEG_REG_LAST_HF_HBLK_DMY_POS))
+#define MJPEG_REG_REFLECT_DMY           MJPEG_REG_REFLECT_DMY
+#define MJPEG_REG_REFLECT_DMY_POS       (6U)
+#define MJPEG_REG_REFLECT_DMY_LEN       (1U)
+#define MJPEG_REG_REFLECT_DMY_MSK       (((1U << MJPEG_REG_REFLECT_DMY_LEN) - 1) << MJPEG_REG_REFLECT_DMY_POS)
+#define MJPEG_REG_REFLECT_DMY_UMSK      (~(((1U << MJPEG_REG_REFLECT_DMY_LEN) - 1) << MJPEG_REG_REFLECT_DMY_POS))
+#define MJPEG_REG_H_BUST                MJPEG_REG_H_BUST
+#define MJPEG_REG_H_BUST_POS            (8U)
+#define MJPEG_REG_H_BUST_LEN            (2U)
+#define MJPEG_REG_H_BUST_MSK            (((1U << MJPEG_REG_H_BUST_LEN) - 1) << MJPEG_REG_H_BUST_POS)
+#define MJPEG_REG_H_BUST_UMSK           (~(((1U << MJPEG_REG_H_BUST_LEN) - 1) << MJPEG_REG_H_BUST_POS))
+#define MJPEG_REG_YUV_MODE              MJPEG_REG_YUV_MODE
+#define MJPEG_REG_YUV_MODE_POS          (12U)
+#define MJPEG_REG_YUV_MODE_LEN          (2U)
+#define MJPEG_REG_YUV_MODE_MSK          (((1U << MJPEG_REG_YUV_MODE_LEN) - 1) << MJPEG_REG_YUV_MODE_POS)
+#define MJPEG_REG_YUV_MODE_UMSK         (~(((1U << MJPEG_REG_YUV_MODE_LEN) - 1) << MJPEG_REG_YUV_MODE_POS))
+#define MJPEG_REG_Q_MODE                MJPEG_REG_Q_MODE
+#define MJPEG_REG_Q_MODE_POS            (16U)
+#define MJPEG_REG_Q_MODE_LEN            (7U)
+#define MJPEG_REG_Q_MODE_MSK            (((1U << MJPEG_REG_Q_MODE_LEN) - 1) << MJPEG_REG_Q_MODE_POS)
+#define MJPEG_REG_Q_MODE_UMSK           (~(((1U << MJPEG_REG_Q_MODE_LEN) - 1) << MJPEG_REG_Q_MODE_POS))
+#define MJPEG_REG_Y0_ORDER              MJPEG_REG_Y0_ORDER
+#define MJPEG_REG_Y0_ORDER_POS          (24U)
+#define MJPEG_REG_Y0_ORDER_LEN          (2U)
+#define MJPEG_REG_Y0_ORDER_MSK          (((1U << MJPEG_REG_Y0_ORDER_LEN) - 1) << MJPEG_REG_Y0_ORDER_POS)
+#define MJPEG_REG_Y0_ORDER_UMSK         (~(((1U << MJPEG_REG_Y0_ORDER_LEN) - 1) << MJPEG_REG_Y0_ORDER_POS))
+#define MJPEG_REG_U0_ORDER              MJPEG_REG_U0_ORDER
+#define MJPEG_REG_U0_ORDER_POS          (26U)
+#define MJPEG_REG_U0_ORDER_LEN          (2U)
+#define MJPEG_REG_U0_ORDER_MSK          (((1U << MJPEG_REG_U0_ORDER_LEN) - 1) << MJPEG_REG_U0_ORDER_POS)
+#define MJPEG_REG_U0_ORDER_UMSK         (~(((1U << MJPEG_REG_U0_ORDER_LEN) - 1) << MJPEG_REG_U0_ORDER_POS))
+#define MJPEG_REG_Y1_ORDER              MJPEG_REG_Y1_ORDER
+#define MJPEG_REG_Y1_ORDER_POS          (28U)
+#define MJPEG_REG_Y1_ORDER_LEN          (2U)
+#define MJPEG_REG_Y1_ORDER_MSK          (((1U << MJPEG_REG_Y1_ORDER_LEN) - 1) << MJPEG_REG_Y1_ORDER_POS)
+#define MJPEG_REG_Y1_ORDER_UMSK         (~(((1U << MJPEG_REG_Y1_ORDER_LEN) - 1) << MJPEG_REG_Y1_ORDER_POS))
+#define MJPEG_REG_V0_ORDER              MJPEG_REG_V0_ORDER
+#define MJPEG_REG_V0_ORDER_POS          (30U)
+#define MJPEG_REG_V0_ORDER_LEN          (2U)
+#define MJPEG_REG_V0_ORDER_MSK          (((1U << MJPEG_REG_V0_ORDER_LEN) - 1) << MJPEG_REG_V0_ORDER_POS)
+#define MJPEG_REG_V0_ORDER_UMSK         (~(((1U << MJPEG_REG_V0_ORDER_LEN) - 1) << MJPEG_REG_V0_ORDER_POS))
+
+/* 0x4 : mjpeg_control_2 */
+#define MJPEG_CONTROL_2_OFFSET          (0x4)
+#define MJPEG_REG_SW_FRAME              MJPEG_REG_SW_FRAME
+#define MJPEG_REG_SW_FRAME_POS          (0U)
+#define MJPEG_REG_SW_FRAME_LEN          (5U)
+#define MJPEG_REG_SW_FRAME_MSK          (((1U << MJPEG_REG_SW_FRAME_LEN) - 1) << MJPEG_REG_SW_FRAME_POS)
+#define MJPEG_REG_SW_FRAME_UMSK         (~(((1U << MJPEG_REG_SW_FRAME_LEN) - 1) << MJPEG_REG_SW_FRAME_POS))
+#define MJPEG_REG_MJPEG_SW_MODE         MJPEG_REG_MJPEG_SW_MODE
+#define MJPEG_REG_MJPEG_SW_MODE_POS     (8U)
+#define MJPEG_REG_MJPEG_SW_MODE_LEN     (1U)
+#define MJPEG_REG_MJPEG_SW_MODE_MSK     (((1U << MJPEG_REG_MJPEG_SW_MODE_LEN) - 1) << MJPEG_REG_MJPEG_SW_MODE_POS)
+#define MJPEG_REG_MJPEG_SW_MODE_UMSK    (~(((1U << MJPEG_REG_MJPEG_SW_MODE_LEN) - 1) << MJPEG_REG_MJPEG_SW_MODE_POS))
+#define MJPEG_REG_MJPEG_SW_RUN          MJPEG_REG_MJPEG_SW_RUN
+#define MJPEG_REG_MJPEG_SW_RUN_POS      (9U)
+#define MJPEG_REG_MJPEG_SW_RUN_LEN      (1U)
+#define MJPEG_REG_MJPEG_SW_RUN_MSK      (((1U << MJPEG_REG_MJPEG_SW_RUN_LEN) - 1) << MJPEG_REG_MJPEG_SW_RUN_POS)
+#define MJPEG_REG_MJPEG_SW_RUN_UMSK     (~(((1U << MJPEG_REG_MJPEG_SW_RUN_LEN) - 1) << MJPEG_REG_MJPEG_SW_RUN_POS))
+#define MJPEG_REG_YY_DVP2AHB_LSEL       MJPEG_REG_YY_DVP2AHB_LSEL
+#define MJPEG_REG_YY_DVP2AHB_LSEL_POS   (12U)
+#define MJPEG_REG_YY_DVP2AHB_LSEL_LEN   (1U)
+#define MJPEG_REG_YY_DVP2AHB_LSEL_MSK   (((1U << MJPEG_REG_YY_DVP2AHB_LSEL_LEN) - 1) << MJPEG_REG_YY_DVP2AHB_LSEL_POS)
+#define MJPEG_REG_YY_DVP2AHB_LSEL_UMSK  (~(((1U << MJPEG_REG_YY_DVP2AHB_LSEL_LEN) - 1) << MJPEG_REG_YY_DVP2AHB_LSEL_POS))
+#define MJPEG_REG_YY_DVP2AHB_FSEL       MJPEG_REG_YY_DVP2AHB_FSEL
+#define MJPEG_REG_YY_DVP2AHB_FSEL_POS   (13U)
+#define MJPEG_REG_YY_DVP2AHB_FSEL_LEN   (1U)
+#define MJPEG_REG_YY_DVP2AHB_FSEL_MSK   (((1U << MJPEG_REG_YY_DVP2AHB_FSEL_LEN) - 1) << MJPEG_REG_YY_DVP2AHB_FSEL_POS)
+#define MJPEG_REG_YY_DVP2AHB_FSEL_UMSK  (~(((1U << MJPEG_REG_YY_DVP2AHB_FSEL_LEN) - 1) << MJPEG_REG_YY_DVP2AHB_FSEL_POS))
+#define MJPEG_REG_UV_DVP2AHB_LSEL       MJPEG_REG_UV_DVP2AHB_LSEL
+#define MJPEG_REG_UV_DVP2AHB_LSEL_POS   (14U)
+#define MJPEG_REG_UV_DVP2AHB_LSEL_LEN   (1U)
+#define MJPEG_REG_UV_DVP2AHB_LSEL_MSK   (((1U << MJPEG_REG_UV_DVP2AHB_LSEL_LEN) - 1) << MJPEG_REG_UV_DVP2AHB_LSEL_POS)
+#define MJPEG_REG_UV_DVP2AHB_LSEL_UMSK  (~(((1U << MJPEG_REG_UV_DVP2AHB_LSEL_LEN) - 1) << MJPEG_REG_UV_DVP2AHB_LSEL_POS))
+#define MJPEG_REG_UV_DVP2AHB_FSEL       MJPEG_REG_UV_DVP2AHB_FSEL
+#define MJPEG_REG_UV_DVP2AHB_FSEL_POS   (15U)
+#define MJPEG_REG_UV_DVP2AHB_FSEL_LEN   (1U)
+#define MJPEG_REG_UV_DVP2AHB_FSEL_MSK   (((1U << MJPEG_REG_UV_DVP2AHB_FSEL_LEN) - 1) << MJPEG_REG_UV_DVP2AHB_FSEL_POS)
+#define MJPEG_REG_UV_DVP2AHB_FSEL_UMSK  (~(((1U << MJPEG_REG_UV_DVP2AHB_FSEL_LEN) - 1) << MJPEG_REG_UV_DVP2AHB_FSEL_POS))
+#define MJPEG_REG_MJPEG_WAIT_CYCLE      MJPEG_REG_MJPEG_WAIT_CYCLE
+#define MJPEG_REG_MJPEG_WAIT_CYCLE_POS  (16U)
+#define MJPEG_REG_MJPEG_WAIT_CYCLE_LEN  (16U)
+#define MJPEG_REG_MJPEG_WAIT_CYCLE_MSK  (((1U << MJPEG_REG_MJPEG_WAIT_CYCLE_LEN) - 1) << MJPEG_REG_MJPEG_WAIT_CYCLE_POS)
+#define MJPEG_REG_MJPEG_WAIT_CYCLE_UMSK (~(((1U << MJPEG_REG_MJPEG_WAIT_CYCLE_LEN) - 1) << MJPEG_REG_MJPEG_WAIT_CYCLE_POS))
+
+/* 0x08 : mjpeg_yy_frame_addr */
+#define MJPEG_YY_FRAME_ADDR_OFFSET   (0x08)
+#define MJPEG_REG_YY_ADDR_START      MJPEG_REG_YY_ADDR_START
+#define MJPEG_REG_YY_ADDR_START_POS  (0U)
+#define MJPEG_REG_YY_ADDR_START_LEN  (32U)
+#define MJPEG_REG_YY_ADDR_START_MSK  (((1U << MJPEG_REG_YY_ADDR_START_LEN) - 1) << MJPEG_REG_YY_ADDR_START_POS)
+#define MJPEG_REG_YY_ADDR_START_UMSK (~(((1U << MJPEG_REG_YY_ADDR_START_LEN) - 1) << MJPEG_REG_YY_ADDR_START_POS))
+
+/* 0x0C : mjpeg_uv_frame_addr */
+#define MJPEG_UV_FRAME_ADDR_OFFSET   (0x0C)
+#define MJPEG_REG_UV_ADDR_START      MJPEG_REG_UV_ADDR_START
+#define MJPEG_REG_UV_ADDR_START_POS  (0U)
+#define MJPEG_REG_UV_ADDR_START_LEN  (32U)
+#define MJPEG_REG_UV_ADDR_START_MSK  (((1U << MJPEG_REG_UV_ADDR_START_LEN) - 1) << MJPEG_REG_UV_ADDR_START_POS)
+#define MJPEG_REG_UV_ADDR_START_UMSK (~(((1U << MJPEG_REG_UV_ADDR_START_LEN) - 1) << MJPEG_REG_UV_ADDR_START_POS))
+
+/* 0x10 : mjpeg_yuv_mem */
+#define MJPEG_YUV_MEM_OFFSET       (0x10)
+#define MJPEG_REG_YY_MEM_HBLK      MJPEG_REG_YY_MEM_HBLK
+#define MJPEG_REG_YY_MEM_HBLK_POS  (0U)
+#define MJPEG_REG_YY_MEM_HBLK_LEN  (13U)
+#define MJPEG_REG_YY_MEM_HBLK_MSK  (((1U << MJPEG_REG_YY_MEM_HBLK_LEN) - 1) << MJPEG_REG_YY_MEM_HBLK_POS)
+#define MJPEG_REG_YY_MEM_HBLK_UMSK (~(((1U << MJPEG_REG_YY_MEM_HBLK_LEN) - 1) << MJPEG_REG_YY_MEM_HBLK_POS))
+#define MJPEG_REG_UV_MEM_HBLK      MJPEG_REG_UV_MEM_HBLK
+#define MJPEG_REG_UV_MEM_HBLK_POS  (16U)
+#define MJPEG_REG_UV_MEM_HBLK_LEN  (13U)
+#define MJPEG_REG_UV_MEM_HBLK_MSK  (((1U << MJPEG_REG_UV_MEM_HBLK_LEN) - 1) << MJPEG_REG_UV_MEM_HBLK_POS)
+#define MJPEG_REG_UV_MEM_HBLK_UMSK (~(((1U << MJPEG_REG_UV_MEM_HBLK_LEN) - 1) << MJPEG_REG_UV_MEM_HBLK_POS))
+
+/* 0x14 : jpeg_frame_addr */
+#define MJPEG_JPEG_FRAME_ADDR_OFFSET (0x14)
+#define MJPEG_REG_W_ADDR_START       MJPEG_REG_W_ADDR_START
+#define MJPEG_REG_W_ADDR_START_POS   (0U)
+#define MJPEG_REG_W_ADDR_START_LEN   (32U)
+#define MJPEG_REG_W_ADDR_START_MSK   (((1U << MJPEG_REG_W_ADDR_START_LEN) - 1) << MJPEG_REG_W_ADDR_START_POS)
+#define MJPEG_REG_W_ADDR_START_UMSK  (~(((1U << MJPEG_REG_W_ADDR_START_LEN) - 1) << MJPEG_REG_W_ADDR_START_POS))
+
+/* 0x18 : jpeg_store_memory */
+#define MJPEG_JPEG_STORE_MEMORY_OFFSET (0x18)
+#define MJPEG_REG_W_BURST_CNT          MJPEG_REG_W_BURST_CNT
+#define MJPEG_REG_W_BURST_CNT_POS      (0U)
+#define MJPEG_REG_W_BURST_CNT_LEN      (32U)
+#define MJPEG_REG_W_BURST_CNT_MSK      (((1U << MJPEG_REG_W_BURST_CNT_LEN) - 1) << MJPEG_REG_W_BURST_CNT_POS)
+#define MJPEG_REG_W_BURST_CNT_UMSK     (~(((1U << MJPEG_REG_W_BURST_CNT_LEN) - 1) << MJPEG_REG_W_BURST_CNT_POS))
+
+/* 0x1C : mjpeg_control_3 */
+#define MJPEG_CONTROL_3_OFFSET            (0x1C)
+#define MJPEG_REG_INT_NORMAL_EN           MJPEG_REG_INT_NORMAL_EN
+#define MJPEG_REG_INT_NORMAL_EN_POS       (0U)
+#define MJPEG_REG_INT_NORMAL_EN_LEN       (1U)
+#define MJPEG_REG_INT_NORMAL_EN_MSK       (((1U << MJPEG_REG_INT_NORMAL_EN_LEN) - 1) << MJPEG_REG_INT_NORMAL_EN_POS)
+#define MJPEG_REG_INT_NORMAL_EN_UMSK      (~(((1U << MJPEG_REG_INT_NORMAL_EN_LEN) - 1) << MJPEG_REG_INT_NORMAL_EN_POS))
+#define MJPEG_REG_INT_CAM_EN              MJPEG_REG_INT_CAM_EN
+#define MJPEG_REG_INT_CAM_EN_POS          (1U)
+#define MJPEG_REG_INT_CAM_EN_LEN          (1U)
+#define MJPEG_REG_INT_CAM_EN_MSK          (((1U << MJPEG_REG_INT_CAM_EN_LEN) - 1) << MJPEG_REG_INT_CAM_EN_POS)
+#define MJPEG_REG_INT_CAM_EN_UMSK         (~(((1U << MJPEG_REG_INT_CAM_EN_LEN) - 1) << MJPEG_REG_INT_CAM_EN_POS))
+#define MJPEG_REG_INT_MEM_EN              MJPEG_REG_INT_MEM_EN
+#define MJPEG_REG_INT_MEM_EN_POS          (2U)
+#define MJPEG_REG_INT_MEM_EN_LEN          (1U)
+#define MJPEG_REG_INT_MEM_EN_MSK          (((1U << MJPEG_REG_INT_MEM_EN_LEN) - 1) << MJPEG_REG_INT_MEM_EN_POS)
+#define MJPEG_REG_INT_MEM_EN_UMSK         (~(((1U << MJPEG_REG_INT_MEM_EN_LEN) - 1) << MJPEG_REG_INT_MEM_EN_POS))
+#define MJPEG_REG_INT_FRAME_EN            MJPEG_REG_INT_FRAME_EN
+#define MJPEG_REG_INT_FRAME_EN_POS        (3U)
+#define MJPEG_REG_INT_FRAME_EN_LEN        (1U)
+#define MJPEG_REG_INT_FRAME_EN_MSK        (((1U << MJPEG_REG_INT_FRAME_EN_LEN) - 1) << MJPEG_REG_INT_FRAME_EN_POS)
+#define MJPEG_REG_INT_FRAME_EN_UMSK       (~(((1U << MJPEG_REG_INT_FRAME_EN_LEN) - 1) << MJPEG_REG_INT_FRAME_EN_POS))
+#define MJPEG_STS_NORMAL_INT              MJPEG_STS_NORMAL_INT
+#define MJPEG_STS_NORMAL_INT_POS          (4U)
+#define MJPEG_STS_NORMAL_INT_LEN          (1U)
+#define MJPEG_STS_NORMAL_INT_MSK          (((1U << MJPEG_STS_NORMAL_INT_LEN) - 1) << MJPEG_STS_NORMAL_INT_POS)
+#define MJPEG_STS_NORMAL_INT_UMSK         (~(((1U << MJPEG_STS_NORMAL_INT_LEN) - 1) << MJPEG_STS_NORMAL_INT_POS))
+#define MJPEG_STS_CAM_INT                 MJPEG_STS_CAM_INT
+#define MJPEG_STS_CAM_INT_POS             (5U)
+#define MJPEG_STS_CAM_INT_LEN             (1U)
+#define MJPEG_STS_CAM_INT_MSK             (((1U << MJPEG_STS_CAM_INT_LEN) - 1) << MJPEG_STS_CAM_INT_POS)
+#define MJPEG_STS_CAM_INT_UMSK            (~(((1U << MJPEG_STS_CAM_INT_LEN) - 1) << MJPEG_STS_CAM_INT_POS))
+#define MJPEG_STS_MEM_INT                 MJPEG_STS_MEM_INT
+#define MJPEG_STS_MEM_INT_POS             (6U)
+#define MJPEG_STS_MEM_INT_LEN             (1U)
+#define MJPEG_STS_MEM_INT_MSK             (((1U << MJPEG_STS_MEM_INT_LEN) - 1) << MJPEG_STS_MEM_INT_POS)
+#define MJPEG_STS_MEM_INT_UMSK            (~(((1U << MJPEG_STS_MEM_INT_LEN) - 1) << MJPEG_STS_MEM_INT_POS))
+#define MJPEG_STS_FRAME_INT               MJPEG_STS_FRAME_INT
+#define MJPEG_STS_FRAME_INT_POS           (7U)
+#define MJPEG_STS_FRAME_INT_LEN           (1U)
+#define MJPEG_STS_FRAME_INT_MSK           (((1U << MJPEG_STS_FRAME_INT_LEN) - 1) << MJPEG_STS_FRAME_INT_POS)
+#define MJPEG_STS_FRAME_INT_UMSK          (~(((1U << MJPEG_STS_FRAME_INT_LEN) - 1) << MJPEG_STS_FRAME_INT_POS))
+#define MJPEG_IDLE                        MJPEG_IDLE
+#define MJPEG_IDLE_POS                    (8U)
+#define MJPEG_IDLE_LEN                    (1U)
+#define MJPEG_IDLE_MSK                    (((1U << MJPEG_IDLE_LEN) - 1) << MJPEG_IDLE_POS)
+#define MJPEG_IDLE_UMSK                   (~(((1U << MJPEG_IDLE_LEN) - 1) << MJPEG_IDLE_POS))
+#define MJPEG_FUNC                        MJPEG_FUNC
+#define MJPEG_FUNC_POS                    (9U)
+#define MJPEG_FUNC_LEN                    (1U)
+#define MJPEG_FUNC_MSK                    (((1U << MJPEG_FUNC_LEN) - 1) << MJPEG_FUNC_POS)
+#define MJPEG_FUNC_UMSK                   (~(((1U << MJPEG_FUNC_LEN) - 1) << MJPEG_FUNC_POS))
+#define MJPEG_WAIT                        MJPEG_WAIT
+#define MJPEG_WAIT_POS                    (10U)
+#define MJPEG_WAIT_LEN                    (1U)
+#define MJPEG_WAIT_MSK                    (((1U << MJPEG_WAIT_LEN) - 1) << MJPEG_WAIT_POS)
+#define MJPEG_WAIT_UMSK                   (~(((1U << MJPEG_WAIT_LEN) - 1) << MJPEG_WAIT_POS))
+#define MJPEG_FLSH                        MJPEG_FLSH
+#define MJPEG_FLSH_POS                    (11U)
+#define MJPEG_FLSH_LEN                    (1U)
+#define MJPEG_FLSH_MSK                    (((1U << MJPEG_FLSH_LEN) - 1) << MJPEG_FLSH_POS)
+#define MJPEG_FLSH_UMSK                   (~(((1U << MJPEG_FLSH_LEN) - 1) << MJPEG_FLSH_POS))
+#define MJPEG_MANS                        MJPEG_MANS
+#define MJPEG_MANS_POS                    (12U)
+#define MJPEG_MANS_LEN                    (1U)
+#define MJPEG_MANS_MSK                    (((1U << MJPEG_MANS_LEN) - 1) << MJPEG_MANS_POS)
+#define MJPEG_MANS_UMSK                   (~(((1U << MJPEG_MANS_LEN) - 1) << MJPEG_MANS_POS))
+#define MJPEG_MANF                        MJPEG_MANF
+#define MJPEG_MANF_POS                    (13U)
+#define MJPEG_MANF_LEN                    (1U)
+#define MJPEG_MANF_MSK                    (((1U << MJPEG_MANF_LEN) - 1) << MJPEG_MANF_POS)
+#define MJPEG_MANF_UMSK                   (~(((1U << MJPEG_MANF_LEN) - 1) << MJPEG_MANF_POS))
+#define MJPEG_AHB_IDLE                    MJPEG_AHB_IDLE
+#define MJPEG_AHB_IDLE_POS                (14U)
+#define MJPEG_AHB_IDLE_LEN                (1U)
+#define MJPEG_AHB_IDLE_MSK                (((1U << MJPEG_AHB_IDLE_LEN) - 1) << MJPEG_AHB_IDLE_POS)
+#define MJPEG_AHB_IDLE_UMSK               (~(((1U << MJPEG_AHB_IDLE_LEN) - 1) << MJPEG_AHB_IDLE_POS))
+#define MJPEG_REG_FRAME_CNT_TRGR_INT      MJPEG_REG_FRAME_CNT_TRGR_INT
+#define MJPEG_REG_FRAME_CNT_TRGR_INT_POS  (16U)
+#define MJPEG_REG_FRAME_CNT_TRGR_INT_LEN  (5U)
+#define MJPEG_REG_FRAME_CNT_TRGR_INT_MSK  (((1U << MJPEG_REG_FRAME_CNT_TRGR_INT_LEN) - 1) << MJPEG_REG_FRAME_CNT_TRGR_INT_POS)
+#define MJPEG_REG_FRAME_CNT_TRGR_INT_UMSK (~(((1U << MJPEG_REG_FRAME_CNT_TRGR_INT_LEN) - 1) << MJPEG_REG_FRAME_CNT_TRGR_INT_POS))
+#define MJPEG_REG_INT_IDLE_EN             MJPEG_REG_INT_IDLE_EN
+#define MJPEG_REG_INT_IDLE_EN_POS         (21U)
+#define MJPEG_REG_INT_IDLE_EN_LEN         (1U)
+#define MJPEG_REG_INT_IDLE_EN_MSK         (((1U << MJPEG_REG_INT_IDLE_EN_LEN) - 1) << MJPEG_REG_INT_IDLE_EN_POS)
+#define MJPEG_REG_INT_IDLE_EN_UMSK        (~(((1U << MJPEG_REG_INT_IDLE_EN_LEN) - 1) << MJPEG_REG_INT_IDLE_EN_POS))
+#define MJPEG_STS_IDLE_INT                MJPEG_STS_IDLE_INT
+#define MJPEG_STS_IDLE_INT_POS            (22U)
+#define MJPEG_STS_IDLE_INT_LEN            (1U)
+#define MJPEG_STS_IDLE_INT_MSK            (((1U << MJPEG_STS_IDLE_INT_LEN) - 1) << MJPEG_STS_IDLE_INT_POS)
+#define MJPEG_STS_IDLE_INT_UMSK           (~(((1U << MJPEG_STS_IDLE_INT_LEN) - 1) << MJPEG_STS_IDLE_INT_POS))
+#define MJPEG_FRAME_VALID_CNT             MJPEG_FRAME_VALID_CNT
+#define MJPEG_FRAME_VALID_CNT_POS         (24U)
+#define MJPEG_FRAME_VALID_CNT_LEN         (5U)
+#define MJPEG_FRAME_VALID_CNT_MSK         (((1U << MJPEG_FRAME_VALID_CNT_LEN) - 1) << MJPEG_FRAME_VALID_CNT_POS)
+#define MJPEG_FRAME_VALID_CNT_UMSK        (~(((1U << MJPEG_FRAME_VALID_CNT_LEN) - 1) << MJPEG_FRAME_VALID_CNT_POS))
+#define MJPEG_REG_INT_SWAP_EN             MJPEG_REG_INT_SWAP_EN
+#define MJPEG_REG_INT_SWAP_EN_POS         (29U)
+#define MJPEG_REG_INT_SWAP_EN_LEN         (1U)
+#define MJPEG_REG_INT_SWAP_EN_MSK         (((1U << MJPEG_REG_INT_SWAP_EN_LEN) - 1) << MJPEG_REG_INT_SWAP_EN_POS)
+#define MJPEG_REG_INT_SWAP_EN_UMSK        (~(((1U << MJPEG_REG_INT_SWAP_EN_LEN) - 1) << MJPEG_REG_INT_SWAP_EN_POS))
+#define MJPEG_STS_SWAP_INT                MJPEG_STS_SWAP_INT
+#define MJPEG_STS_SWAP_INT_POS            (30U)
+#define MJPEG_STS_SWAP_INT_LEN            (1U)
+#define MJPEG_STS_SWAP_INT_MSK            (((1U << MJPEG_STS_SWAP_INT_LEN) - 1) << MJPEG_STS_SWAP_INT_POS)
+#define MJPEG_STS_SWAP_INT_UMSK           (~(((1U << MJPEG_STS_SWAP_INT_LEN) - 1) << MJPEG_STS_SWAP_INT_POS))
+
+/* 0x20 : mjpeg_frame_fifo_pop */
+#define MJPEG_FRAME_FIFO_POP_OFFSET   (0x20)
+#define MJPEG_RFIFO_POP               MJPEG_RFIFO_POP
+#define MJPEG_RFIFO_POP_POS           (0U)
+#define MJPEG_RFIFO_POP_LEN           (1U)
+#define MJPEG_RFIFO_POP_MSK           (((1U << MJPEG_RFIFO_POP_LEN) - 1) << MJPEG_RFIFO_POP_POS)
+#define MJPEG_RFIFO_POP_UMSK          (~(((1U << MJPEG_RFIFO_POP_LEN) - 1) << MJPEG_RFIFO_POP_POS))
+#define MJPEG_REG_W_SWAP_CLR          MJPEG_REG_W_SWAP_CLR
+#define MJPEG_REG_W_SWAP_CLR_POS      (1U)
+#define MJPEG_REG_W_SWAP_CLR_LEN      (1U)
+#define MJPEG_REG_W_SWAP_CLR_MSK      (((1U << MJPEG_REG_W_SWAP_CLR_LEN) - 1) << MJPEG_REG_W_SWAP_CLR_POS)
+#define MJPEG_REG_W_SWAP_CLR_UMSK     (~(((1U << MJPEG_REG_W_SWAP_CLR_LEN) - 1) << MJPEG_REG_W_SWAP_CLR_POS))
+#define MJPEG_REG_INT_NORMAL_CLR      MJPEG_REG_INT_NORMAL_CLR
+#define MJPEG_REG_INT_NORMAL_CLR_POS  (8U)
+#define MJPEG_REG_INT_NORMAL_CLR_LEN  (1U)
+#define MJPEG_REG_INT_NORMAL_CLR_MSK  (((1U << MJPEG_REG_INT_NORMAL_CLR_LEN) - 1) << MJPEG_REG_INT_NORMAL_CLR_POS)
+#define MJPEG_REG_INT_NORMAL_CLR_UMSK (~(((1U << MJPEG_REG_INT_NORMAL_CLR_LEN) - 1) << MJPEG_REG_INT_NORMAL_CLR_POS))
+#define MJPEG_REG_INT_CAM_CLR         MJPEG_REG_INT_CAM_CLR
+#define MJPEG_REG_INT_CAM_CLR_POS     (9U)
+#define MJPEG_REG_INT_CAM_CLR_LEN     (1U)
+#define MJPEG_REG_INT_CAM_CLR_MSK     (((1U << MJPEG_REG_INT_CAM_CLR_LEN) - 1) << MJPEG_REG_INT_CAM_CLR_POS)
+#define MJPEG_REG_INT_CAM_CLR_UMSK    (~(((1U << MJPEG_REG_INT_CAM_CLR_LEN) - 1) << MJPEG_REG_INT_CAM_CLR_POS))
+#define MJPEG_REG_INT_MEM_CLR         MJPEG_REG_INT_MEM_CLR
+#define MJPEG_REG_INT_MEM_CLR_POS     (10U)
+#define MJPEG_REG_INT_MEM_CLR_LEN     (1U)
+#define MJPEG_REG_INT_MEM_CLR_MSK     (((1U << MJPEG_REG_INT_MEM_CLR_LEN) - 1) << MJPEG_REG_INT_MEM_CLR_POS)
+#define MJPEG_REG_INT_MEM_CLR_UMSK    (~(((1U << MJPEG_REG_INT_MEM_CLR_LEN) - 1) << MJPEG_REG_INT_MEM_CLR_POS))
+#define MJPEG_REG_INT_FRAME_CLR       MJPEG_REG_INT_FRAME_CLR
+#define MJPEG_REG_INT_FRAME_CLR_POS   (11U)
+#define MJPEG_REG_INT_FRAME_CLR_LEN   (1U)
+#define MJPEG_REG_INT_FRAME_CLR_MSK   (((1U << MJPEG_REG_INT_FRAME_CLR_LEN) - 1) << MJPEG_REG_INT_FRAME_CLR_POS)
+#define MJPEG_REG_INT_FRAME_CLR_UMSK  (~(((1U << MJPEG_REG_INT_FRAME_CLR_LEN) - 1) << MJPEG_REG_INT_FRAME_CLR_POS))
+#define MJPEG_REG_INT_IDLE_CLR        MJPEG_REG_INT_IDLE_CLR
+#define MJPEG_REG_INT_IDLE_CLR_POS    (12U)
+#define MJPEG_REG_INT_IDLE_CLR_LEN    (1U)
+#define MJPEG_REG_INT_IDLE_CLR_MSK    (((1U << MJPEG_REG_INT_IDLE_CLR_LEN) - 1) << MJPEG_REG_INT_IDLE_CLR_POS)
+#define MJPEG_REG_INT_IDLE_CLR_UMSK   (~(((1U << MJPEG_REG_INT_IDLE_CLR_LEN) - 1) << MJPEG_REG_INT_IDLE_CLR_POS))
+#define MJPEG_REG_INT_SWAP_CLR        MJPEG_REG_INT_SWAP_CLR
+#define MJPEG_REG_INT_SWAP_CLR_POS    (13U)
+#define MJPEG_REG_INT_SWAP_CLR_LEN    (1U)
+#define MJPEG_REG_INT_SWAP_CLR_MSK    (((1U << MJPEG_REG_INT_SWAP_CLR_LEN) - 1) << MJPEG_REG_INT_SWAP_CLR_POS)
+#define MJPEG_REG_INT_SWAP_CLR_UMSK   (~(((1U << MJPEG_REG_INT_SWAP_CLR_LEN) - 1) << MJPEG_REG_INT_SWAP_CLR_POS))
+
+/* 0x24 : mjpeg_frame_size */
+#define MJPEG_FRAME_SIZE_OFFSET   (0x24)
+#define MJPEG_REG_FRAME_WBLK      MJPEG_REG_FRAME_WBLK
+#define MJPEG_REG_FRAME_WBLK_POS  (0U)
+#define MJPEG_REG_FRAME_WBLK_LEN  (12U)
+#define MJPEG_REG_FRAME_WBLK_MSK  (((1U << MJPEG_REG_FRAME_WBLK_LEN) - 1) << MJPEG_REG_FRAME_WBLK_POS)
+#define MJPEG_REG_FRAME_WBLK_UMSK (~(((1U << MJPEG_REG_FRAME_WBLK_LEN) - 1) << MJPEG_REG_FRAME_WBLK_POS))
+#define MJPEG_REG_FRAME_HBLK      MJPEG_REG_FRAME_HBLK
+#define MJPEG_REG_FRAME_HBLK_POS  (16U)
+#define MJPEG_REG_FRAME_HBLK_LEN  (12U)
+#define MJPEG_REG_FRAME_HBLK_MSK  (((1U << MJPEG_REG_FRAME_HBLK_LEN) - 1) << MJPEG_REG_FRAME_HBLK_POS)
+#define MJPEG_REG_FRAME_HBLK_UMSK (~(((1U << MJPEG_REG_FRAME_HBLK_LEN) - 1) << MJPEG_REG_FRAME_HBLK_POS))
+
+/* 0x28 : mjpeg_header_byte */
+#define MJPEG_HEADER_BYTE_OFFSET (0x28)
+#define MJPEG_REG_HEAD_BYTE      MJPEG_REG_HEAD_BYTE
+#define MJPEG_REG_HEAD_BYTE_POS  (0U)
+#define MJPEG_REG_HEAD_BYTE_LEN  (12U)
+#define MJPEG_REG_HEAD_BYTE_MSK  (((1U << MJPEG_REG_HEAD_BYTE_LEN) - 1) << MJPEG_REG_HEAD_BYTE_POS)
+#define MJPEG_REG_HEAD_BYTE_UMSK (~(((1U << MJPEG_REG_HEAD_BYTE_LEN) - 1) << MJPEG_REG_HEAD_BYTE_POS))
+#define MJPEG_REG_TAIL_EXP       MJPEG_REG_TAIL_EXP
+#define MJPEG_REG_TAIL_EXP_POS   (16U)
+#define MJPEG_REG_TAIL_EXP_LEN   (1U)
+#define MJPEG_REG_TAIL_EXP_MSK   (((1U << MJPEG_REG_TAIL_EXP_LEN) - 1) << MJPEG_REG_TAIL_EXP_POS)
+#define MJPEG_REG_TAIL_EXP_UMSK  (~(((1U << MJPEG_REG_TAIL_EXP_LEN) - 1) << MJPEG_REG_TAIL_EXP_POS))
+
+/* 0x30 : mjpeg_swap_mode */
+#define MJPEG_SWAP_MODE_OFFSET       (0x30)
+#define MJPEG_REG_W_SWAP_MODE        MJPEG_REG_W_SWAP_MODE
+#define MJPEG_REG_W_SWAP_MODE_POS    (0U)
+#define MJPEG_REG_W_SWAP_MODE_LEN    (1U)
+#define MJPEG_REG_W_SWAP_MODE_MSK    (((1U << MJPEG_REG_W_SWAP_MODE_LEN) - 1) << MJPEG_REG_W_SWAP_MODE_POS)
+#define MJPEG_REG_W_SWAP_MODE_UMSK   (~(((1U << MJPEG_REG_W_SWAP_MODE_LEN) - 1) << MJPEG_REG_W_SWAP_MODE_POS))
+#define MJPEG_STS_SWAP0_FULL         MJPEG_STS_SWAP0_FULL
+#define MJPEG_STS_SWAP0_FULL_POS     (8U)
+#define MJPEG_STS_SWAP0_FULL_LEN     (1U)
+#define MJPEG_STS_SWAP0_FULL_MSK     (((1U << MJPEG_STS_SWAP0_FULL_LEN) - 1) << MJPEG_STS_SWAP0_FULL_POS)
+#define MJPEG_STS_SWAP0_FULL_UMSK    (~(((1U << MJPEG_STS_SWAP0_FULL_LEN) - 1) << MJPEG_STS_SWAP0_FULL_POS))
+#define MJPEG_STS_SWAP1_FULL         MJPEG_STS_SWAP1_FULL
+#define MJPEG_STS_SWAP1_FULL_POS     (9U)
+#define MJPEG_STS_SWAP1_FULL_LEN     (1U)
+#define MJPEG_STS_SWAP1_FULL_MSK     (((1U << MJPEG_STS_SWAP1_FULL_LEN) - 1) << MJPEG_STS_SWAP1_FULL_POS)
+#define MJPEG_STS_SWAP1_FULL_UMSK    (~(((1U << MJPEG_STS_SWAP1_FULL_LEN) - 1) << MJPEG_STS_SWAP1_FULL_POS))
+#define MJPEG_STS_READ_SWAP_IDX      MJPEG_STS_READ_SWAP_IDX
+#define MJPEG_STS_READ_SWAP_IDX_POS  (10U)
+#define MJPEG_STS_READ_SWAP_IDX_LEN  (1U)
+#define MJPEG_STS_READ_SWAP_IDX_MSK  (((1U << MJPEG_STS_READ_SWAP_IDX_LEN) - 1) << MJPEG_STS_READ_SWAP_IDX_POS)
+#define MJPEG_STS_READ_SWAP_IDX_UMSK (~(((1U << MJPEG_STS_READ_SWAP_IDX_LEN) - 1) << MJPEG_STS_READ_SWAP_IDX_POS))
+#define MJPEG_STS_SWAP_FSTART        MJPEG_STS_SWAP_FSTART
+#define MJPEG_STS_SWAP_FSTART_POS    (11U)
+#define MJPEG_STS_SWAP_FSTART_LEN    (1U)
+#define MJPEG_STS_SWAP_FSTART_MSK    (((1U << MJPEG_STS_SWAP_FSTART_LEN) - 1) << MJPEG_STS_SWAP_FSTART_POS)
+#define MJPEG_STS_SWAP_FSTART_UMSK   (~(((1U << MJPEG_STS_SWAP_FSTART_LEN) - 1) << MJPEG_STS_SWAP_FSTART_POS))
+#define MJPEG_STS_SWAP_FEND          MJPEG_STS_SWAP_FEND
+#define MJPEG_STS_SWAP_FEND_POS      (12U)
+#define MJPEG_STS_SWAP_FEND_LEN      (1U)
+#define MJPEG_STS_SWAP_FEND_MSK      (((1U << MJPEG_STS_SWAP_FEND_LEN) - 1) << MJPEG_STS_SWAP_FEND_POS)
+#define MJPEG_STS_SWAP_FEND_UMSK     (~(((1U << MJPEG_STS_SWAP_FEND_LEN) - 1) << MJPEG_STS_SWAP_FEND_POS))
+
+/* 0x34 : mjpeg_swap_bit_cnt */
+#define MJPEG_SWAP_BIT_CNT_OFFSET         (0x34)
+#define MJPEG_FRAME_SWAP_END_BIT_CNT      MJPEG_FRAME_SWAP_END_BIT_CNT
+#define MJPEG_FRAME_SWAP_END_BIT_CNT_POS  (0U)
+#define MJPEG_FRAME_SWAP_END_BIT_CNT_LEN  (32U)
+#define MJPEG_FRAME_SWAP_END_BIT_CNT_MSK  (((1U << MJPEG_FRAME_SWAP_END_BIT_CNT_LEN) - 1) << MJPEG_FRAME_SWAP_END_BIT_CNT_POS)
+#define MJPEG_FRAME_SWAP_END_BIT_CNT_UMSK (~(((1U << MJPEG_FRAME_SWAP_END_BIT_CNT_LEN) - 1) << MJPEG_FRAME_SWAP_END_BIT_CNT_POS))
+
+/* 0x38 : mjpeg_paket_ctrl */
+#define MJPEG_PAKET_CTRL_OFFSET       (0x38)
+#define MJPEG_REG_PKET_EN             MJPEG_REG_PKET_EN
+#define MJPEG_REG_PKET_EN_POS         (0U)
+#define MJPEG_REG_PKET_EN_LEN         (1U)
+#define MJPEG_REG_PKET_EN_MSK         (((1U << MJPEG_REG_PKET_EN_LEN) - 1) << MJPEG_REG_PKET_EN_POS)
+#define MJPEG_REG_PKET_EN_UMSK        (~(((1U << MJPEG_REG_PKET_EN_LEN) - 1) << MJPEG_REG_PKET_EN_POS))
+#define MJPEG_REG_JEND_TO_PEND        MJPEG_REG_JEND_TO_PEND
+#define MJPEG_REG_JEND_TO_PEND_POS    (1U)
+#define MJPEG_REG_JEND_TO_PEND_LEN    (1U)
+#define MJPEG_REG_JEND_TO_PEND_MSK    (((1U << MJPEG_REG_JEND_TO_PEND_LEN) - 1) << MJPEG_REG_JEND_TO_PEND_POS)
+#define MJPEG_REG_JEND_TO_PEND_UMSK   (~(((1U << MJPEG_REG_JEND_TO_PEND_LEN) - 1) << MJPEG_REG_JEND_TO_PEND_POS))
+#define MJPEG_REG_PKET_BODY_BYTE      MJPEG_REG_PKET_BODY_BYTE
+#define MJPEG_REG_PKET_BODY_BYTE_POS  (16U)
+#define MJPEG_REG_PKET_BODY_BYTE_LEN  (16U)
+#define MJPEG_REG_PKET_BODY_BYTE_MSK  (((1U << MJPEG_REG_PKET_BODY_BYTE_LEN) - 1) << MJPEG_REG_PKET_BODY_BYTE_POS)
+#define MJPEG_REG_PKET_BODY_BYTE_UMSK (~(((1U << MJPEG_REG_PKET_BODY_BYTE_LEN) - 1) << MJPEG_REG_PKET_BODY_BYTE_POS))
+
+/* 0x3C : mjpeg_paket_head_tail */
+#define MJPEG_PAKET_HEAD_TAIL_OFFSET  (0x3C)
+#define MJPEG_REG_PKET_HEAD_BYTE      MJPEG_REG_PKET_HEAD_BYTE
+#define MJPEG_REG_PKET_HEAD_BYTE_POS  (0U)
+#define MJPEG_REG_PKET_HEAD_BYTE_LEN  (12U)
+#define MJPEG_REG_PKET_HEAD_BYTE_MSK  (((1U << MJPEG_REG_PKET_HEAD_BYTE_LEN) - 1) << MJPEG_REG_PKET_HEAD_BYTE_POS)
+#define MJPEG_REG_PKET_HEAD_BYTE_UMSK (~(((1U << MJPEG_REG_PKET_HEAD_BYTE_LEN) - 1) << MJPEG_REG_PKET_HEAD_BYTE_POS))
+#define MJPEG_REG_PKET_TAIL_BYTE      MJPEG_REG_PKET_TAIL_BYTE
+#define MJPEG_REG_PKET_TAIL_BYTE_POS  (16U)
+#define MJPEG_REG_PKET_TAIL_BYTE_LEN  (12U)
+#define MJPEG_REG_PKET_TAIL_BYTE_MSK  (((1U << MJPEG_REG_PKET_TAIL_BYTE_LEN) - 1) << MJPEG_REG_PKET_TAIL_BYTE_POS)
+#define MJPEG_REG_PKET_TAIL_BYTE_UMSK (~(((1U << MJPEG_REG_PKET_TAIL_BYTE_LEN) - 1) << MJPEG_REG_PKET_TAIL_BYTE_POS))
+
+/* 0x40 : mjpeg_Y_frame_read_status_1 */
+#define MJPEG_Y_FRAME_READ_STATUS_1_OFFSET (0x40)
+#define MJPEG_YY_MEM_HBLK_R                MJPEG_YY_MEM_HBLK_R
+#define MJPEG_YY_MEM_HBLK_R_POS            (0U)
+#define MJPEG_YY_MEM_HBLK_R_LEN            (13U)
+#define MJPEG_YY_MEM_HBLK_R_MSK            (((1U << MJPEG_YY_MEM_HBLK_R_LEN) - 1) << MJPEG_YY_MEM_HBLK_R_POS)
+#define MJPEG_YY_MEM_HBLK_R_UMSK           (~(((1U << MJPEG_YY_MEM_HBLK_R_LEN) - 1) << MJPEG_YY_MEM_HBLK_R_POS))
+#define MJPEG_YY_FRM_HBLK_R                MJPEG_YY_FRM_HBLK_R
+#define MJPEG_YY_FRM_HBLK_R_POS            (16U)
+#define MJPEG_YY_FRM_HBLK_R_LEN            (13U)
+#define MJPEG_YY_FRM_HBLK_R_MSK            (((1U << MJPEG_YY_FRM_HBLK_R_LEN) - 1) << MJPEG_YY_FRM_HBLK_R_POS)
+#define MJPEG_YY_FRM_HBLK_R_UMSK           (~(((1U << MJPEG_YY_FRM_HBLK_R_LEN) - 1) << MJPEG_YY_FRM_HBLK_R_POS))
+
+/* 0x44 : mjpeg_Y_frame_read_status_2 */
+#define MJPEG_Y_FRAME_READ_STATUS_2_OFFSET (0x44)
+#define MJPEG_YY_WBLK_R                    MJPEG_YY_WBLK_R
+#define MJPEG_YY_WBLK_R_POS                (0U)
+#define MJPEG_YY_WBLK_R_LEN                (13U)
+#define MJPEG_YY_WBLK_R_MSK                (((1U << MJPEG_YY_WBLK_R_LEN) - 1) << MJPEG_YY_WBLK_R_POS)
+#define MJPEG_YY_WBLK_R_UMSK               (~(((1U << MJPEG_YY_WBLK_R_LEN) - 1) << MJPEG_YY_WBLK_R_POS))
+#define MJPEG_YY_MEM_RND_R                 MJPEG_YY_MEM_RND_R
+#define MJPEG_YY_MEM_RND_R_POS             (16U)
+#define MJPEG_YY_MEM_RND_R_LEN             (8U)
+#define MJPEG_YY_MEM_RND_R_MSK             (((1U << MJPEG_YY_MEM_RND_R_LEN) - 1) << MJPEG_YY_MEM_RND_R_POS)
+#define MJPEG_YY_MEM_RND_R_UMSK            (~(((1U << MJPEG_YY_MEM_RND_R_LEN) - 1) << MJPEG_YY_MEM_RND_R_POS))
+#define MJPEG_YY_FRM_CNT_R                 MJPEG_YY_FRM_CNT_R
+#define MJPEG_YY_FRM_CNT_R_POS             (24U)
+#define MJPEG_YY_FRM_CNT_R_LEN             (8U)
+#define MJPEG_YY_FRM_CNT_R_MSK             (((1U << MJPEG_YY_FRM_CNT_R_LEN) - 1) << MJPEG_YY_FRM_CNT_R_POS)
+#define MJPEG_YY_FRM_CNT_R_UMSK            (~(((1U << MJPEG_YY_FRM_CNT_R_LEN) - 1) << MJPEG_YY_FRM_CNT_R_POS))
+
+/* 0x48 : mjpeg_Y_frame_write_status */
+#define MJPEG_Y_FRAME_WRITE_STATUS_OFFSET (0x48)
+#define MJPEG_YY_MEM_HBLK_W               MJPEG_YY_MEM_HBLK_W
+#define MJPEG_YY_MEM_HBLK_W_POS           (0U)
+#define MJPEG_YY_MEM_HBLK_W_LEN           (13U)
+#define MJPEG_YY_MEM_HBLK_W_MSK           (((1U << MJPEG_YY_MEM_HBLK_W_LEN) - 1) << MJPEG_YY_MEM_HBLK_W_POS)
+#define MJPEG_YY_MEM_HBLK_W_UMSK          (~(((1U << MJPEG_YY_MEM_HBLK_W_LEN) - 1) << MJPEG_YY_MEM_HBLK_W_POS))
+#define MJPEG_YY_MEM_RND_W                MJPEG_YY_MEM_RND_W
+#define MJPEG_YY_MEM_RND_W_POS            (16U)
+#define MJPEG_YY_MEM_RND_W_LEN            (8U)
+#define MJPEG_YY_MEM_RND_W_MSK            (((1U << MJPEG_YY_MEM_RND_W_LEN) - 1) << MJPEG_YY_MEM_RND_W_POS)
+#define MJPEG_YY_MEM_RND_W_UMSK           (~(((1U << MJPEG_YY_MEM_RND_W_LEN) - 1) << MJPEG_YY_MEM_RND_W_POS))
+#define MJPEG_YY_FRM_CNT_W                MJPEG_YY_FRM_CNT_W
+#define MJPEG_YY_FRM_CNT_W_POS            (24U)
+#define MJPEG_YY_FRM_CNT_W_LEN            (8U)
+#define MJPEG_YY_FRM_CNT_W_MSK            (((1U << MJPEG_YY_FRM_CNT_W_LEN) - 1) << MJPEG_YY_FRM_CNT_W_POS)
+#define MJPEG_YY_FRM_CNT_W_UMSK           (~(((1U << MJPEG_YY_FRM_CNT_W_LEN) - 1) << MJPEG_YY_FRM_CNT_W_POS))
+
+/* 0x4C : mjpeg_UV_frame_read_status_1 */
+#define MJPEG_UV_FRAME_READ_STATUS_1_OFFSET (0x4C)
+#define MJPEG_UV_MEM_HBLK_R                 MJPEG_UV_MEM_HBLK_R
+#define MJPEG_UV_MEM_HBLK_R_POS             (0U)
+#define MJPEG_UV_MEM_HBLK_R_LEN             (13U)
+#define MJPEG_UV_MEM_HBLK_R_MSK             (((1U << MJPEG_UV_MEM_HBLK_R_LEN) - 1) << MJPEG_UV_MEM_HBLK_R_POS)
+#define MJPEG_UV_MEM_HBLK_R_UMSK            (~(((1U << MJPEG_UV_MEM_HBLK_R_LEN) - 1) << MJPEG_UV_MEM_HBLK_R_POS))
+#define MJPEG_UV_FRM_HBLK_R                 MJPEG_UV_FRM_HBLK_R
+#define MJPEG_UV_FRM_HBLK_R_POS             (16U)
+#define MJPEG_UV_FRM_HBLK_R_LEN             (13U)
+#define MJPEG_UV_FRM_HBLK_R_MSK             (((1U << MJPEG_UV_FRM_HBLK_R_LEN) - 1) << MJPEG_UV_FRM_HBLK_R_POS)
+#define MJPEG_UV_FRM_HBLK_R_UMSK            (~(((1U << MJPEG_UV_FRM_HBLK_R_LEN) - 1) << MJPEG_UV_FRM_HBLK_R_POS))
+
+/* 0x50 : mjpeg_UV_frame_read_status_2 */
+#define MJPEG_UV_FRAME_READ_STATUS_2_OFFSET (0x50)
+#define MJPEG_UV_WBLK_R                     MJPEG_UV_WBLK_R
+#define MJPEG_UV_WBLK_R_POS                 (0U)
+#define MJPEG_UV_WBLK_R_LEN                 (13U)
+#define MJPEG_UV_WBLK_R_MSK                 (((1U << MJPEG_UV_WBLK_R_LEN) - 1) << MJPEG_UV_WBLK_R_POS)
+#define MJPEG_UV_WBLK_R_UMSK                (~(((1U << MJPEG_UV_WBLK_R_LEN) - 1) << MJPEG_UV_WBLK_R_POS))
+#define MJPEG_UV_MEM_RND_R                  MJPEG_UV_MEM_RND_R
+#define MJPEG_UV_MEM_RND_R_POS              (16U)
+#define MJPEG_UV_MEM_RND_R_LEN              (8U)
+#define MJPEG_UV_MEM_RND_R_MSK              (((1U << MJPEG_UV_MEM_RND_R_LEN) - 1) << MJPEG_UV_MEM_RND_R_POS)
+#define MJPEG_UV_MEM_RND_R_UMSK             (~(((1U << MJPEG_UV_MEM_RND_R_LEN) - 1) << MJPEG_UV_MEM_RND_R_POS))
+#define MJPEG_UV_FRM_CNT_R                  MJPEG_UV_FRM_CNT_R
+#define MJPEG_UV_FRM_CNT_R_POS              (24U)
+#define MJPEG_UV_FRM_CNT_R_LEN              (8U)
+#define MJPEG_UV_FRM_CNT_R_MSK              (((1U << MJPEG_UV_FRM_CNT_R_LEN) - 1) << MJPEG_UV_FRM_CNT_R_POS)
+#define MJPEG_UV_FRM_CNT_R_UMSK             (~(((1U << MJPEG_UV_FRM_CNT_R_LEN) - 1) << MJPEG_UV_FRM_CNT_R_POS))
+
+/* 0x54 : mjpeg_UV_frame_write_status */
+#define MJPEG_UV_FRAME_WRITE_STATUS_OFFSET (0x54)
+#define MJPEG_UV_MEM_HBLK_W                MJPEG_UV_MEM_HBLK_W
+#define MJPEG_UV_MEM_HBLK_W_POS            (0U)
+#define MJPEG_UV_MEM_HBLK_W_LEN            (13U)
+#define MJPEG_UV_MEM_HBLK_W_MSK            (((1U << MJPEG_UV_MEM_HBLK_W_LEN) - 1) << MJPEG_UV_MEM_HBLK_W_POS)
+#define MJPEG_UV_MEM_HBLK_W_UMSK           (~(((1U << MJPEG_UV_MEM_HBLK_W_LEN) - 1) << MJPEG_UV_MEM_HBLK_W_POS))
+#define MJPEG_UV_MEM_RND_W                 MJPEG_UV_MEM_RND_W
+#define MJPEG_UV_MEM_RND_W_POS             (16U)
+#define MJPEG_UV_MEM_RND_W_LEN             (8U)
+#define MJPEG_UV_MEM_RND_W_MSK             (((1U << MJPEG_UV_MEM_RND_W_LEN) - 1) << MJPEG_UV_MEM_RND_W_POS)
+#define MJPEG_UV_MEM_RND_W_UMSK            (~(((1U << MJPEG_UV_MEM_RND_W_LEN) - 1) << MJPEG_UV_MEM_RND_W_POS))
+#define MJPEG_UV_FRM_CNT_W                 MJPEG_UV_FRM_CNT_W
+#define MJPEG_UV_FRM_CNT_W_POS             (24U)
+#define MJPEG_UV_FRM_CNT_W_LEN             (8U)
+#define MJPEG_UV_FRM_CNT_W_MSK             (((1U << MJPEG_UV_FRM_CNT_W_LEN) - 1) << MJPEG_UV_FRM_CNT_W_POS)
+#define MJPEG_UV_FRM_CNT_W_UMSK            (~(((1U << MJPEG_UV_FRM_CNT_W_LEN) - 1) << MJPEG_UV_FRM_CNT_W_POS))
+
+/* 0x80 : mjpeg_start_addr0 */
+#define MJPEG_START_ADDR0_OFFSET      (0x80)
+#define MJPEG_FRAME_START_ADDR_0      MJPEG_FRAME_START_ADDR_0
+#define MJPEG_FRAME_START_ADDR_0_POS  (0U)
+#define MJPEG_FRAME_START_ADDR_0_LEN  (32U)
+#define MJPEG_FRAME_START_ADDR_0_MSK  (((1U << MJPEG_FRAME_START_ADDR_0_LEN) - 1) << MJPEG_FRAME_START_ADDR_0_POS)
+#define MJPEG_FRAME_START_ADDR_0_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_0_LEN) - 1) << MJPEG_FRAME_START_ADDR_0_POS))
+
+/* 0x84 : mjpeg_bit_cnt0 */
+#define MJPEG_BIT_CNT0_OFFSET      (0x84)
+#define MJPEG_FRAME_BIT_CNT_0      MJPEG_FRAME_BIT_CNT_0
+#define MJPEG_FRAME_BIT_CNT_0_POS  (0U)
+#define MJPEG_FRAME_BIT_CNT_0_LEN  (32U)
+#define MJPEG_FRAME_BIT_CNT_0_MSK  (((1U << MJPEG_FRAME_BIT_CNT_0_LEN) - 1) << MJPEG_FRAME_BIT_CNT_0_POS)
+#define MJPEG_FRAME_BIT_CNT_0_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_0_LEN) - 1) << MJPEG_FRAME_BIT_CNT_0_POS))
+
+/* 0x88 : mjpeg_start_addr1 */
+#define MJPEG_START_ADDR1_OFFSET      (0x88)
+#define MJPEG_FRAME_START_ADDR_1      MJPEG_FRAME_START_ADDR_1
+#define MJPEG_FRAME_START_ADDR_1_POS  (0U)
+#define MJPEG_FRAME_START_ADDR_1_LEN  (32U)
+#define MJPEG_FRAME_START_ADDR_1_MSK  (((1U << MJPEG_FRAME_START_ADDR_1_LEN) - 1) << MJPEG_FRAME_START_ADDR_1_POS)
+#define MJPEG_FRAME_START_ADDR_1_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_1_LEN) - 1) << MJPEG_FRAME_START_ADDR_1_POS))
+
+/* 0x8C : mjpeg_bit_cnt1 */
+#define MJPEG_BIT_CNT1_OFFSET      (0x8C)
+#define MJPEG_FRAME_BIT_CNT_1      MJPEG_FRAME_BIT_CNT_1
+#define MJPEG_FRAME_BIT_CNT_1_POS  (0U)
+#define MJPEG_FRAME_BIT_CNT_1_LEN  (32U)
+#define MJPEG_FRAME_BIT_CNT_1_MSK  (((1U << MJPEG_FRAME_BIT_CNT_1_LEN) - 1) << MJPEG_FRAME_BIT_CNT_1_POS)
+#define MJPEG_FRAME_BIT_CNT_1_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_1_LEN) - 1) << MJPEG_FRAME_BIT_CNT_1_POS))
+
+/* 0x90 : mjpeg_start_addr2 */
+#define MJPEG_START_ADDR2_OFFSET      (0x90)
+#define MJPEG_FRAME_START_ADDR_2      MJPEG_FRAME_START_ADDR_2
+#define MJPEG_FRAME_START_ADDR_2_POS  (0U)
+#define MJPEG_FRAME_START_ADDR_2_LEN  (32U)
+#define MJPEG_FRAME_START_ADDR_2_MSK  (((1U << MJPEG_FRAME_START_ADDR_2_LEN) - 1) << MJPEG_FRAME_START_ADDR_2_POS)
+#define MJPEG_FRAME_START_ADDR_2_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_2_LEN) - 1) << MJPEG_FRAME_START_ADDR_2_POS))
+
+/* 0x94 : mjpeg_bit_cnt2 */
+#define MJPEG_BIT_CNT2_OFFSET      (0x94)
+#define MJPEG_FRAME_BIT_CNT_2      MJPEG_FRAME_BIT_CNT_2
+#define MJPEG_FRAME_BIT_CNT_2_POS  (0U)
+#define MJPEG_FRAME_BIT_CNT_2_LEN  (32U)
+#define MJPEG_FRAME_BIT_CNT_2_MSK  (((1U << MJPEG_FRAME_BIT_CNT_2_LEN) - 1) << MJPEG_FRAME_BIT_CNT_2_POS)
+#define MJPEG_FRAME_BIT_CNT_2_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_2_LEN) - 1) << MJPEG_FRAME_BIT_CNT_2_POS))
+
+/* 0x98 : mjpeg_start_addr3 */
+#define MJPEG_START_ADDR3_OFFSET      (0x98)
+#define MJPEG_FRAME_START_ADDR_3      MJPEG_FRAME_START_ADDR_3
+#define MJPEG_FRAME_START_ADDR_3_POS  (0U)
+#define MJPEG_FRAME_START_ADDR_3_LEN  (32U)
+#define MJPEG_FRAME_START_ADDR_3_MSK  (((1U << MJPEG_FRAME_START_ADDR_3_LEN) - 1) << MJPEG_FRAME_START_ADDR_3_POS)
+#define MJPEG_FRAME_START_ADDR_3_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_3_LEN) - 1) << MJPEG_FRAME_START_ADDR_3_POS))
+
+/* 0x9C : mjpeg_bit_cnt3 */
+#define MJPEG_BIT_CNT3_OFFSET      (0x9C)
+#define MJPEG_FRAME_BIT_CNT_3      MJPEG_FRAME_BIT_CNT_3
+#define MJPEG_FRAME_BIT_CNT_3_POS  (0U)
+#define MJPEG_FRAME_BIT_CNT_3_LEN  (32U)
+#define MJPEG_FRAME_BIT_CNT_3_MSK  (((1U << MJPEG_FRAME_BIT_CNT_3_LEN) - 1) << MJPEG_FRAME_BIT_CNT_3_POS)
+#define MJPEG_FRAME_BIT_CNT_3_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_3_LEN) - 1) << MJPEG_FRAME_BIT_CNT_3_POS))
+
+/* 0xA0 : mjpeg_start_addr4 */
+#define MJPEG_START_ADDR4_OFFSET      (0xA0)
+#define MJPEG_FRAME_START_ADDR_4      MJPEG_FRAME_START_ADDR_4
+#define MJPEG_FRAME_START_ADDR_4_POS  (0U)
+#define MJPEG_FRAME_START_ADDR_4_LEN  (32U)
+#define MJPEG_FRAME_START_ADDR_4_MSK  (((1U << MJPEG_FRAME_START_ADDR_4_LEN) - 1) << MJPEG_FRAME_START_ADDR_4_POS)
+#define MJPEG_FRAME_START_ADDR_4_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_4_LEN) - 1) << MJPEG_FRAME_START_ADDR_4_POS))
+
+/* 0xA4 : mjpeg_bit_cnt4 */
+#define MJPEG_BIT_CNT4_OFFSET      (0xA4)
+#define MJPEG_FRAME_BIT_CNT_4      MJPEG_FRAME_BIT_CNT_4
+#define MJPEG_FRAME_BIT_CNT_4_POS  (0U)
+#define MJPEG_FRAME_BIT_CNT_4_LEN  (32U)
+#define MJPEG_FRAME_BIT_CNT_4_MSK  (((1U << MJPEG_FRAME_BIT_CNT_4_LEN) - 1) << MJPEG_FRAME_BIT_CNT_4_POS)
+#define MJPEG_FRAME_BIT_CNT_4_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_4_LEN) - 1) << MJPEG_FRAME_BIT_CNT_4_POS))
+
+/* 0xA8 : mjpeg_start_addr5 */
+#define MJPEG_START_ADDR5_OFFSET      (0xA8)
+#define MJPEG_FRAME_START_ADDR_5      MJPEG_FRAME_START_ADDR_5
+#define MJPEG_FRAME_START_ADDR_5_POS  (0U)
+#define MJPEG_FRAME_START_ADDR_5_LEN  (32U)
+#define MJPEG_FRAME_START_ADDR_5_MSK  (((1U << MJPEG_FRAME_START_ADDR_5_LEN) - 1) << MJPEG_FRAME_START_ADDR_5_POS)
+#define MJPEG_FRAME_START_ADDR_5_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_5_LEN) - 1) << MJPEG_FRAME_START_ADDR_5_POS))
+
+/* 0xAC : mjpeg_bit_cnt5 */
+#define MJPEG_BIT_CNT5_OFFSET      (0xAC)
+#define MJPEG_FRAME_BIT_CNT_5      MJPEG_FRAME_BIT_CNT_5
+#define MJPEG_FRAME_BIT_CNT_5_POS  (0U)
+#define MJPEG_FRAME_BIT_CNT_5_LEN  (32U)
+#define MJPEG_FRAME_BIT_CNT_5_MSK  (((1U << MJPEG_FRAME_BIT_CNT_5_LEN) - 1) << MJPEG_FRAME_BIT_CNT_5_POS)
+#define MJPEG_FRAME_BIT_CNT_5_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_5_LEN) - 1) << MJPEG_FRAME_BIT_CNT_5_POS))
+
+/* 0xB0 : mjpeg_start_addr6 */
+#define MJPEG_START_ADDR6_OFFSET      (0xB0)
+#define MJPEG_FRAME_START_ADDR_6      MJPEG_FRAME_START_ADDR_6
+#define MJPEG_FRAME_START_ADDR_6_POS  (0U)
+#define MJPEG_FRAME_START_ADDR_6_LEN  (32U)
+#define MJPEG_FRAME_START_ADDR_6_MSK  (((1U << MJPEG_FRAME_START_ADDR_6_LEN) - 1) << MJPEG_FRAME_START_ADDR_6_POS)
+#define MJPEG_FRAME_START_ADDR_6_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_6_LEN) - 1) << MJPEG_FRAME_START_ADDR_6_POS))
+
+/* 0xB4 : mjpeg_bit_cnt6 */
+#define MJPEG_BIT_CNT6_OFFSET      (0xB4)
+#define MJPEG_FRAME_BIT_CNT_6      MJPEG_FRAME_BIT_CNT_6
+#define MJPEG_FRAME_BIT_CNT_6_POS  (0U)
+#define MJPEG_FRAME_BIT_CNT_6_LEN  (32U)
+#define MJPEG_FRAME_BIT_CNT_6_MSK  (((1U << MJPEG_FRAME_BIT_CNT_6_LEN) - 1) << MJPEG_FRAME_BIT_CNT_6_POS)
+#define MJPEG_FRAME_BIT_CNT_6_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_6_LEN) - 1) << MJPEG_FRAME_BIT_CNT_6_POS))
+
+/* 0xB8 : mjpeg_start_addr7 */
+#define MJPEG_START_ADDR7_OFFSET      (0xB8)
+#define MJPEG_FRAME_START_ADDR_7      MJPEG_FRAME_START_ADDR_7
+#define MJPEG_FRAME_START_ADDR_7_POS  (0U)
+#define MJPEG_FRAME_START_ADDR_7_LEN  (32U)
+#define MJPEG_FRAME_START_ADDR_7_MSK  (((1U << MJPEG_FRAME_START_ADDR_7_LEN) - 1) << MJPEG_FRAME_START_ADDR_7_POS)
+#define MJPEG_FRAME_START_ADDR_7_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_7_LEN) - 1) << MJPEG_FRAME_START_ADDR_7_POS))
+
+/* 0xBC : mjpeg_bit_cnt7 */
+#define MJPEG_BIT_CNT7_OFFSET      (0xBC)
+#define MJPEG_FRAME_BIT_CNT_7      MJPEG_FRAME_BIT_CNT_7
+#define MJPEG_FRAME_BIT_CNT_7_POS  (0U)
+#define MJPEG_FRAME_BIT_CNT_7_LEN  (32U)
+#define MJPEG_FRAME_BIT_CNT_7_MSK  (((1U << MJPEG_FRAME_BIT_CNT_7_LEN) - 1) << MJPEG_FRAME_BIT_CNT_7_POS)
+#define MJPEG_FRAME_BIT_CNT_7_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_7_LEN) - 1) << MJPEG_FRAME_BIT_CNT_7_POS))
+
+/* 0xC0 : mjpeg_start_addr_8 */
+#define MJPEG_START_ADDR_8_OFFSET     (0xC0)
+#define MJPEG_FRAME_START_ADDR_8      MJPEG_FRAME_START_ADDR_8
+#define MJPEG_FRAME_START_ADDR_8_POS  (0U)
+#define MJPEG_FRAME_START_ADDR_8_LEN  (32U)
+#define MJPEG_FRAME_START_ADDR_8_MSK  (((1U << MJPEG_FRAME_START_ADDR_8_LEN) - 1) << MJPEG_FRAME_START_ADDR_8_POS)
+#define MJPEG_FRAME_START_ADDR_8_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_8_LEN) - 1) << MJPEG_FRAME_START_ADDR_8_POS))
+
+/* 0xC4 : mjpeg_bit_cnt_8 */
+#define MJPEG_BIT_CNT_8_OFFSET     (0xC4)
+#define MJPEG_FRAME_BIT_CNT_8      MJPEG_FRAME_BIT_CNT_8
+#define MJPEG_FRAME_BIT_CNT_8_POS  (0U)
+#define MJPEG_FRAME_BIT_CNT_8_LEN  (32U)
+#define MJPEG_FRAME_BIT_CNT_8_MSK  (((1U << MJPEG_FRAME_BIT_CNT_8_LEN) - 1) << MJPEG_FRAME_BIT_CNT_8_POS)
+#define MJPEG_FRAME_BIT_CNT_8_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_8_LEN) - 1) << MJPEG_FRAME_BIT_CNT_8_POS))
+
+/* 0xC8 : mjpeg_start_addr_9 */
+#define MJPEG_START_ADDR_9_OFFSET     (0xC8)
+#define MJPEG_FRAME_START_ADDR_9      MJPEG_FRAME_START_ADDR_9
+#define MJPEG_FRAME_START_ADDR_9_POS  (0U)
+#define MJPEG_FRAME_START_ADDR_9_LEN  (32U)
+#define MJPEG_FRAME_START_ADDR_9_MSK  (((1U << MJPEG_FRAME_START_ADDR_9_LEN) - 1) << MJPEG_FRAME_START_ADDR_9_POS)
+#define MJPEG_FRAME_START_ADDR_9_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_9_LEN) - 1) << MJPEG_FRAME_START_ADDR_9_POS))
+
+/* 0xCC : mjpeg_bit_cnt_9 */
+#define MJPEG_BIT_CNT_9_OFFSET     (0xCC)
+#define MJPEG_FRAME_BIT_CNT_9      MJPEG_FRAME_BIT_CNT_9
+#define MJPEG_FRAME_BIT_CNT_9_POS  (0U)
+#define MJPEG_FRAME_BIT_CNT_9_LEN  (32U)
+#define MJPEG_FRAME_BIT_CNT_9_MSK  (((1U << MJPEG_FRAME_BIT_CNT_9_LEN) - 1) << MJPEG_FRAME_BIT_CNT_9_POS)
+#define MJPEG_FRAME_BIT_CNT_9_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_9_LEN) - 1) << MJPEG_FRAME_BIT_CNT_9_POS))
+
+/* 0xD0 : mjpeg_start_addr_a */
+#define MJPEG_START_ADDR_A_OFFSET     (0xD0)
+#define MJPEG_FRAME_START_ADDR_A      MJPEG_FRAME_START_ADDR_A
+#define MJPEG_FRAME_START_ADDR_A_POS  (0U)
+#define MJPEG_FRAME_START_ADDR_A_LEN  (32U)
+#define MJPEG_FRAME_START_ADDR_A_MSK  (((1U << MJPEG_FRAME_START_ADDR_A_LEN) - 1) << MJPEG_FRAME_START_ADDR_A_POS)
+#define MJPEG_FRAME_START_ADDR_A_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_A_LEN) - 1) << MJPEG_FRAME_START_ADDR_A_POS))
+
+/* 0xD4 : mjpeg_bit_cnt_a */
+#define MJPEG_BIT_CNT_A_OFFSET     (0xD4)
+#define MJPEG_FRAME_BIT_CNT_A      MJPEG_FRAME_BIT_CNT_A
+#define MJPEG_FRAME_BIT_CNT_A_POS  (0U)
+#define MJPEG_FRAME_BIT_CNT_A_LEN  (32U)
+#define MJPEG_FRAME_BIT_CNT_A_MSK  (((1U << MJPEG_FRAME_BIT_CNT_A_LEN) - 1) << MJPEG_FRAME_BIT_CNT_A_POS)
+#define MJPEG_FRAME_BIT_CNT_A_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_A_LEN) - 1) << MJPEG_FRAME_BIT_CNT_A_POS))
+
+/* 0xD8 : mjpeg_start_addr_b */
+#define MJPEG_START_ADDR_B_OFFSET     (0xD8)
+#define MJPEG_FRAME_START_ADDR_B      MJPEG_FRAME_START_ADDR_B
+#define MJPEG_FRAME_START_ADDR_B_POS  (0U)
+#define MJPEG_FRAME_START_ADDR_B_LEN  (32U)
+#define MJPEG_FRAME_START_ADDR_B_MSK  (((1U << MJPEG_FRAME_START_ADDR_B_LEN) - 1) << MJPEG_FRAME_START_ADDR_B_POS)
+#define MJPEG_FRAME_START_ADDR_B_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_B_LEN) - 1) << MJPEG_FRAME_START_ADDR_B_POS))
+
+/* 0xDC : mjpeg_bit_cnt_b */
+#define MJPEG_BIT_CNT_B_OFFSET     (0xDC)
+#define MJPEG_FRAME_BIT_CNT_B      MJPEG_FRAME_BIT_CNT_B
+#define MJPEG_FRAME_BIT_CNT_B_POS  (0U)
+#define MJPEG_FRAME_BIT_CNT_B_LEN  (32U)
+#define MJPEG_FRAME_BIT_CNT_B_MSK  (((1U << MJPEG_FRAME_BIT_CNT_B_LEN) - 1) << MJPEG_FRAME_BIT_CNT_B_POS)
+#define MJPEG_FRAME_BIT_CNT_B_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_B_LEN) - 1) << MJPEG_FRAME_BIT_CNT_B_POS))
+
+/* 0xE0 : mjpeg_start_addr_c */
+#define MJPEG_START_ADDR_C_OFFSET     (0xE0)
+#define MJPEG_FRAME_START_ADDR_C      MJPEG_FRAME_START_ADDR_C
+#define MJPEG_FRAME_START_ADDR_C_POS  (0U)
+#define MJPEG_FRAME_START_ADDR_C_LEN  (32U)
+#define MJPEG_FRAME_START_ADDR_C_MSK  (((1U << MJPEG_FRAME_START_ADDR_C_LEN) - 1) << MJPEG_FRAME_START_ADDR_C_POS)
+#define MJPEG_FRAME_START_ADDR_C_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_C_LEN) - 1) << MJPEG_FRAME_START_ADDR_C_POS))
+
+/* 0xE4 : mjpeg_bit_cnt_c */
+#define MJPEG_BIT_CNT_C_OFFSET     (0xE4)
+#define MJPEG_FRAME_BIT_CNT_C      MJPEG_FRAME_BIT_CNT_C
+#define MJPEG_FRAME_BIT_CNT_C_POS  (0U)
+#define MJPEG_FRAME_BIT_CNT_C_LEN  (32U)
+#define MJPEG_FRAME_BIT_CNT_C_MSK  (((1U << MJPEG_FRAME_BIT_CNT_C_LEN) - 1) << MJPEG_FRAME_BIT_CNT_C_POS)
+#define MJPEG_FRAME_BIT_CNT_C_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_C_LEN) - 1) << MJPEG_FRAME_BIT_CNT_C_POS))
+
+/* 0xE8 : mjpeg_start_addr_d */
+#define MJPEG_START_ADDR_D_OFFSET     (0xE8)
+#define MJPEG_FRAME_START_ADDR_D      MJPEG_FRAME_START_ADDR_D
+#define MJPEG_FRAME_START_ADDR_D_POS  (0U)
+#define MJPEG_FRAME_START_ADDR_D_LEN  (32U)
+#define MJPEG_FRAME_START_ADDR_D_MSK  (((1U << MJPEG_FRAME_START_ADDR_D_LEN) - 1) << MJPEG_FRAME_START_ADDR_D_POS)
+#define MJPEG_FRAME_START_ADDR_D_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_D_LEN) - 1) << MJPEG_FRAME_START_ADDR_D_POS))
+
+/* 0xEC : mjpeg_bit_cnt_d */
+#define MJPEG_BIT_CNT_D_OFFSET     (0xEC)
+#define MJPEG_FRAME_BIT_CNT_D      MJPEG_FRAME_BIT_CNT_D
+#define MJPEG_FRAME_BIT_CNT_D_POS  (0U)
+#define MJPEG_FRAME_BIT_CNT_D_LEN  (32U)
+#define MJPEG_FRAME_BIT_CNT_D_MSK  (((1U << MJPEG_FRAME_BIT_CNT_D_LEN) - 1) << MJPEG_FRAME_BIT_CNT_D_POS)
+#define MJPEG_FRAME_BIT_CNT_D_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_D_LEN) - 1) << MJPEG_FRAME_BIT_CNT_D_POS))
+
+/* 0xF0 : mjpeg_start_addr_e */
+#define MJPEG_START_ADDR_E_OFFSET     (0xF0)
+#define MJPEG_FRAME_START_ADDR_E      MJPEG_FRAME_START_ADDR_E
+#define MJPEG_FRAME_START_ADDR_E_POS  (0U)
+#define MJPEG_FRAME_START_ADDR_E_LEN  (32U)
+#define MJPEG_FRAME_START_ADDR_E_MSK  (((1U << MJPEG_FRAME_START_ADDR_E_LEN) - 1) << MJPEG_FRAME_START_ADDR_E_POS)
+#define MJPEG_FRAME_START_ADDR_E_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_E_LEN) - 1) << MJPEG_FRAME_START_ADDR_E_POS))
+
+/* 0xF4 : mjpeg_bit_cnt_e */
+#define MJPEG_BIT_CNT_E_OFFSET     (0xF4)
+#define MJPEG_FRAME_BIT_CNT_E      MJPEG_FRAME_BIT_CNT_E
+#define MJPEG_FRAME_BIT_CNT_E_POS  (0U)
+#define MJPEG_FRAME_BIT_CNT_E_LEN  (32U)
+#define MJPEG_FRAME_BIT_CNT_E_MSK  (((1U << MJPEG_FRAME_BIT_CNT_E_LEN) - 1) << MJPEG_FRAME_BIT_CNT_E_POS)
+#define MJPEG_FRAME_BIT_CNT_E_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_E_LEN) - 1) << MJPEG_FRAME_BIT_CNT_E_POS))
+
+/* 0xF8 : mjpeg_start_addr_f */
+#define MJPEG_START_ADDR_F_OFFSET     (0xF8)
+#define MJPEG_FRAME_START_ADDR_F      MJPEG_FRAME_START_ADDR_F
+#define MJPEG_FRAME_START_ADDR_F_POS  (0U)
+#define MJPEG_FRAME_START_ADDR_F_LEN  (32U)
+#define MJPEG_FRAME_START_ADDR_F_MSK  (((1U << MJPEG_FRAME_START_ADDR_F_LEN) - 1) << MJPEG_FRAME_START_ADDR_F_POS)
+#define MJPEG_FRAME_START_ADDR_F_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_F_LEN) - 1) << MJPEG_FRAME_START_ADDR_F_POS))
+
+/* 0xFC : mjpeg_bit_cnt_f */
+#define MJPEG_BIT_CNT_F_OFFSET     (0xFC)
+#define MJPEG_FRAME_BIT_CNT_F      MJPEG_FRAME_BIT_CNT_F
+#define MJPEG_FRAME_BIT_CNT_F_POS  (0U)
+#define MJPEG_FRAME_BIT_CNT_F_LEN  (32U)
+#define MJPEG_FRAME_BIT_CNT_F_MSK  (((1U << MJPEG_FRAME_BIT_CNT_F_LEN) - 1) << MJPEG_FRAME_BIT_CNT_F_POS)
+#define MJPEG_FRAME_BIT_CNT_F_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_F_LEN) - 1) << MJPEG_FRAME_BIT_CNT_F_POS))
+
+/* 0x100 : mjpeg_q_mode0 */
+#define MJPEG_Q_MODE0_OFFSET      (0x100)
+#define MJPEG_FRAME_Q_MODE_0      MJPEG_FRAME_Q_MODE_0
+#define MJPEG_FRAME_Q_MODE_0_POS  (0U)
+#define MJPEG_FRAME_Q_MODE_0_LEN  (7U)
+#define MJPEG_FRAME_Q_MODE_0_MSK  (((1U << MJPEG_FRAME_Q_MODE_0_LEN) - 1) << MJPEG_FRAME_Q_MODE_0_POS)
+#define MJPEG_FRAME_Q_MODE_0_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_0_LEN) - 1) << MJPEG_FRAME_Q_MODE_0_POS))
+
+/* 0x104 : mjpeg_q_mode1 */
+#define MJPEG_Q_MODE1_OFFSET      (0x104)
+#define MJPEG_FRAME_Q_MODE_1      MJPEG_FRAME_Q_MODE_1
+#define MJPEG_FRAME_Q_MODE_1_POS  (0U)
+#define MJPEG_FRAME_Q_MODE_1_LEN  (7U)
+#define MJPEG_FRAME_Q_MODE_1_MSK  (((1U << MJPEG_FRAME_Q_MODE_1_LEN) - 1) << MJPEG_FRAME_Q_MODE_1_POS)
+#define MJPEG_FRAME_Q_MODE_1_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_1_LEN) - 1) << MJPEG_FRAME_Q_MODE_1_POS))
+
+/* 0x108 : mjpeg_q_mode2 */
+#define MJPEG_Q_MODE2_OFFSET      (0x108)
+#define MJPEG_FRAME_Q_MODE_2      MJPEG_FRAME_Q_MODE_2
+#define MJPEG_FRAME_Q_MODE_2_POS  (0U)
+#define MJPEG_FRAME_Q_MODE_2_LEN  (7U)
+#define MJPEG_FRAME_Q_MODE_2_MSK  (((1U << MJPEG_FRAME_Q_MODE_2_LEN) - 1) << MJPEG_FRAME_Q_MODE_2_POS)
+#define MJPEG_FRAME_Q_MODE_2_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_2_LEN) - 1) << MJPEG_FRAME_Q_MODE_2_POS))
+
+/* 0x10C : mjpeg_q_mode3 */
+#define MJPEG_Q_MODE3_OFFSET      (0x10C)
+#define MJPEG_FRAME_Q_MODE_3      MJPEG_FRAME_Q_MODE_3
+#define MJPEG_FRAME_Q_MODE_3_POS  (0U)
+#define MJPEG_FRAME_Q_MODE_3_LEN  (7U)
+#define MJPEG_FRAME_Q_MODE_3_MSK  (((1U << MJPEG_FRAME_Q_MODE_3_LEN) - 1) << MJPEG_FRAME_Q_MODE_3_POS)
+#define MJPEG_FRAME_Q_MODE_3_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_3_LEN) - 1) << MJPEG_FRAME_Q_MODE_3_POS))
+
+/* 0x110 : mjpeg_q_mode4 */
+#define MJPEG_Q_MODE4_OFFSET      (0x110)
+#define MJPEG_FRAME_Q_MODE_4      MJPEG_FRAME_Q_MODE_4
+#define MJPEG_FRAME_Q_MODE_4_POS  (0U)
+#define MJPEG_FRAME_Q_MODE_4_LEN  (7U)
+#define MJPEG_FRAME_Q_MODE_4_MSK  (((1U << MJPEG_FRAME_Q_MODE_4_LEN) - 1) << MJPEG_FRAME_Q_MODE_4_POS)
+#define MJPEG_FRAME_Q_MODE_4_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_4_LEN) - 1) << MJPEG_FRAME_Q_MODE_4_POS))
+
+/* 0x114 : mjpeg_q_mode5 */
+#define MJPEG_Q_MODE5_OFFSET      (0x114)
+#define MJPEG_FRAME_Q_MODE_5      MJPEG_FRAME_Q_MODE_5
+#define MJPEG_FRAME_Q_MODE_5_POS  (0U)
+#define MJPEG_FRAME_Q_MODE_5_LEN  (7U)
+#define MJPEG_FRAME_Q_MODE_5_MSK  (((1U << MJPEG_FRAME_Q_MODE_5_LEN) - 1) << MJPEG_FRAME_Q_MODE_5_POS)
+#define MJPEG_FRAME_Q_MODE_5_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_5_LEN) - 1) << MJPEG_FRAME_Q_MODE_5_POS))
+
+/* 0x118 : mjpeg_q_mode6 */
+#define MJPEG_Q_MODE6_OFFSET      (0x118)
+#define MJPEG_FRAME_Q_MODE_6      MJPEG_FRAME_Q_MODE_6
+#define MJPEG_FRAME_Q_MODE_6_POS  (0U)
+#define MJPEG_FRAME_Q_MODE_6_LEN  (7U)
+#define MJPEG_FRAME_Q_MODE_6_MSK  (((1U << MJPEG_FRAME_Q_MODE_6_LEN) - 1) << MJPEG_FRAME_Q_MODE_6_POS)
+#define MJPEG_FRAME_Q_MODE_6_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_6_LEN) - 1) << MJPEG_FRAME_Q_MODE_6_POS))
+
+/* 0x11C : mjpeg_q_mode7 */
+#define MJPEG_Q_MODE7_OFFSET      (0x11C)
+#define MJPEG_FRAME_Q_MODE_7      MJPEG_FRAME_Q_MODE_7
+#define MJPEG_FRAME_Q_MODE_7_POS  (0U)
+#define MJPEG_FRAME_Q_MODE_7_LEN  (7U)
+#define MJPEG_FRAME_Q_MODE_7_MSK  (((1U << MJPEG_FRAME_Q_MODE_7_LEN) - 1) << MJPEG_FRAME_Q_MODE_7_POS)
+#define MJPEG_FRAME_Q_MODE_7_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_7_LEN) - 1) << MJPEG_FRAME_Q_MODE_7_POS))
+
+/* 0x120 : mjpeg_q_mode_8 */
+#define MJPEG_Q_MODE_8_OFFSET     (0x120)
+#define MJPEG_FRAME_Q_MODE_8      MJPEG_FRAME_Q_MODE_8
+#define MJPEG_FRAME_Q_MODE_8_POS  (0U)
+#define MJPEG_FRAME_Q_MODE_8_LEN  (7U)
+#define MJPEG_FRAME_Q_MODE_8_MSK  (((1U << MJPEG_FRAME_Q_MODE_8_LEN) - 1) << MJPEG_FRAME_Q_MODE_8_POS)
+#define MJPEG_FRAME_Q_MODE_8_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_8_LEN) - 1) << MJPEG_FRAME_Q_MODE_8_POS))
+
+/* 0x124 : mjpeg_q_mode_9 */
+#define MJPEG_Q_MODE_9_OFFSET     (0x124)
+#define MJPEG_FRAME_Q_MODE_9      MJPEG_FRAME_Q_MODE_9
+#define MJPEG_FRAME_Q_MODE_9_POS  (0U)
+#define MJPEG_FRAME_Q_MODE_9_LEN  (7U)
+#define MJPEG_FRAME_Q_MODE_9_MSK  (((1U << MJPEG_FRAME_Q_MODE_9_LEN) - 1) << MJPEG_FRAME_Q_MODE_9_POS)
+#define MJPEG_FRAME_Q_MODE_9_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_9_LEN) - 1) << MJPEG_FRAME_Q_MODE_9_POS))
+
+/* 0x128 : mjpeg_q_mode_a */
+#define MJPEG_Q_MODE_A_OFFSET     (0x128)
+#define MJPEG_FRAME_Q_MODE_A      MJPEG_FRAME_Q_MODE_A
+#define MJPEG_FRAME_Q_MODE_A_POS  (0U)
+#define MJPEG_FRAME_Q_MODE_A_LEN  (7U)
+#define MJPEG_FRAME_Q_MODE_A_MSK  (((1U << MJPEG_FRAME_Q_MODE_A_LEN) - 1) << MJPEG_FRAME_Q_MODE_A_POS)
+#define MJPEG_FRAME_Q_MODE_A_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_A_LEN) - 1) << MJPEG_FRAME_Q_MODE_A_POS))
+
+/* 0x12C : mjpeg_q_mode_b */
+#define MJPEG_Q_MODE_B_OFFSET     (0x12C)
+#define MJPEG_FRAME_Q_MODE_B      MJPEG_FRAME_Q_MODE_B
+#define MJPEG_FRAME_Q_MODE_B_POS  (0U)
+#define MJPEG_FRAME_Q_MODE_B_LEN  (7U)
+#define MJPEG_FRAME_Q_MODE_B_MSK  (((1U << MJPEG_FRAME_Q_MODE_B_LEN) - 1) << MJPEG_FRAME_Q_MODE_B_POS)
+#define MJPEG_FRAME_Q_MODE_B_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_B_LEN) - 1) << MJPEG_FRAME_Q_MODE_B_POS))
+
+/* 0x130 : mjpeg_q_mode_c */
+#define MJPEG_Q_MODE_C_OFFSET     (0x130)
+#define MJPEG_FRAME_Q_MODE_C      MJPEG_FRAME_Q_MODE_C
+#define MJPEG_FRAME_Q_MODE_C_POS  (0U)
+#define MJPEG_FRAME_Q_MODE_C_LEN  (7U)
+#define MJPEG_FRAME_Q_MODE_C_MSK  (((1U << MJPEG_FRAME_Q_MODE_C_LEN) - 1) << MJPEG_FRAME_Q_MODE_C_POS)
+#define MJPEG_FRAME_Q_MODE_C_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_C_LEN) - 1) << MJPEG_FRAME_Q_MODE_C_POS))
+
+/* 0x134 : mjpeg_q_mode_d */
+#define MJPEG_Q_MODE_D_OFFSET     (0x134)
+#define MJPEG_FRAME_Q_MODE_D      MJPEG_FRAME_Q_MODE_D
+#define MJPEG_FRAME_Q_MODE_D_POS  (0U)
+#define MJPEG_FRAME_Q_MODE_D_LEN  (7U)
+#define MJPEG_FRAME_Q_MODE_D_MSK  (((1U << MJPEG_FRAME_Q_MODE_D_LEN) - 1) << MJPEG_FRAME_Q_MODE_D_POS)
+#define MJPEG_FRAME_Q_MODE_D_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_D_LEN) - 1) << MJPEG_FRAME_Q_MODE_D_POS))
+
+/* 0x138 : mjpeg_q_mode_e */
+#define MJPEG_Q_MODE_E_OFFSET     (0x138)
+#define MJPEG_FRAME_Q_MODE_E      MJPEG_FRAME_Q_MODE_E
+#define MJPEG_FRAME_Q_MODE_E_POS  (0U)
+#define MJPEG_FRAME_Q_MODE_E_LEN  (7U)
+#define MJPEG_FRAME_Q_MODE_E_MSK  (((1U << MJPEG_FRAME_Q_MODE_E_LEN) - 1) << MJPEG_FRAME_Q_MODE_E_POS)
+#define MJPEG_FRAME_Q_MODE_E_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_E_LEN) - 1) << MJPEG_FRAME_Q_MODE_E_POS))
+
+/* 0x13C : mjpeg_q_mode_f */
+#define MJPEG_Q_MODE_F_OFFSET     (0x13C)
+#define MJPEG_FRAME_Q_MODE_F      MJPEG_FRAME_Q_MODE_F
+#define MJPEG_FRAME_Q_MODE_F_POS  (0U)
+#define MJPEG_FRAME_Q_MODE_F_LEN  (7U)
+#define MJPEG_FRAME_Q_MODE_F_MSK  (((1U << MJPEG_FRAME_Q_MODE_F_LEN) - 1) << MJPEG_FRAME_Q_MODE_F_POS)
+#define MJPEG_FRAME_Q_MODE_F_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_F_LEN) - 1) << MJPEG_FRAME_Q_MODE_F_POS))
+
+/* 0x1F0 : mjpeg_debug */
+#define MJPEG_DEBUG_OFFSET           (0x1F0)
+#define MJPEG_REG_MJPEG_DBG_EN       MJPEG_REG_MJPEG_DBG_EN
+#define MJPEG_REG_MJPEG_DBG_EN_POS   (0U)
+#define MJPEG_REG_MJPEG_DBG_EN_LEN   (1U)
+#define MJPEG_REG_MJPEG_DBG_EN_MSK   (((1U << MJPEG_REG_MJPEG_DBG_EN_LEN) - 1) << MJPEG_REG_MJPEG_DBG_EN_POS)
+#define MJPEG_REG_MJPEG_DBG_EN_UMSK  (~(((1U << MJPEG_REG_MJPEG_DBG_EN_LEN) - 1) << MJPEG_REG_MJPEG_DBG_EN_POS))
+#define MJPEG_REG_MJPEG_DBG_SEL      MJPEG_REG_MJPEG_DBG_SEL
+#define MJPEG_REG_MJPEG_DBG_SEL_POS  (4U)
+#define MJPEG_REG_MJPEG_DBG_SEL_LEN  (4U)
+#define MJPEG_REG_MJPEG_DBG_SEL_MSK  (((1U << MJPEG_REG_MJPEG_DBG_SEL_LEN) - 1) << MJPEG_REG_MJPEG_DBG_SEL_POS)
+#define MJPEG_REG_MJPEG_DBG_SEL_UMSK (~(((1U << MJPEG_REG_MJPEG_DBG_SEL_LEN) - 1) << MJPEG_REG_MJPEG_DBG_SEL_POS))
+
+/* 0x1FC : mjpeg_dummy_reg */
+#define MJPEG_DUMMY_REG_OFFSET (0x1FC)
+#define MJPEG_DUMMY_REG        MJPEG_DUMMY_REG
+#define MJPEG_DUMMY_REG_POS    (0U)
+#define MJPEG_DUMMY_REG_LEN    (32U)
+#define MJPEG_DUMMY_REG_MSK    (((1U << MJPEG_DUMMY_REG_LEN) - 1) << MJPEG_DUMMY_REG_POS)
+#define MJPEG_DUMMY_REG_UMSK   (~(((1U << MJPEG_DUMMY_REG_LEN) - 1) << MJPEG_DUMMY_REG_POS))
+
+struct mjpeg_reg {
+    /* 0x0 : mjpeg_control_1 */
+    union {
+        struct
+        {
+            uint32_t reg_mjpeg_enable     : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_mjpeg_bit_order  : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_order_u_even     : 1; /* [    2],        r/w,        0x1 */
+            uint32_t reg_wr_over_stop     : 1; /* [    3],        r/w,        0x0 */
+            uint32_t reg_last_hf_wblk_dmy : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_last_hf_hblk_dmy : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_reflect_dmy      : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7           : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_h_bust           : 2; /* [ 9: 8],        r/w,        0x3 */
+            uint32_t reserved_10_11       : 2; /* [11:10],       rsvd,        0x0 */
+            uint32_t reg_yuv_mode         : 2; /* [13:12],        r/w,        0x0 */
+            uint32_t reserved_14_15       : 2; /* [15:14],       rsvd,        0x0 */
+            uint32_t reg_q_mode           : 7; /* [22:16],        r/w,       0x32 */
+            uint32_t reserved_23          : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_y0_order         : 2; /* [25:24],        r/w,        0x0 */
+            uint32_t reg_u0_order         : 2; /* [27:26],        r/w,        0x1 */
+            uint32_t reg_y1_order         : 2; /* [29:28],        r/w,        0x2 */
+            uint32_t reg_v0_order         : 2; /* [31:30],        r/w,        0x3 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_control_1;
+
+    /* 0x4 : mjpeg_control_2 */
+    union {
+        struct
+        {
+            uint32_t reg_sw_frame         : 5;  /* [ 4: 0],        r/w,        0x0 */
+            uint32_t reserved_5_7         : 3;  /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t reg_mjpeg_sw_mode    : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t reg_mjpeg_sw_run     : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t reserved_10_11       : 2;  /* [11:10],       rsvd,        0x0 */
+            uint32_t reg_yy_dvp2ahb_lsel  : 1;  /* [   12],        r/w,        0x0 */
+            uint32_t reg_yy_dvp2ahb_fsel  : 1;  /* [   13],        r/w,        0x0 */
+            uint32_t reg_uv_dvp2ahb_lsel  : 1;  /* [   14],        r/w,        0x0 */
+            uint32_t reg_uv_dvp2ahb_fsel  : 1;  /* [   15],        r/w,        0x0 */
+            uint32_t reg_mjpeg_wait_cycle : 16; /* [31:16],        r/w,      0x400 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_control_2;
+
+    /* 0x08 : mjpeg_yy_frame_addr */
+    union {
+        struct
+        {
+            uint32_t reg_yy_addr_start : 32; /* [31: 0],        r/w, 0x80000000L */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_yy_frame_addr;
+
+    /* 0x0C : mjpeg_uv_frame_addr */
+    union {
+        struct
+        {
+            uint32_t reg_uv_addr_start : 32; /* [31: 0],        r/w, 0x80000000L */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_uv_frame_addr;
+
+    /* 0x10 : mjpeg_yuv_mem */
+    union {
+        struct
+        {
+            uint32_t reg_yy_mem_hblk : 13; /* [12: 0],        r/w,        0x2 */
+            uint32_t reserved_13_15  : 3;  /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_uv_mem_hblk : 13; /* [28:16],        r/w,        0x2 */
+            uint32_t reserved_29_31  : 3;  /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_yuv_mem;
+
+    /* 0x14 : jpeg_frame_addr */
+    union {
+        struct
+        {
+            uint32_t reg_w_addr_start : 32; /* [31: 0],        r/w, 0x80400000L */
+        } BF;
+        uint32_t WORD;
+    } jpeg_frame_addr;
+
+    /* 0x18 : jpeg_store_memory */
+    union {
+        struct
+        {
+            uint32_t reg_w_burst_cnt : 32; /* [31: 0],        r/w,     0x4000 */
+        } BF;
+        uint32_t WORD;
+    } jpeg_store_memory;
+
+    /* 0x1C : mjpeg_control_3 */
+    union {
+        struct
+        {
+            uint32_t reg_int_normal_en      : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_int_cam_en         : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_int_mem_en         : 1; /* [    2],        r/w,        0x0 */
+            uint32_t reg_int_frame_en       : 1; /* [    3],        r/w,        0x0 */
+            uint32_t sts_normal_int         : 1; /* [    4],          r,        0x0 */
+            uint32_t sts_cam_int            : 1; /* [    5],          r,        0x0 */
+            uint32_t sts_mem_int            : 1; /* [    6],          r,        0x0 */
+            uint32_t sts_frame_int          : 1; /* [    7],          r,        0x0 */
+            uint32_t mjpeg_idle             : 1; /* [    8],          r,        0x1 */
+            uint32_t mjpeg_func             : 1; /* [    9],          r,        0x0 */
+            uint32_t mjpeg_wait             : 1; /* [   10],          r,        0x0 */
+            uint32_t mjpeg_flsh             : 1; /* [   11],          r,        0x0 */
+            uint32_t mjpeg_mans             : 1; /* [   12],          r,        0x0 */
+            uint32_t mjpeg_manf             : 1; /* [   13],          r,        0x0 */
+            uint32_t ahb_idle               : 1; /* [   14],          r,        0x0 */
+            uint32_t reserved_15            : 1; /* [   15],       rsvd,        0x0 */
+            uint32_t reg_frame_cnt_trgr_int : 5; /* [20:16],        r/w,        0x0 */
+            uint32_t reg_int_idle_en        : 1; /* [   21],        r/w,        0x0 */
+            uint32_t sts_idle_int           : 1; /* [   22],          r,        0x0 */
+            uint32_t reserved_23            : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t frame_valid_cnt        : 5; /* [28:24],          r,        0x0 */
+            uint32_t reg_int_swap_en        : 1; /* [   29],        r/w,        0x0 */
+            uint32_t sts_swap_int           : 1; /* [   30],          r,        0x0 */
+            uint32_t reserved_31            : 1; /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_control_3;
+
+    /* 0x20 : mjpeg_frame_fifo_pop */
+    union {
+        struct
+        {
+            uint32_t rfifo_pop          : 1;  /* [    0],        w1p,        0x0 */
+            uint32_t reg_w_swap_clr     : 1;  /* [    1],        w1p,        0x0 */
+            uint32_t reserved_2_7       : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t reg_int_normal_clr : 1;  /* [    8],        w1p,        0x0 */
+            uint32_t reg_int_cam_clr    : 1;  /* [    9],        w1p,        0x0 */
+            uint32_t reg_int_mem_clr    : 1;  /* [   10],        w1p,        0x0 */
+            uint32_t reg_int_frame_clr  : 1;  /* [   11],        w1p,        0x0 */
+            uint32_t reg_int_idle_clr   : 1;  /* [   12],        w1p,        0x0 */
+            uint32_t reg_int_swap_clr   : 1;  /* [   13],        w1p,        0x0 */
+            uint32_t reserved_14_31     : 18; /* [31:14],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_frame_fifo_pop;
+
+    /* 0x24 : mjpeg_frame_size */
+    union {
+        struct
+        {
+            uint32_t reg_frame_wblk : 12; /* [11: 0],        r/w,        0xf */
+            uint32_t reserved_12_15 : 4;  /* [15:12],       rsvd,        0x0 */
+            uint32_t reg_frame_hblk : 12; /* [27:16],        r/w,       0x14 */
+            uint32_t reserved_28_31 : 4;  /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_frame_size;
+
+    /* 0x28 : mjpeg_header_byte */
+    union {
+        struct
+        {
+            uint32_t reg_head_byte  : 12; /* [11: 0],        r/w,        0x0 */
+            uint32_t reserved_12_15 : 4;  /* [15:12],       rsvd,        0x0 */
+            uint32_t reg_tail_exp   : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17_31 : 15; /* [31:17],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_header_byte;
+
+    /* 0x2c  reserved */
+    uint8_t RESERVED0x2c[4];
+
+    /* 0x30 : mjpeg_swap_mode */
+    union {
+        struct
+        {
+            uint32_t reg_w_swap_mode   : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_7      : 7;  /* [ 7: 1],       rsvd,        0x0 */
+            uint32_t sts_swap0_full    : 1;  /* [    8],          r,        0x0 */
+            uint32_t sts_swap1_full    : 1;  /* [    9],          r,        0x0 */
+            uint32_t sts_read_swap_idx : 1;  /* [   10],          r,        0x0 */
+            uint32_t sts_swap_fstart   : 1;  /* [   11],          r,        0x0 */
+            uint32_t sts_swap_fend     : 1;  /* [   12],          r,        0x0 */
+            uint32_t reserved_13_31    : 19; /* [31:13],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_swap_mode;
+
+    /* 0x34 : mjpeg_swap_bit_cnt */
+    union {
+        struct
+        {
+            uint32_t frame_swap_end_bit_cnt : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_swap_bit_cnt;
+
+    /* 0x38 : mjpeg_paket_ctrl */
+    union {
+        struct
+        {
+            uint32_t reg_pket_en        : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_jend_to_pend   : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_15      : 14; /* [15: 2],       rsvd,        0x0 */
+            uint32_t reg_pket_body_byte : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_paket_ctrl;
+
+    /* 0x3C : mjpeg_paket_head_tail */
+    union {
+        struct
+        {
+            uint32_t reg_pket_head_byte : 12; /* [11: 0],        r/w,        0x0 */
+            uint32_t reserved_12_15     : 4;  /* [15:12],       rsvd,        0x0 */
+            uint32_t reg_pket_tail_byte : 12; /* [27:16],        r/w,        0x0 */
+            uint32_t reserved_28_31     : 4;  /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_paket_head_tail;
+
+    /* 0x40 : mjpeg_Y_frame_read_status_1 */
+    union {
+        struct
+        {
+            uint32_t yy_mem_hblk_r  : 13; /* [12: 0],          r,        0x0 */
+            uint32_t reserved_13_15 : 3;  /* [15:13],       rsvd,        0x0 */
+            uint32_t yy_frm_hblk_r  : 13; /* [28:16],          r,        0x0 */
+            uint32_t reserved_29_31 : 3;  /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_Y_frame_read_status_1;
+
+    /* 0x44 : mjpeg_Y_frame_read_status_2 */
+    union {
+        struct
+        {
+            uint32_t yy_wblk_r      : 13; /* [12: 0],          r,        0x0 */
+            uint32_t reserved_13_15 : 3;  /* [15:13],       rsvd,        0x0 */
+            uint32_t yy_mem_rnd_r   : 8;  /* [23:16],          r,        0x0 */
+            uint32_t yy_frm_cnt_r   : 8;  /* [31:24],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_Y_frame_read_status_2;
+
+    /* 0x48 : mjpeg_Y_frame_write_status */
+    union {
+        struct
+        {
+            uint32_t yy_mem_hblk_w  : 13; /* [12: 0],          r,        0x0 */
+            uint32_t reserved_13_15 : 3;  /* [15:13],       rsvd,        0x0 */
+            uint32_t yy_mem_rnd_w   : 8;  /* [23:16],          r,        0x0 */
+            uint32_t yy_frm_cnt_w   : 8;  /* [31:24],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_Y_frame_write_status;
+
+    /* 0x4C : mjpeg_UV_frame_read_status_1 */
+    union {
+        struct
+        {
+            uint32_t uv_mem_hblk_r  : 13; /* [12: 0],          r,        0x0 */
+            uint32_t reserved_13_15 : 3;  /* [15:13],       rsvd,        0x0 */
+            uint32_t uv_frm_hblk_r  : 13; /* [28:16],          r,        0x0 */
+            uint32_t reserved_29_31 : 3;  /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_UV_frame_read_status_1;
+
+    /* 0x50 : mjpeg_UV_frame_read_status_2 */
+    union {
+        struct
+        {
+            uint32_t uv_wblk_r      : 13; /* [12: 0],          r,        0x0 */
+            uint32_t reserved_13_15 : 3;  /* [15:13],       rsvd,        0x0 */
+            uint32_t uv_mem_rnd_r   : 8;  /* [23:16],          r,        0x0 */
+            uint32_t uv_frm_cnt_r   : 8;  /* [31:24],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_UV_frame_read_status_2;
+
+    /* 0x54 : mjpeg_UV_frame_write_status */
+    union {
+        struct
+        {
+            uint32_t uv_mem_hblk_w  : 13; /* [12: 0],          r,        0x0 */
+            uint32_t reserved_13_15 : 3;  /* [15:13],       rsvd,        0x0 */
+            uint32_t uv_mem_rnd_w   : 8;  /* [23:16],          r,        0x0 */
+            uint32_t uv_frm_cnt_w   : 8;  /* [31:24],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_UV_frame_write_status;
+
+    /* 0x58  reserved */
+    uint8_t RESERVED0x58[40];
+
+    /* 0x80 : mjpeg_start_addr0 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_start_addr0;
+
+    /* 0x84 : mjpeg_bit_cnt0 */
+    union {
+        struct
+        {
+            uint32_t frame_bit_cnt_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_bit_cnt0;
+
+    /* 0x88 : mjpeg_start_addr1 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_1 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_start_addr1;
+
+    /* 0x8C : mjpeg_bit_cnt1 */
+    union {
+        struct
+        {
+            uint32_t frame_bit_cnt_1 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_bit_cnt1;
+
+    /* 0x90 : mjpeg_start_addr2 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_2 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_start_addr2;
+
+    /* 0x94 : mjpeg_bit_cnt2 */
+    union {
+        struct
+        {
+            uint32_t frame_bit_cnt_2 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_bit_cnt2;
+
+    /* 0x98 : mjpeg_start_addr3 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_3 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_start_addr3;
+
+    /* 0x9C : mjpeg_bit_cnt3 */
+    union {
+        struct
+        {
+            uint32_t frame_bit_cnt_3 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_bit_cnt3;
+
+    /* 0xA0 : mjpeg_start_addr4 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_4 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_start_addr4;
+
+    /* 0xA4 : mjpeg_bit_cnt4 */
+    union {
+        struct
+        {
+            uint32_t frame_bit_cnt_4 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_bit_cnt4;
+
+    /* 0xA8 : mjpeg_start_addr5 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_5 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_start_addr5;
+
+    /* 0xAC : mjpeg_bit_cnt5 */
+    union {
+        struct
+        {
+            uint32_t frame_bit_cnt_5 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_bit_cnt5;
+
+    /* 0xB0 : mjpeg_start_addr6 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_6 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_start_addr6;
+
+    /* 0xB4 : mjpeg_bit_cnt6 */
+    union {
+        struct
+        {
+            uint32_t frame_bit_cnt_6 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_bit_cnt6;
+
+    /* 0xB8 : mjpeg_start_addr7 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_7 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_start_addr7;
+
+    /* 0xBC : mjpeg_bit_cnt7 */
+    union {
+        struct
+        {
+            uint32_t frame_bit_cnt_7 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_bit_cnt7;
+
+    /* 0xC0 : mjpeg_start_addr_8 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_8 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_start_addr_8;
+
+    /* 0xC4 : mjpeg_bit_cnt_8 */
+    union {
+        struct
+        {
+            uint32_t frame_bit_cnt_8 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_bit_cnt_8;
+
+    /* 0xC8 : mjpeg_start_addr_9 */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_9 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_start_addr_9;
+
+    /* 0xCC : mjpeg_bit_cnt_9 */
+    union {
+        struct
+        {
+            uint32_t frame_bit_cnt_9 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_bit_cnt_9;
+
+    /* 0xD0 : mjpeg_start_addr_a */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_a : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_start_addr_a;
+
+    /* 0xD4 : mjpeg_bit_cnt_a */
+    union {
+        struct
+        {
+            uint32_t frame_bit_cnt_a : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_bit_cnt_a;
+
+    /* 0xD8 : mjpeg_start_addr_b */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_b : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_start_addr_b;
+
+    /* 0xDC : mjpeg_bit_cnt_b */
+    union {
+        struct
+        {
+            uint32_t frame_bit_cnt_b : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_bit_cnt_b;
+
+    /* 0xE0 : mjpeg_start_addr_c */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_c : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_start_addr_c;
+
+    /* 0xE4 : mjpeg_bit_cnt_c */
+    union {
+        struct
+        {
+            uint32_t frame_bit_cnt_c : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_bit_cnt_c;
+
+    /* 0xE8 : mjpeg_start_addr_d */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_d : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_start_addr_d;
+
+    /* 0xEC : mjpeg_bit_cnt_d */
+    union {
+        struct
+        {
+            uint32_t frame_bit_cnt_d : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_bit_cnt_d;
+
+    /* 0xF0 : mjpeg_start_addr_e */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_e : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_start_addr_e;
+
+    /* 0xF4 : mjpeg_bit_cnt_e */
+    union {
+        struct
+        {
+            uint32_t frame_bit_cnt_e : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_bit_cnt_e;
+
+    /* 0xF8 : mjpeg_start_addr_f */
+    union {
+        struct
+        {
+            uint32_t frame_start_addr_f : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_start_addr_f;
+
+    /* 0xFC : mjpeg_bit_cnt_f */
+    union {
+        struct
+        {
+            uint32_t frame_bit_cnt_f : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_bit_cnt_f;
+
+    /* 0x100 : mjpeg_q_mode0 */
+    union {
+        struct
+        {
+            uint32_t frame_q_mode_0 : 7;  /* [ 6: 0],          r,        0x0 */
+            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_q_mode0;
+
+    /* 0x104 : mjpeg_q_mode1 */
+    union {
+        struct
+        {
+            uint32_t frame_q_mode_1 : 7;  /* [ 6: 0],          r,        0x0 */
+            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_q_mode1;
+
+    /* 0x108 : mjpeg_q_mode2 */
+    union {
+        struct
+        {
+            uint32_t frame_q_mode_2 : 7;  /* [ 6: 0],          r,        0x0 */
+            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_q_mode2;
+
+    /* 0x10C : mjpeg_q_mode3 */
+    union {
+        struct
+        {
+            uint32_t frame_q_mode_3 : 7;  /* [ 6: 0],          r,        0x0 */
+            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_q_mode3;
+
+    /* 0x110 : mjpeg_q_mode4 */
+    union {
+        struct
+        {
+            uint32_t frame_q_mode_4 : 7;  /* [ 6: 0],          r,        0x0 */
+            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_q_mode4;
+
+    /* 0x114 : mjpeg_q_mode5 */
+    union {
+        struct
+        {
+            uint32_t frame_q_mode_5 : 7;  /* [ 6: 0],          r,        0x0 */
+            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_q_mode5;
+
+    /* 0x118 : mjpeg_q_mode6 */
+    union {
+        struct
+        {
+            uint32_t frame_q_mode_6 : 7;  /* [ 6: 0],          r,        0x0 */
+            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_q_mode6;
+
+    /* 0x11C : mjpeg_q_mode7 */
+    union {
+        struct
+        {
+            uint32_t frame_q_mode_7 : 7;  /* [ 6: 0],          r,        0x0 */
+            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_q_mode7;
+
+    /* 0x120 : mjpeg_q_mode_8 */
+    union {
+        struct
+        {
+            uint32_t frame_q_mode_8 : 7;  /* [ 6: 0],          r,        0x0 */
+            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_q_mode_8;
+
+    /* 0x124 : mjpeg_q_mode_9 */
+    union {
+        struct
+        {
+            uint32_t frame_q_mode_9 : 7;  /* [ 6: 0],          r,        0x0 */
+            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_q_mode_9;
+
+    /* 0x128 : mjpeg_q_mode_a */
+    union {
+        struct
+        {
+            uint32_t frame_q_mode_a : 7;  /* [ 6: 0],          r,        0x0 */
+            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_q_mode_a;
+
+    /* 0x12C : mjpeg_q_mode_b */
+    union {
+        struct
+        {
+            uint32_t frame_q_mode_b : 7;  /* [ 6: 0],          r,        0x0 */
+            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_q_mode_b;
+
+    /* 0x130 : mjpeg_q_mode_c */
+    union {
+        struct
+        {
+            uint32_t frame_q_mode_c : 7;  /* [ 6: 0],          r,        0x0 */
+            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_q_mode_c;
+
+    /* 0x134 : mjpeg_q_mode_d */
+    union {
+        struct
+        {
+            uint32_t frame_q_mode_d : 7;  /* [ 6: 0],          r,        0x0 */
+            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_q_mode_d;
+
+    /* 0x138 : mjpeg_q_mode_e */
+    union {
+        struct
+        {
+            uint32_t frame_q_mode_e : 7;  /* [ 6: 0],          r,        0x0 */
+            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_q_mode_e;
+
+    /* 0x13C : mjpeg_q_mode_f */
+    union {
+        struct
+        {
+            uint32_t frame_q_mode_f : 7;  /* [ 6: 0],          r,        0x0 */
+            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_q_mode_f;
+
+    /* 0x140  reserved */
+    uint8_t RESERVED0x140[176];
+
+    /* 0x1F0 : mjpeg_debug */
+    union {
+        struct
+        {
+            uint32_t reg_mjpeg_dbg_en  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3      : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t reg_mjpeg_dbg_sel : 4;  /* [ 7: 4],        r/w,        0x0 */
+            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_debug;
+
+    /* 0x1f4  reserved */
+    uint8_t RESERVED0x1f4[8];
+
+    /* 0x1FC : mjpeg_dummy_reg */
+    union {
+        struct
+        {
+            uint32_t mjpeg_dummy_reg : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mjpeg_dummy_reg;
+};
+
+typedef volatile struct mjpeg_reg mjpeg_reg_t;
+
+#endif /* __MJPEG_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/pdm_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/pdm_reg.h
new file mode 100644
index 00000000..1da8106f
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/pdm_reg.h
@@ -0,0 +1,351 @@
+/**
+  ******************************************************************************
+  * @file    pdm_reg.h
+  * @version V1.2
+  * @date    2020-02-13
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __PDM_REG_H__
+#define __PDM_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : pdm_datapath_config */
+#define PDM_DATAPATH_CONFIG_OFFSET (0x0)
+#define PDM_EN                     PDM_EN
+#define PDM_EN_POS                 (0U)
+#define PDM_EN_LEN                 (1U)
+#define PDM_EN_MSK                 (((1U << PDM_EN_LEN) - 1) << PDM_EN_POS)
+#define PDM_EN_UMSK                (~(((1U << PDM_EN_LEN) - 1) << PDM_EN_POS))
+#define PDM_RX_SEL_128FS           PDM_RX_SEL_128FS
+#define PDM_RX_SEL_128FS_POS       (2U)
+#define PDM_RX_SEL_128FS_LEN       (1U)
+#define PDM_RX_SEL_128FS_MSK       (((1U << PDM_RX_SEL_128FS_LEN) - 1) << PDM_RX_SEL_128FS_POS)
+#define PDM_RX_SEL_128FS_UMSK      (~(((1U << PDM_RX_SEL_128FS_LEN) - 1) << PDM_RX_SEL_128FS_POS))
+#define PDM_TX_SEL_128FS           PDM_TX_SEL_128FS
+#define PDM_TX_SEL_128FS_POS       (3U)
+#define PDM_TX_SEL_128FS_LEN       (1U)
+#define PDM_TX_SEL_128FS_MSK       (((1U << PDM_TX_SEL_128FS_LEN) - 1) << PDM_TX_SEL_128FS_POS)
+#define PDM_TX_SEL_128FS_UMSK      (~(((1U << PDM_TX_SEL_128FS_LEN) - 1) << PDM_TX_SEL_128FS_POS))
+#define PDM_DC_MUL                 PDM_DC_MUL
+#define PDM_DC_MUL_POS             (4U)
+#define PDM_DC_MUL_LEN             (8U)
+#define PDM_DC_MUL_MSK             (((1U << PDM_DC_MUL_LEN) - 1) << PDM_DC_MUL_POS)
+#define PDM_DC_MUL_UMSK            (~(((1U << PDM_DC_MUL_LEN) - 1) << PDM_DC_MUL_POS))
+#define PDM_SCALE_SEL              PDM_SCALE_SEL
+#define PDM_SCALE_SEL_POS          (12U)
+#define PDM_SCALE_SEL_LEN          (3U)
+#define PDM_SCALE_SEL_MSK          (((1U << PDM_SCALE_SEL_LEN) - 1) << PDM_SCALE_SEL_POS)
+#define PDM_SCALE_SEL_UMSK         (~(((1U << PDM_SCALE_SEL_LEN) - 1) << PDM_SCALE_SEL_POS))
+#define PDM_DITHER_SEL             PDM_DITHER_SEL
+#define PDM_DITHER_SEL_POS         (16U)
+#define PDM_DITHER_SEL_LEN         (2U)
+#define PDM_DITHER_SEL_MSK         (((1U << PDM_DITHER_SEL_LEN) - 1) << PDM_DITHER_SEL_POS)
+#define PDM_DITHER_SEL_UMSK        (~(((1U << PDM_DITHER_SEL_LEN) - 1) << PDM_DITHER_SEL_POS))
+#define PDM_FORCE_LR               PDM_FORCE_LR
+#define PDM_FORCE_LR_POS           (20U)
+#define PDM_FORCE_LR_LEN           (1U)
+#define PDM_FORCE_LR_MSK           (((1U << PDM_FORCE_LR_LEN) - 1) << PDM_FORCE_LR_POS)
+#define PDM_FORCE_LR_UMSK          (~(((1U << PDM_FORCE_LR_LEN) - 1) << PDM_FORCE_LR_POS))
+#define PDM_FORCE_SEL              PDM_FORCE_SEL
+#define PDM_FORCE_SEL_POS          (21U)
+#define PDM_FORCE_SEL_LEN          (1U)
+#define PDM_FORCE_SEL_MSK          (((1U << PDM_FORCE_SEL_LEN) - 1) << PDM_FORCE_SEL_POS)
+#define PDM_FORCE_SEL_UMSK         (~(((1U << PDM_FORCE_SEL_LEN) - 1) << PDM_FORCE_SEL_POS))
+#define PDM_DSD_SWAP               PDM_DSD_SWAP
+#define PDM_DSD_SWAP_POS           (22U)
+#define PDM_DSD_SWAP_LEN           (1U)
+#define PDM_DSD_SWAP_MSK           (((1U << PDM_DSD_SWAP_LEN) - 1) << PDM_DSD_SWAP_POS)
+#define PDM_DSD_SWAP_UMSK          (~(((1U << PDM_DSD_SWAP_LEN) - 1) << PDM_DSD_SWAP_POS))
+#define PDM_OUT_DAT_DLY            PDM_OUT_DAT_DLY
+#define PDM_OUT_DAT_DLY_POS        (24U)
+#define PDM_OUT_DAT_DLY_LEN        (2U)
+#define PDM_OUT_DAT_DLY_MSK        (((1U << PDM_OUT_DAT_DLY_LEN) - 1) << PDM_OUT_DAT_DLY_POS)
+#define PDM_OUT_DAT_DLY_UMSK       (~(((1U << PDM_OUT_DAT_DLY_LEN) - 1) << PDM_OUT_DAT_DLY_POS))
+#define PDM_OUT_SEL_DLY            PDM_OUT_SEL_DLY
+#define PDM_OUT_SEL_DLY_POS        (26U)
+#define PDM_OUT_SEL_DLY_LEN        (2U)
+#define PDM_OUT_SEL_DLY_MSK        (((1U << PDM_OUT_SEL_DLY_LEN) - 1) << PDM_OUT_SEL_DLY_POS)
+#define PDM_OUT_SEL_DLY_UMSK       (~(((1U << PDM_OUT_SEL_DLY_LEN) - 1) << PDM_OUT_SEL_DLY_POS))
+#define PDM_OUT_SEL_INV            PDM_OUT_SEL_INV
+#define PDM_OUT_SEL_INV_POS        (28U)
+#define PDM_OUT_SEL_INV_LEN        (1U)
+#define PDM_OUT_SEL_INV_MSK        (((1U << PDM_OUT_SEL_INV_LEN) - 1) << PDM_OUT_SEL_INV_POS)
+#define PDM_OUT_SEL_INV_UMSK       (~(((1U << PDM_OUT_SEL_INV_LEN) - 1) << PDM_OUT_SEL_INV_POS))
+
+/* 0x4 : pdm_dma_config */
+#define PDM_DMA_CONFIG_OFFSET  (0x4)
+#define PDM_DMA_RX_EN          PDM_DMA_RX_EN
+#define PDM_DMA_RX_EN_POS      (0U)
+#define PDM_DMA_RX_EN_LEN      (1U)
+#define PDM_DMA_RX_EN_MSK      (((1U << PDM_DMA_RX_EN_LEN) - 1) << PDM_DMA_RX_EN_POS)
+#define PDM_DMA_RX_EN_UMSK     (~(((1U << PDM_DMA_RX_EN_LEN) - 1) << PDM_DMA_RX_EN_POS))
+#define PDM_RX_FORMAT          PDM_RX_FORMAT
+#define PDM_RX_FORMAT_POS      (4U)
+#define PDM_RX_FORMAT_LEN      (3U)
+#define PDM_RX_FORMAT_MSK      (((1U << PDM_RX_FORMAT_LEN) - 1) << PDM_RX_FORMAT_POS)
+#define PDM_RX_FORMAT_UMSK     (~(((1U << PDM_RX_FORMAT_LEN) - 1) << PDM_RX_FORMAT_POS))
+#define PDM_DMA_TX_EN          PDM_DMA_TX_EN
+#define PDM_DMA_TX_EN_POS      (8U)
+#define PDM_DMA_TX_EN_LEN      (1U)
+#define PDM_DMA_TX_EN_MSK      (((1U << PDM_DMA_TX_EN_LEN) - 1) << PDM_DMA_TX_EN_POS)
+#define PDM_DMA_TX_EN_UMSK     (~(((1U << PDM_DMA_TX_EN_LEN) - 1) << PDM_DMA_TX_EN_POS))
+#define PDM_TX_FORMAT          PDM_TX_FORMAT
+#define PDM_TX_FORMAT_POS      (12U)
+#define PDM_TX_FORMAT_LEN      (3U)
+#define PDM_TX_FORMAT_MSK      (((1U << PDM_TX_FORMAT_LEN) - 1) << PDM_TX_FORMAT_POS)
+#define PDM_TX_FORMAT_UMSK     (~(((1U << PDM_TX_FORMAT_LEN) - 1) << PDM_TX_FORMAT_POS))
+#define PDM_TX_DATA_SHIFT      PDM_TX_DATA_SHIFT
+#define PDM_TX_DATA_SHIFT_POS  (16U)
+#define PDM_TX_DATA_SHIFT_LEN  (5U)
+#define PDM_TX_DATA_SHIFT_MSK  (((1U << PDM_TX_DATA_SHIFT_LEN) - 1) << PDM_TX_DATA_SHIFT_POS)
+#define PDM_TX_DATA_SHIFT_UMSK (~(((1U << PDM_TX_DATA_SHIFT_LEN) - 1) << PDM_TX_DATA_SHIFT_POS))
+
+/* 0x8 : pdm_dma_wdata2 */
+#define PDM_DMA_WDATA2_OFFSET (0x8)
+#define PDM_DMA_WDATA2        PDM_DMA_WDATA2
+#define PDM_DMA_WDATA2_POS    (0U)
+#define PDM_DMA_WDATA2_LEN    (32U)
+#define PDM_DMA_WDATA2_MSK    (((1U << PDM_DMA_WDATA2_LEN) - 1) << PDM_DMA_WDATA2_POS)
+#define PDM_DMA_WDATA2_UMSK   (~(((1U << PDM_DMA_WDATA2_LEN) - 1) << PDM_DMA_WDATA2_POS))
+
+/* 0x10 : pdm_dma_wdata */
+#define PDM_DMA_WDATA_OFFSET (0x10)
+#define PDM_DMA_WDATA        PDM_DMA_WDATA
+#define PDM_DMA_WDATA_POS    (0U)
+#define PDM_DMA_WDATA_LEN    (32U)
+#define PDM_DMA_WDATA_MSK    (((1U << PDM_DMA_WDATA_LEN) - 1) << PDM_DMA_WDATA_POS)
+#define PDM_DMA_WDATA_UMSK   (~(((1U << PDM_DMA_WDATA_LEN) - 1) << PDM_DMA_WDATA_POS))
+
+/* 0x14 : pdm_dma_rdata */
+#define PDM_DMA_RDATA_OFFSET (0x14)
+#define PDM_DMA_RDATA        PDM_DMA_RDATA
+#define PDM_DMA_RDATA_POS    (0U)
+#define PDM_DMA_RDATA_LEN    (32U)
+#define PDM_DMA_RDATA_MSK    (((1U << PDM_DMA_RDATA_LEN) - 1) << PDM_DMA_RDATA_POS)
+#define PDM_DMA_RDATA_UMSK   (~(((1U << PDM_DMA_RDATA_LEN) - 1) << PDM_DMA_RDATA_POS))
+
+/* 0x18 : pdm_tx_fifo_status */
+#define PDM_TX_FIFO_STATUS_OFFSET (0x18)
+#define PDM_TX_FIFO_EMPTY         PDM_TX_FIFO_EMPTY
+#define PDM_TX_FIFO_EMPTY_POS     (0U)
+#define PDM_TX_FIFO_EMPTY_LEN     (1U)
+#define PDM_TX_FIFO_EMPTY_MSK     (((1U << PDM_TX_FIFO_EMPTY_LEN) - 1) << PDM_TX_FIFO_EMPTY_POS)
+#define PDM_TX_FIFO_EMPTY_UMSK    (~(((1U << PDM_TX_FIFO_EMPTY_LEN) - 1) << PDM_TX_FIFO_EMPTY_POS))
+#define PDM_TX_FIFO_FULL          PDM_TX_FIFO_FULL
+#define PDM_TX_FIFO_FULL_POS      (1U)
+#define PDM_TX_FIFO_FULL_LEN      (1U)
+#define PDM_TX_FIFO_FULL_MSK      (((1U << PDM_TX_FIFO_FULL_LEN) - 1) << PDM_TX_FIFO_FULL_POS)
+#define PDM_TX_FIFO_FULL_UMSK     (~(((1U << PDM_TX_FIFO_FULL_LEN) - 1) << PDM_TX_FIFO_FULL_POS))
+#define PDM_TX_CS                 PDM_TX_CS
+#define PDM_TX_CS_POS             (2U)
+#define PDM_TX_CS_LEN             (2U)
+#define PDM_TX_CS_MSK             (((1U << PDM_TX_CS_LEN) - 1) << PDM_TX_CS_POS)
+#define PDM_TX_CS_UMSK            (~(((1U << PDM_TX_CS_LEN) - 1) << PDM_TX_CS_POS))
+#define PDM_TXFIFORDPTR           PDM_TXFIFORDPTR
+#define PDM_TXFIFORDPTR_POS       (4U)
+#define PDM_TXFIFORDPTR_LEN       (3U)
+#define PDM_TXFIFORDPTR_MSK       (((1U << PDM_TXFIFORDPTR_LEN) - 1) << PDM_TXFIFORDPTR_POS)
+#define PDM_TXFIFORDPTR_UMSK      (~(((1U << PDM_TXFIFORDPTR_LEN) - 1) << PDM_TXFIFORDPTR_POS))
+#define PDM_TXFIFOWRPTR           PDM_TXFIFOWRPTR
+#define PDM_TXFIFOWRPTR_POS       (8U)
+#define PDM_TXFIFOWRPTR_LEN       (2U)
+#define PDM_TXFIFOWRPTR_MSK       (((1U << PDM_TXFIFOWRPTR_LEN) - 1) << PDM_TXFIFOWRPTR_POS)
+#define PDM_TXFIFOWRPTR_UMSK      (~(((1U << PDM_TXFIFOWRPTR_LEN) - 1) << PDM_TXFIFOWRPTR_POS))
+#define PDM_TX2_FIFO_EMPTY        PDM_TX2_FIFO_EMPTY
+#define PDM_TX2_FIFO_EMPTY_POS    (16U)
+#define PDM_TX2_FIFO_EMPTY_LEN    (1U)
+#define PDM_TX2_FIFO_EMPTY_MSK    (((1U << PDM_TX2_FIFO_EMPTY_LEN) - 1) << PDM_TX2_FIFO_EMPTY_POS)
+#define PDM_TX2_FIFO_EMPTY_UMSK   (~(((1U << PDM_TX2_FIFO_EMPTY_LEN) - 1) << PDM_TX2_FIFO_EMPTY_POS))
+#define PDM_TX2_FIFO_FULL         PDM_TX2_FIFO_FULL
+#define PDM_TX2_FIFO_FULL_POS     (17U)
+#define PDM_TX2_FIFO_FULL_LEN     (1U)
+#define PDM_TX2_FIFO_FULL_MSK     (((1U << PDM_TX2_FIFO_FULL_LEN) - 1) << PDM_TX2_FIFO_FULL_POS)
+#define PDM_TX2_FIFO_FULL_UMSK    (~(((1U << PDM_TX2_FIFO_FULL_LEN) - 1) << PDM_TX2_FIFO_FULL_POS))
+#define PDM_TX2_CS                PDM_TX2_CS
+#define PDM_TX2_CS_POS            (18U)
+#define PDM_TX2_CS_LEN            (2U)
+#define PDM_TX2_CS_MSK            (((1U << PDM_TX2_CS_LEN) - 1) << PDM_TX2_CS_POS)
+#define PDM_TX2_CS_UMSK           (~(((1U << PDM_TX2_CS_LEN) - 1) << PDM_TX2_CS_POS))
+#define PDM_TX2FIFORDPTR          PDM_TX2FIFORDPTR
+#define PDM_TX2FIFORDPTR_POS      (20U)
+#define PDM_TX2FIFORDPTR_LEN      (3U)
+#define PDM_TX2FIFORDPTR_MSK      (((1U << PDM_TX2FIFORDPTR_LEN) - 1) << PDM_TX2FIFORDPTR_POS)
+#define PDM_TX2FIFORDPTR_UMSK     (~(((1U << PDM_TX2FIFORDPTR_LEN) - 1) << PDM_TX2FIFORDPTR_POS))
+#define PDM_TX2FIFOWRPTR          PDM_TX2FIFOWRPTR
+#define PDM_TX2FIFOWRPTR_POS      (24U)
+#define PDM_TX2FIFOWRPTR_LEN      (2U)
+#define PDM_TX2FIFOWRPTR_MSK      (((1U << PDM_TX2FIFOWRPTR_LEN) - 1) << PDM_TX2FIFOWRPTR_POS)
+#define PDM_TX2FIFOWRPTR_UMSK     (~(((1U << PDM_TX2FIFOWRPTR_LEN) - 1) << PDM_TX2FIFOWRPTR_POS))
+
+/* 0x1C : pdm_rx_fifo_status */
+#define PDM_RX_FIFO_STATUS_OFFSET (0x1C)
+#define PDM_RX_FIFO_EMPTY         PDM_RX_FIFO_EMPTY
+#define PDM_RX_FIFO_EMPTY_POS     (0U)
+#define PDM_RX_FIFO_EMPTY_LEN     (1U)
+#define PDM_RX_FIFO_EMPTY_MSK     (((1U << PDM_RX_FIFO_EMPTY_LEN) - 1) << PDM_RX_FIFO_EMPTY_POS)
+#define PDM_RX_FIFO_EMPTY_UMSK    (~(((1U << PDM_RX_FIFO_EMPTY_LEN) - 1) << PDM_RX_FIFO_EMPTY_POS))
+#define PDM_RX_FIFO_FULL          PDM_RX_FIFO_FULL
+#define PDM_RX_FIFO_FULL_POS      (1U)
+#define PDM_RX_FIFO_FULL_LEN      (1U)
+#define PDM_RX_FIFO_FULL_MSK      (((1U << PDM_RX_FIFO_FULL_LEN) - 1) << PDM_RX_FIFO_FULL_POS)
+#define PDM_RX_FIFO_FULL_UMSK     (~(((1U << PDM_RX_FIFO_FULL_LEN) - 1) << PDM_RX_FIFO_FULL_POS))
+#define PDM_RX_CS                 PDM_RX_CS
+#define PDM_RX_CS_POS             (2U)
+#define PDM_RX_CS_LEN             (2U)
+#define PDM_RX_CS_MSK             (((1U << PDM_RX_CS_LEN) - 1) << PDM_RX_CS_POS)
+#define PDM_RX_CS_UMSK            (~(((1U << PDM_RX_CS_LEN) - 1) << PDM_RX_CS_POS))
+#define PDM_RXFIFORDPTR           PDM_RXFIFORDPTR
+#define PDM_RXFIFORDPTR_POS       (4U)
+#define PDM_RXFIFORDPTR_LEN       (2U)
+#define PDM_RXFIFORDPTR_MSK       (((1U << PDM_RXFIFORDPTR_LEN) - 1) << PDM_RXFIFORDPTR_POS)
+#define PDM_RXFIFORDPTR_UMSK      (~(((1U << PDM_RXFIFORDPTR_LEN) - 1) << PDM_RXFIFORDPTR_POS))
+#define PDM_RXFIFOWRPTR           PDM_RXFIFOWRPTR
+#define PDM_RXFIFOWRPTR_POS       (8U)
+#define PDM_RXFIFOWRPTR_LEN       (3U)
+#define PDM_RXFIFOWRPTR_MSK       (((1U << PDM_RXFIFOWRPTR_LEN) - 1) << PDM_RXFIFOWRPTR_POS)
+#define PDM_RXFIFOWRPTR_UMSK      (~(((1U << PDM_RXFIFOWRPTR_LEN) - 1) << PDM_RXFIFOWRPTR_POS))
+
+struct pdm_reg {
+    /* 0x0 : pdm_datapath_config */
+    union {
+        struct
+        {
+            uint32_t pdm_en         : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1     : 1; /* [    1],       rsvd,        0x0 */
+            uint32_t rx_sel_128fs   : 1; /* [    2],        r/w,        0x0 */
+            uint32_t tx_sel_128fs   : 1; /* [    3],        r/w,        0x0 */
+            uint32_t dc_mul         : 8; /* [11: 4],        r/w,       0x64 */
+            uint32_t scale_sel      : 3; /* [14:12],        r/w,        0x5 */
+            uint32_t reserved_15    : 1; /* [   15],       rsvd,        0x0 */
+            uint32_t dither_sel     : 2; /* [17:16],        r/w,        0x1 */
+            uint32_t reserved_18_19 : 2; /* [19:18],       rsvd,        0x0 */
+            uint32_t force_lr       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t force_sel      : 1; /* [   21],        r/w,        0x0 */
+            uint32_t dsd_swap       : 1; /* [   22],        r/w,        0x0 */
+            uint32_t reserved_23    : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t out_dat_dly    : 2; /* [25:24],        r/w,        0x0 */
+            uint32_t out_sel_dly    : 2; /* [27:26],        r/w,        0x0 */
+            uint32_t out_sel_inv    : 1; /* [   28],        r/w,        0x0 */
+            uint32_t rsvd_31_29     : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pdm_datapath_config;
+
+    /* 0x4 : pdm_dma_config */
+    union {
+        struct
+        {
+            uint32_t pdm_dma_rx_en  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3   : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t rx_format      : 3;  /* [ 6: 4],        r/w,        0x3 */
+            uint32_t reserved_7     : 1;  /* [    7],       rsvd,        0x0 */
+            uint32_t pdm_dma_tx_en  : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9_11  : 3;  /* [11: 9],       rsvd,        0x0 */
+            uint32_t tx_format      : 3;  /* [14:12],        r/w,        0x3 */
+            uint32_t reserved_15    : 1;  /* [   15],       rsvd,        0x0 */
+            uint32_t tx_data_shift  : 5;  /* [20:16],        r/w,        0x0 */
+            uint32_t reserved_21_31 : 11; /* [31:21],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pdm_dma_config;
+
+    /* 0x8 : pdm_dma_wdata2 */
+    union {
+        struct
+        {
+            uint32_t pdm_dma_wdata2 : 32; /* [31: 0],          w,          x */
+        } BF;
+        uint32_t WORD;
+    } pdm_dma_wdata2;
+
+    /* 0xc  reserved */
+    uint8_t RESERVED0xc[4];
+
+    /* 0x10 : pdm_dma_wdata */
+    union {
+        struct
+        {
+            uint32_t pdm_dma_wdata : 32; /* [31: 0],          w,          x */
+        } BF;
+        uint32_t WORD;
+    } pdm_dma_wdata;
+
+    /* 0x14 : pdm_dma_rdata */
+    union {
+        struct
+        {
+            uint32_t pdm_dma_rdata : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pdm_dma_rdata;
+
+    /* 0x18 : pdm_tx_fifo_status */
+    union {
+        struct
+        {
+            uint32_t tx_fifo_empty  : 1; /* [    0],          r,        0x0 */
+            uint32_t tx_fifo_full   : 1; /* [    1],          r,        0x0 */
+            uint32_t tx_cs          : 2; /* [ 3: 2],          r,        0x0 */
+            uint32_t TxFifoRdPtr    : 3; /* [ 6: 4],          r,        0x4 */
+            uint32_t reserved_7     : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t TxFifoWrPtr    : 2; /* [ 9: 8],          r,        0x0 */
+            uint32_t reserved_10_15 : 6; /* [15:10],       rsvd,        0x0 */
+            uint32_t tx2_fifo_empty : 1; /* [   16],          r,        0x0 */
+            uint32_t tx2_fifo_full  : 1; /* [   17],          r,        0x0 */
+            uint32_t tx2_cs         : 2; /* [19:18],          r,        0x0 */
+            uint32_t Tx2FifoRdPtr   : 3; /* [22:20],          r,        0x4 */
+            uint32_t reserved_23    : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t Tx2FifoWrPtr   : 2; /* [25:24],          r,        0x0 */
+            uint32_t reserved_26_31 : 6; /* [31:26],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pdm_tx_fifo_status;
+
+    /* 0x1C : pdm_rx_fifo_status */
+    union {
+        struct
+        {
+            uint32_t rx_fifo_empty  : 1;  /* [    0],          r,        0x1 */
+            uint32_t rx_fifo_full   : 1;  /* [    1],          r,        0x0 */
+            uint32_t rx_cs          : 2;  /* [ 3: 2],          r,        0x0 */
+            uint32_t RxFifoRdPtr    : 2;  /* [ 5: 4],          r,        0x3 */
+            uint32_t reserved_6_7   : 2;  /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t RxFifoWrPtr    : 3;  /* [10: 8],          r,        0x0 */
+            uint32_t reserved_11_31 : 21; /* [31:11],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pdm_rx_fifo_status;
+};
+
+typedef volatile struct pdm_reg pdm_reg_t;
+
+#endif /* __PDM_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/pds_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/pds_reg.h
new file mode 100644
index 00000000..9b2a0d62
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/pds_reg.h
@@ -0,0 +1,1411 @@
+/**
+  ******************************************************************************
+  * @file    pds_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __PDS_REG_H__
+#define __PDS_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : PDS_CTL */
+#define PDS_CTL_OFFSET                     (0x0)
+#define PDS_START_PS                       PDS_START_PS
+#define PDS_START_PS_POS                   (0U)
+#define PDS_START_PS_LEN                   (1U)
+#define PDS_START_PS_MSK                   (((1U << PDS_START_PS_LEN) - 1) << PDS_START_PS_POS)
+#define PDS_START_PS_UMSK                  (~(((1U << PDS_START_PS_LEN) - 1) << PDS_START_PS_POS))
+#define PDS_CR_SLEEP_FOREVER               PDS_CR_SLEEP_FOREVER
+#define PDS_CR_SLEEP_FOREVER_POS           (1U)
+#define PDS_CR_SLEEP_FOREVER_LEN           (1U)
+#define PDS_CR_SLEEP_FOREVER_MSK           (((1U << PDS_CR_SLEEP_FOREVER_LEN) - 1) << PDS_CR_SLEEP_FOREVER_POS)
+#define PDS_CR_SLEEP_FOREVER_UMSK          (~(((1U << PDS_CR_SLEEP_FOREVER_LEN) - 1) << PDS_CR_SLEEP_FOREVER_POS))
+#define PDS_CR_XTAL_FORCE_OFF              PDS_CR_XTAL_FORCE_OFF
+#define PDS_CR_XTAL_FORCE_OFF_POS          (2U)
+#define PDS_CR_XTAL_FORCE_OFF_LEN          (1U)
+#define PDS_CR_XTAL_FORCE_OFF_MSK          (((1U << PDS_CR_XTAL_FORCE_OFF_LEN) - 1) << PDS_CR_XTAL_FORCE_OFF_POS)
+#define PDS_CR_XTAL_FORCE_OFF_UMSK         (~(((1U << PDS_CR_XTAL_FORCE_OFF_LEN) - 1) << PDS_CR_XTAL_FORCE_OFF_POS))
+#define PDS_CR_WIFI_PDS_SAVE_STATE         PDS_CR_WIFI_PDS_SAVE_STATE
+#define PDS_CR_WIFI_PDS_SAVE_STATE_POS     (3U)
+#define PDS_CR_WIFI_PDS_SAVE_STATE_LEN     (1U)
+#define PDS_CR_WIFI_PDS_SAVE_STATE_MSK     (((1U << PDS_CR_WIFI_PDS_SAVE_STATE_LEN) - 1) << PDS_CR_WIFI_PDS_SAVE_STATE_POS)
+#define PDS_CR_WIFI_PDS_SAVE_STATE_UMSK    (~(((1U << PDS_CR_WIFI_PDS_SAVE_STATE_LEN) - 1) << PDS_CR_WIFI_PDS_SAVE_STATE_POS))
+#define PDS_CR_PDS_PD_DCDC18               PDS_CR_PDS_PD_DCDC18
+#define PDS_CR_PDS_PD_DCDC18_POS           (4U)
+#define PDS_CR_PDS_PD_DCDC18_LEN           (1U)
+#define PDS_CR_PDS_PD_DCDC18_MSK           (((1U << PDS_CR_PDS_PD_DCDC18_LEN) - 1) << PDS_CR_PDS_PD_DCDC18_POS)
+#define PDS_CR_PDS_PD_DCDC18_UMSK          (~(((1U << PDS_CR_PDS_PD_DCDC18_LEN) - 1) << PDS_CR_PDS_PD_DCDC18_POS))
+#define PDS_CR_PDS_PD_BG_SYS               PDS_CR_PDS_PD_BG_SYS
+#define PDS_CR_PDS_PD_BG_SYS_POS           (5U)
+#define PDS_CR_PDS_PD_BG_SYS_LEN           (1U)
+#define PDS_CR_PDS_PD_BG_SYS_MSK           (((1U << PDS_CR_PDS_PD_BG_SYS_LEN) - 1) << PDS_CR_PDS_PD_BG_SYS_POS)
+#define PDS_CR_PDS_PD_BG_SYS_UMSK          (~(((1U << PDS_CR_PDS_PD_BG_SYS_LEN) - 1) << PDS_CR_PDS_PD_BG_SYS_POS))
+#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD      PDS_CR_PDS_CTRL_GPIO_IE_PU_PD
+#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_POS  (6U)
+#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_LEN  (1U)
+#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_MSK  (((1U << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_LEN) - 1) << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_POS)
+#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_UMSK (~(((1U << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_LEN) - 1) << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_POS))
+#define PDS_CR_PDS_CTRL_PU_FLASH           PDS_CR_PDS_CTRL_PU_FLASH
+#define PDS_CR_PDS_CTRL_PU_FLASH_POS       (7U)
+#define PDS_CR_PDS_CTRL_PU_FLASH_LEN       (1U)
+#define PDS_CR_PDS_CTRL_PU_FLASH_MSK       (((1U << PDS_CR_PDS_CTRL_PU_FLASH_LEN) - 1) << PDS_CR_PDS_CTRL_PU_FLASH_POS)
+#define PDS_CR_PDS_CTRL_PU_FLASH_UMSK      (~(((1U << PDS_CR_PDS_CTRL_PU_FLASH_LEN) - 1) << PDS_CR_PDS_CTRL_PU_FLASH_POS))
+#define PDS_CR_PDS_GATE_CLK                PDS_CR_PDS_GATE_CLK
+#define PDS_CR_PDS_GATE_CLK_POS            (8U)
+#define PDS_CR_PDS_GATE_CLK_LEN            (1U)
+#define PDS_CR_PDS_GATE_CLK_MSK            (((1U << PDS_CR_PDS_GATE_CLK_LEN) - 1) << PDS_CR_PDS_GATE_CLK_POS)
+#define PDS_CR_PDS_GATE_CLK_UMSK           (~(((1U << PDS_CR_PDS_GATE_CLK_LEN) - 1) << PDS_CR_PDS_GATE_CLK_POS))
+#define PDS_CR_PDS_MEM_STBY                PDS_CR_PDS_MEM_STBY
+#define PDS_CR_PDS_MEM_STBY_POS            (9U)
+#define PDS_CR_PDS_MEM_STBY_LEN            (1U)
+#define PDS_CR_PDS_MEM_STBY_MSK            (((1U << PDS_CR_PDS_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MEM_STBY_POS)
+#define PDS_CR_PDS_MEM_STBY_UMSK           (~(((1U << PDS_CR_PDS_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MEM_STBY_POS))
+#define PDS_CR_SW_PU_FLASH                 PDS_CR_SW_PU_FLASH
+#define PDS_CR_SW_PU_FLASH_POS             (10U)
+#define PDS_CR_SW_PU_FLASH_LEN             (1U)
+#define PDS_CR_SW_PU_FLASH_MSK             (((1U << PDS_CR_SW_PU_FLASH_LEN) - 1) << PDS_CR_SW_PU_FLASH_POS)
+#define PDS_CR_SW_PU_FLASH_UMSK            (~(((1U << PDS_CR_SW_PU_FLASH_LEN) - 1) << PDS_CR_SW_PU_FLASH_POS))
+#define PDS_CR_PDS_ISO_EN                  PDS_CR_PDS_ISO_EN
+#define PDS_CR_PDS_ISO_EN_POS              (11U)
+#define PDS_CR_PDS_ISO_EN_LEN              (1U)
+#define PDS_CR_PDS_ISO_EN_MSK              (((1U << PDS_CR_PDS_ISO_EN_LEN) - 1) << PDS_CR_PDS_ISO_EN_POS)
+#define PDS_CR_PDS_ISO_EN_UMSK             (~(((1U << PDS_CR_PDS_ISO_EN_LEN) - 1) << PDS_CR_PDS_ISO_EN_POS))
+#define PDS_CR_PDS_WAIT_XTAL_RDY           PDS_CR_PDS_WAIT_XTAL_RDY
+#define PDS_CR_PDS_WAIT_XTAL_RDY_POS       (12U)
+#define PDS_CR_PDS_WAIT_XTAL_RDY_LEN       (1U)
+#define PDS_CR_PDS_WAIT_XTAL_RDY_MSK       (((1U << PDS_CR_PDS_WAIT_XTAL_RDY_LEN) - 1) << PDS_CR_PDS_WAIT_XTAL_RDY_POS)
+#define PDS_CR_PDS_WAIT_XTAL_RDY_UMSK      (~(((1U << PDS_CR_PDS_WAIT_XTAL_RDY_LEN) - 1) << PDS_CR_PDS_WAIT_XTAL_RDY_POS))
+#define PDS_CR_PDS_PWR_OFF                 PDS_CR_PDS_PWR_OFF
+#define PDS_CR_PDS_PWR_OFF_POS             (13U)
+#define PDS_CR_PDS_PWR_OFF_LEN             (1U)
+#define PDS_CR_PDS_PWR_OFF_MSK             (((1U << PDS_CR_PDS_PWR_OFF_LEN) - 1) << PDS_CR_PDS_PWR_OFF_POS)
+#define PDS_CR_PDS_PWR_OFF_UMSK            (~(((1U << PDS_CR_PDS_PWR_OFF_LEN) - 1) << PDS_CR_PDS_PWR_OFF_POS))
+#define PDS_CR_PDS_PD_XTAL                 PDS_CR_PDS_PD_XTAL
+#define PDS_CR_PDS_PD_XTAL_POS             (14U)
+#define PDS_CR_PDS_PD_XTAL_LEN             (1U)
+#define PDS_CR_PDS_PD_XTAL_MSK             (((1U << PDS_CR_PDS_PD_XTAL_LEN) - 1) << PDS_CR_PDS_PD_XTAL_POS)
+#define PDS_CR_PDS_PD_XTAL_UMSK            (~(((1U << PDS_CR_PDS_PD_XTAL_LEN) - 1) << PDS_CR_PDS_PD_XTAL_POS))
+#define PDS_CR_PDS_SOC_ENB_FORCE_ON        PDS_CR_PDS_SOC_ENB_FORCE_ON
+#define PDS_CR_PDS_SOC_ENB_FORCE_ON_POS    (15U)
+#define PDS_CR_PDS_SOC_ENB_FORCE_ON_LEN    (1U)
+#define PDS_CR_PDS_SOC_ENB_FORCE_ON_MSK    (((1U << PDS_CR_PDS_SOC_ENB_FORCE_ON_LEN) - 1) << PDS_CR_PDS_SOC_ENB_FORCE_ON_POS)
+#define PDS_CR_PDS_SOC_ENB_FORCE_ON_UMSK   (~(((1U << PDS_CR_PDS_SOC_ENB_FORCE_ON_LEN) - 1) << PDS_CR_PDS_SOC_ENB_FORCE_ON_POS))
+#define PDS_CR_PDS_RST_SOC_EN              PDS_CR_PDS_RST_SOC_EN
+#define PDS_CR_PDS_RST_SOC_EN_POS          (16U)
+#define PDS_CR_PDS_RST_SOC_EN_LEN          (1U)
+#define PDS_CR_PDS_RST_SOC_EN_MSK          (((1U << PDS_CR_PDS_RST_SOC_EN_LEN) - 1) << PDS_CR_PDS_RST_SOC_EN_POS)
+#define PDS_CR_PDS_RST_SOC_EN_UMSK         (~(((1U << PDS_CR_PDS_RST_SOC_EN_LEN) - 1) << PDS_CR_PDS_RST_SOC_EN_POS))
+#define PDS_CR_PDS_RC32M_OFF_DIS           PDS_CR_PDS_RC32M_OFF_DIS
+#define PDS_CR_PDS_RC32M_OFF_DIS_POS       (17U)
+#define PDS_CR_PDS_RC32M_OFF_DIS_LEN       (1U)
+#define PDS_CR_PDS_RC32M_OFF_DIS_MSK       (((1U << PDS_CR_PDS_RC32M_OFF_DIS_LEN) - 1) << PDS_CR_PDS_RC32M_OFF_DIS_POS)
+#define PDS_CR_PDS_RC32M_OFF_DIS_UMSK      (~(((1U << PDS_CR_PDS_RC32M_OFF_DIS_LEN) - 1) << PDS_CR_PDS_RC32M_OFF_DIS_POS))
+#define PDS_CR_PDS_LDO_VSEL_EN             PDS_CR_PDS_LDO_VSEL_EN
+#define PDS_CR_PDS_LDO_VSEL_EN_POS         (18U)
+#define PDS_CR_PDS_LDO_VSEL_EN_LEN         (1U)
+#define PDS_CR_PDS_LDO_VSEL_EN_MSK         (((1U << PDS_CR_PDS_LDO_VSEL_EN_LEN) - 1) << PDS_CR_PDS_LDO_VSEL_EN_POS)
+#define PDS_CR_PDS_LDO_VSEL_EN_UMSK        (~(((1U << PDS_CR_PDS_LDO_VSEL_EN_LEN) - 1) << PDS_CR_PDS_LDO_VSEL_EN_POS))
+#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN      PDS_CR_PDS_RAM_LP_WITH_CLK_EN
+#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN_POS  (19U)
+#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN_LEN  (1U)
+#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN_MSK  (((1U << PDS_CR_PDS_RAM_LP_WITH_CLK_EN_LEN) - 1) << PDS_CR_PDS_RAM_LP_WITH_CLK_EN_POS)
+#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN_UMSK (~(((1U << PDS_CR_PDS_RAM_LP_WITH_CLK_EN_LEN) - 1) << PDS_CR_PDS_RAM_LP_WITH_CLK_EN_POS))
+#define PDS_CR_NP_WFI_MASK                 PDS_CR_NP_WFI_MASK
+#define PDS_CR_NP_WFI_MASK_POS             (21U)
+#define PDS_CR_NP_WFI_MASK_LEN             (1U)
+#define PDS_CR_NP_WFI_MASK_MSK             (((1U << PDS_CR_NP_WFI_MASK_LEN) - 1) << PDS_CR_NP_WFI_MASK_POS)
+#define PDS_CR_NP_WFI_MASK_UMSK            (~(((1U << PDS_CR_NP_WFI_MASK_LEN) - 1) << PDS_CR_NP_WFI_MASK_POS))
+#define PDS_CR_PDS_PD_LDO11                PDS_CR_PDS_PD_LDO11
+#define PDS_CR_PDS_PD_LDO11_POS            (22U)
+#define PDS_CR_PDS_PD_LDO11_LEN            (1U)
+#define PDS_CR_PDS_PD_LDO11_MSK            (((1U << PDS_CR_PDS_PD_LDO11_LEN) - 1) << PDS_CR_PDS_PD_LDO11_POS)
+#define PDS_CR_PDS_PD_LDO11_UMSK           (~(((1U << PDS_CR_PDS_PD_LDO11_LEN) - 1) << PDS_CR_PDS_PD_LDO11_POS))
+#define PDS_CR_PDS_FORCE_RAM_CLK_EN        PDS_CR_PDS_FORCE_RAM_CLK_EN
+#define PDS_CR_PDS_FORCE_RAM_CLK_EN_POS    (23U)
+#define PDS_CR_PDS_FORCE_RAM_CLK_EN_LEN    (1U)
+#define PDS_CR_PDS_FORCE_RAM_CLK_EN_MSK    (((1U << PDS_CR_PDS_FORCE_RAM_CLK_EN_LEN) - 1) << PDS_CR_PDS_FORCE_RAM_CLK_EN_POS)
+#define PDS_CR_PDS_FORCE_RAM_CLK_EN_UMSK   (~(((1U << PDS_CR_PDS_FORCE_RAM_CLK_EN_LEN) - 1) << PDS_CR_PDS_FORCE_RAM_CLK_EN_POS))
+#define PDS_CR_PDS_LDO_VOL                 PDS_CR_PDS_LDO_VOL
+#define PDS_CR_PDS_LDO_VOL_POS             (24U)
+#define PDS_CR_PDS_LDO_VOL_LEN             (4U)
+#define PDS_CR_PDS_LDO_VOL_MSK             (((1U << PDS_CR_PDS_LDO_VOL_LEN) - 1) << PDS_CR_PDS_LDO_VOL_POS)
+#define PDS_CR_PDS_LDO_VOL_UMSK            (~(((1U << PDS_CR_PDS_LDO_VOL_LEN) - 1) << PDS_CR_PDS_LDO_VOL_POS))
+#define PDS_CR_PDS_CTRL_RF                 PDS_CR_PDS_CTRL_RF
+#define PDS_CR_PDS_CTRL_RF_POS             (28U)
+#define PDS_CR_PDS_CTRL_RF_LEN             (2U)
+#define PDS_CR_PDS_CTRL_RF_MSK             (((1U << PDS_CR_PDS_CTRL_RF_LEN) - 1) << PDS_CR_PDS_CTRL_RF_POS)
+#define PDS_CR_PDS_CTRL_RF_UMSK            (~(((1U << PDS_CR_PDS_CTRL_RF_LEN) - 1) << PDS_CR_PDS_CTRL_RF_POS))
+#define PDS_CR_PDS_CTRL_PLL                PDS_CR_PDS_CTRL_PLL
+#define PDS_CR_PDS_CTRL_PLL_POS            (30U)
+#define PDS_CR_PDS_CTRL_PLL_LEN            (2U)
+#define PDS_CR_PDS_CTRL_PLL_MSK            (((1U << PDS_CR_PDS_CTRL_PLL_LEN) - 1) << PDS_CR_PDS_CTRL_PLL_POS)
+#define PDS_CR_PDS_CTRL_PLL_UMSK           (~(((1U << PDS_CR_PDS_CTRL_PLL_LEN) - 1) << PDS_CR_PDS_CTRL_PLL_POS))
+
+/* 0x4 : PDS_TIME1 */
+#define PDS_TIME1_OFFSET           (0x4)
+#define PDS_CR_SLEEP_DURATION      PDS_CR_SLEEP_DURATION
+#define PDS_CR_SLEEP_DURATION_POS  (0U)
+#define PDS_CR_SLEEP_DURATION_LEN  (32U)
+#define PDS_CR_SLEEP_DURATION_MSK  (((1U << PDS_CR_SLEEP_DURATION_LEN) - 1) << PDS_CR_SLEEP_DURATION_POS)
+#define PDS_CR_SLEEP_DURATION_UMSK (~(((1U << PDS_CR_SLEEP_DURATION_LEN) - 1) << PDS_CR_SLEEP_DURATION_POS))
+
+/* 0xC : PDS_INT */
+#define PDS_INT_OFFSET                    (0xC)
+#define PDS_RO_PDS_WAKE_INT               PDS_RO_PDS_WAKE_INT
+#define PDS_RO_PDS_WAKE_INT_POS           (0U)
+#define PDS_RO_PDS_WAKE_INT_LEN           (1U)
+#define PDS_RO_PDS_WAKE_INT_MSK           (((1U << PDS_RO_PDS_WAKE_INT_LEN) - 1) << PDS_RO_PDS_WAKE_INT_POS)
+#define PDS_RO_PDS_WAKE_INT_UMSK          (~(((1U << PDS_RO_PDS_WAKE_INT_LEN) - 1) << PDS_RO_PDS_WAKE_INT_POS))
+#define PDS_RO_PDS_RF_DONE_INT            PDS_RO_PDS_RF_DONE_INT
+#define PDS_RO_PDS_RF_DONE_INT_POS        (2U)
+#define PDS_RO_PDS_RF_DONE_INT_LEN        (1U)
+#define PDS_RO_PDS_RF_DONE_INT_MSK        (((1U << PDS_RO_PDS_RF_DONE_INT_LEN) - 1) << PDS_RO_PDS_RF_DONE_INT_POS)
+#define PDS_RO_PDS_RF_DONE_INT_UMSK       (~(((1U << PDS_RO_PDS_RF_DONE_INT_LEN) - 1) << PDS_RO_PDS_RF_DONE_INT_POS))
+#define PDS_RO_PDS_PLL_DONE_INT           PDS_RO_PDS_PLL_DONE_INT
+#define PDS_RO_PDS_PLL_DONE_INT_POS       (3U)
+#define PDS_RO_PDS_PLL_DONE_INT_LEN       (1U)
+#define PDS_RO_PDS_PLL_DONE_INT_MSK       (((1U << PDS_RO_PDS_PLL_DONE_INT_LEN) - 1) << PDS_RO_PDS_PLL_DONE_INT_POS)
+#define PDS_RO_PDS_PLL_DONE_INT_UMSK      (~(((1U << PDS_RO_PDS_PLL_DONE_INT_LEN) - 1) << PDS_RO_PDS_PLL_DONE_INT_POS))
+#define PDS_RESET_EVENT                   PDS_RESET_EVENT
+#define PDS_RESET_EVENT_POS               (4U)
+#define PDS_RESET_EVENT_LEN               (3U)
+#define PDS_RESET_EVENT_MSK               (((1U << PDS_RESET_EVENT_LEN) - 1) << PDS_RESET_EVENT_POS)
+#define PDS_RESET_EVENT_UMSK              (~(((1U << PDS_RESET_EVENT_LEN) - 1) << PDS_RESET_EVENT_POS))
+#define PDS_CLR_RESET_EVENT               PDS_CLR_RESET_EVENT
+#define PDS_CLR_RESET_EVENT_POS           (7U)
+#define PDS_CLR_RESET_EVENT_LEN           (1U)
+#define PDS_CLR_RESET_EVENT_MSK           (((1U << PDS_CLR_RESET_EVENT_LEN) - 1) << PDS_CLR_RESET_EVENT_POS)
+#define PDS_CLR_RESET_EVENT_UMSK          (~(((1U << PDS_CLR_RESET_EVENT_LEN) - 1) << PDS_CLR_RESET_EVENT_POS))
+#define PDS_CR_PDS_WAKE_INT_MASK          PDS_CR_PDS_WAKE_INT_MASK
+#define PDS_CR_PDS_WAKE_INT_MASK_POS      (8U)
+#define PDS_CR_PDS_WAKE_INT_MASK_LEN      (1U)
+#define PDS_CR_PDS_WAKE_INT_MASK_MSK      (((1U << PDS_CR_PDS_WAKE_INT_MASK_LEN) - 1) << PDS_CR_PDS_WAKE_INT_MASK_POS)
+#define PDS_CR_PDS_WAKE_INT_MASK_UMSK     (~(((1U << PDS_CR_PDS_WAKE_INT_MASK_LEN) - 1) << PDS_CR_PDS_WAKE_INT_MASK_POS))
+#define PDS_CR_PDS_RF_DONE_INT_MASK       PDS_CR_PDS_RF_DONE_INT_MASK
+#define PDS_CR_PDS_RF_DONE_INT_MASK_POS   (10U)
+#define PDS_CR_PDS_RF_DONE_INT_MASK_LEN   (1U)
+#define PDS_CR_PDS_RF_DONE_INT_MASK_MSK   (((1U << PDS_CR_PDS_RF_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_RF_DONE_INT_MASK_POS)
+#define PDS_CR_PDS_RF_DONE_INT_MASK_UMSK  (~(((1U << PDS_CR_PDS_RF_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_RF_DONE_INT_MASK_POS))
+#define PDS_CR_PDS_PLL_DONE_INT_MASK      PDS_CR_PDS_PLL_DONE_INT_MASK
+#define PDS_CR_PDS_PLL_DONE_INT_MASK_POS  (11U)
+#define PDS_CR_PDS_PLL_DONE_INT_MASK_LEN  (1U)
+#define PDS_CR_PDS_PLL_DONE_INT_MASK_MSK  (((1U << PDS_CR_PDS_PLL_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_PLL_DONE_INT_MASK_POS)
+#define PDS_CR_PDS_PLL_DONE_INT_MASK_UMSK (~(((1U << PDS_CR_PDS_PLL_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_PLL_DONE_INT_MASK_POS))
+#define PDS_CR_PDS_INT_CLR                PDS_CR_PDS_INT_CLR
+#define PDS_CR_PDS_INT_CLR_POS            (15U)
+#define PDS_CR_PDS_INT_CLR_LEN            (1U)
+#define PDS_CR_PDS_INT_CLR_MSK            (((1U << PDS_CR_PDS_INT_CLR_LEN) - 1) << PDS_CR_PDS_INT_CLR_POS)
+#define PDS_CR_PDS_INT_CLR_UMSK           (~(((1U << PDS_CR_PDS_INT_CLR_LEN) - 1) << PDS_CR_PDS_INT_CLR_POS))
+#define PDS_CR_PDS_WAKEUP_SRC_EN          PDS_CR_PDS_WAKEUP_SRC_EN
+#define PDS_CR_PDS_WAKEUP_SRC_EN_POS      (16U)
+#define PDS_CR_PDS_WAKEUP_SRC_EN_LEN      (8U)
+#define PDS_CR_PDS_WAKEUP_SRC_EN_MSK      (((1U << PDS_CR_PDS_WAKEUP_SRC_EN_LEN) - 1) << PDS_CR_PDS_WAKEUP_SRC_EN_POS)
+#define PDS_CR_PDS_WAKEUP_SRC_EN_UMSK     (~(((1U << PDS_CR_PDS_WAKEUP_SRC_EN_LEN) - 1) << PDS_CR_PDS_WAKEUP_SRC_EN_POS))
+#define PDS_RO_PDS_WAKEUP_EVENT           PDS_RO_PDS_WAKEUP_EVENT
+#define PDS_RO_PDS_WAKEUP_EVENT_POS       (24U)
+#define PDS_RO_PDS_WAKEUP_EVENT_LEN       (8U)
+#define PDS_RO_PDS_WAKEUP_EVENT_MSK       (((1U << PDS_RO_PDS_WAKEUP_EVENT_LEN) - 1) << PDS_RO_PDS_WAKEUP_EVENT_POS)
+#define PDS_RO_PDS_WAKEUP_EVENT_UMSK      (~(((1U << PDS_RO_PDS_WAKEUP_EVENT_LEN) - 1) << PDS_RO_PDS_WAKEUP_EVENT_POS))
+
+/* 0x10 : PDS_CTL2 */
+#define PDS_CTL2_OFFSET                    (0x10)
+#define PDS_CR_PDS_FORCE_NP_PWR_OFF        PDS_CR_PDS_FORCE_NP_PWR_OFF
+#define PDS_CR_PDS_FORCE_NP_PWR_OFF_POS    (0U)
+#define PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN    (1U)
+#define PDS_CR_PDS_FORCE_NP_PWR_OFF_MSK    (((1U << PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PWR_OFF_POS)
+#define PDS_CR_PDS_FORCE_NP_PWR_OFF_UMSK   (~(((1U << PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PWR_OFF_POS))
+#define PDS_CR_PDS_FORCE_BZ_PWR_OFF        PDS_CR_PDS_FORCE_BZ_PWR_OFF
+#define PDS_CR_PDS_FORCE_BZ_PWR_OFF_POS    (2U)
+#define PDS_CR_PDS_FORCE_BZ_PWR_OFF_LEN    (1U)
+#define PDS_CR_PDS_FORCE_BZ_PWR_OFF_MSK    (((1U << PDS_CR_PDS_FORCE_BZ_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_PWR_OFF_POS)
+#define PDS_CR_PDS_FORCE_BZ_PWR_OFF_UMSK   (~(((1U << PDS_CR_PDS_FORCE_BZ_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_PWR_OFF_POS))
+#define PDS_CR_PDS_FORCE_USB_PWR_OFF       PDS_CR_PDS_FORCE_USB_PWR_OFF
+#define PDS_CR_PDS_FORCE_USB_PWR_OFF_POS   (3U)
+#define PDS_CR_PDS_FORCE_USB_PWR_OFF_LEN   (1U)
+#define PDS_CR_PDS_FORCE_USB_PWR_OFF_MSK   (((1U << PDS_CR_PDS_FORCE_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PWR_OFF_POS)
+#define PDS_CR_PDS_FORCE_USB_PWR_OFF_UMSK  (~(((1U << PDS_CR_PDS_FORCE_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PWR_OFF_POS))
+#define PDS_CR_PDS_FORCE_NP_ISO_EN         PDS_CR_PDS_FORCE_NP_ISO_EN
+#define PDS_CR_PDS_FORCE_NP_ISO_EN_POS     (4U)
+#define PDS_CR_PDS_FORCE_NP_ISO_EN_LEN     (1U)
+#define PDS_CR_PDS_FORCE_NP_ISO_EN_MSK     (((1U << PDS_CR_PDS_FORCE_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_NP_ISO_EN_POS)
+#define PDS_CR_PDS_FORCE_NP_ISO_EN_UMSK    (~(((1U << PDS_CR_PDS_FORCE_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_NP_ISO_EN_POS))
+#define PDS_CR_PDS_FORCE_BZ_ISO_EN         PDS_CR_PDS_FORCE_BZ_ISO_EN
+#define PDS_CR_PDS_FORCE_BZ_ISO_EN_POS     (6U)
+#define PDS_CR_PDS_FORCE_BZ_ISO_EN_LEN     (1U)
+#define PDS_CR_PDS_FORCE_BZ_ISO_EN_MSK     (((1U << PDS_CR_PDS_FORCE_BZ_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_ISO_EN_POS)
+#define PDS_CR_PDS_FORCE_BZ_ISO_EN_UMSK    (~(((1U << PDS_CR_PDS_FORCE_BZ_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_ISO_EN_POS))
+#define PDS_CR_PDS_FORCE_USB_ISO_EN        PDS_CR_PDS_FORCE_USB_ISO_EN
+#define PDS_CR_PDS_FORCE_USB_ISO_EN_POS    (7U)
+#define PDS_CR_PDS_FORCE_USB_ISO_EN_LEN    (1U)
+#define PDS_CR_PDS_FORCE_USB_ISO_EN_MSK    (((1U << PDS_CR_PDS_FORCE_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_USB_ISO_EN_POS)
+#define PDS_CR_PDS_FORCE_USB_ISO_EN_UMSK   (~(((1U << PDS_CR_PDS_FORCE_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_USB_ISO_EN_POS))
+#define PDS_CR_PDS_FORCE_NP_PDS_RST        PDS_CR_PDS_FORCE_NP_PDS_RST
+#define PDS_CR_PDS_FORCE_NP_PDS_RST_POS    (8U)
+#define PDS_CR_PDS_FORCE_NP_PDS_RST_LEN    (1U)
+#define PDS_CR_PDS_FORCE_NP_PDS_RST_MSK    (((1U << PDS_CR_PDS_FORCE_NP_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PDS_RST_POS)
+#define PDS_CR_PDS_FORCE_NP_PDS_RST_UMSK   (~(((1U << PDS_CR_PDS_FORCE_NP_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PDS_RST_POS))
+#define PDS_CR_PDS_FORCE_BZ_PDS_RST        PDS_CR_PDS_FORCE_BZ_PDS_RST
+#define PDS_CR_PDS_FORCE_BZ_PDS_RST_POS    (10U)
+#define PDS_CR_PDS_FORCE_BZ_PDS_RST_LEN    (1U)
+#define PDS_CR_PDS_FORCE_BZ_PDS_RST_MSK    (((1U << PDS_CR_PDS_FORCE_BZ_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_PDS_RST_POS)
+#define PDS_CR_PDS_FORCE_BZ_PDS_RST_UMSK   (~(((1U << PDS_CR_PDS_FORCE_BZ_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_PDS_RST_POS))
+#define PDS_CR_PDS_FORCE_USB_PDS_RST       PDS_CR_PDS_FORCE_USB_PDS_RST
+#define PDS_CR_PDS_FORCE_USB_PDS_RST_POS   (11U)
+#define PDS_CR_PDS_FORCE_USB_PDS_RST_LEN   (1U)
+#define PDS_CR_PDS_FORCE_USB_PDS_RST_MSK   (((1U << PDS_CR_PDS_FORCE_USB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PDS_RST_POS)
+#define PDS_CR_PDS_FORCE_USB_PDS_RST_UMSK  (~(((1U << PDS_CR_PDS_FORCE_USB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PDS_RST_POS))
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY       PDS_CR_PDS_FORCE_NP_MEM_STBY
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY_POS   (12U)
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN   (1U)
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY_MSK   (((1U << PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_NP_MEM_STBY_POS)
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY_UMSK  (~(((1U << PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_NP_MEM_STBY_POS))
+#define PDS_CR_PDS_FORCE_BZ_MEM_STBY       PDS_CR_PDS_FORCE_BZ_MEM_STBY
+#define PDS_CR_PDS_FORCE_BZ_MEM_STBY_POS   (14U)
+#define PDS_CR_PDS_FORCE_BZ_MEM_STBY_LEN   (1U)
+#define PDS_CR_PDS_FORCE_BZ_MEM_STBY_MSK   (((1U << PDS_CR_PDS_FORCE_BZ_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_MEM_STBY_POS)
+#define PDS_CR_PDS_FORCE_BZ_MEM_STBY_UMSK  (~(((1U << PDS_CR_PDS_FORCE_BZ_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_MEM_STBY_POS))
+#define PDS_CR_PDS_FORCE_USB_MEM_STBY      PDS_CR_PDS_FORCE_USB_MEM_STBY
+#define PDS_CR_PDS_FORCE_USB_MEM_STBY_POS  (15U)
+#define PDS_CR_PDS_FORCE_USB_MEM_STBY_LEN  (1U)
+#define PDS_CR_PDS_FORCE_USB_MEM_STBY_MSK  (((1U << PDS_CR_PDS_FORCE_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_USB_MEM_STBY_POS)
+#define PDS_CR_PDS_FORCE_USB_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_USB_MEM_STBY_POS))
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK       PDS_CR_PDS_FORCE_NP_GATE_CLK
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK_POS   (16U)
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN   (1U)
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK_MSK   (((1U << PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_NP_GATE_CLK_POS)
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK_UMSK  (~(((1U << PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_NP_GATE_CLK_POS))
+#define PDS_CR_PDS_FORCE_BZ_GATE_CLK       PDS_CR_PDS_FORCE_BZ_GATE_CLK
+#define PDS_CR_PDS_FORCE_BZ_GATE_CLK_POS   (18U)
+#define PDS_CR_PDS_FORCE_BZ_GATE_CLK_LEN   (1U)
+#define PDS_CR_PDS_FORCE_BZ_GATE_CLK_MSK   (((1U << PDS_CR_PDS_FORCE_BZ_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_GATE_CLK_POS)
+#define PDS_CR_PDS_FORCE_BZ_GATE_CLK_UMSK  (~(((1U << PDS_CR_PDS_FORCE_BZ_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_GATE_CLK_POS))
+#define PDS_CR_PDS_FORCE_USB_GATE_CLK      PDS_CR_PDS_FORCE_USB_GATE_CLK
+#define PDS_CR_PDS_FORCE_USB_GATE_CLK_POS  (19U)
+#define PDS_CR_PDS_FORCE_USB_GATE_CLK_LEN  (1U)
+#define PDS_CR_PDS_FORCE_USB_GATE_CLK_MSK  (((1U << PDS_CR_PDS_FORCE_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_USB_GATE_CLK_POS)
+#define PDS_CR_PDS_FORCE_USB_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_USB_GATE_CLK_POS))
+
+/* 0x14 : PDS_CTL3 */
+#define PDS_CTL3_OFFSET                     (0x14)
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF       PDS_CR_PDS_FORCE_MISC_PWR_OFF
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS   (1U)
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN   (1U)
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_MSK   (((1U << PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS)
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_UMSK  (~(((1U << PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS))
+#define PDS_CR_PDS_FORCE_BLE_PWR_OFF        PDS_CR_PDS_FORCE_BLE_PWR_OFF
+#define PDS_CR_PDS_FORCE_BLE_PWR_OFF_POS    (2U)
+#define PDS_CR_PDS_FORCE_BLE_PWR_OFF_LEN    (1U)
+#define PDS_CR_PDS_FORCE_BLE_PWR_OFF_MSK    (((1U << PDS_CR_PDS_FORCE_BLE_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_PWR_OFF_POS)
+#define PDS_CR_PDS_FORCE_BLE_PWR_OFF_UMSK   (~(((1U << PDS_CR_PDS_FORCE_BLE_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_PWR_OFF_POS))
+#define PDS_CR_PDS_FORCE_BLE_ISO_EN         PDS_CR_PDS_FORCE_BLE_ISO_EN
+#define PDS_CR_PDS_FORCE_BLE_ISO_EN_POS     (5U)
+#define PDS_CR_PDS_FORCE_BLE_ISO_EN_LEN     (1U)
+#define PDS_CR_PDS_FORCE_BLE_ISO_EN_MSK     (((1U << PDS_CR_PDS_FORCE_BLE_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_ISO_EN_POS)
+#define PDS_CR_PDS_FORCE_BLE_ISO_EN_UMSK    (~(((1U << PDS_CR_PDS_FORCE_BLE_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_ISO_EN_POS))
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST       PDS_CR_PDS_FORCE_MISC_PDS_RST
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST_POS   (7U)
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN   (1U)
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST_MSK   (((1U << PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PDS_RST_POS)
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST_UMSK  (~(((1U << PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PDS_RST_POS))
+#define PDS_CR_PDS_FORCE_BLE_PDS_RST        PDS_CR_PDS_FORCE_BLE_PDS_RST
+#define PDS_CR_PDS_FORCE_BLE_PDS_RST_POS    (8U)
+#define PDS_CR_PDS_FORCE_BLE_PDS_RST_LEN    (1U)
+#define PDS_CR_PDS_FORCE_BLE_PDS_RST_MSK    (((1U << PDS_CR_PDS_FORCE_BLE_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_PDS_RST_POS)
+#define PDS_CR_PDS_FORCE_BLE_PDS_RST_UMSK   (~(((1U << PDS_CR_PDS_FORCE_BLE_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_PDS_RST_POS))
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY      PDS_CR_PDS_FORCE_MISC_MEM_STBY
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS  (10U)
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN  (1U)
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_MSK  (((1U << PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS)
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS))
+#define PDS_CR_PDS_FORCE_BLE_MEM_STBY       PDS_CR_PDS_FORCE_BLE_MEM_STBY
+#define PDS_CR_PDS_FORCE_BLE_MEM_STBY_POS   (11U)
+#define PDS_CR_PDS_FORCE_BLE_MEM_STBY_LEN   (1U)
+#define PDS_CR_PDS_FORCE_BLE_MEM_STBY_MSK   (((1U << PDS_CR_PDS_FORCE_BLE_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_MEM_STBY_POS)
+#define PDS_CR_PDS_FORCE_BLE_MEM_STBY_UMSK  (~(((1U << PDS_CR_PDS_FORCE_BLE_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_MEM_STBY_POS))
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK      PDS_CR_PDS_FORCE_MISC_GATE_CLK
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS  (13U)
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN  (1U)
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_MSK  (((1U << PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS)
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS))
+#define PDS_CR_PDS_FORCE_BLE_GATE_CLK       PDS_CR_PDS_FORCE_BLE_GATE_CLK
+#define PDS_CR_PDS_FORCE_BLE_GATE_CLK_POS   (14U)
+#define PDS_CR_PDS_FORCE_BLE_GATE_CLK_LEN   (1U)
+#define PDS_CR_PDS_FORCE_BLE_GATE_CLK_MSK   (((1U << PDS_CR_PDS_FORCE_BLE_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_GATE_CLK_POS)
+#define PDS_CR_PDS_FORCE_BLE_GATE_CLK_UMSK  (~(((1U << PDS_CR_PDS_FORCE_BLE_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_GATE_CLK_POS))
+#define PDS_CR_PDS_NP_ISO_EN                PDS_CR_PDS_NP_ISO_EN
+#define PDS_CR_PDS_NP_ISO_EN_POS            (24U)
+#define PDS_CR_PDS_NP_ISO_EN_LEN            (1U)
+#define PDS_CR_PDS_NP_ISO_EN_MSK            (((1U << PDS_CR_PDS_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_NP_ISO_EN_POS)
+#define PDS_CR_PDS_NP_ISO_EN_UMSK           (~(((1U << PDS_CR_PDS_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_NP_ISO_EN_POS))
+#define PDS_CR_PDS_BZ_ISO_EN                PDS_CR_PDS_BZ_ISO_EN
+#define PDS_CR_PDS_BZ_ISO_EN_POS            (27U)
+#define PDS_CR_PDS_BZ_ISO_EN_LEN            (1U)
+#define PDS_CR_PDS_BZ_ISO_EN_MSK            (((1U << PDS_CR_PDS_BZ_ISO_EN_LEN) - 1) << PDS_CR_PDS_BZ_ISO_EN_POS)
+#define PDS_CR_PDS_BZ_ISO_EN_UMSK           (~(((1U << PDS_CR_PDS_BZ_ISO_EN_LEN) - 1) << PDS_CR_PDS_BZ_ISO_EN_POS))
+#define PDS_CR_PDS_BLE_ISO_EN               PDS_CR_PDS_BLE_ISO_EN
+#define PDS_CR_PDS_BLE_ISO_EN_POS           (28U)
+#define PDS_CR_PDS_BLE_ISO_EN_LEN           (1U)
+#define PDS_CR_PDS_BLE_ISO_EN_MSK           (((1U << PDS_CR_PDS_BLE_ISO_EN_LEN) - 1) << PDS_CR_PDS_BLE_ISO_EN_POS)
+#define PDS_CR_PDS_BLE_ISO_EN_UMSK          (~(((1U << PDS_CR_PDS_BLE_ISO_EN_LEN) - 1) << PDS_CR_PDS_BLE_ISO_EN_POS))
+#define PDS_CR_PDS_USB_ISO_EN               PDS_CR_PDS_USB_ISO_EN
+#define PDS_CR_PDS_USB_ISO_EN_POS           (29U)
+#define PDS_CR_PDS_USB_ISO_EN_LEN           (1U)
+#define PDS_CR_PDS_USB_ISO_EN_MSK           (((1U << PDS_CR_PDS_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_USB_ISO_EN_POS)
+#define PDS_CR_PDS_USB_ISO_EN_UMSK          (~(((1U << PDS_CR_PDS_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_USB_ISO_EN_POS))
+#define PDS_CR_PDS_MISC_ISO_EN              PDS_CR_PDS_MISC_ISO_EN
+#define PDS_CR_PDS_MISC_ISO_EN_POS          (30U)
+#define PDS_CR_PDS_MISC_ISO_EN_LEN          (1U)
+#define PDS_CR_PDS_MISC_ISO_EN_MSK          (((1U << PDS_CR_PDS_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_MISC_ISO_EN_POS)
+#define PDS_CR_PDS_MISC_ISO_EN_UMSK         (~(((1U << PDS_CR_PDS_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_MISC_ISO_EN_POS))
+
+/* 0x18 : PDS_CTL4 */
+#define PDS_CTL4_OFFSET                  (0x18)
+#define PDS_CR_PDS_NP_PWR_OFF            PDS_CR_PDS_NP_PWR_OFF
+#define PDS_CR_PDS_NP_PWR_OFF_POS        (0U)
+#define PDS_CR_PDS_NP_PWR_OFF_LEN        (1U)
+#define PDS_CR_PDS_NP_PWR_OFF_MSK        (((1U << PDS_CR_PDS_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_NP_PWR_OFF_POS)
+#define PDS_CR_PDS_NP_PWR_OFF_UMSK       (~(((1U << PDS_CR_PDS_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_NP_PWR_OFF_POS))
+#define PDS_CR_PDS_NP_RESET              PDS_CR_PDS_NP_RESET
+#define PDS_CR_PDS_NP_RESET_POS          (1U)
+#define PDS_CR_PDS_NP_RESET_LEN          (1U)
+#define PDS_CR_PDS_NP_RESET_MSK          (((1U << PDS_CR_PDS_NP_RESET_LEN) - 1) << PDS_CR_PDS_NP_RESET_POS)
+#define PDS_CR_PDS_NP_RESET_UMSK         (~(((1U << PDS_CR_PDS_NP_RESET_LEN) - 1) << PDS_CR_PDS_NP_RESET_POS))
+#define PDS_CR_PDS_NP_MEM_STBY           PDS_CR_PDS_NP_MEM_STBY
+#define PDS_CR_PDS_NP_MEM_STBY_POS       (2U)
+#define PDS_CR_PDS_NP_MEM_STBY_LEN       (1U)
+#define PDS_CR_PDS_NP_MEM_STBY_MSK       (((1U << PDS_CR_PDS_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_NP_MEM_STBY_POS)
+#define PDS_CR_PDS_NP_MEM_STBY_UMSK      (~(((1U << PDS_CR_PDS_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_NP_MEM_STBY_POS))
+#define PDS_CR_PDS_NP_GATE_CLK           PDS_CR_PDS_NP_GATE_CLK
+#define PDS_CR_PDS_NP_GATE_CLK_POS       (3U)
+#define PDS_CR_PDS_NP_GATE_CLK_LEN       (1U)
+#define PDS_CR_PDS_NP_GATE_CLK_MSK       (((1U << PDS_CR_PDS_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_NP_GATE_CLK_POS)
+#define PDS_CR_PDS_NP_GATE_CLK_UMSK      (~(((1U << PDS_CR_PDS_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_NP_GATE_CLK_POS))
+#define PDS_CR_PDS_BZ_PWR_OFF            PDS_CR_PDS_BZ_PWR_OFF
+#define PDS_CR_PDS_BZ_PWR_OFF_POS        (12U)
+#define PDS_CR_PDS_BZ_PWR_OFF_LEN        (1U)
+#define PDS_CR_PDS_BZ_PWR_OFF_MSK        (((1U << PDS_CR_PDS_BZ_PWR_OFF_LEN) - 1) << PDS_CR_PDS_BZ_PWR_OFF_POS)
+#define PDS_CR_PDS_BZ_PWR_OFF_UMSK       (~(((1U << PDS_CR_PDS_BZ_PWR_OFF_LEN) - 1) << PDS_CR_PDS_BZ_PWR_OFF_POS))
+#define PDS_CR_PDS_BZ_RESET              PDS_CR_PDS_BZ_RESET
+#define PDS_CR_PDS_BZ_RESET_POS          (13U)
+#define PDS_CR_PDS_BZ_RESET_LEN          (1U)
+#define PDS_CR_PDS_BZ_RESET_MSK          (((1U << PDS_CR_PDS_BZ_RESET_LEN) - 1) << PDS_CR_PDS_BZ_RESET_POS)
+#define PDS_CR_PDS_BZ_RESET_UMSK         (~(((1U << PDS_CR_PDS_BZ_RESET_LEN) - 1) << PDS_CR_PDS_BZ_RESET_POS))
+#define PDS_CR_PDS_BZ_MEM_STBY           PDS_CR_PDS_BZ_MEM_STBY
+#define PDS_CR_PDS_BZ_MEM_STBY_POS       (14U)
+#define PDS_CR_PDS_BZ_MEM_STBY_LEN       (1U)
+#define PDS_CR_PDS_BZ_MEM_STBY_MSK       (((1U << PDS_CR_PDS_BZ_MEM_STBY_LEN) - 1) << PDS_CR_PDS_BZ_MEM_STBY_POS)
+#define PDS_CR_PDS_BZ_MEM_STBY_UMSK      (~(((1U << PDS_CR_PDS_BZ_MEM_STBY_LEN) - 1) << PDS_CR_PDS_BZ_MEM_STBY_POS))
+#define PDS_CR_PDS_BZ_GATE_CLK           PDS_CR_PDS_BZ_GATE_CLK
+#define PDS_CR_PDS_BZ_GATE_CLK_POS       (15U)
+#define PDS_CR_PDS_BZ_GATE_CLK_LEN       (1U)
+#define PDS_CR_PDS_BZ_GATE_CLK_MSK       (((1U << PDS_CR_PDS_BZ_GATE_CLK_LEN) - 1) << PDS_CR_PDS_BZ_GATE_CLK_POS)
+#define PDS_CR_PDS_BZ_GATE_CLK_UMSK      (~(((1U << PDS_CR_PDS_BZ_GATE_CLK_LEN) - 1) << PDS_CR_PDS_BZ_GATE_CLK_POS))
+#define PDS_CR_PDS_BLE_PWR_OFF           PDS_CR_PDS_BLE_PWR_OFF
+#define PDS_CR_PDS_BLE_PWR_OFF_POS       (16U)
+#define PDS_CR_PDS_BLE_PWR_OFF_LEN       (1U)
+#define PDS_CR_PDS_BLE_PWR_OFF_MSK       (((1U << PDS_CR_PDS_BLE_PWR_OFF_LEN) - 1) << PDS_CR_PDS_BLE_PWR_OFF_POS)
+#define PDS_CR_PDS_BLE_PWR_OFF_UMSK      (~(((1U << PDS_CR_PDS_BLE_PWR_OFF_LEN) - 1) << PDS_CR_PDS_BLE_PWR_OFF_POS))
+#define PDS_CR_PDS_BLE_RESET             PDS_CR_PDS_BLE_RESET
+#define PDS_CR_PDS_BLE_RESET_POS         (17U)
+#define PDS_CR_PDS_BLE_RESET_LEN         (1U)
+#define PDS_CR_PDS_BLE_RESET_MSK         (((1U << PDS_CR_PDS_BLE_RESET_LEN) - 1) << PDS_CR_PDS_BLE_RESET_POS)
+#define PDS_CR_PDS_BLE_RESET_UMSK        (~(((1U << PDS_CR_PDS_BLE_RESET_LEN) - 1) << PDS_CR_PDS_BLE_RESET_POS))
+#define PDS_CR_PDS_BLE_MEM_STBY          PDS_CR_PDS_BLE_MEM_STBY
+#define PDS_CR_PDS_BLE_MEM_STBY_POS      (18U)
+#define PDS_CR_PDS_BLE_MEM_STBY_LEN      (1U)
+#define PDS_CR_PDS_BLE_MEM_STBY_MSK      (((1U << PDS_CR_PDS_BLE_MEM_STBY_LEN) - 1) << PDS_CR_PDS_BLE_MEM_STBY_POS)
+#define PDS_CR_PDS_BLE_MEM_STBY_UMSK     (~(((1U << PDS_CR_PDS_BLE_MEM_STBY_LEN) - 1) << PDS_CR_PDS_BLE_MEM_STBY_POS))
+#define PDS_CR_PDS_BLE_GATE_CLK          PDS_CR_PDS_BLE_GATE_CLK
+#define PDS_CR_PDS_BLE_GATE_CLK_POS      (19U)
+#define PDS_CR_PDS_BLE_GATE_CLK_LEN      (1U)
+#define PDS_CR_PDS_BLE_GATE_CLK_MSK      (((1U << PDS_CR_PDS_BLE_GATE_CLK_LEN) - 1) << PDS_CR_PDS_BLE_GATE_CLK_POS)
+#define PDS_CR_PDS_BLE_GATE_CLK_UMSK     (~(((1U << PDS_CR_PDS_BLE_GATE_CLK_LEN) - 1) << PDS_CR_PDS_BLE_GATE_CLK_POS))
+#define PDS_CR_PDS_USB_PWR_OFF           PDS_CR_PDS_USB_PWR_OFF
+#define PDS_CR_PDS_USB_PWR_OFF_POS       (20U)
+#define PDS_CR_PDS_USB_PWR_OFF_LEN       (1U)
+#define PDS_CR_PDS_USB_PWR_OFF_MSK       (((1U << PDS_CR_PDS_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_USB_PWR_OFF_POS)
+#define PDS_CR_PDS_USB_PWR_OFF_UMSK      (~(((1U << PDS_CR_PDS_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_USB_PWR_OFF_POS))
+#define PDS_CR_PDS_USB_RESET             PDS_CR_PDS_USB_RESET
+#define PDS_CR_PDS_USB_RESET_POS         (21U)
+#define PDS_CR_PDS_USB_RESET_LEN         (1U)
+#define PDS_CR_PDS_USB_RESET_MSK         (((1U << PDS_CR_PDS_USB_RESET_LEN) - 1) << PDS_CR_PDS_USB_RESET_POS)
+#define PDS_CR_PDS_USB_RESET_UMSK        (~(((1U << PDS_CR_PDS_USB_RESET_LEN) - 1) << PDS_CR_PDS_USB_RESET_POS))
+#define PDS_CR_PDS_USB_MEM_STBY          PDS_CR_PDS_USB_MEM_STBY
+#define PDS_CR_PDS_USB_MEM_STBY_POS      (22U)
+#define PDS_CR_PDS_USB_MEM_STBY_LEN      (1U)
+#define PDS_CR_PDS_USB_MEM_STBY_MSK      (((1U << PDS_CR_PDS_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_USB_MEM_STBY_POS)
+#define PDS_CR_PDS_USB_MEM_STBY_UMSK     (~(((1U << PDS_CR_PDS_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_USB_MEM_STBY_POS))
+#define PDS_CR_PDS_USB_GATE_CLK          PDS_CR_PDS_USB_GATE_CLK
+#define PDS_CR_PDS_USB_GATE_CLK_POS      (23U)
+#define PDS_CR_PDS_USB_GATE_CLK_LEN      (1U)
+#define PDS_CR_PDS_USB_GATE_CLK_MSK      (((1U << PDS_CR_PDS_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_USB_GATE_CLK_POS)
+#define PDS_CR_PDS_USB_GATE_CLK_UMSK     (~(((1U << PDS_CR_PDS_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_USB_GATE_CLK_POS))
+#define PDS_CR_PDS_MISC_PWR_OFF          PDS_CR_PDS_MISC_PWR_OFF
+#define PDS_CR_PDS_MISC_PWR_OFF_POS      (24U)
+#define PDS_CR_PDS_MISC_PWR_OFF_LEN      (1U)
+#define PDS_CR_PDS_MISC_PWR_OFF_MSK      (((1U << PDS_CR_PDS_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_PWR_OFF_POS)
+#define PDS_CR_PDS_MISC_PWR_OFF_UMSK     (~(((1U << PDS_CR_PDS_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_PWR_OFF_POS))
+#define PDS_CR_PDS_MISC_RESET            PDS_CR_PDS_MISC_RESET
+#define PDS_CR_PDS_MISC_RESET_POS        (25U)
+#define PDS_CR_PDS_MISC_RESET_LEN        (1U)
+#define PDS_CR_PDS_MISC_RESET_MSK        (((1U << PDS_CR_PDS_MISC_RESET_LEN) - 1) << PDS_CR_PDS_MISC_RESET_POS)
+#define PDS_CR_PDS_MISC_RESET_UMSK       (~(((1U << PDS_CR_PDS_MISC_RESET_LEN) - 1) << PDS_CR_PDS_MISC_RESET_POS))
+#define PDS_CR_PDS_MISC_MEM_STBY         PDS_CR_PDS_MISC_MEM_STBY
+#define PDS_CR_PDS_MISC_MEM_STBY_POS     (26U)
+#define PDS_CR_PDS_MISC_MEM_STBY_LEN     (1U)
+#define PDS_CR_PDS_MISC_MEM_STBY_MSK     (((1U << PDS_CR_PDS_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MISC_MEM_STBY_POS)
+#define PDS_CR_PDS_MISC_MEM_STBY_UMSK    (~(((1U << PDS_CR_PDS_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MISC_MEM_STBY_POS))
+#define PDS_CR_PDS_MISC_GATE_CLK         PDS_CR_PDS_MISC_GATE_CLK
+#define PDS_CR_PDS_MISC_GATE_CLK_POS     (27U)
+#define PDS_CR_PDS_MISC_GATE_CLK_LEN     (1U)
+#define PDS_CR_PDS_MISC_GATE_CLK_MSK     (((1U << PDS_CR_PDS_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_MISC_GATE_CLK_POS)
+#define PDS_CR_PDS_MISC_GATE_CLK_UMSK    (~(((1U << PDS_CR_PDS_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_MISC_GATE_CLK_POS))
+#define PDS_CR_PDS_MISC_ANA_PWR_OFF      PDS_CR_PDS_MISC_ANA_PWR_OFF
+#define PDS_CR_PDS_MISC_ANA_PWR_OFF_POS  (30U)
+#define PDS_CR_PDS_MISC_ANA_PWR_OFF_LEN  (1U)
+#define PDS_CR_PDS_MISC_ANA_PWR_OFF_MSK  (((1U << PDS_CR_PDS_MISC_ANA_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_ANA_PWR_OFF_POS)
+#define PDS_CR_PDS_MISC_ANA_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_MISC_ANA_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_ANA_PWR_OFF_POS))
+#define PDS_CR_PDS_MISC_DIG_PWR_OFF      PDS_CR_PDS_MISC_DIG_PWR_OFF
+#define PDS_CR_PDS_MISC_DIG_PWR_OFF_POS  (31U)
+#define PDS_CR_PDS_MISC_DIG_PWR_OFF_LEN  (1U)
+#define PDS_CR_PDS_MISC_DIG_PWR_OFF_MSK  (((1U << PDS_CR_PDS_MISC_DIG_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_DIG_PWR_OFF_POS)
+#define PDS_CR_PDS_MISC_DIG_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_MISC_DIG_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_DIG_PWR_OFF_POS))
+
+/* 0x1C : pds_stat */
+#define PDS_STAT_OFFSET           (0x1C)
+#define PDS_RO_PDS_STATE          PDS_RO_PDS_STATE
+#define PDS_RO_PDS_STATE_POS      (0U)
+#define PDS_RO_PDS_STATE_LEN      (4U)
+#define PDS_RO_PDS_STATE_MSK      (((1U << PDS_RO_PDS_STATE_LEN) - 1) << PDS_RO_PDS_STATE_POS)
+#define PDS_RO_PDS_STATE_UMSK     (~(((1U << PDS_RO_PDS_STATE_LEN) - 1) << PDS_RO_PDS_STATE_POS))
+#define PDS_RO_PDS_RF_STATE       PDS_RO_PDS_RF_STATE
+#define PDS_RO_PDS_RF_STATE_POS   (8U)
+#define PDS_RO_PDS_RF_STATE_LEN   (4U)
+#define PDS_RO_PDS_RF_STATE_MSK   (((1U << PDS_RO_PDS_RF_STATE_LEN) - 1) << PDS_RO_PDS_RF_STATE_POS)
+#define PDS_RO_PDS_RF_STATE_UMSK  (~(((1U << PDS_RO_PDS_RF_STATE_LEN) - 1) << PDS_RO_PDS_RF_STATE_POS))
+#define PDS_RO_PDS_PLL_STATE      PDS_RO_PDS_PLL_STATE
+#define PDS_RO_PDS_PLL_STATE_POS  (16U)
+#define PDS_RO_PDS_PLL_STATE_LEN  (2U)
+#define PDS_RO_PDS_PLL_STATE_MSK  (((1U << PDS_RO_PDS_PLL_STATE_LEN) - 1) << PDS_RO_PDS_PLL_STATE_POS)
+#define PDS_RO_PDS_PLL_STATE_UMSK (~(((1U << PDS_RO_PDS_PLL_STATE_LEN) - 1) << PDS_RO_PDS_PLL_STATE_POS))
+
+/* 0x20 : pds_ram1 */
+#define PDS_RAM1_OFFSET           (0x20)
+#define PDS_CR_PDS_RAM_RET1N      PDS_CR_PDS_RAM_RET1N
+#define PDS_CR_PDS_RAM_RET1N_POS  (0U)
+#define PDS_CR_PDS_RAM_RET1N_LEN  (4U)
+#define PDS_CR_PDS_RAM_RET1N_MSK  (((1U << PDS_CR_PDS_RAM_RET1N_LEN) - 1) << PDS_CR_PDS_RAM_RET1N_POS)
+#define PDS_CR_PDS_RAM_RET1N_UMSK (~(((1U << PDS_CR_PDS_RAM_RET1N_LEN) - 1) << PDS_CR_PDS_RAM_RET1N_POS))
+#define PDS_CR_PDS_RAM_RET2N      PDS_CR_PDS_RAM_RET2N
+#define PDS_CR_PDS_RAM_RET2N_POS  (4U)
+#define PDS_CR_PDS_RAM_RET2N_LEN  (4U)
+#define PDS_CR_PDS_RAM_RET2N_MSK  (((1U << PDS_CR_PDS_RAM_RET2N_LEN) - 1) << PDS_CR_PDS_RAM_RET2N_POS)
+#define PDS_CR_PDS_RAM_RET2N_UMSK (~(((1U << PDS_CR_PDS_RAM_RET2N_LEN) - 1) << PDS_CR_PDS_RAM_RET2N_POS))
+#define PDS_CR_PDS_RAM_PGEN       PDS_CR_PDS_RAM_PGEN
+#define PDS_CR_PDS_RAM_PGEN_POS   (8U)
+#define PDS_CR_PDS_RAM_PGEN_LEN   (4U)
+#define PDS_CR_PDS_RAM_PGEN_MSK   (((1U << PDS_CR_PDS_RAM_PGEN_LEN) - 1) << PDS_CR_PDS_RAM_PGEN_POS)
+#define PDS_CR_PDS_RAM_PGEN_UMSK  (~(((1U << PDS_CR_PDS_RAM_PGEN_LEN) - 1) << PDS_CR_PDS_RAM_PGEN_POS))
+
+/* 0x30 : pds_gpio_set_pu_pd */
+#define PDS_GPIO_SET_PU_PD_OFFSET     (0x30)
+#define PDS_CR_PDS_GPIO_22_17_PD      PDS_CR_PDS_GPIO_22_17_PD
+#define PDS_CR_PDS_GPIO_22_17_PD_POS  (0U)
+#define PDS_CR_PDS_GPIO_22_17_PD_LEN  (6U)
+#define PDS_CR_PDS_GPIO_22_17_PD_MSK  (((1U << PDS_CR_PDS_GPIO_22_17_PD_LEN) - 1) << PDS_CR_PDS_GPIO_22_17_PD_POS)
+#define PDS_CR_PDS_GPIO_22_17_PD_UMSK (~(((1U << PDS_CR_PDS_GPIO_22_17_PD_LEN) - 1) << PDS_CR_PDS_GPIO_22_17_PD_POS))
+#define PDS_CR_PDS_GPIO_22_17_PU      PDS_CR_PDS_GPIO_22_17_PU
+#define PDS_CR_PDS_GPIO_22_17_PU_POS  (8U)
+#define PDS_CR_PDS_GPIO_22_17_PU_LEN  (6U)
+#define PDS_CR_PDS_GPIO_22_17_PU_MSK  (((1U << PDS_CR_PDS_GPIO_22_17_PU_LEN) - 1) << PDS_CR_PDS_GPIO_22_17_PU_POS)
+#define PDS_CR_PDS_GPIO_22_17_PU_UMSK (~(((1U << PDS_CR_PDS_GPIO_22_17_PU_LEN) - 1) << PDS_CR_PDS_GPIO_22_17_PU_POS))
+#define PDS_CR_PDS_GPIO_28_23_PD      PDS_CR_PDS_GPIO_28_23_PD
+#define PDS_CR_PDS_GPIO_28_23_PD_POS  (16U)
+#define PDS_CR_PDS_GPIO_28_23_PD_LEN  (6U)
+#define PDS_CR_PDS_GPIO_28_23_PD_MSK  (((1U << PDS_CR_PDS_GPIO_28_23_PD_LEN) - 1) << PDS_CR_PDS_GPIO_28_23_PD_POS)
+#define PDS_CR_PDS_GPIO_28_23_PD_UMSK (~(((1U << PDS_CR_PDS_GPIO_28_23_PD_LEN) - 1) << PDS_CR_PDS_GPIO_28_23_PD_POS))
+#define PDS_CR_PDS_GPIO_28_23_PU      PDS_CR_PDS_GPIO_28_23_PU
+#define PDS_CR_PDS_GPIO_28_23_PU_POS  (24U)
+#define PDS_CR_PDS_GPIO_28_23_PU_LEN  (6U)
+#define PDS_CR_PDS_GPIO_28_23_PU_MSK  (((1U << PDS_CR_PDS_GPIO_28_23_PU_LEN) - 1) << PDS_CR_PDS_GPIO_28_23_PU_POS)
+#define PDS_CR_PDS_GPIO_28_23_PU_UMSK (~(((1U << PDS_CR_PDS_GPIO_28_23_PU_LEN) - 1) << PDS_CR_PDS_GPIO_28_23_PU_POS))
+
+/* 0x40 : pds_gpio_int */
+#define PDS_GPIO_INT_OFFSET      (0x40)
+#define PDS_GPIO_INT_MASK        PDS_GPIO_INT_MASK
+#define PDS_GPIO_INT_MASK_POS    (0U)
+#define PDS_GPIO_INT_MASK_LEN    (1U)
+#define PDS_GPIO_INT_MASK_MSK    (((1U << PDS_GPIO_INT_MASK_LEN) - 1) << PDS_GPIO_INT_MASK_POS)
+#define PDS_GPIO_INT_MASK_UMSK   (~(((1U << PDS_GPIO_INT_MASK_LEN) - 1) << PDS_GPIO_INT_MASK_POS))
+#define PDS_GPIO_INT_STAT        PDS_GPIO_INT_STAT
+#define PDS_GPIO_INT_STAT_POS    (1U)
+#define PDS_GPIO_INT_STAT_LEN    (1U)
+#define PDS_GPIO_INT_STAT_MSK    (((1U << PDS_GPIO_INT_STAT_LEN) - 1) << PDS_GPIO_INT_STAT_POS)
+#define PDS_GPIO_INT_STAT_UMSK   (~(((1U << PDS_GPIO_INT_STAT_LEN) - 1) << PDS_GPIO_INT_STAT_POS))
+#define PDS_GPIO_INT_CLR         PDS_GPIO_INT_CLR
+#define PDS_GPIO_INT_CLR_POS     (2U)
+#define PDS_GPIO_INT_CLR_LEN     (1U)
+#define PDS_GPIO_INT_CLR_MSK     (((1U << PDS_GPIO_INT_CLR_LEN) - 1) << PDS_GPIO_INT_CLR_POS)
+#define PDS_GPIO_INT_CLR_UMSK    (~(((1U << PDS_GPIO_INT_CLR_LEN) - 1) << PDS_GPIO_INT_CLR_POS))
+#define PDS_GPIO_INT_MODE        PDS_GPIO_INT_MODE
+#define PDS_GPIO_INT_MODE_POS    (4U)
+#define PDS_GPIO_INT_MODE_LEN    (3U)
+#define PDS_GPIO_INT_MODE_MSK    (((1U << PDS_GPIO_INT_MODE_LEN) - 1) << PDS_GPIO_INT_MODE_POS)
+#define PDS_GPIO_INT_MODE_UMSK   (~(((1U << PDS_GPIO_INT_MODE_LEN) - 1) << PDS_GPIO_INT_MODE_POS))
+#define PDS_GPIO_INT_SELECT      PDS_GPIO_INT_SELECT
+#define PDS_GPIO_INT_SELECT_POS  (8U)
+#define PDS_GPIO_INT_SELECT_LEN  (3U)
+#define PDS_GPIO_INT_SELECT_MSK  (((1U << PDS_GPIO_INT_SELECT_LEN) - 1) << PDS_GPIO_INT_SELECT_POS)
+#define PDS_GPIO_INT_SELECT_UMSK (~(((1U << PDS_GPIO_INT_SELECT_LEN) - 1) << PDS_GPIO_INT_SELECT_POS))
+
+/* 0x300 : rc32m_ctrl0 */
+#define PDS_RC32M_CTRL0_OFFSET         (0x300)
+#define PDS_RC32M_CAL_DONE             PDS_RC32M_CAL_DONE
+#define PDS_RC32M_CAL_DONE_POS         (0U)
+#define PDS_RC32M_CAL_DONE_LEN         (1U)
+#define PDS_RC32M_CAL_DONE_MSK         (((1U << PDS_RC32M_CAL_DONE_LEN) - 1) << PDS_RC32M_CAL_DONE_POS)
+#define PDS_RC32M_CAL_DONE_UMSK        (~(((1U << PDS_RC32M_CAL_DONE_LEN) - 1) << PDS_RC32M_CAL_DONE_POS))
+#define PDS_RC32M_RDY                  PDS_RC32M_RDY
+#define PDS_RC32M_RDY_POS              (1U)
+#define PDS_RC32M_RDY_LEN              (1U)
+#define PDS_RC32M_RDY_MSK              (((1U << PDS_RC32M_RDY_LEN) - 1) << PDS_RC32M_RDY_POS)
+#define PDS_RC32M_RDY_UMSK             (~(((1U << PDS_RC32M_RDY_LEN) - 1) << PDS_RC32M_RDY_POS))
+#define PDS_RC32M_CAL_INPROGRESS       PDS_RC32M_CAL_INPROGRESS
+#define PDS_RC32M_CAL_INPROGRESS_POS   (2U)
+#define PDS_RC32M_CAL_INPROGRESS_LEN   (1U)
+#define PDS_RC32M_CAL_INPROGRESS_MSK   (((1U << PDS_RC32M_CAL_INPROGRESS_LEN) - 1) << PDS_RC32M_CAL_INPROGRESS_POS)
+#define PDS_RC32M_CAL_INPROGRESS_UMSK  (~(((1U << PDS_RC32M_CAL_INPROGRESS_LEN) - 1) << PDS_RC32M_CAL_INPROGRESS_POS))
+#define PDS_RC32M_CAL_DIV              PDS_RC32M_CAL_DIV
+#define PDS_RC32M_CAL_DIV_POS          (3U)
+#define PDS_RC32M_CAL_DIV_LEN          (2U)
+#define PDS_RC32M_CAL_DIV_MSK          (((1U << PDS_RC32M_CAL_DIV_LEN) - 1) << PDS_RC32M_CAL_DIV_POS)
+#define PDS_RC32M_CAL_DIV_UMSK         (~(((1U << PDS_RC32M_CAL_DIV_LEN) - 1) << PDS_RC32M_CAL_DIV_POS))
+#define PDS_RC32M_CAL_PRECHARGE        PDS_RC32M_CAL_PRECHARGE
+#define PDS_RC32M_CAL_PRECHARGE_POS    (5U)
+#define PDS_RC32M_CAL_PRECHARGE_LEN    (1U)
+#define PDS_RC32M_CAL_PRECHARGE_MSK    (((1U << PDS_RC32M_CAL_PRECHARGE_LEN) - 1) << PDS_RC32M_CAL_PRECHARGE_POS)
+#define PDS_RC32M_CAL_PRECHARGE_UMSK   (~(((1U << PDS_RC32M_CAL_PRECHARGE_LEN) - 1) << PDS_RC32M_CAL_PRECHARGE_POS))
+#define PDS_RC32M_DIG_CODE_FR_CAL      PDS_RC32M_DIG_CODE_FR_CAL
+#define PDS_RC32M_DIG_CODE_FR_CAL_POS  (6U)
+#define PDS_RC32M_DIG_CODE_FR_CAL_LEN  (8U)
+#define PDS_RC32M_DIG_CODE_FR_CAL_MSK  (((1U << PDS_RC32M_DIG_CODE_FR_CAL_LEN) - 1) << PDS_RC32M_DIG_CODE_FR_CAL_POS)
+#define PDS_RC32M_DIG_CODE_FR_CAL_UMSK (~(((1U << PDS_RC32M_DIG_CODE_FR_CAL_LEN) - 1) << PDS_RC32M_DIG_CODE_FR_CAL_POS))
+#define PDS_RC32M_ALLOW_CAL            PDS_RC32M_ALLOW_CAL
+#define PDS_RC32M_ALLOW_CAL_POS        (17U)
+#define PDS_RC32M_ALLOW_CAL_LEN        (1U)
+#define PDS_RC32M_ALLOW_CAL_MSK        (((1U << PDS_RC32M_ALLOW_CAL_LEN) - 1) << PDS_RC32M_ALLOW_CAL_POS)
+#define PDS_RC32M_ALLOW_CAL_UMSK       (~(((1U << PDS_RC32M_ALLOW_CAL_LEN) - 1) << PDS_RC32M_ALLOW_CAL_POS))
+#define PDS_RC32M_REFCLK_HALF          PDS_RC32M_REFCLK_HALF
+#define PDS_RC32M_REFCLK_HALF_POS      (18U)
+#define PDS_RC32M_REFCLK_HALF_LEN      (1U)
+#define PDS_RC32M_REFCLK_HALF_MSK      (((1U << PDS_RC32M_REFCLK_HALF_LEN) - 1) << PDS_RC32M_REFCLK_HALF_POS)
+#define PDS_RC32M_REFCLK_HALF_UMSK     (~(((1U << PDS_RC32M_REFCLK_HALF_LEN) - 1) << PDS_RC32M_REFCLK_HALF_POS))
+#define PDS_RC32M_EXT_CODE_EN          PDS_RC32M_EXT_CODE_EN
+#define PDS_RC32M_EXT_CODE_EN_POS      (19U)
+#define PDS_RC32M_EXT_CODE_EN_LEN      (1U)
+#define PDS_RC32M_EXT_CODE_EN_MSK      (((1U << PDS_RC32M_EXT_CODE_EN_LEN) - 1) << PDS_RC32M_EXT_CODE_EN_POS)
+#define PDS_RC32M_EXT_CODE_EN_UMSK     (~(((1U << PDS_RC32M_EXT_CODE_EN_LEN) - 1) << PDS_RC32M_EXT_CODE_EN_POS))
+#define PDS_RC32M_CAL_EN               PDS_RC32M_CAL_EN
+#define PDS_RC32M_CAL_EN_POS           (20U)
+#define PDS_RC32M_CAL_EN_LEN           (1U)
+#define PDS_RC32M_CAL_EN_MSK           (((1U << PDS_RC32M_CAL_EN_LEN) - 1) << PDS_RC32M_CAL_EN_POS)
+#define PDS_RC32M_CAL_EN_UMSK          (~(((1U << PDS_RC32M_CAL_EN_LEN) - 1) << PDS_RC32M_CAL_EN_POS))
+#define PDS_RC32M_PD                   PDS_RC32M_PD
+#define PDS_RC32M_PD_POS               (21U)
+#define PDS_RC32M_PD_LEN               (1U)
+#define PDS_RC32M_PD_MSK               (((1U << PDS_RC32M_PD_LEN) - 1) << PDS_RC32M_PD_POS)
+#define PDS_RC32M_PD_UMSK              (~(((1U << PDS_RC32M_PD_LEN) - 1) << PDS_RC32M_PD_POS))
+#define PDS_RC32M_CODE_FR_EXT          PDS_RC32M_CODE_FR_EXT
+#define PDS_RC32M_CODE_FR_EXT_POS      (22U)
+#define PDS_RC32M_CODE_FR_EXT_LEN      (8U)
+#define PDS_RC32M_CODE_FR_EXT_MSK      (((1U << PDS_RC32M_CODE_FR_EXT_LEN) - 1) << PDS_RC32M_CODE_FR_EXT_POS)
+#define PDS_RC32M_CODE_FR_EXT_UMSK     (~(((1U << PDS_RC32M_CODE_FR_EXT_LEN) - 1) << PDS_RC32M_CODE_FR_EXT_POS))
+
+/* 0x304 : rc32m_ctrl1 */
+#define PDS_RC32M_CTRL1_OFFSET      (0x304)
+#define PDS_RC32M_TEST_EN           PDS_RC32M_TEST_EN
+#define PDS_RC32M_TEST_EN_POS       (0U)
+#define PDS_RC32M_TEST_EN_LEN       (1U)
+#define PDS_RC32M_TEST_EN_MSK       (((1U << PDS_RC32M_TEST_EN_LEN) - 1) << PDS_RC32M_TEST_EN_POS)
+#define PDS_RC32M_TEST_EN_UMSK      (~(((1U << PDS_RC32M_TEST_EN_LEN) - 1) << PDS_RC32M_TEST_EN_POS))
+#define PDS_RC32M_SOFT_RST          PDS_RC32M_SOFT_RST
+#define PDS_RC32M_SOFT_RST_POS      (1U)
+#define PDS_RC32M_SOFT_RST_LEN      (1U)
+#define PDS_RC32M_SOFT_RST_MSK      (((1U << PDS_RC32M_SOFT_RST_LEN) - 1) << PDS_RC32M_SOFT_RST_POS)
+#define PDS_RC32M_SOFT_RST_UMSK     (~(((1U << PDS_RC32M_SOFT_RST_LEN) - 1) << PDS_RC32M_SOFT_RST_POS))
+#define PDS_RC32M_CLK_SOFT_RST      PDS_RC32M_CLK_SOFT_RST
+#define PDS_RC32M_CLK_SOFT_RST_POS  (2U)
+#define PDS_RC32M_CLK_SOFT_RST_LEN  (1U)
+#define PDS_RC32M_CLK_SOFT_RST_MSK  (((1U << PDS_RC32M_CLK_SOFT_RST_LEN) - 1) << PDS_RC32M_CLK_SOFT_RST_POS)
+#define PDS_RC32M_CLK_SOFT_RST_UMSK (~(((1U << PDS_RC32M_CLK_SOFT_RST_LEN) - 1) << PDS_RC32M_CLK_SOFT_RST_POS))
+#define PDS_RC32M_CLK_INV           PDS_RC32M_CLK_INV
+#define PDS_RC32M_CLK_INV_POS       (3U)
+#define PDS_RC32M_CLK_INV_LEN       (1U)
+#define PDS_RC32M_CLK_INV_MSK       (((1U << PDS_RC32M_CLK_INV_LEN) - 1) << PDS_RC32M_CLK_INV_POS)
+#define PDS_RC32M_CLK_INV_UMSK      (~(((1U << PDS_RC32M_CLK_INV_LEN) - 1) << PDS_RC32M_CLK_INV_POS))
+#define PDS_RC32M_CLK_FORCE_ON      PDS_RC32M_CLK_FORCE_ON
+#define PDS_RC32M_CLK_FORCE_ON_POS  (4U)
+#define PDS_RC32M_CLK_FORCE_ON_LEN  (1U)
+#define PDS_RC32M_CLK_FORCE_ON_MSK  (((1U << PDS_RC32M_CLK_FORCE_ON_LEN) - 1) << PDS_RC32M_CLK_FORCE_ON_POS)
+#define PDS_RC32M_CLK_FORCE_ON_UMSK (~(((1U << PDS_RC32M_CLK_FORCE_ON_LEN) - 1) << PDS_RC32M_CLK_FORCE_ON_POS))
+#define PDS_RC32M_RESERVED          PDS_RC32M_RESERVED
+#define PDS_RC32M_RESERVED_POS      (24U)
+#define PDS_RC32M_RESERVED_LEN      (8U)
+#define PDS_RC32M_RESERVED_MSK      (((1U << PDS_RC32M_RESERVED_LEN) - 1) << PDS_RC32M_RESERVED_POS)
+#define PDS_RC32M_RESERVED_UMSK     (~(((1U << PDS_RC32M_RESERVED_LEN) - 1) << PDS_RC32M_RESERVED_POS))
+
+/* 0x400 : pu_rst_clkpll */
+#define PDS_PU_RST_CLKPLL_OFFSET      (0x400)
+#define PDS_CLKPLL_SDM_RESET          PDS_CLKPLL_SDM_RESET
+#define PDS_CLKPLL_SDM_RESET_POS      (0U)
+#define PDS_CLKPLL_SDM_RESET_LEN      (1U)
+#define PDS_CLKPLL_SDM_RESET_MSK      (((1U << PDS_CLKPLL_SDM_RESET_LEN) - 1) << PDS_CLKPLL_SDM_RESET_POS)
+#define PDS_CLKPLL_SDM_RESET_UMSK     (~(((1U << PDS_CLKPLL_SDM_RESET_LEN) - 1) << PDS_CLKPLL_SDM_RESET_POS))
+#define PDS_CLKPLL_RESET_POSTDIV      PDS_CLKPLL_RESET_POSTDIV
+#define PDS_CLKPLL_RESET_POSTDIV_POS  (1U)
+#define PDS_CLKPLL_RESET_POSTDIV_LEN  (1U)
+#define PDS_CLKPLL_RESET_POSTDIV_MSK  (((1U << PDS_CLKPLL_RESET_POSTDIV_LEN) - 1) << PDS_CLKPLL_RESET_POSTDIV_POS)
+#define PDS_CLKPLL_RESET_POSTDIV_UMSK (~(((1U << PDS_CLKPLL_RESET_POSTDIV_LEN) - 1) << PDS_CLKPLL_RESET_POSTDIV_POS))
+#define PDS_CLKPLL_RESET_FBDV         PDS_CLKPLL_RESET_FBDV
+#define PDS_CLKPLL_RESET_FBDV_POS     (2U)
+#define PDS_CLKPLL_RESET_FBDV_LEN     (1U)
+#define PDS_CLKPLL_RESET_FBDV_MSK     (((1U << PDS_CLKPLL_RESET_FBDV_LEN) - 1) << PDS_CLKPLL_RESET_FBDV_POS)
+#define PDS_CLKPLL_RESET_FBDV_UMSK    (~(((1U << PDS_CLKPLL_RESET_FBDV_LEN) - 1) << PDS_CLKPLL_RESET_FBDV_POS))
+#define PDS_CLKPLL_RESET_REFDIV       PDS_CLKPLL_RESET_REFDIV
+#define PDS_CLKPLL_RESET_REFDIV_POS   (3U)
+#define PDS_CLKPLL_RESET_REFDIV_LEN   (1U)
+#define PDS_CLKPLL_RESET_REFDIV_MSK   (((1U << PDS_CLKPLL_RESET_REFDIV_LEN) - 1) << PDS_CLKPLL_RESET_REFDIV_POS)
+#define PDS_CLKPLL_RESET_REFDIV_UMSK  (~(((1U << PDS_CLKPLL_RESET_REFDIV_LEN) - 1) << PDS_CLKPLL_RESET_REFDIV_POS))
+#define PDS_CLKPLL_PU_POSTDIV         PDS_CLKPLL_PU_POSTDIV
+#define PDS_CLKPLL_PU_POSTDIV_POS     (4U)
+#define PDS_CLKPLL_PU_POSTDIV_LEN     (1U)
+#define PDS_CLKPLL_PU_POSTDIV_MSK     (((1U << PDS_CLKPLL_PU_POSTDIV_LEN) - 1) << PDS_CLKPLL_PU_POSTDIV_POS)
+#define PDS_CLKPLL_PU_POSTDIV_UMSK    (~(((1U << PDS_CLKPLL_PU_POSTDIV_LEN) - 1) << PDS_CLKPLL_PU_POSTDIV_POS))
+#define PDS_CLKPLL_PU_FBDV            PDS_CLKPLL_PU_FBDV
+#define PDS_CLKPLL_PU_FBDV_POS        (5U)
+#define PDS_CLKPLL_PU_FBDV_LEN        (1U)
+#define PDS_CLKPLL_PU_FBDV_MSK        (((1U << PDS_CLKPLL_PU_FBDV_LEN) - 1) << PDS_CLKPLL_PU_FBDV_POS)
+#define PDS_CLKPLL_PU_FBDV_UMSK       (~(((1U << PDS_CLKPLL_PU_FBDV_LEN) - 1) << PDS_CLKPLL_PU_FBDV_POS))
+#define PDS_CLKPLL_PU_CLAMP_OP        PDS_CLKPLL_PU_CLAMP_OP
+#define PDS_CLKPLL_PU_CLAMP_OP_POS    (6U)
+#define PDS_CLKPLL_PU_CLAMP_OP_LEN    (1U)
+#define PDS_CLKPLL_PU_CLAMP_OP_MSK    (((1U << PDS_CLKPLL_PU_CLAMP_OP_LEN) - 1) << PDS_CLKPLL_PU_CLAMP_OP_POS)
+#define PDS_CLKPLL_PU_CLAMP_OP_UMSK   (~(((1U << PDS_CLKPLL_PU_CLAMP_OP_LEN) - 1) << PDS_CLKPLL_PU_CLAMP_OP_POS))
+#define PDS_CLKPLL_PU_PFD             PDS_CLKPLL_PU_PFD
+#define PDS_CLKPLL_PU_PFD_POS         (7U)
+#define PDS_CLKPLL_PU_PFD_LEN         (1U)
+#define PDS_CLKPLL_PU_PFD_MSK         (((1U << PDS_CLKPLL_PU_PFD_LEN) - 1) << PDS_CLKPLL_PU_PFD_POS)
+#define PDS_CLKPLL_PU_PFD_UMSK        (~(((1U << PDS_CLKPLL_PU_PFD_LEN) - 1) << PDS_CLKPLL_PU_PFD_POS))
+#define PDS_CLKPLL_PU_CP              PDS_CLKPLL_PU_CP
+#define PDS_CLKPLL_PU_CP_POS          (8U)
+#define PDS_CLKPLL_PU_CP_LEN          (1U)
+#define PDS_CLKPLL_PU_CP_MSK          (((1U << PDS_CLKPLL_PU_CP_LEN) - 1) << PDS_CLKPLL_PU_CP_POS)
+#define PDS_CLKPLL_PU_CP_UMSK         (~(((1U << PDS_CLKPLL_PU_CP_LEN) - 1) << PDS_CLKPLL_PU_CP_POS))
+#define PDS_PU_CLKPLL_SFREG           PDS_PU_CLKPLL_SFREG
+#define PDS_PU_CLKPLL_SFREG_POS       (9U)
+#define PDS_PU_CLKPLL_SFREG_LEN       (1U)
+#define PDS_PU_CLKPLL_SFREG_MSK       (((1U << PDS_PU_CLKPLL_SFREG_LEN) - 1) << PDS_PU_CLKPLL_SFREG_POS)
+#define PDS_PU_CLKPLL_SFREG_UMSK      (~(((1U << PDS_PU_CLKPLL_SFREG_LEN) - 1) << PDS_PU_CLKPLL_SFREG_POS))
+#define PDS_PU_CLKPLL                 PDS_PU_CLKPLL
+#define PDS_PU_CLKPLL_POS             (10U)
+#define PDS_PU_CLKPLL_LEN             (1U)
+#define PDS_PU_CLKPLL_MSK             (((1U << PDS_PU_CLKPLL_LEN) - 1) << PDS_PU_CLKPLL_POS)
+#define PDS_PU_CLKPLL_UMSK            (~(((1U << PDS_PU_CLKPLL_LEN) - 1) << PDS_PU_CLKPLL_POS))
+
+/* 0x404 : clkpll_top_ctrl */
+#define PDS_CLKPLL_TOP_CTRL_OFFSET     (0x404)
+#define PDS_CLKPLL_POSTDIV             PDS_CLKPLL_POSTDIV
+#define PDS_CLKPLL_POSTDIV_POS         (0U)
+#define PDS_CLKPLL_POSTDIV_LEN         (7U)
+#define PDS_CLKPLL_POSTDIV_MSK         (((1U << PDS_CLKPLL_POSTDIV_LEN) - 1) << PDS_CLKPLL_POSTDIV_POS)
+#define PDS_CLKPLL_POSTDIV_UMSK        (~(((1U << PDS_CLKPLL_POSTDIV_LEN) - 1) << PDS_CLKPLL_POSTDIV_POS))
+#define PDS_CLKPLL_REFDIV_RATIO        PDS_CLKPLL_REFDIV_RATIO
+#define PDS_CLKPLL_REFDIV_RATIO_POS    (8U)
+#define PDS_CLKPLL_REFDIV_RATIO_LEN    (4U)
+#define PDS_CLKPLL_REFDIV_RATIO_MSK    (((1U << PDS_CLKPLL_REFDIV_RATIO_LEN) - 1) << PDS_CLKPLL_REFDIV_RATIO_POS)
+#define PDS_CLKPLL_REFDIV_RATIO_UMSK   (~(((1U << PDS_CLKPLL_REFDIV_RATIO_LEN) - 1) << PDS_CLKPLL_REFDIV_RATIO_POS))
+#define PDS_CLKPLL_XTAL_RC32M_SEL      PDS_CLKPLL_XTAL_RC32M_SEL
+#define PDS_CLKPLL_XTAL_RC32M_SEL_POS  (12U)
+#define PDS_CLKPLL_XTAL_RC32M_SEL_LEN  (1U)
+#define PDS_CLKPLL_XTAL_RC32M_SEL_MSK  (((1U << PDS_CLKPLL_XTAL_RC32M_SEL_LEN) - 1) << PDS_CLKPLL_XTAL_RC32M_SEL_POS)
+#define PDS_CLKPLL_XTAL_RC32M_SEL_UMSK (~(((1U << PDS_CLKPLL_XTAL_RC32M_SEL_LEN) - 1) << PDS_CLKPLL_XTAL_RC32M_SEL_POS))
+#define PDS_CLKPLL_REFCLK_SEL          PDS_CLKPLL_REFCLK_SEL
+#define PDS_CLKPLL_REFCLK_SEL_POS      (16U)
+#define PDS_CLKPLL_REFCLK_SEL_LEN      (1U)
+#define PDS_CLKPLL_REFCLK_SEL_MSK      (((1U << PDS_CLKPLL_REFCLK_SEL_LEN) - 1) << PDS_CLKPLL_REFCLK_SEL_POS)
+#define PDS_CLKPLL_REFCLK_SEL_UMSK     (~(((1U << PDS_CLKPLL_REFCLK_SEL_LEN) - 1) << PDS_CLKPLL_REFCLK_SEL_POS))
+#define PDS_CLKPLL_VG11_SEL            PDS_CLKPLL_VG11_SEL
+#define PDS_CLKPLL_VG11_SEL_POS        (20U)
+#define PDS_CLKPLL_VG11_SEL_LEN        (2U)
+#define PDS_CLKPLL_VG11_SEL_MSK        (((1U << PDS_CLKPLL_VG11_SEL_LEN) - 1) << PDS_CLKPLL_VG11_SEL_POS)
+#define PDS_CLKPLL_VG11_SEL_UMSK       (~(((1U << PDS_CLKPLL_VG11_SEL_LEN) - 1) << PDS_CLKPLL_VG11_SEL_POS))
+#define PDS_CLKPLL_RESV                PDS_CLKPLL_RESV
+#define PDS_CLKPLL_RESV_POS            (24U)
+#define PDS_CLKPLL_RESV_LEN            (2U)
+#define PDS_CLKPLL_RESV_MSK            (((1U << PDS_CLKPLL_RESV_LEN) - 1) << PDS_CLKPLL_RESV_POS)
+#define PDS_CLKPLL_RESV_UMSK           (~(((1U << PDS_CLKPLL_RESV_LEN) - 1) << PDS_CLKPLL_RESV_POS))
+
+/* 0x408 : clkpll_cp */
+#define PDS_CLKPLL_CP_OFFSET          (0x408)
+#define PDS_CLKPLL_SEL_CP_BIAS        PDS_CLKPLL_SEL_CP_BIAS
+#define PDS_CLKPLL_SEL_CP_BIAS_POS    (0U)
+#define PDS_CLKPLL_SEL_CP_BIAS_LEN    (1U)
+#define PDS_CLKPLL_SEL_CP_BIAS_MSK    (((1U << PDS_CLKPLL_SEL_CP_BIAS_LEN) - 1) << PDS_CLKPLL_SEL_CP_BIAS_POS)
+#define PDS_CLKPLL_SEL_CP_BIAS_UMSK   (~(((1U << PDS_CLKPLL_SEL_CP_BIAS_LEN) - 1) << PDS_CLKPLL_SEL_CP_BIAS_POS))
+#define PDS_CLKPLL_ICP_5U             PDS_CLKPLL_ICP_5U
+#define PDS_CLKPLL_ICP_5U_POS         (4U)
+#define PDS_CLKPLL_ICP_5U_LEN         (2U)
+#define PDS_CLKPLL_ICP_5U_MSK         (((1U << PDS_CLKPLL_ICP_5U_LEN) - 1) << PDS_CLKPLL_ICP_5U_POS)
+#define PDS_CLKPLL_ICP_5U_UMSK        (~(((1U << PDS_CLKPLL_ICP_5U_LEN) - 1) << PDS_CLKPLL_ICP_5U_POS))
+#define PDS_CLKPLL_ICP_1U             PDS_CLKPLL_ICP_1U
+#define PDS_CLKPLL_ICP_1U_POS         (6U)
+#define PDS_CLKPLL_ICP_1U_LEN         (2U)
+#define PDS_CLKPLL_ICP_1U_MSK         (((1U << PDS_CLKPLL_ICP_1U_LEN) - 1) << PDS_CLKPLL_ICP_1U_POS)
+#define PDS_CLKPLL_ICP_1U_UMSK        (~(((1U << PDS_CLKPLL_ICP_1U_LEN) - 1) << PDS_CLKPLL_ICP_1U_POS))
+#define PDS_CLKPLL_INT_FRAC_SW        PDS_CLKPLL_INT_FRAC_SW
+#define PDS_CLKPLL_INT_FRAC_SW_POS    (8U)
+#define PDS_CLKPLL_INT_FRAC_SW_LEN    (1U)
+#define PDS_CLKPLL_INT_FRAC_SW_MSK    (((1U << PDS_CLKPLL_INT_FRAC_SW_LEN) - 1) << PDS_CLKPLL_INT_FRAC_SW_POS)
+#define PDS_CLKPLL_INT_FRAC_SW_UMSK   (~(((1U << PDS_CLKPLL_INT_FRAC_SW_LEN) - 1) << PDS_CLKPLL_INT_FRAC_SW_POS))
+#define PDS_CLKPLL_CP_STARTUP_EN      PDS_CLKPLL_CP_STARTUP_EN
+#define PDS_CLKPLL_CP_STARTUP_EN_POS  (9U)
+#define PDS_CLKPLL_CP_STARTUP_EN_LEN  (1U)
+#define PDS_CLKPLL_CP_STARTUP_EN_MSK  (((1U << PDS_CLKPLL_CP_STARTUP_EN_LEN) - 1) << PDS_CLKPLL_CP_STARTUP_EN_POS)
+#define PDS_CLKPLL_CP_STARTUP_EN_UMSK (~(((1U << PDS_CLKPLL_CP_STARTUP_EN_LEN) - 1) << PDS_CLKPLL_CP_STARTUP_EN_POS))
+#define PDS_CLKPLL_CP_OPAMP_EN        PDS_CLKPLL_CP_OPAMP_EN
+#define PDS_CLKPLL_CP_OPAMP_EN_POS    (10U)
+#define PDS_CLKPLL_CP_OPAMP_EN_LEN    (1U)
+#define PDS_CLKPLL_CP_OPAMP_EN_MSK    (((1U << PDS_CLKPLL_CP_OPAMP_EN_LEN) - 1) << PDS_CLKPLL_CP_OPAMP_EN_POS)
+#define PDS_CLKPLL_CP_OPAMP_EN_UMSK   (~(((1U << PDS_CLKPLL_CP_OPAMP_EN_LEN) - 1) << PDS_CLKPLL_CP_OPAMP_EN_POS))
+
+/* 0x40C : clkpll_rz */
+#define PDS_CLKPLL_RZ_OFFSET     (0x40C)
+#define PDS_CLKPLL_C4_EN         PDS_CLKPLL_C4_EN
+#define PDS_CLKPLL_C4_EN_POS     (0U)
+#define PDS_CLKPLL_C4_EN_LEN     (1U)
+#define PDS_CLKPLL_C4_EN_MSK     (((1U << PDS_CLKPLL_C4_EN_LEN) - 1) << PDS_CLKPLL_C4_EN_POS)
+#define PDS_CLKPLL_C4_EN_UMSK    (~(((1U << PDS_CLKPLL_C4_EN_LEN) - 1) << PDS_CLKPLL_C4_EN_POS))
+#define PDS_CLKPLL_R4            PDS_CLKPLL_R4
+#define PDS_CLKPLL_R4_POS        (4U)
+#define PDS_CLKPLL_R4_LEN        (2U)
+#define PDS_CLKPLL_R4_MSK        (((1U << PDS_CLKPLL_R4_LEN) - 1) << PDS_CLKPLL_R4_POS)
+#define PDS_CLKPLL_R4_UMSK       (~(((1U << PDS_CLKPLL_R4_LEN) - 1) << PDS_CLKPLL_R4_POS))
+#define PDS_CLKPLL_R4_SHORT      PDS_CLKPLL_R4_SHORT
+#define PDS_CLKPLL_R4_SHORT_POS  (8U)
+#define PDS_CLKPLL_R4_SHORT_LEN  (1U)
+#define PDS_CLKPLL_R4_SHORT_MSK  (((1U << PDS_CLKPLL_R4_SHORT_LEN) - 1) << PDS_CLKPLL_R4_SHORT_POS)
+#define PDS_CLKPLL_R4_SHORT_UMSK (~(((1U << PDS_CLKPLL_R4_SHORT_LEN) - 1) << PDS_CLKPLL_R4_SHORT_POS))
+#define PDS_CLKPLL_C3            PDS_CLKPLL_C3
+#define PDS_CLKPLL_C3_POS        (12U)
+#define PDS_CLKPLL_C3_LEN        (2U)
+#define PDS_CLKPLL_C3_MSK        (((1U << PDS_CLKPLL_C3_LEN) - 1) << PDS_CLKPLL_C3_POS)
+#define PDS_CLKPLL_C3_UMSK       (~(((1U << PDS_CLKPLL_C3_LEN) - 1) << PDS_CLKPLL_C3_POS))
+#define PDS_CLKPLL_CZ            PDS_CLKPLL_CZ
+#define PDS_CLKPLL_CZ_POS        (14U)
+#define PDS_CLKPLL_CZ_LEN        (2U)
+#define PDS_CLKPLL_CZ_MSK        (((1U << PDS_CLKPLL_CZ_LEN) - 1) << PDS_CLKPLL_CZ_POS)
+#define PDS_CLKPLL_CZ_UMSK       (~(((1U << PDS_CLKPLL_CZ_LEN) - 1) << PDS_CLKPLL_CZ_POS))
+#define PDS_CLKPLL_RZ            PDS_CLKPLL_RZ
+#define PDS_CLKPLL_RZ_POS        (16U)
+#define PDS_CLKPLL_RZ_LEN        (3U)
+#define PDS_CLKPLL_RZ_MSK        (((1U << PDS_CLKPLL_RZ_LEN) - 1) << PDS_CLKPLL_RZ_POS)
+#define PDS_CLKPLL_RZ_UMSK       (~(((1U << PDS_CLKPLL_RZ_LEN) - 1) << PDS_CLKPLL_RZ_POS))
+
+/* 0x410 : clkpll_fbdv */
+#define PDS_CLKPLL_FBDV_OFFSET         (0x410)
+#define PDS_CLKPLL_SEL_SAMPLE_CLK      PDS_CLKPLL_SEL_SAMPLE_CLK
+#define PDS_CLKPLL_SEL_SAMPLE_CLK_POS  (0U)
+#define PDS_CLKPLL_SEL_SAMPLE_CLK_LEN  (2U)
+#define PDS_CLKPLL_SEL_SAMPLE_CLK_MSK  (((1U << PDS_CLKPLL_SEL_SAMPLE_CLK_LEN) - 1) << PDS_CLKPLL_SEL_SAMPLE_CLK_POS)
+#define PDS_CLKPLL_SEL_SAMPLE_CLK_UMSK (~(((1U << PDS_CLKPLL_SEL_SAMPLE_CLK_LEN) - 1) << PDS_CLKPLL_SEL_SAMPLE_CLK_POS))
+#define PDS_CLKPLL_SEL_FB_CLK          PDS_CLKPLL_SEL_FB_CLK
+#define PDS_CLKPLL_SEL_FB_CLK_POS      (2U)
+#define PDS_CLKPLL_SEL_FB_CLK_LEN      (2U)
+#define PDS_CLKPLL_SEL_FB_CLK_MSK      (((1U << PDS_CLKPLL_SEL_FB_CLK_LEN) - 1) << PDS_CLKPLL_SEL_FB_CLK_POS)
+#define PDS_CLKPLL_SEL_FB_CLK_UMSK     (~(((1U << PDS_CLKPLL_SEL_FB_CLK_LEN) - 1) << PDS_CLKPLL_SEL_FB_CLK_POS))
+
+/* 0x414 : clkpll_vco */
+#define PDS_CLKPLL_VCO_OFFSET     (0x414)
+#define PDS_CLKPLL_VCO_SPEED      PDS_CLKPLL_VCO_SPEED
+#define PDS_CLKPLL_VCO_SPEED_POS  (0U)
+#define PDS_CLKPLL_VCO_SPEED_LEN  (3U)
+#define PDS_CLKPLL_VCO_SPEED_MSK  (((1U << PDS_CLKPLL_VCO_SPEED_LEN) - 1) << PDS_CLKPLL_VCO_SPEED_POS)
+#define PDS_CLKPLL_VCO_SPEED_UMSK (~(((1U << PDS_CLKPLL_VCO_SPEED_LEN) - 1) << PDS_CLKPLL_VCO_SPEED_POS))
+#define PDS_CLKPLL_SHRTR          PDS_CLKPLL_SHRTR
+#define PDS_CLKPLL_SHRTR_POS      (3U)
+#define PDS_CLKPLL_SHRTR_LEN      (1U)
+#define PDS_CLKPLL_SHRTR_MSK      (((1U << PDS_CLKPLL_SHRTR_LEN) - 1) << PDS_CLKPLL_SHRTR_POS)
+#define PDS_CLKPLL_SHRTR_UMSK     (~(((1U << PDS_CLKPLL_SHRTR_LEN) - 1) << PDS_CLKPLL_SHRTR_POS))
+
+/* 0x418 : clkpll_sdm */
+#define PDS_CLKPLL_SDM_OFFSET      (0x418)
+#define PDS_CLKPLL_SDMIN           PDS_CLKPLL_SDMIN
+#define PDS_CLKPLL_SDMIN_POS       (0U)
+#define PDS_CLKPLL_SDMIN_LEN       (24U)
+#define PDS_CLKPLL_SDMIN_MSK       (((1U << PDS_CLKPLL_SDMIN_LEN) - 1) << PDS_CLKPLL_SDMIN_POS)
+#define PDS_CLKPLL_SDMIN_UMSK      (~(((1U << PDS_CLKPLL_SDMIN_LEN) - 1) << PDS_CLKPLL_SDMIN_POS))
+#define PDS_CLKPLL_DITHER_SEL      PDS_CLKPLL_DITHER_SEL
+#define PDS_CLKPLL_DITHER_SEL_POS  (24U)
+#define PDS_CLKPLL_DITHER_SEL_LEN  (2U)
+#define PDS_CLKPLL_DITHER_SEL_MSK  (((1U << PDS_CLKPLL_DITHER_SEL_LEN) - 1) << PDS_CLKPLL_DITHER_SEL_POS)
+#define PDS_CLKPLL_DITHER_SEL_UMSK (~(((1U << PDS_CLKPLL_DITHER_SEL_LEN) - 1) << PDS_CLKPLL_DITHER_SEL_POS))
+#define PDS_CLKPLL_SDM_FLAG        PDS_CLKPLL_SDM_FLAG
+#define PDS_CLKPLL_SDM_FLAG_POS    (28U)
+#define PDS_CLKPLL_SDM_FLAG_LEN    (1U)
+#define PDS_CLKPLL_SDM_FLAG_MSK    (((1U << PDS_CLKPLL_SDM_FLAG_LEN) - 1) << PDS_CLKPLL_SDM_FLAG_POS)
+#define PDS_CLKPLL_SDM_FLAG_UMSK   (~(((1U << PDS_CLKPLL_SDM_FLAG_LEN) - 1) << PDS_CLKPLL_SDM_FLAG_POS))
+#define PDS_CLKPLL_SDM_BYPASS      PDS_CLKPLL_SDM_BYPASS
+#define PDS_CLKPLL_SDM_BYPASS_POS  (29U)
+#define PDS_CLKPLL_SDM_BYPASS_LEN  (1U)
+#define PDS_CLKPLL_SDM_BYPASS_MSK  (((1U << PDS_CLKPLL_SDM_BYPASS_LEN) - 1) << PDS_CLKPLL_SDM_BYPASS_POS)
+#define PDS_CLKPLL_SDM_BYPASS_UMSK (~(((1U << PDS_CLKPLL_SDM_BYPASS_LEN) - 1) << PDS_CLKPLL_SDM_BYPASS_POS))
+
+/* 0x41C : clkpll_output_en */
+#define PDS_CLKPLL_OUTPUT_EN_OFFSET  (0x41C)
+#define PDS_CLKPLL_EN_480M           PDS_CLKPLL_EN_480M
+#define PDS_CLKPLL_EN_480M_POS       (0U)
+#define PDS_CLKPLL_EN_480M_LEN       (1U)
+#define PDS_CLKPLL_EN_480M_MSK       (((1U << PDS_CLKPLL_EN_480M_LEN) - 1) << PDS_CLKPLL_EN_480M_POS)
+#define PDS_CLKPLL_EN_480M_UMSK      (~(((1U << PDS_CLKPLL_EN_480M_LEN) - 1) << PDS_CLKPLL_EN_480M_POS))
+#define PDS_CLKPLL_EN_240M           PDS_CLKPLL_EN_240M
+#define PDS_CLKPLL_EN_240M_POS       (1U)
+#define PDS_CLKPLL_EN_240M_LEN       (1U)
+#define PDS_CLKPLL_EN_240M_MSK       (((1U << PDS_CLKPLL_EN_240M_LEN) - 1) << PDS_CLKPLL_EN_240M_POS)
+#define PDS_CLKPLL_EN_240M_UMSK      (~(((1U << PDS_CLKPLL_EN_240M_LEN) - 1) << PDS_CLKPLL_EN_240M_POS))
+#define PDS_CLKPLL_EN_192M           PDS_CLKPLL_EN_192M
+#define PDS_CLKPLL_EN_192M_POS       (2U)
+#define PDS_CLKPLL_EN_192M_LEN       (1U)
+#define PDS_CLKPLL_EN_192M_MSK       (((1U << PDS_CLKPLL_EN_192M_LEN) - 1) << PDS_CLKPLL_EN_192M_POS)
+#define PDS_CLKPLL_EN_192M_UMSK      (~(((1U << PDS_CLKPLL_EN_192M_LEN) - 1) << PDS_CLKPLL_EN_192M_POS))
+#define PDS_CLKPLL_EN_160M           PDS_CLKPLL_EN_160M
+#define PDS_CLKPLL_EN_160M_POS       (3U)
+#define PDS_CLKPLL_EN_160M_LEN       (1U)
+#define PDS_CLKPLL_EN_160M_MSK       (((1U << PDS_CLKPLL_EN_160M_LEN) - 1) << PDS_CLKPLL_EN_160M_POS)
+#define PDS_CLKPLL_EN_160M_UMSK      (~(((1U << PDS_CLKPLL_EN_160M_LEN) - 1) << PDS_CLKPLL_EN_160M_POS))
+#define PDS_CLKPLL_EN_120M           PDS_CLKPLL_EN_120M
+#define PDS_CLKPLL_EN_120M_POS       (4U)
+#define PDS_CLKPLL_EN_120M_LEN       (1U)
+#define PDS_CLKPLL_EN_120M_MSK       (((1U << PDS_CLKPLL_EN_120M_LEN) - 1) << PDS_CLKPLL_EN_120M_POS)
+#define PDS_CLKPLL_EN_120M_UMSK      (~(((1U << PDS_CLKPLL_EN_120M_LEN) - 1) << PDS_CLKPLL_EN_120M_POS))
+#define PDS_CLKPLL_EN_96M            PDS_CLKPLL_EN_96M
+#define PDS_CLKPLL_EN_96M_POS        (5U)
+#define PDS_CLKPLL_EN_96M_LEN        (1U)
+#define PDS_CLKPLL_EN_96M_MSK        (((1U << PDS_CLKPLL_EN_96M_LEN) - 1) << PDS_CLKPLL_EN_96M_POS)
+#define PDS_CLKPLL_EN_96M_UMSK       (~(((1U << PDS_CLKPLL_EN_96M_LEN) - 1) << PDS_CLKPLL_EN_96M_POS))
+#define PDS_CLKPLL_EN_80M            PDS_CLKPLL_EN_80M
+#define PDS_CLKPLL_EN_80M_POS        (6U)
+#define PDS_CLKPLL_EN_80M_LEN        (1U)
+#define PDS_CLKPLL_EN_80M_MSK        (((1U << PDS_CLKPLL_EN_80M_LEN) - 1) << PDS_CLKPLL_EN_80M_POS)
+#define PDS_CLKPLL_EN_80M_UMSK       (~(((1U << PDS_CLKPLL_EN_80M_LEN) - 1) << PDS_CLKPLL_EN_80M_POS))
+#define PDS_CLKPLL_EN_48M            PDS_CLKPLL_EN_48M
+#define PDS_CLKPLL_EN_48M_POS        (7U)
+#define PDS_CLKPLL_EN_48M_LEN        (1U)
+#define PDS_CLKPLL_EN_48M_MSK        (((1U << PDS_CLKPLL_EN_48M_LEN) - 1) << PDS_CLKPLL_EN_48M_POS)
+#define PDS_CLKPLL_EN_48M_UMSK       (~(((1U << PDS_CLKPLL_EN_48M_LEN) - 1) << PDS_CLKPLL_EN_48M_POS))
+#define PDS_CLKPLL_EN_32M            PDS_CLKPLL_EN_32M
+#define PDS_CLKPLL_EN_32M_POS        (8U)
+#define PDS_CLKPLL_EN_32M_LEN        (1U)
+#define PDS_CLKPLL_EN_32M_MSK        (((1U << PDS_CLKPLL_EN_32M_LEN) - 1) << PDS_CLKPLL_EN_32M_POS)
+#define PDS_CLKPLL_EN_32M_UMSK       (~(((1U << PDS_CLKPLL_EN_32M_LEN) - 1) << PDS_CLKPLL_EN_32M_POS))
+#define PDS_CLKPLL_EN_DIV2_480M      PDS_CLKPLL_EN_DIV2_480M
+#define PDS_CLKPLL_EN_DIV2_480M_POS  (9U)
+#define PDS_CLKPLL_EN_DIV2_480M_LEN  (1U)
+#define PDS_CLKPLL_EN_DIV2_480M_MSK  (((1U << PDS_CLKPLL_EN_DIV2_480M_LEN) - 1) << PDS_CLKPLL_EN_DIV2_480M_POS)
+#define PDS_CLKPLL_EN_DIV2_480M_UMSK (~(((1U << PDS_CLKPLL_EN_DIV2_480M_LEN) - 1) << PDS_CLKPLL_EN_DIV2_480M_POS))
+
+/* 0x420 : clkpll_test_enable */
+#define PDS_CLKPLL_TEST_ENABLE_OFFSET    (0x420)
+#define PDS_DTEN_CLKPLL_POSTDIV_CLK      PDS_DTEN_CLKPLL_POSTDIV_CLK
+#define PDS_DTEN_CLKPLL_POSTDIV_CLK_POS  (0U)
+#define PDS_DTEN_CLKPLL_POSTDIV_CLK_LEN  (1U)
+#define PDS_DTEN_CLKPLL_POSTDIV_CLK_MSK  (((1U << PDS_DTEN_CLKPLL_POSTDIV_CLK_LEN) - 1) << PDS_DTEN_CLKPLL_POSTDIV_CLK_POS)
+#define PDS_DTEN_CLKPLL_POSTDIV_CLK_UMSK (~(((1U << PDS_DTEN_CLKPLL_POSTDIV_CLK_LEN) - 1) << PDS_DTEN_CLKPLL_POSTDIV_CLK_POS))
+#define PDS_DTEN_CLK96M                  PDS_DTEN_CLK96M
+#define PDS_DTEN_CLK96M_POS              (1U)
+#define PDS_DTEN_CLK96M_LEN              (1U)
+#define PDS_DTEN_CLK96M_MSK              (((1U << PDS_DTEN_CLK96M_LEN) - 1) << PDS_DTEN_CLK96M_POS)
+#define PDS_DTEN_CLK96M_UMSK             (~(((1U << PDS_DTEN_CLK96M_LEN) - 1) << PDS_DTEN_CLK96M_POS))
+#define PDS_DTEN_CLK32M                  PDS_DTEN_CLK32M
+#define PDS_DTEN_CLK32M_POS              (2U)
+#define PDS_DTEN_CLK32M_LEN              (1U)
+#define PDS_DTEN_CLK32M_MSK              (((1U << PDS_DTEN_CLK32M_LEN) - 1) << PDS_DTEN_CLK32M_POS)
+#define PDS_DTEN_CLK32M_UMSK             (~(((1U << PDS_DTEN_CLK32M_LEN) - 1) << PDS_DTEN_CLK32M_POS))
+#define PDS_DTEN_CLKPLL_FSDM             PDS_DTEN_CLKPLL_FSDM
+#define PDS_DTEN_CLKPLL_FSDM_POS         (3U)
+#define PDS_DTEN_CLKPLL_FSDM_LEN         (1U)
+#define PDS_DTEN_CLKPLL_FSDM_MSK         (((1U << PDS_DTEN_CLKPLL_FSDM_LEN) - 1) << PDS_DTEN_CLKPLL_FSDM_POS)
+#define PDS_DTEN_CLKPLL_FSDM_UMSK        (~(((1U << PDS_DTEN_CLKPLL_FSDM_LEN) - 1) << PDS_DTEN_CLKPLL_FSDM_POS))
+#define PDS_DTEN_CLKPLL_FREF             PDS_DTEN_CLKPLL_FREF
+#define PDS_DTEN_CLKPLL_FREF_POS         (4U)
+#define PDS_DTEN_CLKPLL_FREF_LEN         (1U)
+#define PDS_DTEN_CLKPLL_FREF_MSK         (((1U << PDS_DTEN_CLKPLL_FREF_LEN) - 1) << PDS_DTEN_CLKPLL_FREF_POS)
+#define PDS_DTEN_CLKPLL_FREF_UMSK        (~(((1U << PDS_DTEN_CLKPLL_FREF_LEN) - 1) << PDS_DTEN_CLKPLL_FREF_POS))
+#define PDS_DTEN_CLKPLL_FIN              PDS_DTEN_CLKPLL_FIN
+#define PDS_DTEN_CLKPLL_FIN_POS          (5U)
+#define PDS_DTEN_CLKPLL_FIN_LEN          (1U)
+#define PDS_DTEN_CLKPLL_FIN_MSK          (((1U << PDS_DTEN_CLKPLL_FIN_LEN) - 1) << PDS_DTEN_CLKPLL_FIN_POS)
+#define PDS_DTEN_CLKPLL_FIN_UMSK         (~(((1U << PDS_DTEN_CLKPLL_FIN_LEN) - 1) << PDS_DTEN_CLKPLL_FIN_POS))
+#define PDS_TEN_CLKPLL_SFREG             PDS_TEN_CLKPLL_SFREG
+#define PDS_TEN_CLKPLL_SFREG_POS         (6U)
+#define PDS_TEN_CLKPLL_SFREG_LEN         (1U)
+#define PDS_TEN_CLKPLL_SFREG_MSK         (((1U << PDS_TEN_CLKPLL_SFREG_LEN) - 1) << PDS_TEN_CLKPLL_SFREG_POS)
+#define PDS_TEN_CLKPLL_SFREG_UMSK        (~(((1U << PDS_TEN_CLKPLL_SFREG_LEN) - 1) << PDS_TEN_CLKPLL_SFREG_POS))
+#define PDS_TEN_CLKPLL                   PDS_TEN_CLKPLL
+#define PDS_TEN_CLKPLL_POS               (7U)
+#define PDS_TEN_CLKPLL_LEN               (1U)
+#define PDS_TEN_CLKPLL_MSK               (((1U << PDS_TEN_CLKPLL_LEN) - 1) << PDS_TEN_CLKPLL_POS)
+#define PDS_TEN_CLKPLL_UMSK              (~(((1U << PDS_TEN_CLKPLL_LEN) - 1) << PDS_TEN_CLKPLL_POS))
+#define PDS_CLKPLL_DC_TP_OUT_EN          PDS_CLKPLL_DC_TP_OUT_EN
+#define PDS_CLKPLL_DC_TP_OUT_EN_POS      (8U)
+#define PDS_CLKPLL_DC_TP_OUT_EN_LEN      (1U)
+#define PDS_CLKPLL_DC_TP_OUT_EN_MSK      (((1U << PDS_CLKPLL_DC_TP_OUT_EN_LEN) - 1) << PDS_CLKPLL_DC_TP_OUT_EN_POS)
+#define PDS_CLKPLL_DC_TP_OUT_EN_UMSK     (~(((1U << PDS_CLKPLL_DC_TP_OUT_EN_LEN) - 1) << PDS_CLKPLL_DC_TP_OUT_EN_POS))
+
+struct pds_reg {
+    /* 0x0 : PDS_CTL */
+    union {
+        struct
+        {
+            uint32_t pds_start_ps              : 1; /* [    0],        w1p,        0x0 */
+            uint32_t cr_sleep_forever          : 1; /* [    1],        r/w,        0x0 */
+            uint32_t cr_xtal_force_off         : 1; /* [    2],        r/w,        0x0 */
+            uint32_t cr_wifi_pds_save_state    : 1; /* [    3],        r/w,        0x0 */
+            uint32_t cr_pds_pd_dcdc18          : 1; /* [    4],        r/w,        0x0 */
+            uint32_t cr_pds_pd_bg_sys          : 1; /* [    5],        r/w,        0x0 */
+            uint32_t cr_pds_ctrl_gpio_ie_pu_pd : 1; /* [    6],        r/w,        0x0 */
+            uint32_t cr_pds_ctrl_pu_flash      : 1; /* [    7],        r/w,        0x0 */
+            uint32_t cr_pds_gate_clk           : 1; /* [    8],        r/w,        0x1 */
+            uint32_t cr_pds_mem_stby           : 1; /* [    9],        r/w,        0x1 */
+            uint32_t cr_sw_pu_flash            : 1; /* [   10],        r/w,        0x1 */
+            uint32_t cr_pds_iso_en             : 1; /* [   11],        r/w,        0x1 */
+            uint32_t cr_pds_wait_xtal_rdy      : 1; /* [   12],        r/w,        0x0 */
+            uint32_t cr_pds_pwr_off            : 1; /* [   13],        r/w,        0x1 */
+            uint32_t cr_pds_pd_xtal            : 1; /* [   14],        r/w,        0x1 */
+            uint32_t cr_pds_soc_enb_force_on   : 1; /* [   15],        r/w,        0x0 */
+            uint32_t cr_pds_rst_soc_en         : 1; /* [   16],        r/w,        0x0 */
+            uint32_t cr_pds_rc32m_off_dis      : 1; /* [   17],        r/w,        0x0 */
+            uint32_t cr_pds_ldo_vsel_en        : 1; /* [   18],        r/w,        0x0 */
+            uint32_t cr_pds_ram_lp_with_clk_en : 1; /* [   19],        r/w,        0x0 */
+            uint32_t reserved_20               : 1; /* [   20],       rsvd,        0x0 */
+            uint32_t cr_np_wfi_mask            : 1; /* [   21],        r/w,        0x0 */
+            uint32_t cr_pds_pd_ldo11           : 1; /* [   22],        r/w,        0x0 */
+            uint32_t cr_pds_force_ram_clk_en   : 1; /* [   23],        r/w,        0x0 */
+            uint32_t cr_pds_ldo_vol            : 4; /* [27:24],        r/w,        0xa */
+            uint32_t cr_pds_ctrl_rf            : 2; /* [29:28],        r/w,        0x1 */
+            uint32_t cr_pds_ctrl_pll           : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } PDS_CTL;
+
+    /* 0x4 : PDS_TIME1 */
+    union {
+        struct
+        {
+            uint32_t cr_sleep_duration : 32; /* [31: 0],        r/w,      0xca8 */
+        } BF;
+        uint32_t WORD;
+    } PDS_TIME1;
+
+    /* 0x8  reserved */
+    uint8_t RESERVED0x8[4];
+
+    /* 0xC : PDS_INT */
+    union {
+        struct
+        {
+            uint32_t ro_pds_wake_int          : 1; /* [    0],          r,        0x0 */
+            uint32_t reserved_1               : 1; /* [    1],       rsvd,        0x0 */
+            uint32_t ro_pds_rf_done_int       : 1; /* [    2],          r,        0x0 */
+            uint32_t ro_pds_pll_done_int      : 1; /* [    3],          r,        0x0 */
+            uint32_t pds_reset_event          : 3; /* [ 6: 4],          r,        0x0 */
+            uint32_t pds_clr_reset_event      : 1; /* [    7],          w,        0x0 */
+            uint32_t cr_pds_wake_int_mask     : 1; /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9               : 1; /* [    9],       rsvd,        0x0 */
+            uint32_t cr_pds_rf_done_int_mask  : 1; /* [   10],        r/w,        0x0 */
+            uint32_t cr_pds_pll_done_int_mask : 1; /* [   11],        r/w,        0x0 */
+            uint32_t reserved_12_14           : 3; /* [14:12],       rsvd,        0x0 */
+            uint32_t cr_pds_int_clr           : 1; /* [   15],        r/w,        0x0 */
+            uint32_t cr_pds_wakeup_src_en     : 8; /* [23:16],        r/w,       0xff */
+            uint32_t ro_pds_wakeup_event      : 8; /* [31:24],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } PDS_INT;
+
+    /* 0x10 : PDS_CTL2 */
+    union {
+        struct
+        {
+            uint32_t cr_pds_force_np_pwr_off   : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1                : 1;  /* [    1],       rsvd,        0x0 */
+            uint32_t cr_pds_force_bz_pwr_off   : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t cr_pds_force_usb_pwr_off  : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t cr_pds_force_np_iso_en    : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reserved_5                : 1;  /* [    5],       rsvd,        0x0 */
+            uint32_t cr_pds_force_bz_iso_en    : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t cr_pds_force_usb_iso_en   : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t cr_pds_force_np_pds_rst   : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9                : 1;  /* [    9],       rsvd,        0x0 */
+            uint32_t cr_pds_force_bz_pds_rst   : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t cr_pds_force_usb_pds_rst  : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t cr_pds_force_np_mem_stby  : 1;  /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13               : 1;  /* [   13],       rsvd,        0x0 */
+            uint32_t cr_pds_force_bz_mem_stby  : 1;  /* [   14],        r/w,        0x0 */
+            uint32_t cr_pds_force_usb_mem_stby : 1;  /* [   15],        r/w,        0x0 */
+            uint32_t cr_pds_force_np_gate_clk  : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17               : 1;  /* [   17],       rsvd,        0x0 */
+            uint32_t cr_pds_force_bz_gate_clk  : 1;  /* [   18],        r/w,        0x0 */
+            uint32_t cr_pds_force_usb_gate_clk : 1;  /* [   19],        r/w,        0x0 */
+            uint32_t reserved_20_31            : 12; /* [31:20],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } PDS_CTL2;
+
+    /* 0x14 : PDS_CTL3 */
+    union {
+        struct
+        {
+            uint32_t reserved_0                 : 1; /* [    0],       rsvd,        0x0 */
+            uint32_t cr_pds_force_misc_pwr_off  : 1; /* [    1],        r/w,        0x0 */
+            uint32_t cr_pds_force_ble_pwr_off   : 1; /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3_4               : 2; /* [ 4: 3],       rsvd,        0x0 */
+            uint32_t cr_pds_force_ble_iso_en    : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6                 : 1; /* [    6],       rsvd,        0x0 */
+            uint32_t cr_pds_force_misc_pds_rst  : 1; /* [    7],        r/w,        0x0 */
+            uint32_t cr_pds_force_ble_pds_rst   : 1; /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9                 : 1; /* [    9],       rsvd,        0x0 */
+            uint32_t cr_pds_force_misc_mem_stby : 1; /* [   10],        r/w,        0x0 */
+            uint32_t cr_pds_force_ble_mem_stby  : 1; /* [   11],        r/w,        0x0 */
+            uint32_t reserved_12                : 1; /* [   12],       rsvd,        0x0 */
+            uint32_t cr_pds_force_misc_gate_clk : 1; /* [   13],        r/w,        0x0 */
+            uint32_t cr_pds_force_ble_gate_clk  : 1; /* [   14],        r/w,        0x0 */
+            uint32_t reserved_15_23             : 9; /* [23:15],       rsvd,        0x0 */
+            uint32_t cr_pds_np_iso_en           : 1; /* [   24],        r/w,        0x1 */
+            uint32_t reserved_25_26             : 2; /* [26:25],       rsvd,        0x0 */
+            uint32_t cr_pds_bz_iso_en           : 1; /* [   27],        r/w,        0x1 */
+            uint32_t cr_pds_ble_iso_en          : 1; /* [   28],        r/w,        0x1 */
+            uint32_t cr_pds_usb_iso_en          : 1; /* [   29],        r/w,        0x1 */
+            uint32_t cr_pds_misc_iso_en         : 1; /* [   30],        r/w,        0x1 */
+            uint32_t reserved_31                : 1; /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } PDS_CTL3;
+
+    /* 0x18 : PDS_CTL4 */
+    union {
+        struct
+        {
+            uint32_t cr_pds_np_pwr_off       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t cr_pds_np_reset         : 1; /* [    1],        r/w,        0x1 */
+            uint32_t cr_pds_np_mem_stby      : 1; /* [    2],        r/w,        0x1 */
+            uint32_t cr_pds_np_gate_clk      : 1; /* [    3],        r/w,        0x1 */
+            uint32_t reserved_4_11           : 8; /* [11: 4],       rsvd,        0x0 */
+            uint32_t cr_pds_bz_pwr_off       : 1; /* [   12],        r/w,        0x1 */
+            uint32_t cr_pds_bz_reset         : 1; /* [   13],        r/w,        0x1 */
+            uint32_t cr_pds_bz_mem_stby      : 1; /* [   14],        r/w,        0x1 */
+            uint32_t cr_pds_bz_gate_clk      : 1; /* [   15],        r/w,        0x1 */
+            uint32_t cr_pds_ble_pwr_off      : 1; /* [   16],        r/w,        0x1 */
+            uint32_t cr_pds_ble_reset        : 1; /* [   17],        r/w,        0x1 */
+            uint32_t cr_pds_ble_mem_stby     : 1; /* [   18],        r/w,        0x1 */
+            uint32_t cr_pds_ble_gate_clk     : 1; /* [   19],        r/w,        0x1 */
+            uint32_t cr_pds_usb_pwr_off      : 1; /* [   20],        r/w,        0x1 */
+            uint32_t cr_pds_usb_reset        : 1; /* [   21],        r/w,        0x1 */
+            uint32_t cr_pds_usb_mem_stby     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t cr_pds_usb_gate_clk     : 1; /* [   23],        r/w,        0x1 */
+            uint32_t cr_pds_misc_pwr_off     : 1; /* [   24],        r/w,        0x1 */
+            uint32_t cr_pds_misc_reset       : 1; /* [   25],        r/w,        0x1 */
+            uint32_t cr_pds_misc_mem_stby    : 1; /* [   26],        r/w,        0x1 */
+            uint32_t cr_pds_misc_gate_clk    : 1; /* [   27],        r/w,        0x1 */
+            uint32_t reserved_28_29          : 2; /* [29:28],       rsvd,        0x0 */
+            uint32_t cr_pds_misc_ana_pwr_off : 1; /* [   30],        r/w,        0x1 */
+            uint32_t cr_pds_misc_dig_pwr_off : 1; /* [   31],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } PDS_CTL4;
+
+    /* 0x1C : pds_stat */
+    union {
+        struct
+        {
+            uint32_t ro_pds_state     : 4;  /* [ 3: 0],          r,        0x0 */
+            uint32_t reserved_4_7     : 4;  /* [ 7: 4],       rsvd,        0x0 */
+            uint32_t ro_pds_rf_state  : 4;  /* [11: 8],          r,        0x0 */
+            uint32_t reserved_12_15   : 4;  /* [15:12],       rsvd,        0x0 */
+            uint32_t ro_pds_pll_state : 2;  /* [17:16],          r,        0x0 */
+            uint32_t reserved_18_31   : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pds_stat;
+
+    /* 0x20 : pds_ram1 */
+    union {
+        struct
+        {
+            uint32_t cr_pds_ram_ret1n : 4;  /* [ 3: 0],        r/w,        0xf */
+            uint32_t cr_pds_ram_ret2n : 4;  /* [ 7: 4],        r/w,        0x0 */
+            uint32_t cr_pds_ram_pgen  : 4;  /* [11: 8],        r/w,        0x0 */
+            uint32_t reserved_12_31   : 20; /* [31:12],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pds_ram1;
+
+    /* 0x24  reserved */
+    uint8_t RESERVED0x24[12];
+
+    /* 0x30 : pds_gpio_set_pu_pd */
+    union {
+        struct
+        {
+            uint32_t cr_pds_gpio_22_17_pd : 6; /* [ 5: 0],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t cr_pds_gpio_22_17_pu : 6; /* [13: 8],        r/w,        0x0 */
+            uint32_t reserved_14_15       : 2; /* [15:14],       rsvd,        0x0 */
+            uint32_t cr_pds_gpio_28_23_pd : 6; /* [21:16],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t cr_pds_gpio_28_23_pu : 6; /* [29:24],        r/w,        0x0 */
+            uint32_t reserved_30_31       : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pds_gpio_set_pu_pd;
+
+    /* 0x34  reserved */
+    uint8_t RESERVED0x34[12];
+
+    /* 0x40 : pds_gpio_int */
+    union {
+        struct
+        {
+            uint32_t pds_gpio_int_mask   : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t pds_gpio_int_stat   : 1;  /* [    1],          r,        0x0 */
+            uint32_t pds_gpio_int_clr    : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3          : 1;  /* [    3],       rsvd,        0x0 */
+            uint32_t pds_gpio_int_mode   : 3;  /* [ 6: 4],        r/w,        0x0 */
+            uint32_t reserved_7          : 1;  /* [    7],       rsvd,        0x0 */
+            uint32_t pds_gpio_int_select : 3;  /* [10: 8],        r/w,        0x0 */
+            uint32_t reserved_11_31      : 21; /* [31:11],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pds_gpio_int;
+
+    /* 0x44  reserved */
+    uint8_t RESERVED0x44[700];
+
+    /* 0x300 : rc32m_ctrl0 */
+    union {
+        struct
+        {
+            uint32_t rc32m_cal_done        : 1; /* [    0],          r,        0x0 */
+            uint32_t rc32m_rdy             : 1; /* [    1],          r,        0x0 */
+            uint32_t rc32m_cal_inprogress  : 1; /* [    2],          r,        0x0 */
+            uint32_t rc32m_cal_div         : 2; /* [ 4: 3],        r/w,        0x3 */
+            uint32_t rc32m_cal_precharge   : 1; /* [    5],          r,        0x0 */
+            uint32_t rc32m_dig_code_fr_cal : 8; /* [13: 6],          r,        0x0 */
+            uint32_t reserved_14_16        : 3; /* [16:14],       rsvd,        0x0 */
+            uint32_t rc32m_allow_cal       : 1; /* [   17],        r/w,        0x0 */
+            uint32_t rc32m_refclk_half     : 1; /* [   18],        r/w,        0x0 */
+            uint32_t rc32m_ext_code_en     : 1; /* [   19],        r/w,        0x1 */
+            uint32_t rc32m_cal_en          : 1; /* [   20],        r/w,        0x0 */
+            uint32_t rc32m_pd              : 1; /* [   21],        r/w,        0x0 */
+            uint32_t rc32m_code_fr_ext     : 8; /* [29:22],        r/w,       0x60 */
+            uint32_t reserved_30_31        : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } rc32m_ctrl0;
+
+    /* 0x304 : rc32m_ctrl1 */
+    union {
+        struct
+        {
+            uint32_t rc32m_test_en      : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t rc32m_soft_rst     : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t rc32m_clk_soft_rst : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t rc32m_clk_inv      : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t rc32m_clk_force_on : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reserved_5_23      : 19; /* [23: 5],       rsvd,        0x0 */
+            uint32_t rc32m_reserved     : 8;  /* [31:24],        r/w,        0xf */
+        } BF;
+        uint32_t WORD;
+    } rc32m_ctrl1;
+
+    /* 0x308  reserved */
+    uint8_t RESERVED0x308[248];
+
+    /* 0x400 : pu_rst_clkpll */
+    union {
+        struct
+        {
+            uint32_t clkpll_sdm_reset     : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t clkpll_reset_postdiv : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t clkpll_reset_fbdv    : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t clkpll_reset_refdiv  : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t clkpll_pu_postdiv    : 1;  /* [    4],        r/w,        0x1 */
+            uint32_t clkpll_pu_fbdv       : 1;  /* [    5],        r/w,        0x1 */
+            uint32_t clkpll_pu_clamp_op   : 1;  /* [    6],        r/w,        0x1 */
+            uint32_t clkpll_pu_pfd        : 1;  /* [    7],        r/w,        0x1 */
+            uint32_t clkpll_pu_cp         : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t pu_clkpll_sfreg      : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t pu_clkpll            : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t reserved_11_31       : 21; /* [31:11],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pu_rst_clkpll;
+
+    /* 0x404 : clkpll_top_ctrl */
+    union {
+        struct
+        {
+            uint32_t clkpll_postdiv        : 7; /* [ 6: 0],        r/w,       0x14 */
+            uint32_t reserved_7            : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t clkpll_refdiv_ratio   : 4; /* [11: 8],        r/w,        0x4 */
+            uint32_t clkpll_xtal_rc32m_sel : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13_15        : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t clkpll_refclk_sel     : 1; /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17_19        : 3; /* [19:17],       rsvd,        0x0 */
+            uint32_t clkpll_vg11_sel       : 2; /* [21:20],        r/w,        0x1 */
+            uint32_t reserved_22_23        : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t clkpll_resv           : 2; /* [25:24],        r/w,        0x1 */
+            uint32_t reserved_26_31        : 6; /* [31:26],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clkpll_top_ctrl;
+
+    /* 0x408 : clkpll_cp */
+    union {
+        struct
+        {
+            uint32_t clkpll_sel_cp_bias   : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reserved_1_3         : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t clkpll_icp_5u        : 2;  /* [ 5: 4],        r/w,        0x0 */
+            uint32_t clkpll_icp_1u        : 2;  /* [ 7: 6],        r/w,        0x1 */
+            uint32_t clkpll_int_frac_sw   : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t clkpll_cp_startup_en : 1;  /* [    9],        r/w,        0x1 */
+            uint32_t clkpll_cp_opamp_en   : 1;  /* [   10],        r/w,        0x1 */
+            uint32_t reserved_11_31       : 21; /* [31:11],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clkpll_cp;
+
+    /* 0x40C : clkpll_rz */
+    union {
+        struct
+        {
+            uint32_t clkpll_c4_en    : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3    : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t clkpll_r4       : 2;  /* [ 5: 4],        r/w,        0x2 */
+            uint32_t reserved_6_7    : 2;  /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t clkpll_r4_short : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9_11   : 3;  /* [11: 9],       rsvd,        0x0 */
+            uint32_t clkpll_c3       : 2;  /* [13:12],        r/w,        0x2 */
+            uint32_t clkpll_cz       : 2;  /* [15:14],        r/w,        0x2 */
+            uint32_t clkpll_rz       : 3;  /* [18:16],        r/w,        0x5 */
+            uint32_t reserved_19_31  : 13; /* [31:19],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clkpll_rz;
+
+    /* 0x410 : clkpll_fbdv */
+    union {
+        struct
+        {
+            uint32_t clkpll_sel_sample_clk : 2;  /* [ 1: 0],        r/w,        0x1 */
+            uint32_t clkpll_sel_fb_clk     : 2;  /* [ 3: 2],        r/w,        0x1 */
+            uint32_t reserved_4_31         : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clkpll_fbdv;
+
+    /* 0x414 : clkpll_vco */
+    union {
+        struct
+        {
+            uint32_t clkpll_vco_speed : 3;  /* [ 2: 0],        r/w,        0x6 */
+            uint32_t clkpll_shrtr     : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t reserved_4_31    : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clkpll_vco;
+
+    /* 0x418 : clkpll_sdm */
+    union {
+        struct
+        {
+            uint32_t clkpll_sdmin      : 24; /* [23: 0],        r/w,   0x600000 */
+            uint32_t clkpll_dither_sel : 2;  /* [25:24],        r/w,        0x0 */
+            uint32_t reserved_26_27    : 2;  /* [27:26],       rsvd,        0x0 */
+            uint32_t clkpll_sdm_flag   : 1;  /* [   28],        r/w,        0x1 */
+            uint32_t clkpll_sdm_bypass : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t reserved_30_31    : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clkpll_sdm;
+
+    /* 0x41C : clkpll_output_en */
+    union {
+        struct
+        {
+            uint32_t clkpll_en_480m      : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t clkpll_en_240m      : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t clkpll_en_192m      : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t clkpll_en_160m      : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t clkpll_en_120m      : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t clkpll_en_96m       : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t clkpll_en_80m       : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t clkpll_en_48m       : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t clkpll_en_32m       : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t clkpll_en_div2_480m : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t reserved_10_31      : 22; /* [31:10],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clkpll_output_en;
+
+    /* 0x420 : clkpll_test_enable */
+    union {
+        struct
+        {
+            uint32_t dten_clkpll_postdiv_clk : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t dten_clk96M             : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t dten_clk32M             : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t dten_clkpll_fsdm        : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t dten_clkpll_fref        : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t dten_clkpll_fin         : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t ten_clkpll_sfreg        : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t ten_clkpll              : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t clkpll_dc_tp_out_en     : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9_31           : 23; /* [31: 9],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clkpll_test_enable;
+};
+
+typedef volatile struct pds_reg pds_reg_t;
+
+#endif /* __PDS_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/pwm_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/pwm_reg.h
new file mode 100644
index 00000000..2b0d67ce
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/pwm_reg.h
@@ -0,0 +1,993 @@
+/**
+  ******************************************************************************
+  * @file    pwm_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __PWM_REG_H__
+#define __PWM_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : pwm_int_config */
+#define PWM_INT_CONFIG_OFFSET  (0x0)
+#define PWM_INTERRUPT_STS      PWM_INTERRUPT_STS
+#define PWM_INTERRUPT_STS_POS  (0U)
+#define PWM_INTERRUPT_STS_LEN  (6U)
+#define PWM_INTERRUPT_STS_MSK  (((1U << PWM_INTERRUPT_STS_LEN) - 1) << PWM_INTERRUPT_STS_POS)
+#define PWM_INTERRUPT_STS_UMSK (~(((1U << PWM_INTERRUPT_STS_LEN) - 1) << PWM_INTERRUPT_STS_POS))
+#define PWM_INT_CLEAR          PWM_INT_CLEAR
+#define PWM_INT_CLEAR_POS      (8U)
+#define PWM_INT_CLEAR_LEN      (6U)
+#define PWM_INT_CLEAR_MSK      (((1U << PWM_INT_CLEAR_LEN) - 1) << PWM_INT_CLEAR_POS)
+#define PWM_INT_CLEAR_UMSK     (~(((1U << PWM_INT_CLEAR_LEN) - 1) << PWM_INT_CLEAR_POS))
+
+/* 0x20 : pwm0_clkdiv */
+#define PWM0_CLKDIV_OFFSET (0x20)
+#define PWM_CLK_DIV        PWM_CLK_DIV
+#define PWM_CLK_DIV_POS    (0U)
+#define PWM_CLK_DIV_LEN    (16U)
+#define PWM_CLK_DIV_MSK    (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)
+#define PWM_CLK_DIV_UMSK   (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS))
+
+/* 0x24 : pwm0_thre1 */
+#define PWM0_THRE1_OFFSET (0x24)
+#define PWM_THRE1         PWM_THRE1
+#define PWM_THRE1_POS     (0U)
+#define PWM_THRE1_LEN     (16U)
+#define PWM_THRE1_MSK     (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)
+#define PWM_THRE1_UMSK    (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS))
+
+/* 0x28 : pwm0_thre2 */
+#define PWM0_THRE2_OFFSET (0x28)
+#define PWM_THRE2         PWM_THRE2
+#define PWM_THRE2_POS     (0U)
+#define PWM_THRE2_LEN     (16U)
+#define PWM_THRE2_MSK     (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)
+#define PWM_THRE2_UMSK    (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS))
+
+/* 0x2C : pwm0_period */
+#define PWM0_PERIOD_OFFSET (0x2C)
+#define PWM_PERIOD         PWM_PERIOD
+#define PWM_PERIOD_POS     (0U)
+#define PWM_PERIOD_LEN     (16U)
+#define PWM_PERIOD_MSK     (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)
+#define PWM_PERIOD_UMSK    (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS))
+
+/* 0x30 : pwm0_config */
+#define PWM0_CONFIG_OFFSET    (0x30)
+#define PWM_REG_CLK_SEL       PWM_REG_CLK_SEL
+#define PWM_REG_CLK_SEL_POS   (0U)
+#define PWM_REG_CLK_SEL_LEN   (2U)
+#define PWM_REG_CLK_SEL_MSK   (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)
+#define PWM_REG_CLK_SEL_UMSK  (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS))
+#define PWM_OUT_INV           PWM_OUT_INV
+#define PWM_OUT_INV_POS       (2U)
+#define PWM_OUT_INV_LEN       (1U)
+#define PWM_OUT_INV_MSK       (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)
+#define PWM_OUT_INV_UMSK      (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS))
+#define PWM_STOP_MODE         PWM_STOP_MODE
+#define PWM_STOP_MODE_POS     (3U)
+#define PWM_STOP_MODE_LEN     (1U)
+#define PWM_STOP_MODE_MSK     (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)
+#define PWM_STOP_MODE_UMSK    (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS))
+#define PWM_SW_FORCE_VAL      PWM_SW_FORCE_VAL
+#define PWM_SW_FORCE_VAL_POS  (4U)
+#define PWM_SW_FORCE_VAL_LEN  (1U)
+#define PWM_SW_FORCE_VAL_MSK  (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)
+#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS))
+#define PWM_SW_MODE           PWM_SW_MODE
+#define PWM_SW_MODE_POS       (5U)
+#define PWM_SW_MODE_LEN       (1U)
+#define PWM_SW_MODE_MSK       (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)
+#define PWM_SW_MODE_UMSK      (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS))
+#define PWM_STOP_EN           PWM_STOP_EN
+#define PWM_STOP_EN_POS       (6U)
+#define PWM_STOP_EN_LEN       (1U)
+#define PWM_STOP_EN_MSK       (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)
+#define PWM_STOP_EN_UMSK      (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS))
+#define PWM_STS_TOP           PWM_STS_TOP
+#define PWM_STS_TOP_POS       (7U)
+#define PWM_STS_TOP_LEN       (1U)
+#define PWM_STS_TOP_MSK       (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)
+#define PWM_STS_TOP_UMSK      (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS))
+
+/* 0x34 : pwm0_interrupt */
+#define PWM0_INTERRUPT_OFFSET   (0x34)
+#define PWM_INT_PERIOD_CNT      PWM_INT_PERIOD_CNT
+#define PWM_INT_PERIOD_CNT_POS  (0U)
+#define PWM_INT_PERIOD_CNT_LEN  (16U)
+#define PWM_INT_PERIOD_CNT_MSK  (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)
+#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS))
+#define PWM_INT_ENABLE          PWM_INT_ENABLE
+#define PWM_INT_ENABLE_POS      (16U)
+#define PWM_INT_ENABLE_LEN      (1U)
+#define PWM_INT_ENABLE_MSK      (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)
+#define PWM_INT_ENABLE_UMSK     (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS))
+
+/* 0x40 : pwm1_clkdiv */
+#define PWM1_CLKDIV_OFFSET (0x40)
+#define PWM_CLK_DIV        PWM_CLK_DIV
+#define PWM_CLK_DIV_POS    (0U)
+#define PWM_CLK_DIV_LEN    (16U)
+#define PWM_CLK_DIV_MSK    (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)
+#define PWM_CLK_DIV_UMSK   (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS))
+
+/* 0x44 : pwm1_thre1 */
+#define PWM1_THRE1_OFFSET (0x44)
+#define PWM_THRE1         PWM_THRE1
+#define PWM_THRE1_POS     (0U)
+#define PWM_THRE1_LEN     (16U)
+#define PWM_THRE1_MSK     (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)
+#define PWM_THRE1_UMSK    (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS))
+
+/* 0x48 : pwm1_thre2 */
+#define PWM1_THRE2_OFFSET (0x48)
+#define PWM_THRE2         PWM_THRE2
+#define PWM_THRE2_POS     (0U)
+#define PWM_THRE2_LEN     (16U)
+#define PWM_THRE2_MSK     (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)
+#define PWM_THRE2_UMSK    (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS))
+
+/* 0x4C : pwm1_period */
+#define PWM1_PERIOD_OFFSET (0x4C)
+#define PWM_PERIOD         PWM_PERIOD
+#define PWM_PERIOD_POS     (0U)
+#define PWM_PERIOD_LEN     (16U)
+#define PWM_PERIOD_MSK     (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)
+#define PWM_PERIOD_UMSK    (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS))
+
+/* 0x50 : pwm1_config */
+#define PWM1_CONFIG_OFFSET    (0x50)
+#define PWM_REG_CLK_SEL       PWM_REG_CLK_SEL
+#define PWM_REG_CLK_SEL_POS   (0U)
+#define PWM_REG_CLK_SEL_LEN   (2U)
+#define PWM_REG_CLK_SEL_MSK   (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)
+#define PWM_REG_CLK_SEL_UMSK  (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS))
+#define PWM_OUT_INV           PWM_OUT_INV
+#define PWM_OUT_INV_POS       (2U)
+#define PWM_OUT_INV_LEN       (1U)
+#define PWM_OUT_INV_MSK       (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)
+#define PWM_OUT_INV_UMSK      (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS))
+#define PWM_STOP_MODE         PWM_STOP_MODE
+#define PWM_STOP_MODE_POS     (3U)
+#define PWM_STOP_MODE_LEN     (1U)
+#define PWM_STOP_MODE_MSK     (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)
+#define PWM_STOP_MODE_UMSK    (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS))
+#define PWM_SW_FORCE_VAL      PWM_SW_FORCE_VAL
+#define PWM_SW_FORCE_VAL_POS  (4U)
+#define PWM_SW_FORCE_VAL_LEN  (1U)
+#define PWM_SW_FORCE_VAL_MSK  (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)
+#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS))
+#define PWM_SW_MODE           PWM_SW_MODE
+#define PWM_SW_MODE_POS       (5U)
+#define PWM_SW_MODE_LEN       (1U)
+#define PWM_SW_MODE_MSK       (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)
+#define PWM_SW_MODE_UMSK      (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS))
+#define PWM_STOP_EN           PWM_STOP_EN
+#define PWM_STOP_EN_POS       (6U)
+#define PWM_STOP_EN_LEN       (1U)
+#define PWM_STOP_EN_MSK       (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)
+#define PWM_STOP_EN_UMSK      (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS))
+#define PWM_STS_TOP           PWM_STS_TOP
+#define PWM_STS_TOP_POS       (7U)
+#define PWM_STS_TOP_LEN       (1U)
+#define PWM_STS_TOP_MSK       (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)
+#define PWM_STS_TOP_UMSK      (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS))
+
+/* 0x54 : pwm1_interrupt */
+#define PWM1_INTERRUPT_OFFSET   (0x54)
+#define PWM_INT_PERIOD_CNT      PWM_INT_PERIOD_CNT
+#define PWM_INT_PERIOD_CNT_POS  (0U)
+#define PWM_INT_PERIOD_CNT_LEN  (16U)
+#define PWM_INT_PERIOD_CNT_MSK  (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)
+#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS))
+#define PWM_INT_ENABLE          PWM_INT_ENABLE
+#define PWM_INT_ENABLE_POS      (16U)
+#define PWM_INT_ENABLE_LEN      (1U)
+#define PWM_INT_ENABLE_MSK      (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)
+#define PWM_INT_ENABLE_UMSK     (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS))
+
+/* 0x60 : pwm2_clkdiv */
+#define PWM2_CLKDIV_OFFSET (0x60)
+#define PWM_CLK_DIV        PWM_CLK_DIV
+#define PWM_CLK_DIV_POS    (0U)
+#define PWM_CLK_DIV_LEN    (16U)
+#define PWM_CLK_DIV_MSK    (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)
+#define PWM_CLK_DIV_UMSK   (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS))
+
+/* 0x64 : pwm2_thre1 */
+#define PWM2_THRE1_OFFSET (0x64)
+#define PWM_THRE1         PWM_THRE1
+#define PWM_THRE1_POS     (0U)
+#define PWM_THRE1_LEN     (16U)
+#define PWM_THRE1_MSK     (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)
+#define PWM_THRE1_UMSK    (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS))
+
+/* 0x68 : pwm2_thre2 */
+#define PWM2_THRE2_OFFSET (0x68)
+#define PWM_THRE2         PWM_THRE2
+#define PWM_THRE2_POS     (0U)
+#define PWM_THRE2_LEN     (16U)
+#define PWM_THRE2_MSK     (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)
+#define PWM_THRE2_UMSK    (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS))
+
+/* 0x6C : pwm2_period */
+#define PWM2_PERIOD_OFFSET (0x6C)
+#define PWM_PERIOD         PWM_PERIOD
+#define PWM_PERIOD_POS     (0U)
+#define PWM_PERIOD_LEN     (16U)
+#define PWM_PERIOD_MSK     (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)
+#define PWM_PERIOD_UMSK    (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS))
+
+/* 0x70 : pwm2_config */
+#define PWM2_CONFIG_OFFSET    (0x70)
+#define PWM_REG_CLK_SEL       PWM_REG_CLK_SEL
+#define PWM_REG_CLK_SEL_POS   (0U)
+#define PWM_REG_CLK_SEL_LEN   (2U)
+#define PWM_REG_CLK_SEL_MSK   (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)
+#define PWM_REG_CLK_SEL_UMSK  (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS))
+#define PWM_OUT_INV           PWM_OUT_INV
+#define PWM_OUT_INV_POS       (2U)
+#define PWM_OUT_INV_LEN       (1U)
+#define PWM_OUT_INV_MSK       (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)
+#define PWM_OUT_INV_UMSK      (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS))
+#define PWM_STOP_MODE         PWM_STOP_MODE
+#define PWM_STOP_MODE_POS     (3U)
+#define PWM_STOP_MODE_LEN     (1U)
+#define PWM_STOP_MODE_MSK     (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)
+#define PWM_STOP_MODE_UMSK    (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS))
+#define PWM_SW_FORCE_VAL      PWM_SW_FORCE_VAL
+#define PWM_SW_FORCE_VAL_POS  (4U)
+#define PWM_SW_FORCE_VAL_LEN  (1U)
+#define PWM_SW_FORCE_VAL_MSK  (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)
+#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS))
+#define PWM_SW_MODE           PWM_SW_MODE
+#define PWM_SW_MODE_POS       (5U)
+#define PWM_SW_MODE_LEN       (1U)
+#define PWM_SW_MODE_MSK       (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)
+#define PWM_SW_MODE_UMSK      (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS))
+#define PWM_STOP_EN           PWM_STOP_EN
+#define PWM_STOP_EN_POS       (6U)
+#define PWM_STOP_EN_LEN       (1U)
+#define PWM_STOP_EN_MSK       (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)
+#define PWM_STOP_EN_UMSK      (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS))
+#define PWM_STS_TOP           PWM_STS_TOP
+#define PWM_STS_TOP_POS       (7U)
+#define PWM_STS_TOP_LEN       (1U)
+#define PWM_STS_TOP_MSK       (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)
+#define PWM_STS_TOP_UMSK      (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS))
+
+/* 0x74 : pwm2_interrupt */
+#define PWM2_INTERRUPT_OFFSET   (0x74)
+#define PWM_INT_PERIOD_CNT      PWM_INT_PERIOD_CNT
+#define PWM_INT_PERIOD_CNT_POS  (0U)
+#define PWM_INT_PERIOD_CNT_LEN  (16U)
+#define PWM_INT_PERIOD_CNT_MSK  (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)
+#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS))
+#define PWM_INT_ENABLE          PWM_INT_ENABLE
+#define PWM_INT_ENABLE_POS      (16U)
+#define PWM_INT_ENABLE_LEN      (1U)
+#define PWM_INT_ENABLE_MSK      (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)
+#define PWM_INT_ENABLE_UMSK     (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS))
+
+/* 0x80 : pwm3_clkdiv */
+#define PWM3_CLKDIV_OFFSET (0x80)
+#define PWM_CLK_DIV        PWM_CLK_DIV
+#define PWM_CLK_DIV_POS    (0U)
+#define PWM_CLK_DIV_LEN    (16U)
+#define PWM_CLK_DIV_MSK    (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)
+#define PWM_CLK_DIV_UMSK   (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS))
+
+/* 0x84 : pwm3_thre1 */
+#define PWM3_THRE1_OFFSET (0x84)
+#define PWM_THRE1         PWM_THRE1
+#define PWM_THRE1_POS     (0U)
+#define PWM_THRE1_LEN     (16U)
+#define PWM_THRE1_MSK     (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)
+#define PWM_THRE1_UMSK    (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS))
+
+/* 0x88 : pwm3_thre2 */
+#define PWM3_THRE2_OFFSET (0x88)
+#define PWM_THRE2         PWM_THRE2
+#define PWM_THRE2_POS     (0U)
+#define PWM_THRE2_LEN     (16U)
+#define PWM_THRE2_MSK     (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)
+#define PWM_THRE2_UMSK    (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS))
+
+/* 0x8C : pwm3_period */
+#define PWM3_PERIOD_OFFSET (0x8C)
+#define PWM_PERIOD         PWM_PERIOD
+#define PWM_PERIOD_POS     (0U)
+#define PWM_PERIOD_LEN     (16U)
+#define PWM_PERIOD_MSK     (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)
+#define PWM_PERIOD_UMSK    (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS))
+
+/* 0x90 : pwm3_config */
+#define PWM3_CONFIG_OFFSET    (0x90)
+#define PWM_REG_CLK_SEL       PWM_REG_CLK_SEL
+#define PWM_REG_CLK_SEL_POS   (0U)
+#define PWM_REG_CLK_SEL_LEN   (2U)
+#define PWM_REG_CLK_SEL_MSK   (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)
+#define PWM_REG_CLK_SEL_UMSK  (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS))
+#define PWM_OUT_INV           PWM_OUT_INV
+#define PWM_OUT_INV_POS       (2U)
+#define PWM_OUT_INV_LEN       (1U)
+#define PWM_OUT_INV_MSK       (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)
+#define PWM_OUT_INV_UMSK      (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS))
+#define PWM_STOP_MODE         PWM_STOP_MODE
+#define PWM_STOP_MODE_POS     (3U)
+#define PWM_STOP_MODE_LEN     (1U)
+#define PWM_STOP_MODE_MSK     (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)
+#define PWM_STOP_MODE_UMSK    (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS))
+#define PWM_SW_FORCE_VAL      PWM_SW_FORCE_VAL
+#define PWM_SW_FORCE_VAL_POS  (4U)
+#define PWM_SW_FORCE_VAL_LEN  (1U)
+#define PWM_SW_FORCE_VAL_MSK  (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)
+#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS))
+#define PWM_SW_MODE           PWM_SW_MODE
+#define PWM_SW_MODE_POS       (5U)
+#define PWM_SW_MODE_LEN       (1U)
+#define PWM_SW_MODE_MSK       (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)
+#define PWM_SW_MODE_UMSK      (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS))
+#define PWM_STOP_EN           PWM_STOP_EN
+#define PWM_STOP_EN_POS       (6U)
+#define PWM_STOP_EN_LEN       (1U)
+#define PWM_STOP_EN_MSK       (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)
+#define PWM_STOP_EN_UMSK      (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS))
+#define PWM_STS_TOP           PWM_STS_TOP
+#define PWM_STS_TOP_POS       (7U)
+#define PWM_STS_TOP_LEN       (1U)
+#define PWM_STS_TOP_MSK       (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)
+#define PWM_STS_TOP_UMSK      (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS))
+
+/* 0x94 : pwm3_interrupt */
+#define PWM3_INTERRUPT_OFFSET   (0x94)
+#define PWM_INT_PERIOD_CNT      PWM_INT_PERIOD_CNT
+#define PWM_INT_PERIOD_CNT_POS  (0U)
+#define PWM_INT_PERIOD_CNT_LEN  (16U)
+#define PWM_INT_PERIOD_CNT_MSK  (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)
+#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS))
+#define PWM_INT_ENABLE          PWM_INT_ENABLE
+#define PWM_INT_ENABLE_POS      (16U)
+#define PWM_INT_ENABLE_LEN      (1U)
+#define PWM_INT_ENABLE_MSK      (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)
+#define PWM_INT_ENABLE_UMSK     (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS))
+
+/* 0xA0 : pwm4_clkdiv */
+#define PWM4_CLKDIV_OFFSET (0xA0)
+#define PWM_CLK_DIV        PWM_CLK_DIV
+#define PWM_CLK_DIV_POS    (0U)
+#define PWM_CLK_DIV_LEN    (16U)
+#define PWM_CLK_DIV_MSK    (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)
+#define PWM_CLK_DIV_UMSK   (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS))
+
+/* 0xA4 : pwm4_thre1 */
+#define PWM4_THRE1_OFFSET (0xA4)
+#define PWM_THRE1         PWM_THRE1
+#define PWM_THRE1_POS     (0U)
+#define PWM_THRE1_LEN     (16U)
+#define PWM_THRE1_MSK     (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)
+#define PWM_THRE1_UMSK    (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS))
+
+/* 0xA8 : pwm4_thre2 */
+#define PWM4_THRE2_OFFSET (0xA8)
+#define PWM_THRE2         PWM_THRE2
+#define PWM_THRE2_POS     (0U)
+#define PWM_THRE2_LEN     (16U)
+#define PWM_THRE2_MSK     (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)
+#define PWM_THRE2_UMSK    (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS))
+
+/* 0xAC : pwm4_period */
+#define PWM4_PERIOD_OFFSET (0xAC)
+#define PWM_PERIOD         PWM_PERIOD
+#define PWM_PERIOD_POS     (0U)
+#define PWM_PERIOD_LEN     (16U)
+#define PWM_PERIOD_MSK     (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)
+#define PWM_PERIOD_UMSK    (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS))
+
+/* 0xB0 : pwm4_config */
+#define PWM4_CONFIG_OFFSET    (0xB0)
+#define PWM_REG_CLK_SEL       PWM_REG_CLK_SEL
+#define PWM_REG_CLK_SEL_POS   (0U)
+#define PWM_REG_CLK_SEL_LEN   (2U)
+#define PWM_REG_CLK_SEL_MSK   (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)
+#define PWM_REG_CLK_SEL_UMSK  (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS))
+#define PWM_OUT_INV           PWM_OUT_INV
+#define PWM_OUT_INV_POS       (2U)
+#define PWM_OUT_INV_LEN       (1U)
+#define PWM_OUT_INV_MSK       (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)
+#define PWM_OUT_INV_UMSK      (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS))
+#define PWM_STOP_MODE         PWM_STOP_MODE
+#define PWM_STOP_MODE_POS     (3U)
+#define PWM_STOP_MODE_LEN     (1U)
+#define PWM_STOP_MODE_MSK     (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)
+#define PWM_STOP_MODE_UMSK    (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS))
+#define PWM_SW_FORCE_VAL      PWM_SW_FORCE_VAL
+#define PWM_SW_FORCE_VAL_POS  (4U)
+#define PWM_SW_FORCE_VAL_LEN  (1U)
+#define PWM_SW_FORCE_VAL_MSK  (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)
+#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS))
+#define PWM_SW_MODE           PWM_SW_MODE
+#define PWM_SW_MODE_POS       (5U)
+#define PWM_SW_MODE_LEN       (1U)
+#define PWM_SW_MODE_MSK       (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)
+#define PWM_SW_MODE_UMSK      (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS))
+#define PWM_STOP_EN           PWM_STOP_EN
+#define PWM_STOP_EN_POS       (6U)
+#define PWM_STOP_EN_LEN       (1U)
+#define PWM_STOP_EN_MSK       (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)
+#define PWM_STOP_EN_UMSK      (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS))
+#define PWM_STS_TOP           PWM_STS_TOP
+#define PWM_STS_TOP_POS       (7U)
+#define PWM_STS_TOP_LEN       (1U)
+#define PWM_STS_TOP_MSK       (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)
+#define PWM_STS_TOP_UMSK      (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS))
+
+/* 0xB4 : pwm4_interrupt */
+#define PWM4_INTERRUPT_OFFSET   (0xB4)
+#define PWM_INT_PERIOD_CNT      PWM_INT_PERIOD_CNT
+#define PWM_INT_PERIOD_CNT_POS  (0U)
+#define PWM_INT_PERIOD_CNT_LEN  (16U)
+#define PWM_INT_PERIOD_CNT_MSK  (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)
+#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS))
+#define PWM_INT_ENABLE          PWM_INT_ENABLE
+#define PWM_INT_ENABLE_POS      (16U)
+#define PWM_INT_ENABLE_LEN      (1U)
+#define PWM_INT_ENABLE_MSK      (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)
+#define PWM_INT_ENABLE_UMSK     (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS))
+
+struct pwm_reg {
+    /* 0x0 : pwm_int_config */
+    union {
+        struct
+        {
+            uint32_t pwm_interrupt_sts : 6;  /* [ 5: 0],          r,        0x0 */
+            uint32_t reserved_6_7      : 2;  /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t pwm_int_clear     : 6;  /* [13: 8],          w,        0x0 */
+            uint32_t reserved_14_31    : 18; /* [31:14],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm_int_config;
+
+    /* 0x4  reserved */
+    uint8_t RESERVED0x4[28];
+
+    /* 0x20 : pwm0_clkdiv */
+    union {
+        struct
+        {
+            uint32_t pwm_clk_div    : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm0_clkdiv;
+
+    /* 0x24 : pwm0_thre1 */
+    union {
+        struct
+        {
+            uint32_t pwm_thre1      : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm0_thre1;
+
+    /* 0x28 : pwm0_thre2 */
+    union {
+        struct
+        {
+            uint32_t pwm_thre2      : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm0_thre2;
+
+    /* 0x2C : pwm0_period */
+    union {
+        struct
+        {
+            uint32_t pwm_period     : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm0_period;
+
+    /* 0x30 : pwm0_config */
+    union {
+        struct
+        {
+            uint32_t reg_clk_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t pwm_out_inv      : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t pwm_stop_mode    : 1;  /* [    3],        r/w,        0x1 */
+            uint32_t pwm_sw_force_val : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t pwm_sw_mode      : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t pwm_stop_en      : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t pwm_sts_top      : 1;  /* [    7],          r,        0x0 */
+            uint32_t reserved_8_31    : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm0_config;
+
+    /* 0x34 : pwm0_interrupt */
+    union {
+        struct
+        {
+            uint32_t pwm_int_period_cnt : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t pwm_int_enable     : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17_31     : 15; /* [31:17],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm0_interrupt;
+
+    /* 0x38  reserved */
+    uint8_t RESERVED0x38[8];
+
+    /* 0x40 : pwm1_clkdiv */
+    union {
+        struct
+        {
+            uint32_t pwm_clk_div    : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm1_clkdiv;
+
+    /* 0x44 : pwm1_thre1 */
+    union {
+        struct
+        {
+            uint32_t pwm_thre1      : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm1_thre1;
+
+    /* 0x48 : pwm1_thre2 */
+    union {
+        struct
+        {
+            uint32_t pwm_thre2      : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm1_thre2;
+
+    /* 0x4C : pwm1_period */
+    union {
+        struct
+        {
+            uint32_t pwm_period     : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm1_period;
+
+    /* 0x50 : pwm1_config */
+    union {
+        struct
+        {
+            uint32_t reg_clk_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t pwm_out_inv      : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t pwm_stop_mode    : 1;  /* [    3],        r/w,        0x1 */
+            uint32_t pwm_sw_force_val : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t pwm_sw_mode      : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t pwm_stop_en      : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t pwm_sts_top      : 1;  /* [    7],          r,        0x0 */
+            uint32_t reserved_8_31    : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm1_config;
+
+    /* 0x54 : pwm1_interrupt */
+    union {
+        struct
+        {
+            uint32_t pwm_int_period_cnt : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t pwm_int_enable     : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17_31     : 15; /* [31:17],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm1_interrupt;
+
+    /* 0x58  reserved */
+    uint8_t RESERVED0x58[8];
+
+    /* 0x60 : pwm2_clkdiv */
+    union {
+        struct
+        {
+            uint32_t pwm_clk_div    : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm2_clkdiv;
+
+    /* 0x64 : pwm2_thre1 */
+    union {
+        struct
+        {
+            uint32_t pwm_thre1      : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm2_thre1;
+
+    /* 0x68 : pwm2_thre2 */
+    union {
+        struct
+        {
+            uint32_t pwm_thre2      : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm2_thre2;
+
+    /* 0x6C : pwm2_period */
+    union {
+        struct
+        {
+            uint32_t pwm_period     : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm2_period;
+
+    /* 0x70 : pwm2_config */
+    union {
+        struct
+        {
+            uint32_t reg_clk_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t pwm_out_inv      : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t pwm_stop_mode    : 1;  /* [    3],        r/w,        0x1 */
+            uint32_t pwm_sw_force_val : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t pwm_sw_mode      : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t pwm_stop_en      : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t pwm_sts_top      : 1;  /* [    7],          r,        0x0 */
+            uint32_t reserved_8_31    : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm2_config;
+
+    /* 0x74 : pwm2_interrupt */
+    union {
+        struct
+        {
+            uint32_t pwm_int_period_cnt : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t pwm_int_enable     : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17_31     : 15; /* [31:17],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm2_interrupt;
+
+    /* 0x78  reserved */
+    uint8_t RESERVED0x78[8];
+
+    /* 0x80 : pwm3_clkdiv */
+    union {
+        struct
+        {
+            uint32_t pwm_clk_div    : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm3_clkdiv;
+
+    /* 0x84 : pwm3_thre1 */
+    union {
+        struct
+        {
+            uint32_t pwm_thre1      : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm3_thre1;
+
+    /* 0x88 : pwm3_thre2 */
+    union {
+        struct
+        {
+            uint32_t pwm_thre2      : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm3_thre2;
+
+    /* 0x8C : pwm3_period */
+    union {
+        struct
+        {
+            uint32_t pwm_period     : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm3_period;
+
+    /* 0x90 : pwm3_config */
+    union {
+        struct
+        {
+            uint32_t reg_clk_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t pwm_out_inv      : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t pwm_stop_mode    : 1;  /* [    3],        r/w,        0x1 */
+            uint32_t pwm_sw_force_val : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t pwm_sw_mode      : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t pwm_stop_en      : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t pwm_sts_top      : 1;  /* [    7],          r,        0x0 */
+            uint32_t reserved_8_31    : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm3_config;
+
+    /* 0x94 : pwm3_interrupt */
+    union {
+        struct
+        {
+            uint32_t pwm_int_period_cnt : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t pwm_int_enable     : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17_31     : 15; /* [31:17],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm3_interrupt;
+
+    /* 0x98  reserved */
+    uint8_t RESERVED0x98[8];
+
+    /* 0xA0 : pwm4_clkdiv */
+    union {
+        struct
+        {
+            uint32_t pwm_clk_div    : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm4_clkdiv;
+
+    /* 0xA4 : pwm4_thre1 */
+    union {
+        struct
+        {
+            uint32_t pwm_thre1      : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm4_thre1;
+
+    /* 0xA8 : pwm4_thre2 */
+    union {
+        struct
+        {
+            uint32_t pwm_thre2      : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm4_thre2;
+
+    /* 0xAC : pwm4_period */
+    union {
+        struct
+        {
+            uint32_t pwm_period     : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm4_period;
+
+    /* 0xB0 : pwm4_config */
+    union {
+        struct
+        {
+            uint32_t reg_clk_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t pwm_out_inv      : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t pwm_stop_mode    : 1;  /* [    3],        r/w,        0x1 */
+            uint32_t pwm_sw_force_val : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t pwm_sw_mode      : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t pwm_stop_en      : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t pwm_sts_top      : 1;  /* [    7],          r,        0x0 */
+            uint32_t reserved_8_31    : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm4_config;
+
+    /* 0xB4 : pwm4_interrupt */
+    union {
+        struct
+        {
+            uint32_t pwm_int_period_cnt : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t pwm_int_enable     : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17_31     : 15; /* [31:17],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm4_interrupt;
+};
+
+typedef volatile struct pwm_reg pwm_reg_t;
+
+/*Following is reg patch*/
+
+/* 0x0 : pwm_clkdiv */
+#define PWM_CLKDIV_OFFSET (0x0)
+#define PWM_CLK_DIV       PWM_CLK_DIV
+#define PWM_CLK_DIV_POS   (0U)
+#define PWM_CLK_DIV_LEN   (16U)
+#define PWM_CLK_DIV_MSK   (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)
+#define PWM_CLK_DIV_UMSK  (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS))
+
+/* 0x4 : pwm_thre1 */
+#define PWM_THRE1_OFFSET (0x4)
+#define PWM_THRE1        PWM_THRE1
+#define PWM_THRE1_POS    (0U)
+#define PWM_THRE1_LEN    (16U)
+#define PWM_THRE1_MSK    (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)
+#define PWM_THRE1_UMSK   (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS))
+
+/* 0x8 : pwm_thre2 */
+#define PWM_THRE2_OFFSET (0x8)
+#define PWM_THRE2        PWM_THRE2
+#define PWM_THRE2_POS    (0U)
+#define PWM_THRE2_LEN    (16U)
+#define PWM_THRE2_MSK    (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)
+#define PWM_THRE2_UMSK   (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS))
+
+/* 0xc : pwm_period */
+#define PWM_PERIOD_OFFSET (0xc)
+#define PWM_PERIOD        PWM_PERIOD
+#define PWM_PERIOD_POS    (0U)
+#define PWM_PERIOD_LEN    (16U)
+#define PWM_PERIOD_MSK    (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)
+#define PWM_PERIOD_UMSK   (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS))
+
+/* 0x10 : pwm_config */
+#define PWM_CONFIG_OFFSET     (0x10)
+#define PWM_REG_CLK_SEL       PWM_REG_CLK_SEL
+#define PWM_REG_CLK_SEL_POS   (0U)
+#define PWM_REG_CLK_SEL_LEN   (2U)
+#define PWM_REG_CLK_SEL_MSK   (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)
+#define PWM_REG_CLK_SEL_UMSK  (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS))
+#define PWM_OUT_INV           PWM_OUT_INV
+#define PWM_OUT_INV_POS       (2U)
+#define PWM_OUT_INV_LEN       (1U)
+#define PWM_OUT_INV_MSK       (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)
+#define PWM_OUT_INV_UMSK      (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS))
+#define PWM_STOP_MODE         PWM_STOP_MODE
+#define PWM_STOP_MODE_POS     (3U)
+#define PWM_STOP_MODE_LEN     (1U)
+#define PWM_STOP_MODE_MSK     (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)
+#define PWM_STOP_MODE_UMSK    (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS))
+#define PWM_SW_FORCE_VAL      PWM_SW_FORCE_VAL
+#define PWM_SW_FORCE_VAL_POS  (4U)
+#define PWM_SW_FORCE_VAL_LEN  (1U)
+#define PWM_SW_FORCE_VAL_MSK  (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)
+#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS))
+#define PWM_SW_MODE           PWM_SW_MODE
+#define PWM_SW_MODE_POS       (5U)
+#define PWM_SW_MODE_LEN       (1U)
+#define PWM_SW_MODE_MSK       (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)
+#define PWM_SW_MODE_UMSK      (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS))
+#define PWM_STOP_EN           PWM_STOP_EN
+#define PWM_STOP_EN_POS       (6U)
+#define PWM_STOP_EN_LEN       (1U)
+#define PWM_STOP_EN_MSK       (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)
+#define PWM_STOP_EN_UMSK      (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS))
+#define PWM_STS_TOP           PWM_STS_TOP
+#define PWM_STS_TOP_POS       (7U)
+#define PWM_STS_TOP_LEN       (1U)
+#define PWM_STS_TOP_MSK       (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)
+#define PWM_STS_TOP_UMSK      (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS))
+
+/* 0x14 : pwm_interrupt */
+#define PWM_INTERRUPT_OFFSET    (0x14)
+#define PWM_INT_PERIOD_CNT      PWM_INT_PERIOD_CNT
+#define PWM_INT_PERIOD_CNT_POS  (0U)
+#define PWM_INT_PERIOD_CNT_LEN  (16U)
+#define PWM_INT_PERIOD_CNT_MSK  (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)
+#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS))
+#define PWM_INT_ENABLE          PWM_INT_ENABLE
+#define PWM_INT_ENABLE_POS      (16U)
+#define PWM_INT_ENABLE_LEN      (1U)
+#define PWM_INT_ENABLE_MSK      (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)
+#define PWM_INT_ENABLE_UMSK     (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS))
+
+struct pwm_channel_reg {
+    /* 0x0 : pwm_clkdiv */
+    union {
+        struct
+        {
+            uint32_t pwm_clk_div    : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm_clkdiv;
+
+    /* 0x4 : pwm_thre1 */
+    union {
+        struct
+        {
+            uint32_t pwm_thre1      : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm_thre1;
+
+    /* 0x8 : pwm_thre2 */
+    union {
+        struct
+        {
+            uint32_t pwm_thre2      : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm_thre2;
+
+    /* 0xc : pwm_period */
+    union {
+        struct
+        {
+            uint32_t pwm_period     : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm_period;
+
+    /* 0x10 : pwm_config */
+    union {
+        struct
+        {
+            uint32_t reg_clk_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t pwm_out_inv      : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t pwm_stop_mode    : 1;  /* [    3],        r/w,        0x1 */
+            uint32_t pwm_sw_force_val : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t pwm_sw_mode      : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t pwm_stop_en      : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t pwm_sts_top      : 1;  /* [    7],          r,        0x0 */
+            uint32_t reserved_8_31    : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm_config;
+
+    /* 0x14 : pwm_interrupt */
+    union {
+        struct
+        {
+            uint32_t pwm_int_period_cnt : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t pwm_int_enable     : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17_31     : 15; /* [31:17],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm_interrupt;
+};
+
+typedef volatile struct pwm_channel_reg pwm_channel_reg_t;
+
+#define PWM_CHANNEL_OFFSET 0x20
+
+#endif /* __PWM_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/qdec_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/qdec_reg.h
new file mode 100644
index 00000000..4883db09
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/qdec_reg.h
@@ -0,0 +1,768 @@
+/**
+  ******************************************************************************
+  * @file    qdec_reg.h
+  * @version V1.2
+  * @date    2020-04-08
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __QDEC_REG_H__
+#define __QDEC_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : qdec0_ctrl0 */
+#define QDEC0_CTRL0_OFFSET   (0x0)
+#define QDEC_EN              QDEC_EN
+#define QDEC_EN_POS          (0U)
+#define QDEC_EN_LEN          (1U)
+#define QDEC_EN_MSK          (((1U << QDEC_EN_LEN) - 1) << QDEC_EN_POS)
+#define QDEC_EN_UMSK         (~(((1U << QDEC_EN_LEN) - 1) << QDEC_EN_POS))
+#define QDEC_LED_EN          QDEC_LED_EN
+#define QDEC_LED_EN_POS      (1U)
+#define QDEC_LED_EN_LEN      (1U)
+#define QDEC_LED_EN_MSK      (((1U << QDEC_LED_EN_LEN) - 1) << QDEC_LED_EN_POS)
+#define QDEC_LED_EN_UMSK     (~(((1U << QDEC_LED_EN_LEN) - 1) << QDEC_LED_EN_POS))
+#define QDEC_LED_POL         QDEC_LED_POL
+#define QDEC_LED_POL_POS     (2U)
+#define QDEC_LED_POL_LEN     (1U)
+#define QDEC_LED_POL_MSK     (((1U << QDEC_LED_POL_LEN) - 1) << QDEC_LED_POL_POS)
+#define QDEC_LED_POL_UMSK    (~(((1U << QDEC_LED_POL_LEN) - 1) << QDEC_LED_POL_POS))
+#define QDEC_DEG_EN          QDEC_DEG_EN
+#define QDEC_DEG_EN_POS      (3U)
+#define QDEC_DEG_EN_LEN      (1U)
+#define QDEC_DEG_EN_MSK      (((1U << QDEC_DEG_EN_LEN) - 1) << QDEC_DEG_EN_POS)
+#define QDEC_DEG_EN_UMSK     (~(((1U << QDEC_DEG_EN_LEN) - 1) << QDEC_DEG_EN_POS))
+#define QDEC_DEG_CNT         QDEC_DEG_CNT
+#define QDEC_DEG_CNT_POS     (4U)
+#define QDEC_DEG_CNT_LEN     (4U)
+#define QDEC_DEG_CNT_MSK     (((1U << QDEC_DEG_CNT_LEN) - 1) << QDEC_DEG_CNT_POS)
+#define QDEC_DEG_CNT_UMSK    (~(((1U << QDEC_DEG_CNT_LEN) - 1) << QDEC_DEG_CNT_POS))
+#define QDEC_SPL_PERIOD      QDEC_SPL_PERIOD
+#define QDEC_SPL_PERIOD_POS  (8U)
+#define QDEC_SPL_PERIOD_LEN  (4U)
+#define QDEC_SPL_PERIOD_MSK  (((1U << QDEC_SPL_PERIOD_LEN) - 1) << QDEC_SPL_PERIOD_POS)
+#define QDEC_SPL_PERIOD_UMSK (~(((1U << QDEC_SPL_PERIOD_LEN) - 1) << QDEC_SPL_PERIOD_POS))
+#define QDEC_RPT_PERIOD      QDEC_RPT_PERIOD
+#define QDEC_RPT_PERIOD_POS  (12U)
+#define QDEC_RPT_PERIOD_LEN  (16U)
+#define QDEC_RPT_PERIOD_MSK  (((1U << QDEC_RPT_PERIOD_LEN) - 1) << QDEC_RPT_PERIOD_POS)
+#define QDEC_RPT_PERIOD_UMSK (~(((1U << QDEC_RPT_PERIOD_LEN) - 1) << QDEC_RPT_PERIOD_POS))
+
+/* 0x4 : qdec0_ctrl1 */
+#define QDEC0_CTRL1_OFFSET   (0x4)
+#define QDEC_ACC_MODE        QDEC_ACC_MODE
+#define QDEC_ACC_MODE_POS    (0U)
+#define QDEC_ACC_MODE_LEN    (1U)
+#define QDEC_ACC_MODE_MSK    (((1U << QDEC_ACC_MODE_LEN) - 1) << QDEC_ACC_MODE_POS)
+#define QDEC_ACC_MODE_UMSK   (~(((1U << QDEC_ACC_MODE_LEN) - 1) << QDEC_ACC_MODE_POS))
+#define QDEC_SPL_MODE        QDEC_SPL_MODE
+#define QDEC_SPL_MODE_POS    (1U)
+#define QDEC_SPL_MODE_LEN    (1U)
+#define QDEC_SPL_MODE_MSK    (((1U << QDEC_SPL_MODE_LEN) - 1) << QDEC_SPL_MODE_POS)
+#define QDEC_SPL_MODE_UMSK   (~(((1U << QDEC_SPL_MODE_LEN) - 1) << QDEC_SPL_MODE_POS))
+#define QDEC_RPT_MODE        QDEC_RPT_MODE
+#define QDEC_RPT_MODE_POS    (2U)
+#define QDEC_RPT_MODE_LEN    (1U)
+#define QDEC_RPT_MODE_MSK    (((1U << QDEC_RPT_MODE_LEN) - 1) << QDEC_RPT_MODE_POS)
+#define QDEC_RPT_MODE_UMSK   (~(((1U << QDEC_RPT_MODE_LEN) - 1) << QDEC_RPT_MODE_POS))
+#define QDEC_INPUT_SWAP      QDEC_INPUT_SWAP
+#define QDEC_INPUT_SWAP_POS  (3U)
+#define QDEC_INPUT_SWAP_LEN  (1U)
+#define QDEC_INPUT_SWAP_MSK  (((1U << QDEC_INPUT_SWAP_LEN) - 1) << QDEC_INPUT_SWAP_POS)
+#define QDEC_INPUT_SWAP_UMSK (~(((1U << QDEC_INPUT_SWAP_LEN) - 1) << QDEC_INPUT_SWAP_POS))
+#define QDEC_LED_PERIOD      QDEC_LED_PERIOD
+#define QDEC_LED_PERIOD_POS  (16U)
+#define QDEC_LED_PERIOD_LEN  (9U)
+#define QDEC_LED_PERIOD_MSK  (((1U << QDEC_LED_PERIOD_LEN) - 1) << QDEC_LED_PERIOD_POS)
+#define QDEC_LED_PERIOD_UMSK (~(((1U << QDEC_LED_PERIOD_LEN) - 1) << QDEC_LED_PERIOD_POS))
+
+/* 0x8 : qdec0_value */
+#define QDEC0_VALUE_OFFSET (0x8)
+#define QDEC_ACC1_VAL      QDEC_ACC1_VAL
+#define QDEC_ACC1_VAL_POS  (0U)
+#define QDEC_ACC1_VAL_LEN  (16U)
+#define QDEC_ACC1_VAL_MSK  (((1U << QDEC_ACC1_VAL_LEN) - 1) << QDEC_ACC1_VAL_POS)
+#define QDEC_ACC1_VAL_UMSK (~(((1U << QDEC_ACC1_VAL_LEN) - 1) << QDEC_ACC1_VAL_POS))
+#define QDEC_ACC2_VAL      QDEC_ACC2_VAL
+#define QDEC_ACC2_VAL_POS  (16U)
+#define QDEC_ACC2_VAL_LEN  (4U)
+#define QDEC_ACC2_VAL_MSK  (((1U << QDEC_ACC2_VAL_LEN) - 1) << QDEC_ACC2_VAL_POS)
+#define QDEC_ACC2_VAL_UMSK (~(((1U << QDEC_ACC2_VAL_LEN) - 1) << QDEC_ACC2_VAL_POS))
+#define QDEC_SPL_VAL       QDEC_SPL_VAL
+#define QDEC_SPL_VAL_POS   (28U)
+#define QDEC_SPL_VAL_LEN   (2U)
+#define QDEC_SPL_VAL_MSK   (((1U << QDEC_SPL_VAL_LEN) - 1) << QDEC_SPL_VAL_POS)
+#define QDEC_SPL_VAL_UMSK  (~(((1U << QDEC_SPL_VAL_LEN) - 1) << QDEC_SPL_VAL_POS))
+
+/* 0x10 : qdec0_int_en */
+#define QDEC0_INT_EN_OFFSET   (0x10)
+#define QDEC_RPT_RDY_EN       QDEC_RPT_RDY_EN
+#define QDEC_RPT_RDY_EN_POS   (0U)
+#define QDEC_RPT_RDY_EN_LEN   (1U)
+#define QDEC_RPT_RDY_EN_MSK   (((1U << QDEC_RPT_RDY_EN_LEN) - 1) << QDEC_RPT_RDY_EN_POS)
+#define QDEC_RPT_RDY_EN_UMSK  (~(((1U << QDEC_RPT_RDY_EN_LEN) - 1) << QDEC_RPT_RDY_EN_POS))
+#define QDEC_SPL_RDY_EN       QDEC_SPL_RDY_EN
+#define QDEC_SPL_RDY_EN_POS   (1U)
+#define QDEC_SPL_RDY_EN_LEN   (1U)
+#define QDEC_SPL_RDY_EN_MSK   (((1U << QDEC_SPL_RDY_EN_LEN) - 1) << QDEC_SPL_RDY_EN_POS)
+#define QDEC_SPL_RDY_EN_UMSK  (~(((1U << QDEC_SPL_RDY_EN_LEN) - 1) << QDEC_SPL_RDY_EN_POS))
+#define QDEC_DBL_RDY_EN       QDEC_DBL_RDY_EN
+#define QDEC_DBL_RDY_EN_POS   (2U)
+#define QDEC_DBL_RDY_EN_LEN   (1U)
+#define QDEC_DBL_RDY_EN_MSK   (((1U << QDEC_DBL_RDY_EN_LEN) - 1) << QDEC_DBL_RDY_EN_POS)
+#define QDEC_DBL_RDY_EN_UMSK  (~(((1U << QDEC_DBL_RDY_EN_LEN) - 1) << QDEC_DBL_RDY_EN_POS))
+#define QDEC_OVERFLOW_EN      QDEC_OVERFLOW_EN
+#define QDEC_OVERFLOW_EN_POS  (3U)
+#define QDEC_OVERFLOW_EN_LEN  (1U)
+#define QDEC_OVERFLOW_EN_MSK  (((1U << QDEC_OVERFLOW_EN_LEN) - 1) << QDEC_OVERFLOW_EN_POS)
+#define QDEC_OVERFLOW_EN_UMSK (~(((1U << QDEC_OVERFLOW_EN_LEN) - 1) << QDEC_OVERFLOW_EN_POS))
+
+/* 0x14 : qdec0_int_sts */
+#define QDEC0_INT_STS_OFFSET   (0x14)
+#define QDEC_RPT_RDY_STS       QDEC_RPT_RDY_STS
+#define QDEC_RPT_RDY_STS_POS   (0U)
+#define QDEC_RPT_RDY_STS_LEN   (1U)
+#define QDEC_RPT_RDY_STS_MSK   (((1U << QDEC_RPT_RDY_STS_LEN) - 1) << QDEC_RPT_RDY_STS_POS)
+#define QDEC_RPT_RDY_STS_UMSK  (~(((1U << QDEC_RPT_RDY_STS_LEN) - 1) << QDEC_RPT_RDY_STS_POS))
+#define QDEC_SPL_RDY_STS       QDEC_SPL_RDY_STS
+#define QDEC_SPL_RDY_STS_POS   (1U)
+#define QDEC_SPL_RDY_STS_LEN   (1U)
+#define QDEC_SPL_RDY_STS_MSK   (((1U << QDEC_SPL_RDY_STS_LEN) - 1) << QDEC_SPL_RDY_STS_POS)
+#define QDEC_SPL_RDY_STS_UMSK  (~(((1U << QDEC_SPL_RDY_STS_LEN) - 1) << QDEC_SPL_RDY_STS_POS))
+#define QDEC_DBL_RDY_STS       QDEC_DBL_RDY_STS
+#define QDEC_DBL_RDY_STS_POS   (2U)
+#define QDEC_DBL_RDY_STS_LEN   (1U)
+#define QDEC_DBL_RDY_STS_MSK   (((1U << QDEC_DBL_RDY_STS_LEN) - 1) << QDEC_DBL_RDY_STS_POS)
+#define QDEC_DBL_RDY_STS_UMSK  (~(((1U << QDEC_DBL_RDY_STS_LEN) - 1) << QDEC_DBL_RDY_STS_POS))
+#define QDEC_OVERFLOW_STS      QDEC_OVERFLOW_STS
+#define QDEC_OVERFLOW_STS_POS  (3U)
+#define QDEC_OVERFLOW_STS_LEN  (1U)
+#define QDEC_OVERFLOW_STS_MSK  (((1U << QDEC_OVERFLOW_STS_LEN) - 1) << QDEC_OVERFLOW_STS_POS)
+#define QDEC_OVERFLOW_STS_UMSK (~(((1U << QDEC_OVERFLOW_STS_LEN) - 1) << QDEC_OVERFLOW_STS_POS))
+
+/* 0x18 : qdec0_int_clr */
+#define QDEC0_INT_CLR_OFFSET   (0x18)
+#define QDEC_RPT_RDY_CLR       QDEC_RPT_RDY_CLR
+#define QDEC_RPT_RDY_CLR_POS   (0U)
+#define QDEC_RPT_RDY_CLR_LEN   (1U)
+#define QDEC_RPT_RDY_CLR_MSK   (((1U << QDEC_RPT_RDY_CLR_LEN) - 1) << QDEC_RPT_RDY_CLR_POS)
+#define QDEC_RPT_RDY_CLR_UMSK  (~(((1U << QDEC_RPT_RDY_CLR_LEN) - 1) << QDEC_RPT_RDY_CLR_POS))
+#define QDEC_SPL_RDY_CLR       QDEC_SPL_RDY_CLR
+#define QDEC_SPL_RDY_CLR_POS   (1U)
+#define QDEC_SPL_RDY_CLR_LEN   (1U)
+#define QDEC_SPL_RDY_CLR_MSK   (((1U << QDEC_SPL_RDY_CLR_LEN) - 1) << QDEC_SPL_RDY_CLR_POS)
+#define QDEC_SPL_RDY_CLR_UMSK  (~(((1U << QDEC_SPL_RDY_CLR_LEN) - 1) << QDEC_SPL_RDY_CLR_POS))
+#define QDEC_DBL_RDY_CLR       QDEC_DBL_RDY_CLR
+#define QDEC_DBL_RDY_CLR_POS   (2U)
+#define QDEC_DBL_RDY_CLR_LEN   (1U)
+#define QDEC_DBL_RDY_CLR_MSK   (((1U << QDEC_DBL_RDY_CLR_LEN) - 1) << QDEC_DBL_RDY_CLR_POS)
+#define QDEC_DBL_RDY_CLR_UMSK  (~(((1U << QDEC_DBL_RDY_CLR_LEN) - 1) << QDEC_DBL_RDY_CLR_POS))
+#define QDEC_OVERFLOW_CLR      QDEC_OVERFLOW_CLR
+#define QDEC_OVERFLOW_CLR_POS  (3U)
+#define QDEC_OVERFLOW_CLR_LEN  (1U)
+#define QDEC_OVERFLOW_CLR_MSK  (((1U << QDEC_OVERFLOW_CLR_LEN) - 1) << QDEC_OVERFLOW_CLR_POS)
+#define QDEC_OVERFLOW_CLR_UMSK (~(((1U << QDEC_OVERFLOW_CLR_LEN) - 1) << QDEC_OVERFLOW_CLR_POS))
+
+/* 0x40 : qdec1_ctrl0 */
+#define QDEC1_CTRL0_OFFSET   (0x40)
+#define QDEC_EN              QDEC_EN
+#define QDEC_EN_POS          (0U)
+#define QDEC_EN_LEN          (1U)
+#define QDEC_EN_MSK          (((1U << QDEC_EN_LEN) - 1) << QDEC_EN_POS)
+#define QDEC_EN_UMSK         (~(((1U << QDEC_EN_LEN) - 1) << QDEC_EN_POS))
+#define QDEC_LED_EN          QDEC_LED_EN
+#define QDEC_LED_EN_POS      (1U)
+#define QDEC_LED_EN_LEN      (1U)
+#define QDEC_LED_EN_MSK      (((1U << QDEC_LED_EN_LEN) - 1) << QDEC_LED_EN_POS)
+#define QDEC_LED_EN_UMSK     (~(((1U << QDEC_LED_EN_LEN) - 1) << QDEC_LED_EN_POS))
+#define QDEC_LED_POL         QDEC_LED_POL
+#define QDEC_LED_POL_POS     (2U)
+#define QDEC_LED_POL_LEN     (1U)
+#define QDEC_LED_POL_MSK     (((1U << QDEC_LED_POL_LEN) - 1) << QDEC_LED_POL_POS)
+#define QDEC_LED_POL_UMSK    (~(((1U << QDEC_LED_POL_LEN) - 1) << QDEC_LED_POL_POS))
+#define QDEC_DEG_EN          QDEC_DEG_EN
+#define QDEC_DEG_EN_POS      (3U)
+#define QDEC_DEG_EN_LEN      (1U)
+#define QDEC_DEG_EN_MSK      (((1U << QDEC_DEG_EN_LEN) - 1) << QDEC_DEG_EN_POS)
+#define QDEC_DEG_EN_UMSK     (~(((1U << QDEC_DEG_EN_LEN) - 1) << QDEC_DEG_EN_POS))
+#define QDEC_DEG_CNT         QDEC_DEG_CNT
+#define QDEC_DEG_CNT_POS     (4U)
+#define QDEC_DEG_CNT_LEN     (4U)
+#define QDEC_DEG_CNT_MSK     (((1U << QDEC_DEG_CNT_LEN) - 1) << QDEC_DEG_CNT_POS)
+#define QDEC_DEG_CNT_UMSK    (~(((1U << QDEC_DEG_CNT_LEN) - 1) << QDEC_DEG_CNT_POS))
+#define QDEC_SPL_PERIOD      QDEC_SPL_PERIOD
+#define QDEC_SPL_PERIOD_POS  (8U)
+#define QDEC_SPL_PERIOD_LEN  (4U)
+#define QDEC_SPL_PERIOD_MSK  (((1U << QDEC_SPL_PERIOD_LEN) - 1) << QDEC_SPL_PERIOD_POS)
+#define QDEC_SPL_PERIOD_UMSK (~(((1U << QDEC_SPL_PERIOD_LEN) - 1) << QDEC_SPL_PERIOD_POS))
+#define QDEC_RPT_PERIOD      QDEC_RPT_PERIOD
+#define QDEC_RPT_PERIOD_POS  (12U)
+#define QDEC_RPT_PERIOD_LEN  (16U)
+#define QDEC_RPT_PERIOD_MSK  (((1U << QDEC_RPT_PERIOD_LEN) - 1) << QDEC_RPT_PERIOD_POS)
+#define QDEC_RPT_PERIOD_UMSK (~(((1U << QDEC_RPT_PERIOD_LEN) - 1) << QDEC_RPT_PERIOD_POS))
+
+/* 0x44 : qdec1_ctrl1 */
+#define QDEC1_CTRL1_OFFSET   (0x44)
+#define QDEC_ACC_MODE        QDEC_ACC_MODE
+#define QDEC_ACC_MODE_POS    (0U)
+#define QDEC_ACC_MODE_LEN    (1U)
+#define QDEC_ACC_MODE_MSK    (((1U << QDEC_ACC_MODE_LEN) - 1) << QDEC_ACC_MODE_POS)
+#define QDEC_ACC_MODE_UMSK   (~(((1U << QDEC_ACC_MODE_LEN) - 1) << QDEC_ACC_MODE_POS))
+#define QDEC_SPL_MODE        QDEC_SPL_MODE
+#define QDEC_SPL_MODE_POS    (1U)
+#define QDEC_SPL_MODE_LEN    (1U)
+#define QDEC_SPL_MODE_MSK    (((1U << QDEC_SPL_MODE_LEN) - 1) << QDEC_SPL_MODE_POS)
+#define QDEC_SPL_MODE_UMSK   (~(((1U << QDEC_SPL_MODE_LEN) - 1) << QDEC_SPL_MODE_POS))
+#define QDEC_RPT_MODE        QDEC_RPT_MODE
+#define QDEC_RPT_MODE_POS    (2U)
+#define QDEC_RPT_MODE_LEN    (1U)
+#define QDEC_RPT_MODE_MSK    (((1U << QDEC_RPT_MODE_LEN) - 1) << QDEC_RPT_MODE_POS)
+#define QDEC_RPT_MODE_UMSK   (~(((1U << QDEC_RPT_MODE_LEN) - 1) << QDEC_RPT_MODE_POS))
+#define QDEC_INPUT_SWAP      QDEC_INPUT_SWAP
+#define QDEC_INPUT_SWAP_POS  (3U)
+#define QDEC_INPUT_SWAP_LEN  (1U)
+#define QDEC_INPUT_SWAP_MSK  (((1U << QDEC_INPUT_SWAP_LEN) - 1) << QDEC_INPUT_SWAP_POS)
+#define QDEC_INPUT_SWAP_UMSK (~(((1U << QDEC_INPUT_SWAP_LEN) - 1) << QDEC_INPUT_SWAP_POS))
+#define QDEC_LED_PERIOD      QDEC_LED_PERIOD
+#define QDEC_LED_PERIOD_POS  (16U)
+#define QDEC_LED_PERIOD_LEN  (9U)
+#define QDEC_LED_PERIOD_MSK  (((1U << QDEC_LED_PERIOD_LEN) - 1) << QDEC_LED_PERIOD_POS)
+#define QDEC_LED_PERIOD_UMSK (~(((1U << QDEC_LED_PERIOD_LEN) - 1) << QDEC_LED_PERIOD_POS))
+
+/* 0x48 : qdec1_value */
+#define QDEC1_VALUE_OFFSET (0x48)
+#define QDEC_ACC1_VAL      QDEC_ACC1_VAL
+#define QDEC_ACC1_VAL_POS  (0U)
+#define QDEC_ACC1_VAL_LEN  (16U)
+#define QDEC_ACC1_VAL_MSK  (((1U << QDEC_ACC1_VAL_LEN) - 1) << QDEC_ACC1_VAL_POS)
+#define QDEC_ACC1_VAL_UMSK (~(((1U << QDEC_ACC1_VAL_LEN) - 1) << QDEC_ACC1_VAL_POS))
+#define QDEC_ACC2_VAL      QDEC_ACC2_VAL
+#define QDEC_ACC2_VAL_POS  (16U)
+#define QDEC_ACC2_VAL_LEN  (4U)
+#define QDEC_ACC2_VAL_MSK  (((1U << QDEC_ACC2_VAL_LEN) - 1) << QDEC_ACC2_VAL_POS)
+#define QDEC_ACC2_VAL_UMSK (~(((1U << QDEC_ACC2_VAL_LEN) - 1) << QDEC_ACC2_VAL_POS))
+#define QDEC_SPL_VAL       QDEC_SPL_VAL
+#define QDEC_SPL_VAL_POS   (28U)
+#define QDEC_SPL_VAL_LEN   (2U)
+#define QDEC_SPL_VAL_MSK   (((1U << QDEC_SPL_VAL_LEN) - 1) << QDEC_SPL_VAL_POS)
+#define QDEC_SPL_VAL_UMSK  (~(((1U << QDEC_SPL_VAL_LEN) - 1) << QDEC_SPL_VAL_POS))
+
+/* 0x50 : qdec1_int_en */
+#define QDEC1_INT_EN_OFFSET   (0x50)
+#define QDEC_RPT_RDY_EN       QDEC_RPT_RDY_EN
+#define QDEC_RPT_RDY_EN_POS   (0U)
+#define QDEC_RPT_RDY_EN_LEN   (1U)
+#define QDEC_RPT_RDY_EN_MSK   (((1U << QDEC_RPT_RDY_EN_LEN) - 1) << QDEC_RPT_RDY_EN_POS)
+#define QDEC_RPT_RDY_EN_UMSK  (~(((1U << QDEC_RPT_RDY_EN_LEN) - 1) << QDEC_RPT_RDY_EN_POS))
+#define QDEC_SPL_RDY_EN       QDEC_SPL_RDY_EN
+#define QDEC_SPL_RDY_EN_POS   (1U)
+#define QDEC_SPL_RDY_EN_LEN   (1U)
+#define QDEC_SPL_RDY_EN_MSK   (((1U << QDEC_SPL_RDY_EN_LEN) - 1) << QDEC_SPL_RDY_EN_POS)
+#define QDEC_SPL_RDY_EN_UMSK  (~(((1U << QDEC_SPL_RDY_EN_LEN) - 1) << QDEC_SPL_RDY_EN_POS))
+#define QDEC_DBL_RDY_EN       QDEC_DBL_RDY_EN
+#define QDEC_DBL_RDY_EN_POS   (2U)
+#define QDEC_DBL_RDY_EN_LEN   (1U)
+#define QDEC_DBL_RDY_EN_MSK   (((1U << QDEC_DBL_RDY_EN_LEN) - 1) << QDEC_DBL_RDY_EN_POS)
+#define QDEC_DBL_RDY_EN_UMSK  (~(((1U << QDEC_DBL_RDY_EN_LEN) - 1) << QDEC_DBL_RDY_EN_POS))
+#define QDEC_OVERFLOW_EN      QDEC_OVERFLOW_EN
+#define QDEC_OVERFLOW_EN_POS  (3U)
+#define QDEC_OVERFLOW_EN_LEN  (1U)
+#define QDEC_OVERFLOW_EN_MSK  (((1U << QDEC_OVERFLOW_EN_LEN) - 1) << QDEC_OVERFLOW_EN_POS)
+#define QDEC_OVERFLOW_EN_UMSK (~(((1U << QDEC_OVERFLOW_EN_LEN) - 1) << QDEC_OVERFLOW_EN_POS))
+
+/* 0x54 : qdec1_int_sts */
+#define QDEC1_INT_STS_OFFSET   (0x54)
+#define QDEC_RPT_RDY_STS       QDEC_RPT_RDY_STS
+#define QDEC_RPT_RDY_STS_POS   (0U)
+#define QDEC_RPT_RDY_STS_LEN   (1U)
+#define QDEC_RPT_RDY_STS_MSK   (((1U << QDEC_RPT_RDY_STS_LEN) - 1) << QDEC_RPT_RDY_STS_POS)
+#define QDEC_RPT_RDY_STS_UMSK  (~(((1U << QDEC_RPT_RDY_STS_LEN) - 1) << QDEC_RPT_RDY_STS_POS))
+#define QDEC_SPL_RDY_STS       QDEC_SPL_RDY_STS
+#define QDEC_SPL_RDY_STS_POS   (1U)
+#define QDEC_SPL_RDY_STS_LEN   (1U)
+#define QDEC_SPL_RDY_STS_MSK   (((1U << QDEC_SPL_RDY_STS_LEN) - 1) << QDEC_SPL_RDY_STS_POS)
+#define QDEC_SPL_RDY_STS_UMSK  (~(((1U << QDEC_SPL_RDY_STS_LEN) - 1) << QDEC_SPL_RDY_STS_POS))
+#define QDEC_DBL_RDY_STS       QDEC_DBL_RDY_STS
+#define QDEC_DBL_RDY_STS_POS   (2U)
+#define QDEC_DBL_RDY_STS_LEN   (1U)
+#define QDEC_DBL_RDY_STS_MSK   (((1U << QDEC_DBL_RDY_STS_LEN) - 1) << QDEC_DBL_RDY_STS_POS)
+#define QDEC_DBL_RDY_STS_UMSK  (~(((1U << QDEC_DBL_RDY_STS_LEN) - 1) << QDEC_DBL_RDY_STS_POS))
+#define QDEC_OVERFLOW_STS      QDEC_OVERFLOW_STS
+#define QDEC_OVERFLOW_STS_POS  (3U)
+#define QDEC_OVERFLOW_STS_LEN  (1U)
+#define QDEC_OVERFLOW_STS_MSK  (((1U << QDEC_OVERFLOW_STS_LEN) - 1) << QDEC_OVERFLOW_STS_POS)
+#define QDEC_OVERFLOW_STS_UMSK (~(((1U << QDEC_OVERFLOW_STS_LEN) - 1) << QDEC_OVERFLOW_STS_POS))
+
+/* 0x58 : qdec1_int_clr */
+#define QDEC1_INT_CLR_OFFSET   (0x58)
+#define QDEC_RPT_RDY_CLR       QDEC_RPT_RDY_CLR
+#define QDEC_RPT_RDY_CLR_POS   (0U)
+#define QDEC_RPT_RDY_CLR_LEN   (1U)
+#define QDEC_RPT_RDY_CLR_MSK   (((1U << QDEC_RPT_RDY_CLR_LEN) - 1) << QDEC_RPT_RDY_CLR_POS)
+#define QDEC_RPT_RDY_CLR_UMSK  (~(((1U << QDEC_RPT_RDY_CLR_LEN) - 1) << QDEC_RPT_RDY_CLR_POS))
+#define QDEC_SPL_RDY_CLR       QDEC_SPL_RDY_CLR
+#define QDEC_SPL_RDY_CLR_POS   (1U)
+#define QDEC_SPL_RDY_CLR_LEN   (1U)
+#define QDEC_SPL_RDY_CLR_MSK   (((1U << QDEC_SPL_RDY_CLR_LEN) - 1) << QDEC_SPL_RDY_CLR_POS)
+#define QDEC_SPL_RDY_CLR_UMSK  (~(((1U << QDEC_SPL_RDY_CLR_LEN) - 1) << QDEC_SPL_RDY_CLR_POS))
+#define QDEC_DBL_RDY_CLR       QDEC_DBL_RDY_CLR
+#define QDEC_DBL_RDY_CLR_POS   (2U)
+#define QDEC_DBL_RDY_CLR_LEN   (1U)
+#define QDEC_DBL_RDY_CLR_MSK   (((1U << QDEC_DBL_RDY_CLR_LEN) - 1) << QDEC_DBL_RDY_CLR_POS)
+#define QDEC_DBL_RDY_CLR_UMSK  (~(((1U << QDEC_DBL_RDY_CLR_LEN) - 1) << QDEC_DBL_RDY_CLR_POS))
+#define QDEC_OVERFLOW_CLR      QDEC_OVERFLOW_CLR
+#define QDEC_OVERFLOW_CLR_POS  (3U)
+#define QDEC_OVERFLOW_CLR_LEN  (1U)
+#define QDEC_OVERFLOW_CLR_MSK  (((1U << QDEC_OVERFLOW_CLR_LEN) - 1) << QDEC_OVERFLOW_CLR_POS)
+#define QDEC_OVERFLOW_CLR_UMSK (~(((1U << QDEC_OVERFLOW_CLR_LEN) - 1) << QDEC_OVERFLOW_CLR_POS))
+
+/* 0x80 : qdec2_ctrl0 */
+#define QDEC2_CTRL0_OFFSET   (0x80)
+#define QDEC_EN              QDEC_EN
+#define QDEC_EN_POS          (0U)
+#define QDEC_EN_LEN          (1U)
+#define QDEC_EN_MSK          (((1U << QDEC_EN_LEN) - 1) << QDEC_EN_POS)
+#define QDEC_EN_UMSK         (~(((1U << QDEC_EN_LEN) - 1) << QDEC_EN_POS))
+#define QDEC_LED_EN          QDEC_LED_EN
+#define QDEC_LED_EN_POS      (1U)
+#define QDEC_LED_EN_LEN      (1U)
+#define QDEC_LED_EN_MSK      (((1U << QDEC_LED_EN_LEN) - 1) << QDEC_LED_EN_POS)
+#define QDEC_LED_EN_UMSK     (~(((1U << QDEC_LED_EN_LEN) - 1) << QDEC_LED_EN_POS))
+#define QDEC_LED_POL         QDEC_LED_POL
+#define QDEC_LED_POL_POS     (2U)
+#define QDEC_LED_POL_LEN     (1U)
+#define QDEC_LED_POL_MSK     (((1U << QDEC_LED_POL_LEN) - 1) << QDEC_LED_POL_POS)
+#define QDEC_LED_POL_UMSK    (~(((1U << QDEC_LED_POL_LEN) - 1) << QDEC_LED_POL_POS))
+#define QDEC_DEG_EN          QDEC_DEG_EN
+#define QDEC_DEG_EN_POS      (3U)
+#define QDEC_DEG_EN_LEN      (1U)
+#define QDEC_DEG_EN_MSK      (((1U << QDEC_DEG_EN_LEN) - 1) << QDEC_DEG_EN_POS)
+#define QDEC_DEG_EN_UMSK     (~(((1U << QDEC_DEG_EN_LEN) - 1) << QDEC_DEG_EN_POS))
+#define QDEC_DEG_CNT         QDEC_DEG_CNT
+#define QDEC_DEG_CNT_POS     (4U)
+#define QDEC_DEG_CNT_LEN     (4U)
+#define QDEC_DEG_CNT_MSK     (((1U << QDEC_DEG_CNT_LEN) - 1) << QDEC_DEG_CNT_POS)
+#define QDEC_DEG_CNT_UMSK    (~(((1U << QDEC_DEG_CNT_LEN) - 1) << QDEC_DEG_CNT_POS))
+#define QDEC_SPL_PERIOD      QDEC_SPL_PERIOD
+#define QDEC_SPL_PERIOD_POS  (8U)
+#define QDEC_SPL_PERIOD_LEN  (4U)
+#define QDEC_SPL_PERIOD_MSK  (((1U << QDEC_SPL_PERIOD_LEN) - 1) << QDEC_SPL_PERIOD_POS)
+#define QDEC_SPL_PERIOD_UMSK (~(((1U << QDEC_SPL_PERIOD_LEN) - 1) << QDEC_SPL_PERIOD_POS))
+#define QDEC_RPT_PERIOD      QDEC_RPT_PERIOD
+#define QDEC_RPT_PERIOD_POS  (12U)
+#define QDEC_RPT_PERIOD_LEN  (16U)
+#define QDEC_RPT_PERIOD_MSK  (((1U << QDEC_RPT_PERIOD_LEN) - 1) << QDEC_RPT_PERIOD_POS)
+#define QDEC_RPT_PERIOD_UMSK (~(((1U << QDEC_RPT_PERIOD_LEN) - 1) << QDEC_RPT_PERIOD_POS))
+
+/* 0x84 : qdec2_ctrl1 */
+#define QDEC2_CTRL1_OFFSET   (0x84)
+#define QDEC_ACC_MODE        QDEC_ACC_MODE
+#define QDEC_ACC_MODE_POS    (0U)
+#define QDEC_ACC_MODE_LEN    (1U)
+#define QDEC_ACC_MODE_MSK    (((1U << QDEC_ACC_MODE_LEN) - 1) << QDEC_ACC_MODE_POS)
+#define QDEC_ACC_MODE_UMSK   (~(((1U << QDEC_ACC_MODE_LEN) - 1) << QDEC_ACC_MODE_POS))
+#define QDEC_SPL_MODE        QDEC_SPL_MODE
+#define QDEC_SPL_MODE_POS    (1U)
+#define QDEC_SPL_MODE_LEN    (1U)
+#define QDEC_SPL_MODE_MSK    (((1U << QDEC_SPL_MODE_LEN) - 1) << QDEC_SPL_MODE_POS)
+#define QDEC_SPL_MODE_UMSK   (~(((1U << QDEC_SPL_MODE_LEN) - 1) << QDEC_SPL_MODE_POS))
+#define QDEC_RPT_MODE        QDEC_RPT_MODE
+#define QDEC_RPT_MODE_POS    (2U)
+#define QDEC_RPT_MODE_LEN    (1U)
+#define QDEC_RPT_MODE_MSK    (((1U << QDEC_RPT_MODE_LEN) - 1) << QDEC_RPT_MODE_POS)
+#define QDEC_RPT_MODE_UMSK   (~(((1U << QDEC_RPT_MODE_LEN) - 1) << QDEC_RPT_MODE_POS))
+#define QDEC_INPUT_SWAP      QDEC_INPUT_SWAP
+#define QDEC_INPUT_SWAP_POS  (3U)
+#define QDEC_INPUT_SWAP_LEN  (1U)
+#define QDEC_INPUT_SWAP_MSK  (((1U << QDEC_INPUT_SWAP_LEN) - 1) << QDEC_INPUT_SWAP_POS)
+#define QDEC_INPUT_SWAP_UMSK (~(((1U << QDEC_INPUT_SWAP_LEN) - 1) << QDEC_INPUT_SWAP_POS))
+#define QDEC_LED_PERIOD      QDEC_LED_PERIOD
+#define QDEC_LED_PERIOD_POS  (16U)
+#define QDEC_LED_PERIOD_LEN  (9U)
+#define QDEC_LED_PERIOD_MSK  (((1U << QDEC_LED_PERIOD_LEN) - 1) << QDEC_LED_PERIOD_POS)
+#define QDEC_LED_PERIOD_UMSK (~(((1U << QDEC_LED_PERIOD_LEN) - 1) << QDEC_LED_PERIOD_POS))
+
+/* 0x88 : qdec2_value */
+#define QDEC2_VALUE_OFFSET (0x88)
+#define QDEC_ACC1_VAL      QDEC_ACC1_VAL
+#define QDEC_ACC1_VAL_POS  (0U)
+#define QDEC_ACC1_VAL_LEN  (16U)
+#define QDEC_ACC1_VAL_MSK  (((1U << QDEC_ACC1_VAL_LEN) - 1) << QDEC_ACC1_VAL_POS)
+#define QDEC_ACC1_VAL_UMSK (~(((1U << QDEC_ACC1_VAL_LEN) - 1) << QDEC_ACC1_VAL_POS))
+#define QDEC_ACC2_VAL      QDEC_ACC2_VAL
+#define QDEC_ACC2_VAL_POS  (16U)
+#define QDEC_ACC2_VAL_LEN  (4U)
+#define QDEC_ACC2_VAL_MSK  (((1U << QDEC_ACC2_VAL_LEN) - 1) << QDEC_ACC2_VAL_POS)
+#define QDEC_ACC2_VAL_UMSK (~(((1U << QDEC_ACC2_VAL_LEN) - 1) << QDEC_ACC2_VAL_POS))
+#define QDEC_SPL_VAL       QDEC_SPL_VAL
+#define QDEC_SPL_VAL_POS   (28U)
+#define QDEC_SPL_VAL_LEN   (2U)
+#define QDEC_SPL_VAL_MSK   (((1U << QDEC_SPL_VAL_LEN) - 1) << QDEC_SPL_VAL_POS)
+#define QDEC_SPL_VAL_UMSK  (~(((1U << QDEC_SPL_VAL_LEN) - 1) << QDEC_SPL_VAL_POS))
+
+/* 0x90 : qdec2_int_en */
+#define QDEC2_INT_EN_OFFSET   (0x90)
+#define QDEC_RPT_RDY_EN       QDEC_RPT_RDY_EN
+#define QDEC_RPT_RDY_EN_POS   (0U)
+#define QDEC_RPT_RDY_EN_LEN   (1U)
+#define QDEC_RPT_RDY_EN_MSK   (((1U << QDEC_RPT_RDY_EN_LEN) - 1) << QDEC_RPT_RDY_EN_POS)
+#define QDEC_RPT_RDY_EN_UMSK  (~(((1U << QDEC_RPT_RDY_EN_LEN) - 1) << QDEC_RPT_RDY_EN_POS))
+#define QDEC_SPL_RDY_EN       QDEC_SPL_RDY_EN
+#define QDEC_SPL_RDY_EN_POS   (1U)
+#define QDEC_SPL_RDY_EN_LEN   (1U)
+#define QDEC_SPL_RDY_EN_MSK   (((1U << QDEC_SPL_RDY_EN_LEN) - 1) << QDEC_SPL_RDY_EN_POS)
+#define QDEC_SPL_RDY_EN_UMSK  (~(((1U << QDEC_SPL_RDY_EN_LEN) - 1) << QDEC_SPL_RDY_EN_POS))
+#define QDEC_DBL_RDY_EN       QDEC_DBL_RDY_EN
+#define QDEC_DBL_RDY_EN_POS   (2U)
+#define QDEC_DBL_RDY_EN_LEN   (1U)
+#define QDEC_DBL_RDY_EN_MSK   (((1U << QDEC_DBL_RDY_EN_LEN) - 1) << QDEC_DBL_RDY_EN_POS)
+#define QDEC_DBL_RDY_EN_UMSK  (~(((1U << QDEC_DBL_RDY_EN_LEN) - 1) << QDEC_DBL_RDY_EN_POS))
+#define QDEC_OVERFLOW_EN      QDEC_OVERFLOW_EN
+#define QDEC_OVERFLOW_EN_POS  (3U)
+#define QDEC_OVERFLOW_EN_LEN  (1U)
+#define QDEC_OVERFLOW_EN_MSK  (((1U << QDEC_OVERFLOW_EN_LEN) - 1) << QDEC_OVERFLOW_EN_POS)
+#define QDEC_OVERFLOW_EN_UMSK (~(((1U << QDEC_OVERFLOW_EN_LEN) - 1) << QDEC_OVERFLOW_EN_POS))
+
+/* 0x94 : qdec2_int_sts */
+#define QDEC2_INT_STS_OFFSET   (0x94)
+#define QDEC_RPT_RDY_STS       QDEC_RPT_RDY_STS
+#define QDEC_RPT_RDY_STS_POS   (0U)
+#define QDEC_RPT_RDY_STS_LEN   (1U)
+#define QDEC_RPT_RDY_STS_MSK   (((1U << QDEC_RPT_RDY_STS_LEN) - 1) << QDEC_RPT_RDY_STS_POS)
+#define QDEC_RPT_RDY_STS_UMSK  (~(((1U << QDEC_RPT_RDY_STS_LEN) - 1) << QDEC_RPT_RDY_STS_POS))
+#define QDEC_SPL_RDY_STS       QDEC_SPL_RDY_STS
+#define QDEC_SPL_RDY_STS_POS   (1U)
+#define QDEC_SPL_RDY_STS_LEN   (1U)
+#define QDEC_SPL_RDY_STS_MSK   (((1U << QDEC_SPL_RDY_STS_LEN) - 1) << QDEC_SPL_RDY_STS_POS)
+#define QDEC_SPL_RDY_STS_UMSK  (~(((1U << QDEC_SPL_RDY_STS_LEN) - 1) << QDEC_SPL_RDY_STS_POS))
+#define QDEC_DBL_RDY_STS       QDEC_DBL_RDY_STS
+#define QDEC_DBL_RDY_STS_POS   (2U)
+#define QDEC_DBL_RDY_STS_LEN   (1U)
+#define QDEC_DBL_RDY_STS_MSK   (((1U << QDEC_DBL_RDY_STS_LEN) - 1) << QDEC_DBL_RDY_STS_POS)
+#define QDEC_DBL_RDY_STS_UMSK  (~(((1U << QDEC_DBL_RDY_STS_LEN) - 1) << QDEC_DBL_RDY_STS_POS))
+#define QDEC_OVERFLOW_STS      QDEC_OVERFLOW_STS
+#define QDEC_OVERFLOW_STS_POS  (3U)
+#define QDEC_OVERFLOW_STS_LEN  (1U)
+#define QDEC_OVERFLOW_STS_MSK  (((1U << QDEC_OVERFLOW_STS_LEN) - 1) << QDEC_OVERFLOW_STS_POS)
+#define QDEC_OVERFLOW_STS_UMSK (~(((1U << QDEC_OVERFLOW_STS_LEN) - 1) << QDEC_OVERFLOW_STS_POS))
+
+/* 0x98 : qdec2_int_clr */
+#define QDEC2_INT_CLR_OFFSET   (0x98)
+#define QDEC_RPT_RDY_CLR       QDEC_RPT_RDY_CLR
+#define QDEC_RPT_RDY_CLR_POS   (0U)
+#define QDEC_RPT_RDY_CLR_LEN   (1U)
+#define QDEC_RPT_RDY_CLR_MSK   (((1U << QDEC_RPT_RDY_CLR_LEN) - 1) << QDEC_RPT_RDY_CLR_POS)
+#define QDEC_RPT_RDY_CLR_UMSK  (~(((1U << QDEC_RPT_RDY_CLR_LEN) - 1) << QDEC_RPT_RDY_CLR_POS))
+#define QDEC_SPL_RDY_CLR       QDEC_SPL_RDY_CLR
+#define QDEC_SPL_RDY_CLR_POS   (1U)
+#define QDEC_SPL_RDY_CLR_LEN   (1U)
+#define QDEC_SPL_RDY_CLR_MSK   (((1U << QDEC_SPL_RDY_CLR_LEN) - 1) << QDEC_SPL_RDY_CLR_POS)
+#define QDEC_SPL_RDY_CLR_UMSK  (~(((1U << QDEC_SPL_RDY_CLR_LEN) - 1) << QDEC_SPL_RDY_CLR_POS))
+#define QDEC_DBL_RDY_CLR       QDEC_DBL_RDY_CLR
+#define QDEC_DBL_RDY_CLR_POS   (2U)
+#define QDEC_DBL_RDY_CLR_LEN   (1U)
+#define QDEC_DBL_RDY_CLR_MSK   (((1U << QDEC_DBL_RDY_CLR_LEN) - 1) << QDEC_DBL_RDY_CLR_POS)
+#define QDEC_DBL_RDY_CLR_UMSK  (~(((1U << QDEC_DBL_RDY_CLR_LEN) - 1) << QDEC_DBL_RDY_CLR_POS))
+#define QDEC_OVERFLOW_CLR      QDEC_OVERFLOW_CLR
+#define QDEC_OVERFLOW_CLR_POS  (3U)
+#define QDEC_OVERFLOW_CLR_LEN  (1U)
+#define QDEC_OVERFLOW_CLR_MSK  (((1U << QDEC_OVERFLOW_CLR_LEN) - 1) << QDEC_OVERFLOW_CLR_POS)
+#define QDEC_OVERFLOW_CLR_UMSK (~(((1U << QDEC_OVERFLOW_CLR_LEN) - 1) << QDEC_OVERFLOW_CLR_POS))
+
+struct qdec_reg {
+    /* 0x0 : qdec0_ctrl0 */
+    union {
+        struct
+        {
+            uint32_t qdec_en        : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t led_en         : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t led_pol        : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t deg_en         : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t deg_cnt        : 4;  /* [ 7: 4],        r/w,        0x0 */
+            uint32_t spl_period     : 4;  /* [11: 8],        r/w,        0x2 */
+            uint32_t rpt_period     : 16; /* [27:12],        r/w,        0xa */
+            uint32_t reserved_28_31 : 4;  /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } qdec0_ctrl0;
+
+    /* 0x4 : qdec0_ctrl1 */
+    union {
+        struct
+        {
+            uint32_t acc_mode       : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t spl_mode       : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t rpt_mode       : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t input_swap     : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t reserved_4_15  : 12; /* [15: 4],       rsvd,        0x0 */
+            uint32_t led_period     : 9;  /* [24:16],        r/w,        0x0 */
+            uint32_t reserved_25_31 : 7;  /* [31:25],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } qdec0_ctrl1;
+
+    /* 0x8 : qdec0_value */
+    union {
+        struct
+        {
+            uint32_t acc1_val       : 16; /* [15: 0],          r,        0x0 */
+            uint32_t acc2_val       : 4;  /* [19:16],          r,        0x0 */
+            uint32_t reserved_20_27 : 8;  /* [27:20],       rsvd,        0x0 */
+            uint32_t spl_val        : 2;  /* [29:28],          r,        0x0 */
+            uint32_t reserved_30_31 : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } qdec0_value;
+
+    /* 0xc  reserved */
+    uint8_t RESERVED0xc[4];
+
+    /* 0x10 : qdec0_int_en */
+    union {
+        struct
+        {
+            uint32_t rpt_rdy_en    : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t spl_rdy_en    : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t dbl_rdy_en    : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t overflow_en   : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } qdec0_int_en;
+
+    /* 0x14 : qdec0_int_sts */
+    union {
+        struct
+        {
+            uint32_t rpt_rdy_sts   : 1;  /* [    0],          r,        0x0 */
+            uint32_t spl_rdy_sts   : 1;  /* [    1],          r,        0x0 */
+            uint32_t dbl_rdy_sts   : 1;  /* [    2],          r,        0x0 */
+            uint32_t overflow_sts  : 1;  /* [    3],          r,        0x0 */
+            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } qdec0_int_sts;
+
+    /* 0x18 : qdec0_int_clr */
+    union {
+        struct
+        {
+            uint32_t rpt_rdy_clr   : 1;  /* [    0],        w1c,        0x0 */
+            uint32_t spl_rdy_clr   : 1;  /* [    1],        w1c,        0x0 */
+            uint32_t dbl_rdy_clr   : 1;  /* [    2],        w1c,        0x0 */
+            uint32_t overflow_clr  : 1;  /* [    3],        w1c,        0x0 */
+            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } qdec0_int_clr;
+
+    /* 0x1c  reserved */
+    uint8_t RESERVED0x1c[36];
+
+    /* 0x40 : qdec1_ctrl0 */
+    union {
+        struct
+        {
+            uint32_t qdec_en        : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t led_en         : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t led_pol        : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t deg_en         : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t deg_cnt        : 4;  /* [ 7: 4],        r/w,        0x0 */
+            uint32_t spl_period     : 4;  /* [11: 8],        r/w,        0x2 */
+            uint32_t rpt_period     : 16; /* [27:12],        r/w,        0xa */
+            uint32_t reserved_28_31 : 4;  /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } qdec1_ctrl0;
+
+    /* 0x44 : qdec1_ctrl1 */
+    union {
+        struct
+        {
+            uint32_t acc_mode       : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t spl_mode       : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t rpt_mode       : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t input_swap     : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t reserved_4_15  : 12; /* [15: 4],       rsvd,        0x0 */
+            uint32_t led_period     : 9;  /* [24:16],        r/w,        0x0 */
+            uint32_t reserved_25_31 : 7;  /* [31:25],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } qdec1_ctrl1;
+
+    /* 0x48 : qdec1_value */
+    union {
+        struct
+        {
+            uint32_t acc1_val       : 16; /* [15: 0],          r,        0x0 */
+            uint32_t acc2_val       : 4;  /* [19:16],          r,        0x0 */
+            uint32_t reserved_20_27 : 8;  /* [27:20],       rsvd,        0x0 */
+            uint32_t spl_val        : 2;  /* [29:28],          r,        0x0 */
+            uint32_t reserved_30_31 : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } qdec1_value;
+
+    /* 0x4c  reserved */
+    uint8_t RESERVED0x4c[4];
+
+    /* 0x50 : qdec1_int_en */
+    union {
+        struct
+        {
+            uint32_t rpt_rdy_en    : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t spl_rdy_en    : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t dbl_rdy_en    : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t overflow_en   : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } qdec1_int_en;
+
+    /* 0x54 : qdec1_int_sts */
+    union {
+        struct
+        {
+            uint32_t rpt_rdy_sts   : 1;  /* [    0],          r,        0x0 */
+            uint32_t spl_rdy_sts   : 1;  /* [    1],          r,        0x0 */
+            uint32_t dbl_rdy_sts   : 1;  /* [    2],          r,        0x0 */
+            uint32_t overflow_sts  : 1;  /* [    3],          r,        0x0 */
+            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } qdec1_int_sts;
+
+    /* 0x58 : qdec1_int_clr */
+    union {
+        struct
+        {
+            uint32_t rpt_rdy_clr   : 1;  /* [    0],        w1c,        0x0 */
+            uint32_t spl_rdy_clr   : 1;  /* [    1],        w1c,        0x0 */
+            uint32_t dbl_rdy_clr   : 1;  /* [    2],        w1c,        0x0 */
+            uint32_t overflow_clr  : 1;  /* [    3],        w1c,        0x0 */
+            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } qdec1_int_clr;
+
+    /* 0x5c  reserved */
+    uint8_t RESERVED0x5c[36];
+
+    /* 0x80 : qdec2_ctrl0 */
+    union {
+        struct
+        {
+            uint32_t qdec_en        : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t led_en         : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t led_pol        : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t deg_en         : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t deg_cnt        : 4;  /* [ 7: 4],        r/w,        0x0 */
+            uint32_t spl_period     : 4;  /* [11: 8],        r/w,        0x2 */
+            uint32_t rpt_period     : 16; /* [27:12],        r/w,        0xa */
+            uint32_t reserved_28_31 : 4;  /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } qdec2_ctrl0;
+
+    /* 0x84 : qdec2_ctrl1 */
+    union {
+        struct
+        {
+            uint32_t acc_mode       : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t spl_mode       : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t rpt_mode       : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t input_swap     : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t reserved_4_15  : 12; /* [15: 4],       rsvd,        0x0 */
+            uint32_t led_period     : 9;  /* [24:16],        r/w,        0x0 */
+            uint32_t reserved_25_31 : 7;  /* [31:25],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } qdec2_ctrl1;
+
+    /* 0x88 : qdec2_value */
+    union {
+        struct
+        {
+            uint32_t acc1_val       : 16; /* [15: 0],          r,        0x0 */
+            uint32_t acc2_val       : 4;  /* [19:16],          r,        0x0 */
+            uint32_t reserved_20_27 : 8;  /* [27:20],       rsvd,        0x0 */
+            uint32_t spl_val        : 2;  /* [29:28],          r,        0x0 */
+            uint32_t reserved_30_31 : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } qdec2_value;
+
+    /* 0x8c  reserved */
+    uint8_t RESERVED0x8c[4];
+
+    /* 0x90 : qdec2_int_en */
+    union {
+        struct
+        {
+            uint32_t rpt_rdy_en    : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t spl_rdy_en    : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t dbl_rdy_en    : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t overflow_en   : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } qdec2_int_en;
+
+    /* 0x94 : qdec2_int_sts */
+    union {
+        struct
+        {
+            uint32_t rpt_rdy_sts   : 1;  /* [    0],          r,        0x0 */
+            uint32_t spl_rdy_sts   : 1;  /* [    1],          r,        0x0 */
+            uint32_t dbl_rdy_sts   : 1;  /* [    2],          r,        0x0 */
+            uint32_t overflow_sts  : 1;  /* [    3],          r,        0x0 */
+            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } qdec2_int_sts;
+
+    /* 0x98 : qdec2_int_clr */
+    union {
+        struct
+        {
+            uint32_t rpt_rdy_clr   : 1;  /* [    0],        w1c,        0x0 */
+            uint32_t spl_rdy_clr   : 1;  /* [    1],        w1c,        0x0 */
+            uint32_t dbl_rdy_clr   : 1;  /* [    2],        w1c,        0x0 */
+            uint32_t overflow_clr  : 1;  /* [    3],        w1c,        0x0 */
+            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } qdec2_int_clr;
+};
+
+typedef volatile struct qdec_reg qdec_reg_t;
+
+#endif /* __QDEC_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/sec_dbg_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/sec_dbg_reg.h
new file mode 100644
index 00000000..76e5d23a
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/sec_dbg_reg.h
@@ -0,0 +1,217 @@
+/**
+  ******************************************************************************
+  * @file    sec_dbg_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __SEC_DBG_REG_H__
+#define __SEC_DBG_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : sd_chip_id_low */
+#define SEC_DBG_SD_CHIP_ID_LOW_OFFSET (0x0)
+#define SEC_DBG_SD_CHIP_ID_LOW        SEC_DBG_SD_CHIP_ID_LOW
+#define SEC_DBG_SD_CHIP_ID_LOW_POS    (0U)
+#define SEC_DBG_SD_CHIP_ID_LOW_LEN    (32U)
+#define SEC_DBG_SD_CHIP_ID_LOW_MSK    (((1U << SEC_DBG_SD_CHIP_ID_LOW_LEN) - 1) << SEC_DBG_SD_CHIP_ID_LOW_POS)
+#define SEC_DBG_SD_CHIP_ID_LOW_UMSK   (~(((1U << SEC_DBG_SD_CHIP_ID_LOW_LEN) - 1) << SEC_DBG_SD_CHIP_ID_LOW_POS))
+
+/* 0x4 : sd_chip_id_high */
+#define SEC_DBG_SD_CHIP_ID_HIGH_OFFSET (0x4)
+#define SEC_DBG_SD_CHIP_ID_HIGH        SEC_DBG_SD_CHIP_ID_HIGH
+#define SEC_DBG_SD_CHIP_ID_HIGH_POS    (0U)
+#define SEC_DBG_SD_CHIP_ID_HIGH_LEN    (32U)
+#define SEC_DBG_SD_CHIP_ID_HIGH_MSK    (((1U << SEC_DBG_SD_CHIP_ID_HIGH_LEN) - 1) << SEC_DBG_SD_CHIP_ID_HIGH_POS)
+#define SEC_DBG_SD_CHIP_ID_HIGH_UMSK   (~(((1U << SEC_DBG_SD_CHIP_ID_HIGH_LEN) - 1) << SEC_DBG_SD_CHIP_ID_HIGH_POS))
+
+/* 0x8 : sd_wifi_mac_low */
+#define SEC_DBG_SD_WIFI_MAC_LOW_OFFSET (0x8)
+#define SEC_DBG_SD_WIFI_MAC_LOW        SEC_DBG_SD_WIFI_MAC_LOW
+#define SEC_DBG_SD_WIFI_MAC_LOW_POS    (0U)
+#define SEC_DBG_SD_WIFI_MAC_LOW_LEN    (32U)
+#define SEC_DBG_SD_WIFI_MAC_LOW_MSK    (((1U << SEC_DBG_SD_WIFI_MAC_LOW_LEN) - 1) << SEC_DBG_SD_WIFI_MAC_LOW_POS)
+#define SEC_DBG_SD_WIFI_MAC_LOW_UMSK   (~(((1U << SEC_DBG_SD_WIFI_MAC_LOW_LEN) - 1) << SEC_DBG_SD_WIFI_MAC_LOW_POS))
+
+/* 0xC : sd_wifi_mac_high */
+#define SEC_DBG_SD_WIFI_MAC_HIGH_OFFSET (0xC)
+#define SEC_DBG_SD_WIFI_MAC_HIGH        SEC_DBG_SD_WIFI_MAC_HIGH
+#define SEC_DBG_SD_WIFI_MAC_HIGH_POS    (0U)
+#define SEC_DBG_SD_WIFI_MAC_HIGH_LEN    (32U)
+#define SEC_DBG_SD_WIFI_MAC_HIGH_MSK    (((1U << SEC_DBG_SD_WIFI_MAC_HIGH_LEN) - 1) << SEC_DBG_SD_WIFI_MAC_HIGH_POS)
+#define SEC_DBG_SD_WIFI_MAC_HIGH_UMSK   (~(((1U << SEC_DBG_SD_WIFI_MAC_HIGH_LEN) - 1) << SEC_DBG_SD_WIFI_MAC_HIGH_POS))
+
+/* 0x10 : sd_dbg_pwd_low */
+#define SEC_DBG_SD_DBG_PWD_LOW_OFFSET (0x10)
+#define SEC_DBG_SD_DBG_PWD_LOW        SEC_DBG_SD_DBG_PWD_LOW
+#define SEC_DBG_SD_DBG_PWD_LOW_POS    (0U)
+#define SEC_DBG_SD_DBG_PWD_LOW_LEN    (32U)
+#define SEC_DBG_SD_DBG_PWD_LOW_MSK    (((1U << SEC_DBG_SD_DBG_PWD_LOW_LEN) - 1) << SEC_DBG_SD_DBG_PWD_LOW_POS)
+#define SEC_DBG_SD_DBG_PWD_LOW_UMSK   (~(((1U << SEC_DBG_SD_DBG_PWD_LOW_LEN) - 1) << SEC_DBG_SD_DBG_PWD_LOW_POS))
+
+/* 0x14 : sd_dbg_pwd_high */
+#define SEC_DBG_SD_DBG_PWD_HIGH_OFFSET (0x14)
+#define SEC_DBG_SD_DBG_PWD_HIGH        SEC_DBG_SD_DBG_PWD_HIGH
+#define SEC_DBG_SD_DBG_PWD_HIGH_POS    (0U)
+#define SEC_DBG_SD_DBG_PWD_HIGH_LEN    (32U)
+#define SEC_DBG_SD_DBG_PWD_HIGH_MSK    (((1U << SEC_DBG_SD_DBG_PWD_HIGH_LEN) - 1) << SEC_DBG_SD_DBG_PWD_HIGH_POS)
+#define SEC_DBG_SD_DBG_PWD_HIGH_UMSK   (~(((1U << SEC_DBG_SD_DBG_PWD_HIGH_LEN) - 1) << SEC_DBG_SD_DBG_PWD_HIGH_POS))
+
+/* 0x18 : sd_status */
+#define SEC_DBG_SD_STATUS_OFFSET        (0x18)
+#define SEC_DBG_SD_DBG_PWD_BUSY         SEC_DBG_SD_DBG_PWD_BUSY
+#define SEC_DBG_SD_DBG_PWD_BUSY_POS     (0U)
+#define SEC_DBG_SD_DBG_PWD_BUSY_LEN     (1U)
+#define SEC_DBG_SD_DBG_PWD_BUSY_MSK     (((1U << SEC_DBG_SD_DBG_PWD_BUSY_LEN) - 1) << SEC_DBG_SD_DBG_PWD_BUSY_POS)
+#define SEC_DBG_SD_DBG_PWD_BUSY_UMSK    (~(((1U << SEC_DBG_SD_DBG_PWD_BUSY_LEN) - 1) << SEC_DBG_SD_DBG_PWD_BUSY_POS))
+#define SEC_DBG_SD_DBG_PWD_TRIG         SEC_DBG_SD_DBG_PWD_TRIG
+#define SEC_DBG_SD_DBG_PWD_TRIG_POS     (1U)
+#define SEC_DBG_SD_DBG_PWD_TRIG_LEN     (1U)
+#define SEC_DBG_SD_DBG_PWD_TRIG_MSK     (((1U << SEC_DBG_SD_DBG_PWD_TRIG_LEN) - 1) << SEC_DBG_SD_DBG_PWD_TRIG_POS)
+#define SEC_DBG_SD_DBG_PWD_TRIG_UMSK    (~(((1U << SEC_DBG_SD_DBG_PWD_TRIG_LEN) - 1) << SEC_DBG_SD_DBG_PWD_TRIG_POS))
+#define SEC_DBG_SD_DBG_CCI_READ_EN      SEC_DBG_SD_DBG_CCI_READ_EN
+#define SEC_DBG_SD_DBG_CCI_READ_EN_POS  (2U)
+#define SEC_DBG_SD_DBG_CCI_READ_EN_LEN  (1U)
+#define SEC_DBG_SD_DBG_CCI_READ_EN_MSK  (((1U << SEC_DBG_SD_DBG_CCI_READ_EN_LEN) - 1) << SEC_DBG_SD_DBG_CCI_READ_EN_POS)
+#define SEC_DBG_SD_DBG_CCI_READ_EN_UMSK (~(((1U << SEC_DBG_SD_DBG_CCI_READ_EN_LEN) - 1) << SEC_DBG_SD_DBG_CCI_READ_EN_POS))
+#define SEC_DBG_SD_DBG_CCI_CLK_SEL      SEC_DBG_SD_DBG_CCI_CLK_SEL
+#define SEC_DBG_SD_DBG_CCI_CLK_SEL_POS  (3U)
+#define SEC_DBG_SD_DBG_CCI_CLK_SEL_LEN  (1U)
+#define SEC_DBG_SD_DBG_CCI_CLK_SEL_MSK  (((1U << SEC_DBG_SD_DBG_CCI_CLK_SEL_LEN) - 1) << SEC_DBG_SD_DBG_CCI_CLK_SEL_POS)
+#define SEC_DBG_SD_DBG_CCI_CLK_SEL_UMSK (~(((1U << SEC_DBG_SD_DBG_CCI_CLK_SEL_LEN) - 1) << SEC_DBG_SD_DBG_CCI_CLK_SEL_POS))
+#define SEC_DBG_SD_DBG_PWD_CNT          SEC_DBG_SD_DBG_PWD_CNT
+#define SEC_DBG_SD_DBG_PWD_CNT_POS      (4U)
+#define SEC_DBG_SD_DBG_PWD_CNT_LEN      (20U)
+#define SEC_DBG_SD_DBG_PWD_CNT_MSK      (((1U << SEC_DBG_SD_DBG_PWD_CNT_LEN) - 1) << SEC_DBG_SD_DBG_PWD_CNT_POS)
+#define SEC_DBG_SD_DBG_PWD_CNT_UMSK     (~(((1U << SEC_DBG_SD_DBG_PWD_CNT_LEN) - 1) << SEC_DBG_SD_DBG_PWD_CNT_POS))
+#define SEC_DBG_SD_DBG_MODE             SEC_DBG_SD_DBG_MODE
+#define SEC_DBG_SD_DBG_MODE_POS         (24U)
+#define SEC_DBG_SD_DBG_MODE_LEN         (4U)
+#define SEC_DBG_SD_DBG_MODE_MSK         (((1U << SEC_DBG_SD_DBG_MODE_LEN) - 1) << SEC_DBG_SD_DBG_MODE_POS)
+#define SEC_DBG_SD_DBG_MODE_UMSK        (~(((1U << SEC_DBG_SD_DBG_MODE_LEN) - 1) << SEC_DBG_SD_DBG_MODE_POS))
+#define SEC_DBG_SD_DBG_ENA              SEC_DBG_SD_DBG_ENA
+#define SEC_DBG_SD_DBG_ENA_POS          (28U)
+#define SEC_DBG_SD_DBG_ENA_LEN          (4U)
+#define SEC_DBG_SD_DBG_ENA_MSK          (((1U << SEC_DBG_SD_DBG_ENA_LEN) - 1) << SEC_DBG_SD_DBG_ENA_POS)
+#define SEC_DBG_SD_DBG_ENA_UMSK         (~(((1U << SEC_DBG_SD_DBG_ENA_LEN) - 1) << SEC_DBG_SD_DBG_ENA_POS))
+
+/* 0x1C : sd_dbg_reserved */
+#define SEC_DBG_SD_DBG_RESERVED_OFFSET (0x1C)
+#define SEC_DBG_SD_DBG_RESERVED        SEC_DBG_SD_DBG_RESERVED
+#define SEC_DBG_SD_DBG_RESERVED_POS    (0U)
+#define SEC_DBG_SD_DBG_RESERVED_LEN    (32U)
+#define SEC_DBG_SD_DBG_RESERVED_MSK    (((1U << SEC_DBG_SD_DBG_RESERVED_LEN) - 1) << SEC_DBG_SD_DBG_RESERVED_POS)
+#define SEC_DBG_SD_DBG_RESERVED_UMSK   (~(((1U << SEC_DBG_SD_DBG_RESERVED_LEN) - 1) << SEC_DBG_SD_DBG_RESERVED_POS))
+
+struct sec_dbg_reg {
+    /* 0x0 : sd_chip_id_low */
+    union {
+        struct
+        {
+            uint32_t sd_chip_id_low : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sd_chip_id_low;
+
+    /* 0x4 : sd_chip_id_high */
+    union {
+        struct
+        {
+            uint32_t sd_chip_id_high : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sd_chip_id_high;
+
+    /* 0x8 : sd_wifi_mac_low */
+    union {
+        struct
+        {
+            uint32_t sd_wifi_mac_low : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sd_wifi_mac_low;
+
+    /* 0xC : sd_wifi_mac_high */
+    union {
+        struct
+        {
+            uint32_t sd_wifi_mac_high : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sd_wifi_mac_high;
+
+    /* 0x10 : sd_dbg_pwd_low */
+    union {
+        struct
+        {
+            uint32_t sd_dbg_pwd_low : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sd_dbg_pwd_low;
+
+    /* 0x14 : sd_dbg_pwd_high */
+    union {
+        struct
+        {
+            uint32_t sd_dbg_pwd_high : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sd_dbg_pwd_high;
+
+    /* 0x18 : sd_status */
+    union {
+        struct
+        {
+            uint32_t sd_dbg_pwd_busy    : 1;  /* [    0],          r,        0x0 */
+            uint32_t sd_dbg_pwd_trig    : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t sd_dbg_cci_read_en : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t sd_dbg_cci_clk_sel : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t sd_dbg_pwd_cnt     : 20; /* [23: 4],          r,        0x0 */
+            uint32_t sd_dbg_mode        : 4;  /* [27:24],          r,        0x0 */
+            uint32_t sd_dbg_ena         : 4;  /* [31:28],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sd_status;
+
+    /* 0x1C : sd_dbg_reserved */
+    union {
+        struct
+        {
+            uint32_t sd_dbg_reserved : 32; /* [31: 0],        r/w,     0xffff */
+        } BF;
+        uint32_t WORD;
+    } sd_dbg_reserved;
+};
+
+typedef volatile struct sec_dbg_reg sec_dbg_reg_t;
+
+#endif /* __SEC_DBG_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/sec_eng_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/sec_eng_reg.h
new file mode 100644
index 00000000..5f6515af
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/sec_eng_reg.h
@@ -0,0 +1,3529 @@
+/**
+  ******************************************************************************
+  * @file    sec_eng_reg.h
+  * @version V1.2
+  * @date    2020-04-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __SEC_ENG_REG_H__
+#define __SEC_ENG_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : se_sha_0_ctrl */
+#define SEC_ENG_SE_SHA_0_CTRL_OFFSET     (0x0)
+#define SEC_ENG_SE_SHA_0_BUSY            SEC_ENG_SE_SHA_0_BUSY
+#define SEC_ENG_SE_SHA_0_BUSY_POS        (0U)
+#define SEC_ENG_SE_SHA_0_BUSY_LEN        (1U)
+#define SEC_ENG_SE_SHA_0_BUSY_MSK        (((1U << SEC_ENG_SE_SHA_0_BUSY_LEN) - 1) << SEC_ENG_SE_SHA_0_BUSY_POS)
+#define SEC_ENG_SE_SHA_0_BUSY_UMSK       (~(((1U << SEC_ENG_SE_SHA_0_BUSY_LEN) - 1) << SEC_ENG_SE_SHA_0_BUSY_POS))
+#define SEC_ENG_SE_SHA_0_TRIG_1T         SEC_ENG_SE_SHA_0_TRIG_1T
+#define SEC_ENG_SE_SHA_0_TRIG_1T_POS     (1U)
+#define SEC_ENG_SE_SHA_0_TRIG_1T_LEN     (1U)
+#define SEC_ENG_SE_SHA_0_TRIG_1T_MSK     (((1U << SEC_ENG_SE_SHA_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_TRIG_1T_POS)
+#define SEC_ENG_SE_SHA_0_TRIG_1T_UMSK    (~(((1U << SEC_ENG_SE_SHA_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_TRIG_1T_POS))
+#define SEC_ENG_SE_SHA_0_MODE            SEC_ENG_SE_SHA_0_MODE
+#define SEC_ENG_SE_SHA_0_MODE_POS        (2U)
+#define SEC_ENG_SE_SHA_0_MODE_LEN        (3U)
+#define SEC_ENG_SE_SHA_0_MODE_MSK        (((1U << SEC_ENG_SE_SHA_0_MODE_LEN) - 1) << SEC_ENG_SE_SHA_0_MODE_POS)
+#define SEC_ENG_SE_SHA_0_MODE_UMSK       (~(((1U << SEC_ENG_SE_SHA_0_MODE_LEN) - 1) << SEC_ENG_SE_SHA_0_MODE_POS))
+#define SEC_ENG_SE_SHA_0_EN              SEC_ENG_SE_SHA_0_EN
+#define SEC_ENG_SE_SHA_0_EN_POS          (5U)
+#define SEC_ENG_SE_SHA_0_EN_LEN          (1U)
+#define SEC_ENG_SE_SHA_0_EN_MSK          (((1U << SEC_ENG_SE_SHA_0_EN_LEN) - 1) << SEC_ENG_SE_SHA_0_EN_POS)
+#define SEC_ENG_SE_SHA_0_EN_UMSK         (~(((1U << SEC_ENG_SE_SHA_0_EN_LEN) - 1) << SEC_ENG_SE_SHA_0_EN_POS))
+#define SEC_ENG_SE_SHA_0_HASH_SEL        SEC_ENG_SE_SHA_0_HASH_SEL
+#define SEC_ENG_SE_SHA_0_HASH_SEL_POS    (6U)
+#define SEC_ENG_SE_SHA_0_HASH_SEL_LEN    (1U)
+#define SEC_ENG_SE_SHA_0_HASH_SEL_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_SEL_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_SEL_POS)
+#define SEC_ENG_SE_SHA_0_HASH_SEL_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_SEL_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_SEL_POS))
+#define SEC_ENG_SE_SHA_0_INT             SEC_ENG_SE_SHA_0_INT
+#define SEC_ENG_SE_SHA_0_INT_POS         (8U)
+#define SEC_ENG_SE_SHA_0_INT_LEN         (1U)
+#define SEC_ENG_SE_SHA_0_INT_MSK         (((1U << SEC_ENG_SE_SHA_0_INT_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_POS)
+#define SEC_ENG_SE_SHA_0_INT_UMSK        (~(((1U << SEC_ENG_SE_SHA_0_INT_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_POS))
+#define SEC_ENG_SE_SHA_0_INT_CLR_1T      SEC_ENG_SE_SHA_0_INT_CLR_1T
+#define SEC_ENG_SE_SHA_0_INT_CLR_1T_POS  (9U)
+#define SEC_ENG_SE_SHA_0_INT_CLR_1T_LEN  (1U)
+#define SEC_ENG_SE_SHA_0_INT_CLR_1T_MSK  (((1U << SEC_ENG_SE_SHA_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_CLR_1T_POS)
+#define SEC_ENG_SE_SHA_0_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_CLR_1T_POS))
+#define SEC_ENG_SE_SHA_0_INT_SET_1T      SEC_ENG_SE_SHA_0_INT_SET_1T
+#define SEC_ENG_SE_SHA_0_INT_SET_1T_POS  (10U)
+#define SEC_ENG_SE_SHA_0_INT_SET_1T_LEN  (1U)
+#define SEC_ENG_SE_SHA_0_INT_SET_1T_MSK  (((1U << SEC_ENG_SE_SHA_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_SET_1T_POS)
+#define SEC_ENG_SE_SHA_0_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_SET_1T_POS))
+#define SEC_ENG_SE_SHA_0_INT_MASK        SEC_ENG_SE_SHA_0_INT_MASK
+#define SEC_ENG_SE_SHA_0_INT_MASK_POS    (11U)
+#define SEC_ENG_SE_SHA_0_INT_MASK_LEN    (1U)
+#define SEC_ENG_SE_SHA_0_INT_MASK_MSK    (((1U << SEC_ENG_SE_SHA_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_MASK_POS)
+#define SEC_ENG_SE_SHA_0_INT_MASK_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_MASK_POS))
+#define SEC_ENG_SE_SHA_0_LINK_MODE       SEC_ENG_SE_SHA_0_LINK_MODE
+#define SEC_ENG_SE_SHA_0_LINK_MODE_POS   (15U)
+#define SEC_ENG_SE_SHA_0_LINK_MODE_LEN   (1U)
+#define SEC_ENG_SE_SHA_0_LINK_MODE_MSK   (((1U << SEC_ENG_SE_SHA_0_LINK_MODE_LEN) - 1) << SEC_ENG_SE_SHA_0_LINK_MODE_POS)
+#define SEC_ENG_SE_SHA_0_LINK_MODE_UMSK  (~(((1U << SEC_ENG_SE_SHA_0_LINK_MODE_LEN) - 1) << SEC_ENG_SE_SHA_0_LINK_MODE_POS))
+#define SEC_ENG_SE_SHA_0_MSG_LEN         SEC_ENG_SE_SHA_0_MSG_LEN
+#define SEC_ENG_SE_SHA_0_MSG_LEN_POS     (16U)
+#define SEC_ENG_SE_SHA_0_MSG_LEN_LEN     (16U)
+#define SEC_ENG_SE_SHA_0_MSG_LEN_MSK     (((1U << SEC_ENG_SE_SHA_0_MSG_LEN_LEN) - 1) << SEC_ENG_SE_SHA_0_MSG_LEN_POS)
+#define SEC_ENG_SE_SHA_0_MSG_LEN_UMSK    (~(((1U << SEC_ENG_SE_SHA_0_MSG_LEN_LEN) - 1) << SEC_ENG_SE_SHA_0_MSG_LEN_POS))
+
+/* 0x4 : se_sha_0_msa */
+#define SEC_ENG_SE_SHA_0_MSA_OFFSET (0x4)
+#define SEC_ENG_SE_SHA_0_MSA        SEC_ENG_SE_SHA_0_MSA
+#define SEC_ENG_SE_SHA_0_MSA_POS    (0U)
+#define SEC_ENG_SE_SHA_0_MSA_LEN    (32U)
+#define SEC_ENG_SE_SHA_0_MSA_MSK    (((1U << SEC_ENG_SE_SHA_0_MSA_LEN) - 1) << SEC_ENG_SE_SHA_0_MSA_POS)
+#define SEC_ENG_SE_SHA_0_MSA_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_MSA_LEN) - 1) << SEC_ENG_SE_SHA_0_MSA_POS))
+
+/* 0x8 : se_sha_0_status */
+#define SEC_ENG_SE_SHA_0_STATUS_OFFSET (0x8)
+#define SEC_ENG_SE_SHA_0_STATUS        SEC_ENG_SE_SHA_0_STATUS
+#define SEC_ENG_SE_SHA_0_STATUS_POS    (0U)
+#define SEC_ENG_SE_SHA_0_STATUS_LEN    (32U)
+#define SEC_ENG_SE_SHA_0_STATUS_MSK    (((1U << SEC_ENG_SE_SHA_0_STATUS_LEN) - 1) << SEC_ENG_SE_SHA_0_STATUS_POS)
+#define SEC_ENG_SE_SHA_0_STATUS_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_STATUS_LEN) - 1) << SEC_ENG_SE_SHA_0_STATUS_POS))
+
+/* 0xC : se_sha_0_endian */
+#define SEC_ENG_SE_SHA_0_ENDIAN_OFFSET    (0xC)
+#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN      SEC_ENG_SE_SHA_0_DOUT_ENDIAN
+#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN_POS  (0U)
+#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN_LEN  (1U)
+#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN_MSK  (((1U << SEC_ENG_SE_SHA_0_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_SHA_0_DOUT_ENDIAN_POS)
+#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_SHA_0_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_SHA_0_DOUT_ENDIAN_POS))
+
+/* 0x10 : se_sha_0_hash_l_0 */
+#define SEC_ENG_SE_SHA_0_HASH_L_0_OFFSET (0x10)
+#define SEC_ENG_SE_SHA_0_HASH_L_0        SEC_ENG_SE_SHA_0_HASH_L_0
+#define SEC_ENG_SE_SHA_0_HASH_L_0_POS    (0U)
+#define SEC_ENG_SE_SHA_0_HASH_L_0_LEN    (32U)
+#define SEC_ENG_SE_SHA_0_HASH_L_0_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_L_0_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_0_POS)
+#define SEC_ENG_SE_SHA_0_HASH_L_0_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_0_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_0_POS))
+
+/* 0x14 : se_sha_0_hash_l_1 */
+#define SEC_ENG_SE_SHA_0_HASH_L_1_OFFSET (0x14)
+#define SEC_ENG_SE_SHA_0_HASH_L_1        SEC_ENG_SE_SHA_0_HASH_L_1
+#define SEC_ENG_SE_SHA_0_HASH_L_1_POS    (0U)
+#define SEC_ENG_SE_SHA_0_HASH_L_1_LEN    (32U)
+#define SEC_ENG_SE_SHA_0_HASH_L_1_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_L_1_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_1_POS)
+#define SEC_ENG_SE_SHA_0_HASH_L_1_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_1_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_1_POS))
+
+/* 0x18 : se_sha_0_hash_l_2 */
+#define SEC_ENG_SE_SHA_0_HASH_L_2_OFFSET (0x18)
+#define SEC_ENG_SE_SHA_0_HASH_L_2        SEC_ENG_SE_SHA_0_HASH_L_2
+#define SEC_ENG_SE_SHA_0_HASH_L_2_POS    (0U)
+#define SEC_ENG_SE_SHA_0_HASH_L_2_LEN    (32U)
+#define SEC_ENG_SE_SHA_0_HASH_L_2_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_L_2_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_2_POS)
+#define SEC_ENG_SE_SHA_0_HASH_L_2_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_2_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_2_POS))
+
+/* 0x1C : se_sha_0_hash_l_3 */
+#define SEC_ENG_SE_SHA_0_HASH_L_3_OFFSET (0x1C)
+#define SEC_ENG_SE_SHA_0_HASH_L_3        SEC_ENG_SE_SHA_0_HASH_L_3
+#define SEC_ENG_SE_SHA_0_HASH_L_3_POS    (0U)
+#define SEC_ENG_SE_SHA_0_HASH_L_3_LEN    (32U)
+#define SEC_ENG_SE_SHA_0_HASH_L_3_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_L_3_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_3_POS)
+#define SEC_ENG_SE_SHA_0_HASH_L_3_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_3_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_3_POS))
+
+/* 0x20 : se_sha_0_hash_l_4 */
+#define SEC_ENG_SE_SHA_0_HASH_L_4_OFFSET (0x20)
+#define SEC_ENG_SE_SHA_0_HASH_L_4        SEC_ENG_SE_SHA_0_HASH_L_4
+#define SEC_ENG_SE_SHA_0_HASH_L_4_POS    (0U)
+#define SEC_ENG_SE_SHA_0_HASH_L_4_LEN    (32U)
+#define SEC_ENG_SE_SHA_0_HASH_L_4_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_L_4_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_4_POS)
+#define SEC_ENG_SE_SHA_0_HASH_L_4_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_4_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_4_POS))
+
+/* 0x24 : se_sha_0_hash_l_5 */
+#define SEC_ENG_SE_SHA_0_HASH_L_5_OFFSET (0x24)
+#define SEC_ENG_SE_SHA_0_HASH_L_5        SEC_ENG_SE_SHA_0_HASH_L_5
+#define SEC_ENG_SE_SHA_0_HASH_L_5_POS    (0U)
+#define SEC_ENG_SE_SHA_0_HASH_L_5_LEN    (32U)
+#define SEC_ENG_SE_SHA_0_HASH_L_5_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_L_5_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_5_POS)
+#define SEC_ENG_SE_SHA_0_HASH_L_5_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_5_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_5_POS))
+
+/* 0x28 : se_sha_0_hash_l_6 */
+#define SEC_ENG_SE_SHA_0_HASH_L_6_OFFSET (0x28)
+#define SEC_ENG_SE_SHA_0_HASH_L_6        SEC_ENG_SE_SHA_0_HASH_L_6
+#define SEC_ENG_SE_SHA_0_HASH_L_6_POS    (0U)
+#define SEC_ENG_SE_SHA_0_HASH_L_6_LEN    (32U)
+#define SEC_ENG_SE_SHA_0_HASH_L_6_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_L_6_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_6_POS)
+#define SEC_ENG_SE_SHA_0_HASH_L_6_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_6_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_6_POS))
+
+/* 0x2C : se_sha_0_hash_l_7 */
+#define SEC_ENG_SE_SHA_0_HASH_L_7_OFFSET (0x2C)
+#define SEC_ENG_SE_SHA_0_HASH_L_7        SEC_ENG_SE_SHA_0_HASH_L_7
+#define SEC_ENG_SE_SHA_0_HASH_L_7_POS    (0U)
+#define SEC_ENG_SE_SHA_0_HASH_L_7_LEN    (32U)
+#define SEC_ENG_SE_SHA_0_HASH_L_7_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_L_7_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_7_POS)
+#define SEC_ENG_SE_SHA_0_HASH_L_7_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_7_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_7_POS))
+
+/* 0x30 : se_sha_0_hash_h_0 */
+#define SEC_ENG_SE_SHA_0_HASH_H_0_OFFSET (0x30)
+#define SEC_ENG_SE_SHA_0_HASH_H_0        SEC_ENG_SE_SHA_0_HASH_H_0
+#define SEC_ENG_SE_SHA_0_HASH_H_0_POS    (0U)
+#define SEC_ENG_SE_SHA_0_HASH_H_0_LEN    (32U)
+#define SEC_ENG_SE_SHA_0_HASH_H_0_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_H_0_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_0_POS)
+#define SEC_ENG_SE_SHA_0_HASH_H_0_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_0_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_0_POS))
+
+/* 0x34 : se_sha_0_hash_h_1 */
+#define SEC_ENG_SE_SHA_0_HASH_H_1_OFFSET (0x34)
+#define SEC_ENG_SE_SHA_0_HASH_H_1        SEC_ENG_SE_SHA_0_HASH_H_1
+#define SEC_ENG_SE_SHA_0_HASH_H_1_POS    (0U)
+#define SEC_ENG_SE_SHA_0_HASH_H_1_LEN    (32U)
+#define SEC_ENG_SE_SHA_0_HASH_H_1_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_H_1_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_1_POS)
+#define SEC_ENG_SE_SHA_0_HASH_H_1_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_1_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_1_POS))
+
+/* 0x38 : se_sha_0_hash_h_2 */
+#define SEC_ENG_SE_SHA_0_HASH_H_2_OFFSET (0x38)
+#define SEC_ENG_SE_SHA_0_HASH_H_2        SEC_ENG_SE_SHA_0_HASH_H_2
+#define SEC_ENG_SE_SHA_0_HASH_H_2_POS    (0U)
+#define SEC_ENG_SE_SHA_0_HASH_H_2_LEN    (32U)
+#define SEC_ENG_SE_SHA_0_HASH_H_2_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_H_2_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_2_POS)
+#define SEC_ENG_SE_SHA_0_HASH_H_2_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_2_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_2_POS))
+
+/* 0x3C : se_sha_0_hash_h_3 */
+#define SEC_ENG_SE_SHA_0_HASH_H_3_OFFSET (0x3C)
+#define SEC_ENG_SE_SHA_0_HASH_H_3        SEC_ENG_SE_SHA_0_HASH_H_3
+#define SEC_ENG_SE_SHA_0_HASH_H_3_POS    (0U)
+#define SEC_ENG_SE_SHA_0_HASH_H_3_LEN    (32U)
+#define SEC_ENG_SE_SHA_0_HASH_H_3_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_H_3_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_3_POS)
+#define SEC_ENG_SE_SHA_0_HASH_H_3_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_3_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_3_POS))
+
+/* 0x40 : se_sha_0_hash_h_4 */
+#define SEC_ENG_SE_SHA_0_HASH_H_4_OFFSET (0x40)
+#define SEC_ENG_SE_SHA_0_HASH_H_4        SEC_ENG_SE_SHA_0_HASH_H_4
+#define SEC_ENG_SE_SHA_0_HASH_H_4_POS    (0U)
+#define SEC_ENG_SE_SHA_0_HASH_H_4_LEN    (32U)
+#define SEC_ENG_SE_SHA_0_HASH_H_4_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_H_4_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_4_POS)
+#define SEC_ENG_SE_SHA_0_HASH_H_4_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_4_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_4_POS))
+
+/* 0x44 : se_sha_0_hash_h_5 */
+#define SEC_ENG_SE_SHA_0_HASH_H_5_OFFSET (0x44)
+#define SEC_ENG_SE_SHA_0_HASH_H_5        SEC_ENG_SE_SHA_0_HASH_H_5
+#define SEC_ENG_SE_SHA_0_HASH_H_5_POS    (0U)
+#define SEC_ENG_SE_SHA_0_HASH_H_5_LEN    (32U)
+#define SEC_ENG_SE_SHA_0_HASH_H_5_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_H_5_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_5_POS)
+#define SEC_ENG_SE_SHA_0_HASH_H_5_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_5_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_5_POS))
+
+/* 0x48 : se_sha_0_hash_h_6 */
+#define SEC_ENG_SE_SHA_0_HASH_H_6_OFFSET (0x48)
+#define SEC_ENG_SE_SHA_0_HASH_H_6        SEC_ENG_SE_SHA_0_HASH_H_6
+#define SEC_ENG_SE_SHA_0_HASH_H_6_POS    (0U)
+#define SEC_ENG_SE_SHA_0_HASH_H_6_LEN    (32U)
+#define SEC_ENG_SE_SHA_0_HASH_H_6_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_H_6_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_6_POS)
+#define SEC_ENG_SE_SHA_0_HASH_H_6_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_6_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_6_POS))
+
+/* 0x4C : se_sha_0_hash_h_7 */
+#define SEC_ENG_SE_SHA_0_HASH_H_7_OFFSET (0x4C)
+#define SEC_ENG_SE_SHA_0_HASH_H_7        SEC_ENG_SE_SHA_0_HASH_H_7
+#define SEC_ENG_SE_SHA_0_HASH_H_7_POS    (0U)
+#define SEC_ENG_SE_SHA_0_HASH_H_7_LEN    (32U)
+#define SEC_ENG_SE_SHA_0_HASH_H_7_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_H_7_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_7_POS)
+#define SEC_ENG_SE_SHA_0_HASH_H_7_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_7_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_7_POS))
+
+/* 0x50 : se_sha_0_link */
+#define SEC_ENG_SE_SHA_0_LINK_OFFSET (0x50)
+#define SEC_ENG_SE_SHA_0_LCA         SEC_ENG_SE_SHA_0_LCA
+#define SEC_ENG_SE_SHA_0_LCA_POS     (0U)
+#define SEC_ENG_SE_SHA_0_LCA_LEN     (32U)
+#define SEC_ENG_SE_SHA_0_LCA_MSK     (((1U << SEC_ENG_SE_SHA_0_LCA_LEN) - 1) << SEC_ENG_SE_SHA_0_LCA_POS)
+#define SEC_ENG_SE_SHA_0_LCA_UMSK    (~(((1U << SEC_ENG_SE_SHA_0_LCA_LEN) - 1) << SEC_ENG_SE_SHA_0_LCA_POS))
+
+/* 0xFC : se_sha_0_ctrl_prot */
+#define SEC_ENG_SE_SHA_0_CTRL_PROT_OFFSET (0xFC)
+#define SEC_ENG_SE_SHA_PROT_EN            SEC_ENG_SE_SHA_PROT_EN
+#define SEC_ENG_SE_SHA_PROT_EN_POS        (0U)
+#define SEC_ENG_SE_SHA_PROT_EN_LEN        (1U)
+#define SEC_ENG_SE_SHA_PROT_EN_MSK        (((1U << SEC_ENG_SE_SHA_PROT_EN_LEN) - 1) << SEC_ENG_SE_SHA_PROT_EN_POS)
+#define SEC_ENG_SE_SHA_PROT_EN_UMSK       (~(((1U << SEC_ENG_SE_SHA_PROT_EN_LEN) - 1) << SEC_ENG_SE_SHA_PROT_EN_POS))
+#define SEC_ENG_SE_SHA_ID0_EN             SEC_ENG_SE_SHA_ID0_EN
+#define SEC_ENG_SE_SHA_ID0_EN_POS         (1U)
+#define SEC_ENG_SE_SHA_ID0_EN_LEN         (1U)
+#define SEC_ENG_SE_SHA_ID0_EN_MSK         (((1U << SEC_ENG_SE_SHA_ID0_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_POS)
+#define SEC_ENG_SE_SHA_ID0_EN_UMSK        (~(((1U << SEC_ENG_SE_SHA_ID0_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_POS))
+#define SEC_ENG_SE_SHA_ID1_EN             SEC_ENG_SE_SHA_ID1_EN
+#define SEC_ENG_SE_SHA_ID1_EN_POS         (2U)
+#define SEC_ENG_SE_SHA_ID1_EN_LEN         (1U)
+#define SEC_ENG_SE_SHA_ID1_EN_MSK         (((1U << SEC_ENG_SE_SHA_ID1_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_POS)
+#define SEC_ENG_SE_SHA_ID1_EN_UMSK        (~(((1U << SEC_ENG_SE_SHA_ID1_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_POS))
+
+/* 0x100 : se_aes_0_ctrl */
+#define SEC_ENG_SE_AES_0_CTRL_OFFSET      (0x100)
+#define SEC_ENG_SE_AES_0_BUSY             SEC_ENG_SE_AES_0_BUSY
+#define SEC_ENG_SE_AES_0_BUSY_POS         (0U)
+#define SEC_ENG_SE_AES_0_BUSY_LEN         (1U)
+#define SEC_ENG_SE_AES_0_BUSY_MSK         (((1U << SEC_ENG_SE_AES_0_BUSY_LEN) - 1) << SEC_ENG_SE_AES_0_BUSY_POS)
+#define SEC_ENG_SE_AES_0_BUSY_UMSK        (~(((1U << SEC_ENG_SE_AES_0_BUSY_LEN) - 1) << SEC_ENG_SE_AES_0_BUSY_POS))
+#define SEC_ENG_SE_AES_0_TRIG_1T          SEC_ENG_SE_AES_0_TRIG_1T
+#define SEC_ENG_SE_AES_0_TRIG_1T_POS      (1U)
+#define SEC_ENG_SE_AES_0_TRIG_1T_LEN      (1U)
+#define SEC_ENG_SE_AES_0_TRIG_1T_MSK      (((1U << SEC_ENG_SE_AES_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_AES_0_TRIG_1T_POS)
+#define SEC_ENG_SE_AES_0_TRIG_1T_UMSK     (~(((1U << SEC_ENG_SE_AES_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_AES_0_TRIG_1T_POS))
+#define SEC_ENG_SE_AES_0_EN               SEC_ENG_SE_AES_0_EN
+#define SEC_ENG_SE_AES_0_EN_POS           (2U)
+#define SEC_ENG_SE_AES_0_EN_LEN           (1U)
+#define SEC_ENG_SE_AES_0_EN_MSK           (((1U << SEC_ENG_SE_AES_0_EN_LEN) - 1) << SEC_ENG_SE_AES_0_EN_POS)
+#define SEC_ENG_SE_AES_0_EN_UMSK          (~(((1U << SEC_ENG_SE_AES_0_EN_LEN) - 1) << SEC_ENG_SE_AES_0_EN_POS))
+#define SEC_ENG_SE_AES_0_MODE             SEC_ENG_SE_AES_0_MODE
+#define SEC_ENG_SE_AES_0_MODE_POS         (3U)
+#define SEC_ENG_SE_AES_0_MODE_LEN         (2U)
+#define SEC_ENG_SE_AES_0_MODE_MSK         (((1U << SEC_ENG_SE_AES_0_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_MODE_POS)
+#define SEC_ENG_SE_AES_0_MODE_UMSK        (~(((1U << SEC_ENG_SE_AES_0_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_MODE_POS))
+#define SEC_ENG_SE_AES_0_DEC_EN           SEC_ENG_SE_AES_0_DEC_EN
+#define SEC_ENG_SE_AES_0_DEC_EN_POS       (5U)
+#define SEC_ENG_SE_AES_0_DEC_EN_LEN       (1U)
+#define SEC_ENG_SE_AES_0_DEC_EN_MSK       (((1U << SEC_ENG_SE_AES_0_DEC_EN_LEN) - 1) << SEC_ENG_SE_AES_0_DEC_EN_POS)
+#define SEC_ENG_SE_AES_0_DEC_EN_UMSK      (~(((1U << SEC_ENG_SE_AES_0_DEC_EN_LEN) - 1) << SEC_ENG_SE_AES_0_DEC_EN_POS))
+#define SEC_ENG_SE_AES_0_DEC_KEY_SEL      SEC_ENG_SE_AES_0_DEC_KEY_SEL
+#define SEC_ENG_SE_AES_0_DEC_KEY_SEL_POS  (6U)
+#define SEC_ENG_SE_AES_0_DEC_KEY_SEL_LEN  (1U)
+#define SEC_ENG_SE_AES_0_DEC_KEY_SEL_MSK  (((1U << SEC_ENG_SE_AES_0_DEC_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_DEC_KEY_SEL_POS)
+#define SEC_ENG_SE_AES_0_DEC_KEY_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_0_DEC_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_DEC_KEY_SEL_POS))
+#define SEC_ENG_SE_AES_0_HW_KEY_EN        SEC_ENG_SE_AES_0_HW_KEY_EN
+#define SEC_ENG_SE_AES_0_HW_KEY_EN_POS    (7U)
+#define SEC_ENG_SE_AES_0_HW_KEY_EN_LEN    (1U)
+#define SEC_ENG_SE_AES_0_HW_KEY_EN_MSK    (((1U << SEC_ENG_SE_AES_0_HW_KEY_EN_LEN) - 1) << SEC_ENG_SE_AES_0_HW_KEY_EN_POS)
+#define SEC_ENG_SE_AES_0_HW_KEY_EN_UMSK   (~(((1U << SEC_ENG_SE_AES_0_HW_KEY_EN_LEN) - 1) << SEC_ENG_SE_AES_0_HW_KEY_EN_POS))
+#define SEC_ENG_SE_AES_0_INT              SEC_ENG_SE_AES_0_INT
+#define SEC_ENG_SE_AES_0_INT_POS          (8U)
+#define SEC_ENG_SE_AES_0_INT_LEN          (1U)
+#define SEC_ENG_SE_AES_0_INT_MSK          (((1U << SEC_ENG_SE_AES_0_INT_LEN) - 1) << SEC_ENG_SE_AES_0_INT_POS)
+#define SEC_ENG_SE_AES_0_INT_UMSK         (~(((1U << SEC_ENG_SE_AES_0_INT_LEN) - 1) << SEC_ENG_SE_AES_0_INT_POS))
+#define SEC_ENG_SE_AES_0_INT_CLR_1T       SEC_ENG_SE_AES_0_INT_CLR_1T
+#define SEC_ENG_SE_AES_0_INT_CLR_1T_POS   (9U)
+#define SEC_ENG_SE_AES_0_INT_CLR_1T_LEN   (1U)
+#define SEC_ENG_SE_AES_0_INT_CLR_1T_MSK   (((1U << SEC_ENG_SE_AES_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_AES_0_INT_CLR_1T_POS)
+#define SEC_ENG_SE_AES_0_INT_CLR_1T_UMSK  (~(((1U << SEC_ENG_SE_AES_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_AES_0_INT_CLR_1T_POS))
+#define SEC_ENG_SE_AES_0_INT_SET_1T       SEC_ENG_SE_AES_0_INT_SET_1T
+#define SEC_ENG_SE_AES_0_INT_SET_1T_POS   (10U)
+#define SEC_ENG_SE_AES_0_INT_SET_1T_LEN   (1U)
+#define SEC_ENG_SE_AES_0_INT_SET_1T_MSK   (((1U << SEC_ENG_SE_AES_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_AES_0_INT_SET_1T_POS)
+#define SEC_ENG_SE_AES_0_INT_SET_1T_UMSK  (~(((1U << SEC_ENG_SE_AES_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_AES_0_INT_SET_1T_POS))
+#define SEC_ENG_SE_AES_0_INT_MASK         SEC_ENG_SE_AES_0_INT_MASK
+#define SEC_ENG_SE_AES_0_INT_MASK_POS     (11U)
+#define SEC_ENG_SE_AES_0_INT_MASK_LEN     (1U)
+#define SEC_ENG_SE_AES_0_INT_MASK_MSK     (((1U << SEC_ENG_SE_AES_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_AES_0_INT_MASK_POS)
+#define SEC_ENG_SE_AES_0_INT_MASK_UMSK    (~(((1U << SEC_ENG_SE_AES_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_AES_0_INT_MASK_POS))
+#define SEC_ENG_SE_AES_0_BLOCK_MODE       SEC_ENG_SE_AES_0_BLOCK_MODE
+#define SEC_ENG_SE_AES_0_BLOCK_MODE_POS   (12U)
+#define SEC_ENG_SE_AES_0_BLOCK_MODE_LEN   (2U)
+#define SEC_ENG_SE_AES_0_BLOCK_MODE_MSK   (((1U << SEC_ENG_SE_AES_0_BLOCK_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_BLOCK_MODE_POS)
+#define SEC_ENG_SE_AES_0_BLOCK_MODE_UMSK  (~(((1U << SEC_ENG_SE_AES_0_BLOCK_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_BLOCK_MODE_POS))
+#define SEC_ENG_SE_AES_0_IV_SEL           SEC_ENG_SE_AES_0_IV_SEL
+#define SEC_ENG_SE_AES_0_IV_SEL_POS       (14U)
+#define SEC_ENG_SE_AES_0_IV_SEL_LEN       (1U)
+#define SEC_ENG_SE_AES_0_IV_SEL_MSK       (((1U << SEC_ENG_SE_AES_0_IV_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_IV_SEL_POS)
+#define SEC_ENG_SE_AES_0_IV_SEL_UMSK      (~(((1U << SEC_ENG_SE_AES_0_IV_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_IV_SEL_POS))
+#define SEC_ENG_SE_AES_0_LINK_MODE        SEC_ENG_SE_AES_0_LINK_MODE
+#define SEC_ENG_SE_AES_0_LINK_MODE_POS    (15U)
+#define SEC_ENG_SE_AES_0_LINK_MODE_LEN    (1U)
+#define SEC_ENG_SE_AES_0_LINK_MODE_MSK    (((1U << SEC_ENG_SE_AES_0_LINK_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_LINK_MODE_POS)
+#define SEC_ENG_SE_AES_0_LINK_MODE_UMSK   (~(((1U << SEC_ENG_SE_AES_0_LINK_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_LINK_MODE_POS))
+#define SEC_ENG_SE_AES_0_MSG_LEN          SEC_ENG_SE_AES_0_MSG_LEN
+#define SEC_ENG_SE_AES_0_MSG_LEN_POS      (16U)
+#define SEC_ENG_SE_AES_0_MSG_LEN_LEN      (16U)
+#define SEC_ENG_SE_AES_0_MSG_LEN_MSK      (((1U << SEC_ENG_SE_AES_0_MSG_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_MSG_LEN_POS)
+#define SEC_ENG_SE_AES_0_MSG_LEN_UMSK     (~(((1U << SEC_ENG_SE_AES_0_MSG_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_MSG_LEN_POS))
+
+/* 0x104 : se_aes_0_msa */
+#define SEC_ENG_SE_AES_0_MSA_OFFSET (0x104)
+#define SEC_ENG_SE_AES_0_MSA        SEC_ENG_SE_AES_0_MSA
+#define SEC_ENG_SE_AES_0_MSA_POS    (0U)
+#define SEC_ENG_SE_AES_0_MSA_LEN    (32U)
+#define SEC_ENG_SE_AES_0_MSA_MSK    (((1U << SEC_ENG_SE_AES_0_MSA_LEN) - 1) << SEC_ENG_SE_AES_0_MSA_POS)
+#define SEC_ENG_SE_AES_0_MSA_UMSK   (~(((1U << SEC_ENG_SE_AES_0_MSA_LEN) - 1) << SEC_ENG_SE_AES_0_MSA_POS))
+
+/* 0x108 : se_aes_0_mda */
+#define SEC_ENG_SE_AES_0_MDA_OFFSET (0x108)
+#define SEC_ENG_SE_AES_0_MDA        SEC_ENG_SE_AES_0_MDA
+#define SEC_ENG_SE_AES_0_MDA_POS    (0U)
+#define SEC_ENG_SE_AES_0_MDA_LEN    (32U)
+#define SEC_ENG_SE_AES_0_MDA_MSK    (((1U << SEC_ENG_SE_AES_0_MDA_LEN) - 1) << SEC_ENG_SE_AES_0_MDA_POS)
+#define SEC_ENG_SE_AES_0_MDA_UMSK   (~(((1U << SEC_ENG_SE_AES_0_MDA_LEN) - 1) << SEC_ENG_SE_AES_0_MDA_POS))
+
+/* 0x10C : se_aes_0_status */
+#define SEC_ENG_SE_AES_0_STATUS_OFFSET (0x10C)
+#define SEC_ENG_SE_AES_0_STATUS        SEC_ENG_SE_AES_0_STATUS
+#define SEC_ENG_SE_AES_0_STATUS_POS    (0U)
+#define SEC_ENG_SE_AES_0_STATUS_LEN    (32U)
+#define SEC_ENG_SE_AES_0_STATUS_MSK    (((1U << SEC_ENG_SE_AES_0_STATUS_LEN) - 1) << SEC_ENG_SE_AES_0_STATUS_POS)
+#define SEC_ENG_SE_AES_0_STATUS_UMSK   (~(((1U << SEC_ENG_SE_AES_0_STATUS_LEN) - 1) << SEC_ENG_SE_AES_0_STATUS_POS))
+
+/* 0x110 : se_aes_0_iv_0 */
+#define SEC_ENG_SE_AES_0_IV_0_OFFSET (0x110)
+#define SEC_ENG_SE_AES_0_IV_0        SEC_ENG_SE_AES_0_IV_0
+#define SEC_ENG_SE_AES_0_IV_0_POS    (0U)
+#define SEC_ENG_SE_AES_0_IV_0_LEN    (32U)
+#define SEC_ENG_SE_AES_0_IV_0_MSK    (((1U << SEC_ENG_SE_AES_0_IV_0_LEN) - 1) << SEC_ENG_SE_AES_0_IV_0_POS)
+#define SEC_ENG_SE_AES_0_IV_0_UMSK   (~(((1U << SEC_ENG_SE_AES_0_IV_0_LEN) - 1) << SEC_ENG_SE_AES_0_IV_0_POS))
+
+/* 0x114 : se_aes_0_iv_1 */
+#define SEC_ENG_SE_AES_0_IV_1_OFFSET (0x114)
+#define SEC_ENG_SE_AES_0_IV_1        SEC_ENG_SE_AES_0_IV_1
+#define SEC_ENG_SE_AES_0_IV_1_POS    (0U)
+#define SEC_ENG_SE_AES_0_IV_1_LEN    (32U)
+#define SEC_ENG_SE_AES_0_IV_1_MSK    (((1U << SEC_ENG_SE_AES_0_IV_1_LEN) - 1) << SEC_ENG_SE_AES_0_IV_1_POS)
+#define SEC_ENG_SE_AES_0_IV_1_UMSK   (~(((1U << SEC_ENG_SE_AES_0_IV_1_LEN) - 1) << SEC_ENG_SE_AES_0_IV_1_POS))
+
+/* 0x118 : se_aes_0_iv_2 */
+#define SEC_ENG_SE_AES_0_IV_2_OFFSET (0x118)
+#define SEC_ENG_SE_AES_0_IV_2        SEC_ENG_SE_AES_0_IV_2
+#define SEC_ENG_SE_AES_0_IV_2_POS    (0U)
+#define SEC_ENG_SE_AES_0_IV_2_LEN    (32U)
+#define SEC_ENG_SE_AES_0_IV_2_MSK    (((1U << SEC_ENG_SE_AES_0_IV_2_LEN) - 1) << SEC_ENG_SE_AES_0_IV_2_POS)
+#define SEC_ENG_SE_AES_0_IV_2_UMSK   (~(((1U << SEC_ENG_SE_AES_0_IV_2_LEN) - 1) << SEC_ENG_SE_AES_0_IV_2_POS))
+
+/* 0x11C : se_aes_0_iv_3 */
+#define SEC_ENG_SE_AES_0_IV_3_OFFSET (0x11C)
+#define SEC_ENG_SE_AES_0_IV_3        SEC_ENG_SE_AES_0_IV_3
+#define SEC_ENG_SE_AES_0_IV_3_POS    (0U)
+#define SEC_ENG_SE_AES_0_IV_3_LEN    (32U)
+#define SEC_ENG_SE_AES_0_IV_3_MSK    (((1U << SEC_ENG_SE_AES_0_IV_3_LEN) - 1) << SEC_ENG_SE_AES_0_IV_3_POS)
+#define SEC_ENG_SE_AES_0_IV_3_UMSK   (~(((1U << SEC_ENG_SE_AES_0_IV_3_LEN) - 1) << SEC_ENG_SE_AES_0_IV_3_POS))
+
+/* 0x120 : se_aes_0_key_0 */
+#define SEC_ENG_SE_AES_0_KEY_0_OFFSET (0x120)
+#define SEC_ENG_SE_AES_0_KEY_0        SEC_ENG_SE_AES_0_KEY_0
+#define SEC_ENG_SE_AES_0_KEY_0_POS    (0U)
+#define SEC_ENG_SE_AES_0_KEY_0_LEN    (32U)
+#define SEC_ENG_SE_AES_0_KEY_0_MSK    (((1U << SEC_ENG_SE_AES_0_KEY_0_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_0_POS)
+#define SEC_ENG_SE_AES_0_KEY_0_UMSK   (~(((1U << SEC_ENG_SE_AES_0_KEY_0_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_0_POS))
+
+/* 0x124 : se_aes_0_key_1 */
+#define SEC_ENG_SE_AES_0_KEY_1_OFFSET (0x124)
+#define SEC_ENG_SE_AES_0_KEY_1        SEC_ENG_SE_AES_0_KEY_1
+#define SEC_ENG_SE_AES_0_KEY_1_POS    (0U)
+#define SEC_ENG_SE_AES_0_KEY_1_LEN    (32U)
+#define SEC_ENG_SE_AES_0_KEY_1_MSK    (((1U << SEC_ENG_SE_AES_0_KEY_1_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_1_POS)
+#define SEC_ENG_SE_AES_0_KEY_1_UMSK   (~(((1U << SEC_ENG_SE_AES_0_KEY_1_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_1_POS))
+
+/* 0x128 : se_aes_0_key_2 */
+#define SEC_ENG_SE_AES_0_KEY_2_OFFSET (0x128)
+#define SEC_ENG_SE_AES_0_KEY_2        SEC_ENG_SE_AES_0_KEY_2
+#define SEC_ENG_SE_AES_0_KEY_2_POS    (0U)
+#define SEC_ENG_SE_AES_0_KEY_2_LEN    (32U)
+#define SEC_ENG_SE_AES_0_KEY_2_MSK    (((1U << SEC_ENG_SE_AES_0_KEY_2_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_2_POS)
+#define SEC_ENG_SE_AES_0_KEY_2_UMSK   (~(((1U << SEC_ENG_SE_AES_0_KEY_2_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_2_POS))
+
+/* 0x12C : se_aes_0_key_3 */
+#define SEC_ENG_SE_AES_0_KEY_3_OFFSET (0x12C)
+#define SEC_ENG_SE_AES_0_KEY_3        SEC_ENG_SE_AES_0_KEY_3
+#define SEC_ENG_SE_AES_0_KEY_3_POS    (0U)
+#define SEC_ENG_SE_AES_0_KEY_3_LEN    (32U)
+#define SEC_ENG_SE_AES_0_KEY_3_MSK    (((1U << SEC_ENG_SE_AES_0_KEY_3_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_3_POS)
+#define SEC_ENG_SE_AES_0_KEY_3_UMSK   (~(((1U << SEC_ENG_SE_AES_0_KEY_3_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_3_POS))
+
+/* 0x130 : se_aes_0_key_4 */
+#define SEC_ENG_SE_AES_0_KEY_4_OFFSET (0x130)
+#define SEC_ENG_SE_AES_0_KEY_4        SEC_ENG_SE_AES_0_KEY_4
+#define SEC_ENG_SE_AES_0_KEY_4_POS    (0U)
+#define SEC_ENG_SE_AES_0_KEY_4_LEN    (32U)
+#define SEC_ENG_SE_AES_0_KEY_4_MSK    (((1U << SEC_ENG_SE_AES_0_KEY_4_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_4_POS)
+#define SEC_ENG_SE_AES_0_KEY_4_UMSK   (~(((1U << SEC_ENG_SE_AES_0_KEY_4_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_4_POS))
+
+/* 0x134 : se_aes_0_key_5 */
+#define SEC_ENG_SE_AES_0_KEY_5_OFFSET (0x134)
+#define SEC_ENG_SE_AES_0_KEY_5        SEC_ENG_SE_AES_0_KEY_5
+#define SEC_ENG_SE_AES_0_KEY_5_POS    (0U)
+#define SEC_ENG_SE_AES_0_KEY_5_LEN    (32U)
+#define SEC_ENG_SE_AES_0_KEY_5_MSK    (((1U << SEC_ENG_SE_AES_0_KEY_5_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_5_POS)
+#define SEC_ENG_SE_AES_0_KEY_5_UMSK   (~(((1U << SEC_ENG_SE_AES_0_KEY_5_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_5_POS))
+
+/* 0x138 : se_aes_0_key_6 */
+#define SEC_ENG_SE_AES_0_KEY_6_OFFSET (0x138)
+#define SEC_ENG_SE_AES_0_KEY_6        SEC_ENG_SE_AES_0_KEY_6
+#define SEC_ENG_SE_AES_0_KEY_6_POS    (0U)
+#define SEC_ENG_SE_AES_0_KEY_6_LEN    (32U)
+#define SEC_ENG_SE_AES_0_KEY_6_MSK    (((1U << SEC_ENG_SE_AES_0_KEY_6_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_6_POS)
+#define SEC_ENG_SE_AES_0_KEY_6_UMSK   (~(((1U << SEC_ENG_SE_AES_0_KEY_6_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_6_POS))
+
+/* 0x13C : se_aes_0_key_7 */
+#define SEC_ENG_SE_AES_0_KEY_7_OFFSET (0x13C)
+#define SEC_ENG_SE_AES_0_KEY_7        SEC_ENG_SE_AES_0_KEY_7
+#define SEC_ENG_SE_AES_0_KEY_7_POS    (0U)
+#define SEC_ENG_SE_AES_0_KEY_7_LEN    (32U)
+#define SEC_ENG_SE_AES_0_KEY_7_MSK    (((1U << SEC_ENG_SE_AES_0_KEY_7_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_7_POS)
+#define SEC_ENG_SE_AES_0_KEY_7_UMSK   (~(((1U << SEC_ENG_SE_AES_0_KEY_7_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_7_POS))
+
+/* 0x140 : se_aes_0_key_sel_0 */
+#define SEC_ENG_SE_AES_0_KEY_SEL_0_OFFSET (0x140)
+#define SEC_ENG_SE_AES_0_KEY_SEL_0        SEC_ENG_SE_AES_0_KEY_SEL_0
+#define SEC_ENG_SE_AES_0_KEY_SEL_0_POS    (0U)
+#define SEC_ENG_SE_AES_0_KEY_SEL_0_LEN    (2U)
+#define SEC_ENG_SE_AES_0_KEY_SEL_0_MSK    (((1U << SEC_ENG_SE_AES_0_KEY_SEL_0_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_SEL_0_POS)
+#define SEC_ENG_SE_AES_0_KEY_SEL_0_UMSK   (~(((1U << SEC_ENG_SE_AES_0_KEY_SEL_0_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_SEL_0_POS))
+
+/* 0x144 : se_aes_0_key_sel_1 */
+#define SEC_ENG_SE_AES_0_KEY_SEL_1_OFFSET (0x144)
+#define SEC_ENG_SE_AES_0_KEY_SEL_1        SEC_ENG_SE_AES_0_KEY_SEL_1
+#define SEC_ENG_SE_AES_0_KEY_SEL_1_POS    (0U)
+#define SEC_ENG_SE_AES_0_KEY_SEL_1_LEN    (2U)
+#define SEC_ENG_SE_AES_0_KEY_SEL_1_MSK    (((1U << SEC_ENG_SE_AES_0_KEY_SEL_1_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_SEL_1_POS)
+#define SEC_ENG_SE_AES_0_KEY_SEL_1_UMSK   (~(((1U << SEC_ENG_SE_AES_0_KEY_SEL_1_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_SEL_1_POS))
+
+/* 0x148 : se_aes_0_endian */
+#define SEC_ENG_SE_AES_0_ENDIAN_OFFSET    (0x148)
+#define SEC_ENG_SE_AES_0_DOUT_ENDIAN      SEC_ENG_SE_AES_0_DOUT_ENDIAN
+#define SEC_ENG_SE_AES_0_DOUT_ENDIAN_POS  (0U)
+#define SEC_ENG_SE_AES_0_DOUT_ENDIAN_LEN  (1U)
+#define SEC_ENG_SE_AES_0_DOUT_ENDIAN_MSK  (((1U << SEC_ENG_SE_AES_0_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_DOUT_ENDIAN_POS)
+#define SEC_ENG_SE_AES_0_DOUT_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_0_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_DOUT_ENDIAN_POS))
+#define SEC_ENG_SE_AES_0_DIN_ENDIAN       SEC_ENG_SE_AES_0_DIN_ENDIAN
+#define SEC_ENG_SE_AES_0_DIN_ENDIAN_POS   (1U)
+#define SEC_ENG_SE_AES_0_DIN_ENDIAN_LEN   (1U)
+#define SEC_ENG_SE_AES_0_DIN_ENDIAN_MSK   (((1U << SEC_ENG_SE_AES_0_DIN_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_DIN_ENDIAN_POS)
+#define SEC_ENG_SE_AES_0_DIN_ENDIAN_UMSK  (~(((1U << SEC_ENG_SE_AES_0_DIN_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_DIN_ENDIAN_POS))
+#define SEC_ENG_SE_AES_0_KEY_ENDIAN       SEC_ENG_SE_AES_0_KEY_ENDIAN
+#define SEC_ENG_SE_AES_0_KEY_ENDIAN_POS   (2U)
+#define SEC_ENG_SE_AES_0_KEY_ENDIAN_LEN   (1U)
+#define SEC_ENG_SE_AES_0_KEY_ENDIAN_MSK   (((1U << SEC_ENG_SE_AES_0_KEY_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_ENDIAN_POS)
+#define SEC_ENG_SE_AES_0_KEY_ENDIAN_UMSK  (~(((1U << SEC_ENG_SE_AES_0_KEY_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_ENDIAN_POS))
+#define SEC_ENG_SE_AES_0_IV_ENDIAN        SEC_ENG_SE_AES_0_IV_ENDIAN
+#define SEC_ENG_SE_AES_0_IV_ENDIAN_POS    (3U)
+#define SEC_ENG_SE_AES_0_IV_ENDIAN_LEN    (1U)
+#define SEC_ENG_SE_AES_0_IV_ENDIAN_MSK    (((1U << SEC_ENG_SE_AES_0_IV_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_IV_ENDIAN_POS)
+#define SEC_ENG_SE_AES_0_IV_ENDIAN_UMSK   (~(((1U << SEC_ENG_SE_AES_0_IV_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_IV_ENDIAN_POS))
+#define SEC_ENG_SE_AES_0_CTR_LEN          SEC_ENG_SE_AES_0_CTR_LEN
+#define SEC_ENG_SE_AES_0_CTR_LEN_POS      (30U)
+#define SEC_ENG_SE_AES_0_CTR_LEN_LEN      (2U)
+#define SEC_ENG_SE_AES_0_CTR_LEN_MSK      (((1U << SEC_ENG_SE_AES_0_CTR_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_CTR_LEN_POS)
+#define SEC_ENG_SE_AES_0_CTR_LEN_UMSK     (~(((1U << SEC_ENG_SE_AES_0_CTR_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_CTR_LEN_POS))
+
+/* 0x14C : se_aes_0_sboot */
+#define SEC_ENG_SE_AES_0_SBOOT_OFFSET       (0x14C)
+#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL      SEC_ENG_SE_AES_0_SBOOT_KEY_SEL
+#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_POS  (0U)
+#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_LEN  (1U)
+#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_MSK  (((1U << SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_POS)
+#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_POS))
+
+/* 0x150 : se_aes_0_link */
+#define SEC_ENG_SE_AES_0_LINK_OFFSET (0x150)
+#define SEC_ENG_SE_AES_0_LCA         SEC_ENG_SE_AES_0_LCA
+#define SEC_ENG_SE_AES_0_LCA_POS     (0U)
+#define SEC_ENG_SE_AES_0_LCA_LEN     (32U)
+#define SEC_ENG_SE_AES_0_LCA_MSK     (((1U << SEC_ENG_SE_AES_0_LCA_LEN) - 1) << SEC_ENG_SE_AES_0_LCA_POS)
+#define SEC_ENG_SE_AES_0_LCA_UMSK    (~(((1U << SEC_ENG_SE_AES_0_LCA_LEN) - 1) << SEC_ENG_SE_AES_0_LCA_POS))
+
+/* 0x1FC : se_aes_0_ctrl_prot */
+#define SEC_ENG_SE_AES_0_CTRL_PROT_OFFSET (0x1FC)
+#define SEC_ENG_SE_AES_PROT_EN            SEC_ENG_SE_AES_PROT_EN
+#define SEC_ENG_SE_AES_PROT_EN_POS        (0U)
+#define SEC_ENG_SE_AES_PROT_EN_LEN        (1U)
+#define SEC_ENG_SE_AES_PROT_EN_MSK        (((1U << SEC_ENG_SE_AES_PROT_EN_LEN) - 1) << SEC_ENG_SE_AES_PROT_EN_POS)
+#define SEC_ENG_SE_AES_PROT_EN_UMSK       (~(((1U << SEC_ENG_SE_AES_PROT_EN_LEN) - 1) << SEC_ENG_SE_AES_PROT_EN_POS))
+#define SEC_ENG_SE_AES_ID0_EN             SEC_ENG_SE_AES_ID0_EN
+#define SEC_ENG_SE_AES_ID0_EN_POS         (1U)
+#define SEC_ENG_SE_AES_ID0_EN_LEN         (1U)
+#define SEC_ENG_SE_AES_ID0_EN_MSK         (((1U << SEC_ENG_SE_AES_ID0_EN_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_POS)
+#define SEC_ENG_SE_AES_ID0_EN_UMSK        (~(((1U << SEC_ENG_SE_AES_ID0_EN_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_POS))
+#define SEC_ENG_SE_AES_ID1_EN             SEC_ENG_SE_AES_ID1_EN
+#define SEC_ENG_SE_AES_ID1_EN_POS         (2U)
+#define SEC_ENG_SE_AES_ID1_EN_LEN         (1U)
+#define SEC_ENG_SE_AES_ID1_EN_MSK         (((1U << SEC_ENG_SE_AES_ID1_EN_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_POS)
+#define SEC_ENG_SE_AES_ID1_EN_UMSK        (~(((1U << SEC_ENG_SE_AES_ID1_EN_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_POS))
+
+/* 0x200 : se_trng_0_ctrl_0 */
+#define SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET       (0x200)
+#define SEC_ENG_SE_TRNG_0_BUSY                SEC_ENG_SE_TRNG_0_BUSY
+#define SEC_ENG_SE_TRNG_0_BUSY_POS            (0U)
+#define SEC_ENG_SE_TRNG_0_BUSY_LEN            (1U)
+#define SEC_ENG_SE_TRNG_0_BUSY_MSK            (((1U << SEC_ENG_SE_TRNG_0_BUSY_LEN) - 1) << SEC_ENG_SE_TRNG_0_BUSY_POS)
+#define SEC_ENG_SE_TRNG_0_BUSY_UMSK           (~(((1U << SEC_ENG_SE_TRNG_0_BUSY_LEN) - 1) << SEC_ENG_SE_TRNG_0_BUSY_POS))
+#define SEC_ENG_SE_TRNG_0_TRIG_1T             SEC_ENG_SE_TRNG_0_TRIG_1T
+#define SEC_ENG_SE_TRNG_0_TRIG_1T_POS         (1U)
+#define SEC_ENG_SE_TRNG_0_TRIG_1T_LEN         (1U)
+#define SEC_ENG_SE_TRNG_0_TRIG_1T_MSK         (((1U << SEC_ENG_SE_TRNG_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_TRIG_1T_POS)
+#define SEC_ENG_SE_TRNG_0_TRIG_1T_UMSK        (~(((1U << SEC_ENG_SE_TRNG_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_TRIG_1T_POS))
+#define SEC_ENG_SE_TRNG_0_EN                  SEC_ENG_SE_TRNG_0_EN
+#define SEC_ENG_SE_TRNG_0_EN_POS              (2U)
+#define SEC_ENG_SE_TRNG_0_EN_LEN              (1U)
+#define SEC_ENG_SE_TRNG_0_EN_MSK              (((1U << SEC_ENG_SE_TRNG_0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_EN_POS)
+#define SEC_ENG_SE_TRNG_0_EN_UMSK             (~(((1U << SEC_ENG_SE_TRNG_0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_EN_POS))
+#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T         SEC_ENG_SE_TRNG_0_DOUT_CLR_1T
+#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_POS     (3U)
+#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_LEN     (1U)
+#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_MSK     (((1U << SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_POS)
+#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_UMSK    (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_POS))
+#define SEC_ENG_SE_TRNG_0_HT_ERROR            SEC_ENG_SE_TRNG_0_HT_ERROR
+#define SEC_ENG_SE_TRNG_0_HT_ERROR_POS        (4U)
+#define SEC_ENG_SE_TRNG_0_HT_ERROR_LEN        (1U)
+#define SEC_ENG_SE_TRNG_0_HT_ERROR_MSK        (((1U << SEC_ENG_SE_TRNG_0_HT_ERROR_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_ERROR_POS)
+#define SEC_ENG_SE_TRNG_0_HT_ERROR_UMSK       (~(((1U << SEC_ENG_SE_TRNG_0_HT_ERROR_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_ERROR_POS))
+#define SEC_ENG_SE_TRNG_0_INT                 SEC_ENG_SE_TRNG_0_INT
+#define SEC_ENG_SE_TRNG_0_INT_POS             (8U)
+#define SEC_ENG_SE_TRNG_0_INT_LEN             (1U)
+#define SEC_ENG_SE_TRNG_0_INT_MSK             (((1U << SEC_ENG_SE_TRNG_0_INT_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_POS)
+#define SEC_ENG_SE_TRNG_0_INT_UMSK            (~(((1U << SEC_ENG_SE_TRNG_0_INT_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_POS))
+#define SEC_ENG_SE_TRNG_0_INT_CLR_1T          SEC_ENG_SE_TRNG_0_INT_CLR_1T
+#define SEC_ENG_SE_TRNG_0_INT_CLR_1T_POS      (9U)
+#define SEC_ENG_SE_TRNG_0_INT_CLR_1T_LEN      (1U)
+#define SEC_ENG_SE_TRNG_0_INT_CLR_1T_MSK      (((1U << SEC_ENG_SE_TRNG_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_CLR_1T_POS)
+#define SEC_ENG_SE_TRNG_0_INT_CLR_1T_UMSK     (~(((1U << SEC_ENG_SE_TRNG_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_CLR_1T_POS))
+#define SEC_ENG_SE_TRNG_0_INT_SET_1T          SEC_ENG_SE_TRNG_0_INT_SET_1T
+#define SEC_ENG_SE_TRNG_0_INT_SET_1T_POS      (10U)
+#define SEC_ENG_SE_TRNG_0_INT_SET_1T_LEN      (1U)
+#define SEC_ENG_SE_TRNG_0_INT_SET_1T_MSK      (((1U << SEC_ENG_SE_TRNG_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_SET_1T_POS)
+#define SEC_ENG_SE_TRNG_0_INT_SET_1T_UMSK     (~(((1U << SEC_ENG_SE_TRNG_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_SET_1T_POS))
+#define SEC_ENG_SE_TRNG_0_INT_MASK            SEC_ENG_SE_TRNG_0_INT_MASK
+#define SEC_ENG_SE_TRNG_0_INT_MASK_POS        (11U)
+#define SEC_ENG_SE_TRNG_0_INT_MASK_LEN        (1U)
+#define SEC_ENG_SE_TRNG_0_INT_MASK_MSK        (((1U << SEC_ENG_SE_TRNG_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_MASK_POS)
+#define SEC_ENG_SE_TRNG_0_INT_MASK_UMSK       (~(((1U << SEC_ENG_SE_TRNG_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_MASK_POS))
+#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL      SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL
+#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_POS  (13U)
+#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_LEN  (1U)
+#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_MSK  (((1U << SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_POS)
+#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_POS))
+#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED       SEC_ENG_SE_TRNG_0_MANUAL_RESEED
+#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED_POS   (14U)
+#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED_LEN   (1U)
+#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED_MSK   (((1U << SEC_ENG_SE_TRNG_0_MANUAL_RESEED_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_RESEED_POS)
+#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED_UMSK  (~(((1U << SEC_ENG_SE_TRNG_0_MANUAL_RESEED_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_RESEED_POS))
+#define SEC_ENG_SE_TRNG_0_MANUAL_EN           SEC_ENG_SE_TRNG_0_MANUAL_EN
+#define SEC_ENG_SE_TRNG_0_MANUAL_EN_POS       (15U)
+#define SEC_ENG_SE_TRNG_0_MANUAL_EN_LEN       (1U)
+#define SEC_ENG_SE_TRNG_0_MANUAL_EN_MSK       (((1U << SEC_ENG_SE_TRNG_0_MANUAL_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_EN_POS)
+#define SEC_ENG_SE_TRNG_0_MANUAL_EN_UMSK      (~(((1U << SEC_ENG_SE_TRNG_0_MANUAL_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_EN_POS))
+
+/* 0x204 : se_trng_0_status */
+#define SEC_ENG_SE_TRNG_0_STATUS_OFFSET (0x204)
+#define SEC_ENG_SE_TRNG_0_STATUS        SEC_ENG_SE_TRNG_0_STATUS
+#define SEC_ENG_SE_TRNG_0_STATUS_POS    (0U)
+#define SEC_ENG_SE_TRNG_0_STATUS_LEN    (32U)
+#define SEC_ENG_SE_TRNG_0_STATUS_MSK    (((1U << SEC_ENG_SE_TRNG_0_STATUS_LEN) - 1) << SEC_ENG_SE_TRNG_0_STATUS_POS)
+#define SEC_ENG_SE_TRNG_0_STATUS_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_STATUS_LEN) - 1) << SEC_ENG_SE_TRNG_0_STATUS_POS))
+
+/* 0x208 : se_trng_0_dout_0 */
+#define SEC_ENG_SE_TRNG_0_DOUT_0_OFFSET (0x208)
+#define SEC_ENG_SE_TRNG_0_DOUT_0        SEC_ENG_SE_TRNG_0_DOUT_0
+#define SEC_ENG_SE_TRNG_0_DOUT_0_POS    (0U)
+#define SEC_ENG_SE_TRNG_0_DOUT_0_LEN    (32U)
+#define SEC_ENG_SE_TRNG_0_DOUT_0_MSK    (((1U << SEC_ENG_SE_TRNG_0_DOUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_0_POS)
+#define SEC_ENG_SE_TRNG_0_DOUT_0_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_0_POS))
+
+/* 0x20C : se_trng_0_dout_1 */
+#define SEC_ENG_SE_TRNG_0_DOUT_1_OFFSET (0x20C)
+#define SEC_ENG_SE_TRNG_0_DOUT_1        SEC_ENG_SE_TRNG_0_DOUT_1
+#define SEC_ENG_SE_TRNG_0_DOUT_1_POS    (0U)
+#define SEC_ENG_SE_TRNG_0_DOUT_1_LEN    (32U)
+#define SEC_ENG_SE_TRNG_0_DOUT_1_MSK    (((1U << SEC_ENG_SE_TRNG_0_DOUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_1_POS)
+#define SEC_ENG_SE_TRNG_0_DOUT_1_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_1_POS))
+
+/* 0x210 : se_trng_0_dout_2 */
+#define SEC_ENG_SE_TRNG_0_DOUT_2_OFFSET (0x210)
+#define SEC_ENG_SE_TRNG_0_DOUT_2        SEC_ENG_SE_TRNG_0_DOUT_2
+#define SEC_ENG_SE_TRNG_0_DOUT_2_POS    (0U)
+#define SEC_ENG_SE_TRNG_0_DOUT_2_LEN    (32U)
+#define SEC_ENG_SE_TRNG_0_DOUT_2_MSK    (((1U << SEC_ENG_SE_TRNG_0_DOUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_2_POS)
+#define SEC_ENG_SE_TRNG_0_DOUT_2_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_2_POS))
+
+/* 0x214 : se_trng_0_dout_3 */
+#define SEC_ENG_SE_TRNG_0_DOUT_3_OFFSET (0x214)
+#define SEC_ENG_SE_TRNG_0_DOUT_3        SEC_ENG_SE_TRNG_0_DOUT_3
+#define SEC_ENG_SE_TRNG_0_DOUT_3_POS    (0U)
+#define SEC_ENG_SE_TRNG_0_DOUT_3_LEN    (32U)
+#define SEC_ENG_SE_TRNG_0_DOUT_3_MSK    (((1U << SEC_ENG_SE_TRNG_0_DOUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_3_POS)
+#define SEC_ENG_SE_TRNG_0_DOUT_3_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_3_POS))
+
+/* 0x218 : se_trng_0_dout_4 */
+#define SEC_ENG_SE_TRNG_0_DOUT_4_OFFSET (0x218)
+#define SEC_ENG_SE_TRNG_0_DOUT_4        SEC_ENG_SE_TRNG_0_DOUT_4
+#define SEC_ENG_SE_TRNG_0_DOUT_4_POS    (0U)
+#define SEC_ENG_SE_TRNG_0_DOUT_4_LEN    (32U)
+#define SEC_ENG_SE_TRNG_0_DOUT_4_MSK    (((1U << SEC_ENG_SE_TRNG_0_DOUT_4_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_4_POS)
+#define SEC_ENG_SE_TRNG_0_DOUT_4_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_4_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_4_POS))
+
+/* 0x21C : se_trng_0_dout_5 */
+#define SEC_ENG_SE_TRNG_0_DOUT_5_OFFSET (0x21C)
+#define SEC_ENG_SE_TRNG_0_DOUT_5        SEC_ENG_SE_TRNG_0_DOUT_5
+#define SEC_ENG_SE_TRNG_0_DOUT_5_POS    (0U)
+#define SEC_ENG_SE_TRNG_0_DOUT_5_LEN    (32U)
+#define SEC_ENG_SE_TRNG_0_DOUT_5_MSK    (((1U << SEC_ENG_SE_TRNG_0_DOUT_5_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_5_POS)
+#define SEC_ENG_SE_TRNG_0_DOUT_5_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_5_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_5_POS))
+
+/* 0x220 : se_trng_0_dout_6 */
+#define SEC_ENG_SE_TRNG_0_DOUT_6_OFFSET (0x220)
+#define SEC_ENG_SE_TRNG_0_DOUT_6        SEC_ENG_SE_TRNG_0_DOUT_6
+#define SEC_ENG_SE_TRNG_0_DOUT_6_POS    (0U)
+#define SEC_ENG_SE_TRNG_0_DOUT_6_LEN    (32U)
+#define SEC_ENG_SE_TRNG_0_DOUT_6_MSK    (((1U << SEC_ENG_SE_TRNG_0_DOUT_6_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_6_POS)
+#define SEC_ENG_SE_TRNG_0_DOUT_6_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_6_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_6_POS))
+
+/* 0x224 : se_trng_0_dout_7 */
+#define SEC_ENG_SE_TRNG_0_DOUT_7_OFFSET (0x224)
+#define SEC_ENG_SE_TRNG_0_DOUT_7        SEC_ENG_SE_TRNG_0_DOUT_7
+#define SEC_ENG_SE_TRNG_0_DOUT_7_POS    (0U)
+#define SEC_ENG_SE_TRNG_0_DOUT_7_LEN    (32U)
+#define SEC_ENG_SE_TRNG_0_DOUT_7_MSK    (((1U << SEC_ENG_SE_TRNG_0_DOUT_7_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_7_POS)
+#define SEC_ENG_SE_TRNG_0_DOUT_7_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_7_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_7_POS))
+
+/* 0x228 : se_trng_0_test */
+#define SEC_ENG_SE_TRNG_0_TEST_OFFSET     (0x228)
+#define SEC_ENG_SE_TRNG_0_TEST_EN         SEC_ENG_SE_TRNG_0_TEST_EN
+#define SEC_ENG_SE_TRNG_0_TEST_EN_POS     (0U)
+#define SEC_ENG_SE_TRNG_0_TEST_EN_LEN     (1U)
+#define SEC_ENG_SE_TRNG_0_TEST_EN_MSK     (((1U << SEC_ENG_SE_TRNG_0_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_EN_POS)
+#define SEC_ENG_SE_TRNG_0_TEST_EN_UMSK    (~(((1U << SEC_ENG_SE_TRNG_0_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_EN_POS))
+#define SEC_ENG_SE_TRNG_0_CP_TEST_EN      SEC_ENG_SE_TRNG_0_CP_TEST_EN
+#define SEC_ENG_SE_TRNG_0_CP_TEST_EN_POS  (1U)
+#define SEC_ENG_SE_TRNG_0_CP_TEST_EN_LEN  (1U)
+#define SEC_ENG_SE_TRNG_0_CP_TEST_EN_MSK  (((1U << SEC_ENG_SE_TRNG_0_CP_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_TEST_EN_POS)
+#define SEC_ENG_SE_TRNG_0_CP_TEST_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_CP_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_TEST_EN_POS))
+#define SEC_ENG_SE_TRNG_0_CP_BYPASS       SEC_ENG_SE_TRNG_0_CP_BYPASS
+#define SEC_ENG_SE_TRNG_0_CP_BYPASS_POS   (2U)
+#define SEC_ENG_SE_TRNG_0_CP_BYPASS_LEN   (1U)
+#define SEC_ENG_SE_TRNG_0_CP_BYPASS_MSK   (((1U << SEC_ENG_SE_TRNG_0_CP_BYPASS_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_BYPASS_POS)
+#define SEC_ENG_SE_TRNG_0_CP_BYPASS_UMSK  (~(((1U << SEC_ENG_SE_TRNG_0_CP_BYPASS_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_BYPASS_POS))
+#define SEC_ENG_SE_TRNG_0_HT_DIS          SEC_ENG_SE_TRNG_0_HT_DIS
+#define SEC_ENG_SE_TRNG_0_HT_DIS_POS      (3U)
+#define SEC_ENG_SE_TRNG_0_HT_DIS_LEN      (1U)
+#define SEC_ENG_SE_TRNG_0_HT_DIS_MSK      (((1U << SEC_ENG_SE_TRNG_0_HT_DIS_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_DIS_POS)
+#define SEC_ENG_SE_TRNG_0_HT_DIS_UMSK     (~(((1U << SEC_ENG_SE_TRNG_0_HT_DIS_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_DIS_POS))
+#define SEC_ENG_SE_TRNG_0_HT_ALARM_N      SEC_ENG_SE_TRNG_0_HT_ALARM_N
+#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_POS  (4U)
+#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_LEN  (8U)
+#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_MSK  (((1U << SEC_ENG_SE_TRNG_0_HT_ALARM_N_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_ALARM_N_POS)
+#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_ALARM_N_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_ALARM_N_POS))
+
+/* 0x22C : se_trng_0_ctrl_1 */
+#define SEC_ENG_SE_TRNG_0_CTRL_1_OFFSET     (0x22C)
+#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB      SEC_ENG_SE_TRNG_0_RESEED_N_LSB
+#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_POS  (0U)
+#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_LEN  (32U)
+#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_MSK  (((1U << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_LEN) - 1) << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_POS)
+#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_LEN) - 1) << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_POS))
+
+/* 0x230 : se_trng_0_ctrl_2 */
+#define SEC_ENG_SE_TRNG_0_CTRL_2_OFFSET     (0x230)
+#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB      SEC_ENG_SE_TRNG_0_RESEED_N_MSB
+#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_POS  (0U)
+#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_LEN  (16U)
+#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_MSK  (((1U << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_LEN) - 1) << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_POS)
+#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_LEN) - 1) << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_POS))
+
+/* 0x234 : se_trng_0_ctrl_3 */
+#define SEC_ENG_SE_TRNG_0_CTRL_3_OFFSET (0x234)
+#define SEC_ENG_SE_TRNG_0_CP_RATIO      SEC_ENG_SE_TRNG_0_CP_RATIO
+#define SEC_ENG_SE_TRNG_0_CP_RATIO_POS  (0U)
+#define SEC_ENG_SE_TRNG_0_CP_RATIO_LEN  (8U)
+#define SEC_ENG_SE_TRNG_0_CP_RATIO_MSK  (((1U << SEC_ENG_SE_TRNG_0_CP_RATIO_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_RATIO_POS)
+#define SEC_ENG_SE_TRNG_0_CP_RATIO_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_CP_RATIO_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_RATIO_POS))
+#define SEC_ENG_SE_TRNG_0_HT_RCT_C      SEC_ENG_SE_TRNG_0_HT_RCT_C
+#define SEC_ENG_SE_TRNG_0_HT_RCT_C_POS  (8U)
+#define SEC_ENG_SE_TRNG_0_HT_RCT_C_LEN  (8U)
+#define SEC_ENG_SE_TRNG_0_HT_RCT_C_MSK  (((1U << SEC_ENG_SE_TRNG_0_HT_RCT_C_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_RCT_C_POS)
+#define SEC_ENG_SE_TRNG_0_HT_RCT_C_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_RCT_C_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_RCT_C_POS))
+#define SEC_ENG_SE_TRNG_0_HT_APT_C      SEC_ENG_SE_TRNG_0_HT_APT_C
+#define SEC_ENG_SE_TRNG_0_HT_APT_C_POS  (16U)
+#define SEC_ENG_SE_TRNG_0_HT_APT_C_LEN  (10U)
+#define SEC_ENG_SE_TRNG_0_HT_APT_C_MSK  (((1U << SEC_ENG_SE_TRNG_0_HT_APT_C_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_APT_C_POS)
+#define SEC_ENG_SE_TRNG_0_HT_APT_C_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_APT_C_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_APT_C_POS))
+#define SEC_ENG_SE_TRNG_0_HT_OD_EN      SEC_ENG_SE_TRNG_0_HT_OD_EN
+#define SEC_ENG_SE_TRNG_0_HT_OD_EN_POS  (26U)
+#define SEC_ENG_SE_TRNG_0_HT_OD_EN_LEN  (1U)
+#define SEC_ENG_SE_TRNG_0_HT_OD_EN_MSK  (((1U << SEC_ENG_SE_TRNG_0_HT_OD_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_OD_EN_POS)
+#define SEC_ENG_SE_TRNG_0_HT_OD_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_OD_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_OD_EN_POS))
+#define SEC_ENG_SE_TRNG_0_ROSC_EN       SEC_ENG_SE_TRNG_0_ROSC_EN
+#define SEC_ENG_SE_TRNG_0_ROSC_EN_POS   (31U)
+#define SEC_ENG_SE_TRNG_0_ROSC_EN_LEN   (1U)
+#define SEC_ENG_SE_TRNG_0_ROSC_EN_MSK   (((1U << SEC_ENG_SE_TRNG_0_ROSC_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_ROSC_EN_POS)
+#define SEC_ENG_SE_TRNG_0_ROSC_EN_UMSK  (~(((1U << SEC_ENG_SE_TRNG_0_ROSC_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_ROSC_EN_POS))
+
+/* 0x240 : se_trng_0_test_out_0 */
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_OFFSET (0x240)
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_0        SEC_ENG_SE_TRNG_0_TEST_OUT_0
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_POS    (0U)
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_LEN    (32U)
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_MSK    (((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_0_POS)
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_0_POS))
+
+/* 0x244 : se_trng_0_test_out_1 */
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_OFFSET (0x244)
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_1        SEC_ENG_SE_TRNG_0_TEST_OUT_1
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_POS    (0U)
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_LEN    (32U)
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_MSK    (((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_1_POS)
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_1_POS))
+
+/* 0x248 : se_trng_0_test_out_2 */
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_OFFSET (0x248)
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_2        SEC_ENG_SE_TRNG_0_TEST_OUT_2
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_POS    (0U)
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_LEN    (32U)
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_MSK    (((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_2_POS)
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_2_POS))
+
+/* 0x24C : se_trng_0_test_out_3 */
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_OFFSET (0x24C)
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_3        SEC_ENG_SE_TRNG_0_TEST_OUT_3
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_POS    (0U)
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_LEN    (32U)
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_MSK    (((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_3_POS)
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_3_POS))
+
+/* 0x2FC : se_trng_0_ctrl_prot */
+#define SEC_ENG_SE_TRNG_0_CTRL_PROT_OFFSET (0x2FC)
+#define SEC_ENG_SE_TRNG_PROT_EN            SEC_ENG_SE_TRNG_PROT_EN
+#define SEC_ENG_SE_TRNG_PROT_EN_POS        (0U)
+#define SEC_ENG_SE_TRNG_PROT_EN_LEN        (1U)
+#define SEC_ENG_SE_TRNG_PROT_EN_MSK        (((1U << SEC_ENG_SE_TRNG_PROT_EN_LEN) - 1) << SEC_ENG_SE_TRNG_PROT_EN_POS)
+#define SEC_ENG_SE_TRNG_PROT_EN_UMSK       (~(((1U << SEC_ENG_SE_TRNG_PROT_EN_LEN) - 1) << SEC_ENG_SE_TRNG_PROT_EN_POS))
+#define SEC_ENG_SE_TRNG_ID0_EN             SEC_ENG_SE_TRNG_ID0_EN
+#define SEC_ENG_SE_TRNG_ID0_EN_POS         (1U)
+#define SEC_ENG_SE_TRNG_ID0_EN_LEN         (1U)
+#define SEC_ENG_SE_TRNG_ID0_EN_MSK         (((1U << SEC_ENG_SE_TRNG_ID0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_POS)
+#define SEC_ENG_SE_TRNG_ID0_EN_UMSK        (~(((1U << SEC_ENG_SE_TRNG_ID0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_POS))
+#define SEC_ENG_SE_TRNG_ID1_EN             SEC_ENG_SE_TRNG_ID1_EN
+#define SEC_ENG_SE_TRNG_ID1_EN_POS         (2U)
+#define SEC_ENG_SE_TRNG_ID1_EN_LEN         (1U)
+#define SEC_ENG_SE_TRNG_ID1_EN_MSK         (((1U << SEC_ENG_SE_TRNG_ID1_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_POS)
+#define SEC_ENG_SE_TRNG_ID1_EN_UMSK        (~(((1U << SEC_ENG_SE_TRNG_ID1_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_POS))
+
+/* 0x300 : se_pka_0_ctrl_0 */
+#define SEC_ENG_SE_PKA_0_CTRL_0_OFFSET      (0x300)
+#define SEC_ENG_SE_PKA_0_DONE               SEC_ENG_SE_PKA_0_DONE
+#define SEC_ENG_SE_PKA_0_DONE_POS           (0U)
+#define SEC_ENG_SE_PKA_0_DONE_LEN           (1U)
+#define SEC_ENG_SE_PKA_0_DONE_MSK           (((1U << SEC_ENG_SE_PKA_0_DONE_LEN) - 1) << SEC_ENG_SE_PKA_0_DONE_POS)
+#define SEC_ENG_SE_PKA_0_DONE_UMSK          (~(((1U << SEC_ENG_SE_PKA_0_DONE_LEN) - 1) << SEC_ENG_SE_PKA_0_DONE_POS))
+#define SEC_ENG_SE_PKA_0_DONE_CLR_1T        SEC_ENG_SE_PKA_0_DONE_CLR_1T
+#define SEC_ENG_SE_PKA_0_DONE_CLR_1T_POS    (1U)
+#define SEC_ENG_SE_PKA_0_DONE_CLR_1T_LEN    (1U)
+#define SEC_ENG_SE_PKA_0_DONE_CLR_1T_MSK    (((1U << SEC_ENG_SE_PKA_0_DONE_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_DONE_CLR_1T_POS)
+#define SEC_ENG_SE_PKA_0_DONE_CLR_1T_UMSK   (~(((1U << SEC_ENG_SE_PKA_0_DONE_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_DONE_CLR_1T_POS))
+#define SEC_ENG_SE_PKA_0_BUSY               SEC_ENG_SE_PKA_0_BUSY
+#define SEC_ENG_SE_PKA_0_BUSY_POS           (2U)
+#define SEC_ENG_SE_PKA_0_BUSY_LEN           (1U)
+#define SEC_ENG_SE_PKA_0_BUSY_MSK           (((1U << SEC_ENG_SE_PKA_0_BUSY_LEN) - 1) << SEC_ENG_SE_PKA_0_BUSY_POS)
+#define SEC_ENG_SE_PKA_0_BUSY_UMSK          (~(((1U << SEC_ENG_SE_PKA_0_BUSY_LEN) - 1) << SEC_ENG_SE_PKA_0_BUSY_POS))
+#define SEC_ENG_SE_PKA_0_EN                 SEC_ENG_SE_PKA_0_EN
+#define SEC_ENG_SE_PKA_0_EN_POS             (3U)
+#define SEC_ENG_SE_PKA_0_EN_LEN             (1U)
+#define SEC_ENG_SE_PKA_0_EN_MSK             (((1U << SEC_ENG_SE_PKA_0_EN_LEN) - 1) << SEC_ENG_SE_PKA_0_EN_POS)
+#define SEC_ENG_SE_PKA_0_EN_UMSK            (~(((1U << SEC_ENG_SE_PKA_0_EN_LEN) - 1) << SEC_ENG_SE_PKA_0_EN_POS))
+#define SEC_ENG_SE_PKA_0_PROT_MD            SEC_ENG_SE_PKA_0_PROT_MD
+#define SEC_ENG_SE_PKA_0_PROT_MD_POS        (4U)
+#define SEC_ENG_SE_PKA_0_PROT_MD_LEN        (4U)
+#define SEC_ENG_SE_PKA_0_PROT_MD_MSK        (((1U << SEC_ENG_SE_PKA_0_PROT_MD_LEN) - 1) << SEC_ENG_SE_PKA_0_PROT_MD_POS)
+#define SEC_ENG_SE_PKA_0_PROT_MD_UMSK       (~(((1U << SEC_ENG_SE_PKA_0_PROT_MD_LEN) - 1) << SEC_ENG_SE_PKA_0_PROT_MD_POS))
+#define SEC_ENG_SE_PKA_0_INT                SEC_ENG_SE_PKA_0_INT
+#define SEC_ENG_SE_PKA_0_INT_POS            (8U)
+#define SEC_ENG_SE_PKA_0_INT_LEN            (1U)
+#define SEC_ENG_SE_PKA_0_INT_MSK            (((1U << SEC_ENG_SE_PKA_0_INT_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_POS)
+#define SEC_ENG_SE_PKA_0_INT_UMSK           (~(((1U << SEC_ENG_SE_PKA_0_INT_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_POS))
+#define SEC_ENG_SE_PKA_0_INT_CLR_1T         SEC_ENG_SE_PKA_0_INT_CLR_1T
+#define SEC_ENG_SE_PKA_0_INT_CLR_1T_POS     (9U)
+#define SEC_ENG_SE_PKA_0_INT_CLR_1T_LEN     (1U)
+#define SEC_ENG_SE_PKA_0_INT_CLR_1T_MSK     (((1U << SEC_ENG_SE_PKA_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_CLR_1T_POS)
+#define SEC_ENG_SE_PKA_0_INT_CLR_1T_UMSK    (~(((1U << SEC_ENG_SE_PKA_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_CLR_1T_POS))
+#define SEC_ENG_SE_PKA_0_INT_SET            SEC_ENG_SE_PKA_0_INT_SET
+#define SEC_ENG_SE_PKA_0_INT_SET_POS        (10U)
+#define SEC_ENG_SE_PKA_0_INT_SET_LEN        (1U)
+#define SEC_ENG_SE_PKA_0_INT_SET_MSK        (((1U << SEC_ENG_SE_PKA_0_INT_SET_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_SET_POS)
+#define SEC_ENG_SE_PKA_0_INT_SET_UMSK       (~(((1U << SEC_ENG_SE_PKA_0_INT_SET_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_SET_POS))
+#define SEC_ENG_SE_PKA_0_INT_MASK           SEC_ENG_SE_PKA_0_INT_MASK
+#define SEC_ENG_SE_PKA_0_INT_MASK_POS       (11U)
+#define SEC_ENG_SE_PKA_0_INT_MASK_LEN       (1U)
+#define SEC_ENG_SE_PKA_0_INT_MASK_MSK       (((1U << SEC_ENG_SE_PKA_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_MASK_POS)
+#define SEC_ENG_SE_PKA_0_INT_MASK_UMSK      (~(((1U << SEC_ENG_SE_PKA_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_MASK_POS))
+#define SEC_ENG_SE_PKA_0_ENDIAN             SEC_ENG_SE_PKA_0_ENDIAN
+#define SEC_ENG_SE_PKA_0_ENDIAN_POS         (12U)
+#define SEC_ENG_SE_PKA_0_ENDIAN_LEN         (1U)
+#define SEC_ENG_SE_PKA_0_ENDIAN_MSK         (((1U << SEC_ENG_SE_PKA_0_ENDIAN_LEN) - 1) << SEC_ENG_SE_PKA_0_ENDIAN_POS)
+#define SEC_ENG_SE_PKA_0_ENDIAN_UMSK        (~(((1U << SEC_ENG_SE_PKA_0_ENDIAN_LEN) - 1) << SEC_ENG_SE_PKA_0_ENDIAN_POS))
+#define SEC_ENG_SE_PKA_0_RAM_CLR_MD         SEC_ENG_SE_PKA_0_RAM_CLR_MD
+#define SEC_ENG_SE_PKA_0_RAM_CLR_MD_POS     (13U)
+#define SEC_ENG_SE_PKA_0_RAM_CLR_MD_LEN     (1U)
+#define SEC_ENG_SE_PKA_0_RAM_CLR_MD_MSK     (((1U << SEC_ENG_SE_PKA_0_RAM_CLR_MD_LEN) - 1) << SEC_ENG_SE_PKA_0_RAM_CLR_MD_POS)
+#define SEC_ENG_SE_PKA_0_RAM_CLR_MD_UMSK    (~(((1U << SEC_ENG_SE_PKA_0_RAM_CLR_MD_LEN) - 1) << SEC_ENG_SE_PKA_0_RAM_CLR_MD_POS))
+#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T      SEC_ENG_SE_PKA_0_STATUS_CLR_1T
+#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T_POS  (15U)
+#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T_LEN  (1U)
+#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T_MSK  (((1U << SEC_ENG_SE_PKA_0_STATUS_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_STATUS_CLR_1T_POS)
+#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_PKA_0_STATUS_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_STATUS_CLR_1T_POS))
+#define SEC_ENG_SE_PKA_0_STATUS             SEC_ENG_SE_PKA_0_STATUS
+#define SEC_ENG_SE_PKA_0_STATUS_POS         (16U)
+#define SEC_ENG_SE_PKA_0_STATUS_LEN         (16U)
+#define SEC_ENG_SE_PKA_0_STATUS_MSK         (((1U << SEC_ENG_SE_PKA_0_STATUS_LEN) - 1) << SEC_ENG_SE_PKA_0_STATUS_POS)
+#define SEC_ENG_SE_PKA_0_STATUS_UMSK        (~(((1U << SEC_ENG_SE_PKA_0_STATUS_LEN) - 1) << SEC_ENG_SE_PKA_0_STATUS_POS))
+
+/* 0x30C : se_pka_0_seed */
+#define SEC_ENG_SE_PKA_0_SEED_OFFSET (0x30C)
+#define SEC_ENG_SE_PKA_0_SEED        SEC_ENG_SE_PKA_0_SEED
+#define SEC_ENG_SE_PKA_0_SEED_POS    (0U)
+#define SEC_ENG_SE_PKA_0_SEED_LEN    (32U)
+#define SEC_ENG_SE_PKA_0_SEED_MSK    (((1U << SEC_ENG_SE_PKA_0_SEED_LEN) - 1) << SEC_ENG_SE_PKA_0_SEED_POS)
+#define SEC_ENG_SE_PKA_0_SEED_UMSK   (~(((1U << SEC_ENG_SE_PKA_0_SEED_LEN) - 1) << SEC_ENG_SE_PKA_0_SEED_POS))
+
+/* 0x310 : se_pka_0_ctrl_1 */
+#define SEC_ENG_SE_PKA_0_CTRL_1_OFFSET (0x310)
+#define SEC_ENG_SE_PKA_0_HBURST        SEC_ENG_SE_PKA_0_HBURST
+#define SEC_ENG_SE_PKA_0_HBURST_POS    (0U)
+#define SEC_ENG_SE_PKA_0_HBURST_LEN    (3U)
+#define SEC_ENG_SE_PKA_0_HBURST_MSK    (((1U << SEC_ENG_SE_PKA_0_HBURST_LEN) - 1) << SEC_ENG_SE_PKA_0_HBURST_POS)
+#define SEC_ENG_SE_PKA_0_HBURST_UMSK   (~(((1U << SEC_ENG_SE_PKA_0_HBURST_LEN) - 1) << SEC_ENG_SE_PKA_0_HBURST_POS))
+#define SEC_ENG_SE_PKA_0_HBYPASS       SEC_ENG_SE_PKA_0_HBYPASS
+#define SEC_ENG_SE_PKA_0_HBYPASS_POS   (3U)
+#define SEC_ENG_SE_PKA_0_HBYPASS_LEN   (1U)
+#define SEC_ENG_SE_PKA_0_HBYPASS_MSK   (((1U << SEC_ENG_SE_PKA_0_HBYPASS_LEN) - 1) << SEC_ENG_SE_PKA_0_HBYPASS_POS)
+#define SEC_ENG_SE_PKA_0_HBYPASS_UMSK  (~(((1U << SEC_ENG_SE_PKA_0_HBYPASS_LEN) - 1) << SEC_ENG_SE_PKA_0_HBYPASS_POS))
+
+/* 0x340 : se_pka_0_rw */
+#define SEC_ENG_SE_PKA_0_RW_OFFSET (0x340)
+
+/* 0x360 : se_pka_0_rw_burst */
+#define SEC_ENG_SE_PKA_0_RW_BURST_OFFSET (0x360)
+
+/* 0x3FC : se_pka_0_ctrl_prot */
+#define SEC_ENG_SE_PKA_0_CTRL_PROT_OFFSET (0x3FC)
+#define SEC_ENG_SE_PKA_PROT_EN            SEC_ENG_SE_PKA_PROT_EN
+#define SEC_ENG_SE_PKA_PROT_EN_POS        (0U)
+#define SEC_ENG_SE_PKA_PROT_EN_LEN        (1U)
+#define SEC_ENG_SE_PKA_PROT_EN_MSK        (((1U << SEC_ENG_SE_PKA_PROT_EN_LEN) - 1) << SEC_ENG_SE_PKA_PROT_EN_POS)
+#define SEC_ENG_SE_PKA_PROT_EN_UMSK       (~(((1U << SEC_ENG_SE_PKA_PROT_EN_LEN) - 1) << SEC_ENG_SE_PKA_PROT_EN_POS))
+#define SEC_ENG_SE_PKA_ID0_EN             SEC_ENG_SE_PKA_ID0_EN
+#define SEC_ENG_SE_PKA_ID0_EN_POS         (1U)
+#define SEC_ENG_SE_PKA_ID0_EN_LEN         (1U)
+#define SEC_ENG_SE_PKA_ID0_EN_MSK         (((1U << SEC_ENG_SE_PKA_ID0_EN_LEN) - 1) << SEC_ENG_SE_PKA_ID0_EN_POS)
+#define SEC_ENG_SE_PKA_ID0_EN_UMSK        (~(((1U << SEC_ENG_SE_PKA_ID0_EN_LEN) - 1) << SEC_ENG_SE_PKA_ID0_EN_POS))
+#define SEC_ENG_SE_PKA_ID1_EN             SEC_ENG_SE_PKA_ID1_EN
+#define SEC_ENG_SE_PKA_ID1_EN_POS         (2U)
+#define SEC_ENG_SE_PKA_ID1_EN_LEN         (1U)
+#define SEC_ENG_SE_PKA_ID1_EN_MSK         (((1U << SEC_ENG_SE_PKA_ID1_EN_LEN) - 1) << SEC_ENG_SE_PKA_ID1_EN_POS)
+#define SEC_ENG_SE_PKA_ID1_EN_UMSK        (~(((1U << SEC_ENG_SE_PKA_ID1_EN_LEN) - 1) << SEC_ENG_SE_PKA_ID1_EN_POS))
+
+/* 0x400 : se_cdet_0_ctrl_0 */
+#define SEC_ENG_SE_CDET_0_CTRL_0_OFFSET   (0x400)
+#define SEC_ENG_SE_CDET_0_EN              SEC_ENG_SE_CDET_0_EN
+#define SEC_ENG_SE_CDET_0_EN_POS          (0U)
+#define SEC_ENG_SE_CDET_0_EN_LEN          (1U)
+#define SEC_ENG_SE_CDET_0_EN_MSK          (((1U << SEC_ENG_SE_CDET_0_EN_LEN) - 1) << SEC_ENG_SE_CDET_0_EN_POS)
+#define SEC_ENG_SE_CDET_0_EN_UMSK         (~(((1U << SEC_ENG_SE_CDET_0_EN_LEN) - 1) << SEC_ENG_SE_CDET_0_EN_POS))
+#define SEC_ENG_SE_CDET_0_ERROR           SEC_ENG_SE_CDET_0_ERROR
+#define SEC_ENG_SE_CDET_0_ERROR_POS       (1U)
+#define SEC_ENG_SE_CDET_0_ERROR_LEN       (1U)
+#define SEC_ENG_SE_CDET_0_ERROR_MSK       (((1U << SEC_ENG_SE_CDET_0_ERROR_LEN) - 1) << SEC_ENG_SE_CDET_0_ERROR_POS)
+#define SEC_ENG_SE_CDET_0_ERROR_UMSK      (~(((1U << SEC_ENG_SE_CDET_0_ERROR_LEN) - 1) << SEC_ENG_SE_CDET_0_ERROR_POS))
+#define SEC_ENG_SE_CDET_0_STATUS          SEC_ENG_SE_CDET_0_STATUS
+#define SEC_ENG_SE_CDET_0_STATUS_POS      (2U)
+#define SEC_ENG_SE_CDET_0_STATUS_LEN      (14U)
+#define SEC_ENG_SE_CDET_0_STATUS_MSK      (((1U << SEC_ENG_SE_CDET_0_STATUS_LEN) - 1) << SEC_ENG_SE_CDET_0_STATUS_POS)
+#define SEC_ENG_SE_CDET_0_STATUS_UMSK     (~(((1U << SEC_ENG_SE_CDET_0_STATUS_LEN) - 1) << SEC_ENG_SE_CDET_0_STATUS_POS))
+#define SEC_ENG_SE_CDET_0_G_LOOP_MAX      SEC_ENG_SE_CDET_0_G_LOOP_MAX
+#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_POS  (16U)
+#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_LEN  (8U)
+#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_MSK  (((1U << SEC_ENG_SE_CDET_0_G_LOOP_MAX_LEN) - 1) << SEC_ENG_SE_CDET_0_G_LOOP_MAX_POS)
+#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_UMSK (~(((1U << SEC_ENG_SE_CDET_0_G_LOOP_MAX_LEN) - 1) << SEC_ENG_SE_CDET_0_G_LOOP_MAX_POS))
+#define SEC_ENG_SE_CDET_0_G_LOOP_MIN      SEC_ENG_SE_CDET_0_G_LOOP_MIN
+#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_POS  (24U)
+#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_LEN  (8U)
+#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_MSK  (((1U << SEC_ENG_SE_CDET_0_G_LOOP_MIN_LEN) - 1) << SEC_ENG_SE_CDET_0_G_LOOP_MIN_POS)
+#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_UMSK (~(((1U << SEC_ENG_SE_CDET_0_G_LOOP_MIN_LEN) - 1) << SEC_ENG_SE_CDET_0_G_LOOP_MIN_POS))
+
+/* 0x404 : se_cdet_0_ctrl_1 */
+#define SEC_ENG_SE_CDET_0_CTRL_1_OFFSET (0x404)
+#define SEC_ENG_SE_CDET_0_T_LOOP_N      SEC_ENG_SE_CDET_0_T_LOOP_N
+#define SEC_ENG_SE_CDET_0_T_LOOP_N_POS  (0U)
+#define SEC_ENG_SE_CDET_0_T_LOOP_N_LEN  (8U)
+#define SEC_ENG_SE_CDET_0_T_LOOP_N_MSK  (((1U << SEC_ENG_SE_CDET_0_T_LOOP_N_LEN) - 1) << SEC_ENG_SE_CDET_0_T_LOOP_N_POS)
+#define SEC_ENG_SE_CDET_0_T_LOOP_N_UMSK (~(((1U << SEC_ENG_SE_CDET_0_T_LOOP_N_LEN) - 1) << SEC_ENG_SE_CDET_0_T_LOOP_N_POS))
+#define SEC_ENG_SE_CDET_0_T_DLY_N       SEC_ENG_SE_CDET_0_T_DLY_N
+#define SEC_ENG_SE_CDET_0_T_DLY_N_POS   (8U)
+#define SEC_ENG_SE_CDET_0_T_DLY_N_LEN   (8U)
+#define SEC_ENG_SE_CDET_0_T_DLY_N_MSK   (((1U << SEC_ENG_SE_CDET_0_T_DLY_N_LEN) - 1) << SEC_ENG_SE_CDET_0_T_DLY_N_POS)
+#define SEC_ENG_SE_CDET_0_T_DLY_N_UMSK  (~(((1U << SEC_ENG_SE_CDET_0_T_DLY_N_LEN) - 1) << SEC_ENG_SE_CDET_0_T_DLY_N_POS))
+#define SEC_ENG_SE_CDET_0_G_SLP_N       SEC_ENG_SE_CDET_0_G_SLP_N
+#define SEC_ENG_SE_CDET_0_G_SLP_N_POS   (16U)
+#define SEC_ENG_SE_CDET_0_G_SLP_N_LEN   (8U)
+#define SEC_ENG_SE_CDET_0_G_SLP_N_MSK   (((1U << SEC_ENG_SE_CDET_0_G_SLP_N_LEN) - 1) << SEC_ENG_SE_CDET_0_G_SLP_N_POS)
+#define SEC_ENG_SE_CDET_0_G_SLP_N_UMSK  (~(((1U << SEC_ENG_SE_CDET_0_G_SLP_N_LEN) - 1) << SEC_ENG_SE_CDET_0_G_SLP_N_POS))
+
+/* 0x4FC : se_cdet_0_ctrl_prot */
+#define SEC_ENG_SE_CDET_0_CTRL_PROT_OFFSET (0x4FC)
+#define SEC_ENG_SE_CDET_PROT_EN            SEC_ENG_SE_CDET_PROT_EN
+#define SEC_ENG_SE_CDET_PROT_EN_POS        (0U)
+#define SEC_ENG_SE_CDET_PROT_EN_LEN        (1U)
+#define SEC_ENG_SE_CDET_PROT_EN_MSK        (((1U << SEC_ENG_SE_CDET_PROT_EN_LEN) - 1) << SEC_ENG_SE_CDET_PROT_EN_POS)
+#define SEC_ENG_SE_CDET_PROT_EN_UMSK       (~(((1U << SEC_ENG_SE_CDET_PROT_EN_LEN) - 1) << SEC_ENG_SE_CDET_PROT_EN_POS))
+#define SEC_ENG_SE_CDET_ID0_EN             SEC_ENG_SE_CDET_ID0_EN
+#define SEC_ENG_SE_CDET_ID0_EN_POS         (1U)
+#define SEC_ENG_SE_CDET_ID0_EN_LEN         (1U)
+#define SEC_ENG_SE_CDET_ID0_EN_MSK         (((1U << SEC_ENG_SE_CDET_ID0_EN_LEN) - 1) << SEC_ENG_SE_CDET_ID0_EN_POS)
+#define SEC_ENG_SE_CDET_ID0_EN_UMSK        (~(((1U << SEC_ENG_SE_CDET_ID0_EN_LEN) - 1) << SEC_ENG_SE_CDET_ID0_EN_POS))
+#define SEC_ENG_SE_CDET_ID1_EN             SEC_ENG_SE_CDET_ID1_EN
+#define SEC_ENG_SE_CDET_ID1_EN_POS         (2U)
+#define SEC_ENG_SE_CDET_ID1_EN_LEN         (1U)
+#define SEC_ENG_SE_CDET_ID1_EN_MSK         (((1U << SEC_ENG_SE_CDET_ID1_EN_LEN) - 1) << SEC_ENG_SE_CDET_ID1_EN_POS)
+#define SEC_ENG_SE_CDET_ID1_EN_UMSK        (~(((1U << SEC_ENG_SE_CDET_ID1_EN_LEN) - 1) << SEC_ENG_SE_CDET_ID1_EN_POS))
+
+/* 0x500 : se_gmac_0_ctrl_0 */
+#define SEC_ENG_SE_GMAC_0_CTRL_0_OFFSET   (0x500)
+#define SEC_ENG_SE_GMAC_0_BUSY            SEC_ENG_SE_GMAC_0_BUSY
+#define SEC_ENG_SE_GMAC_0_BUSY_POS        (0U)
+#define SEC_ENG_SE_GMAC_0_BUSY_LEN        (1U)
+#define SEC_ENG_SE_GMAC_0_BUSY_MSK        (((1U << SEC_ENG_SE_GMAC_0_BUSY_LEN) - 1) << SEC_ENG_SE_GMAC_0_BUSY_POS)
+#define SEC_ENG_SE_GMAC_0_BUSY_UMSK       (~(((1U << SEC_ENG_SE_GMAC_0_BUSY_LEN) - 1) << SEC_ENG_SE_GMAC_0_BUSY_POS))
+#define SEC_ENG_SE_GMAC_0_TRIG_1T         SEC_ENG_SE_GMAC_0_TRIG_1T
+#define SEC_ENG_SE_GMAC_0_TRIG_1T_POS     (1U)
+#define SEC_ENG_SE_GMAC_0_TRIG_1T_LEN     (1U)
+#define SEC_ENG_SE_GMAC_0_TRIG_1T_MSK     (((1U << SEC_ENG_SE_GMAC_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_TRIG_1T_POS)
+#define SEC_ENG_SE_GMAC_0_TRIG_1T_UMSK    (~(((1U << SEC_ENG_SE_GMAC_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_TRIG_1T_POS))
+#define SEC_ENG_SE_GMAC_0_EN              SEC_ENG_SE_GMAC_0_EN
+#define SEC_ENG_SE_GMAC_0_EN_POS          (2U)
+#define SEC_ENG_SE_GMAC_0_EN_LEN          (1U)
+#define SEC_ENG_SE_GMAC_0_EN_MSK          (((1U << SEC_ENG_SE_GMAC_0_EN_LEN) - 1) << SEC_ENG_SE_GMAC_0_EN_POS)
+#define SEC_ENG_SE_GMAC_0_EN_UMSK         (~(((1U << SEC_ENG_SE_GMAC_0_EN_LEN) - 1) << SEC_ENG_SE_GMAC_0_EN_POS))
+#define SEC_ENG_SE_GMAC_0_INT             SEC_ENG_SE_GMAC_0_INT
+#define SEC_ENG_SE_GMAC_0_INT_POS         (8U)
+#define SEC_ENG_SE_GMAC_0_INT_LEN         (1U)
+#define SEC_ENG_SE_GMAC_0_INT_MSK         (((1U << SEC_ENG_SE_GMAC_0_INT_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_POS)
+#define SEC_ENG_SE_GMAC_0_INT_UMSK        (~(((1U << SEC_ENG_SE_GMAC_0_INT_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_POS))
+#define SEC_ENG_SE_GMAC_0_INT_CLR_1T      SEC_ENG_SE_GMAC_0_INT_CLR_1T
+#define SEC_ENG_SE_GMAC_0_INT_CLR_1T_POS  (9U)
+#define SEC_ENG_SE_GMAC_0_INT_CLR_1T_LEN  (1U)
+#define SEC_ENG_SE_GMAC_0_INT_CLR_1T_MSK  (((1U << SEC_ENG_SE_GMAC_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_CLR_1T_POS)
+#define SEC_ENG_SE_GMAC_0_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_CLR_1T_POS))
+#define SEC_ENG_SE_GMAC_0_INT_SET_1T      SEC_ENG_SE_GMAC_0_INT_SET_1T
+#define SEC_ENG_SE_GMAC_0_INT_SET_1T_POS  (10U)
+#define SEC_ENG_SE_GMAC_0_INT_SET_1T_LEN  (1U)
+#define SEC_ENG_SE_GMAC_0_INT_SET_1T_MSK  (((1U << SEC_ENG_SE_GMAC_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_SET_1T_POS)
+#define SEC_ENG_SE_GMAC_0_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_SET_1T_POS))
+#define SEC_ENG_SE_GMAC_0_INT_MASK        SEC_ENG_SE_GMAC_0_INT_MASK
+#define SEC_ENG_SE_GMAC_0_INT_MASK_POS    (11U)
+#define SEC_ENG_SE_GMAC_0_INT_MASK_LEN    (1U)
+#define SEC_ENG_SE_GMAC_0_INT_MASK_MSK    (((1U << SEC_ENG_SE_GMAC_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_MASK_POS)
+#define SEC_ENG_SE_GMAC_0_INT_MASK_UMSK   (~(((1U << SEC_ENG_SE_GMAC_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_MASK_POS))
+#define SEC_ENG_SE_GMAC_0_T_ENDIAN        SEC_ENG_SE_GMAC_0_T_ENDIAN
+#define SEC_ENG_SE_GMAC_0_T_ENDIAN_POS    (12U)
+#define SEC_ENG_SE_GMAC_0_T_ENDIAN_LEN    (1U)
+#define SEC_ENG_SE_GMAC_0_T_ENDIAN_MSK    (((1U << SEC_ENG_SE_GMAC_0_T_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_T_ENDIAN_POS)
+#define SEC_ENG_SE_GMAC_0_T_ENDIAN_UMSK   (~(((1U << SEC_ENG_SE_GMAC_0_T_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_T_ENDIAN_POS))
+#define SEC_ENG_SE_GMAC_0_H_ENDIAN        SEC_ENG_SE_GMAC_0_H_ENDIAN
+#define SEC_ENG_SE_GMAC_0_H_ENDIAN_POS    (13U)
+#define SEC_ENG_SE_GMAC_0_H_ENDIAN_LEN    (1U)
+#define SEC_ENG_SE_GMAC_0_H_ENDIAN_MSK    (((1U << SEC_ENG_SE_GMAC_0_H_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_H_ENDIAN_POS)
+#define SEC_ENG_SE_GMAC_0_H_ENDIAN_UMSK   (~(((1U << SEC_ENG_SE_GMAC_0_H_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_H_ENDIAN_POS))
+#define SEC_ENG_SE_GMAC_0_X_ENDIAN        SEC_ENG_SE_GMAC_0_X_ENDIAN
+#define SEC_ENG_SE_GMAC_0_X_ENDIAN_POS    (14U)
+#define SEC_ENG_SE_GMAC_0_X_ENDIAN_LEN    (1U)
+#define SEC_ENG_SE_GMAC_0_X_ENDIAN_MSK    (((1U << SEC_ENG_SE_GMAC_0_X_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_X_ENDIAN_POS)
+#define SEC_ENG_SE_GMAC_0_X_ENDIAN_UMSK   (~(((1U << SEC_ENG_SE_GMAC_0_X_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_X_ENDIAN_POS))
+
+/* 0x504 : se_gmac_0_lca */
+#define SEC_ENG_SE_GMAC_0_LCA_OFFSET (0x504)
+#define SEC_ENG_SE_GMAC_0_LCA        SEC_ENG_SE_GMAC_0_LCA
+#define SEC_ENG_SE_GMAC_0_LCA_POS    (0U)
+#define SEC_ENG_SE_GMAC_0_LCA_LEN    (32U)
+#define SEC_ENG_SE_GMAC_0_LCA_MSK    (((1U << SEC_ENG_SE_GMAC_0_LCA_LEN) - 1) << SEC_ENG_SE_GMAC_0_LCA_POS)
+#define SEC_ENG_SE_GMAC_0_LCA_UMSK   (~(((1U << SEC_ENG_SE_GMAC_0_LCA_LEN) - 1) << SEC_ENG_SE_GMAC_0_LCA_POS))
+
+/* 0x508 : se_gmac_0_status */
+#define SEC_ENG_SE_GMAC_0_STATUS_OFFSET (0x508)
+#define SEC_ENG_SE_GMAC_0_STATUS        SEC_ENG_SE_GMAC_0_STATUS
+#define SEC_ENG_SE_GMAC_0_STATUS_POS    (0U)
+#define SEC_ENG_SE_GMAC_0_STATUS_LEN    (32U)
+#define SEC_ENG_SE_GMAC_0_STATUS_MSK    (((1U << SEC_ENG_SE_GMAC_0_STATUS_LEN) - 1) << SEC_ENG_SE_GMAC_0_STATUS_POS)
+#define SEC_ENG_SE_GMAC_0_STATUS_UMSK   (~(((1U << SEC_ENG_SE_GMAC_0_STATUS_LEN) - 1) << SEC_ENG_SE_GMAC_0_STATUS_POS))
+
+/* 0x5FC : se_gmac_0_ctrl_prot */
+#define SEC_ENG_SE_GMAC_0_CTRL_PROT_OFFSET (0x5FC)
+#define SEC_ENG_SE_GMAC_PROT_EN            SEC_ENG_SE_GMAC_PROT_EN
+#define SEC_ENG_SE_GMAC_PROT_EN_POS        (0U)
+#define SEC_ENG_SE_GMAC_PROT_EN_LEN        (1U)
+#define SEC_ENG_SE_GMAC_PROT_EN_MSK        (((1U << SEC_ENG_SE_GMAC_PROT_EN_LEN) - 1) << SEC_ENG_SE_GMAC_PROT_EN_POS)
+#define SEC_ENG_SE_GMAC_PROT_EN_UMSK       (~(((1U << SEC_ENG_SE_GMAC_PROT_EN_LEN) - 1) << SEC_ENG_SE_GMAC_PROT_EN_POS))
+#define SEC_ENG_SE_GMAC_ID0_EN             SEC_ENG_SE_GMAC_ID0_EN
+#define SEC_ENG_SE_GMAC_ID0_EN_POS         (1U)
+#define SEC_ENG_SE_GMAC_ID0_EN_LEN         (1U)
+#define SEC_ENG_SE_GMAC_ID0_EN_MSK         (((1U << SEC_ENG_SE_GMAC_ID0_EN_LEN) - 1) << SEC_ENG_SE_GMAC_ID0_EN_POS)
+#define SEC_ENG_SE_GMAC_ID0_EN_UMSK        (~(((1U << SEC_ENG_SE_GMAC_ID0_EN_LEN) - 1) << SEC_ENG_SE_GMAC_ID0_EN_POS))
+#define SEC_ENG_SE_GMAC_ID1_EN             SEC_ENG_SE_GMAC_ID1_EN
+#define SEC_ENG_SE_GMAC_ID1_EN_POS         (2U)
+#define SEC_ENG_SE_GMAC_ID1_EN_LEN         (1U)
+#define SEC_ENG_SE_GMAC_ID1_EN_MSK         (((1U << SEC_ENG_SE_GMAC_ID1_EN_LEN) - 1) << SEC_ENG_SE_GMAC_ID1_EN_POS)
+#define SEC_ENG_SE_GMAC_ID1_EN_UMSK        (~(((1U << SEC_ENG_SE_GMAC_ID1_EN_LEN) - 1) << SEC_ENG_SE_GMAC_ID1_EN_POS))
+
+/* 0xF00 : se_ctrl_prot_rd */
+#define SEC_ENG_SE_CTRL_PROT_RD_OFFSET  (0xF00)
+#define SEC_ENG_SE_SHA_PROT_EN_RD       SEC_ENG_SE_SHA_PROT_EN_RD
+#define SEC_ENG_SE_SHA_PROT_EN_RD_POS   (0U)
+#define SEC_ENG_SE_SHA_PROT_EN_RD_LEN   (1U)
+#define SEC_ENG_SE_SHA_PROT_EN_RD_MSK   (((1U << SEC_ENG_SE_SHA_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_PROT_EN_RD_POS)
+#define SEC_ENG_SE_SHA_PROT_EN_RD_UMSK  (~(((1U << SEC_ENG_SE_SHA_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_PROT_EN_RD_POS))
+#define SEC_ENG_SE_SHA_ID0_EN_RD        SEC_ENG_SE_SHA_ID0_EN_RD
+#define SEC_ENG_SE_SHA_ID0_EN_RD_POS    (1U)
+#define SEC_ENG_SE_SHA_ID0_EN_RD_LEN    (1U)
+#define SEC_ENG_SE_SHA_ID0_EN_RD_MSK    (((1U << SEC_ENG_SE_SHA_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_RD_POS)
+#define SEC_ENG_SE_SHA_ID0_EN_RD_UMSK   (~(((1U << SEC_ENG_SE_SHA_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_RD_POS))
+#define SEC_ENG_SE_SHA_ID1_EN_RD        SEC_ENG_SE_SHA_ID1_EN_RD
+#define SEC_ENG_SE_SHA_ID1_EN_RD_POS    (2U)
+#define SEC_ENG_SE_SHA_ID1_EN_RD_LEN    (1U)
+#define SEC_ENG_SE_SHA_ID1_EN_RD_MSK    (((1U << SEC_ENG_SE_SHA_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_RD_POS)
+#define SEC_ENG_SE_SHA_ID1_EN_RD_UMSK   (~(((1U << SEC_ENG_SE_SHA_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_RD_POS))
+#define SEC_ENG_SE_AES_PROT_EN_RD       SEC_ENG_SE_AES_PROT_EN_RD
+#define SEC_ENG_SE_AES_PROT_EN_RD_POS   (4U)
+#define SEC_ENG_SE_AES_PROT_EN_RD_LEN   (1U)
+#define SEC_ENG_SE_AES_PROT_EN_RD_MSK   (((1U << SEC_ENG_SE_AES_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_PROT_EN_RD_POS)
+#define SEC_ENG_SE_AES_PROT_EN_RD_UMSK  (~(((1U << SEC_ENG_SE_AES_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_PROT_EN_RD_POS))
+#define SEC_ENG_SE_AES_ID0_EN_RD        SEC_ENG_SE_AES_ID0_EN_RD
+#define SEC_ENG_SE_AES_ID0_EN_RD_POS    (5U)
+#define SEC_ENG_SE_AES_ID0_EN_RD_LEN    (1U)
+#define SEC_ENG_SE_AES_ID0_EN_RD_MSK    (((1U << SEC_ENG_SE_AES_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_RD_POS)
+#define SEC_ENG_SE_AES_ID0_EN_RD_UMSK   (~(((1U << SEC_ENG_SE_AES_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_RD_POS))
+#define SEC_ENG_SE_AES_ID1_EN_RD        SEC_ENG_SE_AES_ID1_EN_RD
+#define SEC_ENG_SE_AES_ID1_EN_RD_POS    (6U)
+#define SEC_ENG_SE_AES_ID1_EN_RD_LEN    (1U)
+#define SEC_ENG_SE_AES_ID1_EN_RD_MSK    (((1U << SEC_ENG_SE_AES_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_RD_POS)
+#define SEC_ENG_SE_AES_ID1_EN_RD_UMSK   (~(((1U << SEC_ENG_SE_AES_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_RD_POS))
+#define SEC_ENG_SE_TRNG_PROT_EN_RD      SEC_ENG_SE_TRNG_PROT_EN_RD
+#define SEC_ENG_SE_TRNG_PROT_EN_RD_POS  (8U)
+#define SEC_ENG_SE_TRNG_PROT_EN_RD_LEN  (1U)
+#define SEC_ENG_SE_TRNG_PROT_EN_RD_MSK  (((1U << SEC_ENG_SE_TRNG_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_PROT_EN_RD_POS)
+#define SEC_ENG_SE_TRNG_PROT_EN_RD_UMSK (~(((1U << SEC_ENG_SE_TRNG_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_PROT_EN_RD_POS))
+#define SEC_ENG_SE_TRNG_ID0_EN_RD       SEC_ENG_SE_TRNG_ID0_EN_RD
+#define SEC_ENG_SE_TRNG_ID0_EN_RD_POS   (9U)
+#define SEC_ENG_SE_TRNG_ID0_EN_RD_LEN   (1U)
+#define SEC_ENG_SE_TRNG_ID0_EN_RD_MSK   (((1U << SEC_ENG_SE_TRNG_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_RD_POS)
+#define SEC_ENG_SE_TRNG_ID0_EN_RD_UMSK  (~(((1U << SEC_ENG_SE_TRNG_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_RD_POS))
+#define SEC_ENG_SE_TRNG_ID1_EN_RD       SEC_ENG_SE_TRNG_ID1_EN_RD
+#define SEC_ENG_SE_TRNG_ID1_EN_RD_POS   (10U)
+#define SEC_ENG_SE_TRNG_ID1_EN_RD_LEN   (1U)
+#define SEC_ENG_SE_TRNG_ID1_EN_RD_MSK   (((1U << SEC_ENG_SE_TRNG_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_RD_POS)
+#define SEC_ENG_SE_TRNG_ID1_EN_RD_UMSK  (~(((1U << SEC_ENG_SE_TRNG_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_RD_POS))
+#define SEC_ENG_SE_PKA_PROT_EN_RD       SEC_ENG_SE_PKA_PROT_EN_RD
+#define SEC_ENG_SE_PKA_PROT_EN_RD_POS   (12U)
+#define SEC_ENG_SE_PKA_PROT_EN_RD_LEN   (1U)
+#define SEC_ENG_SE_PKA_PROT_EN_RD_MSK   (((1U << SEC_ENG_SE_PKA_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_PROT_EN_RD_POS)
+#define SEC_ENG_SE_PKA_PROT_EN_RD_UMSK  (~(((1U << SEC_ENG_SE_PKA_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_PROT_EN_RD_POS))
+#define SEC_ENG_SE_PKA_ID0_EN_RD        SEC_ENG_SE_PKA_ID0_EN_RD
+#define SEC_ENG_SE_PKA_ID0_EN_RD_POS    (13U)
+#define SEC_ENG_SE_PKA_ID0_EN_RD_LEN    (1U)
+#define SEC_ENG_SE_PKA_ID0_EN_RD_MSK    (((1U << SEC_ENG_SE_PKA_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_ID0_EN_RD_POS)
+#define SEC_ENG_SE_PKA_ID0_EN_RD_UMSK   (~(((1U << SEC_ENG_SE_PKA_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_ID0_EN_RD_POS))
+#define SEC_ENG_SE_PKA_ID1_EN_RD        SEC_ENG_SE_PKA_ID1_EN_RD
+#define SEC_ENG_SE_PKA_ID1_EN_RD_POS    (14U)
+#define SEC_ENG_SE_PKA_ID1_EN_RD_LEN    (1U)
+#define SEC_ENG_SE_PKA_ID1_EN_RD_MSK    (((1U << SEC_ENG_SE_PKA_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_ID1_EN_RD_POS)
+#define SEC_ENG_SE_PKA_ID1_EN_RD_UMSK   (~(((1U << SEC_ENG_SE_PKA_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_ID1_EN_RD_POS))
+#define SEC_ENG_SE_CDET_PROT_EN_RD      SEC_ENG_SE_CDET_PROT_EN_RD
+#define SEC_ENG_SE_CDET_PROT_EN_RD_POS  (16U)
+#define SEC_ENG_SE_CDET_PROT_EN_RD_LEN  (1U)
+#define SEC_ENG_SE_CDET_PROT_EN_RD_MSK  (((1U << SEC_ENG_SE_CDET_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_PROT_EN_RD_POS)
+#define SEC_ENG_SE_CDET_PROT_EN_RD_UMSK (~(((1U << SEC_ENG_SE_CDET_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_PROT_EN_RD_POS))
+#define SEC_ENG_SE_CDET_ID0_EN_RD       SEC_ENG_SE_CDET_ID0_EN_RD
+#define SEC_ENG_SE_CDET_ID0_EN_RD_POS   (17U)
+#define SEC_ENG_SE_CDET_ID0_EN_RD_LEN   (1U)
+#define SEC_ENG_SE_CDET_ID0_EN_RD_MSK   (((1U << SEC_ENG_SE_CDET_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_ID0_EN_RD_POS)
+#define SEC_ENG_SE_CDET_ID0_EN_RD_UMSK  (~(((1U << SEC_ENG_SE_CDET_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_ID0_EN_RD_POS))
+#define SEC_ENG_SE_CDET_ID1_EN_RD       SEC_ENG_SE_CDET_ID1_EN_RD
+#define SEC_ENG_SE_CDET_ID1_EN_RD_POS   (18U)
+#define SEC_ENG_SE_CDET_ID1_EN_RD_LEN   (1U)
+#define SEC_ENG_SE_CDET_ID1_EN_RD_MSK   (((1U << SEC_ENG_SE_CDET_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_ID1_EN_RD_POS)
+#define SEC_ENG_SE_CDET_ID1_EN_RD_UMSK  (~(((1U << SEC_ENG_SE_CDET_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_ID1_EN_RD_POS))
+#define SEC_ENG_SE_GMAC_PROT_EN_RD      SEC_ENG_SE_GMAC_PROT_EN_RD
+#define SEC_ENG_SE_GMAC_PROT_EN_RD_POS  (20U)
+#define SEC_ENG_SE_GMAC_PROT_EN_RD_LEN  (1U)
+#define SEC_ENG_SE_GMAC_PROT_EN_RD_MSK  (((1U << SEC_ENG_SE_GMAC_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_PROT_EN_RD_POS)
+#define SEC_ENG_SE_GMAC_PROT_EN_RD_UMSK (~(((1U << SEC_ENG_SE_GMAC_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_PROT_EN_RD_POS))
+#define SEC_ENG_SE_GMAC_ID0_EN_RD       SEC_ENG_SE_GMAC_ID0_EN_RD
+#define SEC_ENG_SE_GMAC_ID0_EN_RD_POS   (21U)
+#define SEC_ENG_SE_GMAC_ID0_EN_RD_LEN   (1U)
+#define SEC_ENG_SE_GMAC_ID0_EN_RD_MSK   (((1U << SEC_ENG_SE_GMAC_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_ID0_EN_RD_POS)
+#define SEC_ENG_SE_GMAC_ID0_EN_RD_UMSK  (~(((1U << SEC_ENG_SE_GMAC_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_ID0_EN_RD_POS))
+#define SEC_ENG_SE_GMAC_ID1_EN_RD       SEC_ENG_SE_GMAC_ID1_EN_RD
+#define SEC_ENG_SE_GMAC_ID1_EN_RD_POS   (22U)
+#define SEC_ENG_SE_GMAC_ID1_EN_RD_LEN   (1U)
+#define SEC_ENG_SE_GMAC_ID1_EN_RD_MSK   (((1U << SEC_ENG_SE_GMAC_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_ID1_EN_RD_POS)
+#define SEC_ENG_SE_GMAC_ID1_EN_RD_UMSK  (~(((1U << SEC_ENG_SE_GMAC_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_ID1_EN_RD_POS))
+#define SEC_ENG_SE_DBG_DIS              SEC_ENG_SE_DBG_DIS
+#define SEC_ENG_SE_DBG_DIS_POS          (31U)
+#define SEC_ENG_SE_DBG_DIS_LEN          (1U)
+#define SEC_ENG_SE_DBG_DIS_MSK          (((1U << SEC_ENG_SE_DBG_DIS_LEN) - 1) << SEC_ENG_SE_DBG_DIS_POS)
+#define SEC_ENG_SE_DBG_DIS_UMSK         (~(((1U << SEC_ENG_SE_DBG_DIS_LEN) - 1) << SEC_ENG_SE_DBG_DIS_POS))
+
+/* 0xF04 : se_ctrl_reserved_0 */
+#define SEC_ENG_SE_CTRL_RESERVED_0_OFFSET (0xF04)
+#define SEC_ENG_SE_CTRL_RESERVED_0        SEC_ENG_SE_CTRL_RESERVED_0
+#define SEC_ENG_SE_CTRL_RESERVED_0_POS    (0U)
+#define SEC_ENG_SE_CTRL_RESERVED_0_LEN    (32U)
+#define SEC_ENG_SE_CTRL_RESERVED_0_MSK    (((1U << SEC_ENG_SE_CTRL_RESERVED_0_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_0_POS)
+#define SEC_ENG_SE_CTRL_RESERVED_0_UMSK   (~(((1U << SEC_ENG_SE_CTRL_RESERVED_0_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_0_POS))
+
+/* 0xF08 : se_ctrl_reserved_1 */
+#define SEC_ENG_SE_CTRL_RESERVED_1_OFFSET (0xF08)
+#define SEC_ENG_SE_CTRL_RESERVED_1        SEC_ENG_SE_CTRL_RESERVED_1
+#define SEC_ENG_SE_CTRL_RESERVED_1_POS    (0U)
+#define SEC_ENG_SE_CTRL_RESERVED_1_LEN    (32U)
+#define SEC_ENG_SE_CTRL_RESERVED_1_MSK    (((1U << SEC_ENG_SE_CTRL_RESERVED_1_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_1_POS)
+#define SEC_ENG_SE_CTRL_RESERVED_1_UMSK   (~(((1U << SEC_ENG_SE_CTRL_RESERVED_1_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_1_POS))
+
+/* 0xF0C : se_ctrl_reserved_2 */
+#define SEC_ENG_SE_CTRL_RESERVED_2_OFFSET (0xF0C)
+#define SEC_ENG_SE_CTRL_RESERVED_2        SEC_ENG_SE_CTRL_RESERVED_2
+#define SEC_ENG_SE_CTRL_RESERVED_2_POS    (0U)
+#define SEC_ENG_SE_CTRL_RESERVED_2_LEN    (32U)
+#define SEC_ENG_SE_CTRL_RESERVED_2_MSK    (((1U << SEC_ENG_SE_CTRL_RESERVED_2_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_2_POS)
+#define SEC_ENG_SE_CTRL_RESERVED_2_UMSK   (~(((1U << SEC_ENG_SE_CTRL_RESERVED_2_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_2_POS))
+
+struct sec_eng_reg {
+    /* 0x0 : se_sha_0_ctrl */
+    union {
+        struct
+        {
+            uint32_t se_sha_0_busy       : 1;  /* [    0],          r,        0x0 */
+            uint32_t se_sha_0_trig_1t    : 1;  /* [    1],        w1p,        0x0 */
+            uint32_t se_sha_0_mode       : 3;  /* [ 4: 2],        r/w,        0x0 */
+            uint32_t se_sha_0_en         : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t se_sha_0_hash_sel   : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7          : 1;  /* [    7],       rsvd,        0x0 */
+            uint32_t se_sha_0_int        : 1;  /* [    8],          r,        0x0 */
+            uint32_t se_sha_0_int_clr_1t : 1;  /* [    9],        w1p,        0x0 */
+            uint32_t se_sha_0_int_set_1t : 1;  /* [   10],        w1p,        0x0 */
+            uint32_t se_sha_0_int_mask   : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t reserved_12_14      : 3;  /* [14:12],       rsvd,        0x0 */
+            uint32_t se_sha_0_link_mode  : 1;  /* [   15],        r/w,        0x0 */
+            uint32_t se_sha_0_msg_len    : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_0_ctrl;
+
+    /* 0x4 : se_sha_0_msa */
+    union {
+        struct
+        {
+            uint32_t se_sha_0_msa : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_0_msa;
+
+    /* 0x8 : se_sha_0_status */
+    union {
+        struct
+        {
+            uint32_t se_sha_0_status : 32; /* [31: 0],          r,       0x41 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_0_status;
+
+    /* 0xC : se_sha_0_endian */
+    union {
+        struct
+        {
+            uint32_t se_sha_0_dout_endian : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reserved_1_31        : 31; /* [31: 1],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_0_endian;
+
+    /* 0x10 : se_sha_0_hash_l_0 */
+    union {
+        struct
+        {
+            uint32_t se_sha_0_hash_l_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_0_hash_l_0;
+
+    /* 0x14 : se_sha_0_hash_l_1 */
+    union {
+        struct
+        {
+            uint32_t se_sha_0_hash_l_1 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_0_hash_l_1;
+
+    /* 0x18 : se_sha_0_hash_l_2 */
+    union {
+        struct
+        {
+            uint32_t se_sha_0_hash_l_2 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_0_hash_l_2;
+
+    /* 0x1C : se_sha_0_hash_l_3 */
+    union {
+        struct
+        {
+            uint32_t se_sha_0_hash_l_3 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_0_hash_l_3;
+
+    /* 0x20 : se_sha_0_hash_l_4 */
+    union {
+        struct
+        {
+            uint32_t se_sha_0_hash_l_4 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_0_hash_l_4;
+
+    /* 0x24 : se_sha_0_hash_l_5 */
+    union {
+        struct
+        {
+            uint32_t se_sha_0_hash_l_5 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_0_hash_l_5;
+
+    /* 0x28 : se_sha_0_hash_l_6 */
+    union {
+        struct
+        {
+            uint32_t se_sha_0_hash_l_6 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_0_hash_l_6;
+
+    /* 0x2C : se_sha_0_hash_l_7 */
+    union {
+        struct
+        {
+            uint32_t se_sha_0_hash_l_7 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_0_hash_l_7;
+
+    /* 0x30 : se_sha_0_hash_h_0 */
+    union {
+        struct
+        {
+            uint32_t se_sha_0_hash_h_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_0_hash_h_0;
+
+    /* 0x34 : se_sha_0_hash_h_1 */
+    union {
+        struct
+        {
+            uint32_t se_sha_0_hash_h_1 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_0_hash_h_1;
+
+    /* 0x38 : se_sha_0_hash_h_2 */
+    union {
+        struct
+        {
+            uint32_t se_sha_0_hash_h_2 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_0_hash_h_2;
+
+    /* 0x3C : se_sha_0_hash_h_3 */
+    union {
+        struct
+        {
+            uint32_t se_sha_0_hash_h_3 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_0_hash_h_3;
+
+    /* 0x40 : se_sha_0_hash_h_4 */
+    union {
+        struct
+        {
+            uint32_t se_sha_0_hash_h_4 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_0_hash_h_4;
+
+    /* 0x44 : se_sha_0_hash_h_5 */
+    union {
+        struct
+        {
+            uint32_t se_sha_0_hash_h_5 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_0_hash_h_5;
+
+    /* 0x48 : se_sha_0_hash_h_6 */
+    union {
+        struct
+        {
+            uint32_t se_sha_0_hash_h_6 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_0_hash_h_6;
+
+    /* 0x4C : se_sha_0_hash_h_7 */
+    union {
+        struct
+        {
+            uint32_t se_sha_0_hash_h_7 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_0_hash_h_7;
+
+    /* 0x50 : se_sha_0_link */
+    union {
+        struct
+        {
+            uint32_t se_sha_0_lca : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_0_link;
+
+    /* 0x54  reserved */
+    uint8_t RESERVED0x54[168];
+
+    /* 0xFC : se_sha_0_ctrl_prot */
+    union {
+        struct
+        {
+            uint32_t se_sha_prot_en : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t se_sha_id0_en  : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t se_sha_id1_en  : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t reserved_3_31  : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_0_ctrl_prot;
+
+    /* 0x100 : se_aes_0_ctrl */
+    union {
+        struct
+        {
+            uint32_t se_aes_0_busy        : 1;  /* [    0],          r,        0x0 */
+            uint32_t se_aes_0_trig_1t     : 1;  /* [    1],        w1p,        0x0 */
+            uint32_t se_aes_0_en          : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t se_aes_0_mode        : 2;  /* [ 4: 3],        r/w,        0x0 */
+            uint32_t se_aes_0_dec_en      : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t se_aes_0_dec_key_sel : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t se_aes_0_hw_key_en   : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t se_aes_0_int         : 1;  /* [    8],          r,        0x0 */
+            uint32_t se_aes_0_int_clr_1t  : 1;  /* [    9],        w1p,        0x0 */
+            uint32_t se_aes_0_int_set_1t  : 1;  /* [   10],        w1p,        0x0 */
+            uint32_t se_aes_0_int_mask    : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t se_aes_0_block_mode  : 2;  /* [13:12],        r/w,        0x0 */
+            uint32_t se_aes_0_iv_sel      : 1;  /* [   14],        r/w,        0x0 */
+            uint32_t se_aes_0_link_mode   : 1;  /* [   15],        r/w,        0x0 */
+            uint32_t se_aes_0_msg_len     : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_0_ctrl;
+
+    /* 0x104 : se_aes_0_msa */
+    union {
+        struct
+        {
+            uint32_t se_aes_0_msa : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_0_msa;
+
+    /* 0x108 : se_aes_0_mda */
+    union {
+        struct
+        {
+            uint32_t se_aes_0_mda : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_0_mda;
+
+    /* 0x10C : se_aes_0_status */
+    union {
+        struct
+        {
+            uint32_t se_aes_0_status : 32; /* [31: 0],          r,      0x100 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_0_status;
+
+    /* 0x110 : se_aes_0_iv_0 */
+    union {
+        struct
+        {
+            uint32_t se_aes_0_iv_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_0_iv_0;
+
+    /* 0x114 : se_aes_0_iv_1 */
+    union {
+        struct
+        {
+            uint32_t se_aes_0_iv_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_0_iv_1;
+
+    /* 0x118 : se_aes_0_iv_2 */
+    union {
+        struct
+        {
+            uint32_t se_aes_0_iv_2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_0_iv_2;
+
+    /* 0x11C : se_aes_0_iv_3 */
+    union {
+        struct
+        {
+            uint32_t se_aes_0_iv_3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_0_iv_3;
+
+    /* 0x120 : se_aes_0_key_0 */
+    union {
+        struct
+        {
+            uint32_t se_aes_0_key_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_0_key_0;
+
+    /* 0x124 : se_aes_0_key_1 */
+    union {
+        struct
+        {
+            uint32_t se_aes_0_key_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_0_key_1;
+
+    /* 0x128 : se_aes_0_key_2 */
+    union {
+        struct
+        {
+            uint32_t se_aes_0_key_2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_0_key_2;
+
+    /* 0x12C : se_aes_0_key_3 */
+    union {
+        struct
+        {
+            uint32_t se_aes_0_key_3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_0_key_3;
+
+    /* 0x130 : se_aes_0_key_4 */
+    union {
+        struct
+        {
+            uint32_t se_aes_0_key_4 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_0_key_4;
+
+    /* 0x134 : se_aes_0_key_5 */
+    union {
+        struct
+        {
+            uint32_t se_aes_0_key_5 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_0_key_5;
+
+    /* 0x138 : se_aes_0_key_6 */
+    union {
+        struct
+        {
+            uint32_t se_aes_0_key_6 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_0_key_6;
+
+    /* 0x13C : se_aes_0_key_7 */
+    union {
+        struct
+        {
+            uint32_t se_aes_0_key_7 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_0_key_7;
+
+    /* 0x140 : se_aes_0_key_sel_0 */
+    union {
+        struct
+        {
+            uint32_t se_aes_0_key_sel_0 : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_31      : 30; /* [31: 2],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_0_key_sel_0;
+
+    /* 0x144 : se_aes_0_key_sel_1 */
+    union {
+        struct
+        {
+            uint32_t se_aes_0_key_sel_1 : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_31      : 30; /* [31: 2],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_0_key_sel_1;
+
+    /* 0x148 : se_aes_0_endian */
+    union {
+        struct
+        {
+            uint32_t se_aes_0_dout_endian : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t se_aes_0_din_endian  : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t se_aes_0_key_endian  : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t se_aes_0_iv_endian   : 1;  /* [    3],        r/w,        0x1 */
+            uint32_t reserved_4_29        : 26; /* [29: 4],       rsvd,        0x0 */
+            uint32_t se_aes_0_ctr_len     : 2;  /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_0_endian;
+
+    /* 0x14C : se_aes_0_sboot */
+    union {
+        struct
+        {
+            uint32_t se_aes_0_sboot_key_sel : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_31          : 31; /* [31: 1],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_0_sboot;
+
+    /* 0x150 : se_aes_0_link */
+    union {
+        struct
+        {
+            uint32_t se_aes_0_lca : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_0_link;
+
+    /* 0x154  reserved */
+    uint8_t RESERVED0x154[168];
+
+    /* 0x1FC : se_aes_0_ctrl_prot */
+    union {
+        struct
+        {
+            uint32_t se_aes_prot_en : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t se_aes_id0_en  : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t se_aes_id1_en  : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t reserved_3_31  : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_0_ctrl_prot;
+
+    /* 0x200 : se_trng_0_ctrl_0 */
+    union {
+        struct
+        {
+            uint32_t se_trng_0_busy           : 1;  /* [    0],          r,        0x0 */
+            uint32_t se_trng_0_trig_1t        : 1;  /* [    1],        w1p,        0x0 */
+            uint32_t se_trng_0_en             : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t se_trng_0_dout_clr_1t    : 1;  /* [    3],        w1p,        0x0 */
+            uint32_t se_trng_0_ht_error       : 1;  /* [    4],          r,        0x0 */
+            uint32_t reserved_5_7             : 3;  /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t se_trng_0_int            : 1;  /* [    8],          r,        0x0 */
+            uint32_t se_trng_0_int_clr_1t     : 1;  /* [    9],        w1p,        0x0 */
+            uint32_t se_trng_0_int_set_1t     : 1;  /* [   10],        w1p,        0x0 */
+            uint32_t se_trng_0_int_mask       : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t reserved_12              : 1;  /* [   12],       rsvd,        0x0 */
+            uint32_t se_trng_0_manual_fun_sel : 1;  /* [   13],        r/w,        0x0 */
+            uint32_t se_trng_0_manual_reseed  : 1;  /* [   14],        r/w,        0x0 */
+            uint32_t se_trng_0_manual_en      : 1;  /* [   15],        r/w,        0x0 */
+            uint32_t reserved_16_31           : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_0_ctrl_0;
+
+    /* 0x204 : se_trng_0_status */
+    union {
+        struct
+        {
+            uint32_t se_trng_0_status : 32; /* [31: 0],          r,   0x100020 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_0_status;
+
+    /* 0x208 : se_trng_0_dout_0 */
+    union {
+        struct
+        {
+            uint32_t se_trng_0_dout_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_0_dout_0;
+
+    /* 0x20C : se_trng_0_dout_1 */
+    union {
+        struct
+        {
+            uint32_t se_trng_0_dout_1 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_0_dout_1;
+
+    /* 0x210 : se_trng_0_dout_2 */
+    union {
+        struct
+        {
+            uint32_t se_trng_0_dout_2 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_0_dout_2;
+
+    /* 0x214 : se_trng_0_dout_3 */
+    union {
+        struct
+        {
+            uint32_t se_trng_0_dout_3 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_0_dout_3;
+
+    /* 0x218 : se_trng_0_dout_4 */
+    union {
+        struct
+        {
+            uint32_t se_trng_0_dout_4 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_0_dout_4;
+
+    /* 0x21C : se_trng_0_dout_5 */
+    union {
+        struct
+        {
+            uint32_t se_trng_0_dout_5 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_0_dout_5;
+
+    /* 0x220 : se_trng_0_dout_6 */
+    union {
+        struct
+        {
+            uint32_t se_trng_0_dout_6 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_0_dout_6;
+
+    /* 0x224 : se_trng_0_dout_7 */
+    union {
+        struct
+        {
+            uint32_t se_trng_0_dout_7 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_0_dout_7;
+
+    /* 0x228 : se_trng_0_test */
+    union {
+        struct
+        {
+            uint32_t se_trng_0_test_en    : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t se_trng_0_cp_test_en : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t se_trng_0_cp_bypass  : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t se_trng_0_ht_dis     : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t se_trng_0_ht_alarm_n : 8;  /* [11: 4],        r/w,        0x0 */
+            uint32_t reserved_12_31       : 20; /* [31:12],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_0_test;
+
+    /* 0x22C : se_trng_0_ctrl_1 */
+    union {
+        struct
+        {
+            uint32_t se_trng_0_reseed_n_lsb : 32; /* [31: 0],        r/w,     0xffff */
+        } BF;
+        uint32_t WORD;
+    } se_trng_0_ctrl_1;
+
+    /* 0x230 : se_trng_0_ctrl_2 */
+    union {
+        struct
+        {
+            uint32_t se_trng_0_reseed_n_msb : 16; /* [15: 0],        r/w,       0xff */
+            uint32_t reserved_16_31         : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_0_ctrl_2;
+
+    /* 0x234 : se_trng_0_ctrl_3 */
+    union {
+        struct
+        {
+            uint32_t se_trng_0_cp_ratio : 8;  /* [ 7: 0],        r/w,        0x3 */
+            uint32_t se_trng_0_ht_rct_c : 8;  /* [15: 8],        r/w,       0x42 */
+            uint32_t se_trng_0_ht_apt_c : 10; /* [25:16],        r/w,      0x37a */
+            uint32_t se_trng_0_ht_od_en : 1;  /* [   26],        r/w,        0x0 */
+            uint32_t reserved_27_30     : 4;  /* [30:27],       rsvd,        0x0 */
+            uint32_t se_trng_0_rosc_en  : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_0_ctrl_3;
+
+    /* 0x238  reserved */
+    uint8_t RESERVED0x238[8];
+
+    /* 0x240 : se_trng_0_test_out_0 */
+    union {
+        struct
+        {
+            uint32_t se_trng_0_test_out_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_0_test_out_0;
+
+    /* 0x244 : se_trng_0_test_out_1 */
+    union {
+        struct
+        {
+            uint32_t se_trng_0_test_out_1 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_0_test_out_1;
+
+    /* 0x248 : se_trng_0_test_out_2 */
+    union {
+        struct
+        {
+            uint32_t se_trng_0_test_out_2 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_0_test_out_2;
+
+    /* 0x24C : se_trng_0_test_out_3 */
+    union {
+        struct
+        {
+            uint32_t se_trng_0_test_out_3 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_0_test_out_3;
+
+    /* 0x250  reserved */
+    uint8_t RESERVED0x250[172];
+
+    /* 0x2FC : se_trng_0_ctrl_prot */
+    union {
+        struct
+        {
+            uint32_t se_trng_prot_en : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t se_trng_id0_en  : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t se_trng_id1_en  : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t reserved_3_31   : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_0_ctrl_prot;
+
+    /* 0x300 : se_pka_0_ctrl_0 */
+    union {
+        struct
+        {
+            uint32_t se_pka_0_done          : 1;  /* [    0],          r,        0x0 */
+            uint32_t se_pka_0_done_clr_1t   : 1;  /* [    1],        w1p,        0x0 */
+            uint32_t se_pka_0_busy          : 1;  /* [    2],          r,        0x0 */
+            uint32_t se_pka_0_en            : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t se_pka_0_prot_md       : 4;  /* [ 7: 4],        r/w,        0x0 */
+            uint32_t se_pka_0_int           : 1;  /* [    8],          r,        0x0 */
+            uint32_t se_pka_0_int_clr_1t    : 1;  /* [    9],        w1p,        0x0 */
+            uint32_t se_pka_0_int_set       : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t se_pka_0_int_mask      : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t se_pka_0_endian        : 1;  /* [   12],        r/w,        0x0 */
+            uint32_t se_pka_0_ram_clr_md    : 1;  /* [   13],        r/w,        0x0 */
+            uint32_t reserved_14            : 1;  /* [   14],       rsvd,        0x0 */
+            uint32_t se_pka_0_status_clr_1t : 1;  /* [   15],        w1p,        0x0 */
+            uint32_t se_pka_0_status        : 16; /* [31:16],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_pka_0_ctrl_0;
+
+    /* 0x304  reserved */
+    uint8_t RESERVED0x304[8];
+
+    /* 0x30C : se_pka_0_seed */
+    union {
+        struct
+        {
+            uint32_t se_pka_0_seed : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_pka_0_seed;
+
+    /* 0x310 : se_pka_0_ctrl_1 */
+    union {
+        struct
+        {
+            uint32_t se_pka_0_hburst  : 3;  /* [ 2: 0],        r/w,        0x5 */
+            uint32_t se_pka_0_hbypass : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t reserved_4_31    : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_pka_0_ctrl_1;
+
+    /* 0x314  reserved */
+    uint8_t RESERVED0x314[44];
+
+    /* 0x340 : se_pka_0_rw */
+    union {
+        struct
+        {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_pka_0_rw;
+
+    /* 0x344  reserved */
+    uint8_t RESERVED0x344[28];
+
+    /* 0x360 : se_pka_0_rw_burst */
+    union {
+        struct
+        {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_pka_0_rw_burst;
+
+    /* 0x364  reserved */
+    uint8_t RESERVED0x364[152];
+
+    /* 0x3FC : se_pka_0_ctrl_prot */
+    union {
+        struct
+        {
+            uint32_t se_pka_prot_en : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t se_pka_id0_en  : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t se_pka_id1_en  : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t reserved_3_31  : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_pka_0_ctrl_prot;
+
+    /* 0x400 : se_cdet_0_ctrl_0 */
+    union {
+        struct
+        {
+            uint32_t se_cdet_0_en         : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t se_cdet_0_error      : 1;  /* [    1],          r,        0x0 */
+            uint32_t se_cdet_0_status     : 14; /* [15: 2],          r,        0x1 */
+            uint32_t se_cdet_0_g_loop_max : 8;  /* [23:16],        r/w,       0x64 */
+            uint32_t se_cdet_0_g_loop_min : 8;  /* [31:24],        r/w,       0x21 */
+        } BF;
+        uint32_t WORD;
+    } se_cdet_0_ctrl_0;
+
+    /* 0x404 : se_cdet_0_ctrl_1 */
+    union {
+        struct
+        {
+            uint32_t se_cdet_0_t_loop_n : 8; /* [ 7: 0],        r/w,       0x32 */
+            uint32_t se_cdet_0_t_dly_n  : 8; /* [15: 8],        r/w,        0x3 */
+            uint32_t se_cdet_0_g_slp_n  : 8; /* [23:16],        r/w,       0xff */
+            uint32_t reserved_24_31     : 8; /* [31:24],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_cdet_0_ctrl_1;
+
+    /* 0x408  reserved */
+    uint8_t RESERVED0x408[244];
+
+    /* 0x4FC : se_cdet_0_ctrl_prot */
+    union {
+        struct
+        {
+            uint32_t se_cdet_prot_en : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t se_cdet_id0_en  : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t se_cdet_id1_en  : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t reserved_3_31   : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_cdet_0_ctrl_prot;
+
+    /* 0x500 : se_gmac_0_ctrl_0 */
+    union {
+        struct
+        {
+            uint32_t se_gmac_0_busy       : 1;  /* [    0],          r,        0x0 */
+            uint32_t se_gmac_0_trig_1t    : 1;  /* [    1],        w1p,        0x0 */
+            uint32_t se_gmac_0_en         : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3_7         : 5;  /* [ 7: 3],       rsvd,        0x0 */
+            uint32_t se_gmac_0_int        : 1;  /* [    8],          r,        0x0 */
+            uint32_t se_gmac_0_int_clr_1t : 1;  /* [    9],        w1p,        0x0 */
+            uint32_t se_gmac_0_int_set_1t : 1;  /* [   10],        w1p,        0x0 */
+            uint32_t se_gmac_0_int_mask   : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t se_gmac_0_t_endian   : 1;  /* [   12],        r/w,        0x1 */
+            uint32_t se_gmac_0_h_endian   : 1;  /* [   13],        r/w,        0x1 */
+            uint32_t se_gmac_0_x_endian   : 1;  /* [   14],        r/w,        0x1 */
+            uint32_t reserved_15_31       : 17; /* [31:15],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_gmac_0_ctrl_0;
+
+    /* 0x504 : se_gmac_0_lca */
+    union {
+        struct
+        {
+            uint32_t se_gmac_0_lca : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_gmac_0_lca;
+
+    /* 0x508 : se_gmac_0_status */
+    union {
+        struct
+        {
+            uint32_t se_gmac_0_status : 32; /* [31: 0],          r, 0xf1000000L */
+        } BF;
+        uint32_t WORD;
+    } se_gmac_0_status;
+
+    /* 0x50c  reserved */
+    uint8_t RESERVED0x50c[240];
+
+    /* 0x5FC : se_gmac_0_ctrl_prot */
+    union {
+        struct
+        {
+            uint32_t se_gmac_prot_en : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t se_gmac_id0_en  : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t se_gmac_id1_en  : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t reserved_3_31   : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_gmac_0_ctrl_prot;
+
+    /* 0x600  reserved */
+    uint8_t RESERVED0x600[2304];
+
+    /* 0xF00 : se_ctrl_prot_rd */
+    union {
+        struct
+        {
+            uint32_t se_sha_prot_en_rd  : 1; /* [    0],          r,        0x1 */
+            uint32_t se_sha_id0_en_rd   : 1; /* [    1],          r,        0x1 */
+            uint32_t se_sha_id1_en_rd   : 1; /* [    2],          r,        0x1 */
+            uint32_t reserved_3         : 1; /* [    3],       rsvd,        0x0 */
+            uint32_t se_aes_prot_en_rd  : 1; /* [    4],          r,        0x1 */
+            uint32_t se_aes_id0_en_rd   : 1; /* [    5],          r,        0x1 */
+            uint32_t se_aes_id1_en_rd   : 1; /* [    6],          r,        0x1 */
+            uint32_t reserved_7         : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t se_trng_prot_en_rd : 1; /* [    8],          r,        0x1 */
+            uint32_t se_trng_id0_en_rd  : 1; /* [    9],          r,        0x1 */
+            uint32_t se_trng_id1_en_rd  : 1; /* [   10],          r,        0x1 */
+            uint32_t reserved_11        : 1; /* [   11],       rsvd,        0x0 */
+            uint32_t se_pka_prot_en_rd  : 1; /* [   12],          r,        0x1 */
+            uint32_t se_pka_id0_en_rd   : 1; /* [   13],          r,        0x1 */
+            uint32_t se_pka_id1_en_rd   : 1; /* [   14],          r,        0x1 */
+            uint32_t reserved_15        : 1; /* [   15],       rsvd,        0x0 */
+            uint32_t se_cdet_prot_en_rd : 1; /* [   16],          r,        0x1 */
+            uint32_t se_cdet_id0_en_rd  : 1; /* [   17],          r,        0x1 */
+            uint32_t se_cdet_id1_en_rd  : 1; /* [   18],          r,        0x1 */
+            uint32_t reserved_19        : 1; /* [   19],       rsvd,        0x0 */
+            uint32_t se_gmac_prot_en_rd : 1; /* [   20],          r,        0x1 */
+            uint32_t se_gmac_id0_en_rd  : 1; /* [   21],          r,        0x1 */
+            uint32_t se_gmac_id1_en_rd  : 1; /* [   22],          r,        0x1 */
+            uint32_t reserved_23_30     : 8; /* [30:23],       rsvd,        0x0 */
+            uint32_t se_dbg_dis         : 1; /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_ctrl_prot_rd;
+
+    /* 0xF04 : se_ctrl_reserved_0 */
+    union {
+        struct
+        {
+            uint32_t se_ctrl_reserved_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_ctrl_reserved_0;
+
+    /* 0xF08 : se_ctrl_reserved_1 */
+    union {
+        struct
+        {
+            uint32_t se_ctrl_reserved_1 : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } se_ctrl_reserved_1;
+
+    /* 0xF0C : se_ctrl_reserved_2 */
+    union {
+        struct
+        {
+            uint32_t se_ctrl_reserved_2 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_ctrl_reserved_2;
+};
+
+typedef volatile struct sec_eng_reg sec_eng_reg_t;
+
+/*Following is reg patch*/
+
+/* 0x0 : se_sha_ctrl */
+#define SEC_ENG_SE_SHA_CTRL_OFFSET     (0x0)
+#define SEC_ENG_SE_SHA_BUSY            SEC_ENG_SE_SHA_BUSY
+#define SEC_ENG_SE_SHA_BUSY_POS        (0U)
+#define SEC_ENG_SE_SHA_BUSY_LEN        (1U)
+#define SEC_ENG_SE_SHA_BUSY_MSK        (((1U << SEC_ENG_SE_SHA_BUSY_LEN) - 1) << SEC_ENG_SE_SHA_BUSY_POS)
+#define SEC_ENG_SE_SHA_BUSY_UMSK       (~(((1U << SEC_ENG_SE_SHA_BUSY_LEN) - 1) << SEC_ENG_SE_SHA_BUSY_POS))
+#define SEC_ENG_SE_SHA_TRIG_1T         SEC_ENG_SE_SHA_TRIG_1T
+#define SEC_ENG_SE_SHA_TRIG_1T_POS     (1U)
+#define SEC_ENG_SE_SHA_TRIG_1T_LEN     (1U)
+#define SEC_ENG_SE_SHA_TRIG_1T_MSK     (((1U << SEC_ENG_SE_SHA_TRIG_1T_LEN) - 1) << SEC_ENG_SE_SHA_TRIG_1T_POS)
+#define SEC_ENG_SE_SHA_TRIG_1T_UMSK    (~(((1U << SEC_ENG_SE_SHA_TRIG_1T_LEN) - 1) << SEC_ENG_SE_SHA_TRIG_1T_POS))
+#define SEC_ENG_SE_SHA_MODE            SEC_ENG_SE_SHA_MODE
+#define SEC_ENG_SE_SHA_MODE_POS        (2U)
+#define SEC_ENG_SE_SHA_MODE_LEN        (3U)
+#define SEC_ENG_SE_SHA_MODE_MSK        (((1U << SEC_ENG_SE_SHA_MODE_LEN) - 1) << SEC_ENG_SE_SHA_MODE_POS)
+#define SEC_ENG_SE_SHA_MODE_UMSK       (~(((1U << SEC_ENG_SE_SHA_MODE_LEN) - 1) << SEC_ENG_SE_SHA_MODE_POS))
+#define SEC_ENG_SE_SHA_EN              SEC_ENG_SE_SHA_EN
+#define SEC_ENG_SE_SHA_EN_POS          (5U)
+#define SEC_ENG_SE_SHA_EN_LEN          (1U)
+#define SEC_ENG_SE_SHA_EN_MSK          (((1U << SEC_ENG_SE_SHA_EN_LEN) - 1) << SEC_ENG_SE_SHA_EN_POS)
+#define SEC_ENG_SE_SHA_EN_UMSK         (~(((1U << SEC_ENG_SE_SHA_EN_LEN) - 1) << SEC_ENG_SE_SHA_EN_POS))
+#define SEC_ENG_SE_SHA_HASH_SEL        SEC_ENG_SE_SHA_HASH_SEL
+#define SEC_ENG_SE_SHA_HASH_SEL_POS    (6U)
+#define SEC_ENG_SE_SHA_HASH_SEL_LEN    (1U)
+#define SEC_ENG_SE_SHA_HASH_SEL_MSK    (((1U << SEC_ENG_SE_SHA_HASH_SEL_LEN) - 1) << SEC_ENG_SE_SHA_HASH_SEL_POS)
+#define SEC_ENG_SE_SHA_HASH_SEL_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_SEL_LEN) - 1) << SEC_ENG_SE_SHA_HASH_SEL_POS))
+#define SEC_ENG_SE_SHA_INT             SEC_ENG_SE_SHA_INT
+#define SEC_ENG_SE_SHA_INT_POS         (8U)
+#define SEC_ENG_SE_SHA_INT_LEN         (1U)
+#define SEC_ENG_SE_SHA_INT_MSK         (((1U << SEC_ENG_SE_SHA_INT_LEN) - 1) << SEC_ENG_SE_SHA_INT_POS)
+#define SEC_ENG_SE_SHA_INT_UMSK        (~(((1U << SEC_ENG_SE_SHA_INT_LEN) - 1) << SEC_ENG_SE_SHA_INT_POS))
+#define SEC_ENG_SE_SHA_INT_CLR_1T      SEC_ENG_SE_SHA_INT_CLR_1T
+#define SEC_ENG_SE_SHA_INT_CLR_1T_POS  (9U)
+#define SEC_ENG_SE_SHA_INT_CLR_1T_LEN  (1U)
+#define SEC_ENG_SE_SHA_INT_CLR_1T_MSK  (((1U << SEC_ENG_SE_SHA_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_SHA_INT_CLR_1T_POS)
+#define SEC_ENG_SE_SHA_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_SHA_INT_CLR_1T_POS))
+#define SEC_ENG_SE_SHA_INT_SET_1T      SEC_ENG_SE_SHA_INT_SET_1T
+#define SEC_ENG_SE_SHA_INT_SET_1T_POS  (10U)
+#define SEC_ENG_SE_SHA_INT_SET_1T_LEN  (1U)
+#define SEC_ENG_SE_SHA_INT_SET_1T_MSK  (((1U << SEC_ENG_SE_SHA_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_SHA_INT_SET_1T_POS)
+#define SEC_ENG_SE_SHA_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_SHA_INT_SET_1T_POS))
+#define SEC_ENG_SE_SHA_INT_MASK        SEC_ENG_SE_SHA_INT_MASK
+#define SEC_ENG_SE_SHA_INT_MASK_POS    (11U)
+#define SEC_ENG_SE_SHA_INT_MASK_LEN    (1U)
+#define SEC_ENG_SE_SHA_INT_MASK_MSK    (((1U << SEC_ENG_SE_SHA_INT_MASK_LEN) - 1) << SEC_ENG_SE_SHA_INT_MASK_POS)
+#define SEC_ENG_SE_SHA_INT_MASK_UMSK   (~(((1U << SEC_ENG_SE_SHA_INT_MASK_LEN) - 1) << SEC_ENG_SE_SHA_INT_MASK_POS))
+#define SEC_ENG_SE_SHA_LINK_MODE       SEC_ENG_SE_SHA_LINK_MODE
+#define SEC_ENG_SE_SHA_LINK_MODE_POS   (15U)
+#define SEC_ENG_SE_SHA_LINK_MODE_LEN   (1U)
+#define SEC_ENG_SE_SHA_LINK_MODE_MSK   (((1U << SEC_ENG_SE_SHA_LINK_MODE_LEN) - 1) << SEC_ENG_SE_SHA_LINK_MODE_POS)
+#define SEC_ENG_SE_SHA_LINK_MODE_UMSK  (~(((1U << SEC_ENG_SE_SHA_LINK_MODE_LEN) - 1) << SEC_ENG_SE_SHA_LINK_MODE_POS))
+#define SEC_ENG_SE_SHA_MSG_LEN         SEC_ENG_SE_SHA_MSG_LEN
+#define SEC_ENG_SE_SHA_MSG_LEN_POS     (16U)
+#define SEC_ENG_SE_SHA_MSG_LEN_LEN     (16U)
+#define SEC_ENG_SE_SHA_MSG_LEN_MSK     (((1U << SEC_ENG_SE_SHA_MSG_LEN_LEN) - 1) << SEC_ENG_SE_SHA_MSG_LEN_POS)
+#define SEC_ENG_SE_SHA_MSG_LEN_UMSK    (~(((1U << SEC_ENG_SE_SHA_MSG_LEN_LEN) - 1) << SEC_ENG_SE_SHA_MSG_LEN_POS))
+
+/* 0x4 : se_sha_msa */
+#define SEC_ENG_SE_SHA_MSA_OFFSET (0x4)
+#define SEC_ENG_SE_SHA_MSA        SEC_ENG_SE_SHA_MSA
+#define SEC_ENG_SE_SHA_MSA_POS    (0U)
+#define SEC_ENG_SE_SHA_MSA_LEN    (32U)
+#define SEC_ENG_SE_SHA_MSA_MSK    (((1U << SEC_ENG_SE_SHA_MSA_LEN) - 1) << SEC_ENG_SE_SHA_MSA_POS)
+#define SEC_ENG_SE_SHA_MSA_UMSK   (~(((1U << SEC_ENG_SE_SHA_MSA_LEN) - 1) << SEC_ENG_SE_SHA_MSA_POS))
+
+/* 0x8 : se_sha_status */
+#define SEC_ENG_SE_SHA_STATUS_OFFSET (0x8)
+#define SEC_ENG_SE_SHA_STATUS        SEC_ENG_SE_SHA_STATUS
+#define SEC_ENG_SE_SHA_STATUS_POS    (0U)
+#define SEC_ENG_SE_SHA_STATUS_LEN    (32U)
+#define SEC_ENG_SE_SHA_STATUS_MSK    (((1U << SEC_ENG_SE_SHA_STATUS_LEN) - 1) << SEC_ENG_SE_SHA_STATUS_POS)
+#define SEC_ENG_SE_SHA_STATUS_UMSK   (~(((1U << SEC_ENG_SE_SHA_STATUS_LEN) - 1) << SEC_ENG_SE_SHA_STATUS_POS))
+
+/* 0xc : se_sha_endian */
+#define SEC_ENG_SE_SHA_ENDIAN_OFFSET    (0xc)
+#define SEC_ENG_SE_SHA_DOUT_ENDIAN      SEC_ENG_SE_SHA_DOUT_ENDIAN
+#define SEC_ENG_SE_SHA_DOUT_ENDIAN_POS  (0U)
+#define SEC_ENG_SE_SHA_DOUT_ENDIAN_LEN  (1U)
+#define SEC_ENG_SE_SHA_DOUT_ENDIAN_MSK  (((1U << SEC_ENG_SE_SHA_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_SHA_DOUT_ENDIAN_POS)
+#define SEC_ENG_SE_SHA_DOUT_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_SHA_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_SHA_DOUT_ENDIAN_POS))
+
+/* 0x10 : se_sha_hash_l_0 */
+#define SEC_ENG_SE_SHA_HASH_L_0_OFFSET (0x10)
+#define SEC_ENG_SE_SHA_HASH_L_0        SEC_ENG_SE_SHA_HASH_L_0
+#define SEC_ENG_SE_SHA_HASH_L_0_POS    (0U)
+#define SEC_ENG_SE_SHA_HASH_L_0_LEN    (32U)
+#define SEC_ENG_SE_SHA_HASH_L_0_MSK    (((1U << SEC_ENG_SE_SHA_HASH_L_0_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_0_POS)
+#define SEC_ENG_SE_SHA_HASH_L_0_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_L_0_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_0_POS))
+
+/* 0x14 : se_sha_hash_l_1 */
+#define SEC_ENG_SE_SHA_HASH_L_1_OFFSET (0x14)
+#define SEC_ENG_SE_SHA_HASH_L_1        SEC_ENG_SE_SHA_HASH_L_1
+#define SEC_ENG_SE_SHA_HASH_L_1_POS    (0U)
+#define SEC_ENG_SE_SHA_HASH_L_1_LEN    (32U)
+#define SEC_ENG_SE_SHA_HASH_L_1_MSK    (((1U << SEC_ENG_SE_SHA_HASH_L_1_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_1_POS)
+#define SEC_ENG_SE_SHA_HASH_L_1_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_L_1_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_1_POS))
+
+/* 0x18 : se_sha_hash_l_2 */
+#define SEC_ENG_SE_SHA_HASH_L_2_OFFSET (0x18)
+#define SEC_ENG_SE_SHA_HASH_L_2        SEC_ENG_SE_SHA_HASH_L_2
+#define SEC_ENG_SE_SHA_HASH_L_2_POS    (0U)
+#define SEC_ENG_SE_SHA_HASH_L_2_LEN    (32U)
+#define SEC_ENG_SE_SHA_HASH_L_2_MSK    (((1U << SEC_ENG_SE_SHA_HASH_L_2_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_2_POS)
+#define SEC_ENG_SE_SHA_HASH_L_2_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_L_2_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_2_POS))
+
+/* 0x1c : se_sha_hash_l_3 */
+#define SEC_ENG_SE_SHA_HASH_L_3_OFFSET (0x1c)
+#define SEC_ENG_SE_SHA_HASH_L_3        SEC_ENG_SE_SHA_HASH_L_3
+#define SEC_ENG_SE_SHA_HASH_L_3_POS    (0U)
+#define SEC_ENG_SE_SHA_HASH_L_3_LEN    (32U)
+#define SEC_ENG_SE_SHA_HASH_L_3_MSK    (((1U << SEC_ENG_SE_SHA_HASH_L_3_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_3_POS)
+#define SEC_ENG_SE_SHA_HASH_L_3_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_L_3_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_3_POS))
+
+/* 0x20 : se_sha_hash_l_4 */
+#define SEC_ENG_SE_SHA_HASH_L_4_OFFSET (0x20)
+#define SEC_ENG_SE_SHA_HASH_L_4        SEC_ENG_SE_SHA_HASH_L_4
+#define SEC_ENG_SE_SHA_HASH_L_4_POS    (0U)
+#define SEC_ENG_SE_SHA_HASH_L_4_LEN    (32U)
+#define SEC_ENG_SE_SHA_HASH_L_4_MSK    (((1U << SEC_ENG_SE_SHA_HASH_L_4_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_4_POS)
+#define SEC_ENG_SE_SHA_HASH_L_4_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_L_4_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_4_POS))
+
+/* 0x24 : se_sha_hash_l_5 */
+#define SEC_ENG_SE_SHA_HASH_L_5_OFFSET (0x24)
+#define SEC_ENG_SE_SHA_HASH_L_5        SEC_ENG_SE_SHA_HASH_L_5
+#define SEC_ENG_SE_SHA_HASH_L_5_POS    (0U)
+#define SEC_ENG_SE_SHA_HASH_L_5_LEN    (32U)
+#define SEC_ENG_SE_SHA_HASH_L_5_MSK    (((1U << SEC_ENG_SE_SHA_HASH_L_5_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_5_POS)
+#define SEC_ENG_SE_SHA_HASH_L_5_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_L_5_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_5_POS))
+
+/* 0x28 : se_sha_hash_l_6 */
+#define SEC_ENG_SE_SHA_HASH_L_6_OFFSET (0x28)
+#define SEC_ENG_SE_SHA_HASH_L_6        SEC_ENG_SE_SHA_HASH_L_6
+#define SEC_ENG_SE_SHA_HASH_L_6_POS    (0U)
+#define SEC_ENG_SE_SHA_HASH_L_6_LEN    (32U)
+#define SEC_ENG_SE_SHA_HASH_L_6_MSK    (((1U << SEC_ENG_SE_SHA_HASH_L_6_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_6_POS)
+#define SEC_ENG_SE_SHA_HASH_L_6_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_L_6_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_6_POS))
+
+/* 0x2c : se_sha_hash_l_7 */
+#define SEC_ENG_SE_SHA_HASH_L_7_OFFSET (0x2c)
+#define SEC_ENG_SE_SHA_HASH_L_7        SEC_ENG_SE_SHA_HASH_L_7
+#define SEC_ENG_SE_SHA_HASH_L_7_POS    (0U)
+#define SEC_ENG_SE_SHA_HASH_L_7_LEN    (32U)
+#define SEC_ENG_SE_SHA_HASH_L_7_MSK    (((1U << SEC_ENG_SE_SHA_HASH_L_7_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_7_POS)
+#define SEC_ENG_SE_SHA_HASH_L_7_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_L_7_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_7_POS))
+
+/* 0x30 : se_sha_hash_h_0 */
+#define SEC_ENG_SE_SHA_HASH_H_0_OFFSET (0x30)
+#define SEC_ENG_SE_SHA_HASH_H_0        SEC_ENG_SE_SHA_HASH_H_0
+#define SEC_ENG_SE_SHA_HASH_H_0_POS    (0U)
+#define SEC_ENG_SE_SHA_HASH_H_0_LEN    (32U)
+#define SEC_ENG_SE_SHA_HASH_H_0_MSK    (((1U << SEC_ENG_SE_SHA_HASH_H_0_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_0_POS)
+#define SEC_ENG_SE_SHA_HASH_H_0_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_H_0_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_0_POS))
+
+/* 0x34 : se_sha_hash_h_1 */
+#define SEC_ENG_SE_SHA_HASH_H_1_OFFSET (0x34)
+#define SEC_ENG_SE_SHA_HASH_H_1        SEC_ENG_SE_SHA_HASH_H_1
+#define SEC_ENG_SE_SHA_HASH_H_1_POS    (0U)
+#define SEC_ENG_SE_SHA_HASH_H_1_LEN    (32U)
+#define SEC_ENG_SE_SHA_HASH_H_1_MSK    (((1U << SEC_ENG_SE_SHA_HASH_H_1_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_1_POS)
+#define SEC_ENG_SE_SHA_HASH_H_1_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_H_1_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_1_POS))
+
+/* 0x38 : se_sha_hash_h_2 */
+#define SEC_ENG_SE_SHA_HASH_H_2_OFFSET (0x38)
+#define SEC_ENG_SE_SHA_HASH_H_2        SEC_ENG_SE_SHA_HASH_H_2
+#define SEC_ENG_SE_SHA_HASH_H_2_POS    (0U)
+#define SEC_ENG_SE_SHA_HASH_H_2_LEN    (32U)
+#define SEC_ENG_SE_SHA_HASH_H_2_MSK    (((1U << SEC_ENG_SE_SHA_HASH_H_2_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_2_POS)
+#define SEC_ENG_SE_SHA_HASH_H_2_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_H_2_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_2_POS))
+
+/* 0x3c : se_sha_hash_h_3 */
+#define SEC_ENG_SE_SHA_HASH_H_3_OFFSET (0x3c)
+#define SEC_ENG_SE_SHA_HASH_H_3        SEC_ENG_SE_SHA_HASH_H_3
+#define SEC_ENG_SE_SHA_HASH_H_3_POS    (0U)
+#define SEC_ENG_SE_SHA_HASH_H_3_LEN    (32U)
+#define SEC_ENG_SE_SHA_HASH_H_3_MSK    (((1U << SEC_ENG_SE_SHA_HASH_H_3_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_3_POS)
+#define SEC_ENG_SE_SHA_HASH_H_3_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_H_3_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_3_POS))
+
+/* 0x40 : se_sha_hash_h_4 */
+#define SEC_ENG_SE_SHA_HASH_H_4_OFFSET (0x40)
+#define SEC_ENG_SE_SHA_HASH_H_4        SEC_ENG_SE_SHA_HASH_H_4
+#define SEC_ENG_SE_SHA_HASH_H_4_POS    (0U)
+#define SEC_ENG_SE_SHA_HASH_H_4_LEN    (32U)
+#define SEC_ENG_SE_SHA_HASH_H_4_MSK    (((1U << SEC_ENG_SE_SHA_HASH_H_4_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_4_POS)
+#define SEC_ENG_SE_SHA_HASH_H_4_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_H_4_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_4_POS))
+
+/* 0x44 : se_sha_hash_h_5 */
+#define SEC_ENG_SE_SHA_HASH_H_5_OFFSET (0x44)
+#define SEC_ENG_SE_SHA_HASH_H_5        SEC_ENG_SE_SHA_HASH_H_5
+#define SEC_ENG_SE_SHA_HASH_H_5_POS    (0U)
+#define SEC_ENG_SE_SHA_HASH_H_5_LEN    (32U)
+#define SEC_ENG_SE_SHA_HASH_H_5_MSK    (((1U << SEC_ENG_SE_SHA_HASH_H_5_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_5_POS)
+#define SEC_ENG_SE_SHA_HASH_H_5_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_H_5_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_5_POS))
+
+/* 0x48 : se_sha_hash_h_6 */
+#define SEC_ENG_SE_SHA_HASH_H_6_OFFSET (0x48)
+#define SEC_ENG_SE_SHA_HASH_H_6        SEC_ENG_SE_SHA_HASH_H_6
+#define SEC_ENG_SE_SHA_HASH_H_6_POS    (0U)
+#define SEC_ENG_SE_SHA_HASH_H_6_LEN    (32U)
+#define SEC_ENG_SE_SHA_HASH_H_6_MSK    (((1U << SEC_ENG_SE_SHA_HASH_H_6_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_6_POS)
+#define SEC_ENG_SE_SHA_HASH_H_6_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_H_6_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_6_POS))
+
+/* 0x4c : se_sha_hash_h_7 */
+#define SEC_ENG_SE_SHA_HASH_H_7_OFFSET (0x4c)
+#define SEC_ENG_SE_SHA_HASH_H_7        SEC_ENG_SE_SHA_HASH_H_7
+#define SEC_ENG_SE_SHA_HASH_H_7_POS    (0U)
+#define SEC_ENG_SE_SHA_HASH_H_7_LEN    (32U)
+#define SEC_ENG_SE_SHA_HASH_H_7_MSK    (((1U << SEC_ENG_SE_SHA_HASH_H_7_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_7_POS)
+#define SEC_ENG_SE_SHA_HASH_H_7_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_H_7_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_7_POS))
+
+/* 0x50 : se_sha_link */
+#define SEC_ENG_SE_SHA_LINK_OFFSET (0x50)
+#define SEC_ENG_SE_SHA_LCA         SEC_ENG_SE_SHA_LCA
+#define SEC_ENG_SE_SHA_LCA_POS     (0U)
+#define SEC_ENG_SE_SHA_LCA_LEN     (32U)
+#define SEC_ENG_SE_SHA_LCA_MSK     (((1U << SEC_ENG_SE_SHA_LCA_LEN) - 1) << SEC_ENG_SE_SHA_LCA_POS)
+#define SEC_ENG_SE_SHA_LCA_UMSK    (~(((1U << SEC_ENG_SE_SHA_LCA_LEN) - 1) << SEC_ENG_SE_SHA_LCA_POS))
+
+/* 0xfc : se_sha_ctrl_prot */
+#define SEC_ENG_SE_SHA_CTRL_PROT_OFFSET (0xfc)
+#define SEC_ENG_SE_SHA_PROT_EN          SEC_ENG_SE_SHA_PROT_EN
+#define SEC_ENG_SE_SHA_PROT_EN_POS      (0U)
+#define SEC_ENG_SE_SHA_PROT_EN_LEN      (1U)
+#define SEC_ENG_SE_SHA_PROT_EN_MSK      (((1U << SEC_ENG_SE_SHA_PROT_EN_LEN) - 1) << SEC_ENG_SE_SHA_PROT_EN_POS)
+#define SEC_ENG_SE_SHA_PROT_EN_UMSK     (~(((1U << SEC_ENG_SE_SHA_PROT_EN_LEN) - 1) << SEC_ENG_SE_SHA_PROT_EN_POS))
+#define SEC_ENG_SE_SHA_ID0_EN           SEC_ENG_SE_SHA_ID0_EN
+#define SEC_ENG_SE_SHA_ID0_EN_POS       (1U)
+#define SEC_ENG_SE_SHA_ID0_EN_LEN       (1U)
+#define SEC_ENG_SE_SHA_ID0_EN_MSK       (((1U << SEC_ENG_SE_SHA_ID0_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_POS)
+#define SEC_ENG_SE_SHA_ID0_EN_UMSK      (~(((1U << SEC_ENG_SE_SHA_ID0_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_POS))
+#define SEC_ENG_SE_SHA_ID1_EN           SEC_ENG_SE_SHA_ID1_EN
+#define SEC_ENG_SE_SHA_ID1_EN_POS       (2U)
+#define SEC_ENG_SE_SHA_ID1_EN_LEN       (1U)
+#define SEC_ENG_SE_SHA_ID1_EN_MSK       (((1U << SEC_ENG_SE_SHA_ID1_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_POS)
+#define SEC_ENG_SE_SHA_ID1_EN_UMSK      (~(((1U << SEC_ENG_SE_SHA_ID1_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_POS))
+
+struct sec_eng_sha_reg {
+    /* 0x0 : se_sha_ctrl */
+    union {
+        struct
+        {
+            uint32_t se_sha_busy       : 1;  /* [    0],          r,        0x0 */
+            uint32_t se_sha_trig_1t    : 1;  /* [    1],        w1p,        0x0 */
+            uint32_t se_sha_mode       : 3;  /* [ 4: 2],        r/w,        0x0 */
+            uint32_t se_sha_en         : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t se_sha_hash_sel   : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7        : 1;  /* [    7],       rsvd,        0x0 */
+            uint32_t se_sha_int        : 1;  /* [    8],          r,        0x0 */
+            uint32_t se_sha_int_clr_1t : 1;  /* [    9],        w1p,        0x0 */
+            uint32_t se_sha_int_set_1t : 1;  /* [   10],        w1p,        0x0 */
+            uint32_t se_sha_int_mask   : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t reserved_12_14    : 3;  /* [14:12],       rsvd,        0x0 */
+            uint32_t se_sha_link_mode  : 1;  /* [   15],        r/w,        0x0 */
+            uint32_t se_sha_msg_len    : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_ctrl;
+
+    /* 0x4 : se_sha_msa */
+    union {
+        struct
+        {
+            uint32_t se_sha_msa : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_msa;
+
+    /* 0x8 : se_sha_status */
+    union {
+        struct
+        {
+            uint32_t se_sha_status : 32; /* [31: 0],          r,       0x41 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_status;
+
+    /* 0xc : se_sha_endian */
+    union {
+        struct
+        {
+            uint32_t se_sha_dout_endian : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reserved_1_31      : 31; /* [31: 1],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_endian;
+
+    /* 0x10 : se_sha_hash_l_0 */
+    union {
+        struct
+        {
+            uint32_t se_sha_hash_l_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_hash_l_0;
+
+    /* 0x14 : se_sha_hash_l_1 */
+    union {
+        struct
+        {
+            uint32_t se_sha_hash_l_1 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_hash_l_1;
+
+    /* 0x18 : se_sha_hash_l_2 */
+    union {
+        struct
+        {
+            uint32_t se_sha_hash_l_2 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_hash_l_2;
+
+    /* 0x1c : se_sha_hash_l_3 */
+    union {
+        struct
+        {
+            uint32_t se_sha_hash_l_3 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_hash_l_3;
+
+    /* 0x20 : se_sha_hash_l_4 */
+    union {
+        struct
+        {
+            uint32_t se_sha_hash_l_4 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_hash_l_4;
+
+    /* 0x24 : se_sha_hash_l_5 */
+    union {
+        struct
+        {
+            uint32_t se_sha_hash_l_5 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_hash_l_5;
+
+    /* 0x28 : se_sha_hash_l_6 */
+    union {
+        struct
+        {
+            uint32_t se_sha_hash_l_6 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_hash_l_6;
+
+    /* 0x2c : se_sha_hash_l_7 */
+    union {
+        struct
+        {
+            uint32_t se_sha_hash_l_7 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_hash_l_7;
+
+    /* 0x30 : se_sha_hash_h_0 */
+    union {
+        struct
+        {
+            uint32_t se_sha_hash_h_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_hash_h_0;
+
+    /* 0x34 : se_sha_hash_h_1 */
+    union {
+        struct
+        {
+            uint32_t se_sha_hash_h_1 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_hash_h_1;
+
+    /* 0x38 : se_sha_hash_h_2 */
+    union {
+        struct
+        {
+            uint32_t se_sha_hash_h_2 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_hash_h_2;
+
+    /* 0x3c : se_sha_hash_h_3 */
+    union {
+        struct
+        {
+            uint32_t se_sha_hash_h_3 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_hash_h_3;
+
+    /* 0x40 : se_sha_hash_h_4 */
+    union {
+        struct
+        {
+            uint32_t se_sha_hash_h_4 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_hash_h_4;
+
+    /* 0x44 : se_sha_hash_h_5 */
+    union {
+        struct
+        {
+            uint32_t se_sha_hash_h_5 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_hash_h_5;
+
+    /* 0x48 : se_sha_hash_h_6 */
+    union {
+        struct
+        {
+            uint32_t se_sha_hash_h_6 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_hash_h_6;
+
+    /* 0x4c : se_sha_hash_h_7 */
+    union {
+        struct
+        {
+            uint32_t se_sha_hash_h_7 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_hash_h_7;
+
+    /* 0x50 : se_sha_link */
+    union {
+        struct
+        {
+            uint32_t se_sha_lca : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_link;
+
+    /* 0x54  reserved */
+    uint8_t RESERVED0x54[168];
+
+    /* 0xfc : se_sha_ctrl_prot */
+    union {
+        struct
+        {
+            uint32_t se_sha_prot_en : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t se_sha_id0_en  : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t se_sha_id1_en  : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t reserved_3_31  : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_sha_ctrl_prot;
+};
+
+typedef volatile struct sec_eng_sha_reg sec_eng_sha_reg_t;
+
+#define SEC_ENG_SHA_OFFSET 0x000
+
+/*Following is reg patch*/
+
+/* 0x0 : se_aes_ctrl */
+#define SEC_ENG_SE_AES_CTRL_OFFSET      (0x0)
+#define SEC_ENG_SE_AES_BUSY             SEC_ENG_SE_AES_BUSY
+#define SEC_ENG_SE_AES_BUSY_POS         (0U)
+#define SEC_ENG_SE_AES_BUSY_LEN         (1U)
+#define SEC_ENG_SE_AES_BUSY_MSK         (((1U << SEC_ENG_SE_AES_BUSY_LEN) - 1) << SEC_ENG_SE_AES_BUSY_POS)
+#define SEC_ENG_SE_AES_BUSY_UMSK        (~(((1U << SEC_ENG_SE_AES_BUSY_LEN) - 1) << SEC_ENG_SE_AES_BUSY_POS))
+#define SEC_ENG_SE_AES_TRIG_1T          SEC_ENG_SE_AES_TRIG_1T
+#define SEC_ENG_SE_AES_TRIG_1T_POS      (1U)
+#define SEC_ENG_SE_AES_TRIG_1T_LEN      (1U)
+#define SEC_ENG_SE_AES_TRIG_1T_MSK      (((1U << SEC_ENG_SE_AES_TRIG_1T_LEN) - 1) << SEC_ENG_SE_AES_TRIG_1T_POS)
+#define SEC_ENG_SE_AES_TRIG_1T_UMSK     (~(((1U << SEC_ENG_SE_AES_TRIG_1T_LEN) - 1) << SEC_ENG_SE_AES_TRIG_1T_POS))
+#define SEC_ENG_SE_AES_EN               SEC_ENG_SE_AES_EN
+#define SEC_ENG_SE_AES_EN_POS           (2U)
+#define SEC_ENG_SE_AES_EN_LEN           (1U)
+#define SEC_ENG_SE_AES_EN_MSK           (((1U << SEC_ENG_SE_AES_EN_LEN) - 1) << SEC_ENG_SE_AES_EN_POS)
+#define SEC_ENG_SE_AES_EN_UMSK          (~(((1U << SEC_ENG_SE_AES_EN_LEN) - 1) << SEC_ENG_SE_AES_EN_POS))
+#define SEC_ENG_SE_AES_MODE             SEC_ENG_SE_AES_MODE
+#define SEC_ENG_SE_AES_MODE_POS         (3U)
+#define SEC_ENG_SE_AES_MODE_LEN         (2U)
+#define SEC_ENG_SE_AES_MODE_MSK         (((1U << SEC_ENG_SE_AES_MODE_LEN) - 1) << SEC_ENG_SE_AES_MODE_POS)
+#define SEC_ENG_SE_AES_MODE_UMSK        (~(((1U << SEC_ENG_SE_AES_MODE_LEN) - 1) << SEC_ENG_SE_AES_MODE_POS))
+#define SEC_ENG_SE_AES_DEC_EN           SEC_ENG_SE_AES_DEC_EN
+#define SEC_ENG_SE_AES_DEC_EN_POS       (5U)
+#define SEC_ENG_SE_AES_DEC_EN_LEN       (1U)
+#define SEC_ENG_SE_AES_DEC_EN_MSK       (((1U << SEC_ENG_SE_AES_DEC_EN_LEN) - 1) << SEC_ENG_SE_AES_DEC_EN_POS)
+#define SEC_ENG_SE_AES_DEC_EN_UMSK      (~(((1U << SEC_ENG_SE_AES_DEC_EN_LEN) - 1) << SEC_ENG_SE_AES_DEC_EN_POS))
+#define SEC_ENG_SE_AES_DEC_KEY_SEL      SEC_ENG_SE_AES_DEC_KEY_SEL
+#define SEC_ENG_SE_AES_DEC_KEY_SEL_POS  (6U)
+#define SEC_ENG_SE_AES_DEC_KEY_SEL_LEN  (1U)
+#define SEC_ENG_SE_AES_DEC_KEY_SEL_MSK  (((1U << SEC_ENG_SE_AES_DEC_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_DEC_KEY_SEL_POS)
+#define SEC_ENG_SE_AES_DEC_KEY_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_DEC_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_DEC_KEY_SEL_POS))
+#define SEC_ENG_SE_AES_HW_KEY_EN        SEC_ENG_SE_AES_HW_KEY_EN
+#define SEC_ENG_SE_AES_HW_KEY_EN_POS    (7U)
+#define SEC_ENG_SE_AES_HW_KEY_EN_LEN    (1U)
+#define SEC_ENG_SE_AES_HW_KEY_EN_MSK    (((1U << SEC_ENG_SE_AES_HW_KEY_EN_LEN) - 1) << SEC_ENG_SE_AES_HW_KEY_EN_POS)
+#define SEC_ENG_SE_AES_HW_KEY_EN_UMSK   (~(((1U << SEC_ENG_SE_AES_HW_KEY_EN_LEN) - 1) << SEC_ENG_SE_AES_HW_KEY_EN_POS))
+#define SEC_ENG_SE_AES_INT              SEC_ENG_SE_AES_INT
+#define SEC_ENG_SE_AES_INT_POS          (8U)
+#define SEC_ENG_SE_AES_INT_LEN          (1U)
+#define SEC_ENG_SE_AES_INT_MSK          (((1U << SEC_ENG_SE_AES_INT_LEN) - 1) << SEC_ENG_SE_AES_INT_POS)
+#define SEC_ENG_SE_AES_INT_UMSK         (~(((1U << SEC_ENG_SE_AES_INT_LEN) - 1) << SEC_ENG_SE_AES_INT_POS))
+#define SEC_ENG_SE_AES_INT_CLR_1T       SEC_ENG_SE_AES_INT_CLR_1T
+#define SEC_ENG_SE_AES_INT_CLR_1T_POS   (9U)
+#define SEC_ENG_SE_AES_INT_CLR_1T_LEN   (1U)
+#define SEC_ENG_SE_AES_INT_CLR_1T_MSK   (((1U << SEC_ENG_SE_AES_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_AES_INT_CLR_1T_POS)
+#define SEC_ENG_SE_AES_INT_CLR_1T_UMSK  (~(((1U << SEC_ENG_SE_AES_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_AES_INT_CLR_1T_POS))
+#define SEC_ENG_SE_AES_INT_SET_1T       SEC_ENG_SE_AES_INT_SET_1T
+#define SEC_ENG_SE_AES_INT_SET_1T_POS   (10U)
+#define SEC_ENG_SE_AES_INT_SET_1T_LEN   (1U)
+#define SEC_ENG_SE_AES_INT_SET_1T_MSK   (((1U << SEC_ENG_SE_AES_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_AES_INT_SET_1T_POS)
+#define SEC_ENG_SE_AES_INT_SET_1T_UMSK  (~(((1U << SEC_ENG_SE_AES_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_AES_INT_SET_1T_POS))
+#define SEC_ENG_SE_AES_INT_MASK         SEC_ENG_SE_AES_INT_MASK
+#define SEC_ENG_SE_AES_INT_MASK_POS     (11U)
+#define SEC_ENG_SE_AES_INT_MASK_LEN     (1U)
+#define SEC_ENG_SE_AES_INT_MASK_MSK     (((1U << SEC_ENG_SE_AES_INT_MASK_LEN) - 1) << SEC_ENG_SE_AES_INT_MASK_POS)
+#define SEC_ENG_SE_AES_INT_MASK_UMSK    (~(((1U << SEC_ENG_SE_AES_INT_MASK_LEN) - 1) << SEC_ENG_SE_AES_INT_MASK_POS))
+#define SEC_ENG_SE_AES_BLOCK_MODE       SEC_ENG_SE_AES_BLOCK_MODE
+#define SEC_ENG_SE_AES_BLOCK_MODE_POS   (12U)
+#define SEC_ENG_SE_AES_BLOCK_MODE_LEN   (2U)
+#define SEC_ENG_SE_AES_BLOCK_MODE_MSK   (((1U << SEC_ENG_SE_AES_BLOCK_MODE_LEN) - 1) << SEC_ENG_SE_AES_BLOCK_MODE_POS)
+#define SEC_ENG_SE_AES_BLOCK_MODE_UMSK  (~(((1U << SEC_ENG_SE_AES_BLOCK_MODE_LEN) - 1) << SEC_ENG_SE_AES_BLOCK_MODE_POS))
+#define SEC_ENG_SE_AES_IV_SEL           SEC_ENG_SE_AES_IV_SEL
+#define SEC_ENG_SE_AES_IV_SEL_POS       (14U)
+#define SEC_ENG_SE_AES_IV_SEL_LEN       (1U)
+#define SEC_ENG_SE_AES_IV_SEL_MSK       (((1U << SEC_ENG_SE_AES_IV_SEL_LEN) - 1) << SEC_ENG_SE_AES_IV_SEL_POS)
+#define SEC_ENG_SE_AES_IV_SEL_UMSK      (~(((1U << SEC_ENG_SE_AES_IV_SEL_LEN) - 1) << SEC_ENG_SE_AES_IV_SEL_POS))
+#define SEC_ENG_SE_AES_LINK_MODE        SEC_ENG_SE_AES_LINK_MODE
+#define SEC_ENG_SE_AES_LINK_MODE_POS    (15U)
+#define SEC_ENG_SE_AES_LINK_MODE_LEN    (1U)
+#define SEC_ENG_SE_AES_LINK_MODE_MSK    (((1U << SEC_ENG_SE_AES_LINK_MODE_LEN) - 1) << SEC_ENG_SE_AES_LINK_MODE_POS)
+#define SEC_ENG_SE_AES_LINK_MODE_UMSK   (~(((1U << SEC_ENG_SE_AES_LINK_MODE_LEN) - 1) << SEC_ENG_SE_AES_LINK_MODE_POS))
+#define SEC_ENG_SE_AES_MSG_LEN          SEC_ENG_SE_AES_MSG_LEN
+#define SEC_ENG_SE_AES_MSG_LEN_POS      (16U)
+#define SEC_ENG_SE_AES_MSG_LEN_LEN      (16U)
+#define SEC_ENG_SE_AES_MSG_LEN_MSK      (((1U << SEC_ENG_SE_AES_MSG_LEN_LEN) - 1) << SEC_ENG_SE_AES_MSG_LEN_POS)
+#define SEC_ENG_SE_AES_MSG_LEN_UMSK     (~(((1U << SEC_ENG_SE_AES_MSG_LEN_LEN) - 1) << SEC_ENG_SE_AES_MSG_LEN_POS))
+
+/* 0x4 : se_aes_msa */
+#define SEC_ENG_SE_AES_MSA_OFFSET (0x4)
+#define SEC_ENG_SE_AES_MSA        SEC_ENG_SE_AES_MSA
+#define SEC_ENG_SE_AES_MSA_POS    (0U)
+#define SEC_ENG_SE_AES_MSA_LEN    (32U)
+#define SEC_ENG_SE_AES_MSA_MSK    (((1U << SEC_ENG_SE_AES_MSA_LEN) - 1) << SEC_ENG_SE_AES_MSA_POS)
+#define SEC_ENG_SE_AES_MSA_UMSK   (~(((1U << SEC_ENG_SE_AES_MSA_LEN) - 1) << SEC_ENG_SE_AES_MSA_POS))
+
+/* 0x8 : se_aes_mda */
+#define SEC_ENG_SE_AES_MDA_OFFSET (0x8)
+#define SEC_ENG_SE_AES_MDA        SEC_ENG_SE_AES_MDA
+#define SEC_ENG_SE_AES_MDA_POS    (0U)
+#define SEC_ENG_SE_AES_MDA_LEN    (32U)
+#define SEC_ENG_SE_AES_MDA_MSK    (((1U << SEC_ENG_SE_AES_MDA_LEN) - 1) << SEC_ENG_SE_AES_MDA_POS)
+#define SEC_ENG_SE_AES_MDA_UMSK   (~(((1U << SEC_ENG_SE_AES_MDA_LEN) - 1) << SEC_ENG_SE_AES_MDA_POS))
+
+/* 0xc : se_aes_status */
+#define SEC_ENG_SE_AES_STATUS_OFFSET (0xc)
+#define SEC_ENG_SE_AES_STATUS        SEC_ENG_SE_AES_STATUS
+#define SEC_ENG_SE_AES_STATUS_POS    (0U)
+#define SEC_ENG_SE_AES_STATUS_LEN    (32U)
+#define SEC_ENG_SE_AES_STATUS_MSK    (((1U << SEC_ENG_SE_AES_STATUS_LEN) - 1) << SEC_ENG_SE_AES_STATUS_POS)
+#define SEC_ENG_SE_AES_STATUS_UMSK   (~(((1U << SEC_ENG_SE_AES_STATUS_LEN) - 1) << SEC_ENG_SE_AES_STATUS_POS))
+
+/* 0x10 : se_aes_iv_0 */
+#define SEC_ENG_SE_AES_IV_0_OFFSET (0x10)
+#define SEC_ENG_SE_AES_IV_0        SEC_ENG_SE_AES_IV_0
+#define SEC_ENG_SE_AES_IV_0_POS    (0U)
+#define SEC_ENG_SE_AES_IV_0_LEN    (32U)
+#define SEC_ENG_SE_AES_IV_0_MSK    (((1U << SEC_ENG_SE_AES_IV_0_LEN) - 1) << SEC_ENG_SE_AES_IV_0_POS)
+#define SEC_ENG_SE_AES_IV_0_UMSK   (~(((1U << SEC_ENG_SE_AES_IV_0_LEN) - 1) << SEC_ENG_SE_AES_IV_0_POS))
+
+/* 0x14 : se_aes_iv_1 */
+#define SEC_ENG_SE_AES_IV_1_OFFSET (0x14)
+#define SEC_ENG_SE_AES_IV_1        SEC_ENG_SE_AES_IV_1
+#define SEC_ENG_SE_AES_IV_1_POS    (0U)
+#define SEC_ENG_SE_AES_IV_1_LEN    (32U)
+#define SEC_ENG_SE_AES_IV_1_MSK    (((1U << SEC_ENG_SE_AES_IV_1_LEN) - 1) << SEC_ENG_SE_AES_IV_1_POS)
+#define SEC_ENG_SE_AES_IV_1_UMSK   (~(((1U << SEC_ENG_SE_AES_IV_1_LEN) - 1) << SEC_ENG_SE_AES_IV_1_POS))
+
+/* 0x18 : se_aes_iv_2 */
+#define SEC_ENG_SE_AES_IV_2_OFFSET (0x18)
+#define SEC_ENG_SE_AES_IV_2        SEC_ENG_SE_AES_IV_2
+#define SEC_ENG_SE_AES_IV_2_POS    (0U)
+#define SEC_ENG_SE_AES_IV_2_LEN    (32U)
+#define SEC_ENG_SE_AES_IV_2_MSK    (((1U << SEC_ENG_SE_AES_IV_2_LEN) - 1) << SEC_ENG_SE_AES_IV_2_POS)
+#define SEC_ENG_SE_AES_IV_2_UMSK   (~(((1U << SEC_ENG_SE_AES_IV_2_LEN) - 1) << SEC_ENG_SE_AES_IV_2_POS))
+
+/* 0x1c : se_aes_iv_3 */
+#define SEC_ENG_SE_AES_IV_3_OFFSET (0x1c)
+#define SEC_ENG_SE_AES_IV_3        SEC_ENG_SE_AES_IV_3
+#define SEC_ENG_SE_AES_IV_3_POS    (0U)
+#define SEC_ENG_SE_AES_IV_3_LEN    (32U)
+#define SEC_ENG_SE_AES_IV_3_MSK    (((1U << SEC_ENG_SE_AES_IV_3_LEN) - 1) << SEC_ENG_SE_AES_IV_3_POS)
+#define SEC_ENG_SE_AES_IV_3_UMSK   (~(((1U << SEC_ENG_SE_AES_IV_3_LEN) - 1) << SEC_ENG_SE_AES_IV_3_POS))
+
+/* 0x20 : se_aes_key_0 */
+#define SEC_ENG_SE_AES_KEY_0_OFFSET (0x20)
+#define SEC_ENG_SE_AES_KEY_0        SEC_ENG_SE_AES_KEY_0
+#define SEC_ENG_SE_AES_KEY_0_POS    (0U)
+#define SEC_ENG_SE_AES_KEY_0_LEN    (32U)
+#define SEC_ENG_SE_AES_KEY_0_MSK    (((1U << SEC_ENG_SE_AES_KEY_0_LEN) - 1) << SEC_ENG_SE_AES_KEY_0_POS)
+#define SEC_ENG_SE_AES_KEY_0_UMSK   (~(((1U << SEC_ENG_SE_AES_KEY_0_LEN) - 1) << SEC_ENG_SE_AES_KEY_0_POS))
+
+/* 0x24 : se_aes_key_1 */
+#define SEC_ENG_SE_AES_KEY_1_OFFSET (0x24)
+#define SEC_ENG_SE_AES_KEY_1        SEC_ENG_SE_AES_KEY_1
+#define SEC_ENG_SE_AES_KEY_1_POS    (0U)
+#define SEC_ENG_SE_AES_KEY_1_LEN    (32U)
+#define SEC_ENG_SE_AES_KEY_1_MSK    (((1U << SEC_ENG_SE_AES_KEY_1_LEN) - 1) << SEC_ENG_SE_AES_KEY_1_POS)
+#define SEC_ENG_SE_AES_KEY_1_UMSK   (~(((1U << SEC_ENG_SE_AES_KEY_1_LEN) - 1) << SEC_ENG_SE_AES_KEY_1_POS))
+
+/* 0x28 : se_aes_key_2 */
+#define SEC_ENG_SE_AES_KEY_2_OFFSET (0x28)
+#define SEC_ENG_SE_AES_KEY_2        SEC_ENG_SE_AES_KEY_2
+#define SEC_ENG_SE_AES_KEY_2_POS    (0U)
+#define SEC_ENG_SE_AES_KEY_2_LEN    (32U)
+#define SEC_ENG_SE_AES_KEY_2_MSK    (((1U << SEC_ENG_SE_AES_KEY_2_LEN) - 1) << SEC_ENG_SE_AES_KEY_2_POS)
+#define SEC_ENG_SE_AES_KEY_2_UMSK   (~(((1U << SEC_ENG_SE_AES_KEY_2_LEN) - 1) << SEC_ENG_SE_AES_KEY_2_POS))
+
+/* 0x2c : se_aes_key_3 */
+#define SEC_ENG_SE_AES_KEY_3_OFFSET (0x2c)
+#define SEC_ENG_SE_AES_KEY_3        SEC_ENG_SE_AES_KEY_3
+#define SEC_ENG_SE_AES_KEY_3_POS    (0U)
+#define SEC_ENG_SE_AES_KEY_3_LEN    (32U)
+#define SEC_ENG_SE_AES_KEY_3_MSK    (((1U << SEC_ENG_SE_AES_KEY_3_LEN) - 1) << SEC_ENG_SE_AES_KEY_3_POS)
+#define SEC_ENG_SE_AES_KEY_3_UMSK   (~(((1U << SEC_ENG_SE_AES_KEY_3_LEN) - 1) << SEC_ENG_SE_AES_KEY_3_POS))
+
+/* 0x30 : se_aes_key_4 */
+#define SEC_ENG_SE_AES_KEY_4_OFFSET (0x30)
+#define SEC_ENG_SE_AES_KEY_4        SEC_ENG_SE_AES_KEY_4
+#define SEC_ENG_SE_AES_KEY_4_POS    (0U)
+#define SEC_ENG_SE_AES_KEY_4_LEN    (32U)
+#define SEC_ENG_SE_AES_KEY_4_MSK    (((1U << SEC_ENG_SE_AES_KEY_4_LEN) - 1) << SEC_ENG_SE_AES_KEY_4_POS)
+#define SEC_ENG_SE_AES_KEY_4_UMSK   (~(((1U << SEC_ENG_SE_AES_KEY_4_LEN) - 1) << SEC_ENG_SE_AES_KEY_4_POS))
+
+/* 0x34 : se_aes_key_5 */
+#define SEC_ENG_SE_AES_KEY_5_OFFSET (0x34)
+#define SEC_ENG_SE_AES_KEY_5        SEC_ENG_SE_AES_KEY_5
+#define SEC_ENG_SE_AES_KEY_5_POS    (0U)
+#define SEC_ENG_SE_AES_KEY_5_LEN    (32U)
+#define SEC_ENG_SE_AES_KEY_5_MSK    (((1U << SEC_ENG_SE_AES_KEY_5_LEN) - 1) << SEC_ENG_SE_AES_KEY_5_POS)
+#define SEC_ENG_SE_AES_KEY_5_UMSK   (~(((1U << SEC_ENG_SE_AES_KEY_5_LEN) - 1) << SEC_ENG_SE_AES_KEY_5_POS))
+
+/* 0x38 : se_aes_key_6 */
+#define SEC_ENG_SE_AES_KEY_6_OFFSET (0x38)
+#define SEC_ENG_SE_AES_KEY_6        SEC_ENG_SE_AES_KEY_6
+#define SEC_ENG_SE_AES_KEY_6_POS    (0U)
+#define SEC_ENG_SE_AES_KEY_6_LEN    (32U)
+#define SEC_ENG_SE_AES_KEY_6_MSK    (((1U << SEC_ENG_SE_AES_KEY_6_LEN) - 1) << SEC_ENG_SE_AES_KEY_6_POS)
+#define SEC_ENG_SE_AES_KEY_6_UMSK   (~(((1U << SEC_ENG_SE_AES_KEY_6_LEN) - 1) << SEC_ENG_SE_AES_KEY_6_POS))
+
+/* 0x3c : se_aes_key_7 */
+#define SEC_ENG_SE_AES_KEY_7_OFFSET (0x3c)
+#define SEC_ENG_SE_AES_KEY_7        SEC_ENG_SE_AES_KEY_7
+#define SEC_ENG_SE_AES_KEY_7_POS    (0U)
+#define SEC_ENG_SE_AES_KEY_7_LEN    (32U)
+#define SEC_ENG_SE_AES_KEY_7_MSK    (((1U << SEC_ENG_SE_AES_KEY_7_LEN) - 1) << SEC_ENG_SE_AES_KEY_7_POS)
+#define SEC_ENG_SE_AES_KEY_7_UMSK   (~(((1U << SEC_ENG_SE_AES_KEY_7_LEN) - 1) << SEC_ENG_SE_AES_KEY_7_POS))
+
+/* 0x40 : se_aes_key_sel_0 */
+#define SEC_ENG_SE_AES_KEY_SEL_0_OFFSET (0x40)
+#define SEC_ENG_SE_AES_KEY_SEL_0        SEC_ENG_SE_AES_KEY_SEL_0
+#define SEC_ENG_SE_AES_KEY_SEL_0_POS    (0U)
+#define SEC_ENG_SE_AES_KEY_SEL_0_LEN    (2U)
+#define SEC_ENG_SE_AES_KEY_SEL_0_MSK    (((1U << SEC_ENG_SE_AES_KEY_SEL_0_LEN) - 1) << SEC_ENG_SE_AES_KEY_SEL_0_POS)
+#define SEC_ENG_SE_AES_KEY_SEL_0_UMSK   (~(((1U << SEC_ENG_SE_AES_KEY_SEL_0_LEN) - 1) << SEC_ENG_SE_AES_KEY_SEL_0_POS))
+
+/* 0x44 : se_aes_key_sel_1 */
+#define SEC_ENG_SE_AES_KEY_SEL_1_OFFSET (0x44)
+#define SEC_ENG_SE_AES_KEY_SEL_1        SEC_ENG_SE_AES_KEY_SEL_1
+#define SEC_ENG_SE_AES_KEY_SEL_1_POS    (0U)
+#define SEC_ENG_SE_AES_KEY_SEL_1_LEN    (2U)
+#define SEC_ENG_SE_AES_KEY_SEL_1_MSK    (((1U << SEC_ENG_SE_AES_KEY_SEL_1_LEN) - 1) << SEC_ENG_SE_AES_KEY_SEL_1_POS)
+#define SEC_ENG_SE_AES_KEY_SEL_1_UMSK   (~(((1U << SEC_ENG_SE_AES_KEY_SEL_1_LEN) - 1) << SEC_ENG_SE_AES_KEY_SEL_1_POS))
+
+/* 0x48 : se_aes_endian */
+#define SEC_ENG_SE_AES_ENDIAN_OFFSET    (0x48)
+#define SEC_ENG_SE_AES_DOUT_ENDIAN      SEC_ENG_SE_AES_DOUT_ENDIAN
+#define SEC_ENG_SE_AES_DOUT_ENDIAN_POS  (0U)
+#define SEC_ENG_SE_AES_DOUT_ENDIAN_LEN  (1U)
+#define SEC_ENG_SE_AES_DOUT_ENDIAN_MSK  (((1U << SEC_ENG_SE_AES_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_DOUT_ENDIAN_POS)
+#define SEC_ENG_SE_AES_DOUT_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_DOUT_ENDIAN_POS))
+#define SEC_ENG_SE_AES_DIN_ENDIAN       SEC_ENG_SE_AES_DIN_ENDIAN
+#define SEC_ENG_SE_AES_DIN_ENDIAN_POS   (1U)
+#define SEC_ENG_SE_AES_DIN_ENDIAN_LEN   (1U)
+#define SEC_ENG_SE_AES_DIN_ENDIAN_MSK   (((1U << SEC_ENG_SE_AES_DIN_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_DIN_ENDIAN_POS)
+#define SEC_ENG_SE_AES_DIN_ENDIAN_UMSK  (~(((1U << SEC_ENG_SE_AES_DIN_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_DIN_ENDIAN_POS))
+#define SEC_ENG_SE_AES_KEY_ENDIAN       SEC_ENG_SE_AES_KEY_ENDIAN
+#define SEC_ENG_SE_AES_KEY_ENDIAN_POS   (2U)
+#define SEC_ENG_SE_AES_KEY_ENDIAN_LEN   (1U)
+#define SEC_ENG_SE_AES_KEY_ENDIAN_MSK   (((1U << SEC_ENG_SE_AES_KEY_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_KEY_ENDIAN_POS)
+#define SEC_ENG_SE_AES_KEY_ENDIAN_UMSK  (~(((1U << SEC_ENG_SE_AES_KEY_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_KEY_ENDIAN_POS))
+#define SEC_ENG_SE_AES_IV_ENDIAN        SEC_ENG_SE_AES_IV_ENDIAN
+#define SEC_ENG_SE_AES_IV_ENDIAN_POS    (3U)
+#define SEC_ENG_SE_AES_IV_ENDIAN_LEN    (1U)
+#define SEC_ENG_SE_AES_IV_ENDIAN_MSK    (((1U << SEC_ENG_SE_AES_IV_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_IV_ENDIAN_POS)
+#define SEC_ENG_SE_AES_IV_ENDIAN_UMSK   (~(((1U << SEC_ENG_SE_AES_IV_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_IV_ENDIAN_POS))
+#define SEC_ENG_SE_AES_CTR_LEN          SEC_ENG_SE_AES_CTR_LEN
+#define SEC_ENG_SE_AES_CTR_LEN_POS      (30U)
+#define SEC_ENG_SE_AES_CTR_LEN_LEN      (2U)
+#define SEC_ENG_SE_AES_CTR_LEN_MSK      (((1U << SEC_ENG_SE_AES_CTR_LEN_LEN) - 1) << SEC_ENG_SE_AES_CTR_LEN_POS)
+#define SEC_ENG_SE_AES_CTR_LEN_UMSK     (~(((1U << SEC_ENG_SE_AES_CTR_LEN_LEN) - 1) << SEC_ENG_SE_AES_CTR_LEN_POS))
+
+/* 0x4c : se_aes_sboot */
+#define SEC_ENG_SE_AES_SBOOT_OFFSET       (0x4c)
+#define SEC_ENG_SE_AES_SBOOT_KEY_SEL      SEC_ENG_SE_AES_SBOOT_KEY_SEL
+#define SEC_ENG_SE_AES_SBOOT_KEY_SEL_POS  (0U)
+#define SEC_ENG_SE_AES_SBOOT_KEY_SEL_LEN  (1U)
+#define SEC_ENG_SE_AES_SBOOT_KEY_SEL_MSK  (((1U << SEC_ENG_SE_AES_SBOOT_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_SBOOT_KEY_SEL_POS)
+#define SEC_ENG_SE_AES_SBOOT_KEY_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_SBOOT_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_SBOOT_KEY_SEL_POS))
+
+/* 0x50 : se_aes_link */
+#define SEC_ENG_SE_AES_LINK_OFFSET (0x50)
+#define SEC_ENG_SE_AES_LCA         SEC_ENG_SE_AES_LCA
+#define SEC_ENG_SE_AES_LCA_POS     (0U)
+#define SEC_ENG_SE_AES_LCA_LEN     (32U)
+#define SEC_ENG_SE_AES_LCA_MSK     (((1U << SEC_ENG_SE_AES_LCA_LEN) - 1) << SEC_ENG_SE_AES_LCA_POS)
+#define SEC_ENG_SE_AES_LCA_UMSK    (~(((1U << SEC_ENG_SE_AES_LCA_LEN) - 1) << SEC_ENG_SE_AES_LCA_POS))
+
+/* 0xfc : se_aes_ctrl_prot */
+#define SEC_ENG_SE_AES_CTRL_PROT_OFFSET (0xfc)
+#define SEC_ENG_SE_AES_PROT_EN          SEC_ENG_SE_AES_PROT_EN
+#define SEC_ENG_SE_AES_PROT_EN_POS      (0U)
+#define SEC_ENG_SE_AES_PROT_EN_LEN      (1U)
+#define SEC_ENG_SE_AES_PROT_EN_MSK      (((1U << SEC_ENG_SE_AES_PROT_EN_LEN) - 1) << SEC_ENG_SE_AES_PROT_EN_POS)
+#define SEC_ENG_SE_AES_PROT_EN_UMSK     (~(((1U << SEC_ENG_SE_AES_PROT_EN_LEN) - 1) << SEC_ENG_SE_AES_PROT_EN_POS))
+#define SEC_ENG_SE_AES_ID0_EN           SEC_ENG_SE_AES_ID0_EN
+#define SEC_ENG_SE_AES_ID0_EN_POS       (1U)
+#define SEC_ENG_SE_AES_ID0_EN_LEN       (1U)
+#define SEC_ENG_SE_AES_ID0_EN_MSK       (((1U << SEC_ENG_SE_AES_ID0_EN_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_POS)
+#define SEC_ENG_SE_AES_ID0_EN_UMSK      (~(((1U << SEC_ENG_SE_AES_ID0_EN_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_POS))
+#define SEC_ENG_SE_AES_ID1_EN           SEC_ENG_SE_AES_ID1_EN
+#define SEC_ENG_SE_AES_ID1_EN_POS       (2U)
+#define SEC_ENG_SE_AES_ID1_EN_LEN       (1U)
+#define SEC_ENG_SE_AES_ID1_EN_MSK       (((1U << SEC_ENG_SE_AES_ID1_EN_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_POS)
+#define SEC_ENG_SE_AES_ID1_EN_UMSK      (~(((1U << SEC_ENG_SE_AES_ID1_EN_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_POS))
+
+struct sec_eng_aes_reg {
+    /* 0x0 : se_aes_ctrl */
+    union {
+        struct
+        {
+            uint32_t se_aes_busy        : 1;  /* [    0],          r,        0x0 */
+            uint32_t se_aes_trig_1t     : 1;  /* [    1],        w1p,        0x0 */
+            uint32_t se_aes_en          : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t se_aes_mode        : 2;  /* [ 4: 3],        r/w,        0x0 */
+            uint32_t se_aes_dec_en      : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t se_aes_dec_key_sel : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t se_aes_hw_key_en   : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t se_aes_int         : 1;  /* [    8],          r,        0x0 */
+            uint32_t se_aes_int_clr_1t  : 1;  /* [    9],        w1p,        0x0 */
+            uint32_t se_aes_int_set_1t  : 1;  /* [   10],        w1p,        0x0 */
+            uint32_t se_aes_int_mask    : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t se_aes_block_mode  : 2;  /* [13:12],        r/w,        0x0 */
+            uint32_t se_aes_iv_sel      : 1;  /* [   14],        r/w,        0x0 */
+            uint32_t se_aes_link_mode   : 1;  /* [   15],        r/w,        0x0 */
+            uint32_t se_aes_msg_len     : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_ctrl;
+
+    /* 0x4 : se_aes_msa */
+    union {
+        struct
+        {
+            uint32_t se_aes_msa : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_msa;
+
+    /* 0x8 : se_aes_mda */
+    union {
+        struct
+        {
+            uint32_t se_aes_mda : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_mda;
+
+    /* 0xc : se_aes_status */
+    union {
+        struct
+        {
+            uint32_t se_aes_status : 32; /* [31: 0],          r,      0x100 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_status;
+
+    /* 0x10 : se_aes_iv_0 */
+    union {
+        struct
+        {
+            uint32_t se_aes_iv_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_iv_0;
+
+    /* 0x14 : se_aes_iv_1 */
+    union {
+        struct
+        {
+            uint32_t se_aes_iv_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_iv_1;
+
+    /* 0x18 : se_aes_iv_2 */
+    union {
+        struct
+        {
+            uint32_t se_aes_iv_2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_iv_2;
+
+    /* 0x1c : se_aes_iv_3 */
+    union {
+        struct
+        {
+            uint32_t se_aes_iv_3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_iv_3;
+
+    /* 0x20 : se_aes_key_0 */
+    union {
+        struct
+        {
+            uint32_t se_aes_key_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_key_0;
+
+    /* 0x24 : se_aes_key_1 */
+    union {
+        struct
+        {
+            uint32_t se_aes_key_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_key_1;
+
+    /* 0x28 : se_aes_key_2 */
+    union {
+        struct
+        {
+            uint32_t se_aes_key_2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_key_2;
+
+    /* 0x2c : se_aes_key_3 */
+    union {
+        struct
+        {
+            uint32_t se_aes_key_3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_key_3;
+
+    /* 0x30 : se_aes_key_4 */
+    union {
+        struct
+        {
+            uint32_t se_aes_key_4 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_key_4;
+
+    /* 0x34 : se_aes_key_5 */
+    union {
+        struct
+        {
+            uint32_t se_aes_key_5 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_key_5;
+
+    /* 0x38 : se_aes_key_6 */
+    union {
+        struct
+        {
+            uint32_t se_aes_key_6 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_key_6;
+
+    /* 0x3c : se_aes_key_7 */
+    union {
+        struct
+        {
+            uint32_t se_aes_key_7 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_key_7;
+
+    /* 0x40 : se_aes_key_sel_0 */
+    union {
+        struct
+        {
+            uint32_t se_aes_key_sel_0 : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_31    : 30; /* [31: 2],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_key_sel_0;
+
+    /* 0x44 : se_aes_key_sel_1 */
+    union {
+        struct
+        {
+            uint32_t se_aes_key_sel_1 : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_31    : 30; /* [31: 2],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_key_sel_1;
+
+    /* 0x48 : se_aes_endian */
+    union {
+        struct
+        {
+            uint32_t se_aes_dout_endian : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t se_aes_din_endian  : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t se_aes_key_endian  : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t se_aes_iv_endian   : 1;  /* [    3],        r/w,        0x1 */
+            uint32_t reserved_4_29      : 26; /* [29: 4],       rsvd,        0x0 */
+            uint32_t se_aes_ctr_len     : 2;  /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_endian;
+
+    /* 0x4c : se_aes_sboot */
+    union {
+        struct
+        {
+            uint32_t se_aes_sboot_key_sel : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_31        : 31; /* [31: 1],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_sboot;
+
+    /* 0x50 : se_aes_link */
+    union {
+        struct
+        {
+            uint32_t se_aes_lca : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_link;
+
+    /* 0x54  reserved */
+    uint8_t RESERVED0x54[168];
+
+    /* 0xfc : se_aes_ctrl_prot */
+    union {
+        struct
+        {
+            uint32_t se_aes_prot_en : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t se_aes_id0_en  : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t se_aes_id1_en  : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t reserved_3_31  : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_aes_ctrl_prot;
+};
+
+typedef volatile struct sec_eng_aes_reg sec_eng_aes_reg_t;
+
+#define SEC_ENG_AES_OFFSET 0x100
+
+/*Following is reg patch*/
+
+/* 0x0 : se_trng_ctrl_0 */
+#define SEC_ENG_SE_TRNG_CTRL_0_OFFSET       (0x0)
+#define SEC_ENG_SE_TRNG_BUSY                SEC_ENG_SE_TRNG_BUSY
+#define SEC_ENG_SE_TRNG_BUSY_POS            (0U)
+#define SEC_ENG_SE_TRNG_BUSY_LEN            (1U)
+#define SEC_ENG_SE_TRNG_BUSY_MSK            (((1U << SEC_ENG_SE_TRNG_BUSY_LEN) - 1) << SEC_ENG_SE_TRNG_BUSY_POS)
+#define SEC_ENG_SE_TRNG_BUSY_UMSK           (~(((1U << SEC_ENG_SE_TRNG_BUSY_LEN) - 1) << SEC_ENG_SE_TRNG_BUSY_POS))
+#define SEC_ENG_SE_TRNG_TRIG_1T             SEC_ENG_SE_TRNG_TRIG_1T
+#define SEC_ENG_SE_TRNG_TRIG_1T_POS         (1U)
+#define SEC_ENG_SE_TRNG_TRIG_1T_LEN         (1U)
+#define SEC_ENG_SE_TRNG_TRIG_1T_MSK         (((1U << SEC_ENG_SE_TRNG_TRIG_1T_LEN) - 1) << SEC_ENG_SE_TRNG_TRIG_1T_POS)
+#define SEC_ENG_SE_TRNG_TRIG_1T_UMSK        (~(((1U << SEC_ENG_SE_TRNG_TRIG_1T_LEN) - 1) << SEC_ENG_SE_TRNG_TRIG_1T_POS))
+#define SEC_ENG_SE_TRNG_EN                  SEC_ENG_SE_TRNG_EN
+#define SEC_ENG_SE_TRNG_EN_POS              (2U)
+#define SEC_ENG_SE_TRNG_EN_LEN              (1U)
+#define SEC_ENG_SE_TRNG_EN_MSK              (((1U << SEC_ENG_SE_TRNG_EN_LEN) - 1) << SEC_ENG_SE_TRNG_EN_POS)
+#define SEC_ENG_SE_TRNG_EN_UMSK             (~(((1U << SEC_ENG_SE_TRNG_EN_LEN) - 1) << SEC_ENG_SE_TRNG_EN_POS))
+#define SEC_ENG_SE_TRNG_DOUT_CLR_1T         SEC_ENG_SE_TRNG_DOUT_CLR_1T
+#define SEC_ENG_SE_TRNG_DOUT_CLR_1T_POS     (3U)
+#define SEC_ENG_SE_TRNG_DOUT_CLR_1T_LEN     (1U)
+#define SEC_ENG_SE_TRNG_DOUT_CLR_1T_MSK     (((1U << SEC_ENG_SE_TRNG_DOUT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_CLR_1T_POS)
+#define SEC_ENG_SE_TRNG_DOUT_CLR_1T_UMSK    (~(((1U << SEC_ENG_SE_TRNG_DOUT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_CLR_1T_POS))
+#define SEC_ENG_SE_TRNG_HT_ERROR            SEC_ENG_SE_TRNG_HT_ERROR
+#define SEC_ENG_SE_TRNG_HT_ERROR_POS        (4U)
+#define SEC_ENG_SE_TRNG_HT_ERROR_LEN        (1U)
+#define SEC_ENG_SE_TRNG_HT_ERROR_MSK        (((1U << SEC_ENG_SE_TRNG_HT_ERROR_LEN) - 1) << SEC_ENG_SE_TRNG_HT_ERROR_POS)
+#define SEC_ENG_SE_TRNG_HT_ERROR_UMSK       (~(((1U << SEC_ENG_SE_TRNG_HT_ERROR_LEN) - 1) << SEC_ENG_SE_TRNG_HT_ERROR_POS))
+#define SEC_ENG_SE_TRNG_INT                 SEC_ENG_SE_TRNG_INT
+#define SEC_ENG_SE_TRNG_INT_POS             (8U)
+#define SEC_ENG_SE_TRNG_INT_LEN             (1U)
+#define SEC_ENG_SE_TRNG_INT_MSK             (((1U << SEC_ENG_SE_TRNG_INT_LEN) - 1) << SEC_ENG_SE_TRNG_INT_POS)
+#define SEC_ENG_SE_TRNG_INT_UMSK            (~(((1U << SEC_ENG_SE_TRNG_INT_LEN) - 1) << SEC_ENG_SE_TRNG_INT_POS))
+#define SEC_ENG_SE_TRNG_INT_CLR_1T          SEC_ENG_SE_TRNG_INT_CLR_1T
+#define SEC_ENG_SE_TRNG_INT_CLR_1T_POS      (9U)
+#define SEC_ENG_SE_TRNG_INT_CLR_1T_LEN      (1U)
+#define SEC_ENG_SE_TRNG_INT_CLR_1T_MSK      (((1U << SEC_ENG_SE_TRNG_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_INT_CLR_1T_POS)
+#define SEC_ENG_SE_TRNG_INT_CLR_1T_UMSK     (~(((1U << SEC_ENG_SE_TRNG_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_INT_CLR_1T_POS))
+#define SEC_ENG_SE_TRNG_INT_SET_1T          SEC_ENG_SE_TRNG_INT_SET_1T
+#define SEC_ENG_SE_TRNG_INT_SET_1T_POS      (10U)
+#define SEC_ENG_SE_TRNG_INT_SET_1T_LEN      (1U)
+#define SEC_ENG_SE_TRNG_INT_SET_1T_MSK      (((1U << SEC_ENG_SE_TRNG_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_TRNG_INT_SET_1T_POS)
+#define SEC_ENG_SE_TRNG_INT_SET_1T_UMSK     (~(((1U << SEC_ENG_SE_TRNG_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_TRNG_INT_SET_1T_POS))
+#define SEC_ENG_SE_TRNG_INT_MASK            SEC_ENG_SE_TRNG_INT_MASK
+#define SEC_ENG_SE_TRNG_INT_MASK_POS        (11U)
+#define SEC_ENG_SE_TRNG_INT_MASK_LEN        (1U)
+#define SEC_ENG_SE_TRNG_INT_MASK_MSK        (((1U << SEC_ENG_SE_TRNG_INT_MASK_LEN) - 1) << SEC_ENG_SE_TRNG_INT_MASK_POS)
+#define SEC_ENG_SE_TRNG_INT_MASK_UMSK       (~(((1U << SEC_ENG_SE_TRNG_INT_MASK_LEN) - 1) << SEC_ENG_SE_TRNG_INT_MASK_POS))
+#define SEC_ENG_SE_TRNG_MANUAL_FUN_SEL      SEC_ENG_SE_TRNG_MANUAL_FUN_SEL
+#define SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_POS  (13U)
+#define SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_LEN  (1U)
+#define SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_MSK  (((1U << SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_LEN) - 1) << SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_POS)
+#define SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_UMSK (~(((1U << SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_LEN) - 1) << SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_POS))
+#define SEC_ENG_SE_TRNG_MANUAL_RESEED       SEC_ENG_SE_TRNG_MANUAL_RESEED
+#define SEC_ENG_SE_TRNG_MANUAL_RESEED_POS   (14U)
+#define SEC_ENG_SE_TRNG_MANUAL_RESEED_LEN   (1U)
+#define SEC_ENG_SE_TRNG_MANUAL_RESEED_MSK   (((1U << SEC_ENG_SE_TRNG_MANUAL_RESEED_LEN) - 1) << SEC_ENG_SE_TRNG_MANUAL_RESEED_POS)
+#define SEC_ENG_SE_TRNG_MANUAL_RESEED_UMSK  (~(((1U << SEC_ENG_SE_TRNG_MANUAL_RESEED_LEN) - 1) << SEC_ENG_SE_TRNG_MANUAL_RESEED_POS))
+#define SEC_ENG_SE_TRNG_MANUAL_EN           SEC_ENG_SE_TRNG_MANUAL_EN
+#define SEC_ENG_SE_TRNG_MANUAL_EN_POS       (15U)
+#define SEC_ENG_SE_TRNG_MANUAL_EN_LEN       (1U)
+#define SEC_ENG_SE_TRNG_MANUAL_EN_MSK       (((1U << SEC_ENG_SE_TRNG_MANUAL_EN_LEN) - 1) << SEC_ENG_SE_TRNG_MANUAL_EN_POS)
+#define SEC_ENG_SE_TRNG_MANUAL_EN_UMSK      (~(((1U << SEC_ENG_SE_TRNG_MANUAL_EN_LEN) - 1) << SEC_ENG_SE_TRNG_MANUAL_EN_POS))
+
+/* 0x4 : se_trng_status */
+#define SEC_ENG_SE_TRNG_STATUS_OFFSET (0x4)
+#define SEC_ENG_SE_TRNG_STATUS        SEC_ENG_SE_TRNG_STATUS
+#define SEC_ENG_SE_TRNG_STATUS_POS    (0U)
+#define SEC_ENG_SE_TRNG_STATUS_LEN    (32U)
+#define SEC_ENG_SE_TRNG_STATUS_MSK    (((1U << SEC_ENG_SE_TRNG_STATUS_LEN) - 1) << SEC_ENG_SE_TRNG_STATUS_POS)
+#define SEC_ENG_SE_TRNG_STATUS_UMSK   (~(((1U << SEC_ENG_SE_TRNG_STATUS_LEN) - 1) << SEC_ENG_SE_TRNG_STATUS_POS))
+
+/* 0x8 : se_trng_dout_0 */
+#define SEC_ENG_SE_TRNG_DOUT_0_OFFSET (0x8)
+#define SEC_ENG_SE_TRNG_DOUT_0        SEC_ENG_SE_TRNG_DOUT_0
+#define SEC_ENG_SE_TRNG_DOUT_0_POS    (0U)
+#define SEC_ENG_SE_TRNG_DOUT_0_LEN    (32U)
+#define SEC_ENG_SE_TRNG_DOUT_0_MSK    (((1U << SEC_ENG_SE_TRNG_DOUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_0_POS)
+#define SEC_ENG_SE_TRNG_DOUT_0_UMSK   (~(((1U << SEC_ENG_SE_TRNG_DOUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_0_POS))
+
+/* 0xc : se_trng_dout_1 */
+#define SEC_ENG_SE_TRNG_DOUT_1_OFFSET (0xc)
+#define SEC_ENG_SE_TRNG_DOUT_1        SEC_ENG_SE_TRNG_DOUT_1
+#define SEC_ENG_SE_TRNG_DOUT_1_POS    (0U)
+#define SEC_ENG_SE_TRNG_DOUT_1_LEN    (32U)
+#define SEC_ENG_SE_TRNG_DOUT_1_MSK    (((1U << SEC_ENG_SE_TRNG_DOUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_1_POS)
+#define SEC_ENG_SE_TRNG_DOUT_1_UMSK   (~(((1U << SEC_ENG_SE_TRNG_DOUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_1_POS))
+
+/* 0x10 : se_trng_dout_2 */
+#define SEC_ENG_SE_TRNG_DOUT_2_OFFSET (0x10)
+#define SEC_ENG_SE_TRNG_DOUT_2        SEC_ENG_SE_TRNG_DOUT_2
+#define SEC_ENG_SE_TRNG_DOUT_2_POS    (0U)
+#define SEC_ENG_SE_TRNG_DOUT_2_LEN    (32U)
+#define SEC_ENG_SE_TRNG_DOUT_2_MSK    (((1U << SEC_ENG_SE_TRNG_DOUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_2_POS)
+#define SEC_ENG_SE_TRNG_DOUT_2_UMSK   (~(((1U << SEC_ENG_SE_TRNG_DOUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_2_POS))
+
+/* 0x14 : se_trng_dout_3 */
+#define SEC_ENG_SE_TRNG_DOUT_3_OFFSET (0x14)
+#define SEC_ENG_SE_TRNG_DOUT_3        SEC_ENG_SE_TRNG_DOUT_3
+#define SEC_ENG_SE_TRNG_DOUT_3_POS    (0U)
+#define SEC_ENG_SE_TRNG_DOUT_3_LEN    (32U)
+#define SEC_ENG_SE_TRNG_DOUT_3_MSK    (((1U << SEC_ENG_SE_TRNG_DOUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_3_POS)
+#define SEC_ENG_SE_TRNG_DOUT_3_UMSK   (~(((1U << SEC_ENG_SE_TRNG_DOUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_3_POS))
+
+/* 0x18 : se_trng_dout_4 */
+#define SEC_ENG_SE_TRNG_DOUT_4_OFFSET (0x18)
+#define SEC_ENG_SE_TRNG_DOUT_4        SEC_ENG_SE_TRNG_DOUT_4
+#define SEC_ENG_SE_TRNG_DOUT_4_POS    (0U)
+#define SEC_ENG_SE_TRNG_DOUT_4_LEN    (32U)
+#define SEC_ENG_SE_TRNG_DOUT_4_MSK    (((1U << SEC_ENG_SE_TRNG_DOUT_4_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_4_POS)
+#define SEC_ENG_SE_TRNG_DOUT_4_UMSK   (~(((1U << SEC_ENG_SE_TRNG_DOUT_4_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_4_POS))
+
+/* 0x1c : se_trng_dout_5 */
+#define SEC_ENG_SE_TRNG_DOUT_5_OFFSET (0x1c)
+#define SEC_ENG_SE_TRNG_DOUT_5        SEC_ENG_SE_TRNG_DOUT_5
+#define SEC_ENG_SE_TRNG_DOUT_5_POS    (0U)
+#define SEC_ENG_SE_TRNG_DOUT_5_LEN    (32U)
+#define SEC_ENG_SE_TRNG_DOUT_5_MSK    (((1U << SEC_ENG_SE_TRNG_DOUT_5_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_5_POS)
+#define SEC_ENG_SE_TRNG_DOUT_5_UMSK   (~(((1U << SEC_ENG_SE_TRNG_DOUT_5_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_5_POS))
+
+/* 0x20 : se_trng_dout_6 */
+#define SEC_ENG_SE_TRNG_DOUT_6_OFFSET (0x20)
+#define SEC_ENG_SE_TRNG_DOUT_6        SEC_ENG_SE_TRNG_DOUT_6
+#define SEC_ENG_SE_TRNG_DOUT_6_POS    (0U)
+#define SEC_ENG_SE_TRNG_DOUT_6_LEN    (32U)
+#define SEC_ENG_SE_TRNG_DOUT_6_MSK    (((1U << SEC_ENG_SE_TRNG_DOUT_6_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_6_POS)
+#define SEC_ENG_SE_TRNG_DOUT_6_UMSK   (~(((1U << SEC_ENG_SE_TRNG_DOUT_6_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_6_POS))
+
+/* 0x24 : se_trng_dout_7 */
+#define SEC_ENG_SE_TRNG_DOUT_7_OFFSET (0x24)
+#define SEC_ENG_SE_TRNG_DOUT_7        SEC_ENG_SE_TRNG_DOUT_7
+#define SEC_ENG_SE_TRNG_DOUT_7_POS    (0U)
+#define SEC_ENG_SE_TRNG_DOUT_7_LEN    (32U)
+#define SEC_ENG_SE_TRNG_DOUT_7_MSK    (((1U << SEC_ENG_SE_TRNG_DOUT_7_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_7_POS)
+#define SEC_ENG_SE_TRNG_DOUT_7_UMSK   (~(((1U << SEC_ENG_SE_TRNG_DOUT_7_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_7_POS))
+
+/* 0x28 : se_trng_test */
+#define SEC_ENG_SE_TRNG_TEST_OFFSET     (0x28)
+#define SEC_ENG_SE_TRNG_TEST_EN         SEC_ENG_SE_TRNG_TEST_EN
+#define SEC_ENG_SE_TRNG_TEST_EN_POS     (0U)
+#define SEC_ENG_SE_TRNG_TEST_EN_LEN     (1U)
+#define SEC_ENG_SE_TRNG_TEST_EN_MSK     (((1U << SEC_ENG_SE_TRNG_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_EN_POS)
+#define SEC_ENG_SE_TRNG_TEST_EN_UMSK    (~(((1U << SEC_ENG_SE_TRNG_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_EN_POS))
+#define SEC_ENG_SE_TRNG_CP_TEST_EN      SEC_ENG_SE_TRNG_CP_TEST_EN
+#define SEC_ENG_SE_TRNG_CP_TEST_EN_POS  (1U)
+#define SEC_ENG_SE_TRNG_CP_TEST_EN_LEN  (1U)
+#define SEC_ENG_SE_TRNG_CP_TEST_EN_MSK  (((1U << SEC_ENG_SE_TRNG_CP_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_CP_TEST_EN_POS)
+#define SEC_ENG_SE_TRNG_CP_TEST_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_CP_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_CP_TEST_EN_POS))
+#define SEC_ENG_SE_TRNG_CP_BYPASS       SEC_ENG_SE_TRNG_CP_BYPASS
+#define SEC_ENG_SE_TRNG_CP_BYPASS_POS   (2U)
+#define SEC_ENG_SE_TRNG_CP_BYPASS_LEN   (1U)
+#define SEC_ENG_SE_TRNG_CP_BYPASS_MSK   (((1U << SEC_ENG_SE_TRNG_CP_BYPASS_LEN) - 1) << SEC_ENG_SE_TRNG_CP_BYPASS_POS)
+#define SEC_ENG_SE_TRNG_CP_BYPASS_UMSK  (~(((1U << SEC_ENG_SE_TRNG_CP_BYPASS_LEN) - 1) << SEC_ENG_SE_TRNG_CP_BYPASS_POS))
+#define SEC_ENG_SE_TRNG_HT_DIS          SEC_ENG_SE_TRNG_HT_DIS
+#define SEC_ENG_SE_TRNG_HT_DIS_POS      (3U)
+#define SEC_ENG_SE_TRNG_HT_DIS_LEN      (1U)
+#define SEC_ENG_SE_TRNG_HT_DIS_MSK      (((1U << SEC_ENG_SE_TRNG_HT_DIS_LEN) - 1) << SEC_ENG_SE_TRNG_HT_DIS_POS)
+#define SEC_ENG_SE_TRNG_HT_DIS_UMSK     (~(((1U << SEC_ENG_SE_TRNG_HT_DIS_LEN) - 1) << SEC_ENG_SE_TRNG_HT_DIS_POS))
+#define SEC_ENG_SE_TRNG_HT_ALARM_N      SEC_ENG_SE_TRNG_HT_ALARM_N
+#define SEC_ENG_SE_TRNG_HT_ALARM_N_POS  (4U)
+#define SEC_ENG_SE_TRNG_HT_ALARM_N_LEN  (8U)
+#define SEC_ENG_SE_TRNG_HT_ALARM_N_MSK  (((1U << SEC_ENG_SE_TRNG_HT_ALARM_N_LEN) - 1) << SEC_ENG_SE_TRNG_HT_ALARM_N_POS)
+#define SEC_ENG_SE_TRNG_HT_ALARM_N_UMSK (~(((1U << SEC_ENG_SE_TRNG_HT_ALARM_N_LEN) - 1) << SEC_ENG_SE_TRNG_HT_ALARM_N_POS))
+
+/* 0x2c : se_trng_ctrl_1 */
+#define SEC_ENG_SE_TRNG_CTRL_1_OFFSET     (0x2c)
+#define SEC_ENG_SE_TRNG_RESEED_N_LSB      SEC_ENG_SE_TRNG_RESEED_N_LSB
+#define SEC_ENG_SE_TRNG_RESEED_N_LSB_POS  (0U)
+#define SEC_ENG_SE_TRNG_RESEED_N_LSB_LEN  (32U)
+#define SEC_ENG_SE_TRNG_RESEED_N_LSB_MSK  (((1U << SEC_ENG_SE_TRNG_RESEED_N_LSB_LEN) - 1) << SEC_ENG_SE_TRNG_RESEED_N_LSB_POS)
+#define SEC_ENG_SE_TRNG_RESEED_N_LSB_UMSK (~(((1U << SEC_ENG_SE_TRNG_RESEED_N_LSB_LEN) - 1) << SEC_ENG_SE_TRNG_RESEED_N_LSB_POS))
+
+/* 0x30 : se_trng_ctrl_2 */
+#define SEC_ENG_SE_TRNG_CTRL_2_OFFSET     (0x30)
+#define SEC_ENG_SE_TRNG_RESEED_N_MSB      SEC_ENG_SE_TRNG_RESEED_N_MSB
+#define SEC_ENG_SE_TRNG_RESEED_N_MSB_POS  (0U)
+#define SEC_ENG_SE_TRNG_RESEED_N_MSB_LEN  (16U)
+#define SEC_ENG_SE_TRNG_RESEED_N_MSB_MSK  (((1U << SEC_ENG_SE_TRNG_RESEED_N_MSB_LEN) - 1) << SEC_ENG_SE_TRNG_RESEED_N_MSB_POS)
+#define SEC_ENG_SE_TRNG_RESEED_N_MSB_UMSK (~(((1U << SEC_ENG_SE_TRNG_RESEED_N_MSB_LEN) - 1) << SEC_ENG_SE_TRNG_RESEED_N_MSB_POS))
+
+/* 0x34 : se_trng_ctrl_3 */
+#define SEC_ENG_SE_TRNG_CTRL_3_OFFSET (0x34)
+#define SEC_ENG_SE_TRNG_CP_RATIO      SEC_ENG_SE_TRNG_CP_RATIO
+#define SEC_ENG_SE_TRNG_CP_RATIO_POS  (0U)
+#define SEC_ENG_SE_TRNG_CP_RATIO_LEN  (8U)
+#define SEC_ENG_SE_TRNG_CP_RATIO_MSK  (((1U << SEC_ENG_SE_TRNG_CP_RATIO_LEN) - 1) << SEC_ENG_SE_TRNG_CP_RATIO_POS)
+#define SEC_ENG_SE_TRNG_CP_RATIO_UMSK (~(((1U << SEC_ENG_SE_TRNG_CP_RATIO_LEN) - 1) << SEC_ENG_SE_TRNG_CP_RATIO_POS))
+#define SEC_ENG_SE_TRNG_HT_RCT_C      SEC_ENG_SE_TRNG_HT_RCT_C
+#define SEC_ENG_SE_TRNG_HT_RCT_C_POS  (8U)
+#define SEC_ENG_SE_TRNG_HT_RCT_C_LEN  (8U)
+#define SEC_ENG_SE_TRNG_HT_RCT_C_MSK  (((1U << SEC_ENG_SE_TRNG_HT_RCT_C_LEN) - 1) << SEC_ENG_SE_TRNG_HT_RCT_C_POS)
+#define SEC_ENG_SE_TRNG_HT_RCT_C_UMSK (~(((1U << SEC_ENG_SE_TRNG_HT_RCT_C_LEN) - 1) << SEC_ENG_SE_TRNG_HT_RCT_C_POS))
+#define SEC_ENG_SE_TRNG_HT_APT_C      SEC_ENG_SE_TRNG_HT_APT_C
+#define SEC_ENG_SE_TRNG_HT_APT_C_POS  (16U)
+#define SEC_ENG_SE_TRNG_HT_APT_C_LEN  (10U)
+#define SEC_ENG_SE_TRNG_HT_APT_C_MSK  (((1U << SEC_ENG_SE_TRNG_HT_APT_C_LEN) - 1) << SEC_ENG_SE_TRNG_HT_APT_C_POS)
+#define SEC_ENG_SE_TRNG_HT_APT_C_UMSK (~(((1U << SEC_ENG_SE_TRNG_HT_APT_C_LEN) - 1) << SEC_ENG_SE_TRNG_HT_APT_C_POS))
+#define SEC_ENG_SE_TRNG_HT_OD_EN      SEC_ENG_SE_TRNG_HT_OD_EN
+#define SEC_ENG_SE_TRNG_HT_OD_EN_POS  (26U)
+#define SEC_ENG_SE_TRNG_HT_OD_EN_LEN  (1U)
+#define SEC_ENG_SE_TRNG_HT_OD_EN_MSK  (((1U << SEC_ENG_SE_TRNG_HT_OD_EN_LEN) - 1) << SEC_ENG_SE_TRNG_HT_OD_EN_POS)
+#define SEC_ENG_SE_TRNG_HT_OD_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_HT_OD_EN_LEN) - 1) << SEC_ENG_SE_TRNG_HT_OD_EN_POS))
+#define SEC_ENG_SE_TRNG_ROSC_EN       SEC_ENG_SE_TRNG_ROSC_EN
+#define SEC_ENG_SE_TRNG_ROSC_EN_POS   (31U)
+#define SEC_ENG_SE_TRNG_ROSC_EN_LEN   (1U)
+#define SEC_ENG_SE_TRNG_ROSC_EN_MSK   (((1U << SEC_ENG_SE_TRNG_ROSC_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ROSC_EN_POS)
+#define SEC_ENG_SE_TRNG_ROSC_EN_UMSK  (~(((1U << SEC_ENG_SE_TRNG_ROSC_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ROSC_EN_POS))
+
+/* 0x40 : se_trng_test_out_0 */
+#define SEC_ENG_SE_TRNG_TEST_OUT_0_OFFSET (0x40)
+#define SEC_ENG_SE_TRNG_TEST_OUT_0        SEC_ENG_SE_TRNG_TEST_OUT_0
+#define SEC_ENG_SE_TRNG_TEST_OUT_0_POS    (0U)
+#define SEC_ENG_SE_TRNG_TEST_OUT_0_LEN    (32U)
+#define SEC_ENG_SE_TRNG_TEST_OUT_0_MSK    (((1U << SEC_ENG_SE_TRNG_TEST_OUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_0_POS)
+#define SEC_ENG_SE_TRNG_TEST_OUT_0_UMSK   (~(((1U << SEC_ENG_SE_TRNG_TEST_OUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_0_POS))
+
+/* 0x44 : se_trng_test_out_1 */
+#define SEC_ENG_SE_TRNG_TEST_OUT_1_OFFSET (0x44)
+#define SEC_ENG_SE_TRNG_TEST_OUT_1        SEC_ENG_SE_TRNG_TEST_OUT_1
+#define SEC_ENG_SE_TRNG_TEST_OUT_1_POS    (0U)
+#define SEC_ENG_SE_TRNG_TEST_OUT_1_LEN    (32U)
+#define SEC_ENG_SE_TRNG_TEST_OUT_1_MSK    (((1U << SEC_ENG_SE_TRNG_TEST_OUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_1_POS)
+#define SEC_ENG_SE_TRNG_TEST_OUT_1_UMSK   (~(((1U << SEC_ENG_SE_TRNG_TEST_OUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_1_POS))
+
+/* 0x48 : se_trng_test_out_2 */
+#define SEC_ENG_SE_TRNG_TEST_OUT_2_OFFSET (0x48)
+#define SEC_ENG_SE_TRNG_TEST_OUT_2        SEC_ENG_SE_TRNG_TEST_OUT_2
+#define SEC_ENG_SE_TRNG_TEST_OUT_2_POS    (0U)
+#define SEC_ENG_SE_TRNG_TEST_OUT_2_LEN    (32U)
+#define SEC_ENG_SE_TRNG_TEST_OUT_2_MSK    (((1U << SEC_ENG_SE_TRNG_TEST_OUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_2_POS)
+#define SEC_ENG_SE_TRNG_TEST_OUT_2_UMSK   (~(((1U << SEC_ENG_SE_TRNG_TEST_OUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_2_POS))
+
+/* 0x4c : se_trng_test_out_3 */
+#define SEC_ENG_SE_TRNG_TEST_OUT_3_OFFSET (0x4c)
+#define SEC_ENG_SE_TRNG_TEST_OUT_3        SEC_ENG_SE_TRNG_TEST_OUT_3
+#define SEC_ENG_SE_TRNG_TEST_OUT_3_POS    (0U)
+#define SEC_ENG_SE_TRNG_TEST_OUT_3_LEN    (32U)
+#define SEC_ENG_SE_TRNG_TEST_OUT_3_MSK    (((1U << SEC_ENG_SE_TRNG_TEST_OUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_3_POS)
+#define SEC_ENG_SE_TRNG_TEST_OUT_3_UMSK   (~(((1U << SEC_ENG_SE_TRNG_TEST_OUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_3_POS))
+
+/* 0xfc : se_trng_ctrl_prot */
+#define SEC_ENG_SE_TRNG_CTRL_PROT_OFFSET (0xfc)
+#define SEC_ENG_SE_TRNG_PROT_EN          SEC_ENG_SE_TRNG_PROT_EN
+#define SEC_ENG_SE_TRNG_PROT_EN_POS      (0U)
+#define SEC_ENG_SE_TRNG_PROT_EN_LEN      (1U)
+#define SEC_ENG_SE_TRNG_PROT_EN_MSK      (((1U << SEC_ENG_SE_TRNG_PROT_EN_LEN) - 1) << SEC_ENG_SE_TRNG_PROT_EN_POS)
+#define SEC_ENG_SE_TRNG_PROT_EN_UMSK     (~(((1U << SEC_ENG_SE_TRNG_PROT_EN_LEN) - 1) << SEC_ENG_SE_TRNG_PROT_EN_POS))
+#define SEC_ENG_SE_TRNG_ID0_EN           SEC_ENG_SE_TRNG_ID0_EN
+#define SEC_ENG_SE_TRNG_ID0_EN_POS       (1U)
+#define SEC_ENG_SE_TRNG_ID0_EN_LEN       (1U)
+#define SEC_ENG_SE_TRNG_ID0_EN_MSK       (((1U << SEC_ENG_SE_TRNG_ID0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_POS)
+#define SEC_ENG_SE_TRNG_ID0_EN_UMSK      (~(((1U << SEC_ENG_SE_TRNG_ID0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_POS))
+#define SEC_ENG_SE_TRNG_ID1_EN           SEC_ENG_SE_TRNG_ID1_EN
+#define SEC_ENG_SE_TRNG_ID1_EN_POS       (2U)
+#define SEC_ENG_SE_TRNG_ID1_EN_LEN       (1U)
+#define SEC_ENG_SE_TRNG_ID1_EN_MSK       (((1U << SEC_ENG_SE_TRNG_ID1_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_POS)
+#define SEC_ENG_SE_TRNG_ID1_EN_UMSK      (~(((1U << SEC_ENG_SE_TRNG_ID1_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_POS))
+
+struct sec_eng_trng_reg {
+    /* 0x0 : se_trng_ctrl_0 */
+    union {
+        struct
+        {
+            uint32_t se_trng_busy           : 1;  /* [    0],          r,        0x0 */
+            uint32_t se_trng_trig_1t        : 1;  /* [    1],        w1p,        0x0 */
+            uint32_t se_trng_en             : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t se_trng_dout_clr_1t    : 1;  /* [    3],        w1p,        0x0 */
+            uint32_t se_trng_ht_error       : 1;  /* [    4],          r,        0x0 */
+            uint32_t reserved_5_7           : 3;  /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t se_trng_int            : 1;  /* [    8],          r,        0x0 */
+            uint32_t se_trng_int_clr_1t     : 1;  /* [    9],        w1p,        0x0 */
+            uint32_t se_trng_int_set_1t     : 1;  /* [   10],        w1p,        0x0 */
+            uint32_t se_trng_int_mask       : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t reserved_12            : 1;  /* [   12],       rsvd,        0x0 */
+            uint32_t se_trng_manual_fun_sel : 1;  /* [   13],        r/w,        0x0 */
+            uint32_t se_trng_manual_reseed  : 1;  /* [   14],        r/w,        0x0 */
+            uint32_t se_trng_manual_en      : 1;  /* [   15],        r/w,        0x0 */
+            uint32_t reserved_16_31         : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_ctrl_0;
+
+    /* 0x4 : se_trng_status */
+    union {
+        struct
+        {
+            uint32_t se_trng_status : 32; /* [31: 0],          r,   0x100020 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_status;
+
+    /* 0x8 : se_trng_dout_0 */
+    union {
+        struct
+        {
+            uint32_t se_trng_dout_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_dout_0;
+
+    /* 0xc : se_trng_dout_1 */
+    union {
+        struct
+        {
+            uint32_t se_trng_dout_1 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_dout_1;
+
+    /* 0x10 : se_trng_dout_2 */
+    union {
+        struct
+        {
+            uint32_t se_trng_dout_2 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_dout_2;
+
+    /* 0x14 : se_trng_dout_3 */
+    union {
+        struct
+        {
+            uint32_t se_trng_dout_3 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_dout_3;
+
+    /* 0x18 : se_trng_dout_4 */
+    union {
+        struct
+        {
+            uint32_t se_trng_dout_4 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_dout_4;
+
+    /* 0x1c : se_trng_dout_5 */
+    union {
+        struct
+        {
+            uint32_t se_trng_dout_5 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_dout_5;
+
+    /* 0x20 : se_trng_dout_6 */
+    union {
+        struct
+        {
+            uint32_t se_trng_dout_6 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_dout_6;
+
+    /* 0x24 : se_trng_dout_7 */
+    union {
+        struct
+        {
+            uint32_t se_trng_dout_7 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_dout_7;
+
+    /* 0x28 : se_trng_test */
+    union {
+        struct
+        {
+            uint32_t se_trng_test_en    : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t se_trng_cp_test_en : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t se_trng_cp_bypass  : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t se_trng_ht_dis     : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t se_trng_ht_alarm_n : 8;  /* [11: 4],        r/w,        0x0 */
+            uint32_t reserved_12_31     : 20; /* [31:12],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_test;
+
+    /* 0x2c : se_trng_ctrl_1 */
+    union {
+        struct
+        {
+            uint32_t se_trng_reseed_n_lsb : 32; /* [31: 0],        r/w,     0xffff */
+        } BF;
+        uint32_t WORD;
+    } se_trng_ctrl_1;
+
+    /* 0x30 : se_trng_ctrl_2 */
+    union {
+        struct
+        {
+            uint32_t se_trng_reseed_n_msb : 16; /* [15: 0],        r/w,       0xff */
+            uint32_t reserved_16_31       : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_ctrl_2;
+
+    /* 0x34 : se_trng_ctrl_3 */
+    union {
+        struct
+        {
+            uint32_t se_trng_cp_ratio : 8;  /* [ 7: 0],        r/w,        0x3 */
+            uint32_t se_trng_ht_rct_c : 8;  /* [15: 8],        r/w,       0x42 */
+            uint32_t se_trng_ht_apt_c : 10; /* [25:16],        r/w,      0x37a */
+            uint32_t se_trng_ht_od_en : 1;  /* [   26],        r/w,        0x0 */
+            uint32_t reserved_27_30   : 4;  /* [30:27],       rsvd,        0x0 */
+            uint32_t se_trng_rosc_en  : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_ctrl_3;
+
+    /* 0x38  reserved */
+    uint8_t RESERVED0x38[8];
+
+    /* 0x40 : se_trng_test_out_0 */
+    union {
+        struct
+        {
+            uint32_t se_trng_test_out_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_test_out_0;
+
+    /* 0x44 : se_trng_test_out_1 */
+    union {
+        struct
+        {
+            uint32_t se_trng_test_out_1 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_test_out_1;
+
+    /* 0x48 : se_trng_test_out_2 */
+    union {
+        struct
+        {
+            uint32_t se_trng_test_out_2 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_test_out_2;
+
+    /* 0x4c : se_trng_test_out_3 */
+    union {
+        struct
+        {
+            uint32_t se_trng_test_out_3 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_test_out_3;
+
+    /* 0x50  reserved */
+    uint8_t RESERVED0x50[172];
+
+    /* 0xfc : se_trng_ctrl_prot */
+    union {
+        struct
+        {
+            uint32_t se_trng_prot_en : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t se_trng_id0_en  : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t se_trng_id1_en  : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t reserved_3_31   : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } se_trng_ctrl_prot;
+};
+
+typedef volatile struct sec_eng_trng_reg sec_eng_trng_reg_t;
+
+#define SEC_ENG_TRNG_OFFSET 0x200
+
+#endif /* __SEC_ENG_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/sf_ctrl_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/sf_ctrl_reg.h
new file mode 100644
index 00000000..45eda741
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/sf_ctrl_reg.h
@@ -0,0 +1,2735 @@
+/**
+  ******************************************************************************
+  * @file    sf_ctrl_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __SF_CTRL_REG_H__
+#define __SF_CTRL_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : sf_ctrl_0 */
+#define SF_CTRL_0_OFFSET                  (0x0)
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL      SF_CTRL_SF_CLK_SF_RX_INV_SEL
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS  (2U)
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN  (1U)
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_MSK  (((1U << SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS)
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS))
+#define SF_CTRL_SF_CLK_OUT_GATE_EN        SF_CTRL_SF_CLK_OUT_GATE_EN
+#define SF_CTRL_SF_CLK_OUT_GATE_EN_POS    (3U)
+#define SF_CTRL_SF_CLK_OUT_GATE_EN_LEN    (1U)
+#define SF_CTRL_SF_CLK_OUT_GATE_EN_MSK    (((1U << SF_CTRL_SF_CLK_OUT_GATE_EN_LEN) - 1) << SF_CTRL_SF_CLK_OUT_GATE_EN_POS)
+#define SF_CTRL_SF_CLK_OUT_GATE_EN_UMSK   (~(((1U << SF_CTRL_SF_CLK_OUT_GATE_EN_LEN) - 1) << SF_CTRL_SF_CLK_OUT_GATE_EN_POS))
+#define SF_CTRL_SF_CLK_OUT_INV_SEL        SF_CTRL_SF_CLK_OUT_INV_SEL
+#define SF_CTRL_SF_CLK_OUT_INV_SEL_POS    (4U)
+#define SF_CTRL_SF_CLK_OUT_INV_SEL_LEN    (1U)
+#define SF_CTRL_SF_CLK_OUT_INV_SEL_MSK    (((1U << SF_CTRL_SF_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_INV_SEL_POS)
+#define SF_CTRL_SF_CLK_OUT_INV_SEL_UMSK   (~(((1U << SF_CTRL_SF_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_INV_SEL_POS))
+#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL      SF_CTRL_SF_CLK_SAHB_SRAM_SEL
+#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_POS  (5U)
+#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_LEN  (1U)
+#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_MSK  (((1U << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_POS)
+#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_POS))
+#define SF_CTRL_SF_IF_READ_DLY_N          SF_CTRL_SF_IF_READ_DLY_N
+#define SF_CTRL_SF_IF_READ_DLY_N_POS      (8U)
+#define SF_CTRL_SF_IF_READ_DLY_N_LEN      (3U)
+#define SF_CTRL_SF_IF_READ_DLY_N_MSK      (((1U << SF_CTRL_SF_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_N_POS)
+#define SF_CTRL_SF_IF_READ_DLY_N_UMSK     (~(((1U << SF_CTRL_SF_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_N_POS))
+#define SF_CTRL_SF_IF_READ_DLY_EN         SF_CTRL_SF_IF_READ_DLY_EN
+#define SF_CTRL_SF_IF_READ_DLY_EN_POS     (11U)
+#define SF_CTRL_SF_IF_READ_DLY_EN_LEN     (1U)
+#define SF_CTRL_SF_IF_READ_DLY_EN_MSK     (((1U << SF_CTRL_SF_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_EN_POS)
+#define SF_CTRL_SF_IF_READ_DLY_EN_UMSK    (~(((1U << SF_CTRL_SF_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_EN_POS))
+#define SF_CTRL_SF_IF_INT                 SF_CTRL_SF_IF_INT
+#define SF_CTRL_SF_IF_INT_POS             (16U)
+#define SF_CTRL_SF_IF_INT_LEN             (1U)
+#define SF_CTRL_SF_IF_INT_MSK             (((1U << SF_CTRL_SF_IF_INT_LEN) - 1) << SF_CTRL_SF_IF_INT_POS)
+#define SF_CTRL_SF_IF_INT_UMSK            (~(((1U << SF_CTRL_SF_IF_INT_LEN) - 1) << SF_CTRL_SF_IF_INT_POS))
+#define SF_CTRL_SF_IF_INT_CLR             SF_CTRL_SF_IF_INT_CLR
+#define SF_CTRL_SF_IF_INT_CLR_POS         (17U)
+#define SF_CTRL_SF_IF_INT_CLR_LEN         (1U)
+#define SF_CTRL_SF_IF_INT_CLR_MSK         (((1U << SF_CTRL_SF_IF_INT_CLR_LEN) - 1) << SF_CTRL_SF_IF_INT_CLR_POS)
+#define SF_CTRL_SF_IF_INT_CLR_UMSK        (~(((1U << SF_CTRL_SF_IF_INT_CLR_LEN) - 1) << SF_CTRL_SF_IF_INT_CLR_POS))
+#define SF_CTRL_SF_IF_INT_SET             SF_CTRL_SF_IF_INT_SET
+#define SF_CTRL_SF_IF_INT_SET_POS         (18U)
+#define SF_CTRL_SF_IF_INT_SET_LEN         (1U)
+#define SF_CTRL_SF_IF_INT_SET_MSK         (((1U << SF_CTRL_SF_IF_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_INT_SET_POS)
+#define SF_CTRL_SF_IF_INT_SET_UMSK        (~(((1U << SF_CTRL_SF_IF_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_INT_SET_POS))
+#define SF_CTRL_SF_AES_DLY_MODE           SF_CTRL_SF_AES_DLY_MODE
+#define SF_CTRL_SF_AES_DLY_MODE_POS       (19U)
+#define SF_CTRL_SF_AES_DLY_MODE_LEN       (1U)
+#define SF_CTRL_SF_AES_DLY_MODE_MSK       (((1U << SF_CTRL_SF_AES_DLY_MODE_LEN) - 1) << SF_CTRL_SF_AES_DLY_MODE_POS)
+#define SF_CTRL_SF_AES_DLY_MODE_UMSK      (~(((1U << SF_CTRL_SF_AES_DLY_MODE_LEN) - 1) << SF_CTRL_SF_AES_DLY_MODE_POS))
+#define SF_CTRL_SF_AES_DOUT_ENDIAN        SF_CTRL_SF_AES_DOUT_ENDIAN
+#define SF_CTRL_SF_AES_DOUT_ENDIAN_POS    (20U)
+#define SF_CTRL_SF_AES_DOUT_ENDIAN_LEN    (1U)
+#define SF_CTRL_SF_AES_DOUT_ENDIAN_MSK    (((1U << SF_CTRL_SF_AES_DOUT_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_DOUT_ENDIAN_POS)
+#define SF_CTRL_SF_AES_DOUT_ENDIAN_UMSK   (~(((1U << SF_CTRL_SF_AES_DOUT_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_DOUT_ENDIAN_POS))
+#define SF_CTRL_SF_AES_CTR_PLUS_EN        SF_CTRL_SF_AES_CTR_PLUS_EN
+#define SF_CTRL_SF_AES_CTR_PLUS_EN_POS    (21U)
+#define SF_CTRL_SF_AES_CTR_PLUS_EN_LEN    (1U)
+#define SF_CTRL_SF_AES_CTR_PLUS_EN_MSK    (((1U << SF_CTRL_SF_AES_CTR_PLUS_EN_LEN) - 1) << SF_CTRL_SF_AES_CTR_PLUS_EN_POS)
+#define SF_CTRL_SF_AES_CTR_PLUS_EN_UMSK   (~(((1U << SF_CTRL_SF_AES_CTR_PLUS_EN_LEN) - 1) << SF_CTRL_SF_AES_CTR_PLUS_EN_POS))
+#define SF_CTRL_SF_AES_KEY_ENDIAN         SF_CTRL_SF_AES_KEY_ENDIAN
+#define SF_CTRL_SF_AES_KEY_ENDIAN_POS     (22U)
+#define SF_CTRL_SF_AES_KEY_ENDIAN_LEN     (1U)
+#define SF_CTRL_SF_AES_KEY_ENDIAN_MSK     (((1U << SF_CTRL_SF_AES_KEY_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_KEY_ENDIAN_POS)
+#define SF_CTRL_SF_AES_KEY_ENDIAN_UMSK    (~(((1U << SF_CTRL_SF_AES_KEY_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_KEY_ENDIAN_POS))
+#define SF_CTRL_SF_AES_IV_ENDIAN          SF_CTRL_SF_AES_IV_ENDIAN
+#define SF_CTRL_SF_AES_IV_ENDIAN_POS      (23U)
+#define SF_CTRL_SF_AES_IV_ENDIAN_LEN      (1U)
+#define SF_CTRL_SF_AES_IV_ENDIAN_MSK      (((1U << SF_CTRL_SF_AES_IV_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_IV_ENDIAN_POS)
+#define SF_CTRL_SF_AES_IV_ENDIAN_UMSK     (~(((1U << SF_CTRL_SF_AES_IV_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_IV_ENDIAN_POS))
+#define SF_CTRL_SF_ID                     SF_CTRL_SF_ID
+#define SF_CTRL_SF_ID_POS                 (24U)
+#define SF_CTRL_SF_ID_LEN                 (8U)
+#define SF_CTRL_SF_ID_MSK                 (((1U << SF_CTRL_SF_ID_LEN) - 1) << SF_CTRL_SF_ID_POS)
+#define SF_CTRL_SF_ID_UMSK                (~(((1U << SF_CTRL_SF_ID_LEN) - 1) << SF_CTRL_SF_ID_POS))
+
+/* 0x4 : sf_ctrl_1 */
+#define SF_CTRL_1_OFFSET                (0x4)
+#define SF_CTRL_SF_IF_SR_PAT_MASK       SF_CTRL_SF_IF_SR_PAT_MASK
+#define SF_CTRL_SF_IF_SR_PAT_MASK_POS   (0U)
+#define SF_CTRL_SF_IF_SR_PAT_MASK_LEN   (8U)
+#define SF_CTRL_SF_IF_SR_PAT_MASK_MSK   (((1U << SF_CTRL_SF_IF_SR_PAT_MASK_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_MASK_POS)
+#define SF_CTRL_SF_IF_SR_PAT_MASK_UMSK  (~(((1U << SF_CTRL_SF_IF_SR_PAT_MASK_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_MASK_POS))
+#define SF_CTRL_SF_IF_SR_PAT            SF_CTRL_SF_IF_SR_PAT
+#define SF_CTRL_SF_IF_SR_PAT_POS        (8U)
+#define SF_CTRL_SF_IF_SR_PAT_LEN        (8U)
+#define SF_CTRL_SF_IF_SR_PAT_MSK        (((1U << SF_CTRL_SF_IF_SR_PAT_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_POS)
+#define SF_CTRL_SF_IF_SR_PAT_UMSK       (~(((1U << SF_CTRL_SF_IF_SR_PAT_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_POS))
+#define SF_CTRL_SF_IF_SR_INT            SF_CTRL_SF_IF_SR_INT
+#define SF_CTRL_SF_IF_SR_INT_POS        (16U)
+#define SF_CTRL_SF_IF_SR_INT_LEN        (1U)
+#define SF_CTRL_SF_IF_SR_INT_MSK        (((1U << SF_CTRL_SF_IF_SR_INT_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_POS)
+#define SF_CTRL_SF_IF_SR_INT_UMSK       (~(((1U << SF_CTRL_SF_IF_SR_INT_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_POS))
+#define SF_CTRL_SF_IF_SR_INT_EN         SF_CTRL_SF_IF_SR_INT_EN
+#define SF_CTRL_SF_IF_SR_INT_EN_POS     (17U)
+#define SF_CTRL_SF_IF_SR_INT_EN_LEN     (1U)
+#define SF_CTRL_SF_IF_SR_INT_EN_MSK     (((1U << SF_CTRL_SF_IF_SR_INT_EN_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_EN_POS)
+#define SF_CTRL_SF_IF_SR_INT_EN_UMSK    (~(((1U << SF_CTRL_SF_IF_SR_INT_EN_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_EN_POS))
+#define SF_CTRL_SF_IF_SR_INT_SET        SF_CTRL_SF_IF_SR_INT_SET
+#define SF_CTRL_SF_IF_SR_INT_SET_POS    (18U)
+#define SF_CTRL_SF_IF_SR_INT_SET_LEN    (1U)
+#define SF_CTRL_SF_IF_SR_INT_SET_MSK    (((1U << SF_CTRL_SF_IF_SR_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_SET_POS)
+#define SF_CTRL_SF_IF_SR_INT_SET_UMSK   (~(((1U << SF_CTRL_SF_IF_SR_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_SET_POS))
+#define SF_CTRL_SF_IF_0_ACK_LAT         SF_CTRL_SF_IF_0_ACK_LAT
+#define SF_CTRL_SF_IF_0_ACK_LAT_POS     (20U)
+#define SF_CTRL_SF_IF_0_ACK_LAT_LEN     (3U)
+#define SF_CTRL_SF_IF_0_ACK_LAT_MSK     (((1U << SF_CTRL_SF_IF_0_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_0_ACK_LAT_POS)
+#define SF_CTRL_SF_IF_0_ACK_LAT_UMSK    (~(((1U << SF_CTRL_SF_IF_0_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_0_ACK_LAT_POS))
+#define SF_CTRL_SF_IF_REG_HOLD          SF_CTRL_SF_IF_REG_HOLD
+#define SF_CTRL_SF_IF_REG_HOLD_POS      (24U)
+#define SF_CTRL_SF_IF_REG_HOLD_LEN      (1U)
+#define SF_CTRL_SF_IF_REG_HOLD_MSK      (((1U << SF_CTRL_SF_IF_REG_HOLD_LEN) - 1) << SF_CTRL_SF_IF_REG_HOLD_POS)
+#define SF_CTRL_SF_IF_REG_HOLD_UMSK     (~(((1U << SF_CTRL_SF_IF_REG_HOLD_LEN) - 1) << SF_CTRL_SF_IF_REG_HOLD_POS))
+#define SF_CTRL_SF_IF_REG_WP            SF_CTRL_SF_IF_REG_WP
+#define SF_CTRL_SF_IF_REG_WP_POS        (25U)
+#define SF_CTRL_SF_IF_REG_WP_LEN        (1U)
+#define SF_CTRL_SF_IF_REG_WP_MSK        (((1U << SF_CTRL_SF_IF_REG_WP_LEN) - 1) << SF_CTRL_SF_IF_REG_WP_POS)
+#define SF_CTRL_SF_IF_REG_WP_UMSK       (~(((1U << SF_CTRL_SF_IF_REG_WP_LEN) - 1) << SF_CTRL_SF_IF_REG_WP_POS))
+#define SF_CTRL_SF_AHB2SIF_STOPPED      SF_CTRL_SF_AHB2SIF_STOPPED
+#define SF_CTRL_SF_AHB2SIF_STOPPED_POS  (26U)
+#define SF_CTRL_SF_AHB2SIF_STOPPED_LEN  (1U)
+#define SF_CTRL_SF_AHB2SIF_STOPPED_MSK  (((1U << SF_CTRL_SF_AHB2SIF_STOPPED_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOPPED_POS)
+#define SF_CTRL_SF_AHB2SIF_STOPPED_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_STOPPED_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOPPED_POS))
+#define SF_CTRL_SF_AHB2SIF_STOP         SF_CTRL_SF_AHB2SIF_STOP
+#define SF_CTRL_SF_AHB2SIF_STOP_POS     (27U)
+#define SF_CTRL_SF_AHB2SIF_STOP_LEN     (1U)
+#define SF_CTRL_SF_AHB2SIF_STOP_MSK     (((1U << SF_CTRL_SF_AHB2SIF_STOP_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOP_POS)
+#define SF_CTRL_SF_AHB2SIF_STOP_UMSK    (~(((1U << SF_CTRL_SF_AHB2SIF_STOP_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOP_POS))
+#define SF_CTRL_SF_IF_FN_SEL            SF_CTRL_SF_IF_FN_SEL
+#define SF_CTRL_SF_IF_FN_SEL_POS        (28U)
+#define SF_CTRL_SF_IF_FN_SEL_LEN        (1U)
+#define SF_CTRL_SF_IF_FN_SEL_MSK        (((1U << SF_CTRL_SF_IF_FN_SEL_LEN) - 1) << SF_CTRL_SF_IF_FN_SEL_POS)
+#define SF_CTRL_SF_IF_FN_SEL_UMSK       (~(((1U << SF_CTRL_SF_IF_FN_SEL_LEN) - 1) << SF_CTRL_SF_IF_FN_SEL_POS))
+#define SF_CTRL_SF_IF_EN                SF_CTRL_SF_IF_EN
+#define SF_CTRL_SF_IF_EN_POS            (29U)
+#define SF_CTRL_SF_IF_EN_LEN            (1U)
+#define SF_CTRL_SF_IF_EN_MSK            (((1U << SF_CTRL_SF_IF_EN_LEN) - 1) << SF_CTRL_SF_IF_EN_POS)
+#define SF_CTRL_SF_IF_EN_UMSK           (~(((1U << SF_CTRL_SF_IF_EN_LEN) - 1) << SF_CTRL_SF_IF_EN_POS))
+#define SF_CTRL_SF_AHB2SIF_EN           SF_CTRL_SF_AHB2SIF_EN
+#define SF_CTRL_SF_AHB2SIF_EN_POS       (30U)
+#define SF_CTRL_SF_AHB2SIF_EN_LEN       (1U)
+#define SF_CTRL_SF_AHB2SIF_EN_MSK       (((1U << SF_CTRL_SF_AHB2SIF_EN_LEN) - 1) << SF_CTRL_SF_AHB2SIF_EN_POS)
+#define SF_CTRL_SF_AHB2SIF_EN_UMSK      (~(((1U << SF_CTRL_SF_AHB2SIF_EN_LEN) - 1) << SF_CTRL_SF_AHB2SIF_EN_POS))
+#define SF_CTRL_SF_AHB2SRAM_EN          SF_CTRL_SF_AHB2SRAM_EN
+#define SF_CTRL_SF_AHB2SRAM_EN_POS      (31U)
+#define SF_CTRL_SF_AHB2SRAM_EN_LEN      (1U)
+#define SF_CTRL_SF_AHB2SRAM_EN_MSK      (((1U << SF_CTRL_SF_AHB2SRAM_EN_LEN) - 1) << SF_CTRL_SF_AHB2SRAM_EN_POS)
+#define SF_CTRL_SF_AHB2SRAM_EN_UMSK     (~(((1U << SF_CTRL_SF_AHB2SRAM_EN_LEN) - 1) << SF_CTRL_SF_AHB2SRAM_EN_POS))
+
+/* 0x8 : sf_if_sahb_0 */
+#define SF_CTRL_SF_IF_SAHB_0_OFFSET      (0x8)
+#define SF_CTRL_SF_IF_BUSY               SF_CTRL_SF_IF_BUSY
+#define SF_CTRL_SF_IF_BUSY_POS           (0U)
+#define SF_CTRL_SF_IF_BUSY_LEN           (1U)
+#define SF_CTRL_SF_IF_BUSY_MSK           (((1U << SF_CTRL_SF_IF_BUSY_LEN) - 1) << SF_CTRL_SF_IF_BUSY_POS)
+#define SF_CTRL_SF_IF_BUSY_UMSK          (~(((1U << SF_CTRL_SF_IF_BUSY_LEN) - 1) << SF_CTRL_SF_IF_BUSY_POS))
+#define SF_CTRL_SF_IF_0_TRIG             SF_CTRL_SF_IF_0_TRIG
+#define SF_CTRL_SF_IF_0_TRIG_POS         (1U)
+#define SF_CTRL_SF_IF_0_TRIG_LEN         (1U)
+#define SF_CTRL_SF_IF_0_TRIG_MSK         (((1U << SF_CTRL_SF_IF_0_TRIG_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_POS)
+#define SF_CTRL_SF_IF_0_TRIG_UMSK        (~(((1U << SF_CTRL_SF_IF_0_TRIG_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_POS))
+#define SF_CTRL_SF_IF_0_DAT_BYTE         SF_CTRL_SF_IF_0_DAT_BYTE
+#define SF_CTRL_SF_IF_0_DAT_BYTE_POS     (2U)
+#define SF_CTRL_SF_IF_0_DAT_BYTE_LEN     (10U)
+#define SF_CTRL_SF_IF_0_DAT_BYTE_MSK     (((1U << SF_CTRL_SF_IF_0_DAT_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_BYTE_POS)
+#define SF_CTRL_SF_IF_0_DAT_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_0_DAT_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_BYTE_POS))
+#define SF_CTRL_SF_IF_0_DMY_BYTE         SF_CTRL_SF_IF_0_DMY_BYTE
+#define SF_CTRL_SF_IF_0_DMY_BYTE_POS     (12U)
+#define SF_CTRL_SF_IF_0_DMY_BYTE_LEN     (5U)
+#define SF_CTRL_SF_IF_0_DMY_BYTE_MSK     (((1U << SF_CTRL_SF_IF_0_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_BYTE_POS)
+#define SF_CTRL_SF_IF_0_DMY_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_0_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_BYTE_POS))
+#define SF_CTRL_SF_IF_0_ADR_BYTE         SF_CTRL_SF_IF_0_ADR_BYTE
+#define SF_CTRL_SF_IF_0_ADR_BYTE_POS     (17U)
+#define SF_CTRL_SF_IF_0_ADR_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_0_ADR_BYTE_MSK     (((1U << SF_CTRL_SF_IF_0_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_BYTE_POS)
+#define SF_CTRL_SF_IF_0_ADR_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_0_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_BYTE_POS))
+#define SF_CTRL_SF_IF_0_CMD_BYTE         SF_CTRL_SF_IF_0_CMD_BYTE
+#define SF_CTRL_SF_IF_0_CMD_BYTE_POS     (20U)
+#define SF_CTRL_SF_IF_0_CMD_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_0_CMD_BYTE_MSK     (((1U << SF_CTRL_SF_IF_0_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BYTE_POS)
+#define SF_CTRL_SF_IF_0_CMD_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_0_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BYTE_POS))
+#define SF_CTRL_SF_IF_0_DAT_RW           SF_CTRL_SF_IF_0_DAT_RW
+#define SF_CTRL_SF_IF_0_DAT_RW_POS       (23U)
+#define SF_CTRL_SF_IF_0_DAT_RW_LEN       (1U)
+#define SF_CTRL_SF_IF_0_DAT_RW_MSK       (((1U << SF_CTRL_SF_IF_0_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_RW_POS)
+#define SF_CTRL_SF_IF_0_DAT_RW_UMSK      (~(((1U << SF_CTRL_SF_IF_0_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_RW_POS))
+#define SF_CTRL_SF_IF_0_DAT_EN           SF_CTRL_SF_IF_0_DAT_EN
+#define SF_CTRL_SF_IF_0_DAT_EN_POS       (24U)
+#define SF_CTRL_SF_IF_0_DAT_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_0_DAT_EN_MSK       (((1U << SF_CTRL_SF_IF_0_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_EN_POS)
+#define SF_CTRL_SF_IF_0_DAT_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_0_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_EN_POS))
+#define SF_CTRL_SF_IF_0_DMY_EN           SF_CTRL_SF_IF_0_DMY_EN
+#define SF_CTRL_SF_IF_0_DMY_EN_POS       (25U)
+#define SF_CTRL_SF_IF_0_DMY_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_0_DMY_EN_MSK       (((1U << SF_CTRL_SF_IF_0_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_EN_POS)
+#define SF_CTRL_SF_IF_0_DMY_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_0_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_EN_POS))
+#define SF_CTRL_SF_IF_0_ADR_EN           SF_CTRL_SF_IF_0_ADR_EN
+#define SF_CTRL_SF_IF_0_ADR_EN_POS       (26U)
+#define SF_CTRL_SF_IF_0_ADR_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_0_ADR_EN_MSK       (((1U << SF_CTRL_SF_IF_0_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_EN_POS)
+#define SF_CTRL_SF_IF_0_ADR_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_0_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_EN_POS))
+#define SF_CTRL_SF_IF_0_CMD_EN           SF_CTRL_SF_IF_0_CMD_EN
+#define SF_CTRL_SF_IF_0_CMD_EN_POS       (27U)
+#define SF_CTRL_SF_IF_0_CMD_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_0_CMD_EN_MSK       (((1U << SF_CTRL_SF_IF_0_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_EN_POS)
+#define SF_CTRL_SF_IF_0_CMD_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_0_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_EN_POS))
+#define SF_CTRL_SF_IF_0_SPI_MODE         SF_CTRL_SF_IF_0_SPI_MODE
+#define SF_CTRL_SF_IF_0_SPI_MODE_POS     (28U)
+#define SF_CTRL_SF_IF_0_SPI_MODE_LEN     (3U)
+#define SF_CTRL_SF_IF_0_SPI_MODE_MSK     (((1U << SF_CTRL_SF_IF_0_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_0_SPI_MODE_POS)
+#define SF_CTRL_SF_IF_0_SPI_MODE_UMSK    (~(((1U << SF_CTRL_SF_IF_0_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_0_SPI_MODE_POS))
+#define SF_CTRL_SF_IF_0_QPI_MODE_EN      SF_CTRL_SF_IF_0_QPI_MODE_EN
+#define SF_CTRL_SF_IF_0_QPI_MODE_EN_POS  (31U)
+#define SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN  (1U)
+#define SF_CTRL_SF_IF_0_QPI_MODE_EN_MSK  (((1U << SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_0_QPI_MODE_EN_POS)
+#define SF_CTRL_SF_IF_0_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_0_QPI_MODE_EN_POS))
+
+/* 0xC : sf_if_sahb_1 */
+#define SF_CTRL_SF_IF_SAHB_1_OFFSET    (0xC)
+#define SF_CTRL_SF_IF_0_CMD_BUF_0      SF_CTRL_SF_IF_0_CMD_BUF_0
+#define SF_CTRL_SF_IF_0_CMD_BUF_0_POS  (0U)
+#define SF_CTRL_SF_IF_0_CMD_BUF_0_LEN  (32U)
+#define SF_CTRL_SF_IF_0_CMD_BUF_0_MSK  (((1U << SF_CTRL_SF_IF_0_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_0_POS)
+#define SF_CTRL_SF_IF_0_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_0_POS))
+
+/* 0x10 : sf_if_sahb_2 */
+#define SF_CTRL_SF_IF_SAHB_2_OFFSET    (0x10)
+#define SF_CTRL_SF_IF_0_CMD_BUF_1      SF_CTRL_SF_IF_0_CMD_BUF_1
+#define SF_CTRL_SF_IF_0_CMD_BUF_1_POS  (0U)
+#define SF_CTRL_SF_IF_0_CMD_BUF_1_LEN  (32U)
+#define SF_CTRL_SF_IF_0_CMD_BUF_1_MSK  (((1U << SF_CTRL_SF_IF_0_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_1_POS)
+#define SF_CTRL_SF_IF_0_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_1_POS))
+
+/* 0x14 : sf_if_iahb_0 */
+#define SF_CTRL_SF_IF_IAHB_0_OFFSET      (0x14)
+#define SF_CTRL_SF_IF_1_DMY_BYTE         SF_CTRL_SF_IF_1_DMY_BYTE
+#define SF_CTRL_SF_IF_1_DMY_BYTE_POS     (12U)
+#define SF_CTRL_SF_IF_1_DMY_BYTE_LEN     (5U)
+#define SF_CTRL_SF_IF_1_DMY_BYTE_MSK     (((1U << SF_CTRL_SF_IF_1_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_BYTE_POS)
+#define SF_CTRL_SF_IF_1_DMY_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_1_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_BYTE_POS))
+#define SF_CTRL_SF_IF_1_ADR_BYTE         SF_CTRL_SF_IF_1_ADR_BYTE
+#define SF_CTRL_SF_IF_1_ADR_BYTE_POS     (17U)
+#define SF_CTRL_SF_IF_1_ADR_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_1_ADR_BYTE_MSK     (((1U << SF_CTRL_SF_IF_1_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_BYTE_POS)
+#define SF_CTRL_SF_IF_1_ADR_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_1_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_BYTE_POS))
+#define SF_CTRL_SF_IF_1_CMD_BYTE         SF_CTRL_SF_IF_1_CMD_BYTE
+#define SF_CTRL_SF_IF_1_CMD_BYTE_POS     (20U)
+#define SF_CTRL_SF_IF_1_CMD_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_1_CMD_BYTE_MSK     (((1U << SF_CTRL_SF_IF_1_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BYTE_POS)
+#define SF_CTRL_SF_IF_1_CMD_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_1_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BYTE_POS))
+#define SF_CTRL_SF_IF_1_DAT_RW           SF_CTRL_SF_IF_1_DAT_RW
+#define SF_CTRL_SF_IF_1_DAT_RW_POS       (23U)
+#define SF_CTRL_SF_IF_1_DAT_RW_LEN       (1U)
+#define SF_CTRL_SF_IF_1_DAT_RW_MSK       (((1U << SF_CTRL_SF_IF_1_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_RW_POS)
+#define SF_CTRL_SF_IF_1_DAT_RW_UMSK      (~(((1U << SF_CTRL_SF_IF_1_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_RW_POS))
+#define SF_CTRL_SF_IF_1_DAT_EN           SF_CTRL_SF_IF_1_DAT_EN
+#define SF_CTRL_SF_IF_1_DAT_EN_POS       (24U)
+#define SF_CTRL_SF_IF_1_DAT_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_1_DAT_EN_MSK       (((1U << SF_CTRL_SF_IF_1_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_EN_POS)
+#define SF_CTRL_SF_IF_1_DAT_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_1_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_EN_POS))
+#define SF_CTRL_SF_IF_1_DMY_EN           SF_CTRL_SF_IF_1_DMY_EN
+#define SF_CTRL_SF_IF_1_DMY_EN_POS       (25U)
+#define SF_CTRL_SF_IF_1_DMY_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_1_DMY_EN_MSK       (((1U << SF_CTRL_SF_IF_1_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_EN_POS)
+#define SF_CTRL_SF_IF_1_DMY_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_1_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_EN_POS))
+#define SF_CTRL_SF_IF_1_ADR_EN           SF_CTRL_SF_IF_1_ADR_EN
+#define SF_CTRL_SF_IF_1_ADR_EN_POS       (26U)
+#define SF_CTRL_SF_IF_1_ADR_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_1_ADR_EN_MSK       (((1U << SF_CTRL_SF_IF_1_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_EN_POS)
+#define SF_CTRL_SF_IF_1_ADR_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_1_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_EN_POS))
+#define SF_CTRL_SF_IF_1_CMD_EN           SF_CTRL_SF_IF_1_CMD_EN
+#define SF_CTRL_SF_IF_1_CMD_EN_POS       (27U)
+#define SF_CTRL_SF_IF_1_CMD_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_1_CMD_EN_MSK       (((1U << SF_CTRL_SF_IF_1_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_EN_POS)
+#define SF_CTRL_SF_IF_1_CMD_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_1_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_EN_POS))
+#define SF_CTRL_SF_IF_1_SPI_MODE         SF_CTRL_SF_IF_1_SPI_MODE
+#define SF_CTRL_SF_IF_1_SPI_MODE_POS     (28U)
+#define SF_CTRL_SF_IF_1_SPI_MODE_LEN     (3U)
+#define SF_CTRL_SF_IF_1_SPI_MODE_MSK     (((1U << SF_CTRL_SF_IF_1_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_1_SPI_MODE_POS)
+#define SF_CTRL_SF_IF_1_SPI_MODE_UMSK    (~(((1U << SF_CTRL_SF_IF_1_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_1_SPI_MODE_POS))
+#define SF_CTRL_SF_IF_1_QPI_MODE_EN      SF_CTRL_SF_IF_1_QPI_MODE_EN
+#define SF_CTRL_SF_IF_1_QPI_MODE_EN_POS  (31U)
+#define SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN  (1U)
+#define SF_CTRL_SF_IF_1_QPI_MODE_EN_MSK  (((1U << SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_1_QPI_MODE_EN_POS)
+#define SF_CTRL_SF_IF_1_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_1_QPI_MODE_EN_POS))
+
+/* 0x18 : sf_if_iahb_1 */
+#define SF_CTRL_SF_IF_IAHB_1_OFFSET    (0x18)
+#define SF_CTRL_SF_IF_1_CMD_BUF_0      SF_CTRL_SF_IF_1_CMD_BUF_0
+#define SF_CTRL_SF_IF_1_CMD_BUF_0_POS  (0U)
+#define SF_CTRL_SF_IF_1_CMD_BUF_0_LEN  (32U)
+#define SF_CTRL_SF_IF_1_CMD_BUF_0_MSK  (((1U << SF_CTRL_SF_IF_1_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_0_POS)
+#define SF_CTRL_SF_IF_1_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_0_POS))
+
+/* 0x1C : sf_if_iahb_2 */
+#define SF_CTRL_SF_IF_IAHB_2_OFFSET    (0x1C)
+#define SF_CTRL_SF_IF_1_CMD_BUF_1      SF_CTRL_SF_IF_1_CMD_BUF_1
+#define SF_CTRL_SF_IF_1_CMD_BUF_1_POS  (0U)
+#define SF_CTRL_SF_IF_1_CMD_BUF_1_LEN  (32U)
+#define SF_CTRL_SF_IF_1_CMD_BUF_1_MSK  (((1U << SF_CTRL_SF_IF_1_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_1_POS)
+#define SF_CTRL_SF_IF_1_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_1_POS))
+
+/* 0x20 : sf_if_status_0 */
+#define SF_CTRL_SF_IF_STATUS_0_OFFSET (0x20)
+#define SF_CTRL_SF_IF_STATUS_0        SF_CTRL_SF_IF_STATUS_0
+#define SF_CTRL_SF_IF_STATUS_0_POS    (0U)
+#define SF_CTRL_SF_IF_STATUS_0_LEN    (32U)
+#define SF_CTRL_SF_IF_STATUS_0_MSK    (((1U << SF_CTRL_SF_IF_STATUS_0_LEN) - 1) << SF_CTRL_SF_IF_STATUS_0_POS)
+#define SF_CTRL_SF_IF_STATUS_0_UMSK   (~(((1U << SF_CTRL_SF_IF_STATUS_0_LEN) - 1) << SF_CTRL_SF_IF_STATUS_0_POS))
+
+/* 0x24 : sf_if_status_1 */
+#define SF_CTRL_SF_IF_STATUS_1_OFFSET (0x24)
+#define SF_CTRL_SF_IF_STATUS_1        SF_CTRL_SF_IF_STATUS_1
+#define SF_CTRL_SF_IF_STATUS_1_POS    (0U)
+#define SF_CTRL_SF_IF_STATUS_1_LEN    (32U)
+#define SF_CTRL_SF_IF_STATUS_1_MSK    (((1U << SF_CTRL_SF_IF_STATUS_1_LEN) - 1) << SF_CTRL_SF_IF_STATUS_1_POS)
+#define SF_CTRL_SF_IF_STATUS_1_UMSK   (~(((1U << SF_CTRL_SF_IF_STATUS_1_LEN) - 1) << SF_CTRL_SF_IF_STATUS_1_POS))
+
+/* 0x28 : sf_aes */
+#define SF_CTRL_SF_AES_OFFSET         (0x28)
+#define SF_CTRL_SF_AES_EN             SF_CTRL_SF_AES_EN
+#define SF_CTRL_SF_AES_EN_POS         (0U)
+#define SF_CTRL_SF_AES_EN_LEN         (1U)
+#define SF_CTRL_SF_AES_EN_MSK         (((1U << SF_CTRL_SF_AES_EN_LEN) - 1) << SF_CTRL_SF_AES_EN_POS)
+#define SF_CTRL_SF_AES_EN_UMSK        (~(((1U << SF_CTRL_SF_AES_EN_LEN) - 1) << SF_CTRL_SF_AES_EN_POS))
+#define SF_CTRL_SF_AES_MODE           SF_CTRL_SF_AES_MODE
+#define SF_CTRL_SF_AES_MODE_POS       (1U)
+#define SF_CTRL_SF_AES_MODE_LEN       (2U)
+#define SF_CTRL_SF_AES_MODE_MSK       (((1U << SF_CTRL_SF_AES_MODE_LEN) - 1) << SF_CTRL_SF_AES_MODE_POS)
+#define SF_CTRL_SF_AES_MODE_UMSK      (~(((1U << SF_CTRL_SF_AES_MODE_LEN) - 1) << SF_CTRL_SF_AES_MODE_POS))
+#define SF_CTRL_SF_AES_PREF_TRIG      SF_CTRL_SF_AES_PREF_TRIG
+#define SF_CTRL_SF_AES_PREF_TRIG_POS  (3U)
+#define SF_CTRL_SF_AES_PREF_TRIG_LEN  (1U)
+#define SF_CTRL_SF_AES_PREF_TRIG_MSK  (((1U << SF_CTRL_SF_AES_PREF_TRIG_LEN) - 1) << SF_CTRL_SF_AES_PREF_TRIG_POS)
+#define SF_CTRL_SF_AES_PREF_TRIG_UMSK (~(((1U << SF_CTRL_SF_AES_PREF_TRIG_LEN) - 1) << SF_CTRL_SF_AES_PREF_TRIG_POS))
+#define SF_CTRL_SF_AES_PREF_BUSY      SF_CTRL_SF_AES_PREF_BUSY
+#define SF_CTRL_SF_AES_PREF_BUSY_POS  (4U)
+#define SF_CTRL_SF_AES_PREF_BUSY_LEN  (1U)
+#define SF_CTRL_SF_AES_PREF_BUSY_MSK  (((1U << SF_CTRL_SF_AES_PREF_BUSY_LEN) - 1) << SF_CTRL_SF_AES_PREF_BUSY_POS)
+#define SF_CTRL_SF_AES_PREF_BUSY_UMSK (~(((1U << SF_CTRL_SF_AES_PREF_BUSY_LEN) - 1) << SF_CTRL_SF_AES_PREF_BUSY_POS))
+#define SF_CTRL_SF_AES_STATUS         SF_CTRL_SF_AES_STATUS
+#define SF_CTRL_SF_AES_STATUS_POS     (5U)
+#define SF_CTRL_SF_AES_STATUS_LEN     (27U)
+#define SF_CTRL_SF_AES_STATUS_MSK     (((1U << SF_CTRL_SF_AES_STATUS_LEN) - 1) << SF_CTRL_SF_AES_STATUS_POS)
+#define SF_CTRL_SF_AES_STATUS_UMSK    (~(((1U << SF_CTRL_SF_AES_STATUS_LEN) - 1) << SF_CTRL_SF_AES_STATUS_POS))
+
+/* 0x2C : sf_ahb2sif_status */
+#define SF_CTRL_SF_AHB2SIF_STATUS_OFFSET (0x2C)
+#define SF_CTRL_SF_AHB2SIF_STATUS        SF_CTRL_SF_AHB2SIF_STATUS
+#define SF_CTRL_SF_AHB2SIF_STATUS_POS    (0U)
+#define SF_CTRL_SF_AHB2SIF_STATUS_LEN    (32U)
+#define SF_CTRL_SF_AHB2SIF_STATUS_MSK    (((1U << SF_CTRL_SF_AHB2SIF_STATUS_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STATUS_POS)
+#define SF_CTRL_SF_AHB2SIF_STATUS_UMSK   (~(((1U << SF_CTRL_SF_AHB2SIF_STATUS_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STATUS_POS))
+
+/* 0x30 : sf_if_io_dly_0 */
+#define SF_CTRL_SF_IF_IO_DLY_0_OFFSET   (0x30)
+#define SF_CTRL_SF_CS_DLY_SEL           SF_CTRL_SF_CS_DLY_SEL
+#define SF_CTRL_SF_CS_DLY_SEL_POS       (0U)
+#define SF_CTRL_SF_CS_DLY_SEL_LEN       (2U)
+#define SF_CTRL_SF_CS_DLY_SEL_MSK       (((1U << SF_CTRL_SF_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS_DLY_SEL_POS)
+#define SF_CTRL_SF_CS_DLY_SEL_UMSK      (~(((1U << SF_CTRL_SF_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS_DLY_SEL_POS))
+#define SF_CTRL_SF_CS2_DLY_SEL          SF_CTRL_SF_CS2_DLY_SEL
+#define SF_CTRL_SF_CS2_DLY_SEL_POS      (2U)
+#define SF_CTRL_SF_CS2_DLY_SEL_LEN      (2U)
+#define SF_CTRL_SF_CS2_DLY_SEL_MSK      (((1U << SF_CTRL_SF_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS2_DLY_SEL_POS)
+#define SF_CTRL_SF_CS2_DLY_SEL_UMSK     (~(((1U << SF_CTRL_SF_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS2_DLY_SEL_POS))
+#define SF_CTRL_SF_CLK_OUT_DLY_SEL      SF_CTRL_SF_CLK_OUT_DLY_SEL
+#define SF_CTRL_SF_CLK_OUT_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_CLK_OUT_DLY_SEL_MSK  (((1U << SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_DLY_SEL_POS)
+#define SF_CTRL_SF_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_DLY_SEL_POS))
+#define SF_CTRL_SF_DQS_OE_DLY_SEL       SF_CTRL_SF_DQS_OE_DLY_SEL
+#define SF_CTRL_SF_DQS_OE_DLY_SEL_POS   (26U)
+#define SF_CTRL_SF_DQS_OE_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF_DQS_OE_DLY_SEL_MSK   (((1U << SF_CTRL_SF_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_OE_DLY_SEL_POS)
+#define SF_CTRL_SF_DQS_OE_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_OE_DLY_SEL_POS))
+#define SF_CTRL_SF_DQS_DI_DLY_SEL       SF_CTRL_SF_DQS_DI_DLY_SEL
+#define SF_CTRL_SF_DQS_DI_DLY_SEL_POS   (28U)
+#define SF_CTRL_SF_DQS_DI_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF_DQS_DI_DLY_SEL_MSK   (((1U << SF_CTRL_SF_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DI_DLY_SEL_POS)
+#define SF_CTRL_SF_DQS_DI_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DI_DLY_SEL_POS))
+#define SF_CTRL_SF_DQS_DO_DLY_SEL       SF_CTRL_SF_DQS_DO_DLY_SEL
+#define SF_CTRL_SF_DQS_DO_DLY_SEL_POS   (30U)
+#define SF_CTRL_SF_DQS_DO_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF_DQS_DO_DLY_SEL_MSK   (((1U << SF_CTRL_SF_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DO_DLY_SEL_POS)
+#define SF_CTRL_SF_DQS_DO_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DO_DLY_SEL_POS))
+
+/* 0x34 : sf_if_io_dly_1 */
+#define SF_CTRL_SF_IF_IO_DLY_1_OFFSET   (0x34)
+#define SF_CTRL_SF_IO_0_OE_DLY_SEL      SF_CTRL_SF_IO_0_OE_DLY_SEL
+#define SF_CTRL_SF_IO_0_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_0_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_OE_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_OE_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_0_DI_DLY_SEL      SF_CTRL_SF_IO_0_DI_DLY_SEL
+#define SF_CTRL_SF_IO_0_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_0_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DI_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DI_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_0_DO_DLY_SEL      SF_CTRL_SF_IO_0_DO_DLY_SEL
+#define SF_CTRL_SF_IO_0_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_0_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DO_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DO_DLY_SEL_POS))
+
+/* 0x38 : sf_if_io_dly_2 */
+#define SF_CTRL_SF_IF_IO_DLY_2_OFFSET   (0x38)
+#define SF_CTRL_SF_IO_1_OE_DLY_SEL      SF_CTRL_SF_IO_1_OE_DLY_SEL
+#define SF_CTRL_SF_IO_1_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_1_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_OE_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_OE_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_1_DI_DLY_SEL      SF_CTRL_SF_IO_1_DI_DLY_SEL
+#define SF_CTRL_SF_IO_1_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_1_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DI_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DI_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_1_DO_DLY_SEL      SF_CTRL_SF_IO_1_DO_DLY_SEL
+#define SF_CTRL_SF_IO_1_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_1_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DO_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DO_DLY_SEL_POS))
+
+/* 0x3C : sf_if_io_dly_3 */
+#define SF_CTRL_SF_IF_IO_DLY_3_OFFSET   (0x3C)
+#define SF_CTRL_SF_IO_2_OE_DLY_SEL      SF_CTRL_SF_IO_2_OE_DLY_SEL
+#define SF_CTRL_SF_IO_2_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_2_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_OE_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_OE_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_2_DI_DLY_SEL      SF_CTRL_SF_IO_2_DI_DLY_SEL
+#define SF_CTRL_SF_IO_2_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_2_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DI_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DI_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_2_DO_DLY_SEL      SF_CTRL_SF_IO_2_DO_DLY_SEL
+#define SF_CTRL_SF_IO_2_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_2_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DO_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DO_DLY_SEL_POS))
+
+/* 0x40 : sf_if_io_dly_4 */
+#define SF_CTRL_SF_IF_IO_DLY_4_OFFSET   (0x40)
+#define SF_CTRL_SF_IO_3_OE_DLY_SEL      SF_CTRL_SF_IO_3_OE_DLY_SEL
+#define SF_CTRL_SF_IO_3_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_3_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_OE_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_OE_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_3_DI_DLY_SEL      SF_CTRL_SF_IO_3_DI_DLY_SEL
+#define SF_CTRL_SF_IO_3_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_3_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DI_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DI_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_3_DO_DLY_SEL      SF_CTRL_SF_IO_3_DO_DLY_SEL
+#define SF_CTRL_SF_IO_3_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_3_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DO_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DO_DLY_SEL_POS))
+
+/* 0x44 : sf_reserved */
+#define SF_CTRL_SF_RESERVED_OFFSET (0x44)
+#define SF_CTRL_SF_RESERVED        SF_CTRL_SF_RESERVED
+#define SF_CTRL_SF_RESERVED_POS    (0U)
+#define SF_CTRL_SF_RESERVED_LEN    (32U)
+#define SF_CTRL_SF_RESERVED_MSK    (((1U << SF_CTRL_SF_RESERVED_LEN) - 1) << SF_CTRL_SF_RESERVED_POS)
+#define SF_CTRL_SF_RESERVED_UMSK   (~(((1U << SF_CTRL_SF_RESERVED_LEN) - 1) << SF_CTRL_SF_RESERVED_POS))
+
+/* 0x48 : sf2_if_io_dly_0 */
+#define SF_CTRL_SF2_IF_IO_DLY_0_OFFSET   (0x48)
+#define SF_CTRL_SF2_CS_DLY_SEL           SF_CTRL_SF2_CS_DLY_SEL
+#define SF_CTRL_SF2_CS_DLY_SEL_POS       (0U)
+#define SF_CTRL_SF2_CS_DLY_SEL_LEN       (2U)
+#define SF_CTRL_SF2_CS_DLY_SEL_MSK       (((1U << SF_CTRL_SF2_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS_DLY_SEL_POS)
+#define SF_CTRL_SF2_CS_DLY_SEL_UMSK      (~(((1U << SF_CTRL_SF2_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS_DLY_SEL_POS))
+#define SF_CTRL_SF2_CS2_DLY_SEL          SF_CTRL_SF2_CS2_DLY_SEL
+#define SF_CTRL_SF2_CS2_DLY_SEL_POS      (2U)
+#define SF_CTRL_SF2_CS2_DLY_SEL_LEN      (2U)
+#define SF_CTRL_SF2_CS2_DLY_SEL_MSK      (((1U << SF_CTRL_SF2_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS2_DLY_SEL_POS)
+#define SF_CTRL_SF2_CS2_DLY_SEL_UMSK     (~(((1U << SF_CTRL_SF2_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS2_DLY_SEL_POS))
+#define SF_CTRL_SF2_CLK_OUT_DLY_SEL      SF_CTRL_SF2_CLK_OUT_DLY_SEL
+#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS)
+#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS))
+#define SF_CTRL_SF2_DQS_OE_DLY_SEL       SF_CTRL_SF2_DQS_OE_DLY_SEL
+#define SF_CTRL_SF2_DQS_OE_DLY_SEL_POS   (26U)
+#define SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF2_DQS_OE_DLY_SEL_MSK   (((1U << SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_OE_DLY_SEL_POS)
+#define SF_CTRL_SF2_DQS_OE_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_OE_DLY_SEL_POS))
+#define SF_CTRL_SF2_DQS_DI_DLY_SEL       SF_CTRL_SF2_DQS_DI_DLY_SEL
+#define SF_CTRL_SF2_DQS_DI_DLY_SEL_POS   (28U)
+#define SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF2_DQS_DI_DLY_SEL_MSK   (((1U << SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DI_DLY_SEL_POS)
+#define SF_CTRL_SF2_DQS_DI_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DI_DLY_SEL_POS))
+#define SF_CTRL_SF2_DQS_DO_DLY_SEL       SF_CTRL_SF2_DQS_DO_DLY_SEL
+#define SF_CTRL_SF2_DQS_DO_DLY_SEL_POS   (30U)
+#define SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF2_DQS_DO_DLY_SEL_MSK   (((1U << SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DO_DLY_SEL_POS)
+#define SF_CTRL_SF2_DQS_DO_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DO_DLY_SEL_POS))
+
+/* 0x4C : sf2_if_io_dly_1 */
+#define SF_CTRL_SF2_IF_IO_DLY_1_OFFSET   (0x4C)
+#define SF_CTRL_SF2_IO_0_OE_DLY_SEL      SF_CTRL_SF2_IO_0_OE_DLY_SEL
+#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_0_DI_DLY_SEL      SF_CTRL_SF2_IO_0_DI_DLY_SEL
+#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_0_DO_DLY_SEL      SF_CTRL_SF2_IO_0_DO_DLY_SEL
+#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS))
+
+/* 0x50 : sf2_if_io_dly_2 */
+#define SF_CTRL_SF2_IF_IO_DLY_2_OFFSET   (0x50)
+#define SF_CTRL_SF2_IO_1_OE_DLY_SEL      SF_CTRL_SF2_IO_1_OE_DLY_SEL
+#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_1_DI_DLY_SEL      SF_CTRL_SF2_IO_1_DI_DLY_SEL
+#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_1_DO_DLY_SEL      SF_CTRL_SF2_IO_1_DO_DLY_SEL
+#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS))
+
+/* 0x54 : sf2_if_io_dly_3 */
+#define SF_CTRL_SF2_IF_IO_DLY_3_OFFSET   (0x54)
+#define SF_CTRL_SF2_IO_2_OE_DLY_SEL      SF_CTRL_SF2_IO_2_OE_DLY_SEL
+#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_2_DI_DLY_SEL      SF_CTRL_SF2_IO_2_DI_DLY_SEL
+#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_2_DO_DLY_SEL      SF_CTRL_SF2_IO_2_DO_DLY_SEL
+#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS))
+
+/* 0x58 : sf2_if_io_dly_4 */
+#define SF_CTRL_SF2_IF_IO_DLY_4_OFFSET   (0x58)
+#define SF_CTRL_SF2_IO_3_OE_DLY_SEL      SF_CTRL_SF2_IO_3_OE_DLY_SEL
+#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_3_DI_DLY_SEL      SF_CTRL_SF2_IO_3_DI_DLY_SEL
+#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_3_DO_DLY_SEL      SF_CTRL_SF2_IO_3_DO_DLY_SEL
+#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS))
+
+/* 0x5C : sf3_if_io_dly_0 */
+#define SF_CTRL_SF3_IF_IO_DLY_0_OFFSET   (0x5C)
+#define SF_CTRL_SF3_CS_DLY_SEL           SF_CTRL_SF3_CS_DLY_SEL
+#define SF_CTRL_SF3_CS_DLY_SEL_POS       (0U)
+#define SF_CTRL_SF3_CS_DLY_SEL_LEN       (2U)
+#define SF_CTRL_SF3_CS_DLY_SEL_MSK       (((1U << SF_CTRL_SF3_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS_DLY_SEL_POS)
+#define SF_CTRL_SF3_CS_DLY_SEL_UMSK      (~(((1U << SF_CTRL_SF3_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS_DLY_SEL_POS))
+#define SF_CTRL_SF3_CS2_DLY_SEL          SF_CTRL_SF3_CS2_DLY_SEL
+#define SF_CTRL_SF3_CS2_DLY_SEL_POS      (2U)
+#define SF_CTRL_SF3_CS2_DLY_SEL_LEN      (2U)
+#define SF_CTRL_SF3_CS2_DLY_SEL_MSK      (((1U << SF_CTRL_SF3_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS2_DLY_SEL_POS)
+#define SF_CTRL_SF3_CS2_DLY_SEL_UMSK     (~(((1U << SF_CTRL_SF3_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS2_DLY_SEL_POS))
+#define SF_CTRL_SF3_CLK_OUT_DLY_SEL      SF_CTRL_SF3_CLK_OUT_DLY_SEL
+#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS)
+#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS))
+#define SF_CTRL_SF3_DQS_OE_DLY_SEL       SF_CTRL_SF3_DQS_OE_DLY_SEL
+#define SF_CTRL_SF3_DQS_OE_DLY_SEL_POS   (26U)
+#define SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF3_DQS_OE_DLY_SEL_MSK   (((1U << SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_OE_DLY_SEL_POS)
+#define SF_CTRL_SF3_DQS_OE_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_OE_DLY_SEL_POS))
+#define SF_CTRL_SF3_DQS_DI_DLY_SEL       SF_CTRL_SF3_DQS_DI_DLY_SEL
+#define SF_CTRL_SF3_DQS_DI_DLY_SEL_POS   (28U)
+#define SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF3_DQS_DI_DLY_SEL_MSK   (((1U << SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DI_DLY_SEL_POS)
+#define SF_CTRL_SF3_DQS_DI_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DI_DLY_SEL_POS))
+#define SF_CTRL_SF3_DQS_DO_DLY_SEL       SF_CTRL_SF3_DQS_DO_DLY_SEL
+#define SF_CTRL_SF3_DQS_DO_DLY_SEL_POS   (30U)
+#define SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF3_DQS_DO_DLY_SEL_MSK   (((1U << SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DO_DLY_SEL_POS)
+#define SF_CTRL_SF3_DQS_DO_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DO_DLY_SEL_POS))
+
+/* 0x60 : sf3_if_io_dly_1 */
+#define SF_CTRL_SF3_IF_IO_DLY_1_OFFSET   (0x60)
+#define SF_CTRL_SF3_IO_0_OE_DLY_SEL      SF_CTRL_SF3_IO_0_OE_DLY_SEL
+#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_0_DI_DLY_SEL      SF_CTRL_SF3_IO_0_DI_DLY_SEL
+#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_0_DO_DLY_SEL      SF_CTRL_SF3_IO_0_DO_DLY_SEL
+#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS))
+
+/* 0x64 : sf3_if_io_dly_2 */
+#define SF_CTRL_SF3_IF_IO_DLY_2_OFFSET   (0x64)
+#define SF_CTRL_SF3_IO_1_OE_DLY_SEL      SF_CTRL_SF3_IO_1_OE_DLY_SEL
+#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_1_DI_DLY_SEL      SF_CTRL_SF3_IO_1_DI_DLY_SEL
+#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_1_DO_DLY_SEL      SF_CTRL_SF3_IO_1_DO_DLY_SEL
+#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS))
+
+/* 0x68 : sf3_if_io_dly_3 */
+#define SF_CTRL_SF3_IF_IO_DLY_3_OFFSET   (0x68)
+#define SF_CTRL_SF3_IO_2_OE_DLY_SEL      SF_CTRL_SF3_IO_2_OE_DLY_SEL
+#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_2_DI_DLY_SEL      SF_CTRL_SF3_IO_2_DI_DLY_SEL
+#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_2_DO_DLY_SEL      SF_CTRL_SF3_IO_2_DO_DLY_SEL
+#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS))
+
+/* 0x6C : sf3_if_io_dly_4 */
+#define SF_CTRL_SF3_IF_IO_DLY_4_OFFSET   (0x6C)
+#define SF_CTRL_SF3_IO_3_OE_DLY_SEL      SF_CTRL_SF3_IO_3_OE_DLY_SEL
+#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_3_DI_DLY_SEL      SF_CTRL_SF3_IO_3_DI_DLY_SEL
+#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_3_DO_DLY_SEL      SF_CTRL_SF3_IO_3_DO_DLY_SEL
+#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS))
+
+/* 0x70 : sf_ctrl_2 */
+#define SF_CTRL_2_OFFSET                (0x70)
+#define SF_CTRL_SF_IF_PAD_SEL           SF_CTRL_SF_IF_PAD_SEL
+#define SF_CTRL_SF_IF_PAD_SEL_POS       (0U)
+#define SF_CTRL_SF_IF_PAD_SEL_LEN       (2U)
+#define SF_CTRL_SF_IF_PAD_SEL_MSK       (((1U << SF_CTRL_SF_IF_PAD_SEL_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_POS)
+#define SF_CTRL_SF_IF_PAD_SEL_UMSK      (~(((1U << SF_CTRL_SF_IF_PAD_SEL_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_POS))
+#define SF_CTRL_SF_IF_PAD_SEL_LOCK      SF_CTRL_SF_IF_PAD_SEL_LOCK
+#define SF_CTRL_SF_IF_PAD_SEL_LOCK_POS  (3U)
+#define SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN  (1U)
+#define SF_CTRL_SF_IF_PAD_SEL_LOCK_MSK  (((1U << SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_LOCK_POS)
+#define SF_CTRL_SF_IF_PAD_SEL_LOCK_UMSK (~(((1U << SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_LOCK_POS))
+#define SF_CTRL_SF_IF_DTR_EN            SF_CTRL_SF_IF_DTR_EN
+#define SF_CTRL_SF_IF_DTR_EN_POS        (4U)
+#define SF_CTRL_SF_IF_DTR_EN_LEN        (1U)
+#define SF_CTRL_SF_IF_DTR_EN_MSK        (((1U << SF_CTRL_SF_IF_DTR_EN_LEN) - 1) << SF_CTRL_SF_IF_DTR_EN_POS)
+#define SF_CTRL_SF_IF_DTR_EN_UMSK       (~(((1U << SF_CTRL_SF_IF_DTR_EN_LEN) - 1) << SF_CTRL_SF_IF_DTR_EN_POS))
+#define SF_CTRL_SF_IF_DQS_EN            SF_CTRL_SF_IF_DQS_EN
+#define SF_CTRL_SF_IF_DQS_EN_POS        (5U)
+#define SF_CTRL_SF_IF_DQS_EN_LEN        (1U)
+#define SF_CTRL_SF_IF_DQS_EN_MSK        (((1U << SF_CTRL_SF_IF_DQS_EN_LEN) - 1) << SF_CTRL_SF_IF_DQS_EN_POS)
+#define SF_CTRL_SF_IF_DQS_EN_UMSK       (~(((1U << SF_CTRL_SF_IF_DQS_EN_LEN) - 1) << SF_CTRL_SF_IF_DQS_EN_POS))
+#define SF_CTRL_SF_IF_BK_SWAP           SF_CTRL_SF_IF_BK_SWAP
+#define SF_CTRL_SF_IF_BK_SWAP_POS       (28U)
+#define SF_CTRL_SF_IF_BK_SWAP_LEN       (1U)
+#define SF_CTRL_SF_IF_BK_SWAP_MSK       (((1U << SF_CTRL_SF_IF_BK_SWAP_LEN) - 1) << SF_CTRL_SF_IF_BK_SWAP_POS)
+#define SF_CTRL_SF_IF_BK_SWAP_UMSK      (~(((1U << SF_CTRL_SF_IF_BK_SWAP_LEN) - 1) << SF_CTRL_SF_IF_BK_SWAP_POS))
+#define SF_CTRL_SF_IF_BK2_MODE          SF_CTRL_SF_IF_BK2_MODE
+#define SF_CTRL_SF_IF_BK2_MODE_POS      (29U)
+#define SF_CTRL_SF_IF_BK2_MODE_LEN      (1U)
+#define SF_CTRL_SF_IF_BK2_MODE_MSK      (((1U << SF_CTRL_SF_IF_BK2_MODE_LEN) - 1) << SF_CTRL_SF_IF_BK2_MODE_POS)
+#define SF_CTRL_SF_IF_BK2_MODE_UMSK     (~(((1U << SF_CTRL_SF_IF_BK2_MODE_LEN) - 1) << SF_CTRL_SF_IF_BK2_MODE_POS))
+#define SF_CTRL_SF_IF_BK2_EN            SF_CTRL_SF_IF_BK2_EN
+#define SF_CTRL_SF_IF_BK2_EN_POS        (30U)
+#define SF_CTRL_SF_IF_BK2_EN_LEN        (1U)
+#define SF_CTRL_SF_IF_BK2_EN_MSK        (((1U << SF_CTRL_SF_IF_BK2_EN_LEN) - 1) << SF_CTRL_SF_IF_BK2_EN_POS)
+#define SF_CTRL_SF_IF_BK2_EN_UMSK       (~(((1U << SF_CTRL_SF_IF_BK2_EN_LEN) - 1) << SF_CTRL_SF_IF_BK2_EN_POS))
+#define SF_CTRL_SF_IF_0_BK_SEL          SF_CTRL_SF_IF_0_BK_SEL
+#define SF_CTRL_SF_IF_0_BK_SEL_POS      (31U)
+#define SF_CTRL_SF_IF_0_BK_SEL_LEN      (1U)
+#define SF_CTRL_SF_IF_0_BK_SEL_MSK      (((1U << SF_CTRL_SF_IF_0_BK_SEL_LEN) - 1) << SF_CTRL_SF_IF_0_BK_SEL_POS)
+#define SF_CTRL_SF_IF_0_BK_SEL_UMSK     (~(((1U << SF_CTRL_SF_IF_0_BK_SEL_LEN) - 1) << SF_CTRL_SF_IF_0_BK_SEL_POS))
+
+/* 0x74 : sf_ctrl_3 */
+#define SF_CTRL_3_OFFSET                (0x74)
+#define SF_CTRL_SF_CMDS_WRAP_LEN        SF_CTRL_SF_CMDS_WRAP_LEN
+#define SF_CTRL_SF_CMDS_WRAP_LEN_POS    (0U)
+#define SF_CTRL_SF_CMDS_WRAP_LEN_LEN    (4U)
+#define SF_CTRL_SF_CMDS_WRAP_LEN_MSK    (((1U << SF_CTRL_SF_CMDS_WRAP_LEN_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_LEN_POS)
+#define SF_CTRL_SF_CMDS_WRAP_LEN_UMSK   (~(((1U << SF_CTRL_SF_CMDS_WRAP_LEN_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_LEN_POS))
+#define SF_CTRL_SF_CMDS_EN              SF_CTRL_SF_CMDS_EN
+#define SF_CTRL_SF_CMDS_EN_POS          (4U)
+#define SF_CTRL_SF_CMDS_EN_LEN          (1U)
+#define SF_CTRL_SF_CMDS_EN_MSK          (((1U << SF_CTRL_SF_CMDS_EN_LEN) - 1) << SF_CTRL_SF_CMDS_EN_POS)
+#define SF_CTRL_SF_CMDS_EN_UMSK         (~(((1U << SF_CTRL_SF_CMDS_EN_LEN) - 1) << SF_CTRL_SF_CMDS_EN_POS))
+#define SF_CTRL_SF_CMDS_BT_DLY          SF_CTRL_SF_CMDS_BT_DLY
+#define SF_CTRL_SF_CMDS_BT_DLY_POS      (5U)
+#define SF_CTRL_SF_CMDS_BT_DLY_LEN      (3U)
+#define SF_CTRL_SF_CMDS_BT_DLY_MSK      (((1U << SF_CTRL_SF_CMDS_BT_DLY_LEN) - 1) << SF_CTRL_SF_CMDS_BT_DLY_POS)
+#define SF_CTRL_SF_CMDS_BT_DLY_UMSK     (~(((1U << SF_CTRL_SF_CMDS_BT_DLY_LEN) - 1) << SF_CTRL_SF_CMDS_BT_DLY_POS))
+#define SF_CTRL_SF_CMDS_BT_EN           SF_CTRL_SF_CMDS_BT_EN
+#define SF_CTRL_SF_CMDS_BT_EN_POS       (8U)
+#define SF_CTRL_SF_CMDS_BT_EN_LEN       (1U)
+#define SF_CTRL_SF_CMDS_BT_EN_MSK       (((1U << SF_CTRL_SF_CMDS_BT_EN_LEN) - 1) << SF_CTRL_SF_CMDS_BT_EN_POS)
+#define SF_CTRL_SF_CMDS_BT_EN_UMSK      (~(((1U << SF_CTRL_SF_CMDS_BT_EN_LEN) - 1) << SF_CTRL_SF_CMDS_BT_EN_POS))
+#define SF_CTRL_SF_CMDS_WRAP_Q_INI      SF_CTRL_SF_CMDS_WRAP_Q_INI
+#define SF_CTRL_SF_CMDS_WRAP_Q_INI_POS  (9U)
+#define SF_CTRL_SF_CMDS_WRAP_Q_INI_LEN  (1U)
+#define SF_CTRL_SF_CMDS_WRAP_Q_INI_MSK  (((1U << SF_CTRL_SF_CMDS_WRAP_Q_INI_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_INI_POS)
+#define SF_CTRL_SF_CMDS_WRAP_Q_INI_UMSK (~(((1U << SF_CTRL_SF_CMDS_WRAP_Q_INI_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_INI_POS))
+#define SF_CTRL_SF_CMDS_WRAP_MODE       SF_CTRL_SF_CMDS_WRAP_MODE
+#define SF_CTRL_SF_CMDS_WRAP_MODE_POS   (10U)
+#define SF_CTRL_SF_CMDS_WRAP_MODE_LEN   (1U)
+#define SF_CTRL_SF_CMDS_WRAP_MODE_MSK   (((1U << SF_CTRL_SF_CMDS_WRAP_MODE_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_MODE_POS)
+#define SF_CTRL_SF_CMDS_WRAP_MODE_UMSK  (~(((1U << SF_CTRL_SF_CMDS_WRAP_MODE_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_MODE_POS))
+#define SF_CTRL_SF_CMDS_WRAP_Q          SF_CTRL_SF_CMDS_WRAP_Q
+#define SF_CTRL_SF_CMDS_WRAP_Q_POS      (11U)
+#define SF_CTRL_SF_CMDS_WRAP_Q_LEN      (1U)
+#define SF_CTRL_SF_CMDS_WRAP_Q_MSK      (((1U << SF_CTRL_SF_CMDS_WRAP_Q_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_POS)
+#define SF_CTRL_SF_CMDS_WRAP_Q_UMSK     (~(((1U << SF_CTRL_SF_CMDS_WRAP_Q_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_POS))
+#define SF_CTRL_SF_IF_1_ACK_LAT         SF_CTRL_SF_IF_1_ACK_LAT
+#define SF_CTRL_SF_IF_1_ACK_LAT_POS     (29U)
+#define SF_CTRL_SF_IF_1_ACK_LAT_LEN     (3U)
+#define SF_CTRL_SF_IF_1_ACK_LAT_MSK     (((1U << SF_CTRL_SF_IF_1_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_1_ACK_LAT_POS)
+#define SF_CTRL_SF_IF_1_ACK_LAT_UMSK    (~(((1U << SF_CTRL_SF_IF_1_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_1_ACK_LAT_POS))
+
+/* 0x78 : sf_if_iahb_3 */
+#define SF_CTRL_SF_IF_IAHB_3_OFFSET      (0x78)
+#define SF_CTRL_SF_IF_2_DMY_BYTE         SF_CTRL_SF_IF_2_DMY_BYTE
+#define SF_CTRL_SF_IF_2_DMY_BYTE_POS     (12U)
+#define SF_CTRL_SF_IF_2_DMY_BYTE_LEN     (5U)
+#define SF_CTRL_SF_IF_2_DMY_BYTE_MSK     (((1U << SF_CTRL_SF_IF_2_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_BYTE_POS)
+#define SF_CTRL_SF_IF_2_DMY_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_2_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_BYTE_POS))
+#define SF_CTRL_SF_IF_2_ADR_BYTE         SF_CTRL_SF_IF_2_ADR_BYTE
+#define SF_CTRL_SF_IF_2_ADR_BYTE_POS     (17U)
+#define SF_CTRL_SF_IF_2_ADR_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_2_ADR_BYTE_MSK     (((1U << SF_CTRL_SF_IF_2_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_BYTE_POS)
+#define SF_CTRL_SF_IF_2_ADR_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_2_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_BYTE_POS))
+#define SF_CTRL_SF_IF_2_CMD_BYTE         SF_CTRL_SF_IF_2_CMD_BYTE
+#define SF_CTRL_SF_IF_2_CMD_BYTE_POS     (20U)
+#define SF_CTRL_SF_IF_2_CMD_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_2_CMD_BYTE_MSK     (((1U << SF_CTRL_SF_IF_2_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BYTE_POS)
+#define SF_CTRL_SF_IF_2_CMD_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_2_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BYTE_POS))
+#define SF_CTRL_SF_IF_2_DAT_RW           SF_CTRL_SF_IF_2_DAT_RW
+#define SF_CTRL_SF_IF_2_DAT_RW_POS       (23U)
+#define SF_CTRL_SF_IF_2_DAT_RW_LEN       (1U)
+#define SF_CTRL_SF_IF_2_DAT_RW_MSK       (((1U << SF_CTRL_SF_IF_2_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_RW_POS)
+#define SF_CTRL_SF_IF_2_DAT_RW_UMSK      (~(((1U << SF_CTRL_SF_IF_2_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_RW_POS))
+#define SF_CTRL_SF_IF_2_DAT_EN           SF_CTRL_SF_IF_2_DAT_EN
+#define SF_CTRL_SF_IF_2_DAT_EN_POS       (24U)
+#define SF_CTRL_SF_IF_2_DAT_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_2_DAT_EN_MSK       (((1U << SF_CTRL_SF_IF_2_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_EN_POS)
+#define SF_CTRL_SF_IF_2_DAT_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_2_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_EN_POS))
+#define SF_CTRL_SF_IF_2_DMY_EN           SF_CTRL_SF_IF_2_DMY_EN
+#define SF_CTRL_SF_IF_2_DMY_EN_POS       (25U)
+#define SF_CTRL_SF_IF_2_DMY_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_2_DMY_EN_MSK       (((1U << SF_CTRL_SF_IF_2_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_EN_POS)
+#define SF_CTRL_SF_IF_2_DMY_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_2_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_EN_POS))
+#define SF_CTRL_SF_IF_2_ADR_EN           SF_CTRL_SF_IF_2_ADR_EN
+#define SF_CTRL_SF_IF_2_ADR_EN_POS       (26U)
+#define SF_CTRL_SF_IF_2_ADR_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_2_ADR_EN_MSK       (((1U << SF_CTRL_SF_IF_2_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_EN_POS)
+#define SF_CTRL_SF_IF_2_ADR_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_2_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_EN_POS))
+#define SF_CTRL_SF_IF_2_CMD_EN           SF_CTRL_SF_IF_2_CMD_EN
+#define SF_CTRL_SF_IF_2_CMD_EN_POS       (27U)
+#define SF_CTRL_SF_IF_2_CMD_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_2_CMD_EN_MSK       (((1U << SF_CTRL_SF_IF_2_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_EN_POS)
+#define SF_CTRL_SF_IF_2_CMD_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_2_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_EN_POS))
+#define SF_CTRL_SF_IF_2_SPI_MODE         SF_CTRL_SF_IF_2_SPI_MODE
+#define SF_CTRL_SF_IF_2_SPI_MODE_POS     (28U)
+#define SF_CTRL_SF_IF_2_SPI_MODE_LEN     (3U)
+#define SF_CTRL_SF_IF_2_SPI_MODE_MSK     (((1U << SF_CTRL_SF_IF_2_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_2_SPI_MODE_POS)
+#define SF_CTRL_SF_IF_2_SPI_MODE_UMSK    (~(((1U << SF_CTRL_SF_IF_2_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_2_SPI_MODE_POS))
+#define SF_CTRL_SF_IF_2_QPI_MODE_EN      SF_CTRL_SF_IF_2_QPI_MODE_EN
+#define SF_CTRL_SF_IF_2_QPI_MODE_EN_POS  (31U)
+#define SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN  (1U)
+#define SF_CTRL_SF_IF_2_QPI_MODE_EN_MSK  (((1U << SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_2_QPI_MODE_EN_POS)
+#define SF_CTRL_SF_IF_2_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_2_QPI_MODE_EN_POS))
+
+/* 0x7C : sf_if_iahb_4 */
+#define SF_CTRL_SF_IF_IAHB_4_OFFSET    (0x7C)
+#define SF_CTRL_SF_IF_2_CMD_BUF_0      SF_CTRL_SF_IF_2_CMD_BUF_0
+#define SF_CTRL_SF_IF_2_CMD_BUF_0_POS  (0U)
+#define SF_CTRL_SF_IF_2_CMD_BUF_0_LEN  (32U)
+#define SF_CTRL_SF_IF_2_CMD_BUF_0_MSK  (((1U << SF_CTRL_SF_IF_2_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_0_POS)
+#define SF_CTRL_SF_IF_2_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_0_POS))
+
+/* 0x80 : sf_if_iahb_5 */
+#define SF_CTRL_SF_IF_IAHB_5_OFFSET    (0x80)
+#define SF_CTRL_SF_IF_2_CMD_BUF_1      SF_CTRL_SF_IF_2_CMD_BUF_1
+#define SF_CTRL_SF_IF_2_CMD_BUF_1_POS  (0U)
+#define SF_CTRL_SF_IF_2_CMD_BUF_1_LEN  (32U)
+#define SF_CTRL_SF_IF_2_CMD_BUF_1_MSK  (((1U << SF_CTRL_SF_IF_2_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_1_POS)
+#define SF_CTRL_SF_IF_2_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_1_POS))
+
+/* 0x84 : sf_if_iahb_6 */
+#define SF_CTRL_SF_IF_IAHB_6_OFFSET      (0x84)
+#define SF_CTRL_SF_IF_3_ADR_BYTE         SF_CTRL_SF_IF_3_ADR_BYTE
+#define SF_CTRL_SF_IF_3_ADR_BYTE_POS     (17U)
+#define SF_CTRL_SF_IF_3_ADR_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_3_ADR_BYTE_MSK     (((1U << SF_CTRL_SF_IF_3_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_ADR_BYTE_POS)
+#define SF_CTRL_SF_IF_3_ADR_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_3_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_ADR_BYTE_POS))
+#define SF_CTRL_SF_IF_3_CMD_BYTE         SF_CTRL_SF_IF_3_CMD_BYTE
+#define SF_CTRL_SF_IF_3_CMD_BYTE_POS     (20U)
+#define SF_CTRL_SF_IF_3_CMD_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_3_CMD_BYTE_MSK     (((1U << SF_CTRL_SF_IF_3_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BYTE_POS)
+#define SF_CTRL_SF_IF_3_CMD_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_3_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BYTE_POS))
+#define SF_CTRL_SF_IF_3_ADR_EN           SF_CTRL_SF_IF_3_ADR_EN
+#define SF_CTRL_SF_IF_3_ADR_EN_POS       (26U)
+#define SF_CTRL_SF_IF_3_ADR_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_3_ADR_EN_MSK       (((1U << SF_CTRL_SF_IF_3_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_3_ADR_EN_POS)
+#define SF_CTRL_SF_IF_3_ADR_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_3_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_3_ADR_EN_POS))
+#define SF_CTRL_SF_IF_3_CMD_EN           SF_CTRL_SF_IF_3_CMD_EN
+#define SF_CTRL_SF_IF_3_CMD_EN_POS       (27U)
+#define SF_CTRL_SF_IF_3_CMD_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_3_CMD_EN_MSK       (((1U << SF_CTRL_SF_IF_3_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_EN_POS)
+#define SF_CTRL_SF_IF_3_CMD_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_3_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_EN_POS))
+#define SF_CTRL_SF_IF_3_SPI_MODE         SF_CTRL_SF_IF_3_SPI_MODE
+#define SF_CTRL_SF_IF_3_SPI_MODE_POS     (28U)
+#define SF_CTRL_SF_IF_3_SPI_MODE_LEN     (3U)
+#define SF_CTRL_SF_IF_3_SPI_MODE_MSK     (((1U << SF_CTRL_SF_IF_3_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_3_SPI_MODE_POS)
+#define SF_CTRL_SF_IF_3_SPI_MODE_UMSK    (~(((1U << SF_CTRL_SF_IF_3_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_3_SPI_MODE_POS))
+#define SF_CTRL_SF_IF_3_QPI_MODE_EN      SF_CTRL_SF_IF_3_QPI_MODE_EN
+#define SF_CTRL_SF_IF_3_QPI_MODE_EN_POS  (31U)
+#define SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN  (1U)
+#define SF_CTRL_SF_IF_3_QPI_MODE_EN_MSK  (((1U << SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_3_QPI_MODE_EN_POS)
+#define SF_CTRL_SF_IF_3_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_3_QPI_MODE_EN_POS))
+
+/* 0x88 : sf_if_iahb_7 */
+#define SF_CTRL_SF_IF_IAHB_7_OFFSET    (0x88)
+#define SF_CTRL_SF_IF_3_CMD_BUF_0      SF_CTRL_SF_IF_3_CMD_BUF_0
+#define SF_CTRL_SF_IF_3_CMD_BUF_0_POS  (0U)
+#define SF_CTRL_SF_IF_3_CMD_BUF_0_LEN  (32U)
+#define SF_CTRL_SF_IF_3_CMD_BUF_0_MSK  (((1U << SF_CTRL_SF_IF_3_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_0_POS)
+#define SF_CTRL_SF_IF_3_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_3_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_0_POS))
+
+/* 0x8C : sf_if_iahb_8 */
+#define SF_CTRL_SF_IF_IAHB_8_OFFSET    (0x8C)
+#define SF_CTRL_SF_IF_3_CMD_BUF_1      SF_CTRL_SF_IF_3_CMD_BUF_1
+#define SF_CTRL_SF_IF_3_CMD_BUF_1_POS  (0U)
+#define SF_CTRL_SF_IF_3_CMD_BUF_1_LEN  (32U)
+#define SF_CTRL_SF_IF_3_CMD_BUF_1_MSK  (((1U << SF_CTRL_SF_IF_3_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_1_POS)
+#define SF_CTRL_SF_IF_3_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_3_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_1_POS))
+
+/* 0x90 : sf_if_iahb_9 */
+#define SF_CTRL_SF_IF_IAHB_9_OFFSET      (0x90)
+#define SF_CTRL_SF_IF_4_DMY_BYTE         SF_CTRL_SF_IF_4_DMY_BYTE
+#define SF_CTRL_SF_IF_4_DMY_BYTE_POS     (12U)
+#define SF_CTRL_SF_IF_4_DMY_BYTE_LEN     (5U)
+#define SF_CTRL_SF_IF_4_DMY_BYTE_MSK     (((1U << SF_CTRL_SF_IF_4_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_DMY_BYTE_POS)
+#define SF_CTRL_SF_IF_4_DMY_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_4_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_DMY_BYTE_POS))
+#define SF_CTRL_SF_IF_4_ADR_BYTE         SF_CTRL_SF_IF_4_ADR_BYTE
+#define SF_CTRL_SF_IF_4_ADR_BYTE_POS     (17U)
+#define SF_CTRL_SF_IF_4_ADR_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_4_ADR_BYTE_MSK     (((1U << SF_CTRL_SF_IF_4_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_ADR_BYTE_POS)
+#define SF_CTRL_SF_IF_4_ADR_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_4_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_ADR_BYTE_POS))
+#define SF_CTRL_SF_IF_4_CMD_BYTE         SF_CTRL_SF_IF_4_CMD_BYTE
+#define SF_CTRL_SF_IF_4_CMD_BYTE_POS     (20U)
+#define SF_CTRL_SF_IF_4_CMD_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_4_CMD_BYTE_MSK     (((1U << SF_CTRL_SF_IF_4_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BYTE_POS)
+#define SF_CTRL_SF_IF_4_CMD_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_4_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BYTE_POS))
+#define SF_CTRL_SF_IF_4_DAT_RW           SF_CTRL_SF_IF_4_DAT_RW
+#define SF_CTRL_SF_IF_4_DAT_RW_POS       (23U)
+#define SF_CTRL_SF_IF_4_DAT_RW_LEN       (1U)
+#define SF_CTRL_SF_IF_4_DAT_RW_MSK       (((1U << SF_CTRL_SF_IF_4_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_4_DAT_RW_POS)
+#define SF_CTRL_SF_IF_4_DAT_RW_UMSK      (~(((1U << SF_CTRL_SF_IF_4_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_4_DAT_RW_POS))
+#define SF_CTRL_SF_IF_4_DAT_EN           SF_CTRL_SF_IF_4_DAT_EN
+#define SF_CTRL_SF_IF_4_DAT_EN_POS       (24U)
+#define SF_CTRL_SF_IF_4_DAT_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_4_DAT_EN_MSK       (((1U << SF_CTRL_SF_IF_4_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_4_DAT_EN_POS)
+#define SF_CTRL_SF_IF_4_DAT_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_4_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_4_DAT_EN_POS))
+#define SF_CTRL_SF_IF_4_DMY_EN           SF_CTRL_SF_IF_4_DMY_EN
+#define SF_CTRL_SF_IF_4_DMY_EN_POS       (25U)
+#define SF_CTRL_SF_IF_4_DMY_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_4_DMY_EN_MSK       (((1U << SF_CTRL_SF_IF_4_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_4_DMY_EN_POS)
+#define SF_CTRL_SF_IF_4_DMY_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_4_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_4_DMY_EN_POS))
+#define SF_CTRL_SF_IF_4_ADR_EN           SF_CTRL_SF_IF_4_ADR_EN
+#define SF_CTRL_SF_IF_4_ADR_EN_POS       (26U)
+#define SF_CTRL_SF_IF_4_ADR_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_4_ADR_EN_MSK       (((1U << SF_CTRL_SF_IF_4_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_4_ADR_EN_POS)
+#define SF_CTRL_SF_IF_4_ADR_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_4_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_4_ADR_EN_POS))
+#define SF_CTRL_SF_IF_4_CMD_EN           SF_CTRL_SF_IF_4_CMD_EN
+#define SF_CTRL_SF_IF_4_CMD_EN_POS       (27U)
+#define SF_CTRL_SF_IF_4_CMD_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_4_CMD_EN_MSK       (((1U << SF_CTRL_SF_IF_4_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_EN_POS)
+#define SF_CTRL_SF_IF_4_CMD_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_4_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_EN_POS))
+#define SF_CTRL_SF_IF_4_SPI_MODE         SF_CTRL_SF_IF_4_SPI_MODE
+#define SF_CTRL_SF_IF_4_SPI_MODE_POS     (28U)
+#define SF_CTRL_SF_IF_4_SPI_MODE_LEN     (3U)
+#define SF_CTRL_SF_IF_4_SPI_MODE_MSK     (((1U << SF_CTRL_SF_IF_4_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_4_SPI_MODE_POS)
+#define SF_CTRL_SF_IF_4_SPI_MODE_UMSK    (~(((1U << SF_CTRL_SF_IF_4_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_4_SPI_MODE_POS))
+#define SF_CTRL_SF_IF_4_QPI_MODE_EN      SF_CTRL_SF_IF_4_QPI_MODE_EN
+#define SF_CTRL_SF_IF_4_QPI_MODE_EN_POS  (31U)
+#define SF_CTRL_SF_IF_4_QPI_MODE_EN_LEN  (1U)
+#define SF_CTRL_SF_IF_4_QPI_MODE_EN_MSK  (((1U << SF_CTRL_SF_IF_4_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_4_QPI_MODE_EN_POS)
+#define SF_CTRL_SF_IF_4_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_4_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_4_QPI_MODE_EN_POS))
+
+/* 0x94 : sf_if_iahb_10 */
+#define SF_CTRL_SF_IF_IAHB_10_OFFSET   (0x94)
+#define SF_CTRL_SF_IF_4_CMD_BUF_0      SF_CTRL_SF_IF_4_CMD_BUF_0
+#define SF_CTRL_SF_IF_4_CMD_BUF_0_POS  (0U)
+#define SF_CTRL_SF_IF_4_CMD_BUF_0_LEN  (32U)
+#define SF_CTRL_SF_IF_4_CMD_BUF_0_MSK  (((1U << SF_CTRL_SF_IF_4_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BUF_0_POS)
+#define SF_CTRL_SF_IF_4_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_4_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BUF_0_POS))
+
+/* 0x98 : sf_if_iahb_11 */
+#define SF_CTRL_SF_IF_IAHB_11_OFFSET   (0x98)
+#define SF_CTRL_SF_IF_4_CMD_BUF_1      SF_CTRL_SF_IF_4_CMD_BUF_1
+#define SF_CTRL_SF_IF_4_CMD_BUF_1_POS  (0U)
+#define SF_CTRL_SF_IF_4_CMD_BUF_1_LEN  (32U)
+#define SF_CTRL_SF_IF_4_CMD_BUF_1_MSK  (((1U << SF_CTRL_SF_IF_4_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BUF_1_POS)
+#define SF_CTRL_SF_IF_4_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_4_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BUF_1_POS))
+
+/* 0x9C : sf_if_iahb_12 */
+#define SF_CTRL_SF_IF_IAHB_12_OFFSET       (0x9C)
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL      SF_CTRL_SF2_CLK_SF_RX_INV_SEL
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL_POS  (2U)
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL_LEN  (1U)
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL_MSK  (((1U << SF_CTRL_SF2_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_SF_RX_INV_SEL_POS)
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL_UMSK (~(((1U << SF_CTRL_SF2_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_SF_RX_INV_SEL_POS))
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC      SF_CTRL_SF2_CLK_SF_RX_INV_SRC
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC_POS  (3U)
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC_LEN  (1U)
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC_MSK  (((1U << SF_CTRL_SF2_CLK_SF_RX_INV_SRC_LEN) - 1) << SF_CTRL_SF2_CLK_SF_RX_INV_SRC_POS)
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC_UMSK (~(((1U << SF_CTRL_SF2_CLK_SF_RX_INV_SRC_LEN) - 1) << SF_CTRL_SF2_CLK_SF_RX_INV_SRC_POS))
+#define SF_CTRL_SF2_CLK_OUT_INV_SEL        SF_CTRL_SF2_CLK_OUT_INV_SEL
+#define SF_CTRL_SF2_CLK_OUT_INV_SEL_POS    (4U)
+#define SF_CTRL_SF2_CLK_OUT_INV_SEL_LEN    (1U)
+#define SF_CTRL_SF2_CLK_OUT_INV_SEL_MSK    (((1U << SF_CTRL_SF2_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_INV_SEL_POS)
+#define SF_CTRL_SF2_CLK_OUT_INV_SEL_UMSK   (~(((1U << SF_CTRL_SF2_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_INV_SEL_POS))
+#define SF_CTRL_SF3_CLK_OUT_INV_SEL        SF_CTRL_SF3_CLK_OUT_INV_SEL
+#define SF_CTRL_SF3_CLK_OUT_INV_SEL_POS    (5U)
+#define SF_CTRL_SF3_CLK_OUT_INV_SEL_LEN    (1U)
+#define SF_CTRL_SF3_CLK_OUT_INV_SEL_MSK    (((1U << SF_CTRL_SF3_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_INV_SEL_POS)
+#define SF_CTRL_SF3_CLK_OUT_INV_SEL_UMSK   (~(((1U << SF_CTRL_SF3_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_INV_SEL_POS))
+#define SF_CTRL_SF2_IF_READ_DLY_N          SF_CTRL_SF2_IF_READ_DLY_N
+#define SF_CTRL_SF2_IF_READ_DLY_N_POS      (8U)
+#define SF_CTRL_SF2_IF_READ_DLY_N_LEN      (3U)
+#define SF_CTRL_SF2_IF_READ_DLY_N_MSK      (((1U << SF_CTRL_SF2_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_N_POS)
+#define SF_CTRL_SF2_IF_READ_DLY_N_UMSK     (~(((1U << SF_CTRL_SF2_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_N_POS))
+#define SF_CTRL_SF2_IF_READ_DLY_EN         SF_CTRL_SF2_IF_READ_DLY_EN
+#define SF_CTRL_SF2_IF_READ_DLY_EN_POS     (11U)
+#define SF_CTRL_SF2_IF_READ_DLY_EN_LEN     (1U)
+#define SF_CTRL_SF2_IF_READ_DLY_EN_MSK     (((1U << SF_CTRL_SF2_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_EN_POS)
+#define SF_CTRL_SF2_IF_READ_DLY_EN_UMSK    (~(((1U << SF_CTRL_SF2_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_EN_POS))
+#define SF_CTRL_SF2_IF_READ_DLY_SRC        SF_CTRL_SF2_IF_READ_DLY_SRC
+#define SF_CTRL_SF2_IF_READ_DLY_SRC_POS    (12U)
+#define SF_CTRL_SF2_IF_READ_DLY_SRC_LEN    (1U)
+#define SF_CTRL_SF2_IF_READ_DLY_SRC_MSK    (((1U << SF_CTRL_SF2_IF_READ_DLY_SRC_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_SRC_POS)
+#define SF_CTRL_SF2_IF_READ_DLY_SRC_UMSK   (~(((1U << SF_CTRL_SF2_IF_READ_DLY_SRC_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_SRC_POS))
+
+/* 0x100 : sf_ctrl_prot_en_rd */
+#define SF_CTRL_PROT_EN_RD_OFFSET         (0x100)
+#define SF_CTRL_PROT_EN_RD                SF_CTRL_PROT_EN_RD
+#define SF_CTRL_PROT_EN_RD_POS            (0U)
+#define SF_CTRL_PROT_EN_RD_LEN            (1U)
+#define SF_CTRL_PROT_EN_RD_MSK            (((1U << SF_CTRL_PROT_EN_RD_LEN) - 1) << SF_CTRL_PROT_EN_RD_POS)
+#define SF_CTRL_PROT_EN_RD_UMSK           (~(((1U << SF_CTRL_PROT_EN_RD_LEN) - 1) << SF_CTRL_PROT_EN_RD_POS))
+#define SF_CTRL_ID0_EN_RD                 SF_CTRL_ID0_EN_RD
+#define SF_CTRL_ID0_EN_RD_POS             (1U)
+#define SF_CTRL_ID0_EN_RD_LEN             (1U)
+#define SF_CTRL_ID0_EN_RD_MSK             (((1U << SF_CTRL_ID0_EN_RD_LEN) - 1) << SF_CTRL_ID0_EN_RD_POS)
+#define SF_CTRL_ID0_EN_RD_UMSK            (~(((1U << SF_CTRL_ID0_EN_RD_LEN) - 1) << SF_CTRL_ID0_EN_RD_POS))
+#define SF_CTRL_ID1_EN_RD                 SF_CTRL_ID1_EN_RD
+#define SF_CTRL_ID1_EN_RD_POS             (2U)
+#define SF_CTRL_ID1_EN_RD_LEN             (1U)
+#define SF_CTRL_ID1_EN_RD_MSK             (((1U << SF_CTRL_ID1_EN_RD_LEN) - 1) << SF_CTRL_ID1_EN_RD_POS)
+#define SF_CTRL_ID1_EN_RD_UMSK            (~(((1U << SF_CTRL_ID1_EN_RD_LEN) - 1) << SF_CTRL_ID1_EN_RD_POS))
+#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK      SF_CTRL_SF_IF_0_TRIG_WR_LOCK
+#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS  (30U)
+#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN  (1U)
+#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_MSK  (((1U << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS)
+#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_UMSK (~(((1U << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS))
+#define SF_CTRL_SF_DBG_DIS                SF_CTRL_SF_DBG_DIS
+#define SF_CTRL_SF_DBG_DIS_POS            (31U)
+#define SF_CTRL_SF_DBG_DIS_LEN            (1U)
+#define SF_CTRL_SF_DBG_DIS_MSK            (((1U << SF_CTRL_SF_DBG_DIS_LEN) - 1) << SF_CTRL_SF_DBG_DIS_POS)
+#define SF_CTRL_SF_DBG_DIS_UMSK           (~(((1U << SF_CTRL_SF_DBG_DIS_LEN) - 1) << SF_CTRL_SF_DBG_DIS_POS))
+
+/* 0x104 : sf_ctrl_prot_en */
+#define SF_CTRL_PROT_EN_OFFSET (0x104)
+#define SF_CTRL_PROT_EN        SF_CTRL_PROT_EN
+#define SF_CTRL_PROT_EN_POS    (0U)
+#define SF_CTRL_PROT_EN_LEN    (1U)
+#define SF_CTRL_PROT_EN_MSK    (((1U << SF_CTRL_PROT_EN_LEN) - 1) << SF_CTRL_PROT_EN_POS)
+#define SF_CTRL_PROT_EN_UMSK   (~(((1U << SF_CTRL_PROT_EN_LEN) - 1) << SF_CTRL_PROT_EN_POS))
+#define SF_CTRL_ID0_EN         SF_CTRL_ID0_EN
+#define SF_CTRL_ID0_EN_POS     (1U)
+#define SF_CTRL_ID0_EN_LEN     (1U)
+#define SF_CTRL_ID0_EN_MSK     (((1U << SF_CTRL_ID0_EN_LEN) - 1) << SF_CTRL_ID0_EN_POS)
+#define SF_CTRL_ID0_EN_UMSK    (~(((1U << SF_CTRL_ID0_EN_LEN) - 1) << SF_CTRL_ID0_EN_POS))
+#define SF_CTRL_ID1_EN         SF_CTRL_ID1_EN
+#define SF_CTRL_ID1_EN_POS     (2U)
+#define SF_CTRL_ID1_EN_LEN     (1U)
+#define SF_CTRL_ID1_EN_MSK     (((1U << SF_CTRL_ID1_EN_LEN) - 1) << SF_CTRL_ID1_EN_POS)
+#define SF_CTRL_ID1_EN_UMSK    (~(((1U << SF_CTRL_ID1_EN_LEN) - 1) << SF_CTRL_ID1_EN_POS))
+
+/* 0x200 : sf_aes_key_r0_0 */
+#define SF_CTRL_SF_AES_KEY_R0_0_OFFSET (0x200)
+#define SF_CTRL_SF_AES_KEY_R0_0        SF_CTRL_SF_AES_KEY_R0_0
+#define SF_CTRL_SF_AES_KEY_R0_0_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R0_0_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R0_0_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_0_POS)
+#define SF_CTRL_SF_AES_KEY_R0_0_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_0_POS))
+
+/* 0x204 : sf_aes_key_r0_1 */
+#define SF_CTRL_SF_AES_KEY_R0_1_OFFSET (0x204)
+#define SF_CTRL_SF_AES_KEY_R0_1        SF_CTRL_SF_AES_KEY_R0_1
+#define SF_CTRL_SF_AES_KEY_R0_1_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R0_1_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R0_1_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_1_POS)
+#define SF_CTRL_SF_AES_KEY_R0_1_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_1_POS))
+
+/* 0x208 : sf_aes_key_r0_2 */
+#define SF_CTRL_SF_AES_KEY_R0_2_OFFSET (0x208)
+#define SF_CTRL_SF_AES_KEY_R0_2        SF_CTRL_SF_AES_KEY_R0_2
+#define SF_CTRL_SF_AES_KEY_R0_2_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R0_2_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R0_2_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_2_POS)
+#define SF_CTRL_SF_AES_KEY_R0_2_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_2_POS))
+
+/* 0x20C : sf_aes_key_r0_3 */
+#define SF_CTRL_SF_AES_KEY_R0_3_OFFSET (0x20C)
+#define SF_CTRL_SF_AES_KEY_R0_3        SF_CTRL_SF_AES_KEY_R0_3
+#define SF_CTRL_SF_AES_KEY_R0_3_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R0_3_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R0_3_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_3_POS)
+#define SF_CTRL_SF_AES_KEY_R0_3_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_3_POS))
+
+/* 0x210 : sf_aes_key_r0_4 */
+#define SF_CTRL_SF_AES_KEY_R0_4_OFFSET (0x210)
+#define SF_CTRL_SF_AES_KEY_R0_4        SF_CTRL_SF_AES_KEY_R0_4
+#define SF_CTRL_SF_AES_KEY_R0_4_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R0_4_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R0_4_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_4_POS)
+#define SF_CTRL_SF_AES_KEY_R0_4_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_4_POS))
+
+/* 0x214 : sf_aes_key_r0_5 */
+#define SF_CTRL_SF_AES_KEY_R0_5_OFFSET (0x214)
+#define SF_CTRL_SF_AES_KEY_R0_5        SF_CTRL_SF_AES_KEY_R0_5
+#define SF_CTRL_SF_AES_KEY_R0_5_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R0_5_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R0_5_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_5_POS)
+#define SF_CTRL_SF_AES_KEY_R0_5_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_5_POS))
+
+/* 0x218 : sf_aes_key_r0_6 */
+#define SF_CTRL_SF_AES_KEY_R0_6_OFFSET (0x218)
+#define SF_CTRL_SF_AES_KEY_R0_6        SF_CTRL_SF_AES_KEY_R0_6
+#define SF_CTRL_SF_AES_KEY_R0_6_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R0_6_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R0_6_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_6_POS)
+#define SF_CTRL_SF_AES_KEY_R0_6_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_6_POS))
+
+/* 0x21C : sf_aes_key_r0_7 */
+#define SF_CTRL_SF_AES_KEY_R0_7_OFFSET (0x21C)
+#define SF_CTRL_SF_AES_KEY_R0_7        SF_CTRL_SF_AES_KEY_R0_7
+#define SF_CTRL_SF_AES_KEY_R0_7_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R0_7_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R0_7_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_7_POS)
+#define SF_CTRL_SF_AES_KEY_R0_7_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_7_POS))
+
+/* 0x220 : sf_aes_iv_r0_w0 */
+#define SF_CTRL_SF_AES_IV_R0_W0_OFFSET (0x220)
+#define SF_CTRL_SF_AES_IV_R0_W0        SF_CTRL_SF_AES_IV_R0_W0
+#define SF_CTRL_SF_AES_IV_R0_W0_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R0_W0_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R0_W0_MSK    (((1U << SF_CTRL_SF_AES_IV_R0_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W0_POS)
+#define SF_CTRL_SF_AES_IV_R0_W0_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R0_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W0_POS))
+
+/* 0x224 : sf_aes_iv_r0_w1 */
+#define SF_CTRL_SF_AES_IV_R0_W1_OFFSET (0x224)
+#define SF_CTRL_SF_AES_IV_R0_W1        SF_CTRL_SF_AES_IV_R0_W1
+#define SF_CTRL_SF_AES_IV_R0_W1_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R0_W1_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R0_W1_MSK    (((1U << SF_CTRL_SF_AES_IV_R0_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W1_POS)
+#define SF_CTRL_SF_AES_IV_R0_W1_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R0_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W1_POS))
+
+/* 0x228 : sf_aes_iv_r0_w2 */
+#define SF_CTRL_SF_AES_IV_R0_W2_OFFSET (0x228)
+#define SF_CTRL_SF_AES_IV_R0_W2        SF_CTRL_SF_AES_IV_R0_W2
+#define SF_CTRL_SF_AES_IV_R0_W2_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R0_W2_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R0_W2_MSK    (((1U << SF_CTRL_SF_AES_IV_R0_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W2_POS)
+#define SF_CTRL_SF_AES_IV_R0_W2_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R0_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W2_POS))
+
+/* 0x22C : sf_aes_iv_r0_w3 */
+#define SF_CTRL_SF_AES_IV_R0_W3_OFFSET (0x22C)
+#define SF_CTRL_SF_AES_IV_R0_W3        SF_CTRL_SF_AES_IV_R0_W3
+#define SF_CTRL_SF_AES_IV_R0_W3_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R0_W3_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R0_W3_MSK    (((1U << SF_CTRL_SF_AES_IV_R0_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W3_POS)
+#define SF_CTRL_SF_AES_IV_R0_W3_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R0_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W3_POS))
+
+/* 0x230 : sf_aes_cfg_r0 */
+#define SF_CTRL_SF_AES_CFG_R0_OFFSET            (0x230)
+#define SF_CTRL_SF_AES_REGION_R0_END            SF_CTRL_SF_AES_REGION_R0_END
+#define SF_CTRL_SF_AES_REGION_R0_END_POS        (0U)
+#define SF_CTRL_SF_AES_REGION_R0_END_LEN        (14U)
+#define SF_CTRL_SF_AES_REGION_R0_END_MSK        (((1U << SF_CTRL_SF_AES_REGION_R0_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_END_POS)
+#define SF_CTRL_SF_AES_REGION_R0_END_UMSK       (~(((1U << SF_CTRL_SF_AES_REGION_R0_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_END_POS))
+#define SF_CTRL_SF_AES_REGION_R0_START          SF_CTRL_SF_AES_REGION_R0_START
+#define SF_CTRL_SF_AES_REGION_R0_START_POS      (14U)
+#define SF_CTRL_SF_AES_REGION_R0_START_LEN      (14U)
+#define SF_CTRL_SF_AES_REGION_R0_START_MSK      (((1U << SF_CTRL_SF_AES_REGION_R0_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_START_POS)
+#define SF_CTRL_SF_AES_REGION_R0_START_UMSK     (~(((1U << SF_CTRL_SF_AES_REGION_R0_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_START_POS))
+#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN      SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN
+#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS  (29U)
+#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN  (1U)
+#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_MSK  (((1U << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS)
+#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS))
+#define SF_CTRL_SF_AES_REGION_R0_EN             SF_CTRL_SF_AES_REGION_R0_EN
+#define SF_CTRL_SF_AES_REGION_R0_EN_POS         (30U)
+#define SF_CTRL_SF_AES_REGION_R0_EN_LEN         (1U)
+#define SF_CTRL_SF_AES_REGION_R0_EN_MSK         (((1U << SF_CTRL_SF_AES_REGION_R0_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_EN_POS)
+#define SF_CTRL_SF_AES_REGION_R0_EN_UMSK        (~(((1U << SF_CTRL_SF_AES_REGION_R0_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_EN_POS))
+#define SF_CTRL_SF_AES_REGION_R0_LOCK           SF_CTRL_SF_AES_REGION_R0_LOCK
+#define SF_CTRL_SF_AES_REGION_R0_LOCK_POS       (31U)
+#define SF_CTRL_SF_AES_REGION_R0_LOCK_LEN       (1U)
+#define SF_CTRL_SF_AES_REGION_R0_LOCK_MSK       (((1U << SF_CTRL_SF_AES_REGION_R0_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_LOCK_POS)
+#define SF_CTRL_SF_AES_REGION_R0_LOCK_UMSK      (~(((1U << SF_CTRL_SF_AES_REGION_R0_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_LOCK_POS))
+
+/* 0x300 : sf_aes_key_r1_0 */
+#define SF_CTRL_SF_AES_KEY_R1_0_OFFSET (0x300)
+#define SF_CTRL_SF_AES_KEY_R1_0        SF_CTRL_SF_AES_KEY_R1_0
+#define SF_CTRL_SF_AES_KEY_R1_0_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R1_0_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R1_0_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_0_POS)
+#define SF_CTRL_SF_AES_KEY_R1_0_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_0_POS))
+
+/* 0x304 : sf_aes_key_r1_1 */
+#define SF_CTRL_SF_AES_KEY_R1_1_OFFSET (0x304)
+#define SF_CTRL_SF_AES_KEY_R1_1        SF_CTRL_SF_AES_KEY_R1_1
+#define SF_CTRL_SF_AES_KEY_R1_1_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R1_1_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R1_1_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_1_POS)
+#define SF_CTRL_SF_AES_KEY_R1_1_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_1_POS))
+
+/* 0x308 : sf_aes_key_r1_2 */
+#define SF_CTRL_SF_AES_KEY_R1_2_OFFSET (0x308)
+#define SF_CTRL_SF_AES_KEY_R1_2        SF_CTRL_SF_AES_KEY_R1_2
+#define SF_CTRL_SF_AES_KEY_R1_2_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R1_2_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R1_2_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_2_POS)
+#define SF_CTRL_SF_AES_KEY_R1_2_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_2_POS))
+
+/* 0x30C : sf_aes_key_r1_3 */
+#define SF_CTRL_SF_AES_KEY_R1_3_OFFSET (0x30C)
+#define SF_CTRL_SF_AES_KEY_R1_3        SF_CTRL_SF_AES_KEY_R1_3
+#define SF_CTRL_SF_AES_KEY_R1_3_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R1_3_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R1_3_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_3_POS)
+#define SF_CTRL_SF_AES_KEY_R1_3_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_3_POS))
+
+/* 0x310 : sf_aes_key_r1_4 */
+#define SF_CTRL_SF_AES_KEY_R1_4_OFFSET (0x310)
+#define SF_CTRL_SF_AES_KEY_R1_4        SF_CTRL_SF_AES_KEY_R1_4
+#define SF_CTRL_SF_AES_KEY_R1_4_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R1_4_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R1_4_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_4_POS)
+#define SF_CTRL_SF_AES_KEY_R1_4_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_4_POS))
+
+/* 0x314 : sf_aes_key_r1_5 */
+#define SF_CTRL_SF_AES_KEY_R1_5_OFFSET (0x314)
+#define SF_CTRL_SF_AES_KEY_R1_5        SF_CTRL_SF_AES_KEY_R1_5
+#define SF_CTRL_SF_AES_KEY_R1_5_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R1_5_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R1_5_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_5_POS)
+#define SF_CTRL_SF_AES_KEY_R1_5_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_5_POS))
+
+/* 0x318 : sf_aes_key_r1_6 */
+#define SF_CTRL_SF_AES_KEY_R1_6_OFFSET (0x318)
+#define SF_CTRL_SF_AES_KEY_R1_6        SF_CTRL_SF_AES_KEY_R1_6
+#define SF_CTRL_SF_AES_KEY_R1_6_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R1_6_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R1_6_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_6_POS)
+#define SF_CTRL_SF_AES_KEY_R1_6_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_6_POS))
+
+/* 0x31C : sf_aes_key_r1_7 */
+#define SF_CTRL_SF_AES_KEY_R1_7_OFFSET (0x31C)
+#define SF_CTRL_SF_AES_KEY_R1_7        SF_CTRL_SF_AES_KEY_R1_7
+#define SF_CTRL_SF_AES_KEY_R1_7_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R1_7_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R1_7_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_7_POS)
+#define SF_CTRL_SF_AES_KEY_R1_7_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_7_POS))
+
+/* 0x320 : sf_aes_iv_r1_w0 */
+#define SF_CTRL_SF_AES_IV_R1_W0_OFFSET (0x320)
+#define SF_CTRL_SF_AES_IV_R1_W0        SF_CTRL_SF_AES_IV_R1_W0
+#define SF_CTRL_SF_AES_IV_R1_W0_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R1_W0_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R1_W0_MSK    (((1U << SF_CTRL_SF_AES_IV_R1_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W0_POS)
+#define SF_CTRL_SF_AES_IV_R1_W0_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R1_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W0_POS))
+
+/* 0x324 : sf_aes_iv_r1_w1 */
+#define SF_CTRL_SF_AES_IV_R1_W1_OFFSET (0x324)
+#define SF_CTRL_SF_AES_IV_R1_W1        SF_CTRL_SF_AES_IV_R1_W1
+#define SF_CTRL_SF_AES_IV_R1_W1_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R1_W1_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R1_W1_MSK    (((1U << SF_CTRL_SF_AES_IV_R1_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W1_POS)
+#define SF_CTRL_SF_AES_IV_R1_W1_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R1_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W1_POS))
+
+/* 0x328 : sf_aes_iv_r1_w2 */
+#define SF_CTRL_SF_AES_IV_R1_W2_OFFSET (0x328)
+#define SF_CTRL_SF_AES_IV_R1_W2        SF_CTRL_SF_AES_IV_R1_W2
+#define SF_CTRL_SF_AES_IV_R1_W2_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R1_W2_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R1_W2_MSK    (((1U << SF_CTRL_SF_AES_IV_R1_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W2_POS)
+#define SF_CTRL_SF_AES_IV_R1_W2_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R1_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W2_POS))
+
+/* 0x32C : sf_aes_iv_r1_w3 */
+#define SF_CTRL_SF_AES_IV_R1_W3_OFFSET (0x32C)
+#define SF_CTRL_SF_AES_IV_R1_W3        SF_CTRL_SF_AES_IV_R1_W3
+#define SF_CTRL_SF_AES_IV_R1_W3_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R1_W3_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R1_W3_MSK    (((1U << SF_CTRL_SF_AES_IV_R1_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W3_POS)
+#define SF_CTRL_SF_AES_IV_R1_W3_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R1_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W3_POS))
+
+/* 0x330 : sf_aes_r1 */
+#define SF_CTRL_SF_AES_R1_OFFSET         (0x330)
+#define SF_CTRL_SF_AES_R1_END            SF_CTRL_SF_AES_R1_END
+#define SF_CTRL_SF_AES_R1_END_POS        (0U)
+#define SF_CTRL_SF_AES_R1_END_LEN        (14U)
+#define SF_CTRL_SF_AES_R1_END_MSK        (((1U << SF_CTRL_SF_AES_R1_END_LEN) - 1) << SF_CTRL_SF_AES_R1_END_POS)
+#define SF_CTRL_SF_AES_R1_END_UMSK       (~(((1U << SF_CTRL_SF_AES_R1_END_LEN) - 1) << SF_CTRL_SF_AES_R1_END_POS))
+#define SF_CTRL_SF_AES_R1_START          SF_CTRL_SF_AES_R1_START
+#define SF_CTRL_SF_AES_R1_START_POS      (14U)
+#define SF_CTRL_SF_AES_R1_START_LEN      (14U)
+#define SF_CTRL_SF_AES_R1_START_MSK      (((1U << SF_CTRL_SF_AES_R1_START_LEN) - 1) << SF_CTRL_SF_AES_R1_START_POS)
+#define SF_CTRL_SF_AES_R1_START_UMSK     (~(((1U << SF_CTRL_SF_AES_R1_START_LEN) - 1) << SF_CTRL_SF_AES_R1_START_POS))
+#define SF_CTRL_SF_AES_R1_HW_KEY_EN      SF_CTRL_SF_AES_R1_HW_KEY_EN
+#define SF_CTRL_SF_AES_R1_HW_KEY_EN_POS  (29U)
+#define SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN  (1U)
+#define SF_CTRL_SF_AES_R1_HW_KEY_EN_MSK  (((1U << SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_HW_KEY_EN_POS)
+#define SF_CTRL_SF_AES_R1_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_HW_KEY_EN_POS))
+#define SF_CTRL_SF_AES_R1_EN             SF_CTRL_SF_AES_R1_EN
+#define SF_CTRL_SF_AES_R1_EN_POS         (30U)
+#define SF_CTRL_SF_AES_R1_EN_LEN         (1U)
+#define SF_CTRL_SF_AES_R1_EN_MSK         (((1U << SF_CTRL_SF_AES_R1_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_EN_POS)
+#define SF_CTRL_SF_AES_R1_EN_UMSK        (~(((1U << SF_CTRL_SF_AES_R1_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_EN_POS))
+#define SF_CTRL_SF_AES_R1_LOCK           SF_CTRL_SF_AES_R1_LOCK
+#define SF_CTRL_SF_AES_R1_LOCK_POS       (31U)
+#define SF_CTRL_SF_AES_R1_LOCK_LEN       (1U)
+#define SF_CTRL_SF_AES_R1_LOCK_MSK       (((1U << SF_CTRL_SF_AES_R1_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R1_LOCK_POS)
+#define SF_CTRL_SF_AES_R1_LOCK_UMSK      (~(((1U << SF_CTRL_SF_AES_R1_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R1_LOCK_POS))
+
+/* 0x400 : sf_aes_key_r2_0 */
+#define SF_CTRL_SF_AES_KEY_R2_0_OFFSET (0x400)
+#define SF_CTRL_SF_AES_KEY_R2_0        SF_CTRL_SF_AES_KEY_R2_0
+#define SF_CTRL_SF_AES_KEY_R2_0_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R2_0_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R2_0_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_0_POS)
+#define SF_CTRL_SF_AES_KEY_R2_0_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_0_POS))
+
+/* 0x404 : sf_aes_key_r2_1 */
+#define SF_CTRL_SF_AES_KEY_R2_1_OFFSET (0x404)
+#define SF_CTRL_SF_AES_KEY_R2_1        SF_CTRL_SF_AES_KEY_R2_1
+#define SF_CTRL_SF_AES_KEY_R2_1_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R2_1_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R2_1_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_1_POS)
+#define SF_CTRL_SF_AES_KEY_R2_1_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_1_POS))
+
+/* 0x408 : sf_aes_key_r2_2 */
+#define SF_CTRL_SF_AES_KEY_R2_2_OFFSET (0x408)
+#define SF_CTRL_SF_AES_KEY_R2_2        SF_CTRL_SF_AES_KEY_R2_2
+#define SF_CTRL_SF_AES_KEY_R2_2_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R2_2_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R2_2_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_2_POS)
+#define SF_CTRL_SF_AES_KEY_R2_2_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_2_POS))
+
+/* 0x40C : sf_aes_key_r2_3 */
+#define SF_CTRL_SF_AES_KEY_R2_3_OFFSET (0x40C)
+#define SF_CTRL_SF_AES_KEY_R2_3        SF_CTRL_SF_AES_KEY_R2_3
+#define SF_CTRL_SF_AES_KEY_R2_3_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R2_3_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R2_3_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_3_POS)
+#define SF_CTRL_SF_AES_KEY_R2_3_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_3_POS))
+
+/* 0x410 : sf_aes_key_r2_4 */
+#define SF_CTRL_SF_AES_KEY_R2_4_OFFSET (0x410)
+#define SF_CTRL_SF_AES_KEY_R2_4        SF_CTRL_SF_AES_KEY_R2_4
+#define SF_CTRL_SF_AES_KEY_R2_4_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R2_4_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R2_4_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_4_POS)
+#define SF_CTRL_SF_AES_KEY_R2_4_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_4_POS))
+
+/* 0x414 : sf_aes_key_r2_5 */
+#define SF_CTRL_SF_AES_KEY_R2_5_OFFSET (0x414)
+#define SF_CTRL_SF_AES_KEY_R2_5        SF_CTRL_SF_AES_KEY_R2_5
+#define SF_CTRL_SF_AES_KEY_R2_5_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R2_5_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R2_5_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_5_POS)
+#define SF_CTRL_SF_AES_KEY_R2_5_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_5_POS))
+
+/* 0x418 : sf_aes_key_r2_6 */
+#define SF_CTRL_SF_AES_KEY_R2_6_OFFSET (0x418)
+#define SF_CTRL_SF_AES_KEY_R2_6        SF_CTRL_SF_AES_KEY_R2_6
+#define SF_CTRL_SF_AES_KEY_R2_6_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R2_6_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R2_6_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_6_POS)
+#define SF_CTRL_SF_AES_KEY_R2_6_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_6_POS))
+
+/* 0x41C : sf_aes_key_r2_7 */
+#define SF_CTRL_SF_AES_KEY_R2_7_OFFSET (0x41C)
+#define SF_CTRL_SF_AES_KEY_R2_7        SF_CTRL_SF_AES_KEY_R2_7
+#define SF_CTRL_SF_AES_KEY_R2_7_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R2_7_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R2_7_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_7_POS)
+#define SF_CTRL_SF_AES_KEY_R2_7_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_7_POS))
+
+/* 0x420 : sf_aes_iv_r2_w0 */
+#define SF_CTRL_SF_AES_IV_R2_W0_OFFSET (0x420)
+#define SF_CTRL_SF_AES_IV_R2_W0        SF_CTRL_SF_AES_IV_R2_W0
+#define SF_CTRL_SF_AES_IV_R2_W0_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R2_W0_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R2_W0_MSK    (((1U << SF_CTRL_SF_AES_IV_R2_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W0_POS)
+#define SF_CTRL_SF_AES_IV_R2_W0_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R2_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W0_POS))
+
+/* 0x424 : sf_aes_iv_r2_w1 */
+#define SF_CTRL_SF_AES_IV_R2_W1_OFFSET (0x424)
+#define SF_CTRL_SF_AES_IV_R2_W1        SF_CTRL_SF_AES_IV_R2_W1
+#define SF_CTRL_SF_AES_IV_R2_W1_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R2_W1_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R2_W1_MSK    (((1U << SF_CTRL_SF_AES_IV_R2_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W1_POS)
+#define SF_CTRL_SF_AES_IV_R2_W1_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R2_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W1_POS))
+
+/* 0x428 : sf_aes_iv_r2_w2 */
+#define SF_CTRL_SF_AES_IV_R2_W2_OFFSET (0x428)
+#define SF_CTRL_SF_AES_IV_R2_W2        SF_CTRL_SF_AES_IV_R2_W2
+#define SF_CTRL_SF_AES_IV_R2_W2_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R2_W2_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R2_W2_MSK    (((1U << SF_CTRL_SF_AES_IV_R2_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W2_POS)
+#define SF_CTRL_SF_AES_IV_R2_W2_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R2_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W2_POS))
+
+/* 0x42C : sf_aes_iv_r2_w3 */
+#define SF_CTRL_SF_AES_IV_R2_W3_OFFSET (0x42C)
+#define SF_CTRL_SF_AES_IV_R2_W3        SF_CTRL_SF_AES_IV_R2_W3
+#define SF_CTRL_SF_AES_IV_R2_W3_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R2_W3_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R2_W3_MSK    (((1U << SF_CTRL_SF_AES_IV_R2_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W3_POS)
+#define SF_CTRL_SF_AES_IV_R2_W3_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R2_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W3_POS))
+
+/* 0x430 : sf_aes_r2 */
+#define SF_CTRL_SF_AES_R2_OFFSET         (0x430)
+#define SF_CTRL_SF_AES_R2_END            SF_CTRL_SF_AES_R2_END
+#define SF_CTRL_SF_AES_R2_END_POS        (0U)
+#define SF_CTRL_SF_AES_R2_END_LEN        (14U)
+#define SF_CTRL_SF_AES_R2_END_MSK        (((1U << SF_CTRL_SF_AES_R2_END_LEN) - 1) << SF_CTRL_SF_AES_R2_END_POS)
+#define SF_CTRL_SF_AES_R2_END_UMSK       (~(((1U << SF_CTRL_SF_AES_R2_END_LEN) - 1) << SF_CTRL_SF_AES_R2_END_POS))
+#define SF_CTRL_SF_AES_R2_START          SF_CTRL_SF_AES_R2_START
+#define SF_CTRL_SF_AES_R2_START_POS      (14U)
+#define SF_CTRL_SF_AES_R2_START_LEN      (14U)
+#define SF_CTRL_SF_AES_R2_START_MSK      (((1U << SF_CTRL_SF_AES_R2_START_LEN) - 1) << SF_CTRL_SF_AES_R2_START_POS)
+#define SF_CTRL_SF_AES_R2_START_UMSK     (~(((1U << SF_CTRL_SF_AES_R2_START_LEN) - 1) << SF_CTRL_SF_AES_R2_START_POS))
+#define SF_CTRL_SF_AES_R2_HW_KEY_EN      SF_CTRL_SF_AES_R2_HW_KEY_EN
+#define SF_CTRL_SF_AES_R2_HW_KEY_EN_POS  (29U)
+#define SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN  (1U)
+#define SF_CTRL_SF_AES_R2_HW_KEY_EN_MSK  (((1U << SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_HW_KEY_EN_POS)
+#define SF_CTRL_SF_AES_R2_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_HW_KEY_EN_POS))
+#define SF_CTRL_SF_AES_R2_EN             SF_CTRL_SF_AES_R2_EN
+#define SF_CTRL_SF_AES_R2_EN_POS         (30U)
+#define SF_CTRL_SF_AES_R2_EN_LEN         (1U)
+#define SF_CTRL_SF_AES_R2_EN_MSK         (((1U << SF_CTRL_SF_AES_R2_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_EN_POS)
+#define SF_CTRL_SF_AES_R2_EN_UMSK        (~(((1U << SF_CTRL_SF_AES_R2_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_EN_POS))
+#define SF_CTRL_SF_AES_R2_LOCK           SF_CTRL_SF_AES_R2_LOCK
+#define SF_CTRL_SF_AES_R2_LOCK_POS       (31U)
+#define SF_CTRL_SF_AES_R2_LOCK_LEN       (1U)
+#define SF_CTRL_SF_AES_R2_LOCK_MSK       (((1U << SF_CTRL_SF_AES_R2_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R2_LOCK_POS)
+#define SF_CTRL_SF_AES_R2_LOCK_UMSK      (~(((1U << SF_CTRL_SF_AES_R2_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R2_LOCK_POS))
+
+/* 0x434 : sf_id0_offset */
+#define SF_CTRL_SF_ID0_OFFSET_OFFSET (0x434)
+#define SF_CTRL_SF_ID0_OFFSET        SF_CTRL_SF_ID0_OFFSET
+#define SF_CTRL_SF_ID0_OFFSET_POS    (0U)
+#define SF_CTRL_SF_ID0_OFFSET_LEN    (24U)
+#define SF_CTRL_SF_ID0_OFFSET_MSK    (((1U << SF_CTRL_SF_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_ID0_OFFSET_POS)
+#define SF_CTRL_SF_ID0_OFFSET_UMSK   (~(((1U << SF_CTRL_SF_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_ID0_OFFSET_POS))
+
+/* 0x438 : sf_id1_offset */
+#define SF_CTRL_SF_ID1_OFFSET_OFFSET (0x438)
+#define SF_CTRL_SF_ID1_OFFSET        SF_CTRL_SF_ID1_OFFSET
+#define SF_CTRL_SF_ID1_OFFSET_POS    (0U)
+#define SF_CTRL_SF_ID1_OFFSET_LEN    (24U)
+#define SF_CTRL_SF_ID1_OFFSET_MSK    (((1U << SF_CTRL_SF_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_ID1_OFFSET_POS)
+#define SF_CTRL_SF_ID1_OFFSET_UMSK   (~(((1U << SF_CTRL_SF_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_ID1_OFFSET_POS))
+
+/* 0x43C : sf_bk2_id0_offset */
+#define SF_CTRL_SF_BK2_ID0_OFFSET_OFFSET (0x43C)
+#define SF_CTRL_SF_BK2_ID0_OFFSET        SF_CTRL_SF_BK2_ID0_OFFSET
+#define SF_CTRL_SF_BK2_ID0_OFFSET_POS    (0U)
+#define SF_CTRL_SF_BK2_ID0_OFFSET_LEN    (24U)
+#define SF_CTRL_SF_BK2_ID0_OFFSET_MSK    (((1U << SF_CTRL_SF_BK2_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_BK2_ID0_OFFSET_POS)
+#define SF_CTRL_SF_BK2_ID0_OFFSET_UMSK   (~(((1U << SF_CTRL_SF_BK2_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_BK2_ID0_OFFSET_POS))
+
+/* 0x440 : sf_bk2_id1_offset */
+#define SF_CTRL_SF_BK2_ID1_OFFSET_OFFSET (0x440)
+#define SF_CTRL_SF_BK2_ID1_OFFSET        SF_CTRL_SF_BK2_ID1_OFFSET
+#define SF_CTRL_SF_BK2_ID1_OFFSET_POS    (0U)
+#define SF_CTRL_SF_BK2_ID1_OFFSET_LEN    (24U)
+#define SF_CTRL_SF_BK2_ID1_OFFSET_MSK    (((1U << SF_CTRL_SF_BK2_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_BK2_ID1_OFFSET_POS)
+#define SF_CTRL_SF_BK2_ID1_OFFSET_UMSK   (~(((1U << SF_CTRL_SF_BK2_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_BK2_ID1_OFFSET_POS))
+
+struct sf_ctrl_reg {
+    /* 0x0 : sf_ctrl_0 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_1         : 2; /* [ 1: 0],       rsvd,        0x0 */
+            uint32_t sf_clk_sf_rx_inv_sel : 1; /* [    2],        r/w,        0x1 */
+            uint32_t sf_clk_out_gate_en   : 1; /* [    3],        r/w,        0x1 */
+            uint32_t sf_clk_out_inv_sel   : 1; /* [    4],        r/w,        0x1 */
+            uint32_t sf_clk_sahb_sram_sel : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t sf_if_read_dly_n     : 3; /* [10: 8],        r/w,        0x0 */
+            uint32_t sf_if_read_dly_en    : 1; /* [   11],        r/w,        0x0 */
+            uint32_t reserved_12_15       : 4; /* [15:12],       rsvd,        0x0 */
+            uint32_t sf_if_int            : 1; /* [   16],          r,        0x0 */
+            uint32_t sf_if_int_clr        : 1; /* [   17],        r/w,        0x1 */
+            uint32_t sf_if_int_set        : 1; /* [   18],        r/w,        0x0 */
+            uint32_t sf_aes_dly_mode      : 1; /* [   19],        r/w,        0x0 */
+            uint32_t sf_aes_dout_endian   : 1; /* [   20],        r/w,        0x1 */
+            uint32_t sf_aes_ctr_plus_en   : 1; /* [   21],        r/w,        0x0 */
+            uint32_t sf_aes_key_endian    : 1; /* [   22],        r/w,        0x1 */
+            uint32_t sf_aes_iv_endian     : 1; /* [   23],        r/w,        0x1 */
+            uint32_t sf_id                : 8; /* [31:24],        r/w,       0x1a */
+        } BF;
+        uint32_t WORD;
+    } sf_ctrl_0;
+
+    /* 0x4 : sf_ctrl_1 */
+    union {
+        struct
+        {
+            uint32_t sf_if_sr_pat_mask  : 8; /* [ 7: 0],        r/w,        0x0 */
+            uint32_t sf_if_sr_pat       : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t sf_if_sr_int       : 1; /* [   16],          r,        0x0 */
+            uint32_t sf_if_sr_int_en    : 1; /* [   17],        r/w,        0x0 */
+            uint32_t sf_if_sr_int_set   : 1; /* [   18],        r/w,        0x0 */
+            uint32_t reserved_19        : 1; /* [   19],       rsvd,        0x0 */
+            uint32_t sf_if_0_ack_lat    : 3; /* [22:20],        r/w,        0x6 */
+            uint32_t reserved_23        : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t sf_if_reg_hold     : 1; /* [   24],        r/w,        0x1 */
+            uint32_t sf_if_reg_wp       : 1; /* [   25],        r/w,        0x1 */
+            uint32_t sf_ahb2sif_stopped : 1; /* [   26],          r,        0x0 */
+            uint32_t sf_ahb2sif_stop    : 1; /* [   27],        r/w,        0x0 */
+            uint32_t sf_if_fn_sel       : 1; /* [   28],        r/w,        0x1 */
+            uint32_t sf_if_en           : 1; /* [   29],        r/w,        0x1 */
+            uint32_t sf_ahb2sif_en      : 1; /* [   30],        r/w,        0x1 */
+            uint32_t sf_ahb2sram_en     : 1; /* [   31],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } sf_ctrl_1;
+
+    /* 0x8 : sf_if_sahb_0 */
+    union {
+        struct
+        {
+            uint32_t sf_if_busy          : 1;  /* [    0],          r,        0x0 */
+            uint32_t sf_if_0_trig        : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t sf_if_0_dat_byte    : 10; /* [11: 2],        r/w,        0x0 */
+            uint32_t sf_if_0_dmy_byte    : 5;  /* [16:12],        r/w,        0x0 */
+            uint32_t sf_if_0_adr_byte    : 3;  /* [19:17],        r/w,        0x0 */
+            uint32_t sf_if_0_cmd_byte    : 3;  /* [22:20],        r/w,        0x0 */
+            uint32_t sf_if_0_dat_rw      : 1;  /* [   23],        r/w,        0x0 */
+            uint32_t sf_if_0_dat_en      : 1;  /* [   24],        r/w,        0x0 */
+            uint32_t sf_if_0_dmy_en      : 1;  /* [   25],        r/w,        0x0 */
+            uint32_t sf_if_0_adr_en      : 1;  /* [   26],        r/w,        0x0 */
+            uint32_t sf_if_0_cmd_en      : 1;  /* [   27],        r/w,        0x0 */
+            uint32_t sf_if_0_spi_mode    : 3;  /* [30:28],        r/w,        0x0 */
+            uint32_t sf_if_0_qpi_mode_en : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_sahb_0;
+
+    /* 0xC : sf_if_sahb_1 */
+    union {
+        struct
+        {
+            uint32_t sf_if_0_cmd_buf_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_sahb_1;
+
+    /* 0x10 : sf_if_sahb_2 */
+    union {
+        struct
+        {
+            uint32_t sf_if_0_cmd_buf_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_sahb_2;
+
+    /* 0x14 : sf_if_iahb_0 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_11       : 12; /* [11: 0],       rsvd,        0x0 */
+            uint32_t sf_if_1_dmy_byte    : 5;  /* [16:12],        r/w,        0x0 */
+            uint32_t sf_if_1_adr_byte    : 3;  /* [19:17],        r/w,        0x2 */
+            uint32_t sf_if_1_cmd_byte    : 3;  /* [22:20],        r/w,        0x0 */
+            uint32_t sf_if_1_dat_rw      : 1;  /* [   23],        r/w,        0x0 */
+            uint32_t sf_if_1_dat_en      : 1;  /* [   24],        r/w,        0x1 */
+            uint32_t sf_if_1_dmy_en      : 1;  /* [   25],        r/w,        0x0 */
+            uint32_t sf_if_1_adr_en      : 1;  /* [   26],        r/w,        0x1 */
+            uint32_t sf_if_1_cmd_en      : 1;  /* [   27],        r/w,        0x1 */
+            uint32_t sf_if_1_spi_mode    : 3;  /* [30:28],        r/w,        0x0 */
+            uint32_t sf_if_1_qpi_mode_en : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_0;
+
+    /* 0x18 : sf_if_iahb_1 */
+    union {
+        struct
+        {
+            uint32_t sf_if_1_cmd_buf_0 : 32; /* [31: 0],        r/w,  0x3000000 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_1;
+
+    /* 0x1C : sf_if_iahb_2 */
+    union {
+        struct
+        {
+            uint32_t sf_if_1_cmd_buf_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_2;
+
+    /* 0x20 : sf_if_status_0 */
+    union {
+        struct
+        {
+            uint32_t sf_if_status_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_status_0;
+
+    /* 0x24 : sf_if_status_1 */
+    union {
+        struct
+        {
+            uint32_t sf_if_status_1 : 32; /* [31: 0],          r, 0x20000000 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_status_1;
+
+    /* 0x28 : sf_aes */
+    union {
+        struct
+        {
+            uint32_t sf_aes_en        : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t sf_aes_mode      : 2;  /* [ 2: 1],        r/w,        0x0 */
+            uint32_t sf_aes_pref_trig : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t sf_aes_pref_busy : 1;  /* [    4],          r,        0x0 */
+            uint32_t sf_aes_status    : 27; /* [31: 5],          r,        0x2 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes;
+
+    /* 0x2C : sf_ahb2sif_status */
+    union {
+        struct
+        {
+            uint32_t sf_ahb2sif_status : 32; /* [31: 0],          r, 0x10000003 */
+        } BF;
+        uint32_t WORD;
+    } sf_ahb2sif_status;
+
+    /* 0x30 : sf_if_io_dly_0 */
+    union {
+        struct
+        {
+            uint32_t sf_cs_dly_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t sf_cs2_dly_sel     : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reserved_4_7       : 4;  /* [ 7: 4],       rsvd,        0x0 */
+            uint32_t sf_clk_out_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_25     : 16; /* [25:10],       rsvd,        0x0 */
+            uint32_t sf_dqs_oe_dly_sel  : 2;  /* [27:26],        r/w,        0x0 */
+            uint32_t sf_dqs_di_dly_sel  : 2;  /* [29:28],        r/w,        0x0 */
+            uint32_t sf_dqs_do_dly_sel  : 2;  /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_io_dly_0;
+
+    /* 0x34 : sf_if_io_dly_1 */
+    union {
+        struct
+        {
+            uint32_t sf_io_0_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7       : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf_io_0_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15     : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf_io_0_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31     : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_io_dly_1;
+
+    /* 0x38 : sf_if_io_dly_2 */
+    union {
+        struct
+        {
+            uint32_t sf_io_1_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7       : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf_io_1_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15     : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf_io_1_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31     : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_io_dly_2;
+
+    /* 0x3C : sf_if_io_dly_3 */
+    union {
+        struct
+        {
+            uint32_t sf_io_2_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7       : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf_io_2_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15     : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf_io_2_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31     : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_io_dly_3;
+
+    /* 0x40 : sf_if_io_dly_4 */
+    union {
+        struct
+        {
+            uint32_t sf_io_3_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7       : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf_io_3_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15     : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf_io_3_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31     : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_io_dly_4;
+
+    /* 0x44 : sf_reserved */
+    union {
+        struct
+        {
+            uint32_t sf_reserved : 32; /* [31: 0],        r/w,     0xffff */
+        } BF;
+        uint32_t WORD;
+    } sf_reserved;
+
+    /* 0x48 : sf2_if_io_dly_0 */
+    union {
+        struct
+        {
+            uint32_t sf2_cs_dly_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t sf2_cs2_dly_sel     : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reserved_4_7        : 4;  /* [ 7: 4],       rsvd,        0x0 */
+            uint32_t sf2_clk_out_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_25      : 16; /* [25:10],       rsvd,        0x0 */
+            uint32_t sf2_dqs_oe_dly_sel  : 2;  /* [27:26],        r/w,        0x0 */
+            uint32_t sf2_dqs_di_dly_sel  : 2;  /* [29:28],        r/w,        0x0 */
+            uint32_t sf2_dqs_do_dly_sel  : 2;  /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf2_if_io_dly_0;
+
+    /* 0x4C : sf2_if_io_dly_1 */
+    union {
+        struct
+        {
+            uint32_t sf2_io_0_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf2_io_0_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf2_io_0_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf2_if_io_dly_1;
+
+    /* 0x50 : sf2_if_io_dly_2 */
+    union {
+        struct
+        {
+            uint32_t sf2_io_1_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf2_io_1_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf2_io_1_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf2_if_io_dly_2;
+
+    /* 0x54 : sf2_if_io_dly_3 */
+    union {
+        struct
+        {
+            uint32_t sf2_io_2_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf2_io_2_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf2_io_2_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf2_if_io_dly_3;
+
+    /* 0x58 : sf2_if_io_dly_4 */
+    union {
+        struct
+        {
+            uint32_t sf2_io_3_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf2_io_3_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf2_io_3_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf2_if_io_dly_4;
+
+    /* 0x5C : sf3_if_io_dly_0 */
+    union {
+        struct
+        {
+            uint32_t sf3_cs_dly_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t sf3_cs2_dly_sel     : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reserved_4_7        : 4;  /* [ 7: 4],       rsvd,        0x0 */
+            uint32_t sf3_clk_out_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_25      : 16; /* [25:10],       rsvd,        0x0 */
+            uint32_t sf3_dqs_oe_dly_sel  : 2;  /* [27:26],        r/w,        0x0 */
+            uint32_t sf3_dqs_di_dly_sel  : 2;  /* [29:28],        r/w,        0x0 */
+            uint32_t sf3_dqs_do_dly_sel  : 2;  /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf3_if_io_dly_0;
+
+    /* 0x60 : sf3_if_io_dly_1 */
+    union {
+        struct
+        {
+            uint32_t sf3_io_0_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf3_io_0_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf3_io_0_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf3_if_io_dly_1;
+
+    /* 0x64 : sf3_if_io_dly_2 */
+    union {
+        struct
+        {
+            uint32_t sf3_io_1_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf3_io_1_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf3_io_1_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf3_if_io_dly_2;
+
+    /* 0x68 : sf3_if_io_dly_3 */
+    union {
+        struct
+        {
+            uint32_t sf3_io_2_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf3_io_2_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf3_io_2_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf3_if_io_dly_3;
+
+    /* 0x6C : sf3_if_io_dly_4 */
+    union {
+        struct
+        {
+            uint32_t sf3_io_3_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf3_io_3_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf3_io_3_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf3_if_io_dly_4;
+
+    /* 0x70 : sf_ctrl_2 */
+    union {
+        struct
+        {
+            uint32_t sf_if_pad_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2         : 1;  /* [    2],       rsvd,        0x0 */
+            uint32_t sf_if_pad_sel_lock : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t sf_if_dtr_en       : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t sf_if_dqs_en       : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_27      : 22; /* [27: 6],       rsvd,        0x0 */
+            uint32_t sf_if_bk_swap      : 1;  /* [   28],        r/w,        0x0 */
+            uint32_t sf_if_bk2_mode     : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t sf_if_bk2_en       : 1;  /* [   30],        r/w,        0x0 */
+            uint32_t sf_if_0_bk_sel     : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_ctrl_2;
+
+    /* 0x74 : sf_ctrl_3 */
+    union {
+        struct
+        {
+            uint32_t sf_cmds_wrap_len   : 4;  /* [ 3: 0],        r/w,        0x6 */
+            uint32_t sf_cmds_en         : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t sf_cmds_bt_dly     : 3;  /* [ 7: 5],        r/w,        0x2 */
+            uint32_t sf_cmds_bt_en      : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t sf_cmds_wrap_q_ini : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t sf_cmds_wrap_mode  : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t sf_cmds_wrap_q     : 1;  /* [   11],          r,        0x0 */
+            uint32_t reserved_12_28     : 17; /* [28:12],       rsvd,        0x0 */
+            uint32_t sf_if_1_ack_lat    : 3;  /* [31:29],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } sf_ctrl_3;
+
+    /* 0x78 : sf_if_iahb_3 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_11       : 12; /* [11: 0],       rsvd,        0x0 */
+            uint32_t sf_if_2_dmy_byte    : 5;  /* [16:12],        r/w,        0x0 */
+            uint32_t sf_if_2_adr_byte    : 3;  /* [19:17],        r/w,        0x2 */
+            uint32_t sf_if_2_cmd_byte    : 3;  /* [22:20],        r/w,        0x0 */
+            uint32_t sf_if_2_dat_rw      : 1;  /* [   23],        r/w,        0x1 */
+            uint32_t sf_if_2_dat_en      : 1;  /* [   24],        r/w,        0x1 */
+            uint32_t sf_if_2_dmy_en      : 1;  /* [   25],        r/w,        0x0 */
+            uint32_t sf_if_2_adr_en      : 1;  /* [   26],        r/w,        0x1 */
+            uint32_t sf_if_2_cmd_en      : 1;  /* [   27],        r/w,        0x1 */
+            uint32_t sf_if_2_spi_mode    : 3;  /* [30:28],        r/w,        0x0 */
+            uint32_t sf_if_2_qpi_mode_en : 1;  /* [   31],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_3;
+
+    /* 0x7C : sf_if_iahb_4 */
+    union {
+        struct
+        {
+            uint32_t sf_if_2_cmd_buf_0 : 32; /* [31: 0],        r/w, 0x38000000 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_4;
+
+    /* 0x80 : sf_if_iahb_5 */
+    union {
+        struct
+        {
+            uint32_t sf_if_2_cmd_buf_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_5;
+
+    /* 0x84 : sf_if_iahb_6 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_16       : 17; /* [16: 0],       rsvd,        0x0 */
+            uint32_t sf_if_3_adr_byte    : 3;  /* [19:17],        r/w,        0x0 */
+            uint32_t sf_if_3_cmd_byte    : 3;  /* [22:20],        r/w,        0x0 */
+            uint32_t reserved_23_25      : 3;  /* [25:23],       rsvd,        0x0 */
+            uint32_t sf_if_3_adr_en      : 1;  /* [   26],        r/w,        0x0 */
+            uint32_t sf_if_3_cmd_en      : 1;  /* [   27],        r/w,        0x1 */
+            uint32_t sf_if_3_spi_mode    : 3;  /* [30:28],        r/w,        0x0 */
+            uint32_t sf_if_3_qpi_mode_en : 1;  /* [   31],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_6;
+
+    /* 0x88 : sf_if_iahb_7 */
+    union {
+        struct
+        {
+            uint32_t sf_if_3_cmd_buf_0 : 32; /* [31: 0],        r/w, 0xc0000000L */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_7;
+
+    /* 0x8C : sf_if_iahb_8 */
+    union {
+        struct
+        {
+            uint32_t sf_if_3_cmd_buf_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_8;
+
+    /* 0x90 : sf_if_iahb_9 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_11       : 12; /* [11: 0],       rsvd,        0x0 */
+            uint32_t sf_if_4_dmy_byte    : 5;  /* [16:12],        r/w,        0x2 */
+            uint32_t sf_if_4_adr_byte    : 3;  /* [19:17],        r/w,        0x2 */
+            uint32_t sf_if_4_cmd_byte    : 3;  /* [22:20],        r/w,        0x0 */
+            uint32_t sf_if_4_dat_rw      : 1;  /* [   23],        r/w,        0x0 */
+            uint32_t sf_if_4_dat_en      : 1;  /* [   24],        r/w,        0x1 */
+            uint32_t sf_if_4_dmy_en      : 1;  /* [   25],        r/w,        0x1 */
+            uint32_t sf_if_4_adr_en      : 1;  /* [   26],        r/w,        0x1 */
+            uint32_t sf_if_4_cmd_en      : 1;  /* [   27],        r/w,        0x1 */
+            uint32_t sf_if_4_spi_mode    : 3;  /* [30:28],        r/w,        0x0 */
+            uint32_t sf_if_4_qpi_mode_en : 1;  /* [   31],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_9;
+
+    /* 0x94 : sf_if_iahb_10 */
+    union {
+        struct
+        {
+            uint32_t sf_if_4_cmd_buf_0 : 32; /* [31: 0],        r/w, 0xeb000000L */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_10;
+
+    /* 0x98 : sf_if_iahb_11 */
+    union {
+        struct
+        {
+            uint32_t sf_if_4_cmd_buf_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_11;
+
+    /* 0x9C : sf_if_iahb_12 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_1          : 2;  /* [ 1: 0],       rsvd,        0x0 */
+            uint32_t sf2_clk_sf_rx_inv_sel : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t sf2_clk_sf_rx_inv_src : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t sf2_clk_out_inv_sel   : 1;  /* [    4],        r/w,        0x1 */
+            uint32_t sf3_clk_out_inv_sel   : 1;  /* [    5],        r/w,        0x1 */
+            uint32_t reserved_6_7          : 2;  /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t sf2_if_read_dly_n     : 3;  /* [10: 8],        r/w,        0x0 */
+            uint32_t sf2_if_read_dly_en    : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t sf2_if_read_dly_src   : 1;  /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13_31        : 19; /* [31:13],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_12;
+
+    /* 0xa0  reserved */
+    uint8_t RESERVED0xa0[96];
+
+    /* 0x100 : sf_ctrl_prot_en_rd */
+    union {
+        struct
+        {
+            uint32_t sf_ctrl_prot_en_rd   : 1;  /* [    0],          r,        0x1 */
+            uint32_t sf_ctrl_id0_en_rd    : 1;  /* [    1],          r,        0x1 */
+            uint32_t sf_ctrl_id1_en_rd    : 1;  /* [    2],          r,        0x1 */
+            uint32_t reserved_3_29        : 27; /* [29: 3],       rsvd,        0x0 */
+            uint32_t sf_if_0_trig_wr_lock : 1;  /* [   30],          r,        0x0 */
+            uint32_t sf_dbg_dis           : 1;  /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_ctrl_prot_en_rd;
+
+    /* 0x104 : sf_ctrl_prot_en */
+    union {
+        struct
+        {
+            uint32_t sf_ctrl_prot_en : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t sf_ctrl_id0_en  : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t sf_ctrl_id1_en  : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t reserved_3_31   : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_ctrl_prot_en;
+
+    /* 0x108  reserved */
+    uint8_t RESERVED0x108[248];
+
+    /* 0x200 : sf_aes_key_r0_0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r0_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r0_0;
+
+    /* 0x204 : sf_aes_key_r0_1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r0_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r0_1;
+
+    /* 0x208 : sf_aes_key_r0_2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r0_2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r0_2;
+
+    /* 0x20C : sf_aes_key_r0_3 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r0_3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r0_3;
+
+    /* 0x210 : sf_aes_key_r0_4 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r0_4 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r0_4;
+
+    /* 0x214 : sf_aes_key_r0_5 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r0_5 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r0_5;
+
+    /* 0x218 : sf_aes_key_r0_6 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r0_6 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r0_6;
+
+    /* 0x21C : sf_aes_key_r0_7 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r0_7 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r0_7;
+
+    /* 0x220 : sf_aes_iv_r0_w0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r0_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r0_w0;
+
+    /* 0x224 : sf_aes_iv_r0_w1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r0_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r0_w1;
+
+    /* 0x228 : sf_aes_iv_r0_w2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r0_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r0_w2;
+
+    /* 0x22C : sf_aes_iv_r0_w3 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r0_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r0_w3;
+
+    /* 0x230 : sf_aes_cfg_r0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_region_r0_end       : 14; /* [13: 0],        r/w,     0x3fff */
+            uint32_t sf_aes_region_r0_start     : 14; /* [27:14],        r/w,        0x0 */
+            uint32_t reserved_28                : 1;  /* [   28],       rsvd,        0x0 */
+            uint32_t sf_aes_region_r0_hw_key_en : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t sf_aes_region_r0_en        : 1;  /* [   30],        r/w,        0x0 */
+            uint32_t sf_aes_region_r0_lock      : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_cfg_r0;
+
+    /* 0x234  reserved */
+    uint8_t RESERVED0x234[204];
+
+    /* 0x300 : sf_aes_key_r1_0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r1_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r1_0;
+
+    /* 0x304 : sf_aes_key_r1_1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r1_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r1_1;
+
+    /* 0x308 : sf_aes_key_r1_2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r1_2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r1_2;
+
+    /* 0x30C : sf_aes_key_r1_3 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r1_3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r1_3;
+
+    /* 0x310 : sf_aes_key_r1_4 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r1_4 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r1_4;
+
+    /* 0x314 : sf_aes_key_r1_5 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r1_5 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r1_5;
+
+    /* 0x318 : sf_aes_key_r1_6 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r1_6 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r1_6;
+
+    /* 0x31C : sf_aes_key_r1_7 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r1_7 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r1_7;
+
+    /* 0x320 : sf_aes_iv_r1_w0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r1_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r1_w0;
+
+    /* 0x324 : sf_aes_iv_r1_w1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r1_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r1_w1;
+
+    /* 0x328 : sf_aes_iv_r1_w2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r1_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r1_w2;
+
+    /* 0x32C : sf_aes_iv_r1_w3 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r1_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r1_w3;
+
+    /* 0x330 : sf_aes_r1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_r1_end       : 14; /* [13: 0],        r/w,     0x3fff */
+            uint32_t sf_aes_r1_start     : 14; /* [27:14],        r/w,        0x0 */
+            uint32_t reserved_28         : 1;  /* [   28],       rsvd,        0x0 */
+            uint32_t sf_aes_r1_hw_key_en : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t sf_aes_r1_en        : 1;  /* [   30],        r/w,        0x0 */
+            uint32_t sf_aes_r1_lock      : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_r1;
+
+    /* 0x334  reserved */
+    uint8_t RESERVED0x334[204];
+
+    /* 0x400 : sf_aes_key_r2_0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r2_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r2_0;
+
+    /* 0x404 : sf_aes_key_r2_1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r2_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r2_1;
+
+    /* 0x408 : sf_aes_key_r2_2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r2_2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r2_2;
+
+    /* 0x40C : sf_aes_key_r2_3 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r2_3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r2_3;
+
+    /* 0x410 : sf_aes_key_r2_4 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r2_4 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r2_4;
+
+    /* 0x414 : sf_aes_key_r2_5 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r2_5 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r2_5;
+
+    /* 0x418 : sf_aes_key_r2_6 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r2_6 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r2_6;
+
+    /* 0x41C : sf_aes_key_r2_7 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r2_7 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r2_7;
+
+    /* 0x420 : sf_aes_iv_r2_w0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r2_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r2_w0;
+
+    /* 0x424 : sf_aes_iv_r2_w1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r2_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r2_w1;
+
+    /* 0x428 : sf_aes_iv_r2_w2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r2_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r2_w2;
+
+    /* 0x42C : sf_aes_iv_r2_w3 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r2_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r2_w3;
+
+    /* 0x430 : sf_aes_r2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_r2_end       : 14; /* [13: 0],        r/w,     0x3fff */
+            uint32_t sf_aes_r2_start     : 14; /* [27:14],        r/w,        0x0 */
+            uint32_t reserved_28         : 1;  /* [   28],       rsvd,        0x0 */
+            uint32_t sf_aes_r2_hw_key_en : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t sf_aes_r2_en        : 1;  /* [   30],        r/w,        0x0 */
+            uint32_t sf_aes_r2_lock      : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_r2;
+
+    /* 0x434 : sf_id0_offset */
+    union {
+        struct
+        {
+            uint32_t sf_id0_offset  : 24; /* [23: 0],        r/w,        0x0 */
+            uint32_t reserved_24_31 : 8;  /* [31:24],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_id0_offset;
+
+    /* 0x438 : sf_id1_offset */
+    union {
+        struct
+        {
+            uint32_t sf_id1_offset  : 24; /* [23: 0],        r/w,        0x0 */
+            uint32_t reserved_24_31 : 8;  /* [31:24],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_id1_offset;
+
+    /* 0x43C : sf_bk2_id0_offset */
+    union {
+        struct
+        {
+            uint32_t sf_bk2_id0_offset : 24; /* [23: 0],        r/w,        0x0 */
+            uint32_t reserved_24_31    : 8;  /* [31:24],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_bk2_id0_offset;
+
+    /* 0x440 : sf_bk2_id1_offset */
+    union {
+        struct
+        {
+            uint32_t sf_bk2_id1_offset : 24; /* [23: 0],        r/w,        0x0 */
+            uint32_t reserved_24_31    : 8;  /* [31:24],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_bk2_id1_offset;
+};
+
+typedef volatile struct sf_ctrl_reg sf_ctrl_reg_t;
+
+/*Following is reg patch*/
+
+/* 0x0 : sf_aes_key_0 */
+#define SF_CTRL_SF_AES_KEY_0_OFFSET (0x0)
+#define SF_CTRL_SF_AES_KEY_0        SF_CTRL_SF_AES_KEY_0
+#define SF_CTRL_SF_AES_KEY_0_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_0_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_0_MSK    (((1U << SF_CTRL_SF_AES_KEY_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_0_POS)
+#define SF_CTRL_SF_AES_KEY_0_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_0_POS))
+
+/* 0x4 : sf_aes_key_1 */
+#define SF_CTRL_SF_AES_KEY_1_OFFSET (0x4)
+#define SF_CTRL_SF_AES_KEY_1        SF_CTRL_SF_AES_KEY_1
+#define SF_CTRL_SF_AES_KEY_1_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_1_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_1_MSK    (((1U << SF_CTRL_SF_AES_KEY_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_1_POS)
+#define SF_CTRL_SF_AES_KEY_1_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_1_POS))
+
+/* 0x8 : sf_aes_key_2 */
+#define SF_CTRL_SF_AES_KEY_2_OFFSET (0x8)
+#define SF_CTRL_SF_AES_KEY_2        SF_CTRL_SF_AES_KEY_2
+#define SF_CTRL_SF_AES_KEY_2_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_2_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_2_MSK    (((1U << SF_CTRL_SF_AES_KEY_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_2_POS)
+#define SF_CTRL_SF_AES_KEY_2_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_2_POS))
+
+/* 0xc : sf_aes_key_3 */
+#define SF_CTRL_SF_AES_KEY_3_OFFSET (0xc)
+#define SF_CTRL_SF_AES_KEY_3        SF_CTRL_SF_AES_KEY_3
+#define SF_CTRL_SF_AES_KEY_3_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_3_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_3_MSK    (((1U << SF_CTRL_SF_AES_KEY_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_3_POS)
+#define SF_CTRL_SF_AES_KEY_3_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_3_POS))
+
+/* 0x10 : sf_aes_key_4 */
+#define SF_CTRL_SF_AES_KEY_4_OFFSET (0x10)
+#define SF_CTRL_SF_AES_KEY_4        SF_CTRL_SF_AES_KEY_4
+#define SF_CTRL_SF_AES_KEY_4_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_4_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_4_MSK    (((1U << SF_CTRL_SF_AES_KEY_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_4_POS)
+#define SF_CTRL_SF_AES_KEY_4_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_4_POS))
+
+/* 0x14 : sf_aes_key_5 */
+#define SF_CTRL_SF_AES_KEY_5_OFFSET (0x14)
+#define SF_CTRL_SF_AES_KEY_5        SF_CTRL_SF_AES_KEY_5
+#define SF_CTRL_SF_AES_KEY_5_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_5_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_5_MSK    (((1U << SF_CTRL_SF_AES_KEY_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_5_POS)
+#define SF_CTRL_SF_AES_KEY_5_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_5_POS))
+
+/* 0x18 : sf_aes_key_6 */
+#define SF_CTRL_SF_AES_KEY_6_OFFSET (0x18)
+#define SF_CTRL_SF_AES_KEY_6        SF_CTRL_SF_AES_KEY_6
+#define SF_CTRL_SF_AES_KEY_6_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_6_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_6_MSK    (((1U << SF_CTRL_SF_AES_KEY_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_6_POS)
+#define SF_CTRL_SF_AES_KEY_6_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_6_POS))
+
+/* 0x1c : sf_aes_key_7 */
+#define SF_CTRL_SF_AES_KEY_7_OFFSET (0x1c)
+#define SF_CTRL_SF_AES_KEY_7        SF_CTRL_SF_AES_KEY_7
+#define SF_CTRL_SF_AES_KEY_7_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_7_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_7_MSK    (((1U << SF_CTRL_SF_AES_KEY_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_7_POS)
+#define SF_CTRL_SF_AES_KEY_7_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_7_POS))
+
+/* 0x20 : sf_aes_iv_w0 */
+#define SF_CTRL_SF_AES_IV_W0_OFFSET (0x20)
+#define SF_CTRL_SF_AES_IV_W0        SF_CTRL_SF_AES_IV_W0
+#define SF_CTRL_SF_AES_IV_W0_POS    (0U)
+#define SF_CTRL_SF_AES_IV_W0_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_W0_MSK    (((1U << SF_CTRL_SF_AES_IV_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_W0_POS)
+#define SF_CTRL_SF_AES_IV_W0_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_W0_POS))
+
+/* 0x24 : sf_aes_iv_w1 */
+#define SF_CTRL_SF_AES_IV_W1_OFFSET (0x24)
+#define SF_CTRL_SF_AES_IV_W1        SF_CTRL_SF_AES_IV_W1
+#define SF_CTRL_SF_AES_IV_W1_POS    (0U)
+#define SF_CTRL_SF_AES_IV_W1_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_W1_MSK    (((1U << SF_CTRL_SF_AES_IV_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_W1_POS)
+#define SF_CTRL_SF_AES_IV_W1_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_W1_POS))
+
+/* 0x28 : sf_aes_iv_w2 */
+#define SF_CTRL_SF_AES_IV_W2_OFFSET (0x28)
+#define SF_CTRL_SF_AES_IV_W2        SF_CTRL_SF_AES_IV_W2
+#define SF_CTRL_SF_AES_IV_W2_POS    (0U)
+#define SF_CTRL_SF_AES_IV_W2_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_W2_MSK    (((1U << SF_CTRL_SF_AES_IV_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_W2_POS)
+#define SF_CTRL_SF_AES_IV_W2_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_W2_POS))
+
+/* 0x2c : sf_aes_iv_w3 */
+#define SF_CTRL_SF_AES_IV_W3_OFFSET (0x2c)
+#define SF_CTRL_SF_AES_IV_W3        SF_CTRL_SF_AES_IV_W3
+#define SF_CTRL_SF_AES_IV_W3_POS    (0U)
+#define SF_CTRL_SF_AES_IV_W3_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_W3_MSK    (((1U << SF_CTRL_SF_AES_IV_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_W3_POS)
+#define SF_CTRL_SF_AES_IV_W3_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_W3_POS))
+
+/* 0x30 : sf_aes_cfg */
+#define SF_CTRL_SF_AES_CFG_OFFSET            (0x30)
+#define SF_CTRL_SF_AES_REGION_END            SF_CTRL_SF_AES_REGION_END
+#define SF_CTRL_SF_AES_REGION_END_POS        (0U)
+#define SF_CTRL_SF_AES_REGION_END_LEN        (14U)
+#define SF_CTRL_SF_AES_REGION_END_MSK        (((1U << SF_CTRL_SF_AES_REGION_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_END_POS)
+#define SF_CTRL_SF_AES_REGION_END_UMSK       (~(((1U << SF_CTRL_SF_AES_REGION_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_END_POS))
+#define SF_CTRL_SF_AES_REGION_START          SF_CTRL_SF_AES_REGION_START
+#define SF_CTRL_SF_AES_REGION_START_POS      (14U)
+#define SF_CTRL_SF_AES_REGION_START_LEN      (14U)
+#define SF_CTRL_SF_AES_REGION_START_MSK      (((1U << SF_CTRL_SF_AES_REGION_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_START_POS)
+#define SF_CTRL_SF_AES_REGION_START_UMSK     (~(((1U << SF_CTRL_SF_AES_REGION_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_START_POS))
+#define SF_CTRL_SF_AES_REGION_HW_KEY_EN      SF_CTRL_SF_AES_REGION_HW_KEY_EN
+#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS  (29U)
+#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN  (1U)
+#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_MSK  (((1U << SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS)
+#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS))
+#define SF_CTRL_SF_AES_REGION_EN             SF_CTRL_SF_AES_REGION_EN
+#define SF_CTRL_SF_AES_REGION_EN_POS         (30U)
+#define SF_CTRL_SF_AES_REGION_EN_LEN         (1U)
+#define SF_CTRL_SF_AES_REGION_EN_MSK         (((1U << SF_CTRL_SF_AES_REGION_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_EN_POS)
+#define SF_CTRL_SF_AES_REGION_EN_UMSK        (~(((1U << SF_CTRL_SF_AES_REGION_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_EN_POS))
+#define SF_CTRL_SF_AES_REGION_LOCK           SF_CTRL_SF_AES_REGION_LOCK
+#define SF_CTRL_SF_AES_REGION_LOCK_POS       (31U)
+#define SF_CTRL_SF_AES_REGION_LOCK_LEN       (1U)
+#define SF_CTRL_SF_AES_REGION_LOCK_MSK       (((1U << SF_CTRL_SF_AES_REGION_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_LOCK_POS)
+#define SF_CTRL_SF_AES_REGION_LOCK_UMSK      (~(((1U << SF_CTRL_SF_AES_REGION_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_LOCK_POS))
+
+struct sf_ctrl_aes_region_reg {
+    /* 0x0 : sf_aes_key_0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_0;
+
+    /* 0x4 : sf_aes_key_1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_1;
+
+    /* 0x8 : sf_aes_key_2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_2;
+
+    /* 0xc : sf_aes_key_3 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_3;
+
+    /* 0x10 : sf_aes_key_4 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_4 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_4;
+
+    /* 0x14 : sf_aes_key_5 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_5 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_5;
+
+    /* 0x18 : sf_aes_key_6 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_6 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_6;
+
+    /* 0x1c : sf_aes_key_7 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_7 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_7;
+
+    /* 0x20 : sf_aes_iv_w0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_w0;
+
+    /* 0x24 : sf_aes_iv_w1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_w1;
+
+    /* 0x28 : sf_aes_iv_w2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_w2;
+
+    /* 0x2c : sf_aes_iv_w3 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_w3;
+
+    /* 0x30 : sf_aes_cfg */
+    union {
+        struct
+        {
+            uint32_t sf_aes_region_end       : 14; /* [13: 0],        r/w,     0x3fff */
+            uint32_t sf_aes_region_start     : 14; /* [27:14],        r/w,        0x0 */
+            uint32_t reserved_28             : 1;  /* [   28],       rsvd,        0x0 */
+            uint32_t sf_aes_region_hw_key_en : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t sf_aes_region_en        : 1;  /* [   30],        r/w,        0x0 */
+            uint32_t sf_aes_region_lock      : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_cfg;
+};
+
+typedef volatile struct sf_ctrl_aes_region_reg sf_ctrl_aes_region_reg_t;
+
+#define SF_CTRL_AES_REGION_OFFSET 0x200
+
+#endif /* __SF_CTRL_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/soc702_reg.svd b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/soc702_reg.svd
new file mode 100644
index 00000000..939bb8ed
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/soc702_reg.svd
@@ -0,0 +1,22548 @@
+
+	
+		bouffalolab
+		bouffalolab
+		702
+		WiFi BT
+		high-performance, 32-bit RV32IMAFC core
+		8
+		32
+		32
+		0x00000000
+		0xFFFFFFFF
+		
+			702
+			little
+		
+		
+			
+				glb
+				glb.
+				0x40000000
+				glb
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						clk_cfg0
+						clk_cfg0.
+						0x0
+						
+							
+								glb_id
+								28
+								31
+							
+							
+								chip_rdy
+								27
+								27
+							
+							
+								fclk_sw_state
+								24
+								26
+							
+							
+								reg_bclk_div
+								16
+								23
+							
+							
+								reg_hclk_div
+								8
+								15
+							
+							
+								hbn_root_clk_sel
+								6
+								7
+							
+							
+								reg_pll_sel
+								4
+								5
+							
+							
+								reg_bclk_en
+								3
+								3
+							
+							
+								reg_hclk_en
+								2
+								2
+							
+							
+								reg_fclk_en
+								1
+								1
+							
+							
+								reg_pll_en
+								0
+								0
+							
+						
+					
+					
+						clk_cfg1
+						clk_cfg1.
+						0x4
+						
+							
+								reg_cam_ref_clk_div
+								30
+								31
+							
+							
+								reg_cam_ref_clk_src_sel
+								29
+								29
+							
+							
+								reg_cam_ref_clk_en
+								28
+								28
+							
+							
+								m154_zbEn
+								25
+								25
+							
+							
+								ble_en
+								24
+								24
+							
+							
+								ble_clk_sel
+								16
+								21
+							
+							
+								reg_i2s_0_ref_clk_oe
+								14
+								14
+							
+							
+								reg_i2s0_clk_en
+								13
+								13
+							
+							
+								reg_i2s_clk_sel
+								12
+								12
+							
+							
+								dll_48m_div_en
+								9
+								9
+							
+							
+								usb_clk_en
+								8
+								8
+							
+							
+								qdec_clk_sel
+								7
+								7
+							
+							
+								qdec_clk_div
+								0
+								4
+							
+						
+					
+					
+						clk_cfg2
+						clk_cfg2.
+						0x8
+						
+							
+								dma_clk_en
+								24
+								31
+							
+							
+								ir_clk_en
+								23
+								23
+							
+							
+								ir_clk_div
+								16
+								21
+							
+							
+								sf_clk_sel2
+								14
+								15
+							
+							
+								sf_clk_sel
+								12
+								13
+							
+							
+								sf_clk_en
+								11
+								11
+							
+							
+								sf_clk_div
+								8
+								10
+							
+							
+								hbn_uart_clk_sel
+								7
+								7
+							
+							
+								uart_clk_en
+								4
+								4
+							
+							
+								uart_clk_div
+								0
+								2
+							
+						
+					
+					
+						clk_cfg3
+						clk_cfg3.
+						0xC
+						
+							
+								chip_clk_out_1_sel
+								30
+								31
+							
+							
+								chip_clk_out_0_sel
+								28
+								29
+							
+							
+								i2c_clk_en
+								24
+								24
+							
+							
+								i2c_clk_div
+								16
+								23
+							
+							
+								cfg_inv_eth_rx_clk
+								10
+								10
+							
+							
+								cfg_inv_rf_test_clk_o
+								9
+								9
+							
+							
+								spi_clk_en
+								8
+								8
+							
+							
+								cfg_inv_eth_tx_clk
+								7
+								7
+							
+							
+								cfg_inv_eth_ref_clk_o
+								6
+								6
+							
+							
+								cfg_sel_eth_ref_clk_o
+								5
+								5
+							
+							
+								spi_clk_div
+								0
+								4
+							
+						
+					
+					
+						swrst_cfg0
+						swrst_cfg0.
+						0x10
+						
+							
+								swrst_s30
+								8
+								8
+							
+							
+								swrst_s20
+								4
+								4
+							
+							
+								swrst_s01
+								1
+								1
+							
+							
+								swrst_s00
+								0
+								0
+							
+						
+					
+					
+						swrst_cfg1
+						swrst_cfg1.
+						0x14
+						
+							
+								swrst_s1ae
+								30
+								30
+							
+							
+								swrst_s1ad
+								29
+								29
+							
+							
+								swrst_s1ac
+								28
+								28
+							
+							
+								swrst_s1ab
+								27
+								27
+							
+							
+								swrst_s1aa
+								26
+								26
+							
+							
+								swrst_s1a9
+								25
+								25
+							
+							
+								swrst_s1a8
+								24
+								24
+							
+							
+								swrst_s1a7
+								23
+								23
+							
+							
+								swrst_s1a6
+								22
+								22
+							
+							
+								swrst_s1a5
+								21
+								21
+							
+							
+								swrst_s1a4
+								20
+								20
+							
+							
+								swrst_s1a3
+								19
+								19
+							
+							
+								swrst_s1a2
+								18
+								18
+							
+							
+								swrst_s1a1
+								17
+								17
+							
+							
+								swrst_s1a0
+								16
+								16
+							
+							
+								swrst_s1f
+								15
+								15
+							
+							
+								swrst_s1e
+								14
+								14
+							
+							
+								swrst_s1d
+								13
+								13
+							
+							
+								swrst_s1c
+								12
+								12
+							
+							
+								swrst_s1b
+								11
+								11
+							
+							
+								swrst_s1a
+								10
+								10
+							
+							
+								swrst_s19
+								9
+								9
+							
+							
+								swrst_s18
+								8
+								8
+							
+							
+								swrst_s17
+								7
+								7
+							
+							
+								swrst_s16
+								6
+								6
+							
+							
+								swrst_s15
+								5
+								5
+							
+							
+								swrst_s14
+								4
+								4
+							
+							
+								swrst_s13
+								3
+								3
+							
+							
+								swrst_s12
+								2
+								2
+							
+							
+								swrst_s11
+								1
+								1
+							
+							
+								swrst_s10
+								0
+								0
+							
+						
+					
+					
+						swrst_cfg2
+						swrst_cfg2.
+						0x18
+						
+							
+								pka_clk_sel
+								24
+								24
+							
+							
+								reg_ctrl_reset_dummy
+								4
+								7
+							
+							
+								reg_ctrl_sys_reset
+								2
+								2
+							
+							
+								reg_ctrl_cpu_reset
+								1
+								1
+							
+							
+								reg_ctrl_pwron_rst
+								0
+								0
+							
+						
+					
+					
+						swrst_cfg3
+						swrst_cfg3.
+						0x1C
+						
+					
+					
+						cgen_cfg0
+						cgen_cfg0.
+						0x20
+						
+							
+								cgen_m
+								0
+								7
+							
+						
+					
+					
+						cgen_cfg1
+						cgen_cfg1.
+						0x24
+						
+							
+								cgen_s1a
+								16
+								31
+							
+							
+								cgen_s1
+								0
+								15
+							
+						
+					
+					
+						cgen_cfg2
+						cgen_cfg2.
+						0x28
+						
+							
+								cgen_s3
+								4
+								4
+							
+							
+								cgen_s2
+								0
+								0
+							
+						
+					
+					
+						cgen_cfg3
+						cgen_cfg3.
+						0x2C
+						
+					
+					
+						MBIST_CTL
+						MBIST_CTL.
+						0x30
+						
+							
+								reg_mbist_rst_n
+								31
+								31
+							
+							
+								em_ram_mbist_mode
+								5
+								5
+							
+							
+								ocram_mbist_mode
+								4
+								4
+							
+							
+								tag_mbist_mode
+								3
+								3
+							
+							
+								hsram_cache_mbist_mode
+								2
+								2
+							
+							
+								hsram_mem_mbist_mode
+								1
+								1
+							
+							
+								irom_mbist_mode
+								0
+								0
+							
+						
+					
+					
+						MBIST_STAT
+						MBIST_STAT.
+						0x34
+						
+							
+								em_ram_mbist_fail
+								21
+								21
+							
+							
+								ocram_mbist_fail
+								20
+								20
+							
+							
+								tag_mbist_fail
+								19
+								19
+							
+							
+								hsram_cache_mbist_fail
+								18
+								18
+							
+							
+								hsram_mem_mbist_fail
+								17
+								17
+							
+							
+								irom_mbist_fail
+								16
+								16
+							
+							
+								em_ram_mbist_done
+								5
+								5
+							
+							
+								ocram_mbist_done
+								4
+								4
+							
+							
+								tag_mbist_done
+								3
+								3
+							
+							
+								hsram_cache_mbist_done
+								2
+								2
+							
+							
+								hsram_mem_mbist_done
+								1
+								1
+							
+							
+								irom_mbist_done
+								0
+								0
+							
+						
+					
+					
+						bmx_cfg1
+						bmx_cfg1.
+						0x50
+						
+							
+								hbn_apb_cfg
+								24
+								31
+							
+							
+								pds_apb_cfg
+								16
+								23
+							
+							
+								hsel_option
+								12
+								15
+							
+							
+								bmx_gating_dis
+								10
+								10
+							
+							
+								bmx_busy_option_dis
+								9
+								9
+							
+							
+								bmx_err_en
+								8
+								8
+							
+							
+								bmx_arb_mode
+								4
+								5
+							
+							
+								bmx_timeout_en
+								0
+								3
+							
+						
+					
+					
+						bmx_cfg2
+						bmx_cfg2.
+						0x54
+						
+							
+								bmx_dbg_sel
+								28
+								31
+							
+							
+								reg_w_thre_l1c
+								10
+								11
+							
+							
+								reg_w_thre_bmx
+								8
+								9
+							
+							
+								bmx_err_tz
+								5
+								5
+							
+							
+								bmx_err_dec
+								4
+								4
+							
+							
+								bmx_err_addr_dis
+								0
+								0
+							
+						
+					
+					
+						bmx_err_addr
+						bmx_err_addr.
+						0x58
+						
+							
+								bmx_err_addr
+								0
+								31
+							
+						
+					
+					
+						bmx_dbg_out
+						bmx_dbg_out.
+						0x5C
+						
+							
+								bmx_dbg_out
+								0
+								31
+							
+						
+					
+					
+						rsv0
+						rsv0.
+						0x60
+						
+							
+								rsvd_31_0
+								0
+								31
+							
+						
+					
+					
+						rsv1
+						rsv1.
+						0x64
+						
+							
+								rsvd_31_0
+								0
+								31
+							
+						
+					
+					
+						rsv2
+						rsv2.
+						0x68
+						
+							
+								rsvd_31_0
+								0
+								31
+							
+						
+					
+					
+						rsv3
+						rsv3.
+						0x6C
+						
+							
+								rsvd_31_0
+								0
+								31
+							
+						
+					
+					
+						sram_ret
+						sram_ret.
+						0x70
+						
+							
+								reg_sram_ret
+								0
+								31
+							
+						
+					
+					
+						sram_slp
+						sram_slp.
+						0x74
+						
+							
+								reg_sram_slp
+								0
+								31
+							
+						
+					
+					
+						sram_parm
+						sram_parm.
+						0x78
+						
+							
+								reg_sram_parm
+								0
+								31
+							
+						
+					
+					
+						seam_misc
+						seam_misc.
+						0x7C
+						
+							
+								em_sel
+								0
+								3
+							
+						
+					
+					
+						glb_parm
+						glb_parm.
+						0x80
+						
+							
+								pin_sel_emac_cam
+								31
+								31
+							
+							
+								reg_ext_rst_smt
+								30
+								30
+							
+							
+								reg_kys_drv_val
+								29
+								29
+							
+							
+								uart_swap_set
+								24
+								27
+							
+							
+								p6_jtag_use_io_0_2_7
+								23
+								23
+							
+							
+								p5_dac_test_with_jtag
+								21
+								21
+							
+							
+								p4_adc_test_with_jtag
+								20
+								20
+							
+							
+								p3_cci_use_io_0_2_7
+								19
+								19
+							
+							
+								p2_dac_test_with_cci
+								18
+								18
+							
+							
+								p1_adc_test_with_cci
+								17
+								17
+							
+							
+								reg_cci_use_jtag_pin
+								16
+								16
+							
+							
+								reg_spi_0_swap
+								13
+								13
+							
+							
+								reg_spi_0_master_mode
+								12
+								12
+							
+							
+								cfg_flash_scenario
+								10
+								11
+							
+							
+								cfg_sflash2_swap_cs_io2
+								9
+								9
+							
+							
+								cfg_sflash2_swap_io0_io3
+								8
+								8
+							
+							
+								jtag_swap_set
+								0
+								7
+							
+						
+					
+					
+						PDM_CLK_CTRL
+						PDM_CLK_CTRL.
+						0x84
+						
+							
+								reg_pdm0_clk_en
+								7
+								7
+							
+							
+								reg_pdm0_clk_div
+								0
+								5
+							
+						
+					
+					
+						GPIO_USE_PSRAM__IO
+						GPIO_USE_PSRAM__IO.
+						0x88
+						
+							
+								cfg_gpio_use_psram_io
+								0
+								5
+							
+						
+					
+					
+						CPU_CLK_CFG
+						CPU_CLK_CFG.
+						0x90
+						
+							
+								debug_ndreset_gate
+								20
+								20
+							
+							
+								cpu_rtc_sel
+								19
+								19
+							
+							
+								cpu_rtc_en
+								18
+								18
+							
+							
+								cpu_rtc_div
+								0
+								16
+							
+						
+					
+					
+						GPADC_32M_SRC_CTRL
+						GPADC_32M_SRC_CTRL.
+						0xA4
+						
+							
+								gpadc_32m_div_en
+								8
+								8
+							
+							
+								gpadc_32m_clk_sel
+								7
+								7
+							
+							
+								gpadc_32m_clk_div
+								0
+								5
+							
+						
+					
+					
+						DIG32K_WAKEUP_CTRL
+						DIG32K_WAKEUP_CTRL.
+						0xA8
+						
+							
+								reg_en_platform_wakeup
+								31
+								31
+							
+							
+								dig_clk_src_sel
+								28
+								29
+							
+							
+								dig_512k_comp
+								25
+								25
+							
+							
+								dig_512k_en
+								24
+								24
+							
+							
+								dig_512k_div
+								16
+								22
+							
+							
+								dig_32k_comp
+								13
+								13
+							
+							
+								dig_32k_en
+								12
+								12
+							
+							
+								dig_32k_div
+								0
+								10
+							
+						
+					
+					
+						WIFI_BT_COEX_CTRL
+						WIFI_BT_COEX_CTRL.
+						0xAC
+						
+							
+								en_gpio_bt_coex
+								12
+								12
+							
+							
+								coex_bt_bw
+								11
+								11
+							
+							
+								coex_bt_pti
+								7
+								10
+							
+							
+								coex_bt_channel
+								0
+								6
+							
+						
+					
+					
+						BZ_COEX_CTRL
+						BZ_COEX_CTRL.
+						0xB0
+						
+							
+								coex_arb
+								28
+								31
+							
+							
+								ble_tx_abort_dis
+								27
+								27
+							
+							
+								ble_rx_abort_dis
+								26
+								26
+							
+							
+								m154_tx_abort_dis
+								25
+								25
+							
+							
+								m154_rx_abort_dis
+								24
+								24
+							
+							
+								coex_force_ch
+								16
+								22
+							
+							
+								coex_option
+								15
+								15
+							
+							
+								force_ble_win
+								14
+								14
+							
+							
+								force_m154_win
+								13
+								13
+							
+							
+								coex_pri
+								12
+								12
+							
+							
+								bz_abort_pol
+								11
+								11
+							
+							
+								bz_active_pol
+								10
+								10
+							
+							
+								bz_pri_pol
+								9
+								9
+							
+							
+								bz_pri_en
+								8
+								8
+							
+							
+								bz_pri_thr
+								4
+								7
+							
+							
+								m154_rx_ignore
+								3
+								3
+							
+							
+								ble_rx_ignore
+								2
+								2
+							
+							
+								wlan_en
+								1
+								1
+							
+							
+								coex_en
+								0
+								0
+							
+						
+					
+					
+						UART_SIG_SEL_0
+						UART_SIG_SEL_0.
+						0xC0
+						
+							
+								uart_sig_7_sel
+								28
+								31
+							
+							
+								uart_sig_6_sel
+								24
+								27
+							
+							
+								uart_sig_5_sel
+								20
+								23
+							
+							
+								uart_sig_4_sel
+								16
+								19
+							
+							
+								uart_sig_3_sel
+								12
+								15
+							
+							
+								uart_sig_2_sel
+								8
+								11
+							
+							
+								uart_sig_1_sel
+								4
+								7
+							
+							
+								uart_sig_0_sel
+								0
+								3
+							
+						
+					
+					
+						DBG_SEL_LL
+						DBG_SEL_LL.
+						0xD0
+						
+							
+								reg_dbg_ll_ctrl
+								0
+								31
+							
+						
+					
+					
+						DBG_SEL_LH
+						DBG_SEL_LH.
+						0xD4
+						
+							
+								reg_dbg_lh_ctrl
+								0
+								31
+							
+						
+					
+					
+						DBG_SEL_HL
+						DBG_SEL_HL.
+						0xD8
+						
+							
+								reg_dbg_hl_ctrl
+								0
+								31
+							
+						
+					
+					
+						DBG_SEL_HH
+						DBG_SEL_HH.
+						0xDC
+						
+							
+								reg_dbg_hh_ctrl
+								0
+								31
+							
+						
+					
+					
+						debug
+						debug.
+						0xE0
+						
+							
+								debug_i
+								1
+								31
+							
+							
+								debug_oe
+								0
+								0
+							
+						
+					
+					
+						GPIO_CFGCTL0
+						GPIO_CFGCTL0.
+						0x100
+						
+							
+								reg_gpio_1_func_sel
+								24
+								28
+							
+							
+								reg_gpio_1_pd
+								21
+								21
+							
+							
+								reg_gpio_1_pu
+								20
+								20
+							
+							
+								reg_gpio_1_drv
+								18
+								19
+							
+							
+								reg_gpio_1_smt
+								17
+								17
+							
+							
+								reg_gpio_1_ie
+								16
+								16
+							
+							
+								reg_gpio_0_func_sel
+								8
+								12
+							
+							
+								reg_gpio_0_pd
+								5
+								5
+							
+							
+								reg_gpio_0_pu
+								4
+								4
+							
+							
+								reg_gpio_0_drv
+								2
+								3
+							
+							
+								reg_gpio_0_smt
+								1
+								1
+							
+							
+								reg_gpio_0_ie
+								0
+								0
+							
+						
+					
+					
+						GPIO_CFGCTL1
+						GPIO_CFGCTL1.
+						0x104
+						
+							
+								reg_gpio_3_func_sel
+								24
+								28
+							
+							
+								reg_gpio_3_pd
+								21
+								21
+							
+							
+								reg_gpio_3_pu
+								20
+								20
+							
+							
+								reg_gpio_3_drv
+								18
+								19
+							
+							
+								reg_gpio_3_smt
+								17
+								17
+							
+							
+								reg_gpio_3_ie
+								16
+								16
+							
+							
+								reg_gpio_2_func_sel
+								8
+								12
+							
+							
+								reg_gpio_2_pd
+								5
+								5
+							
+							
+								reg_gpio_2_pu
+								4
+								4
+							
+							
+								reg_gpio_2_drv
+								2
+								3
+							
+							
+								reg_gpio_2_smt
+								1
+								1
+							
+							
+								reg_gpio_2_ie
+								0
+								0
+							
+						
+					
+					
+						GPIO_CFGCTL2
+						GPIO_CFGCTL2.
+						0x108
+						
+							
+								reg_gpio_5_func_sel
+								24
+								28
+							
+							
+								reg_gpio_5_pd
+								21
+								21
+							
+							
+								reg_gpio_5_pu
+								20
+								20
+							
+							
+								reg_gpio_5_drv
+								18
+								19
+							
+							
+								reg_gpio_5_smt
+								17
+								17
+							
+							
+								reg_gpio_5_ie
+								16
+								16
+							
+							
+								reg_gpio_4_func_sel
+								8
+								12
+							
+							
+								reg_gpio_4_pd
+								5
+								5
+							
+							
+								reg_gpio_4_pu
+								4
+								4
+							
+							
+								reg_gpio_4_drv
+								2
+								3
+							
+							
+								reg_gpio_4_smt
+								1
+								1
+							
+							
+								reg_gpio_4_ie
+								0
+								0
+							
+						
+					
+					
+						GPIO_CFGCTL3
+						GPIO_CFGCTL3.
+						0x10C
+						
+							
+								reg_gpio_7_func_sel
+								24
+								28
+							
+							
+								reg_gpio_7_pd
+								21
+								21
+							
+							
+								reg_gpio_7_pu
+								20
+								20
+							
+							
+								reg_gpio_7_drv
+								18
+								19
+							
+							
+								reg_gpio_7_smt
+								17
+								17
+							
+							
+								reg_gpio_7_ie
+								16
+								16
+							
+							
+								reg_gpio_6_func_sel
+								8
+								12
+							
+							
+								reg_gpio_6_pd
+								5
+								5
+							
+							
+								reg_gpio_6_pu
+								4
+								4
+							
+							
+								reg_gpio_6_drv
+								2
+								3
+							
+							
+								reg_gpio_6_smt
+								1
+								1
+							
+							
+								reg_gpio_6_ie
+								0
+								0
+							
+						
+					
+					
+						GPIO_CFGCTL4
+						GPIO_CFGCTL4.
+						0x110
+						
+							
+								reg_gpio_9_func_sel
+								24
+								28
+							
+							
+								reg_gpio_9_pd
+								21
+								21
+							
+							
+								reg_gpio_9_pu
+								20
+								20
+							
+							
+								reg_gpio_9_drv
+								18
+								19
+							
+							
+								reg_gpio_9_smt
+								17
+								17
+							
+							
+								reg_gpio_9_ie
+								16
+								16
+							
+							
+								reg_gpio_8_func_sel
+								8
+								12
+							
+							
+								reg_gpio_8_pd
+								5
+								5
+							
+							
+								reg_gpio_8_pu
+								4
+								4
+							
+							
+								reg_gpio_8_drv
+								2
+								3
+							
+							
+								reg_gpio_8_smt
+								1
+								1
+							
+							
+								reg_gpio_8_ie
+								0
+								0
+							
+						
+					
+					
+						GPIO_CFGCTL5
+						GPIO_CFGCTL5.
+						0x114
+						
+							
+								reg_gpio_11_func_sel
+								24
+								28
+							
+							
+								reg_gpio_11_pd
+								21
+								21
+							
+							
+								reg_gpio_11_pu
+								20
+								20
+							
+							
+								reg_gpio_11_drv
+								18
+								19
+							
+							
+								reg_gpio_11_smt
+								17
+								17
+							
+							
+								reg_gpio_11_ie
+								16
+								16
+							
+							
+								reg_gpio_10_func_sel
+								8
+								12
+							
+							
+								reg_gpio_10_pd
+								5
+								5
+							
+							
+								reg_gpio_10_pu
+								4
+								4
+							
+							
+								reg_gpio_10_drv
+								2
+								3
+							
+							
+								reg_gpio_10_smt
+								1
+								1
+							
+							
+								reg_gpio_10_ie
+								0
+								0
+							
+						
+					
+					
+						GPIO_CFGCTL6
+						GPIO_CFGCTL6.
+						0x118
+						
+							
+								reg_gpio_13_func_sel
+								24
+								28
+							
+							
+								reg_gpio_13_pd
+								21
+								21
+							
+							
+								reg_gpio_13_pu
+								20
+								20
+							
+							
+								reg_gpio_13_drv
+								18
+								19
+							
+							
+								reg_gpio_13_smt
+								17
+								17
+							
+							
+								reg_gpio_13_ie
+								16
+								16
+							
+							
+								reg_gpio_12_func_sel
+								8
+								12
+							
+							
+								reg_gpio_12_pd
+								5
+								5
+							
+							
+								reg_gpio_12_pu
+								4
+								4
+							
+							
+								reg_gpio_12_drv
+								2
+								3
+							
+							
+								reg_gpio_12_smt
+								1
+								1
+							
+							
+								reg_gpio_12_ie
+								0
+								0
+							
+						
+					
+					
+						GPIO_CFGCTL7
+						GPIO_CFGCTL7.
+						0x11C
+						
+							
+								reg_gpio_15_func_sel
+								24
+								28
+							
+							
+								reg_gpio_15_pd
+								21
+								21
+							
+							
+								reg_gpio_15_pu
+								20
+								20
+							
+							
+								reg_gpio_15_drv
+								18
+								19
+							
+							
+								reg_gpio_15_smt
+								17
+								17
+							
+							
+								reg_gpio_15_ie
+								16
+								16
+							
+							
+								reg_gpio_14_func_sel
+								8
+								12
+							
+							
+								reg_gpio_14_pd
+								5
+								5
+							
+							
+								reg_gpio_14_pu
+								4
+								4
+							
+							
+								reg_gpio_14_drv
+								2
+								3
+							
+							
+								reg_gpio_14_smt
+								1
+								1
+							
+							
+								reg_gpio_14_ie
+								0
+								0
+							
+						
+					
+					
+						GPIO_CFGCTL8
+						GPIO_CFGCTL8.
+						0x120
+						
+							
+								reg_gpio_17_func_sel
+								24
+								28
+							
+							
+								reg_gpio_17_pd
+								21
+								21
+							
+							
+								reg_gpio_17_pu
+								20
+								20
+							
+							
+								reg_gpio_17_drv
+								18
+								19
+							
+							
+								reg_gpio_17_smt
+								17
+								17
+							
+							
+								reg_gpio_17_ie
+								16
+								16
+							
+							
+								reg_gpio_16_func_sel
+								8
+								12
+							
+							
+								reg_gpio_16_pd
+								5
+								5
+							
+							
+								reg_gpio_16_pu
+								4
+								4
+							
+							
+								reg_gpio_16_drv
+								2
+								3
+							
+							
+								reg_gpio_16_smt
+								1
+								1
+							
+							
+								reg_gpio_16_ie
+								0
+								0
+							
+						
+					
+					
+						GPIO_CFGCTL9
+						GPIO_CFGCTL9.
+						0x124
+						
+							
+								reg_gpio_19_func_sel
+								24
+								28
+							
+							
+								reg_gpio_19_pd
+								21
+								21
+							
+							
+								reg_gpio_19_pu
+								20
+								20
+							
+							
+								reg_gpio_19_drv
+								18
+								19
+							
+							
+								reg_gpio_19_smt
+								17
+								17
+							
+							
+								reg_gpio_19_ie
+								16
+								16
+							
+							
+								reg_gpio_18_func_sel
+								8
+								12
+							
+							
+								reg_gpio_18_pd
+								5
+								5
+							
+							
+								reg_gpio_18_pu
+								4
+								4
+							
+							
+								reg_gpio_18_drv
+								2
+								3
+							
+							
+								reg_gpio_18_smt
+								1
+								1
+							
+							
+								reg_gpio_18_ie
+								0
+								0
+							
+						
+					
+					
+						GPIO_CFGCTL10
+						GPIO_CFGCTL10.
+						0x128
+						
+							
+								reg_gpio_21_func_sel
+								24
+								28
+							
+							
+								reg_gpio_21_pd
+								21
+								21
+							
+							
+								reg_gpio_21_pu
+								20
+								20
+							
+							
+								reg_gpio_21_drv
+								18
+								19
+							
+							
+								reg_gpio_21_smt
+								17
+								17
+							
+							
+								reg_gpio_21_ie
+								16
+								16
+							
+							
+								reg_gpio_20_func_sel
+								8
+								12
+							
+							
+								reg_gpio_20_pd
+								5
+								5
+							
+							
+								reg_gpio_20_pu
+								4
+								4
+							
+							
+								reg_gpio_20_drv
+								2
+								3
+							
+							
+								reg_gpio_20_smt
+								1
+								1
+							
+							
+								reg_gpio_20_ie
+								0
+								0
+							
+						
+					
+					
+						GPIO_CFGCTL11
+						GPIO_CFGCTL11.
+						0x12C
+						
+							
+								reg_gpio_23_func_sel
+								24
+								28
+							
+							
+								reg_gpio_23_pd
+								21
+								21
+							
+							
+								reg_gpio_23_pu
+								20
+								20
+							
+							
+								reg_gpio_23_drv
+								18
+								19
+							
+							
+								reg_gpio_23_smt
+								17
+								17
+							
+							
+								reg_gpio_23_ie
+								16
+								16
+							
+							
+								reg_gpio_22_func_sel
+								8
+								12
+							
+							
+								reg_gpio_22_pd
+								5
+								5
+							
+							
+								reg_gpio_22_pu
+								4
+								4
+							
+							
+								reg_gpio_22_drv
+								2
+								3
+							
+							
+								reg_gpio_22_smt
+								1
+								1
+							
+							
+								reg_gpio_22_ie
+								0
+								0
+							
+						
+					
+					
+						GPIO_CFGCTL12
+						GPIO_CFGCTL12.
+						0x130
+						
+							
+								reg_gpio_25_func_sel
+								24
+								28
+							
+							
+								reg_gpio_25_pd
+								21
+								21
+							
+							
+								reg_gpio_25_pu
+								20
+								20
+							
+							
+								reg_gpio_25_drv
+								18
+								19
+							
+							
+								reg_gpio_25_smt
+								17
+								17
+							
+							
+								reg_gpio_25_ie
+								16
+								16
+							
+							
+								reg_gpio_24_func_sel
+								8
+								12
+							
+							
+								reg_gpio_24_pd
+								5
+								5
+							
+							
+								reg_gpio_24_pu
+								4
+								4
+							
+							
+								reg_gpio_24_drv
+								2
+								3
+							
+							
+								reg_gpio_24_smt
+								1
+								1
+							
+							
+								reg_gpio_24_ie
+								0
+								0
+							
+						
+					
+					
+						GPIO_CFGCTL13
+						GPIO_CFGCTL13.
+						0x134
+						
+							
+								reg_gpio_27_func_sel
+								24
+								28
+							
+							
+								reg_gpio_27_pd
+								21
+								21
+							
+							
+								reg_gpio_27_pu
+								20
+								20
+							
+							
+								reg_gpio_27_drv
+								18
+								19
+							
+							
+								reg_gpio_27_smt
+								17
+								17
+							
+							
+								reg_gpio_27_ie
+								16
+								16
+							
+							
+								reg_gpio_26_func_sel
+								8
+								12
+							
+							
+								reg_gpio_26_pd
+								5
+								5
+							
+							
+								reg_gpio_26_pu
+								4
+								4
+							
+							
+								reg_gpio_26_drv
+								2
+								3
+							
+							
+								reg_gpio_26_smt
+								1
+								1
+							
+							
+								reg_gpio_26_ie
+								0
+								0
+							
+						
+					
+					
+						GPIO_CFGCTL14
+						GPIO_CFGCTL14.
+						0x138
+						
+							
+								reg_gpio_29_func_sel
+								24
+								28
+							
+							
+								reg_gpio_29_pd
+								21
+								21
+							
+							
+								reg_gpio_29_pu
+								20
+								20
+							
+							
+								reg_gpio_29_drv
+								18
+								19
+							
+							
+								reg_gpio_29_smt
+								17
+								17
+							
+							
+								reg_gpio_29_ie
+								16
+								16
+							
+							
+								reg_gpio_28_func_sel
+								8
+								12
+							
+							
+								reg_gpio_28_pd
+								5
+								5
+							
+							
+								reg_gpio_28_pu
+								4
+								4
+							
+							
+								reg_gpio_28_drv
+								2
+								3
+							
+							
+								reg_gpio_28_smt
+								1
+								1
+							
+							
+								reg_gpio_28_ie
+								0
+								0
+							
+						
+					
+					
+						GPIO_CFGCTL15
+						GPIO_CFGCTL15.
+						0x13C
+						
+							
+								reg_gpio_31_func_sel
+								24
+								28
+							
+							
+								reg_gpio_31_pd
+								21
+								21
+							
+							
+								reg_gpio_31_pu
+								20
+								20
+							
+							
+								reg_gpio_31_drv
+								18
+								19
+							
+							
+								reg_gpio_31_smt
+								17
+								17
+							
+							
+								reg_gpio_31_ie
+								16
+								16
+							
+							
+								reg_gpio_30_func_sel
+								8
+								12
+							
+							
+								reg_gpio_30_pd
+								5
+								5
+							
+							
+								reg_gpio_30_pu
+								4
+								4
+							
+							
+								reg_gpio_30_drv
+								2
+								3
+							
+							
+								reg_gpio_30_smt
+								1
+								1
+							
+							
+								reg_gpio_30_ie
+								0
+								0
+							
+						
+					
+					
+						GPIO_CFGCTL16
+						GPIO_CFGCTL16.
+						0x140
+						
+							
+								reg_gpio_33_pd
+								21
+								21
+							
+							
+								reg_gpio_33_pu
+								20
+								20
+							
+							
+								reg_gpio_33_drv
+								18
+								19
+							
+							
+								reg_gpio_33_smt
+								17
+								17
+							
+							
+								reg_gpio_33_ie
+								16
+								16
+							
+							
+								reg_gpio_32_pd
+								5
+								5
+							
+							
+								reg_gpio_32_pu
+								4
+								4
+							
+							
+								reg_gpio_32_drv
+								2
+								3
+							
+							
+								reg_gpio_32_smt
+								1
+								1
+							
+							
+								reg_gpio_32_ie
+								0
+								0
+							
+						
+					
+					
+						GPIO_CFGCTL17
+						GPIO_CFGCTL17.
+						0x144
+						
+							
+								reg_gpio_35_pd
+								21
+								21
+							
+							
+								reg_gpio_35_pu
+								20
+								20
+							
+							
+								reg_gpio_35_drv
+								18
+								19
+							
+							
+								reg_gpio_35_smt
+								17
+								17
+							
+							
+								reg_gpio_35_ie
+								16
+								16
+							
+							
+								reg_gpio_34_pd
+								5
+								5
+							
+							
+								reg_gpio_34_pu
+								4
+								4
+							
+							
+								reg_gpio_34_drv
+								2
+								3
+							
+							
+								reg_gpio_34_smt
+								1
+								1
+							
+							
+								reg_gpio_34_ie
+								0
+								0
+							
+						
+					
+					
+						GPIO_CFGCTL18
+						GPIO_CFGCTL18.
+						0x148
+						
+							
+								reg_gpio_37_pd
+								21
+								21
+							
+							
+								reg_gpio_37_pu
+								20
+								20
+							
+							
+								reg_gpio_37_drv
+								18
+								19
+							
+							
+								reg_gpio_37_smt
+								17
+								17
+							
+							
+								reg_gpio_37_ie
+								16
+								16
+							
+							
+								reg_gpio_36_pd
+								5
+								5
+							
+							
+								reg_gpio_36_pu
+								4
+								4
+							
+							
+								reg_gpio_36_drv
+								2
+								3
+							
+							
+								reg_gpio_36_smt
+								1
+								1
+							
+							
+								reg_gpio_36_ie
+								0
+								0
+							
+						
+					
+					
+						GPIO_CFGCTL30
+						GPIO_CFGCTL30.
+						0x180
+						
+							
+								reg_gpio_31_i
+								31
+								31
+							
+							
+								reg_gpio_30_i
+								30
+								30
+							
+							
+								reg_gpio_29_i
+								29
+								29
+							
+							
+								reg_gpio_28_i
+								28
+								28
+							
+							
+								reg_gpio_27_i
+								27
+								27
+							
+							
+								reg_gpio_26_i
+								26
+								26
+							
+							
+								reg_gpio_25_i
+								25
+								25
+							
+							
+								reg_gpio_24_i
+								24
+								24
+							
+							
+								reg_gpio_23_i
+								23
+								23
+							
+							
+								reg_gpio_22_i
+								22
+								22
+							
+							
+								reg_gpio_21_i
+								21
+								21
+							
+							
+								reg_gpio_20_i
+								20
+								20
+							
+							
+								reg_gpio_19_i
+								19
+								19
+							
+							
+								reg_gpio_18_i
+								18
+								18
+							
+							
+								reg_gpio_17_i
+								17
+								17
+							
+							
+								reg_gpio_16_i
+								16
+								16
+							
+							
+								reg_gpio_15_i
+								15
+								15
+							
+							
+								reg_gpio_14_i
+								14
+								14
+							
+							
+								reg_gpio_13_i
+								13
+								13
+							
+							
+								reg_gpio_12_i
+								12
+								12
+							
+							
+								reg_gpio_11_i
+								11
+								11
+							
+							
+								reg_gpio_10_i
+								10
+								10
+							
+							
+								reg_gpio_9_i
+								9
+								9
+							
+							
+								reg_gpio_8_i
+								8
+								8
+							
+							
+								reg_gpio_7_i
+								7
+								7
+							
+							
+								reg_gpio_6_i
+								6
+								6
+							
+							
+								reg_gpio_5_i
+								5
+								5
+							
+							
+								reg_gpio_4_i
+								4
+								4
+							
+							
+								reg_gpio_3_i
+								3
+								3
+							
+							
+								reg_gpio_2_i
+								2
+								2
+							
+							
+								reg_gpio_1_i
+								1
+								1
+							
+							
+								reg_gpio_0_i
+								0
+								0
+							
+						
+					
+					
+						GPIO_CFGCTL31
+						GPIO_CFGCTL31.
+						0x184
+						
+					
+					
+						GPIO_CFGCTL32
+						GPIO_CFGCTL32.
+						0x188
+						
+							
+								reg_gpio_31_o
+								31
+								31
+							
+							
+								reg_gpio_30_o
+								30
+								30
+							
+							
+								reg_gpio_29_o
+								29
+								29
+							
+							
+								reg_gpio_28_o
+								28
+								28
+							
+							
+								reg_gpio_27_o
+								27
+								27
+							
+							
+								reg_gpio_26_o
+								26
+								26
+							
+							
+								reg_gpio_25_o
+								25
+								25
+							
+							
+								reg_gpio_24_o
+								24
+								24
+							
+							
+								reg_gpio_23_o
+								23
+								23
+							
+							
+								reg_gpio_22_o
+								22
+								22
+							
+							
+								reg_gpio_21_o
+								21
+								21
+							
+							
+								reg_gpio_20_o
+								20
+								20
+							
+							
+								reg_gpio_19_o
+								19
+								19
+							
+							
+								reg_gpio_18_o
+								18
+								18
+							
+							
+								reg_gpio_17_o
+								17
+								17
+							
+							
+								reg_gpio_16_o
+								16
+								16
+							
+							
+								reg_gpio_15_o
+								15
+								15
+							
+							
+								reg_gpio_14_o
+								14
+								14
+							
+							
+								reg_gpio_13_o
+								13
+								13
+							
+							
+								reg_gpio_12_o
+								12
+								12
+							
+							
+								reg_gpio_11_o
+								11
+								11
+							
+							
+								reg_gpio_10_o
+								10
+								10
+							
+							
+								reg_gpio_9_o
+								9
+								9
+							
+							
+								reg_gpio_8_o
+								8
+								8
+							
+							
+								reg_gpio_7_o
+								7
+								7
+							
+							
+								reg_gpio_6_o
+								6
+								6
+							
+							
+								reg_gpio_5_o
+								5
+								5
+							
+							
+								reg_gpio_4_o
+								4
+								4
+							
+							
+								reg_gpio_3_o
+								3
+								3
+							
+							
+								reg_gpio_2_o
+								2
+								2
+							
+							
+								reg_gpio_1_o
+								1
+								1
+							
+							
+								reg_gpio_0_o
+								0
+								0
+							
+						
+					
+					
+						GPIO_CFGCTL33
+						GPIO_CFGCTL33.
+						0x18C
+						
+					
+					
+						GPIO_CFGCTL34
+						GPIO_CFGCTL34.
+						0x190
+						
+							
+								reg_gpio_31_oe
+								31
+								31
+							
+							
+								reg_gpio_30_oe
+								30
+								30
+							
+							
+								reg_gpio_29_oe
+								29
+								29
+							
+							
+								reg_gpio_28_oe
+								28
+								28
+							
+							
+								reg_gpio_27_oe
+								27
+								27
+							
+							
+								reg_gpio_26_oe
+								26
+								26
+							
+							
+								reg_gpio_25_oe
+								25
+								25
+							
+							
+								reg_gpio_24_oe
+								24
+								24
+							
+							
+								reg_gpio_23_oe
+								23
+								23
+							
+							
+								reg_gpio_22_oe
+								22
+								22
+							
+							
+								reg_gpio_21_oe
+								21
+								21
+							
+							
+								reg_gpio_20_oe
+								20
+								20
+							
+							
+								reg_gpio_19_oe
+								19
+								19
+							
+							
+								reg_gpio_18_oe
+								18
+								18
+							
+							
+								reg_gpio_17_oe
+								17
+								17
+							
+							
+								reg_gpio_16_oe
+								16
+								16
+							
+							
+								reg_gpio_15_oe
+								15
+								15
+							
+							
+								reg_gpio_14_oe
+								14
+								14
+							
+							
+								reg_gpio_13_oe
+								13
+								13
+							
+							
+								reg_gpio_12_oe
+								12
+								12
+							
+							
+								reg_gpio_11_oe
+								11
+								11
+							
+							
+								reg_gpio_10_oe
+								10
+								10
+							
+							
+								reg_gpio_9_oe
+								9
+								9
+							
+							
+								reg_gpio_8_oe
+								8
+								8
+							
+							
+								reg_gpio_7_oe
+								7
+								7
+							
+							
+								reg_gpio_6_oe
+								6
+								6
+							
+							
+								reg_gpio_5_oe
+								5
+								5
+							
+							
+								reg_gpio_4_oe
+								4
+								4
+							
+							
+								reg_gpio_3_oe
+								3
+								3
+							
+							
+								reg_gpio_2_oe
+								2
+								2
+							
+							
+								reg_gpio_1_oe
+								1
+								1
+							
+							
+								reg_gpio_0_oe
+								0
+								0
+							
+						
+					
+					
+						GPIO_CFGCTL35
+						GPIO_CFGCTL35.
+						0x194
+						
+					
+					
+						GPIO_INT_MASK1
+						GPIO_INT_MASK1.
+						0x1A0
+						
+							
+								reg_gpio_int_mask1
+								0
+								31
+							
+						
+					
+					
+						GPIO_INT_STAT1
+						GPIO_INT_STAT1.
+						0x1A8
+						
+							
+								gpio_int_stat1
+								0
+								31
+							
+						
+					
+					
+						GPIO_INT_CLR1
+						GPIO_INT_CLR1.
+						0x1B0
+						
+							
+								reg_gpio_int_clr1
+								0
+								31
+							
+						
+					
+					
+						GPIO_INT_MODE_SET1
+						GPIO_INT_MODE_SET1.
+						0x1C0
+						
+							
+								reg_gpio_int_mode_set1
+								0
+								29
+							
+						
+					
+					
+						GPIO_INT_MODE_SET2
+						GPIO_INT_MODE_SET2.
+						0x1C4
+						
+							
+								reg_gpio_int_mode_set2
+								0
+								29
+							
+						
+					
+					
+						GPIO_INT_MODE_SET3
+						GPIO_INT_MODE_SET3.
+						0x1C8
+						
+							
+								reg_gpio_int_mode_set3
+								0
+								29
+							
+						
+					
+					
+						GPIO_INT_MODE_SET4
+						GPIO_INT_MODE_SET4.
+						0x1CC
+						
+							
+								reg_gpio_int_mode_set4
+								0
+								5
+							
+						
+					
+					
+						GPIO_INT2_MASK1
+						GPIO_INT2_MASK1.
+						0x1D0
+						
+							
+								reg_gpio_int2_mask1
+								0
+								31
+							
+						
+					
+					
+						GPIO_INT2_STAT1
+						GPIO_INT2_STAT1.
+						0x1D4
+						
+							
+								gpio_int2_stat1
+								0
+								31
+							
+						
+					
+					
+						GPIO_INT2_CLR1
+						GPIO_INT2_CLR1.
+						0x1D8
+						
+							
+								reg_gpio_int2_clr1
+								0
+								31
+							
+						
+					
+					
+						GPIO_INT2_MODE_SET1
+						GPIO_INT2_MODE_SET1.
+						0x1DC
+						
+							
+								reg_gpio_int2_mode_set1
+								0
+								29
+							
+						
+					
+					
+						GPIO_INT2_MODE_SET2
+						GPIO_INT2_MODE_SET2.
+						0x1E0
+						
+							
+								reg_gpio_int2_mode_set2
+								0
+								29
+							
+						
+					
+					
+						GPIO_INT2_MODE_SET3
+						GPIO_INT2_MODE_SET3.
+						0x1E4
+						
+							
+								reg_gpio_int2_mode_set3
+								0
+								29
+							
+						
+					
+					
+						GPIO_INT2_MODE_SET4
+						GPIO_INT2_MODE_SET4.
+						0x1E8
+						
+							
+								reg_gpio_int2_mode_set4
+								0
+								5
+							
+						
+					
+					
+						dll
+						dll.
+						0x200
+						
+							
+								ppu_dll
+								31
+								31
+							
+							
+								pu_dll
+								30
+								30
+							
+							
+								dll_reset
+								29
+								29
+							
+							
+								dll_refclk_sel
+								28
+								28
+							
+							
+								dll_cp_hiz
+								23
+								23
+							
+							
+								dll_cp_op_en
+								22
+								22
+							
+							
+								dll_delay_sel
+								20
+								21
+							
+							
+								dll_post_div
+								16
+								19
+							
+							
+								dll_vctrl_force_en
+								15
+								15
+							
+							
+								dll_prechg_en
+								14
+								14
+							
+							
+								dll_prechg_reg
+								13
+								13
+							
+							
+								dll_prechg_sel
+								12
+								12
+							
+							
+								dll_vctrl_sel
+								8
+								10
+							
+							
+								dll_clk_57p6M_en
+								7
+								7
+							
+							
+								dll_clk_96M_en
+								6
+								6
+							
+							
+								dll_clk_144M_en
+								5
+								5
+							
+							
+								dll_clk_288M_en
+								4
+								4
+							
+							
+								dll_clk_mmdiv_en
+								3
+								3
+							
+							
+								ten_dll
+								2
+								2
+							
+							
+								dtest_en_dll_outclk
+								1
+								1
+							
+							
+								dtest_en_dll_refclk
+								0
+								0
+							
+						
+					
+					
+						led_driver
+						led_driver.
+						0x224
+						
+							
+								pu_leddrv
+								31
+								31
+							
+							
+								leddrv_out_en
+								28
+								29
+							
+							
+								ir_rx_gpio_sel
+								8
+								11
+							
+							
+								leddrv_ibias
+								4
+								7
+							
+							
+								led_din_polarity_sel
+								2
+								2
+							
+							
+								led_din_sel
+								1
+								1
+							
+							
+								led_din_reg
+								0
+								0
+							
+						
+					
+					
+						usb_xcvr
+						usb_xcvr.
+						0x228
+						
+							
+								usb_rcv
+								27
+								27
+							
+							
+								usb_vip
+								26
+								26
+							
+							
+								usb_vim
+								25
+								25
+							
+							
+								usb_bd
+								24
+								24
+							
+							
+								pu_usb
+								23
+								23
+							
+							
+								usb_sus
+								22
+								22
+							
+							
+								usb_spd
+								21
+								21
+							
+							
+								usb_enum
+								20
+								20
+							
+							
+								usb_data_convert
+								16
+								16
+							
+							
+								usb_oeb
+								14
+								14
+							
+							
+								usb_oeb_reg
+								13
+								13
+							
+							
+								usb_oeb_sel
+								12
+								12
+							
+							
+								usb_rout_pmos
+								8
+								10
+							
+							
+								usb_rout_nmos
+								4
+								6
+							
+							
+								pu_usb_ldo
+								3
+								3
+							
+							
+								usb_ldo_vfb
+								0
+								2
+							
+						
+					
+					
+						usb_xcvr_config
+						usb_xcvr_config.
+						0x22C
+						
+							
+								usb_slewrate_p_rise
+								28
+								30
+							
+							
+								usb_slewrate_p_fall
+								24
+								26
+							
+							
+								usb_slewrate_m_rise
+								20
+								22
+							
+							
+								usb_slewrate_m_fall
+								16
+								18
+							
+							
+								usb_res_pullup_tune
+								12
+								14
+							
+							
+								reg_usb_use_ctrl
+								11
+								11
+							
+							
+								usb_str_drv
+								8
+								10
+							
+							
+								reg_usb_use_xcvr
+								7
+								7
+							
+							
+								usb_bd_vth
+								4
+								6
+							
+							
+								usb_v_hys_p
+								2
+								3
+							
+							
+								usb_v_hys_m
+								0
+								1
+							
+						
+					
+					
+						gpdac_ctrl
+						gpdac_ctrl.
+						0x308
+						
+							
+								gpdac_reserved
+								24
+								31
+							
+							
+								gpdac_test_sel
+								9
+								11
+							
+							
+								gpdac_ref_sel
+								8
+								8
+							
+							
+								gpdac_test_en
+								7
+								7
+							
+							
+								gpdacb_rstn_ana
+								1
+								1
+							
+							
+								gpdaca_rstn_ana
+								0
+								0
+							
+						
+					
+					
+						gpdac_actrl
+						gpdac_actrl.
+						0x30C
+						
+							
+								gpdac_a_outmux
+								20
+								22
+							
+							
+								gpdac_a_rng
+								18
+								19
+							
+							
+								gpdac_ioa_en
+								1
+								1
+							
+							
+								gpdac_a_en
+								0
+								0
+							
+						
+					
+					
+						gpdac_bctrl
+						gpdac_bctrl.
+						0x310
+						
+							
+								gpdac_b_outmux
+								20
+								22
+							
+							
+								gpdac_b_rng
+								18
+								19
+							
+							
+								gpdac_iob_en
+								1
+								1
+							
+							
+								gpdac_b_en
+								0
+								0
+							
+						
+					
+					
+						gpdac_data
+						gpdac_data.
+						0x314
+						
+							
+								gpdac_a_data
+								16
+								25
+							
+							
+								gpdac_b_data
+								0
+								9
+							
+						
+					
+					
+						chip_revision
+						chip_revision.
+						0xE00
+						
+							
+								chip_rev
+								0
+								3
+							
+						
+					
+					
+						tzc_glb_ctrl_0
+						tzc_glb_ctrl_0.
+						0xF00
+						
+							
+								tzc_glb_clk_lock
+								31
+								31
+							
+							
+								tzc_glb_mbist_lock
+								30
+								30
+							
+							
+								tzc_glb_dbg_lock
+								29
+								29
+							
+							
+								tzc_glb_bmx_lock
+								28
+								28
+							
+							
+								tzc_glb_l2c_lock
+								27
+								27
+							
+							
+								tzc_glb_sram_lock
+								26
+								26
+							
+							
+								tzc_glb_misc_lock
+								25
+								25
+							
+							
+								tzc_glb_ctrl_ungated_ap_lock
+								15
+								15
+							
+							
+								tzc_glb_ctrl_sys_reset_lock
+								14
+								14
+							
+							
+								tzc_glb_ctrl_cpu_reset_lock
+								13
+								13
+							
+							
+								tzc_glb_ctrl_pwron_rst_lock
+								12
+								12
+							
+							
+								tzc_glb_swrst_s30_lock
+								8
+								8
+							
+							
+								tzc_glb_swrst_s01_lock
+								1
+								1
+							
+							
+								tzc_glb_swrst_s00_lock
+								0
+								0
+							
+						
+					
+					
+						tzc_glb_ctrl_1
+						tzc_glb_ctrl_1.
+						0xF04
+						
+							
+								tzc_glb_swrst_s1f_lock
+								31
+								31
+							
+							
+								tzc_glb_swrst_s1e_lock
+								30
+								30
+							
+							
+								tzc_glb_swrst_s1d_lock
+								29
+								29
+							
+							
+								tzc_glb_swrst_s1c_lock
+								28
+								28
+							
+							
+								tzc_glb_swrst_s1b_lock
+								27
+								27
+							
+							
+								tzc_glb_swrst_s1a_lock
+								26
+								26
+							
+							
+								tzc_glb_swrst_s19_lock
+								25
+								25
+							
+							
+								tzc_glb_swrst_s18_lock
+								24
+								24
+							
+							
+								tzc_glb_swrst_s17_lock
+								23
+								23
+							
+							
+								tzc_glb_swrst_s16_lock
+								22
+								22
+							
+							
+								tzc_glb_swrst_s15_lock
+								21
+								21
+							
+							
+								tzc_glb_swrst_s14_lock
+								20
+								20
+							
+							
+								tzc_glb_swrst_s13_lock
+								19
+								19
+							
+							
+								tzc_glb_swrst_s12_lock
+								18
+								18
+							
+							
+								tzc_glb_swrst_s11_lock
+								17
+								17
+							
+							
+								tzc_glb_swrst_s10_lock
+								16
+								16
+							
+							
+								tzc_glb_swrst_s2f_lock
+								15
+								15
+							
+							
+								tzc_glb_swrst_s2e_lock
+								14
+								14
+							
+							
+								tzc_glb_swrst_s2d_lock
+								13
+								13
+							
+							
+								tzc_glb_swrst_s2c_lock
+								12
+								12
+							
+							
+								tzc_glb_swrst_s2b_lock
+								11
+								11
+							
+							
+								tzc_glb_swrst_s2a_lock
+								10
+								10
+							
+							
+								tzc_glb_swrst_s29_lock
+								9
+								9
+							
+							
+								tzc_glb_swrst_s28_lock
+								8
+								8
+							
+							
+								tzc_glb_swrst_s27_lock
+								7
+								7
+							
+							
+								tzc_glb_swrst_s26_lock
+								6
+								6
+							
+							
+								tzc_glb_swrst_s25_lock
+								5
+								5
+							
+							
+								tzc_glb_swrst_s24_lock
+								4
+								4
+							
+							
+								tzc_glb_swrst_s23_lock
+								3
+								3
+							
+							
+								tzc_glb_swrst_s22_lock
+								2
+								2
+							
+							
+								tzc_glb_swrst_s21_lock
+								1
+								1
+							
+							
+								tzc_glb_swrst_s20_lock
+								0
+								0
+							
+						
+					
+					
+						tzc_glb_ctrl_2
+						tzc_glb_ctrl_2.
+						0xF08
+						
+							
+								tzc_glb_gpio_31_lock
+								31
+								31
+							
+							
+								tzc_glb_gpio_30_lock
+								30
+								30
+							
+							
+								tzc_glb_gpio_29_lock
+								29
+								29
+							
+							
+								tzc_glb_gpio_28_lock
+								28
+								28
+							
+							
+								tzc_glb_gpio_27_lock
+								27
+								27
+							
+							
+								tzc_glb_gpio_26_lock
+								26
+								26
+							
+							
+								tzc_glb_gpio_25_lock
+								25
+								25
+							
+							
+								tzc_glb_gpio_24_lock
+								24
+								24
+							
+							
+								tzc_glb_gpio_23_lock
+								23
+								23
+							
+							
+								tzc_glb_gpio_22_lock
+								22
+								22
+							
+							
+								tzc_glb_gpio_21_lock
+								21
+								21
+							
+							
+								tzc_glb_gpio_20_lock
+								20
+								20
+							
+							
+								tzc_glb_gpio_19_lock
+								19
+								19
+							
+							
+								tzc_glb_gpio_18_lock
+								18
+								18
+							
+							
+								tzc_glb_gpio_17_lock
+								17
+								17
+							
+							
+								tzc_glb_gpio_16_lock
+								16
+								16
+							
+							
+								tzc_glb_gpio_15_lock
+								15
+								15
+							
+							
+								tzc_glb_gpio_14_lock
+								14
+								14
+							
+							
+								tzc_glb_gpio_13_lock
+								13
+								13
+							
+							
+								tzc_glb_gpio_12_lock
+								12
+								12
+							
+							
+								tzc_glb_gpio_11_lock
+								11
+								11
+							
+							
+								tzc_glb_gpio_10_lock
+								10
+								10
+							
+							
+								tzc_glb_gpio_9_lock
+								9
+								9
+							
+							
+								tzc_glb_gpio_8_lock
+								8
+								8
+							
+							
+								tzc_glb_gpio_7_lock
+								7
+								7
+							
+							
+								tzc_glb_gpio_6_lock
+								6
+								6
+							
+							
+								tzc_glb_gpio_5_lock
+								5
+								5
+							
+							
+								tzc_glb_gpio_4_lock
+								4
+								4
+							
+							
+								tzc_glb_gpio_3_lock
+								3
+								3
+							
+							
+								tzc_glb_gpio_2_lock
+								2
+								2
+							
+							
+								tzc_glb_gpio_1_lock
+								1
+								1
+							
+							
+								tzc_glb_gpio_0_lock
+								0
+								0
+							
+						
+					
+					
+						tzc_glb_ctrl_3
+						tzc_glb_ctrl_3.
+						0xF0C
+						
+							
+								tzc_glb_gpio_37_lock
+								5
+								5
+							
+							
+								tzc_glb_gpio_36_lock
+								4
+								4
+							
+							
+								tzc_glb_gpio_35_lock
+								3
+								3
+							
+							
+								tzc_glb_gpio_34_lock
+								2
+								2
+							
+							
+								tzc_glb_gpio_33_lock
+								1
+								1
+							
+							
+								tzc_glb_gpio_32_lock
+								0
+								0
+							
+						
+					
+				
+			
+			
+				gpip
+				gpip.
+				0x40002000
+				gpip
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						gpadc_config
+						gpadc_config.
+						0x0
+						
+							
+								rsvd_31_24
+								24
+								31
+							
+							
+								gpadc_fifo_thl
+								22
+								23
+							
+							
+								gpadc_fifo_data_count
+								16
+								21
+							
+							
+								gpadc_fifo_rdy_mask
+								15
+								15
+							
+							
+								gpadc_fifo_underrun_mask
+								14
+								14
+							
+							
+								gpadc_fifo_overrun_mask
+								13
+								13
+							
+							
+								gpadc_rdy_mask
+								12
+								12
+							
+							
+								gpadc_fifo_underrun_clr
+								10
+								10
+							
+							
+								gpadc_fifo_overrun_clr
+								9
+								9
+							
+							
+								gpadc_rdy_clr
+								8
+								8
+							
+							
+								gpadc_fifo_rdy
+								7
+								7
+							
+							
+								gpadc_fifo_underrun
+								6
+								6
+							
+							
+								gpadc_fifo_overrun
+								5
+								5
+							
+							
+								gpadc_rdy
+								4
+								4
+							
+							
+								gpadc_fifo_full
+								3
+								3
+							
+							
+								gpadc_fifo_ne
+								2
+								2
+							
+							
+								gpadc_fifo_clr
+								1
+								1
+							
+							
+								gpadc_dma_en
+								0
+								0
+							
+						
+					
+					
+						gpadc_dma_rdata
+						gpadc_dma_rdata.
+						0x4
+						
+							
+								rsvd_31_26
+								26
+								31
+							
+							
+								gpadc_dma_rdata
+								0
+								25
+							
+						
+					
+					
+						gpdac_config
+						gpdac_config.
+						0x40
+						
+							
+								rsvd_31_24
+								24
+								31
+							
+							
+								gpdac_ch_b_sel
+								20
+								23
+							
+							
+								gpdac_ch_a_sel
+								16
+								19
+							
+							
+								gpdac_mode
+								8
+								10
+							
+							
+								dsm_mode
+								4
+								5
+							
+							
+								gpdac_en2
+								1
+								1
+							
+							
+								gpdac_en
+								0
+								0
+							
+						
+					
+					
+						gpdac_dma_config
+						gpdac_dma_config.
+						0x44
+						
+							
+								gpdac_dma_format
+								4
+								5
+							
+							
+								gpdac_dma_tx_en
+								0
+								0
+							
+						
+					
+					
+						gpdac_dma_wdata
+						gpdac_dma_wdata.
+						0x48
+						
+							
+								gpdac_dma_wdata
+								0
+								31
+							
+						
+					
+					
+						gpdac_tx_fifo_status
+						gpdac_tx_fifo_status.
+						0x4C
+						
+							
+								TxFifoWrPtr
+								8
+								9
+							
+							
+								TxFifoRdPtr
+								4
+								6
+							
+							
+								tx_cs
+								2
+								3
+							
+							
+								tx_fifo_full
+								1
+								1
+							
+							
+								tx_fifo_empty
+								0
+								0
+							
+						
+					
+				
+			
+			
+				sec_dbg
+				sec_dbg.
+				0x40003000
+				sec_dbg
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						sd_chip_id_low
+						sd_chip_id_low.
+						0x0
+						
+							
+								sd_chip_id_low
+								0
+								31
+							
+						
+					
+					
+						sd_chip_id_high
+						sd_chip_id_high.
+						0x4
+						
+							
+								sd_chip_id_high
+								0
+								31
+							
+						
+					
+					
+						sd_wifi_mac_low
+						sd_wifi_mac_low.
+						0x8
+						
+							
+								sd_wifi_mac_low
+								0
+								31
+							
+						
+					
+					
+						sd_wifi_mac_high
+						sd_wifi_mac_high.
+						0xC
+						
+							
+								sd_wifi_mac_high
+								0
+								31
+							
+						
+					
+					
+						sd_dbg_pwd_low
+						sd_dbg_pwd_low.
+						0x10
+						
+							
+								sd_dbg_pwd_low
+								0
+								31
+							
+						
+					
+					
+						sd_dbg_pwd_high
+						sd_dbg_pwd_high.
+						0x14
+						
+							
+								sd_dbg_pwd_high
+								0
+								31
+							
+						
+					
+					
+						sd_status
+						sd_status.
+						0x18
+						
+							
+								sd_dbg_ena
+								28
+								31
+							
+							
+								sd_dbg_mode
+								24
+								27
+							
+							
+								sd_dbg_pwd_cnt
+								4
+								23
+							
+							
+								sd_dbg_cci_clk_sel
+								3
+								3
+							
+							
+								sd_dbg_cci_read_en
+								2
+								2
+							
+							
+								sd_dbg_pwd_trig
+								1
+								1
+							
+							
+								sd_dbg_pwd_busy
+								0
+								0
+							
+						
+					
+					
+						sd_dbg_reserved
+						sd_dbg_reserved.
+						0x1C
+						
+							
+								sd_dbg_reserved
+								0
+								31
+							
+						
+					
+				
+			
+			
+				sec_eng
+				sec_eng.
+				0x40004000
+				sec_eng
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						se_sha_0_ctrl
+						se_sha_0_ctrl.
+						0x0
+						
+							
+								se_sha_0_msg_len
+								16
+								31
+							
+							
+								se_sha_0_link_mode
+								15
+								15
+							
+							
+								se_sha_0_int_mask
+								11
+								11
+							
+							
+								se_sha_0_int_set_1t
+								10
+								10
+							
+							
+								se_sha_0_int_clr_1t
+								9
+								9
+							
+							
+								se_sha_0_int
+								8
+								8
+							
+							
+								se_sha_0_hash_sel
+								6
+								6
+							
+							
+								se_sha_0_en
+								5
+								5
+							
+							
+								se_sha_0_mode
+								2
+								4
+							
+							
+								se_sha_0_trig_1t
+								1
+								1
+							
+							
+								se_sha_0_busy
+								0
+								0
+							
+						
+					
+					
+						se_sha_0_msa
+						se_sha_0_msa.
+						0x4
+						
+							
+								se_sha_0_msa
+								0
+								31
+							
+						
+					
+					
+						se_sha_0_status
+						se_sha_0_status.
+						0x8
+						
+							
+								se_sha_0_status
+								0
+								31
+							
+						
+					
+					
+						se_sha_0_endian
+						se_sha_0_endian.
+						0xC
+						
+							
+								se_sha_0_dout_endian
+								0
+								0
+							
+						
+					
+					
+						se_sha_0_hash_l_0
+						se_sha_0_hash_l_0.
+						0x10
+						
+							
+								se_sha_0_hash_l_0
+								0
+								31
+							
+						
+					
+					
+						se_sha_0_hash_l_1
+						se_sha_0_hash_l_1.
+						0x14
+						
+							
+								se_sha_0_hash_l_1
+								0
+								31
+							
+						
+					
+					
+						se_sha_0_hash_l_2
+						se_sha_0_hash_l_2.
+						0x18
+						
+							
+								se_sha_0_hash_l_2
+								0
+								31
+							
+						
+					
+					
+						se_sha_0_hash_l_3
+						se_sha_0_hash_l_3.
+						0x1C
+						
+							
+								se_sha_0_hash_l_3
+								0
+								31
+							
+						
+					
+					
+						se_sha_0_hash_l_4
+						se_sha_0_hash_l_4.
+						0x20
+						
+							
+								se_sha_0_hash_l_4
+								0
+								31
+							
+						
+					
+					
+						se_sha_0_hash_l_5
+						se_sha_0_hash_l_5.
+						0x24
+						
+							
+								se_sha_0_hash_l_5
+								0
+								31
+							
+						
+					
+					
+						se_sha_0_hash_l_6
+						se_sha_0_hash_l_6.
+						0x28
+						
+							
+								se_sha_0_hash_l_6
+								0
+								31
+							
+						
+					
+					
+						se_sha_0_hash_l_7
+						se_sha_0_hash_l_7.
+						0x2C
+						
+							
+								se_sha_0_hash_l_7
+								0
+								31
+							
+						
+					
+					
+						se_sha_0_hash_h_0
+						se_sha_0_hash_h_0.
+						0x30
+						
+							
+								se_sha_0_hash_h_0
+								0
+								31
+							
+						
+					
+					
+						se_sha_0_hash_h_1
+						se_sha_0_hash_h_1.
+						0x34
+						
+							
+								se_sha_0_hash_h_1
+								0
+								31
+							
+						
+					
+					
+						se_sha_0_hash_h_2
+						se_sha_0_hash_h_2.
+						0x38
+						
+							
+								se_sha_0_hash_h_2
+								0
+								31
+							
+						
+					
+					
+						se_sha_0_hash_h_3
+						se_sha_0_hash_h_3.
+						0x3C
+						
+							
+								se_sha_0_hash_h_3
+								0
+								31
+							
+						
+					
+					
+						se_sha_0_hash_h_4
+						se_sha_0_hash_h_4.
+						0x40
+						
+							
+								se_sha_0_hash_h_4
+								0
+								31
+							
+						
+					
+					
+						se_sha_0_hash_h_5
+						se_sha_0_hash_h_5.
+						0x44
+						
+							
+								se_sha_0_hash_h_5
+								0
+								31
+							
+						
+					
+					
+						se_sha_0_hash_h_6
+						se_sha_0_hash_h_6.
+						0x48
+						
+							
+								se_sha_0_hash_h_6
+								0
+								31
+							
+						
+					
+					
+						se_sha_0_hash_h_7
+						se_sha_0_hash_h_7.
+						0x4C
+						
+							
+								se_sha_0_hash_h_7
+								0
+								31
+							
+						
+					
+					
+						se_sha_0_link
+						se_sha_0_link.
+						0x50
+						
+							
+								se_sha_0_lca
+								0
+								31
+							
+						
+					
+					
+						se_sha_0_ctrl_prot
+						se_sha_0_ctrl_prot.
+						0xFC
+						
+							
+								se_sha_id1_en
+								2
+								2
+							
+							
+								se_sha_id0_en
+								1
+								1
+							
+							
+								se_sha_prot_en
+								0
+								0
+							
+						
+					
+					
+						se_aes_0_ctrl
+						se_aes_0_ctrl.
+						0x100
+						
+							
+								se_aes_0_msg_len
+								16
+								31
+							
+							
+								se_aes_0_link_mode
+								15
+								15
+							
+							
+								se_aes_0_iv_sel
+								14
+								14
+							
+							
+								se_aes_0_block_mode
+								12
+								13
+							
+							
+								se_aes_0_int_mask
+								11
+								11
+							
+							
+								se_aes_0_int_set_1t
+								10
+								10
+							
+							
+								se_aes_0_int_clr_1t
+								9
+								9
+							
+							
+								se_aes_0_int
+								8
+								8
+							
+							
+								se_aes_0_hw_key_en
+								7
+								7
+							
+							
+								se_aes_0_dec_key_sel
+								6
+								6
+							
+							
+								se_aes_0_dec_en
+								5
+								5
+							
+							
+								se_aes_0_mode
+								3
+								4
+							
+							
+								se_aes_0_en
+								2
+								2
+							
+							
+								se_aes_0_trig_1t
+								1
+								1
+							
+							
+								se_aes_0_busy
+								0
+								0
+							
+						
+					
+					
+						se_aes_0_msa
+						se_aes_0_msa.
+						0x104
+						
+							
+								se_aes_0_msa
+								0
+								31
+							
+						
+					
+					
+						se_aes_0_mda
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+							
+								se_aes_0_mda
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+						
+					
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+						se_aes_0_status
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+						0x10C
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+							
+								se_aes_0_status
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+							
+						
+					
+					
+						se_aes_0_iv_0
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+						0x110
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+							
+								se_aes_0_iv_0
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+							
+						
+					
+					
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+						0x114
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+							
+								se_aes_0_iv_1
+								0
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+							
+						
+					
+					
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+						0x118
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+							
+								se_aes_0_iv_2
+								0
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+							
+						
+					
+					
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+						0x11C
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+							
+								se_aes_0_iv_3
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+						
+					
+					
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+							
+								se_aes_0_key_0
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+						
+					
+					
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+						0x124
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+							
+								se_aes_0_key_1
+								0
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+							
+						
+					
+					
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+							
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+								0
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+							
+						
+					
+					
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+						0x12C
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+							
+								se_aes_0_key_3
+								0
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+							
+						
+					
+					
+						se_aes_0_key_4
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+						0x130
+						
+							
+								se_aes_0_key_4
+								0
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+							
+						
+					
+					
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+						0x134
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+							
+								se_aes_0_key_5
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+						
+					
+					
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+						0x138
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+							
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+						
+					
+					
+						se_aes_0_key_7
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+						0x13C
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+							
+								se_aes_0_key_7
+								0
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+							
+						
+					
+					
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+						0x140
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+							
+								se_aes_0_key_sel_0
+								0
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+							
+						
+					
+					
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+						0x144
+						
+							
+								se_aes_0_key_sel_1
+								0
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+						
+					
+					
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+						0x148
+						
+							
+								se_aes_0_ctr_len
+								30
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+							
+							
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+							
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+							
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+							
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+						
+					
+					
+						se_aes_0_sboot
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+						0x14C
+						
+							
+								se_aes_0_sboot_key_sel
+								0
+								0
+							
+						
+					
+					
+						se_aes_0_link
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+						0x150
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+							
+								se_aes_0_lca
+								0
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+						
+					
+					
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+							
+								se_aes_id1_en
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+							
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+							
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+					
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+							
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+								14
+								14
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+							
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+								13
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+							
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+								11
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+							
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+								10
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+							
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+							
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+						
+					
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+						
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+						
+					
+					
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+								4
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+							
+							
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+							
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+							
+							
+								se_trng_0_cp_test_en
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+							
+							
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+								0
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+							
+						
+					
+					
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+							
+								se_trng_0_reseed_n_lsb
+								0
+								31
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+						
+					
+					
+						se_trng_0_ctrl_2
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+						0x230
+						
+							
+								se_trng_0_reseed_n_msb
+								0
+								15
+							
+						
+					
+					
+						se_trng_0_ctrl_3
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+							
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+							
+							
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+								26
+								26
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+							
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+								16
+								25
+							
+							
+								se_trng_0_ht_rct_c
+								8
+								15
+							
+							
+								se_trng_0_cp_ratio
+								0
+								7
+							
+						
+					
+					
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+							
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+								0
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+							
+						
+					
+					
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+						
+							
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+								0
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+						
+					
+					
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+						
+							
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+								0
+								31
+							
+						
+					
+					
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+						0x24C
+						
+							
+								se_trng_0_test_out_3
+								0
+								31
+							
+						
+					
+					
+						se_trng_0_ctrl_prot
+						se_trng_0_ctrl_prot.
+						0x2FC
+						
+							
+								se_trng_id1_en
+								2
+								2
+							
+							
+								se_trng_id0_en
+								1
+								1
+							
+							
+								se_trng_prot_en
+								0
+								0
+							
+						
+					
+					
+						se_pka_0_ctrl_0
+						se_pka_0_ctrl_0.
+						0x300
+						
+							
+								se_pka_0_status
+								16
+								31
+							
+							
+								se_pka_0_status_clr_1t
+								15
+								15
+							
+							
+								se_pka_0_ram_clr_md
+								13
+								13
+							
+							
+								se_pka_0_endian
+								12
+								12
+							
+							
+								se_pka_0_int_mask
+								11
+								11
+							
+							
+								se_pka_0_int_set
+								10
+								10
+							
+							
+								se_pka_0_int_clr_1t
+								9
+								9
+							
+							
+								se_pka_0_int
+								8
+								8
+							
+							
+								se_pka_0_prot_md
+								4
+								7
+							
+							
+								se_pka_0_en
+								3
+								3
+							
+							
+								se_pka_0_busy
+								2
+								2
+							
+							
+								se_pka_0_done_clr_1t
+								1
+								1
+							
+							
+								se_pka_0_done
+								0
+								0
+							
+						
+					
+					
+						se_pka_0_seed
+						se_pka_0_seed.
+						0x30C
+						
+							
+								se_pka_0_seed
+								0
+								31
+							
+						
+					
+					
+						se_pka_0_ctrl_1
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+						0x310
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+							
+								se_pka_0_hbypass
+								3
+								3
+							
+							
+								se_pka_0_hburst
+								0
+								2
+							
+						
+					
+					
+						se_pka_0_rw
+						se_pka_0_rw.
+						0x340
+						
+					
+					
+						se_pka_0_rw_burst
+						se_pka_0_rw_burst.
+						0x360
+						
+					
+					
+						se_pka_0_ctrl_prot
+						se_pka_0_ctrl_prot.
+						0x3FC
+						
+							
+								se_pka_id1_en
+								2
+								2
+							
+							
+								se_pka_id0_en
+								1
+								1
+							
+							
+								se_pka_prot_en
+								0
+								0
+							
+						
+					
+					
+						se_cdet_0_ctrl_0
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+						0x400
+						
+							
+								se_cdet_0_g_loop_min
+								24
+								31
+							
+							
+								se_cdet_0_g_loop_max
+								16
+								23
+							
+							
+								se_cdet_0_status
+								2
+								15
+							
+							
+								se_cdet_0_error
+								1
+								1
+							
+							
+								se_cdet_0_en
+								0
+								0
+							
+						
+					
+					
+						se_cdet_0_ctrl_1
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+						0x404
+						
+							
+								se_cdet_0_g_slp_n
+								16
+								23
+							
+							
+								se_cdet_0_t_dly_n
+								8
+								15
+							
+							
+								se_cdet_0_t_loop_n
+								0
+								7
+							
+						
+					
+					
+						se_cdet_0_ctrl_prot
+						se_cdet_0_ctrl_prot.
+						0x4FC
+						
+							
+								se_cdet_id1_en
+								2
+								2
+							
+							
+								se_cdet_id0_en
+								1
+								1
+							
+							
+								se_cdet_prot_en
+								0
+								0
+							
+						
+					
+					
+						se_gmac_0_ctrl_0
+						se_gmac_0_ctrl_0.
+						0x500
+						
+							
+								se_gmac_0_x_endian
+								14
+								14
+							
+							
+								se_gmac_0_h_endian
+								13
+								13
+							
+							
+								se_gmac_0_t_endian
+								12
+								12
+							
+							
+								se_gmac_0_int_mask
+								11
+								11
+							
+							
+								se_gmac_0_int_set_1t
+								10
+								10
+							
+							
+								se_gmac_0_int_clr_1t
+								9
+								9
+							
+							
+								se_gmac_0_int
+								8
+								8
+							
+							
+								se_gmac_0_en
+								2
+								2
+							
+							
+								se_gmac_0_trig_1t
+								1
+								1
+							
+							
+								se_gmac_0_busy
+								0
+								0
+							
+						
+					
+					
+						se_gmac_0_lca
+						se_gmac_0_lca.
+						0x504
+						
+							
+								se_gmac_0_lca
+								0
+								31
+							
+						
+					
+					
+						se_gmac_0_status
+						se_gmac_0_status.
+						0x508
+						
+							
+								se_gmac_0_status
+								0
+								31
+							
+						
+					
+					
+						se_gmac_0_ctrl_prot
+						se_gmac_0_ctrl_prot.
+						0x5FC
+						
+							
+								se_gmac_id1_en
+								2
+								2
+							
+							
+								se_gmac_id0_en
+								1
+								1
+							
+							
+								se_gmac_prot_en
+								0
+								0
+							
+						
+					
+					
+						se_ctrl_prot_rd
+						se_ctrl_prot_rd.
+						0xF00
+						
+							
+								se_dbg_dis
+								31
+								31
+							
+							
+								se_gmac_id1_en_rd
+								22
+								22
+							
+							
+								se_gmac_id0_en_rd
+								21
+								21
+							
+							
+								se_gmac_prot_en_rd
+								20
+								20
+							
+							
+								se_cdet_id1_en_rd
+								18
+								18
+							
+							
+								se_cdet_id0_en_rd
+								17
+								17
+							
+							
+								se_cdet_prot_en_rd
+								16
+								16
+							
+							
+								se_pka_id1_en_rd
+								14
+								14
+							
+							
+								se_pka_id0_en_rd
+								13
+								13
+							
+							
+								se_pka_prot_en_rd
+								12
+								12
+							
+							
+								se_trng_id1_en_rd
+								10
+								10
+							
+							
+								se_trng_id0_en_rd
+								9
+								9
+							
+							
+								se_trng_prot_en_rd
+								8
+								8
+							
+							
+								se_aes_id1_en_rd
+								6
+								6
+							
+							
+								se_aes_id0_en_rd
+								5
+								5
+							
+							
+								se_aes_prot_en_rd
+								4
+								4
+							
+							
+								se_sha_id1_en_rd
+								2
+								2
+							
+							
+								se_sha_id0_en_rd
+								1
+								1
+							
+							
+								se_sha_prot_en_rd
+								0
+								0
+							
+						
+					
+					
+						se_ctrl_reserved_0
+						se_ctrl_reserved_0.
+						0xF04
+						
+							
+								se_ctrl_reserved_0
+								0
+								31
+							
+						
+					
+					
+						se_ctrl_reserved_1
+						se_ctrl_reserved_1.
+						0xF08
+						
+							
+								se_ctrl_reserved_1
+								0
+								31
+							
+						
+					
+					
+						se_ctrl_reserved_2
+						se_ctrl_reserved_2.
+						0xF0C
+						
+							
+								se_ctrl_reserved_2
+								0
+								31
+							
+						
+					
+				
+			
+			
+				tzc_sec
+				tzc_sec.
+				0x40005000
+				tzc_sec
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						tzc_rom_ctrl
+						tzc_rom_ctrl.
+						0x40
+						
+							
+								tzc_sboot_done
+								28
+								31
+							
+							
+								tzc_rom1_r1_lock
+								27
+								27
+							
+							
+								tzc_rom1_r0_lock
+								26
+								26
+							
+							
+								tzc_rom0_r1_lock
+								25
+								25
+							
+							
+								tzc_rom0_r0_lock
+								24
+								24
+							
+							
+								tzc_rom1_r1_en
+								19
+								19
+							
+							
+								tzc_rom1_r0_en
+								18
+								18
+							
+							
+								tzc_rom0_r1_en
+								17
+								17
+							
+							
+								tzc_rom0_r0_en
+								16
+								16
+							
+							
+								tzc_rom1_r1_id1_en
+								11
+								11
+							
+							
+								tzc_rom1_r0_id1_en
+								10
+								10
+							
+							
+								tzc_rom0_r1_id1_en
+								9
+								9
+							
+							
+								tzc_rom0_r0_id1_en
+								8
+								8
+							
+							
+								tzc_rom1_r1_id0_en
+								3
+								3
+							
+							
+								tzc_rom1_r0_id0_en
+								2
+								2
+							
+							
+								tzc_rom0_r1_id0_en
+								1
+								1
+							
+							
+								tzc_rom0_r0_id0_en
+								0
+								0
+							
+						
+					
+					
+						tzc_rom0_r0
+						tzc_rom0_r0.
+						0x44
+						
+							
+								tzc_rom0_r0_start
+								16
+								31
+							
+							
+								tzc_rom0_r0_end
+								0
+								15
+							
+						
+					
+					
+						tzc_rom0_r1
+						tzc_rom0_r1.
+						0x48
+						
+							
+								tzc_rom0_r1_start
+								16
+								31
+							
+							
+								tzc_rom0_r1_end
+								0
+								15
+							
+						
+					
+					
+						tzc_rom1_r0
+						tzc_rom1_r0.
+						0x4C
+						
+							
+								tzc_rom1_r0_start
+								16
+								31
+							
+							
+								tzc_rom1_r0_end
+								0
+								15
+							
+						
+					
+					
+						tzc_rom1_r1
+						tzc_rom1_r1.
+						0x50
+						
+							
+								tzc_rom1_r1_start
+								16
+								31
+							
+							
+								tzc_rom1_r1_end
+								0
+								15
+							
+						
+					
+				
+			
+			
+				tzc_nsec
+				tzc_nsec.
+				0x40006000
+				tzc_nsec
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						tzc_rom_ctrl
+						tzc_rom_ctrl.
+						0x40
+						
+							
+								tzc_sboot_done
+								28
+								31
+							
+							
+								tzc_rom1_r1_lock
+								27
+								27
+							
+							
+								tzc_rom1_r0_lock
+								26
+								26
+							
+							
+								tzc_rom0_r1_lock
+								25
+								25
+							
+							
+								tzc_rom0_r0_lock
+								24
+								24
+							
+							
+								tzc_rom1_r1_en
+								19
+								19
+							
+							
+								tzc_rom1_r0_en
+								18
+								18
+							
+							
+								tzc_rom0_r1_en
+								17
+								17
+							
+							
+								tzc_rom0_r0_en
+								16
+								16
+							
+							
+								tzc_rom1_r1_id1_en
+								11
+								11
+							
+							
+								tzc_rom1_r0_id1_en
+								10
+								10
+							
+							
+								tzc_rom0_r1_id1_en
+								9
+								9
+							
+							
+								tzc_rom0_r0_id1_en
+								8
+								8
+							
+							
+								tzc_rom1_r1_id0_en
+								3
+								3
+							
+							
+								tzc_rom1_r0_id0_en
+								2
+								2
+							
+							
+								tzc_rom0_r1_id0_en
+								1
+								1
+							
+							
+								tzc_rom0_r0_id0_en
+								0
+								0
+							
+						
+					
+					
+						tzc_rom0_r0
+						tzc_rom0_r0.
+						0x44
+						
+							
+								tzc_rom0_r0_start
+								16
+								31
+							
+							
+								tzc_rom0_r0_end
+								0
+								15
+							
+						
+					
+					
+						tzc_rom0_r1
+						tzc_rom0_r1.
+						0x48
+						
+							
+								tzc_rom0_r1_start
+								16
+								31
+							
+							
+								tzc_rom0_r1_end
+								0
+								15
+							
+						
+					
+					
+						tzc_rom1_r0
+						tzc_rom1_r0.
+						0x4C
+						
+							
+								tzc_rom1_r0_start
+								16
+								31
+							
+							
+								tzc_rom1_r0_end
+								0
+								15
+							
+						
+					
+					
+						tzc_rom1_r1
+						tzc_rom1_r1.
+						0x50
+						
+							
+								tzc_rom1_r1_start
+								16
+								31
+							
+							
+								tzc_rom1_r1_end
+								0
+								15
+							
+						
+					
+				
+			
+			
+				ef_data_0
+				ef_data_0.
+				0x40007000
+				ef_data_0
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						ef_cfg_0
+						ef_cfg_0.
+						0x0
+						
+							
+								ef_dbg_mode
+								28
+								31
+							
+							
+								ef_dbg_jtag_0_dis
+								26
+								27
+							
+							
+								ef_dbg_jtag_1_dis
+								24
+								25
+							
+							
+								ef_efuse_dbg_dis
+								23
+								23
+							
+							
+								ef_se_dbg_dis
+								22
+								22
+							
+							
+								ef_cpu_rst_dbg_dis
+								21
+								21
+							
+							
+								ef_cpu1_dis
+								20
+								20
+							
+							
+								ef_sf_dis
+								19
+								19
+							
+							
+								ef_cam_dis
+								18
+								18
+							
+							
+								ef_0_key_enc_en
+								17
+								17
+							
+							
+								ef_wifi_dis
+								16
+								16
+							
+							
+								ef_ble_dis
+								15
+								15
+							
+							
+								ef_sdu_dis
+								14
+								14
+							
+							
+								ef_sf_key_0_sel
+								12
+								13
+							
+							
+								ef_boot_sel
+								8
+								11
+							
+							
+								ef_cpu0_enc_en
+								7
+								7
+							
+							
+								ef_cpu1_enc_en
+								6
+								6
+							
+							
+								ef_sboot_en
+								4
+								5
+							
+							
+								ef_sboot_sign_mode
+								2
+								3
+							
+							
+								ef_sf_aes_mode
+								0
+								1
+							
+						
+					
+					
+						ef_dbg_pwd_low
+						ef_dbg_pwd_low.
+						0x4
+						
+							
+								ef_dbg_pwd_low
+								0
+								31
+							
+						
+					
+					
+						ef_dbg_pwd_high
+						ef_dbg_pwd_high.
+						0x8
+						
+							
+								ef_dbg_pwd_high
+								0
+								31
+							
+						
+					
+					
+						ef_ana_trim_0
+						ef_ana_trim_0.
+						0xC
+						
+							
+								ef_ana_trim_0
+								0
+								31
+							
+						
+					
+					
+						ef_sw_usage_0
+						ef_sw_usage_0.
+						0x10
+						
+							
+								ef_sw_usage_0
+								0
+								31
+							
+						
+					
+					
+						ef_wifi_mac_low
+						ef_wifi_mac_low.
+						0x14
+						
+							
+								ef_wifi_mac_low
+								0
+								31
+							
+						
+					
+					
+						ef_wifi_mac_high
+						ef_wifi_mac_high.
+						0x18
+						
+							
+								ef_wifi_mac_high
+								0
+								31
+							
+						
+					
+					
+						ef_key_slot_0_w0
+						ef_key_slot_0_w0.
+						0x1C
+						
+							
+								ef_key_slot_0_w0
+								0
+								31
+							
+						
+					
+					
+						ef_key_slot_0_w1
+						ef_key_slot_0_w1.
+						0x20
+						
+							
+								ef_key_slot_0_w1
+								0
+								31
+							
+						
+					
+					
+						ef_key_slot_0_w2
+						ef_key_slot_0_w2.
+						0x24
+						
+							
+								ef_key_slot_0_w2
+								0
+								31
+							
+						
+					
+					
+						ef_key_slot_0_w3
+						ef_key_slot_0_w3.
+						0x28
+						
+							
+								ef_key_slot_0_w3
+								0
+								31
+							
+						
+					
+					
+						ef_key_slot_1_w0
+						ef_key_slot_1_w0.
+						0x2C
+						
+							
+								ef_key_slot_1_w0
+								0
+								31
+							
+						
+					
+					
+						ef_key_slot_1_w1
+						ef_key_slot_1_w1.
+						0x30
+						
+							
+								ef_key_slot_1_w1
+								0
+								31
+							
+						
+					
+					
+						ef_key_slot_1_w2
+						ef_key_slot_1_w2.
+						0x34
+						
+							
+								ef_key_slot_1_w2
+								0
+								31
+							
+						
+					
+					
+						ef_key_slot_1_w3
+						ef_key_slot_1_w3.
+						0x38
+						
+							
+								ef_key_slot_1_w3
+								0
+								31
+							
+						
+					
+					
+						ef_key_slot_2_w0
+						ef_key_slot_2_w0.
+						0x3C
+						
+							
+								ef_key_slot_2_w0
+								0
+								31
+							
+						
+					
+					
+						ef_key_slot_2_w1
+						ef_key_slot_2_w1.
+						0x40
+						
+							
+								ef_key_slot_2_w1
+								0
+								31
+							
+						
+					
+					
+						ef_key_slot_2_w2
+						ef_key_slot_2_w2.
+						0x44
+						
+							
+								ef_key_slot_2_w2
+								0
+								31
+							
+						
+					
+					
+						ef_key_slot_2_w3
+						ef_key_slot_2_w3.
+						0x48
+						
+							
+								ef_key_slot_2_w3
+								0
+								31
+							
+						
+					
+					
+						ef_key_slot_3_w0
+						ef_key_slot_3_w0.
+						0x4C
+						
+							
+								ef_key_slot_3_w0
+								0
+								31
+							
+						
+					
+					
+						ef_key_slot_3_w1
+						ef_key_slot_3_w1.
+						0x50
+						
+							
+								ef_key_slot_3_w1
+								0
+								31
+							
+						
+					
+					
+						ef_key_slot_3_w2
+						ef_key_slot_3_w2.
+						0x54
+						
+							
+								ef_key_slot_3_w2
+								0
+								31
+							
+						
+					
+					
+						ef_key_slot_3_w3
+						ef_key_slot_3_w3.
+						0x58
+						
+							
+								ef_key_slot_3_w3
+								0
+								31
+							
+						
+					
+					
+						ef_key_slot_4_w0
+						ef_key_slot_4_w0.
+						0x5C
+						
+							
+								ef_key_slot_4_w0
+								0
+								31
+							
+						
+					
+					
+						ef_key_slot_4_w1
+						ef_key_slot_4_w1.
+						0x60
+						
+							
+								ef_key_slot_4_w1
+								0
+								31
+							
+						
+					
+					
+						ef_key_slot_4_w2
+						ef_key_slot_4_w2.
+						0x64
+						
+							
+								ef_key_slot_4_w2
+								0
+								31
+							
+						
+					
+					
+						ef_key_slot_4_w3
+						ef_key_slot_4_w3.
+						0x68
+						
+							
+								ef_key_slot_4_w3
+								0
+								31
+							
+						
+					
+					
+						ef_key_slot_5_w0
+						ef_key_slot_5_w0.
+						0x6C
+						
+							
+								ef_key_slot_5_w0
+								0
+								31
+							
+						
+					
+					
+						ef_key_slot_5_w1
+						ef_key_slot_5_w1.
+						0x70
+						
+							
+								ef_key_slot_5_w1
+								0
+								31
+							
+						
+					
+					
+						ef_key_slot_5_w2
+						ef_key_slot_5_w2.
+						0x74
+						
+							
+								ef_key_slot_5_w2
+								0
+								31
+							
+						
+					
+					
+						ef_key_slot_5_w3
+						ef_key_slot_5_w3.
+						0x78
+						
+							
+								ef_key_slot_5_w3
+								0
+								31
+							
+						
+					
+					
+						ef_data_0_lock
+						ef_data_0_lock.
+						0x7C
+						
+							
+								rd_lock_key_slot_5
+								31
+								31
+							
+							
+								rd_lock_key_slot_4
+								30
+								30
+							
+							
+								rd_lock_key_slot_3
+								29
+								29
+							
+							
+								rd_lock_key_slot_2
+								28
+								28
+							
+							
+								rd_lock_key_slot_1
+								27
+								27
+							
+							
+								rd_lock_key_slot_0
+								26
+								26
+							
+							
+								rd_lock_dbg_pwd
+								25
+								25
+							
+							
+								wr_lock_key_slot_5_h
+								24
+								24
+							
+							
+								wr_lock_key_slot_4_h
+								23
+								23
+							
+							
+								wr_lock_key_slot_3
+								22
+								22
+							
+							
+								wr_lock_key_slot_2
+								21
+								21
+							
+							
+								wr_lock_key_slot_1
+								20
+								20
+							
+							
+								wr_lock_key_slot_0
+								19
+								19
+							
+							
+								wr_lock_wifi_mac
+								18
+								18
+							
+							
+								wr_lock_sw_usage_0
+								17
+								17
+							
+							
+								wr_lock_dbg_pwd
+								16
+								16
+							
+							
+								wr_lock_boot_mode
+								15
+								15
+							
+							
+								wr_lock_key_slot_5_l
+								14
+								14
+							
+							
+								wr_lock_key_slot_4_l
+								13
+								13
+							
+							
+								ef_ana_trim_1
+								0
+								12
+							
+						
+					
+				
+			
+			
+				ef_data_1
+				ef_data_1.
+				0x40007000
+				ef_data_1
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						reg_key_slot_6_w0
+						reg_key_slot_6_w0.
+						0x80
+						
+							
+								reg_key_slot_6_w0
+								0
+								31
+							
+						
+					
+					
+						reg_key_slot_6_w1
+						reg_key_slot_6_w1.
+						0x84
+						
+							
+								reg_key_slot_6_w1
+								0
+								31
+							
+						
+					
+					
+						reg_key_slot_6_w2
+						reg_key_slot_6_w2.
+						0x88
+						
+							
+								reg_key_slot_6_w2
+								0
+								31
+							
+						
+					
+					
+						reg_key_slot_6_w3
+						reg_key_slot_6_w3.
+						0x8C
+						
+							
+								reg_key_slot_6_w3
+								0
+								31
+							
+						
+					
+					
+						reg_key_slot_7_w0
+						reg_key_slot_7_w0.
+						0x90
+						
+							
+								reg_key_slot_7_w0
+								0
+								31
+							
+						
+					
+					
+						reg_key_slot_7_w1
+						reg_key_slot_7_w1.
+						0x94
+						
+							
+								reg_key_slot_7_w1
+								0
+								31
+							
+						
+					
+					
+						reg_key_slot_7_w2
+						reg_key_slot_7_w2.
+						0x98
+						
+							
+								reg_key_slot_7_w2
+								0
+								31
+							
+						
+					
+					
+						reg_key_slot_7_w3
+						reg_key_slot_7_w3.
+						0x9C
+						
+							
+								reg_key_slot_7_w3
+								0
+								31
+							
+						
+					
+					
+						reg_key_slot_8_w0
+						reg_key_slot_8_w0.
+						0xA0
+						
+							
+								reg_key_slot_8_w0
+								0
+								31
+							
+						
+					
+					
+						reg_key_slot_8_w1
+						reg_key_slot_8_w1.
+						0xA4
+						
+							
+								reg_key_slot_8_w1
+								0
+								31
+							
+						
+					
+					
+						reg_key_slot_8_w2
+						reg_key_slot_8_w2.
+						0xA8
+						
+							
+								reg_key_slot_8_w2
+								0
+								31
+							
+						
+					
+					
+						reg_key_slot_8_w3
+						reg_key_slot_8_w3.
+						0xAC
+						
+							
+								reg_key_slot_8_w3
+								0
+								31
+							
+						
+					
+					
+						reg_key_slot_9_w0
+						reg_key_slot_9_w0.
+						0xB0
+						
+							
+								reg_key_slot_9_w0
+								0
+								31
+							
+						
+					
+					
+						reg_key_slot_9_w1
+						reg_key_slot_9_w1.
+						0xB4
+						
+							
+								reg_key_slot_9_w1
+								0
+								31
+							
+						
+					
+					
+						reg_key_slot_9_w2
+						reg_key_slot_9_w2.
+						0xB8
+						
+							
+								reg_key_slot_9_w2
+								0
+								31
+							
+						
+					
+					
+						reg_key_slot_9_w3
+						reg_key_slot_9_w3.
+						0xBC
+						
+							
+								reg_key_slot_9_w3
+								0
+								31
+							
+						
+					
+					
+						reg_key_slot_10_w0
+						reg_key_slot_10_w0.
+						0xC0
+						
+					
+					
+						reg_key_slot_10_w1
+						reg_key_slot_10_w1.
+						0xC4
+						
+					
+					
+						reg_key_slot_10_w2
+						reg_key_slot_10_w2.
+						0xC8
+						
+					
+					
+						reg_key_slot_10_w3
+						reg_key_slot_10_w3.
+						0xCC
+						
+					
+					
+						reg_key_slot_11_w0
+						reg_key_slot_11_w0.
+						0xD0
+						
+					
+					
+						reg_key_slot_11_w1
+						reg_key_slot_11_w1.
+						0xD4
+						
+					
+					
+						reg_key_slot_11_w2
+						reg_key_slot_11_w2.
+						0xD8
+						
+					
+					
+						reg_key_slot_11_w3
+						reg_key_slot_11_w3.
+						0xDC
+						
+					
+					
+						reg_data_1_lock
+						reg_data_1_lock.
+						0xE0
+						
+							
+								rd_lock_key_slot_9
+								29
+								29
+							
+							
+								rd_lock_key_slot_8
+								28
+								28
+							
+							
+								rd_lock_key_slot_7
+								27
+								27
+							
+							
+								rd_lock_key_slot_6
+								26
+								26
+							
+							
+								RESERVED_25_16
+								16
+								25
+							
+							
+								wr_lock_key_slot_9
+								13
+								13
+							
+							
+								wr_lock_key_slot_8
+								12
+								12
+							
+							
+								wr_lock_key_slot_7
+								11
+								11
+							
+							
+								wr_lock_key_slot_6
+								10
+								10
+							
+							
+								RESERVED_9_0
+								0
+								9
+							
+						
+					
+				
+			
+			
+				ef_ctrl
+				ef_ctrl.
+				0x40007000
+				ef_ctrl
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						ef_if_ctrl_0
+						ef_if_ctrl_0.
+						0x800
+						
+							
+								ef_if_prot_code_cyc
+								24
+								31
+							
+							
+								ef_if_0_int_set
+								22
+								22
+							
+							
+								ef_if_0_int_clr
+								21
+								21
+							
+							
+								ef_if_0_int
+								20
+								20
+							
+							
+								ef_if_cyc_modify_lock
+								19
+								19
+							
+							
+								ef_if_auto_rd_en
+								18
+								18
+							
+							
+								ef_clk_sahb_data_gate
+								17
+								17
+							
+							
+								ef_if_por_dig
+								16
+								16
+							
+							
+								ef_if_prot_code_ctrl
+								8
+								15
+							
+							
+								ef_clk_sahb_data_sel
+								7
+								7
+							
+							
+								ef_if_0_cyc_modify
+								6
+								6
+							
+							
+								ef_if_0_manual_en
+								5
+								5
+							
+							
+								ef_if_0_trig
+								4
+								4
+							
+							
+								ef_if_0_rw
+								3
+								3
+							
+							
+								ef_if_0_busy
+								2
+								2
+							
+							
+								ef_if_0_autoload_done
+								1
+								1
+							
+							
+								ef_if_0_autoload_p1_done
+								0
+								0
+							
+						
+					
+					
+						ef_if_cyc_0
+						ef_if_cyc_0.
+						0x804
+						
+							
+								ef_if_cyc_pd_cs_s
+								24
+								31
+							
+							
+								ef_if_cyc_cs
+								18
+								23
+							
+							
+								ef_if_cyc_rd_adr
+								12
+								17
+							
+							
+								ef_if_cyc_rd_dat
+								6
+								11
+							
+							
+								ef_if_cyc_rd_dmy
+								0
+								5
+							
+						
+					
+					
+						ef_if_cyc_1
+						ef_if_cyc_1.
+						0x808
+						
+							
+								ef_if_cyc_pd_cs_h
+								26
+								31
+							
+							
+								ef_if_cyc_ps_cs
+								20
+								25
+							
+							
+								ef_if_cyc_wr_adr
+								14
+								19
+							
+							
+								ef_if_cyc_pp
+								6
+								13
+							
+							
+								ef_if_cyc_pi
+								0
+								5
+							
+						
+					
+					
+						ef_if_0_manual
+						ef_if_0_manual.
+						0x80C
+						
+							
+								ef_if_prot_code_manual
+								24
+								31
+							
+							
+								ef_if_0_q
+								16
+								23
+							
+							
+								ef_if_csb
+								15
+								15
+							
+							
+								ef_if_load
+								14
+								14
+							
+							
+								ef_if_pgenb
+								13
+								13
+							
+							
+								ef_if_strobe
+								12
+								12
+							
+							
+								ef_if_ps
+								11
+								11
+							
+							
+								ef_if_pd
+								10
+								10
+							
+							
+								ef_if_a
+								0
+								9
+							
+						
+					
+					
+						ef_if_0_status
+						ef_if_0_status.
+						0x810
+						
+							
+								ef_if_0_status
+								0
+								31
+							
+						
+					
+					
+						ef_if_cfg_0
+						ef_if_cfg_0.
+						0x814
+						
+							
+								ef_if_dbg_mode
+								28
+								31
+							
+							
+								ef_if_dbg_jtag_0_dis
+								26
+								27
+							
+							
+								ef_if_dbg_jtag_1_dis
+								24
+								25
+							
+							
+								ef_if_efuse_dbg_dis
+								23
+								23
+							
+							
+								ef_if_se_dbg_dis
+								22
+								22
+							
+							
+								ef_if_cpu_rst_dbg_dis
+								21
+								21
+							
+							
+								ef_if_cpu1_dis
+								20
+								20
+							
+							
+								ef_if_sf_dis
+								19
+								19
+							
+							
+								ef_if_cam_dis
+								18
+								18
+							
+							
+								ef_if_0_key_enc_en
+								17
+								17
+							
+							
+								ef_if_wifi_dis
+								16
+								16
+							
+							
+								ef_if_ble_dis
+								15
+								15
+							
+							
+								ef_if_sdu_dis
+								14
+								14
+							
+							
+								ef_if_sf_key_0_sel
+								12
+								13
+							
+							
+								ef_if_boot_sel
+								8
+								11
+							
+							
+								ef_if_cpu0_enc_en
+								7
+								7
+							
+							
+								ef_if_cpu1_enc_en
+								6
+								6
+							
+							
+								ef_if_sboot_en
+								4
+								5
+							
+							
+								ef_if_sboot_sign_mode
+								2
+								3
+							
+							
+								ef_if_sf_aes_mode
+								0
+								1
+							
+						
+					
+					
+						ef_sw_cfg_0
+						ef_sw_cfg_0.
+						0x818
+						
+							
+								ef_sw_dbg_mode
+								28
+								31
+							
+							
+								ef_sw_dbg_jtag_0_dis
+								26
+								27
+							
+							
+								ef_sw_dbg_jtag_1_dis
+								24
+								25
+							
+							
+								ef_sw_efuse_dbg_dis
+								23
+								23
+							
+							
+								ef_sw_se_dbg_dis
+								22
+								22
+							
+							
+								ef_sw_cpu_rst_dbg_dis
+								21
+								21
+							
+							
+								ef_sw_cpu1_dis
+								20
+								20
+							
+							
+								ef_sw_sf_dis
+								19
+								19
+							
+							
+								ef_sw_cam_dis
+								18
+								18
+							
+							
+								ef_sw_0_key_enc_en
+								17
+								17
+							
+							
+								ef_sw_wifi_dis
+								16
+								16
+							
+							
+								ef_sw_ble_dis
+								15
+								15
+							
+							
+								ef_sw_sdu_dis
+								14
+								14
+							
+							
+								ef_sw_sf_key_0_sel
+								12
+								13
+							
+							
+								ef_sw_cpu0_enc_en
+								7
+								7
+							
+							
+								ef_sw_cpu1_enc_en
+								6
+								6
+							
+							
+								ef_sw_sboot_en
+								4
+								5
+							
+							
+								ef_sw_sboot_sign_mode
+								2
+								3
+							
+							
+								ef_sw_sf_aes_mode
+								0
+								1
+							
+						
+					
+					
+						ef_reserved
+						ef_reserved.
+						0x81C
+						
+							
+								ef_reserved
+								0
+								31
+							
+						
+					
+					
+						ef_if_ana_trim_0
+						ef_if_ana_trim_0.
+						0x820
+						
+							
+								ef_if_ana_trim_0
+								0
+								31
+							
+						
+					
+					
+						ef_if_sw_usage_0
+						ef_if_sw_usage_0.
+						0x824
+						
+							
+								ef_if_sw_usage_0
+								0
+								31
+							
+						
+					
+					
+						ef_crc_ctrl_0
+						ef_crc_ctrl_0.
+						0xA00
+						
+							
+								ef_crc_slp_n
+								16
+								31
+							
+							
+								ef_crc_lock
+								11
+								11
+							
+							
+								ef_crc_int_set
+								10
+								10
+							
+							
+								ef_crc_int_clr
+								9
+								9
+							
+							
+								ef_crc_int
+								8
+								8
+							
+							
+								ef_crc_din_endian
+								7
+								7
+							
+							
+								ef_crc_dout_endian
+								6
+								6
+							
+							
+								ef_crc_dout_inv_en
+								5
+								5
+							
+							
+								ef_crc_error
+								4
+								4
+							
+							
+								ef_crc_mode
+								3
+								3
+							
+							
+								ef_crc_en
+								2
+								2
+							
+							
+								ef_crc_trig
+								1
+								1
+							
+							
+								ef_crc_busy
+								0
+								0
+							
+						
+					
+					
+						ef_crc_ctrl_1
+						ef_crc_ctrl_1.
+						0xA04
+						
+							
+								ef_crc_data_0_en
+								0
+								31
+							
+						
+					
+					
+						ef_crc_ctrl_2
+						ef_crc_ctrl_2.
+						0xA08
+						
+							
+								ef_crc_data_1_en
+								0
+								31
+							
+						
+					
+					
+						ef_crc_ctrl_3
+						ef_crc_ctrl_3.
+						0xA0C
+						
+							
+								ef_crc_iv
+								0
+								31
+							
+						
+					
+					
+						ef_crc_ctrl_4
+						ef_crc_ctrl_4.
+						0xA10
+						
+							
+								ef_crc_golden
+								0
+								31
+							
+						
+					
+					
+						ef_crc_ctrl_5
+						ef_crc_ctrl_5.
+						0xA14
+						
+							
+								ef_crc_dout
+								0
+								31
+							
+						
+					
+				
+			
+			
+				cci
+				cci.
+				0x40008000
+				cci
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						cci_cfg
+						cci_cfg.
+						0x0
+						
+							
+								reg_mcci_clk_inv
+								9
+								9
+							
+							
+								reg_scci_clk_inv
+								8
+								8
+							
+							
+								cfg_cci1_pre_read
+								7
+								7
+							
+							
+								reg_div_m_cci_sclk
+								5
+								6
+							
+							
+								reg_m_cci_sclk_en
+								4
+								4
+							
+							
+								cci_mas_hw_mode
+								3
+								3
+							
+							
+								cci_mas_sel_cci2
+								2
+								2
+							
+							
+								cci_slv_sel_cci2
+								1
+								1
+							
+							
+								cci_en
+								0
+								0
+							
+						
+					
+					
+						cci_addr
+						cci_addr.
+						0x4
+						
+							
+								apb_cci_addr
+								0
+								31
+							
+						
+					
+					
+						cci_wdata
+						cci_wdata.
+						0x8
+						
+							
+								apb_cci_wdata
+								0
+								31
+							
+						
+					
+					
+						cci_rdata
+						cci_rdata.
+						0xC
+						
+							
+								apb_cci_rdata
+								0
+								31
+							
+						
+					
+					
+						cci_ctl
+						cci_ctl.
+						0x10
+						
+							
+								ahb_state
+								2
+								3
+							
+							
+								cci_read_flag
+								1
+								1
+							
+							
+								cci_write_flag
+								0
+								0
+							
+						
+					
+				
+			
+			
+				l1c
+				l1c.
+				0x40009000
+				l1c
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						l1c_config
+						l1c_config.
+						0x0
+						
+							
+								reserved_31_30
+								30
+								31
+							
+							
+								l1c_flush_done
+								29
+								29
+							
+							
+								l1c_flush_en
+								28
+								28
+							
+							
+								wrap_dis
+								26
+								26
+							
+							
+								early_resp_dis
+								25
+								25
+							
+							
+								l1c_bmx_busy_option_dis
+								24
+								24
+							
+							
+								l1c_bmx_timeout_en
+								20
+								23
+							
+							
+								l1c_bmx_arb_mode
+								16
+								17
+							
+							
+								l1c_bmx_err_en
+								15
+								15
+							
+							
+								l1c_bypass
+								14
+								14
+							
+							
+								irom_2t_access
+								12
+								12
+							
+							
+								l1c_way_dis
+								8
+								11
+							
+							
+								l1c_wa_en
+								6
+								6
+							
+							
+								l1c_wb_en
+								5
+								5
+							
+							
+								l1c_wt_en
+								4
+								4
+							
+							
+								l1c_invalid_done
+								3
+								3
+							
+							
+								l1c_invalid_en
+								2
+								2
+							
+							
+								l1c_cnt_en
+								1
+								1
+							
+							
+								l1c_cacheable
+								0
+								0
+							
+						
+					
+					
+						hit_cnt_lsb
+						hit_cnt_lsb.
+						0x4
+						
+							
+								hit_cnt_lsb
+								0
+								31
+							
+						
+					
+					
+						hit_cnt_msb
+						hit_cnt_msb.
+						0x8
+						
+							
+								hit_cnt_msb
+								0
+								31
+							
+						
+					
+					
+						miss_cnt
+						miss_cnt.
+						0xC
+						
+							
+								miss_cnt
+								0
+								31
+							
+						
+					
+					
+						l1c_misc
+						l1c_misc.
+						0x10
+						
+							
+								l1c_fsm
+								28
+								30
+							
+						
+					
+					
+						l1c_bmx_err_addr_en
+						l1c_bmx_err_addr_en.
+						0x200
+						
+							
+								l1c_hsel_option
+								16
+								19
+							
+							
+								l1c_bmx_err_tz
+								5
+								5
+							
+							
+								l1c_bmx_err_dec
+								4
+								4
+							
+							
+								l1c_bmx_err_addr_dis
+								0
+								0
+							
+						
+					
+					
+						l1c_bmx_err_addr
+						l1c_bmx_err_addr.
+						0x204
+						
+							
+								l1c_bmx_err_addr
+								0
+								31
+							
+						
+					
+					
+						irom1_misr_dataout_0
+						irom1_misr_dataout_0.
+						0x208
+						
+							
+								irom1_misr_dataout_0
+								0
+								31
+							
+						
+					
+					
+						irom1_misr_dataout_1
+						irom1_misr_dataout_1.
+						0x20C
+						
+							
+								irom1_misr_dataout_1
+								0
+								31
+							
+						
+					
+					
+						cpu_clk_gate
+						cpu_clk_gate.
+						0x210
+						
+							
+								force_e21_clock_on_2
+								2
+								2
+							
+							
+								force_e21_clock_on_1
+								1
+								1
+							
+							
+								force_e21_clock_on_0
+								0
+								0
+							
+						
+					
+				
+			
+			
+				uart
+				uart.
+				0x4000A000
+				uart
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						utx_config
+						utx_config.
+						0x0
+						
+							
+								cr_utx_len
+								16
+								31
+							
+							
+								cr_utx_bit_cnt_b
+								13
+								15
+							
+							
+								cr_utx_bit_cnt_p
+								11
+								12
+							
+							
+								cr_utx_bit_cnt_d
+								8
+								10
+							
+							
+								cr_utx_ir_inv
+								7
+								7
+							
+							
+								cr_utx_ir_en
+								6
+								6
+							
+							
+								cr_utx_prt_sel
+								5
+								5
+							
+							
+								cr_utx_prt_en
+								4
+								4
+							
+							
+								cr_utx_lin_en
+								3
+								3
+							
+							
+								cr_utx_frm_en
+								2
+								2
+							
+							
+								cr_utx_cts_en
+								1
+								1
+							
+							
+								cr_utx_en
+								0
+								0
+							
+						
+					
+					
+						urx_config
+						urx_config.
+						0x4
+						
+							
+								cr_urx_len
+								16
+								31
+							
+							
+								cr_urx_deg_cnt
+								12
+								15
+							
+							
+								cr_urx_deg_en
+								11
+								11
+							
+							
+								cr_urx_bit_cnt_d
+								8
+								10
+							
+							
+								cr_urx_ir_inv
+								7
+								7
+							
+							
+								cr_urx_ir_en
+								6
+								6
+							
+							
+								cr_urx_prt_sel
+								5
+								5
+							
+							
+								cr_urx_prt_en
+								4
+								4
+							
+							
+								cr_urx_lin_en
+								3
+								3
+							
+							
+								cr_urx_abr_en
+								1
+								1
+							
+							
+								cr_urx_en
+								0
+								0
+							
+						
+					
+					
+						uart_bit_prd
+						uart_bit_prd.
+						0x8
+						
+							
+								cr_urx_bit_prd
+								16
+								31
+							
+							
+								cr_utx_bit_prd
+								0
+								15
+							
+						
+					
+					
+						data_config
+						data_config.
+						0xC
+						
+							
+								cr_uart_bit_inv
+								0
+								0
+							
+						
+					
+					
+						utx_ir_position
+						utx_ir_position.
+						0x10
+						
+							
+								cr_utx_ir_pos_p
+								16
+								31
+							
+							
+								cr_utx_ir_pos_s
+								0
+								15
+							
+						
+					
+					
+						urx_ir_position
+						urx_ir_position.
+						0x14
+						
+							
+								cr_urx_ir_pos_s
+								0
+								15
+							
+						
+					
+					
+						urx_rto_timer
+						urx_rto_timer.
+						0x18
+						
+							
+								cr_urx_rto_value
+								0
+								7
+							
+						
+					
+					
+						uart_sw_mode
+						uart_sw_mode.
+						0x1C
+						
+							
+								cr_urx_rts_sw_val
+								3
+								3
+							
+							
+								cr_urx_rts_sw_mode
+								2
+								2
+							
+							
+								cr_utx_txd_sw_val
+								1
+								1
+							
+							
+								cr_utx_txd_sw_mode
+								0
+								0
+							
+						
+					
+					
+						uart_int_sts
+						UART interrupt status
+						0x20
+						
+							
+								urx_lse_int
+								8
+								8
+							
+							
+								urx_fer_int
+								7
+								7
+							
+							
+								utx_fer_int
+								6
+								6
+							
+							
+								urx_pce_int
+								5
+								5
+							
+							
+								urx_rto_int
+								4
+								4
+							
+							
+								urx_fifo_int
+								3
+								3
+							
+							
+								utx_fifo_int
+								2
+								2
+							
+							
+								urx_end_int
+								1
+								1
+							
+							
+								utx_end_int
+								0
+								0
+							
+						
+					
+					
+						uart_int_mask
+						UART interrupt mask
+						0x24
+						
+							
+								cr_urx_lse_mask
+								8
+								8
+							
+							
+								cr_urx_fer_mask
+								7
+								7
+							
+							
+								cr_utx_fer_mask
+								6
+								6
+							
+							
+								cr_urx_pce_mask
+								5
+								5
+							
+							
+								cr_urx_rto_mask
+								4
+								4
+							
+							
+								cr_urx_fifo_mask
+								3
+								3
+							
+							
+								cr_utx_fifo_mask
+								2
+								2
+							
+							
+								cr_urx_end_mask
+								1
+								1
+							
+							
+								cr_utx_end_mask
+								0
+								0
+							
+						
+					
+					
+						uart_int_clear
+						UART interrupt clear
+						0x28
+						
+							
+								cr_urx_lse_clr
+								8
+								8
+							
+							
+								rsvd_7
+								7
+								7
+							
+							
+								rsvd_6
+								6
+								6
+							
+							
+								cr_urx_pce_clr
+								5
+								5
+							
+							
+								cr_urx_rto_clr
+								4
+								4
+							
+							
+								rsvd_3
+								3
+								3
+							
+							
+								rsvd_2
+								2
+								2
+							
+							
+								cr_urx_end_clr
+								1
+								1
+							
+							
+								cr_utx_end_clr
+								0
+								0
+							
+						
+					
+					
+						uart_int_en
+						UART interrupt enable
+						0x2C
+						
+							
+								cr_urx_lse_en
+								8
+								8
+							
+							
+								cr_urx_fer_en
+								7
+								7
+							
+							
+								cr_utx_fer_en
+								6
+								6
+							
+							
+								cr_urx_pce_en
+								5
+								5
+							
+							
+								cr_urx_rto_en
+								4
+								4
+							
+							
+								cr_urx_fifo_en
+								3
+								3
+							
+							
+								cr_utx_fifo_en
+								2
+								2
+							
+							
+								cr_urx_end_en
+								1
+								1
+							
+							
+								cr_utx_end_en
+								0
+								0
+							
+						
+					
+					
+						uart_status
+						uart_status.
+						0x30
+						
+							
+								sts_urx_bus_busy
+								1
+								1
+							
+							
+								sts_utx_bus_busy
+								0
+								0
+							
+						
+					
+					
+						sts_urx_abr_prd
+						sts_urx_abr_prd.
+						0x34
+						
+							
+								sts_urx_abr_prd_0x55
+								16
+								31
+							
+							
+								sts_urx_abr_prd_start
+								0
+								15
+							
+						
+					
+					
+						uart_fifo_config_0
+						uart_fifo_config_0.
+						0x80
+						
+							
+								rx_fifo_underflow
+								7
+								7
+							
+							
+								rx_fifo_overflow
+								6
+								6
+							
+							
+								tx_fifo_underflow
+								5
+								5
+							
+							
+								tx_fifo_overflow
+								4
+								4
+							
+							
+								rx_fifo_clr
+								3
+								3
+							
+							
+								tx_fifo_clr
+								2
+								2
+							
+							
+								uart_dma_rx_en
+								1
+								1
+							
+							
+								uart_dma_tx_en
+								0
+								0
+							
+						
+					
+					
+						uart_fifo_config_1
+						uart_fifo_config_1.
+						0x84
+						
+							
+								rx_fifo_th
+								24
+								30
+							
+							
+								tx_fifo_th
+								16
+								22
+							
+							
+								rx_fifo_cnt
+								8
+								15
+							
+							
+								tx_fifo_cnt
+								0
+								7
+							
+						
+					
+					
+						uart_fifo_wdata
+						uart_fifo_wdata.
+						0x88
+						
+							
+								uart_fifo_wdata
+								0
+								7
+							
+						
+					
+					
+						uart_fifo_rdata
+						uart_fifo_rdata.
+						0x8C
+						
+							
+								uart_fifo_rdata
+								0
+								7
+							
+						
+					
+				
+			
+			
+				spi
+				spi.
+				0x4000A200
+				spi
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						spi_config
+						spi_config.
+						0x0
+						
+							
+								cr_spi_deg_cnt
+								12
+								15
+							
+							
+								cr_spi_deg_en
+								11
+								11
+							
+							
+								cr_spi_m_cont_en
+								9
+								9
+							
+							
+								cr_spi_rxd_ignr_en
+								8
+								8
+							
+							
+								cr_spi_byte_inv
+								7
+								7
+							
+							
+								cr_spi_bit_inv
+								6
+								6
+							
+							
+								cr_spi_sclk_ph
+								5
+								5
+							
+							
+								cr_spi_sclk_pol
+								4
+								4
+							
+							
+								cr_spi_frame_size
+								2
+								3
+							
+							
+								cr_spi_s_en
+								1
+								1
+							
+							
+								cr_spi_m_en
+								0
+								0
+							
+						
+					
+					
+						spi_int_sts
+						spi_int_sts.
+						0x4
+						
+							
+								cr_spi_fer_en
+								29
+								29
+							
+							
+								cr_spi_txu_en
+								28
+								28
+							
+							
+								cr_spi_sto_en
+								27
+								27
+							
+							
+								cr_spi_rxf_en
+								26
+								26
+							
+							
+								cr_spi_txf_en
+								25
+								25
+							
+							
+								cr_spi_end_en
+								24
+								24
+							
+							
+								rsvd_21
+								21
+								21
+							
+							
+								cr_spi_txu_clr
+								20
+								20
+							
+							
+								cr_spi_sto_clr
+								19
+								19
+							
+							
+								rsvd_18
+								18
+								18
+							
+							
+								rsvd_17
+								17
+								17
+							
+							
+								cr_spi_end_clr
+								16
+								16
+							
+							
+								cr_spi_fer_mask
+								13
+								13
+							
+							
+								cr_spi_txu_mask
+								12
+								12
+							
+							
+								cr_spi_sto_mask
+								11
+								11
+							
+							
+								cr_spi_rxf_mask
+								10
+								10
+							
+							
+								cr_spi_txf_mask
+								9
+								9
+							
+							
+								cr_spi_end_mask
+								8
+								8
+							
+							
+								spi_fer_int
+								5
+								5
+							
+							
+								spi_txu_int
+								4
+								4
+							
+							
+								spi_sto_int
+								3
+								3
+							
+							
+								spi_rxf_int
+								2
+								2
+							
+							
+								spi_txf_int
+								1
+								1
+							
+							
+								spi_end_int
+								0
+								0
+							
+						
+					
+					
+						spi_bus_busy
+						spi_bus_busy.
+						0x8
+						
+							
+								sts_spi_bus_busy
+								0
+								0
+							
+						
+					
+					
+						spi_prd_0
+						spi_prd_0.
+						0x10
+						
+							
+								cr_spi_prd_d_ph_1
+								24
+								31
+							
+							
+								cr_spi_prd_d_ph_0
+								16
+								23
+							
+							
+								cr_spi_prd_p
+								8
+								15
+							
+							
+								cr_spi_prd_s
+								0
+								7
+							
+						
+					
+					
+						spi_prd_1
+						spi_prd_1.
+						0x14
+						
+							
+								cr_spi_prd_i
+								0
+								7
+							
+						
+					
+					
+						spi_rxd_ignr
+						spi_rxd_ignr.
+						0x18
+						
+							
+								cr_spi_rxd_ignr_s
+								16
+								20
+							
+							
+								cr_spi_rxd_ignr_p
+								0
+								4
+							
+						
+					
+					
+						spi_sto_value
+						spi_sto_value.
+						0x1C
+						
+							
+								cr_spi_sto_value
+								0
+								11
+							
+						
+					
+					
+						spi_fifo_config_0
+						spi_fifo_config_0.
+						0x80
+						
+							
+								rx_fifo_underflow
+								7
+								7
+							
+							
+								rx_fifo_overflow
+								6
+								6
+							
+							
+								tx_fifo_underflow
+								5
+								5
+							
+							
+								tx_fifo_overflow
+								4
+								4
+							
+							
+								rx_fifo_clr
+								3
+								3
+							
+							
+								tx_fifo_clr
+								2
+								2
+							
+							
+								spi_dma_rx_en
+								1
+								1
+							
+							
+								spi_dma_tx_en
+								0
+								0
+							
+						
+					
+					
+						spi_fifo_config_1
+						spi_fifo_config_1.
+						0x84
+						
+							
+								rx_fifo_th
+								24
+								25
+							
+							
+								tx_fifo_th
+								16
+								17
+							
+							
+								rx_fifo_cnt
+								8
+								10
+							
+							
+								tx_fifo_cnt
+								0
+								2
+							
+						
+					
+					
+						spi_fifo_wdata
+						spi_fifo_wdata.
+						0x88
+						
+							
+								spi_fifo_wdata
+								0
+								31
+							
+						
+					
+					
+						spi_fifo_rdata
+						spi_fifo_rdata.
+						0x8C
+						
+							
+								spi_fifo_rdata
+								0
+								31
+							
+						
+					
+				
+			
+			
+				i2c
+				i2c.
+				0x4000A300
+				i2c
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						i2c_config
+						i2c_config.
+						0x0
+						
+							
+								cr_i2c_deg_cnt
+								28
+								31
+							
+							
+								cr_i2c_pkt_len
+								16
+								23
+							
+							
+								cr_i2c_slv_addr
+								8
+								14
+							
+							
+								cr_i2c_sub_addr_bc
+								5
+								6
+							
+							
+								cr_i2c_sub_addr_en
+								4
+								4
+							
+							
+								cr_i2c_scl_sync_en
+								3
+								3
+							
+							
+								cr_i2c_deg_en
+								2
+								2
+							
+							
+								cr_i2c_pkt_dir
+								1
+								1
+							
+							
+								cr_i2c_m_en
+								0
+								0
+							
+						
+					
+					
+						i2c_int_sts
+						i2c_int_sts.
+						0x4
+						
+							
+								cr_i2c_fer_en
+								29
+								29
+							
+							
+								cr_i2c_arb_en
+								28
+								28
+							
+							
+								cr_i2c_nak_en
+								27
+								27
+							
+							
+								cr_i2c_rxf_en
+								26
+								26
+							
+							
+								cr_i2c_txf_en
+								25
+								25
+							
+							
+								cr_i2c_end_en
+								24
+								24
+							
+							
+								rsvd_21
+								21
+								21
+							
+							
+								cr_i2c_arb_clr
+								20
+								20
+							
+							
+								cr_i2c_nak_clr
+								19
+								19
+							
+							
+								rsvd_18
+								18
+								18
+							
+							
+								rsvd_17
+								17
+								17
+							
+							
+								cr_i2c_end_clr
+								16
+								16
+							
+							
+								cr_i2c_fer_mask
+								13
+								13
+							
+							
+								cr_i2c_arb_mask
+								12
+								12
+							
+							
+								cr_i2c_nak_mask
+								11
+								11
+							
+							
+								cr_i2c_rxf_mask
+								10
+								10
+							
+							
+								cr_i2c_txf_mask
+								9
+								9
+							
+							
+								cr_i2c_end_mask
+								8
+								8
+							
+							
+								i2c_fer_int
+								5
+								5
+							
+							
+								i2c_arb_int
+								4
+								4
+							
+							
+								i2c_nak_int
+								3
+								3
+							
+							
+								i2c_rxf_int
+								2
+								2
+							
+							
+								i2c_txf_int
+								1
+								1
+							
+							
+								i2c_end_int
+								0
+								0
+							
+						
+					
+					
+						i2c_sub_addr
+						i2c_sub_addr.
+						0x8
+						
+							
+								cr_i2c_sub_addr_b3
+								24
+								31
+							
+							
+								cr_i2c_sub_addr_b2
+								16
+								23
+							
+							
+								cr_i2c_sub_addr_b1
+								8
+								15
+							
+							
+								cr_i2c_sub_addr_b0
+								0
+								7
+							
+						
+					
+					
+						i2c_bus_busy
+						i2c_bus_busy.
+						0xC
+						
+							
+								cr_i2c_bus_busy_clr
+								1
+								1
+							
+							
+								sts_i2c_bus_busy
+								0
+								0
+							
+						
+					
+					
+						i2c_prd_start
+						i2c_prd_start.
+						0x10
+						
+							
+								cr_i2c_prd_s_ph_3
+								24
+								31
+							
+							
+								cr_i2c_prd_s_ph_2
+								16
+								23
+							
+							
+								cr_i2c_prd_s_ph_1
+								8
+								15
+							
+							
+								cr_i2c_prd_s_ph_0
+								0
+								7
+							
+						
+					
+					
+						i2c_prd_stop
+						i2c_prd_stop.
+						0x14
+						
+							
+								cr_i2c_prd_p_ph_3
+								24
+								31
+							
+							
+								cr_i2c_prd_p_ph_2
+								16
+								23
+							
+							
+								cr_i2c_prd_p_ph_1
+								8
+								15
+							
+							
+								cr_i2c_prd_p_ph_0
+								0
+								7
+							
+						
+					
+					
+						i2c_prd_data
+						i2c_prd_data.
+						0x18
+						
+							
+								cr_i2c_prd_d_ph_3
+								24
+								31
+							
+							
+								cr_i2c_prd_d_ph_2
+								16
+								23
+							
+							
+								cr_i2c_prd_d_ph_1
+								8
+								15
+							
+							
+								cr_i2c_prd_d_ph_0
+								0
+								7
+							
+						
+					
+					
+						i2c_fifo_config_0
+						i2c_fifo_config_0.
+						0x80
+						
+							
+								rx_fifo_underflow
+								7
+								7
+							
+							
+								rx_fifo_overflow
+								6
+								6
+							
+							
+								tx_fifo_underflow
+								5
+								5
+							
+							
+								tx_fifo_overflow
+								4
+								4
+							
+							
+								rx_fifo_clr
+								3
+								3
+							
+							
+								tx_fifo_clr
+								2
+								2
+							
+							
+								i2c_dma_rx_en
+								1
+								1
+							
+							
+								i2c_dma_tx_en
+								0
+								0
+							
+						
+					
+					
+						i2c_fifo_config_1
+						i2c_fifo_config_1.
+						0x84
+						
+							
+								rx_fifo_th
+								24
+								24
+							
+							
+								tx_fifo_th
+								16
+								16
+							
+							
+								rx_fifo_cnt
+								8
+								9
+							
+							
+								tx_fifo_cnt
+								0
+								1
+							
+						
+					
+					
+						i2c_fifo_wdata
+						i2c_fifo_wdata.
+						0x88
+						
+							
+								i2c_fifo_wdata
+								0
+								31
+							
+						
+					
+					
+						i2c_fifo_rdata
+						i2c_fifo_rdata.
+						0x8C
+						
+							
+								i2c_fifo_rdata
+								0
+								31
+							
+						
+					
+				
+			
+			
+				pwm
+				pwm.
+				0x4000A400
+				pwm
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						pwm_int_config
+						pwm_int_config.
+						0x0
+						
+							
+								pwm_int_clear
+								8
+								13
+							
+							
+								pwm_interrupt_sts
+								0
+								5
+							
+						
+					
+					
+						pwm0_clkdiv
+						pwm0_clkdiv.
+						0x20
+						
+							
+								pwm_clk_div
+								0
+								15
+							
+						
+					
+					
+						pwm0_thre1
+						pwm0_thre1.
+						0x24
+						
+							
+								pwm_thre1
+								0
+								15
+							
+						
+					
+					
+						pwm0_thre2
+						pwm0_thre2.
+						0x28
+						
+							
+								pwm_thre2
+								0
+								15
+							
+						
+					
+					
+						pwm0_period
+						pwm0_period.
+						0x2C
+						
+							
+								pwm_period
+								0
+								15
+							
+						
+					
+					
+						pwm0_config
+						pwm0_config.
+						0x30
+						
+							
+								pwm_sts_top
+								7
+								7
+							
+							
+								pwm_stop_en
+								6
+								6
+							
+							
+								pwm_sw_mode
+								5
+								5
+							
+							
+								pwm_sw_force_val
+								4
+								4
+							
+							
+								pwm_stop_mode
+								3
+								3
+							
+							
+								pwm_out_inv
+								2
+								2
+							
+							
+								reg_clk_sel
+								0
+								1
+							
+						
+					
+					
+						pwm0_interrupt
+						pwm0_interrupt.
+						0x34
+						
+							
+								pwm_int_enable
+								16
+								16
+							
+							
+								pwm_int_period_cnt
+								0
+								15
+							
+						
+					
+					
+						pwm1_clkdiv
+						pwm1_clkdiv.
+						0x40
+						
+							
+								pwm_clk_div
+								0
+								15
+							
+						
+					
+					
+						pwm1_thre1
+						pwm1_thre1.
+						0x44
+						
+							
+								pwm_thre1
+								0
+								15
+							
+						
+					
+					
+						pwm1_thre2
+						pwm1_thre2.
+						0x48
+						
+							
+								pwm_thre2
+								0
+								15
+							
+						
+					
+					
+						pwm1_period
+						pwm1_period.
+						0x4C
+						
+							
+								pwm_period
+								0
+								15
+							
+						
+					
+					
+						pwm1_config
+						pwm1_config.
+						0x50
+						
+							
+								pwm_sts_top
+								7
+								7
+							
+							
+								pwm_stop_en
+								6
+								6
+							
+							
+								pwm_sw_mode
+								5
+								5
+							
+							
+								pwm_sw_force_val
+								4
+								4
+							
+							
+								pwm_stop_mode
+								3
+								3
+							
+							
+								pwm_out_inv
+								2
+								2
+							
+							
+								reg_clk_sel
+								0
+								1
+							
+						
+					
+					
+						pwm1_interrupt
+						pwm1_interrupt.
+						0x54
+						
+							
+								pwm_int_enable
+								16
+								16
+							
+							
+								pwm_int_period_cnt
+								0
+								15
+							
+						
+					
+					
+						pwm2_clkdiv
+						pwm2_clkdiv.
+						0x60
+						
+							
+								pwm_clk_div
+								0
+								15
+							
+						
+					
+					
+						pwm2_thre1
+						pwm2_thre1.
+						0x64
+						
+							
+								pwm_thre1
+								0
+								15
+							
+						
+					
+					
+						pwm2_thre2
+						pwm2_thre2.
+						0x68
+						
+							
+								pwm_thre2
+								0
+								15
+							
+						
+					
+					
+						pwm2_period
+						pwm2_period.
+						0x6C
+						
+							
+								pwm_period
+								0
+								15
+							
+						
+					
+					
+						pwm2_config
+						pwm2_config.
+						0x70
+						
+							
+								pwm_sts_top
+								7
+								7
+							
+							
+								pwm_stop_en
+								6
+								6
+							
+							
+								pwm_sw_mode
+								5
+								5
+							
+							
+								pwm_sw_force_val
+								4
+								4
+							
+							
+								pwm_stop_mode
+								3
+								3
+							
+							
+								pwm_out_inv
+								2
+								2
+							
+							
+								reg_clk_sel
+								0
+								1
+							
+						
+					
+					
+						pwm2_interrupt
+						pwm2_interrupt.
+						0x74
+						
+							
+								pwm_int_enable
+								16
+								16
+							
+							
+								pwm_int_period_cnt
+								0
+								15
+							
+						
+					
+					
+						pwm3_clkdiv
+						pwm3_clkdiv.
+						0x80
+						
+							
+								pwm_clk_div
+								0
+								15
+							
+						
+					
+					
+						pwm3_thre1
+						pwm3_thre1.
+						0x84
+						
+							
+								pwm_thre1
+								0
+								15
+							
+						
+					
+					
+						pwm3_thre2
+						pwm3_thre2.
+						0x88
+						
+							
+								pwm_thre2
+								0
+								15
+							
+						
+					
+					
+						pwm3_period
+						pwm3_period.
+						0x8C
+						
+							
+								pwm_period
+								0
+								15
+							
+						
+					
+					
+						pwm3_config
+						pwm3_config.
+						0x90
+						
+							
+								pwm_sts_top
+								7
+								7
+							
+							
+								pwm_stop_en
+								6
+								6
+							
+							
+								pwm_sw_mode
+								5
+								5
+							
+							
+								pwm_sw_force_val
+								4
+								4
+							
+							
+								pwm_stop_mode
+								3
+								3
+							
+							
+								pwm_out_inv
+								2
+								2
+							
+							
+								reg_clk_sel
+								0
+								1
+							
+						
+					
+					
+						pwm3_interrupt
+						pwm3_interrupt.
+						0x94
+						
+							
+								pwm_int_enable
+								16
+								16
+							
+							
+								pwm_int_period_cnt
+								0
+								15
+							
+						
+					
+					
+						pwm4_clkdiv
+						pwm4_clkdiv.
+						0xA0
+						
+							
+								pwm_clk_div
+								0
+								15
+							
+						
+					
+					
+						pwm4_thre1
+						pwm4_thre1.
+						0xA4
+						
+							
+								pwm_thre1
+								0
+								15
+							
+						
+					
+					
+						pwm4_thre2
+						pwm4_thre2.
+						0xA8
+						
+							
+								pwm_thre2
+								0
+								15
+							
+						
+					
+					
+						pwm4_period
+						pwm4_period.
+						0xAC
+						
+							
+								pwm_period
+								0
+								15
+							
+						
+					
+					
+						pwm4_config
+						pwm4_config.
+						0xB0
+						
+							
+								pwm_sts_top
+								7
+								7
+							
+							
+								pwm_stop_en
+								6
+								6
+							
+							
+								pwm_sw_mode
+								5
+								5
+							
+							
+								pwm_sw_force_val
+								4
+								4
+							
+							
+								pwm_stop_mode
+								3
+								3
+							
+							
+								pwm_out_inv
+								2
+								2
+							
+							
+								reg_clk_sel
+								0
+								1
+							
+						
+					
+					
+						pwm4_interrupt
+						pwm4_interrupt.
+						0xB4
+						
+							
+								pwm_int_enable
+								16
+								16
+							
+							
+								pwm_int_period_cnt
+								0
+								15
+							
+						
+					
+				
+			
+			
+				timer
+				timer.
+				0x4000A500
+				timer
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						TCCR
+						TCCR.
+						0x0
+						
+							
+								cs_wdt
+								8
+								9
+							
+							
+								RESERVED_7
+								7
+								7
+							
+							
+								cs_2
+								5
+								6
+							
+							
+								RESERVED_4
+								4
+								4
+							
+							
+								cs_1
+								2
+								3
+							
+						
+					
+					
+						TMR2_0
+						TMR2_0.
+						0x10
+						
+							
+								tmr
+								0
+								31
+							
+						
+					
+					
+						TMR2_1
+						TMR2_1.
+						0x14
+						
+							
+								tmr
+								0
+								31
+							
+						
+					
+					
+						TMR2_2
+						TMR2_2.
+						0x18
+						
+							
+								tmr
+								0
+								31
+							
+						
+					
+					
+						TMR3_0
+						TMR3_0.
+						0x1C
+						
+							
+								tmr
+								0
+								31
+							
+						
+					
+					
+						TMR3_1
+						TMR3_1.
+						0x20
+						
+							
+								tmr
+								0
+								31
+							
+						
+					
+					
+						TMR3_2
+						TMR3_2.
+						0x24
+						
+							
+								tmr
+								0
+								31
+							
+						
+					
+					
+						TCR2
+						TCR2.
+						0x2C
+						
+							
+								tcr
+								0
+								31
+							
+						
+					
+					
+						TCR3
+						TCR3.
+						0x30
+						
+							
+								tcr
+								0
+								31
+							
+						
+					
+					
+						TMSR2
+						TMSR2.
+						0x38
+						
+							
+								tmsr_2
+								2
+								2
+							
+							
+								tmsr_1
+								1
+								1
+							
+							
+								tmsr_0
+								0
+								0
+							
+						
+					
+					
+						TMSR3
+						TMSR3.
+						0x3C
+						
+							
+								tmsr_2
+								2
+								2
+							
+							
+								tmsr_1
+								1
+								1
+							
+							
+								tmsr_0
+								0
+								0
+							
+						
+					
+					
+						TIER2
+						TIER2.
+						0x44
+						
+							
+								tier_2
+								2
+								2
+							
+							
+								tier_1
+								1
+								1
+							
+							
+								tier_0
+								0
+								0
+							
+						
+					
+					
+						TIER3
+						TIER3.
+						0x48
+						
+							
+								tier_2
+								2
+								2
+							
+							
+								tier_1
+								1
+								1
+							
+							
+								tier_0
+								0
+								0
+							
+						
+					
+					
+						TPLVR2
+						TPLVR2.
+						0x50
+						
+							
+								tplvr
+								0
+								31
+							
+						
+					
+					
+						TPLVR3
+						TPLVR3.
+						0x54
+						
+							
+								tplvr
+								0
+								31
+							
+						
+					
+					
+						TPLCR2
+						TPLCR2.
+						0x5C
+						
+							
+								tplcr
+								0
+								1
+							
+						
+					
+					
+						TPLCR3
+						TPLCR3.
+						0x60
+						
+							
+								tplcr
+								0
+								1
+							
+						
+					
+					
+						WMER
+						WMER.
+						0x64
+						
+							
+								wrie
+								1
+								1
+							
+							
+								we
+								0
+								0
+							
+						
+					
+					
+						WMR
+						WMR.
+						0x68
+						
+							
+								wmr
+								0
+								15
+							
+						
+					
+					
+						WVR
+						WVR.
+						0x6C
+						
+							
+								wvr
+								0
+								15
+							
+						
+					
+					
+						WSR
+						WSR.
+						0x70
+						
+							
+								wts
+								0
+								0
+							
+						
+					
+					
+						TICR2
+						TICR2.
+						0x78
+						
+							
+								tclr_2
+								2
+								2
+							
+							
+								tclr_1
+								1
+								1
+							
+							
+								tclr_0
+								0
+								0
+							
+						
+					
+					
+						TICR3
+						TICR3.
+						0x7C
+						
+							
+								tclr_2
+								2
+								2
+							
+							
+								tclr_1
+								1
+								1
+							
+							
+								tclr_0
+								0
+								0
+							
+						
+					
+					
+						WICR
+						WICR.
+						0x80
+						
+							
+								wiclr
+								0
+								0
+							
+						
+					
+					
+						TCER
+						TCER.
+						0x84
+						
+							
+								timer3_en
+								2
+								2
+							
+							
+								timer2_en
+								1
+								1
+							
+						
+					
+					
+						TCMR
+						TCMR.
+						0x88
+						
+							
+								timer3_mode
+								2
+								2
+							
+							
+								timer2_mode
+								1
+								1
+							
+						
+					
+					
+						TILR2
+						TILR2.
+						0x90
+						
+							
+								tilr_2
+								2
+								2
+							
+							
+								tilr_1
+								1
+								1
+							
+							
+								tilr_0
+								0
+								0
+							
+						
+					
+					
+						TILR3
+						TILR3.
+						0x94
+						
+							
+								tilr_2
+								2
+								2
+							
+							
+								tilr_1
+								1
+								1
+							
+							
+								tilr_0
+								0
+								0
+							
+						
+					
+					
+						WCR
+						WCR.
+						0x98
+						
+							
+								wcr
+								0
+								0
+							
+						
+					
+					
+						WFAR
+						WFAR.
+						0x9C
+						
+							
+								wfar
+								0
+								15
+							
+						
+					
+					
+						WSAR
+						WSAR.
+						0xA0
+						
+							
+								wsar
+								0
+								15
+							
+						
+					
+					
+						TCVWR2
+						TCVWR2.
+						0xA8
+						
+							
+								tcvwr
+								0
+								31
+							
+						
+					
+					
+						TCVWR3
+						TCVWR3.
+						0xAC
+						
+							
+								tcvwr
+								0
+								31
+							
+						
+					
+					
+						TCVSYN2
+						TCVSYN2.
+						0xB4
+						
+							
+								tcvsyn2
+								0
+								31
+							
+						
+					
+					
+						TCVSYN3
+						TCVSYN3.
+						0xB8
+						
+							
+								tcvsyn3
+								0
+								31
+							
+						
+					
+					
+						TCDR
+						TCDR.
+						0xBC
+						
+							
+								wcdr
+								24
+								31
+							
+							
+								tcdr3
+								16
+								23
+							
+							
+								tcdr2
+								8
+								15
+							
+						
+					
+				
+			
+			
+				ir
+				ir.
+				0x4000A600
+				ir
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						irtx_config
+						irtx_config.
+						0x0
+						
+							
+								cr_irtx_data_num
+								12
+								17
+							
+							
+								cr_irtx_tail_hl_inv
+								11
+								11
+							
+							
+								cr_irtx_tail_en
+								10
+								10
+							
+							
+								cr_irtx_head_hl_inv
+								9
+								9
+							
+							
+								cr_irtx_head_en
+								8
+								8
+							
+							
+								cr_irtx_logic1_hl_inv
+								6
+								6
+							
+							
+								cr_irtx_logic0_hl_inv
+								5
+								5
+							
+							
+								cr_irtx_data_en
+								4
+								4
+							
+							
+								cr_irtx_swm_en
+								3
+								3
+							
+							
+								cr_irtx_mod_en
+								2
+								2
+							
+							
+								cr_irtx_out_inv
+								1
+								1
+							
+							
+								cr_irtx_en
+								0
+								0
+							
+						
+					
+					
+						irtx_int_sts
+						irtx_int_sts.
+						0x4
+						
+							
+								cr_irtx_end_en
+								24
+								24
+							
+							
+								cr_irtx_end_clr
+								16
+								16
+							
+							
+								cr_irtx_end_mask
+								8
+								8
+							
+							
+								irtx_end_int
+								0
+								0
+							
+						
+					
+					
+						irtx_data_word0
+						irtx_data_word0.
+						0x8
+						
+							
+								cr_irtx_data_word0
+								0
+								31
+							
+						
+					
+					
+						irtx_data_word1
+						irtx_data_word1.
+						0xC
+						
+							
+								cr_irtx_data_word1
+								0
+								31
+							
+						
+					
+					
+						irtx_pulse_width
+						irtx_pulse_width.
+						0x10
+						
+							
+								cr_irtx_mod_ph1_w
+								24
+								31
+							
+							
+								cr_irtx_mod_ph0_w
+								16
+								23
+							
+							
+								cr_irtx_pw_unit
+								0
+								11
+							
+						
+					
+					
+						irtx_pw
+						irtx_pw.
+						0x14
+						
+							
+								cr_irtx_tail_ph1_w
+								28
+								31
+							
+							
+								cr_irtx_tail_ph0_w
+								24
+								27
+							
+							
+								cr_irtx_head_ph1_w
+								20
+								23
+							
+							
+								cr_irtx_head_ph0_w
+								16
+								19
+							
+							
+								cr_irtx_logic1_ph1_w
+								12
+								15
+							
+							
+								cr_irtx_logic1_ph0_w
+								8
+								11
+							
+							
+								cr_irtx_logic0_ph1_w
+								4
+								7
+							
+							
+								cr_irtx_logic0_ph0_w
+								0
+								3
+							
+						
+					
+					
+						irtx_swm_pw_0
+						irtx_swm_pw_0.
+						0x40
+						
+							
+								cr_irtx_swm_pw_0
+								0
+								31
+							
+						
+					
+					
+						irtx_swm_pw_1
+						irtx_swm_pw_1.
+						0x44
+						
+							
+								cr_irtx_swm_pw_1
+								0
+								31
+							
+						
+					
+					
+						irtx_swm_pw_2
+						irtx_swm_pw_2.
+						0x48
+						
+							
+								cr_irtx_swm_pw_2
+								0
+								31
+							
+						
+					
+					
+						irtx_swm_pw_3
+						irtx_swm_pw_3.
+						0x4C
+						
+							
+								cr_irtx_swm_pw_3
+								0
+								31
+							
+						
+					
+					
+						irtx_swm_pw_4
+						irtx_swm_pw_4.
+						0x50
+						
+							
+								cr_irtx_swm_pw_4
+								0
+								31
+							
+						
+					
+					
+						irtx_swm_pw_5
+						irtx_swm_pw_5.
+						0x54
+						
+							
+								cr_irtx_swm_pw_5
+								0
+								31
+							
+						
+					
+					
+						irtx_swm_pw_6
+						irtx_swm_pw_6.
+						0x58
+						
+							
+								cr_irtx_swm_pw_6
+								0
+								31
+							
+						
+					
+					
+						irtx_swm_pw_7
+						irtx_swm_pw_7.
+						0x5C
+						
+							
+								cr_irtx_swm_pw_7
+								0
+								31
+							
+						
+					
+					
+						irrx_config
+						irrx_config.
+						0x80
+						
+							
+								cr_irrx_deg_cnt
+								8
+								11
+							
+							
+								cr_irrx_deg_en
+								4
+								4
+							
+							
+								cr_irrx_mode
+								2
+								3
+							
+							
+								cr_irrx_in_inv
+								1
+								1
+							
+							
+								cr_irrx_en
+								0
+								0
+							
+						
+					
+					
+						irrx_int_sts
+						irrx_int_sts.
+						0x84
+						
+							
+								cr_irrx_end_en
+								24
+								24
+							
+							
+								cr_irrx_end_clr
+								16
+								16
+							
+							
+								cr_irrx_end_mask
+								8
+								8
+							
+							
+								irrx_end_int
+								0
+								0
+							
+						
+					
+					
+						irrx_pw_config
+						irrx_pw_config.
+						0x88
+						
+							
+								cr_irrx_end_th
+								16
+								31
+							
+							
+								cr_irrx_data_th
+								0
+								15
+							
+						
+					
+					
+						irrx_data_count
+						irrx_data_count.
+						0x90
+						
+							
+								sts_irrx_data_cnt
+								0
+								6
+							
+						
+					
+					
+						irrx_data_word0
+						irrx_data_word0.
+						0x94
+						
+							
+								sts_irrx_data_word0
+								0
+								31
+							
+						
+					
+					
+						irrx_data_word1
+						irrx_data_word1.
+						0x98
+						
+							
+								sts_irrx_data_word1
+								0
+								31
+							
+						
+					
+					
+						irrx_swm_fifo_config_0
+						irrx_swm_fifo_config_0.
+						0xC0
+						
+							
+								rx_fifo_cnt
+								4
+								10
+							
+							
+								rx_fifo_underflow
+								3
+								3
+							
+							
+								rx_fifo_overflow
+								2
+								2
+							
+							
+								rx_fifo_clr
+								0
+								0
+							
+						
+					
+					
+						irrx_swm_fifo_rdata
+						irrx_swm_fifo_rdata.
+						0xC4
+						
+							
+								rx_fifo_rdata
+								0
+								15
+							
+						
+					
+				
+			
+			
+				cks
+				cks.
+				0x4000A700
+				cks
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						cks_config
+						cks_config.
+						0x0
+						
+							
+								cr_cks_byte_swap
+								1
+								1
+							
+							
+								cr_cks_clr
+								0
+								0
+							
+						
+					
+					
+						data_in
+						data_in.
+						0x4
+						
+							
+								data_in
+								0
+								7
+							
+						
+					
+					
+						cks_out
+						cks_out.
+						0x8
+						
+							
+								cks_out
+								0
+								15
+							
+						
+					
+				
+			
+			
+				qdec
+				qdec.
+				0x4000A800
+				qdec
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						qdec_ctrl
+						qdec_ctrl.
+						0x0
+						
+							
+								input_swap
+								31
+								31
+							
+							
+								rpt_mode
+								30
+								30
+							
+							
+								spl_mode
+								29
+								29
+							
+							
+								led_period
+								20
+								28
+							
+							
+								rpt_period
+								12
+								19
+							
+							
+								spl_period
+								8
+								11
+							
+							
+								deg_cnt
+								4
+								7
+							
+							
+								deg_en
+								3
+								3
+							
+							
+								led_pol
+								2
+								2
+							
+							
+								led_en
+								1
+								1
+							
+							
+								qdec_en
+								0
+								0
+							
+						
+					
+					
+						qdec_value
+						qdec_value.
+						0x4
+						
+							
+								spl_val
+								28
+								29
+							
+							
+								acc2_val
+								16
+								19
+							
+							
+								acc1_val
+								0
+								10
+							
+						
+					
+					
+						qdec_int_en
+						qdec_int_en.
+						0x10
+						
+							
+								overflow_en
+								3
+								3
+							
+							
+								dbl_rdy_en
+								2
+								2
+							
+							
+								spl_rdy_en
+								1
+								1
+							
+							
+								rpt_rdy_en
+								0
+								0
+							
+						
+					
+					
+						qdec_int_sts
+						qdec_int_sts.
+						0x14
+						
+							
+								overflow_sts
+								3
+								3
+							
+							
+								dbl_rdy_sts
+								2
+								2
+							
+							
+								spl_rdy_sts
+								1
+								1
+							
+							
+								rpt_rdy_sts
+								0
+								0
+							
+						
+					
+					
+						qdec_int_clr
+						qdec_int_clr.
+						0x18
+						
+							
+								overflow_clr
+								3
+								3
+							
+							
+								dbl_rdy_clr
+								2
+								2
+							
+							
+								spl_rdy_clr
+								1
+								1
+							
+							
+								rpt_rdy_clr
+								0
+								0
+							
+						
+					
+				
+			
+			
+				kys
+				kys.
+				0x4000AB00
+				kys
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						ks_ctrl
+						ks_ctrl.
+						0x0
+						
+							
+								col_num
+								20
+								24
+							
+							
+								row_num
+								16
+								18
+							
+							
+								rc_ext
+								8
+								9
+							
+							
+								deg_cnt
+								4
+								7
+							
+							
+								deg_en
+								3
+								3
+							
+							
+								ghost_en
+								2
+								2
+							
+							
+								ks_en
+								0
+								0
+							
+						
+					
+					
+						ks_int_en
+						ks_int_en.
+						0x10
+						
+							
+								ks_int_en
+								0
+								0
+							
+						
+					
+					
+						ks_int_sts
+						ks_int_sts.
+						0x14
+						
+							
+								keycode_valid
+								0
+								3
+							
+						
+					
+					
+						keycode_clr
+						keycode_clr.
+						0x18
+						
+							
+								keycode_clr
+								0
+								3
+							
+						
+					
+					
+						keycode_value
+						keycode_value.
+						0x1C
+						
+							
+								keycode3
+								24
+								31
+							
+							
+								keycode2
+								16
+								23
+							
+							
+								keycode1
+								8
+								15
+							
+							
+								keycode0
+								0
+								7
+							
+						
+					
+				
+			
+			
+				i2s
+				i2s.
+				0x4000AA00
+				i2s
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						i2s_config
+						i2s_config.
+						0x0
+						
+							
+								cr_ofs_en
+								25
+								25
+							
+							
+								cr_ofs_cnt
+								20
+								24
+							
+							
+								cr_mono_rx_ch
+								19
+								19
+							
+							
+								cr_endian
+								18
+								18
+							
+							
+								cr_i2s_mode
+								16
+								17
+							
+							
+								cr_data_size
+								14
+								15
+							
+							
+								cr_frame_size
+								12
+								13
+							
+							
+								cr_fs_3ch_mode
+								8
+								8
+							
+							
+								cr_fs_4ch_mode
+								7
+								7
+							
+							
+								cr_fs_1t_mode
+								6
+								6
+							
+							
+								cr_mute_mode
+								5
+								5
+							
+							
+								cr_mono_mode
+								4
+								4
+							
+							
+								cr_i2s_rxd_en
+								3
+								3
+							
+							
+								cr_i2s_txd_en
+								2
+								2
+							
+							
+								cr_i2s_s_en
+								1
+								1
+							
+							
+								cr_i2s_m_en
+								0
+								0
+							
+						
+					
+					
+						i2s_int_sts
+						i2s_int_sts.
+						0x4
+						
+							
+								cr_i2s_fer_en
+								26
+								26
+							
+							
+								cr_i2s_rxf_en
+								25
+								25
+							
+							
+								cr_i2s_txf_en
+								24
+								24
+							
+							
+								cr_i2s_fer_mask
+								10
+								10
+							
+							
+								cr_i2s_rxf_mask
+								9
+								9
+							
+							
+								cr_i2s_txf_mask
+								8
+								8
+							
+							
+								i2s_fer_int
+								2
+								2
+							
+							
+								i2s_rxf_int
+								1
+								1
+							
+							
+								i2s_txf_int
+								0
+								0
+							
+						
+					
+					
+						i2s_bclk_config
+						i2s_bclk_config.
+						0x10
+						
+							
+								cr_bclk_div_h
+								16
+								27
+							
+							
+								cr_bclk_div_l
+								0
+								11
+							
+						
+					
+					
+						i2s_fifo_config_0
+						i2s_fifo_config_0.
+						0x80
+						
+							
+								cr_fifo_24b_lj
+								10
+								10
+							
+							
+								cr_fifo_lr_exchg
+								9
+								9
+							
+							
+								cr_fifo_lr_merge
+								8
+								8
+							
+							
+								rx_fifo_underflow
+								7
+								7
+							
+							
+								rx_fifo_overflow
+								6
+								6
+							
+							
+								tx_fifo_underflow
+								5
+								5
+							
+							
+								tx_fifo_overflow
+								4
+								4
+							
+							
+								rx_fifo_clr
+								3
+								3
+							
+							
+								tx_fifo_clr
+								2
+								2
+							
+							
+								i2s_dma_rx_en
+								1
+								1
+							
+							
+								i2s_dma_tx_en
+								0
+								0
+							
+						
+					
+					
+						i2s_fifo_config_1
+						i2s_fifo_config_1.
+						0x84
+						
+							
+								rx_fifo_th
+								24
+								27
+							
+							
+								tx_fifo_th
+								16
+								19
+							
+							
+								rx_fifo_cnt
+								8
+								12
+							
+							
+								tx_fifo_cnt
+								0
+								4
+							
+						
+					
+					
+						i2s_fifo_wdata
+						i2s_fifo_wdata.
+						0x88
+						
+							
+								i2s_fifo_wdata
+								0
+								31
+							
+						
+					
+					
+						i2s_fifo_rdata
+						i2s_fifo_rdata.
+						0x8C
+						
+							
+								i2s_fifo_rdata
+								0
+								31
+							
+						
+					
+					
+						i2s_io_config
+						i2s_io_config.
+						0xFC
+						
+							
+								cr_deg_en
+								7
+								7
+							
+							
+								cr_deg_cnt
+								4
+								6
+							
+							
+								cr_i2s_bclk_inv
+								3
+								3
+							
+							
+								cr_i2s_fs_inv
+								2
+								2
+							
+							
+								cr_i2s_rxd_inv
+								1
+								1
+							
+							
+								cr_i2s_txd_inv
+								0
+								0
+							
+						
+					
+				
+			
+			
+				cam
+				cam.
+				0x4000AD00
+				cam
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						dvp2axi_configue
+						dvp2axi_configue.
+						0x0
+						
+							
+								reg_dvp_wait_cycle
+								24
+								31
+							
+							
+								reg_dvp_pix_clk_cg
+								20
+								20
+							
+							
+								reg_interlv_mode
+								16
+								16
+							
+							
+								reg_subsample_even
+								15
+								15
+							
+							
+								reg_subsample_en
+								14
+								14
+							
+							
+								reg_drop_even
+								13
+								13
+							
+							
+								reg_drop_en
+								12
+								12
+							
+							
+								reg_hw_mode_fwrap
+								11
+								11
+							
+							
+								reg_dvp_mode
+								8
+								10
+							
+							
+								reg_hburst
+								4
+								5
+							
+							
+								reg_line_vld_pol
+								3
+								3
+							
+							
+								reg_fram_vld_pol
+								2
+								2
+							
+							
+								reg_sw_mode
+								1
+								1
+							
+							
+								reg_dvp_enable
+								0
+								0
+							
+						
+					
+					
+						dvp2ahb_addr_start_0
+						dvp2ahb_addr_start_0.
+						0x4
+						
+							
+								reg_addr_start_0
+								0
+								31
+							
+						
+					
+					
+						dvp2ahb_mem_bcnt_0
+						dvp2ahb_mem_bcnt_0.
+						0x8
+						
+							
+								reg_mem_burst_cnt_0
+								0
+								31
+							
+						
+					
+					
+						dvp2ahb_frame_bcnt_0
+						dvp2ahb_frame_bcnt_0.
+						0xC
+						
+							
+								reg_frame_burst_cnt_0
+								0
+								31
+							
+						
+					
+					
+						dvp2ahb_addr_start_1
+						dvp2ahb_addr_start_1.
+						0x10
+						
+							
+								reg_addr_start_1
+								0
+								31
+							
+						
+					
+					
+						dvp2ahb_mem_bcnt_1
+						dvp2ahb_mem_bcnt_1.
+						0x14
+						
+							
+								reg_mem_burst_cnt_1
+								0
+								31
+							
+						
+					
+					
+						dvp2ahb_frame_bcnt_1
+						dvp2ahb_frame_bcnt_1.
+						0x18
+						
+							
+								reg_frame_burst_cnt_1
+								0
+								31
+							
+						
+					
+					
+						dvp_status_and_error
+						dvp_status_and_error.
+						0x1C
+						
+							
+								st_bus_flsh
+								31
+								31
+							
+							
+								st_bus_wait
+								30
+								30
+							
+							
+								st_bus_func
+								29
+								29
+							
+							
+								st_bus_idle
+								28
+								28
+							
+							
+								frame_valid_cnt_1
+								24
+								27
+							
+							
+								frame_valid_cnt_0
+								20
+								23
+							
+							
+								st_dvp_idle
+								19
+								19
+							
+							
+								ahb_idle_1
+								17
+								17
+							
+							
+								ahb_idle_0
+								16
+								16
+							
+							
+								sts_vcnt_int
+								9
+								9
+							
+							
+								sts_hcnt_int
+								8
+								8
+							
+							
+								sts_fifo_int_1
+								7
+								7
+							
+							
+								sts_fifo_int_0
+								6
+								6
+							
+							
+								sts_frame_int_1
+								5
+								5
+							
+							
+								sts_frame_int_0
+								4
+								4
+							
+							
+								sts_mem_int_1
+								3
+								3
+							
+							
+								sts_mem_int_0
+								2
+								2
+							
+							
+								sts_normal_int_1
+								1
+								1
+							
+							
+								sts_normal_int_0
+								0
+								0
+							
+						
+					
+					
+						dvp_frame_fifo_pop
+						dvp_frame_fifo_pop.
+						0x20
+						
+							
+								reg_int_fifo_clr_1
+								19
+								19
+							
+							
+								reg_int_frame_clr_1
+								18
+								18
+							
+							
+								reg_int_mem_clr_1
+								17
+								17
+							
+							
+								reg_int_normal_clr_1
+								16
+								16
+							
+							
+								reg_int_vcnt_clr_0
+								9
+								9
+							
+							
+								reg_int_hcnt_clr_0
+								8
+								8
+							
+							
+								reg_int_fifo_clr_0
+								7
+								7
+							
+							
+								reg_int_frame_clr_0
+								6
+								6
+							
+							
+								reg_int_mem_clr_0
+								5
+								5
+							
+							
+								reg_int_normal_clr_0
+								4
+								4
+							
+							
+								rfifo_pop_1
+								1
+								1
+							
+							
+								rfifo_pop_0
+								0
+								0
+							
+						
+					
+					
+						snsr_control
+						snsr_control.
+						0x24
+						
+							
+								reg_cam_pwdn
+								1
+								1
+							
+							
+								reg_cam_rst
+								0
+								0
+							
+						
+					
+					
+						int_control
+						int_control.
+						0x28
+						
+							
+								reg_frame_cnt_trgr_int
+								28
+								31
+							
+							
+								reg_int_vcnt_en
+								6
+								6
+							
+							
+								reg_int_hcnt_en
+								5
+								5
+							
+							
+								reg_int_fifo_en
+								4
+								4
+							
+							
+								reg_int_frame_en
+								3
+								3
+							
+							
+								reg_int_mem_en
+								2
+								2
+							
+							
+								reg_int_normal_1_en
+								1
+								1
+							
+							
+								reg_int_normal_0_en
+								0
+								0
+							
+						
+					
+					
+						hsync_control
+						hsync_control.
+						0x30
+						
+							
+								reg_hsync_act_start
+								16
+								31
+							
+							
+								reg_hsync_act_end
+								0
+								15
+							
+						
+					
+					
+						vsync_control
+						vsync_control.
+						0x34
+						
+							
+								reg_vsync_act_start
+								16
+								31
+							
+							
+								reg_vsync_act_end
+								0
+								15
+							
+						
+					
+					
+						frame_size_control
+						frame_size_control.
+						0x38
+						
+							
+								reg_total_vcnt
+								16
+								31
+							
+							
+								reg_total_hcnt
+								0
+								15
+							
+						
+					
+					
+						frame_start_addr0_0
+						frame_start_addr0_0.
+						0x40
+						
+							
+								frame_start_addr_0_0
+								0
+								31
+							
+						
+					
+					
+						frame_byte_cnt0_0
+						frame_byte_cnt0_0.
+						0x44
+						
+							
+								frame_byte_cnt_0_0
+								0
+								31
+							
+						
+					
+					
+						frame_start_addr0_1
+						frame_start_addr0_1.
+						0x48
+						
+							
+								frame_start_addr_0_1
+								0
+								31
+							
+						
+					
+					
+						frame_byte_cnt0_1
+						frame_byte_cnt0_1.
+						0x4C
+						
+							
+								frame_byte_cnt_0_1
+								0
+								31
+							
+						
+					
+					
+						frame_start_addr0_2
+						frame_start_addr0_2.
+						0x50
+						
+							
+								frame_start_addr_0_2
+								0
+								31
+							
+						
+					
+					
+						frame_byte_cnt0_2
+						frame_byte_cnt0_2.
+						0x54
+						
+							
+								frame_byte_cnt_0_2
+								0
+								31
+							
+						
+					
+					
+						frame_start_addr0_3
+						frame_start_addr0_3.
+						0x58
+						
+							
+								frame_start_addr_0_3
+								0
+								31
+							
+						
+					
+					
+						frame_byte_cnt0_3
+						frame_byte_cnt0_3.
+						0x5C
+						
+							
+								frame_byte_cnt_0_3
+								0
+								31
+							
+						
+					
+					
+						frame_start_addr0_4
+						frame_start_addr0_4.
+						0x60
+						
+							
+								frame_start_addr_0_4
+								0
+								31
+							
+						
+					
+					
+						frame_byte_cnt0_4
+						frame_byte_cnt0_4.
+						0x64
+						
+							
+								frame_byte_cnt_0_4
+								0
+								31
+							
+						
+					
+					
+						frame_start_addr0_5
+						frame_start_addr0_5.
+						0x68
+						
+							
+								frame_start_addr_0_5
+								0
+								31
+							
+						
+					
+					
+						frame_byte_cnt0_5
+						frame_byte_cnt0_5.
+						0x6C
+						
+							
+								frame_byte_cnt_0_5
+								0
+								31
+							
+						
+					
+					
+						frame_start_addr0_6
+						frame_start_addr0_6.
+						0x70
+						
+							
+								frame_start_addr_0_6
+								0
+								31
+							
+						
+					
+					
+						frame_byte_cnt0_6
+						frame_byte_cnt0_6.
+						0x74
+						
+							
+								frame_byte_cnt_0_6
+								0
+								31
+							
+						
+					
+					
+						frame_start_addr0_7
+						frame_start_addr0_7.
+						0x78
+						
+							
+								frame_start_addr_0_7
+								0
+								31
+							
+						
+					
+					
+						frame_byte_cnt0_7
+						frame_byte_cnt0_7.
+						0x7C
+						
+							
+								frame_byte_cnt_0_7
+								0
+								31
+							
+						
+					
+					
+						frame_start_addr1_0
+						frame_start_addr1_0.
+						0x80
+						
+							
+								frame_start_addr_1_0
+								0
+								31
+							
+						
+					
+					
+						frame_byte_cnt1_0
+						frame_byte_cnt1_0.
+						0x84
+						
+							
+								frame_byte_cnt_1_0
+								0
+								31
+							
+						
+					
+					
+						frame_start_addr1_1
+						frame_start_addr1_1.
+						0x88
+						
+							
+								frame_start_addr_1_1
+								0
+								31
+							
+						
+					
+					
+						frame_byte_cnt1_1
+						frame_byte_cnt1_1.
+						0x8C
+						
+							
+								frame_byte_cnt_1_1
+								0
+								31
+							
+						
+					
+					
+						frame_start_addr1_2
+						frame_start_addr1_2.
+						0x90
+						
+							
+								frame_start_addr_1_2
+								0
+								31
+							
+						
+					
+					
+						frame_byte_cnt1_2
+						frame_byte_cnt1_2.
+						0x94
+						
+							
+								frame_byte_cnt_1_2
+								0
+								31
+							
+						
+					
+					
+						frame_start_addr1_3
+						frame_start_addr1_3.
+						0x98
+						
+							
+								frame_start_addr_1_3
+								0
+								31
+							
+						
+					
+					
+						frame_byte_cnt1_3
+						frame_byte_cnt1_3.
+						0x9C
+						
+							
+								frame_byte_cnt_1_3
+								0
+								31
+							
+						
+					
+					
+						frame_start_addr1_4
+						frame_start_addr1_4.
+						0xA0
+						
+							
+								frame_start_addr_1_4
+								0
+								31
+							
+						
+					
+					
+						frame_byte_cnt1_4
+						frame_byte_cnt1_4.
+						0xA4
+						
+							
+								frame_byte_cnt_1_4
+								0
+								31
+							
+						
+					
+					
+						frame_start_addr1_5
+						frame_start_addr1_5.
+						0xA8
+						
+							
+								frame_start_addr_1_5
+								0
+								31
+							
+						
+					
+					
+						frame_byte_cnt1_5
+						frame_byte_cnt1_5.
+						0xAC
+						
+							
+								frame_byte_cnt_1_5
+								0
+								31
+							
+						
+					
+					
+						frame_start_addr1_6
+						frame_start_addr1_6.
+						0xB0
+						
+							
+								frame_start_addr_1_6
+								0
+								31
+							
+						
+					
+					
+						frame_byte_cnt1_6
+						frame_byte_cnt1_6.
+						0xB4
+						
+							
+								frame_byte_cnt_1_6
+								0
+								31
+							
+						
+					
+					
+						frame_start_addr1_7
+						frame_start_addr1_7.
+						0xB8
+						
+							
+								frame_start_addr_1_7
+								0
+								31
+							
+						
+					
+					
+						frame_byte_cnt1_7
+						frame_byte_cnt1_7.
+						0xBC
+						
+							
+								frame_byte_cnt_1_7
+								0
+								31
+							
+						
+					
+					
+						dvp_debug
+						dvp_debug.
+						0xFF0
+						
+							
+								reg_dvp_dbg_sel
+								1
+								3
+							
+							
+								reg_dvp_dbg_en
+								0
+								0
+							
+						
+					
+					
+						dvp_dummy_reg
+						dvp_dummy_reg.
+						0xFFC
+						
+							
+								RESERVED_31_0
+								0
+								31
+							
+						
+					
+				
+			
+			
+				mjpeg
+				mjpeg.
+				0x4000AE00
+				mjpeg
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						mjpeg_control_1
+						mjpeg_control_1.
+						0x0
+						
+							
+								reg_v0_order
+								30
+								31
+							
+							
+								reg_y1_order
+								28
+								29
+							
+							
+								reg_u0_order
+								26
+								27
+							
+							
+								reg_y0_order
+								24
+								25
+							
+							
+								reg_q_mode
+								16
+								22
+							
+							
+								reg_yuv_mode
+								12
+								13
+							
+							
+								reg_h_bust
+								8
+								9
+							
+							
+								reg_reflect_dmy
+								6
+								6
+							
+							
+								reg_last_hf_hblk_dmy
+								5
+								5
+							
+							
+								reg_last_hf_wblk_dmy
+								4
+								4
+							
+							
+								reg_wr_over_stop
+								3
+								3
+							
+							
+								reg_order_u_even
+								2
+								2
+							
+							
+								reg_mjpeg_bit_order
+								1
+								1
+							
+							
+								reg_mjpeg_enable
+								0
+								0
+							
+						
+					
+					
+						mjpeg_control_2
+						mjpeg_control_2.
+						0x4
+						
+							
+								reg_mjpeg_wait_cycle
+								16
+								31
+							
+							
+								reg_uv_dvp2ahb_fsel
+								15
+								15
+							
+							
+								reg_uv_dvp2ahb_lsel
+								14
+								14
+							
+							
+								reg_yy_dvp2ahb_fsel
+								13
+								13
+							
+							
+								reg_yy_dvp2ahb_lsel
+								12
+								12
+							
+							
+								reg_mjpeg_sw_run
+								9
+								9
+							
+							
+								reg_mjpeg_sw_mode
+								8
+								8
+							
+							
+								reg_sw_frame
+								0
+								4
+							
+						
+					
+					
+						mjpeg_yy_frame_addr
+						mjpeg_yy_frame_addr.
+						0x08
+						
+							
+								reg_yy_addr_start
+								0
+								31
+							
+						
+					
+					
+						mjpeg_uv_frame_addr
+						mjpeg_uv_frame_addr.
+						0x0C
+						
+							
+								reg_uv_addr_start
+								0
+								31
+							
+						
+					
+					
+						mjpeg_yuv_mem
+						mjpeg_yuv_mem.
+						0x10
+						
+							
+								reg_uv_mem_hblk
+								16
+								28
+							
+							
+								reg_yy_mem_hblk
+								0
+								12
+							
+						
+					
+					
+						jpeg_frame_addr
+						jpeg_frame_addr.
+						0x14
+						
+							
+								reg_w_addr_start
+								0
+								31
+							
+						
+					
+					
+						jpeg_store_memory
+						jpeg_store_memory.
+						0x18
+						
+							
+								reg_w_burst_cnt
+								0
+								31
+							
+						
+					
+					
+						mjpeg_control_3
+						mjpeg_control_3.
+						0x1C
+						
+							
+								sts_swap_int
+								30
+								30
+							
+							
+								reg_int_swap_en
+								29
+								29
+							
+							
+								frame_valid_cnt
+								24
+								28
+							
+							
+								sts_idle_int
+								22
+								22
+							
+							
+								reg_int_idle_en
+								21
+								21
+							
+							
+								reg_frame_cnt_trgr_int
+								16
+								20
+							
+							
+								ahb_idle
+								14
+								14
+							
+							
+								mjpeg_manf
+								13
+								13
+							
+							
+								mjpeg_mans
+								12
+								12
+							
+							
+								mjpeg_flsh
+								11
+								11
+							
+							
+								mjpeg_wait
+								10
+								10
+							
+							
+								mjpeg_func
+								9
+								9
+							
+							
+								mjpeg_idle
+								8
+								8
+							
+							
+								sts_frame_int
+								7
+								7
+							
+							
+								sts_mem_int
+								6
+								6
+							
+							
+								sts_cam_int
+								5
+								5
+							
+							
+								sts_normal_int
+								4
+								4
+							
+							
+								reg_int_frame_en
+								3
+								3
+							
+							
+								reg_int_mem_en
+								2
+								2
+							
+							
+								reg_int_cam_en
+								1
+								1
+							
+							
+								reg_int_normal_en
+								0
+								0
+							
+						
+					
+					
+						mjpeg_frame_fifo_pop
+						mjpeg_frame_fifo_pop.
+						0x20
+						
+							
+								reg_int_swap_clr
+								13
+								13
+							
+							
+								reg_int_idle_clr
+								12
+								12
+							
+							
+								reg_int_frame_clr
+								11
+								11
+							
+							
+								reg_int_mem_clr
+								10
+								10
+							
+							
+								reg_int_cam_clr
+								9
+								9
+							
+							
+								reg_int_normal_clr
+								8
+								8
+							
+							
+								reg_w_swap_clr
+								1
+								1
+							
+							
+								rfifo_pop
+								0
+								0
+							
+						
+					
+					
+						mjpeg_frame_size
+						mjpeg_frame_size.
+						0x24
+						
+							
+								reg_frame_hblk
+								16
+								27
+							
+							
+								reg_frame_wblk
+								0
+								11
+							
+						
+					
+					
+						mjpeg_header_byte
+						mjpeg_header_byte.
+						0x28
+						
+							
+								reg_tail_exp
+								16
+								16
+							
+							
+								reg_head_byte
+								0
+								11
+							
+						
+					
+					
+						mjpeg_swap_mode
+						mjpeg_swap_mode.
+						0x30
+						
+							
+								sts_swap_fend
+								12
+								12
+							
+							
+								sts_swap_fstart
+								11
+								11
+							
+							
+								sts_read_swap_idx
+								10
+								10
+							
+							
+								sts_swap1_full
+								9
+								9
+							
+							
+								sts_swap0_full
+								8
+								8
+							
+							
+								reg_w_swap_mode
+								0
+								0
+							
+						
+					
+					
+						mjpeg_swap_bit_cnt
+						mjpeg_swap_bit_cnt.
+						0x34
+						
+							
+								frame_swap_end_bit_cnt
+								0
+								31
+							
+						
+					
+					
+						mjpeg_paket_ctrl
+						mjpeg_paket_ctrl.
+						0x38
+						
+							
+								reg_pket_body_byte
+								16
+								31
+							
+							
+								reg_jend_to_pend
+								1
+								1
+							
+							
+								reg_pket_en
+								0
+								0
+							
+						
+					
+					
+						mjpeg_paket_head_tail
+						mjpeg_paket_head_tail.
+						0x3C
+						
+							
+								reg_pket_tail_byte
+								16
+								27
+							
+							
+								reg_pket_head_byte
+								0
+								11
+							
+						
+					
+					
+						mjpeg_Y_frame_read_status_1
+						mjpeg_Y_frame_read_status_1.
+						0x40
+						
+							
+								yy_frm_hblk_r
+								16
+								28
+							
+							
+								yy_mem_hblk_r
+								0
+								12
+							
+						
+					
+					
+						mjpeg_Y_frame_read_status_2
+						mjpeg_Y_frame_read_status_2.
+						0x44
+						
+							
+								yy_frm_cnt_r
+								24
+								31
+							
+							
+								yy_mem_rnd_r
+								16
+								23
+							
+							
+								yy_wblk_r
+								0
+								12
+							
+						
+					
+					
+						mjpeg_Y_frame_write_status
+						mjpeg_Y_frame_write_status.
+						0x48
+						
+							
+								yy_frm_cnt_w
+								24
+								31
+							
+							
+								yy_mem_rnd_w
+								16
+								23
+							
+							
+								yy_mem_hblk_w
+								0
+								12
+							
+						
+					
+					
+						mjpeg_UV_frame_read_status_1
+						mjpeg_UV_frame_read_status_1.
+						0x4C
+						
+							
+								uv_frm_hblk_r
+								16
+								28
+							
+							
+								uv_mem_hblk_r
+								0
+								12
+							
+						
+					
+					
+						mjpeg_UV_frame_read_status_2
+						mjpeg_UV_frame_read_status_2.
+						0x50
+						
+							
+								uv_frm_cnt_r
+								24
+								31
+							
+							
+								uv_mem_rnd_r
+								16
+								23
+							
+							
+								uv_wblk_r
+								0
+								12
+							
+						
+					
+					
+						mjpeg_UV_frame_write_status
+						mjpeg_UV_frame_write_status.
+						0x54
+						
+							
+								uv_frm_cnt_w
+								24
+								31
+							
+							
+								uv_mem_rnd_w
+								16
+								23
+							
+							
+								uv_mem_hblk_w
+								0
+								12
+							
+						
+					
+					
+						mjpeg_start_addr0
+						mjpeg_start_addr0.
+						0x80
+						
+							
+								frame_start_addr_0
+								0
+								31
+							
+						
+					
+					
+						mjpeg_bit_cnt0
+						mjpeg_bit_cnt0.
+						0x84
+						
+							
+								frame_bit_cnt_0
+								0
+								31
+							
+						
+					
+					
+						mjpeg_start_addr1
+						mjpeg_start_addr1.
+						0x88
+						
+							
+								frame_start_addr_1
+								0
+								31
+							
+						
+					
+					
+						mjpeg_bit_cnt1
+						mjpeg_bit_cnt1.
+						0x8C
+						
+							
+								frame_bit_cnt_1
+								0
+								31
+							
+						
+					
+					
+						mjpeg_start_addr2
+						mjpeg_start_addr2.
+						0x90
+						
+							
+								frame_start_addr_2
+								0
+								31
+							
+						
+					
+					
+						mjpeg_bit_cnt2
+						mjpeg_bit_cnt2.
+						0x94
+						
+							
+								frame_bit_cnt_2
+								0
+								31
+							
+						
+					
+					
+						mjpeg_start_addr3
+						mjpeg_start_addr3.
+						0x98
+						
+							
+								frame_start_addr_3
+								0
+								31
+							
+						
+					
+					
+						mjpeg_bit_cnt3
+						mjpeg_bit_cnt3.
+						0x9C
+						
+							
+								frame_bit_cnt_3
+								0
+								31
+							
+						
+					
+					
+						mjpeg_start_addr4
+						mjpeg_start_addr4.
+						0xA0
+						
+							
+								frame_start_addr_4
+								0
+								31
+							
+						
+					
+					
+						mjpeg_bit_cnt4
+						mjpeg_bit_cnt4.
+						0xA4
+						
+							
+								frame_bit_cnt_4
+								0
+								31
+							
+						
+					
+					
+						mjpeg_start_addr5
+						mjpeg_start_addr5.
+						0xA8
+						
+							
+								frame_start_addr_5
+								0
+								31
+							
+						
+					
+					
+						mjpeg_bit_cnt5
+						mjpeg_bit_cnt5.
+						0xAC
+						
+							
+								frame_bit_cnt_5
+								0
+								31
+							
+						
+					
+					
+						mjpeg_start_addr6
+						mjpeg_start_addr6.
+						0xB0
+						
+							
+								frame_start_addr_6
+								0
+								31
+							
+						
+					
+					
+						mjpeg_bit_cnt6
+						mjpeg_bit_cnt6.
+						0xB4
+						
+							
+								frame_bit_cnt_6
+								0
+								31
+							
+						
+					
+					
+						mjpeg_start_addr7
+						mjpeg_start_addr7.
+						0xB8
+						
+							
+								frame_start_addr_7
+								0
+								31
+							
+						
+					
+					
+						mjpeg_bit_cnt7
+						mjpeg_bit_cnt7.
+						0xBC
+						
+							
+								frame_bit_cnt_7
+								0
+								31
+							
+						
+					
+					
+						mjpeg_start_addr_8
+						mjpeg_start_addr_8.
+						0xC0
+						
+							
+								frame_start_addr_8
+								0
+								31
+							
+						
+					
+					
+						mjpeg_bit_cnt_8
+						mjpeg_bit_cnt_8.
+						0xC4
+						
+							
+								frame_bit_cnt_8
+								0
+								31
+							
+						
+					
+					
+						mjpeg_start_addr_9
+						mjpeg_start_addr_9.
+						0xC8
+						
+							
+								frame_start_addr_9
+								0
+								31
+							
+						
+					
+					
+						mjpeg_bit_cnt_9
+						mjpeg_bit_cnt_9.
+						0xCC
+						
+							
+								frame_bit_cnt_9
+								0
+								31
+							
+						
+					
+					
+						mjpeg_start_addr_a
+						mjpeg_start_addr_a.
+						0xD0
+						
+							
+								frame_start_addr_a
+								0
+								31
+							
+						
+					
+					
+						mjpeg_bit_cnt_a
+						mjpeg_bit_cnt_a.
+						0xD4
+						
+							
+								frame_bit_cnt_a
+								0
+								31
+							
+						
+					
+					
+						mjpeg_start_addr_b
+						mjpeg_start_addr_b.
+						0xD8
+						
+							
+								frame_start_addr_b
+								0
+								31
+							
+						
+					
+					
+						mjpeg_bit_cnt_b
+						mjpeg_bit_cnt_b.
+						0xDC
+						
+							
+								frame_bit_cnt_b
+								0
+								31
+							
+						
+					
+					
+						mjpeg_start_addr_c
+						mjpeg_start_addr_c.
+						0xE0
+						
+							
+								frame_start_addr_c
+								0
+								31
+							
+						
+					
+					
+						mjpeg_bit_cnt_c
+						mjpeg_bit_cnt_c.
+						0xE4
+						
+							
+								frame_bit_cnt_c
+								0
+								31
+							
+						
+					
+					
+						mjpeg_start_addr_d
+						mjpeg_start_addr_d.
+						0xE8
+						
+							
+								frame_start_addr_d
+								0
+								31
+							
+						
+					
+					
+						mjpeg_bit_cnt_d
+						mjpeg_bit_cnt_d.
+						0xEC
+						
+							
+								frame_bit_cnt_d
+								0
+								31
+							
+						
+					
+					
+						mjpeg_start_addr_e
+						mjpeg_start_addr_e.
+						0xF0
+						
+							
+								frame_start_addr_e
+								0
+								31
+							
+						
+					
+					
+						mjpeg_bit_cnt_e
+						mjpeg_bit_cnt_e.
+						0xF4
+						
+							
+								frame_bit_cnt_e
+								0
+								31
+							
+						
+					
+					
+						mjpeg_start_addr_f
+						mjpeg_start_addr_f.
+						0xF8
+						
+							
+								frame_start_addr_f
+								0
+								31
+							
+						
+					
+					
+						mjpeg_bit_cnt_f
+						mjpeg_bit_cnt_f.
+						0xFC
+						
+							
+								frame_bit_cnt_f
+								0
+								31
+							
+						
+					
+					
+						mjpeg_q_mode0
+						mjpeg_q_mode0.
+						0x100
+						
+							
+								frame_q_mode_0
+								0
+								6
+							
+						
+					
+					
+						mjpeg_q_mode1
+						mjpeg_q_mode1.
+						0x104
+						
+							
+								frame_q_mode_1
+								0
+								6
+							
+						
+					
+					
+						mjpeg_q_mode2
+						mjpeg_q_mode2.
+						0x108
+						
+							
+								frame_q_mode_2
+								0
+								6
+							
+						
+					
+					
+						mjpeg_q_mode3
+						mjpeg_q_mode3.
+						0x10C
+						
+							
+								frame_q_mode_3
+								0
+								6
+							
+						
+					
+					
+						mjpeg_q_mode4
+						mjpeg_q_mode4.
+						0x110
+						
+							
+								frame_q_mode_4
+								0
+								6
+							
+						
+					
+					
+						mjpeg_q_mode5
+						mjpeg_q_mode5.
+						0x114
+						
+							
+								frame_q_mode_5
+								0
+								6
+							
+						
+					
+					
+						mjpeg_q_mode6
+						mjpeg_q_mode6.
+						0x118
+						
+							
+								frame_q_mode_6
+								0
+								6
+							
+						
+					
+					
+						mjpeg_q_mode7
+						mjpeg_q_mode7.
+						0x11C
+						
+							
+								frame_q_mode_7
+								0
+								6
+							
+						
+					
+					
+						mjpeg_q_mode_8
+						mjpeg_q_mode_8.
+						0x120
+						
+							
+								frame_q_mode_8
+								0
+								6
+							
+						
+					
+					
+						mjpeg_q_mode_9
+						mjpeg_q_mode_9.
+						0x124
+						
+							
+								frame_q_mode_9
+								0
+								6
+							
+						
+					
+					
+						mjpeg_q_mode_a
+						mjpeg_q_mode_a.
+						0x128
+						
+							
+								frame_q_mode_a
+								0
+								6
+							
+						
+					
+					
+						mjpeg_q_mode_b
+						mjpeg_q_mode_b.
+						0x12C
+						
+							
+								frame_q_mode_b
+								0
+								6
+							
+						
+					
+					
+						mjpeg_q_mode_c
+						mjpeg_q_mode_c.
+						0x130
+						
+							
+								frame_q_mode_c
+								0
+								6
+							
+						
+					
+					
+						mjpeg_q_mode_d
+						mjpeg_q_mode_d.
+						0x134
+						
+							
+								frame_q_mode_d
+								0
+								6
+							
+						
+					
+					
+						mjpeg_q_mode_e
+						mjpeg_q_mode_e.
+						0x138
+						
+							
+								frame_q_mode_e
+								0
+								6
+							
+						
+					
+					
+						mjpeg_q_mode_f
+						mjpeg_q_mode_f.
+						0x13C
+						
+							
+								frame_q_mode_f
+								0
+								6
+							
+						
+					
+					
+						mjpeg_debug
+						mjpeg_debug.
+						0x1F0
+						
+							
+								reg_mjpeg_dbg_sel
+								4
+								7
+							
+							
+								reg_mjpeg_dbg_en
+								0
+								0
+							
+						
+					
+					
+						mjpeg_dummy_reg
+						mjpeg_dummy_reg.
+						0x1FC
+						
+							
+								mjpeg_dummy_reg
+								0
+								31
+							
+						
+					
+				
+			
+			
+				sf_ctrl
+				sf_ctrl.
+				0x4000B000
+				sf_ctrl
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						sf_ctrl_0
+						sf_ctrl_0.
+						0x0
+						
+							
+								sf_id
+								24
+								31
+							
+							
+								sf_aes_iv_endian
+								23
+								23
+							
+							
+								sf_aes_key_endian
+								22
+								22
+							
+							
+								sf_aes_ctr_plus_en
+								21
+								21
+							
+							
+								sf_aes_dout_endian
+								20
+								20
+							
+							
+								sf_aes_dly_mode
+								19
+								19
+							
+							
+								sf_if_int_set
+								18
+								18
+							
+							
+								sf_if_int_clr
+								17
+								17
+							
+							
+								sf_if_int
+								16
+								16
+							
+							
+								sf_if_read_dly_en
+								11
+								11
+							
+							
+								sf_if_read_dly_n
+								8
+								10
+							
+							
+								sf_clk_sahb_sram_sel
+								5
+								5
+							
+							
+								sf_clk_out_inv_sel
+								4
+								4
+							
+							
+								sf_clk_out_gate_en
+								3
+								3
+							
+							
+								sf_clk_sf_rx_inv_sel
+								2
+								2
+							
+						
+					
+					
+						sf_ctrl_1
+						sf_ctrl_1.
+						0x4
+						
+							
+								sf_ahb2sram_en
+								31
+								31
+							
+							
+								sf_ahb2sif_en
+								30
+								30
+							
+							
+								sf_if_en
+								29
+								29
+							
+							
+								sf_if_fn_sel
+								28
+								28
+							
+							
+								sf_ahb2sif_stop
+								27
+								27
+							
+							
+								sf_ahb2sif_stopped
+								26
+								26
+							
+							
+								sf_if_reg_wp
+								25
+								25
+							
+							
+								sf_if_reg_hold
+								24
+								24
+							
+							
+								sf_if_0_ack_lat
+								20
+								22
+							
+							
+								sf_if_sr_int_set
+								18
+								18
+							
+							
+								sf_if_sr_int_en
+								17
+								17
+							
+							
+								sf_if_sr_int
+								16
+								16
+							
+							
+								sf_if_sr_pat
+								8
+								15
+							
+							
+								sf_if_sr_pat_mask
+								0
+								7
+							
+						
+					
+					
+						sf_if_sahb_0
+						sf_if_sahb_0.
+						0x8
+						
+							
+								sf_if_0_qpi_mode_en
+								31
+								31
+							
+							
+								sf_if_0_spi_mode
+								28
+								30
+							
+							
+								sf_if_0_cmd_en
+								27
+								27
+							
+							
+								sf_if_0_adr_en
+								26
+								26
+							
+							
+								sf_if_0_dmy_en
+								25
+								25
+							
+							
+								sf_if_0_dat_en
+								24
+								24
+							
+							
+								sf_if_0_dat_rw  
+								23
+								23
+							
+							
+								sf_if_0_cmd_byte
+								20
+								22
+							
+							
+								sf_if_0_adr_byte
+								17
+								19
+							
+							
+								sf_if_0_dmy_byte
+								12
+								16
+							
+							
+								sf_if_0_dat_byte
+								2
+								11
+							
+							
+								sf_if_0_trig
+								1
+								1
+							
+							
+								sf_if_busy
+								0
+								0
+							
+						
+					
+					
+						sf_if_sahb_1
+						sf_if_sahb_1.
+						0xC
+						
+							
+								sf_if_0_cmd_buf_0
+								0
+								31
+							
+						
+					
+					
+						sf_if_sahb_2
+						sf_if_sahb_2.
+						0x10
+						
+							
+								sf_if_0_cmd_buf_1
+								0
+								31
+							
+						
+					
+					
+						sf_if_iahb_0
+						sf_if_iahb_0.
+						0x14
+						
+							
+								sf_if_1_qpi_mode_en
+								31
+								31
+							
+							
+								sf_if_1_spi_mode
+								28
+								30
+							
+							
+								sf_if_1_cmd_en
+								27
+								27
+							
+							
+								sf_if_1_adr_en
+								26
+								26
+							
+							
+								sf_if_1_dmy_en
+								25
+								25
+							
+							
+								sf_if_1_dat_en
+								24
+								24
+							
+							
+								sf_if_1_dat_rw  
+								23
+								23
+							
+							
+								sf_if_1_cmd_byte
+								20
+								22
+							
+							
+								sf_if_1_adr_byte
+								17
+								19
+							
+							
+								sf_if_1_dmy_byte
+								12
+								16
+							
+						
+					
+					
+						sf_if_iahb_1
+						sf_if_iahb_1.
+						0x18
+						
+							
+								sf_if_1_cmd_buf_0
+								0
+								31
+							
+						
+					
+					
+						sf_if_iahb_2
+						sf_if_iahb_2.
+						0x1C
+						
+							
+								sf_if_1_cmd_buf_1
+								0
+								31
+							
+						
+					
+					
+						sf_if_status_0
+						sf_if_status_0.
+						0x20
+						
+							
+								sf_if_status_0
+								0
+								31
+							
+						
+					
+					
+						sf_if_status_1
+						sf_if_status_1.
+						0x24
+						
+							
+								sf_if_status_1
+								0
+								31
+							
+						
+					
+					
+						sf_aes
+						sf_aes.
+						0x28
+						
+							
+								sf_aes_status
+								5
+								31
+							
+							
+								sf_aes_pref_busy
+								4
+								4
+							
+							
+								sf_aes_pref_trig
+								3
+								3
+							
+							
+								sf_aes_mode
+								1
+								2
+							
+							
+								sf_aes_en
+								0
+								0
+							
+						
+					
+					
+						sf_ahb2sif_status
+						sf_ahb2sif_status.
+						0x2C
+						
+							
+								sf_ahb2sif_status
+								0
+								31
+							
+						
+					
+					
+						sf_if_io_dly_0
+						sf_if_io_dly_0.
+						0x30
+						
+							
+								sf_dqs_do_dly_sel
+								30
+								31
+							
+							
+								sf_dqs_di_dly_sel
+								28
+								29
+							
+							
+								sf_dqs_oe_dly_sel
+								26
+								27
+							
+							
+								sf_clk_out_dly_sel
+								8
+								9
+							
+							
+								sf_cs2_dly_sel
+								2
+								3
+							
+							
+								sf_cs_dly_sel
+								0
+								1
+							
+						
+					
+					
+						sf_if_io_dly_1
+						sf_if_io_dly_1.
+						0x34
+						
+							
+								sf_io_0_do_dly_sel
+								16
+								17
+							
+							
+								sf_io_0_di_dly_sel
+								8
+								9
+							
+							
+								sf_io_0_oe_dly_sel
+								0
+								1
+							
+						
+					
+					
+						sf_if_io_dly_2
+						sf_if_io_dly_2.
+						0x38
+						
+							
+								sf_io_1_do_dly_sel
+								16
+								17
+							
+							
+								sf_io_1_di_dly_sel
+								8
+								9
+							
+							
+								sf_io_1_oe_dly_sel
+								0
+								1
+							
+						
+					
+					
+						sf_if_io_dly_3
+						sf_if_io_dly_3.
+						0x3C
+						
+							
+								sf_io_2_do_dly_sel
+								16
+								17
+							
+							
+								sf_io_2_di_dly_sel
+								8
+								9
+							
+							
+								sf_io_2_oe_dly_sel
+								0
+								1
+							
+						
+					
+					
+						sf_if_io_dly_4
+						sf_if_io_dly_4.
+						0x40
+						
+							
+								sf_io_3_do_dly_sel
+								16
+								17
+							
+							
+								sf_io_3_di_dly_sel
+								8
+								9
+							
+							
+								sf_io_3_oe_dly_sel
+								0
+								1
+							
+						
+					
+					
+						sf_reserved
+						sf_reserved.
+						0x44
+						
+							
+								sf_reserved
+								0
+								31
+							
+						
+					
+					
+						sf2_if_io_dly_0
+						sf2_if_io_dly_0.
+						0x48
+						
+							
+								sf2_dqs_do_dly_sel
+								30
+								31
+							
+							
+								sf2_dqs_di_dly_sel
+								28
+								29
+							
+							
+								sf2_dqs_oe_dly_sel
+								26
+								27
+							
+							
+								sf2_clk_out_dly_sel
+								8
+								9
+							
+							
+								sf2_cs2_dly_sel
+								2
+								3
+							
+							
+								sf2_cs_dly_sel
+								0
+								1
+							
+						
+					
+					
+						sf2_if_io_dly_1
+						sf2_if_io_dly_1.
+						0x4C
+						
+							
+								sf2_io_0_do_dly_sel
+								16
+								17
+							
+							
+								sf2_io_0_di_dly_sel
+								8
+								9
+							
+							
+								sf2_io_0_oe_dly_sel
+								0
+								1
+							
+						
+					
+					
+						sf2_if_io_dly_2
+						sf2_if_io_dly_2.
+						0x50
+						
+							
+								sf2_io_1_do_dly_sel
+								16
+								17
+							
+							
+								sf2_io_1_di_dly_sel
+								8
+								9
+							
+							
+								sf2_io_1_oe_dly_sel
+								0
+								1
+							
+						
+					
+					
+						sf2_if_io_dly_3
+						sf2_if_io_dly_3.
+						0x54
+						
+							
+								sf2_io_2_do_dly_sel
+								16
+								17
+							
+							
+								sf2_io_2_di_dly_sel
+								8
+								9
+							
+							
+								sf2_io_2_oe_dly_sel
+								0
+								1
+							
+						
+					
+					
+						sf2_if_io_dly_4
+						sf2_if_io_dly_4.
+						0x58
+						
+							
+								sf2_io_3_do_dly_sel
+								16
+								17
+							
+							
+								sf2_io_3_di_dly_sel
+								8
+								9
+							
+							
+								sf2_io_3_oe_dly_sel
+								0
+								1
+							
+						
+					
+					
+						sf3_if_io_dly_0
+						sf3_if_io_dly_0.
+						0x5C
+						
+							
+								sf3_dqs_do_dly_sel
+								30
+								31
+							
+							
+								sf3_dqs_di_dly_sel
+								28
+								29
+							
+							
+								sf3_dqs_oe_dly_sel
+								26
+								27
+							
+							
+								sf3_clk_out_dly_sel
+								8
+								9
+							
+							
+								sf3_cs2_dly_sel
+								2
+								3
+							
+							
+								sf3_cs_dly_sel
+								0
+								1
+							
+						
+					
+					
+						sf3_if_io_dly_1
+						sf3_if_io_dly_1.
+						0x60
+						
+							
+								sf3_io_0_do_dly_sel
+								16
+								17
+							
+							
+								sf3_io_0_di_dly_sel
+								8
+								9
+							
+							
+								sf3_io_0_oe_dly_sel
+								0
+								1
+							
+						
+					
+					
+						sf3_if_io_dly_2
+						sf3_if_io_dly_2.
+						0x64
+						
+							
+								sf3_io_1_do_dly_sel
+								16
+								17
+							
+							
+								sf3_io_1_di_dly_sel
+								8
+								9
+							
+							
+								sf3_io_1_oe_dly_sel
+								0
+								1
+							
+						
+					
+					
+						sf3_if_io_dly_3
+						sf3_if_io_dly_3.
+						0x68
+						
+							
+								sf3_io_2_do_dly_sel
+								16
+								17
+							
+							
+								sf3_io_2_di_dly_sel
+								8
+								9
+							
+							
+								sf3_io_2_oe_dly_sel
+								0
+								1
+							
+						
+					
+					
+						sf3_if_io_dly_4
+						sf3_if_io_dly_4.
+						0x6C
+						
+							
+								sf3_io_3_do_dly_sel
+								16
+								17
+							
+							
+								sf3_io_3_di_dly_sel
+								8
+								9
+							
+							
+								sf3_io_3_oe_dly_sel
+								0
+								1
+							
+						
+					
+					
+						sf_ctrl_2
+						sf_ctrl_2.
+						0x70
+						
+							
+								sf_if_0_bk_sel
+								31
+								31
+							
+							
+								sf_if_bk2_en
+								30
+								30
+							
+							
+								sf_if_bk2_mode
+								29
+								29
+							
+							
+								sf_if_bk_swap
+								28
+								28
+							
+							
+								sf_if_dqs_en
+								5
+								5
+							
+							
+								sf_if_dtr_en
+								4
+								4
+							
+							
+								sf_if_pad_sel_lock
+								3
+								3
+							
+							
+								sf_if_pad_sel
+								0
+								1
+							
+						
+					
+					
+						sf_ctrl_3
+						sf_ctrl_3.
+						0x74
+						
+							
+								sf_if_1_ack_lat
+								29
+								31
+							
+							
+								sf_cmds_wrap_q
+								11
+								11
+							
+							
+								sf_cmds_wrap_mode
+								10
+								10
+							
+							
+								sf_cmds_wrap_q_ini
+								9
+								9
+							
+							
+								sf_cmds_bt_en
+								8
+								8
+							
+							
+								sf_cmds_bt_dly
+								5
+								7
+							
+							
+								sf_cmds_en
+								4
+								4
+							
+							
+								sf_cmds_wrap_len
+								0
+								3
+							
+						
+					
+					
+						sf_if_iahb_3
+						sf_if_iahb_3.
+						0x78
+						
+							
+								sf_if_2_qpi_mode_en
+								31
+								31
+							
+							
+								sf_if_2_spi_mode
+								28
+								30
+							
+							
+								sf_if_2_cmd_en
+								27
+								27
+							
+							
+								sf_if_2_adr_en
+								26
+								26
+							
+							
+								sf_if_2_dmy_en
+								25
+								25
+							
+							
+								sf_if_2_dat_en
+								24
+								24
+							
+							
+								sf_if_2_dat_rw  
+								23
+								23
+							
+							
+								sf_if_2_cmd_byte
+								20
+								22
+							
+							
+								sf_if_2_adr_byte
+								17
+								19
+							
+							
+								sf_if_2_dmy_byte
+								12
+								16
+							
+						
+					
+					
+						sf_if_iahb_4
+						sf_if_iahb_4.
+						0x7C
+						
+							
+								sf_if_2_cmd_buf_0
+								0
+								31
+							
+						
+					
+					
+						sf_if_iahb_5
+						sf_if_iahb_5.
+						0x80
+						
+							
+								sf_if_2_cmd_buf_1
+								0
+								31
+							
+						
+					
+					
+						sf_if_iahb_6
+						sf_if_iahb_6.
+						0x84
+						
+							
+								sf_if_3_qpi_mode_en
+								31
+								31
+							
+							
+								sf_if_3_spi_mode
+								28
+								30
+							
+							
+								sf_if_3_cmd_en
+								27
+								27
+							
+							
+								sf_if_3_adr_en
+								26
+								26
+							
+							
+								sf_if_3_cmd_byte
+								20
+								22
+							
+							
+								sf_if_3_adr_byte
+								17
+								19
+							
+						
+					
+					
+						sf_if_iahb_7
+						sf_if_iahb_7.
+						0x88
+						
+							
+								sf_if_3_cmd_buf_0
+								0
+								31
+							
+						
+					
+					
+						sf_if_iahb_8
+						sf_if_iahb_8.
+						0x8C
+						
+							
+								sf_if_3_cmd_buf_1
+								0
+								31
+							
+						
+					
+					
+						sf_if_iahb_9
+						sf_if_iahb_9.
+						0x90
+						
+							
+								sf_if_4_qpi_mode_en
+								31
+								31
+							
+							
+								sf_if_4_spi_mode
+								28
+								30
+							
+							
+								sf_if_4_cmd_en
+								27
+								27
+							
+							
+								sf_if_4_adr_en
+								26
+								26
+							
+							
+								sf_if_4_dmy_en
+								25
+								25
+							
+							
+								sf_if_4_dat_en
+								24
+								24
+							
+							
+								sf_if_4_dat_rw  
+								23
+								23
+							
+							
+								sf_if_4_cmd_byte
+								20
+								22
+							
+							
+								sf_if_4_adr_byte
+								17
+								19
+							
+							
+								sf_if_4_dmy_byte
+								12
+								16
+							
+						
+					
+					
+						sf_if_iahb_10
+						sf_if_iahb_10.
+						0x94
+						
+							
+								sf_if_4_cmd_buf_0
+								0
+								31
+							
+						
+					
+					
+						sf_if_iahb_11
+						sf_if_iahb_11.
+						0x98
+						
+							
+								sf_if_4_cmd_buf_1
+								0
+								31
+							
+						
+					
+					
+						sf_if_iahb_12
+						sf_if_iahb_12.
+						0x9C
+						
+							
+								sf2_if_read_dly_src
+								12
+								12
+							
+							
+								sf2_if_read_dly_en
+								11
+								11
+							
+							
+								sf2_if_read_dly_n
+								8
+								10
+							
+							
+								sf3_clk_out_inv_sel
+								5
+								5
+							
+							
+								sf2_clk_out_inv_sel
+								4
+								4
+							
+							
+								sf2_clk_sf_rx_inv_src
+								3
+								3
+							
+							
+								sf2_clk_sf_rx_inv_sel
+								2
+								2
+							
+						
+					
+					
+						sf_ctrl_prot_en_rd
+						sf_ctrl_prot_en_rd.
+						0x100
+						
+							
+								sf_dbg_dis
+								31
+								31
+							
+							
+								sf_if_0_trig_wr_lock
+								30
+								30
+							
+							
+								sf_ctrl_id1_en_rd
+								2
+								2
+							
+							
+								sf_ctrl_id0_en_rd
+								1
+								1
+							
+							
+								sf_ctrl_prot_en_rd
+								0
+								0
+							
+						
+					
+					
+						sf_ctrl_prot_en
+						sf_ctrl_prot_en.
+						0x104
+						
+							
+								sf_ctrl_id1_en
+								2
+								2
+							
+							
+								sf_ctrl_id0_en
+								1
+								1
+							
+							
+								sf_ctrl_prot_en
+								0
+								0
+							
+						
+					
+					
+						sf_aes_key_r0_0
+						sf_aes_key_r0_0.
+						0x200
+						
+							
+								sf_aes_key_r0_0
+								0
+								31
+							
+						
+					
+					
+						sf_aes_key_r0_1
+						sf_aes_key_r0_1.
+						0x204
+						
+							
+								sf_aes_key_r0_1
+								0
+								31
+							
+						
+					
+					
+						sf_aes_key_r0_2
+						sf_aes_key_r0_2.
+						0x208
+						
+							
+								sf_aes_key_r0_2
+								0
+								31
+							
+						
+					
+					
+						sf_aes_key_r0_3
+						sf_aes_key_r0_3.
+						0x20C
+						
+							
+								sf_aes_key_r0_3
+								0
+								31
+							
+						
+					
+					
+						sf_aes_key_r0_4
+						sf_aes_key_r0_4.
+						0x210
+						
+							
+								sf_aes_key_r0_4
+								0
+								31
+							
+						
+					
+					
+						sf_aes_key_r0_5
+						sf_aes_key_r0_5.
+						0x214
+						
+							
+								sf_aes_key_r0_5
+								0
+								31
+							
+						
+					
+					
+						sf_aes_key_r0_6
+						sf_aes_key_r0_6.
+						0x218
+						
+							
+								sf_aes_key_r0_6
+								0
+								31
+							
+						
+					
+					
+						sf_aes_key_r0_7
+						sf_aes_key_r0_7.
+						0x21C
+						
+							
+								sf_aes_key_r0_7
+								0
+								31
+							
+						
+					
+					
+						sf_aes_iv_r0_w0
+						sf_aes_iv_r0_w0.
+						0x220
+						
+							
+								sf_aes_iv_r0_w0
+								0
+								31
+							
+						
+					
+					
+						sf_aes_iv_r0_w1
+						sf_aes_iv_r0_w1.
+						0x224
+						
+							
+								sf_aes_iv_r0_w1
+								0
+								31
+							
+						
+					
+					
+						sf_aes_iv_r0_w2
+						sf_aes_iv_r0_w2.
+						0x228
+						
+							
+								sf_aes_iv_r0_w2
+								0
+								31
+							
+						
+					
+					
+						sf_aes_iv_r0_w3
+						sf_aes_iv_r0_w3.
+						0x22C
+						
+							
+								sf_aes_iv_r0_w3
+								0
+								31
+							
+						
+					
+					
+						sf_aes_cfg_r0
+						sf_aes_cfg_r0.
+						0x230
+						
+							
+								sf_aes_region_r0_lock
+								31
+								31
+							
+							
+								sf_aes_region_r0_en
+								30
+								30
+							
+							
+								sf_aes_region_r0_hw_key_en
+								29
+								29
+							
+							
+								sf_aes_region_r0_start
+								14
+								27
+							
+							
+								sf_aes_region_r0_end
+								0
+								13
+							
+						
+					
+					
+						sf_aes_key_r1_0
+						sf_aes_key_r1_0.
+						0x300
+						
+							
+								sf_aes_key_r1_0
+								0
+								31
+							
+						
+					
+					
+						sf_aes_key_r1_1
+						sf_aes_key_r1_1.
+						0x304
+						
+							
+								sf_aes_key_r1_1
+								0
+								31
+							
+						
+					
+					
+						sf_aes_key_r1_2
+						sf_aes_key_r1_2.
+						0x308
+						
+							
+								sf_aes_key_r1_2
+								0
+								31
+							
+						
+					
+					
+						sf_aes_key_r1_3
+						sf_aes_key_r1_3.
+						0x30C
+						
+							
+								sf_aes_key_r1_3
+								0
+								31
+							
+						
+					
+					
+						sf_aes_key_r1_4
+						sf_aes_key_r1_4.
+						0x310
+						
+							
+								sf_aes_key_r1_4
+								0
+								31
+							
+						
+					
+					
+						sf_aes_key_r1_5
+						sf_aes_key_r1_5.
+						0x314
+						
+							
+								sf_aes_key_r1_5
+								0
+								31
+							
+						
+					
+					
+						sf_aes_key_r1_6
+						sf_aes_key_r1_6.
+						0x318
+						
+							
+								sf_aes_key_r1_6
+								0
+								31
+							
+						
+					
+					
+						sf_aes_key_r1_7
+						sf_aes_key_r1_7.
+						0x31C
+						
+							
+								sf_aes_key_r1_7
+								0
+								31
+							
+						
+					
+					
+						sf_aes_iv_r1_w0
+						sf_aes_iv_r1_w0.
+						0x320
+						
+							
+								sf_aes_iv_r1_w0
+								0
+								31
+							
+						
+					
+					
+						sf_aes_iv_r1_w1
+						sf_aes_iv_r1_w1.
+						0x324
+						
+							
+								sf_aes_iv_r1_w1
+								0
+								31
+							
+						
+					
+					
+						sf_aes_iv_r1_w2
+						sf_aes_iv_r1_w2.
+						0x328
+						
+							
+								sf_aes_iv_r1_w2
+								0
+								31
+							
+						
+					
+					
+						sf_aes_iv_r1_w3
+						sf_aes_iv_r1_w3.
+						0x32C
+						
+							
+								sf_aes_iv_r1_w3
+								0
+								31
+							
+						
+					
+					
+						sf_aes_r1
+						sf_aes_r1.
+						0x330
+						
+							
+								sf_aes_r1_lock
+								31
+								31
+							
+							
+								sf_aes_r1_en
+								30
+								30
+							
+							
+								sf_aes_r1_hw_key_en
+								29
+								29
+							
+							
+								sf_aes_r1_start
+								14
+								27
+							
+							
+								sf_aes_r1_end
+								0
+								13
+							
+						
+					
+					
+						sf_aes_key_r2_0
+						sf_aes_key_r2_0.
+						0x400
+						
+							
+								sf_aes_key_r2_0
+								0
+								31
+							
+						
+					
+					
+						sf_aes_key_r2_1
+						sf_aes_key_r2_1.
+						0x404
+						
+							
+								sf_aes_key_r2_1
+								0
+								31
+							
+						
+					
+					
+						sf_aes_key_r2_2
+						sf_aes_key_r2_2.
+						0x408
+						
+							
+								sf_aes_key_r2_2
+								0
+								31
+							
+						
+					
+					
+						sf_aes_key_r2_3
+						sf_aes_key_r2_3.
+						0x40C
+						
+							
+								sf_aes_key_r2_3
+								0
+								31
+							
+						
+					
+					
+						sf_aes_key_r2_4
+						sf_aes_key_r2_4.
+						0x410
+						
+							
+								sf_aes_key_r2_4
+								0
+								31
+							
+						
+					
+					
+						sf_aes_key_r2_5
+						sf_aes_key_r2_5.
+						0x414
+						
+							
+								sf_aes_key_r2_5
+								0
+								31
+							
+						
+					
+					
+						sf_aes_key_r2_6
+						sf_aes_key_r2_6.
+						0x418
+						
+							
+								sf_aes_key_r2_6
+								0
+								31
+							
+						
+					
+					
+						sf_aes_key_r2_7
+						sf_aes_key_r2_7.
+						0x41C
+						
+							
+								sf_aes_key_r2_7
+								0
+								31
+							
+						
+					
+					
+						sf_aes_iv_r2_w0
+						sf_aes_iv_r2_w0.
+						0x420
+						
+							
+								sf_aes_iv_r2_w0
+								0
+								31
+							
+						
+					
+					
+						sf_aes_iv_r2_w1
+						sf_aes_iv_r2_w1.
+						0x424
+						
+							
+								sf_aes_iv_r2_w1
+								0
+								31
+							
+						
+					
+					
+						sf_aes_iv_r2_w2
+						sf_aes_iv_r2_w2.
+						0x428
+						
+							
+								sf_aes_iv_r2_w2
+								0
+								31
+							
+						
+					
+					
+						sf_aes_iv_r2_w3
+						sf_aes_iv_r2_w3.
+						0x42C
+						
+							
+								sf_aes_iv_r2_w3
+								0
+								31
+							
+						
+					
+					
+						sf_aes_r2
+						sf_aes_r2.
+						0x430
+						
+							
+								sf_aes_r2_lock
+								31
+								31
+							
+							
+								sf_aes_r2_en
+								30
+								30
+							
+							
+								sf_aes_r2_hw_key_en
+								29
+								29
+							
+							
+								sf_aes_r2_start
+								14
+								27
+							
+							
+								sf_aes_r2_end
+								0
+								13
+							
+						
+					
+					
+						sf_id0_offset
+						sf_id0_offset.
+						0x434
+						
+							
+								sf_id0_offset
+								0
+								23
+							
+						
+					
+					
+						sf_id1_offset
+						sf_id1_offset.
+						0x438
+						
+							
+								sf_id1_offset
+								0
+								23
+							
+						
+					
+					
+						sf_bk2_id0_offset
+						sf_bk2_id0_offset.
+						0x43C
+						
+							
+								sf_bk2_id0_offset
+								0
+								23
+							
+						
+					
+					
+						sf_bk2_id1_offset
+						sf_bk2_id1_offset.
+						0x440
+						
+							
+								sf_bk2_id1_offset
+								0
+								23
+							
+						
+					
+				
+			
+			
+				dma
+				dma.
+				0x40007000
+				dma
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						DMA_IntStatus
+						DMA_IntStatus.
+						0x0
+						
+							
+								IntStatus
+								0
+								7
+							
+						
+					
+					
+						DMA_IntTCStatus
+						DMA_IntTCStatus.
+						0x4
+						
+							
+								IntTCStatus
+								0
+								7
+							
+						
+					
+					
+						DMA_IntTCClear
+						DMA_IntTCClear.
+						0x8
+						
+							
+								IntTCClear
+								0
+								7
+							
+						
+					
+					
+						DMA_IntErrorStatus
+						DMA_IntErrorStatus.
+						0xC
+						
+							
+								IntErrorStatus
+								0
+								7
+							
+						
+					
+					
+						DMA_IntErrClr
+						DMA_IntErrClr.
+						0x10
+						
+							
+								IntErrClr
+								0
+								7
+							
+						
+					
+					
+						DMA_RawIntTCStatus
+						DMA_RawIntTCStatus.
+						0x14
+						
+							
+								RawIntTCStatus
+								0
+								7
+							
+						
+					
+					
+						DMA_RawIntErrorStatus
+						DMA_RawIntErrorStatus.
+						0x18
+						
+							
+								RawIntErrorStatus
+								0
+								7
+							
+						
+					
+					
+						DMA_EnbldChns
+						DMA_EnbldChns.
+						0x1C
+						
+							
+								EnabledChannels
+								0
+								7
+							
+						
+					
+					
+						DMA_SoftBReq
+						DMA_SoftBReq.
+						0x20
+						
+							
+								SoftBReq
+								0
+								31
+							
+						
+					
+					
+						DMA_SoftSReq
+						DMA_SoftSReq.
+						0x24
+						
+							
+								SoftSReq
+								0
+								31
+							
+						
+					
+					
+						DMA_SoftLBReq
+						DMA_SoftLBReq.
+						0x28
+						
+							
+								SoftLBReq
+								0
+								31
+							
+						
+					
+					
+						DMA_SoftLSReq
+						DMA_SoftLSReq.
+						0x2C
+						
+							
+								SoftLSReq
+								0
+								31
+							
+						
+					
+					
+						DMA_Top_Config
+						DMA_Top_Config.
+						0x30
+						
+							
+								M
+								1
+								1
+							
+							
+								E
+								0
+								0
+							
+						
+					
+					
+						DMA_Sync
+						DMA_Sync.
+						0x34
+						
+							
+								DMA_Sync
+								0
+								31
+							
+						
+					
+					
+						DMA_C0SrcAddr
+						DMA_C0SrcAddr.
+						0x100
+						
+							
+								SrcAddr
+								0
+								31
+							
+						
+					
+					
+						DMA_C0DstAddr
+						DMA_C0DstAddr.
+						0x104
+						
+							
+								DstAddr
+								0
+								31
+							
+						
+					
+					
+						DMA_C0LLI
+						DMA_C0LLI.
+						0x108
+						
+							
+								LLI
+								0
+								31
+							
+						
+					
+					
+						DMA_C0Control
+						DMA_C0Control.
+						0x10C
+						
+							
+								I
+								31
+								31
+							
+							
+								Prot
+								28
+								30
+							
+							
+								DI
+								27
+								27
+							
+							
+								SI
+								26
+								26
+							
+							
+								SLargerD
+								25
+								25
+							
+							
+								fix_cnt
+								23
+								24
+							
+							
+								DWidth
+								21
+								22
+							
+							
+								SWidth
+								18
+								19
+							
+							
+								dst_add_mode
+								17
+								17
+							
+							
+								DBSize
+								15
+								16
+							
+							
+								dst_min_mode
+								14
+								14
+							
+							
+								SBSize
+								12
+								13
+							
+							
+								TransferSize
+								0
+								11
+							
+						
+					
+					
+						DMA_C0Config
+						DMA_C0Config.
+						0x110
+						
+							
+								LLICounter
+								20
+								29
+							
+							
+								H
+								18
+								18
+							
+							
+								A
+								17
+								17
+							
+							
+								L
+								16
+								16
+							
+							
+								ITC
+								15
+								15
+							
+							
+								IE
+								14
+								14
+							
+							
+								FlowCntrl
+								11
+								13
+							
+							
+								DstPeripheral
+								6
+								10
+							
+							
+								SrcPeripheral
+								1
+								5
+							
+							
+								E
+								0
+								0
+							
+						
+					
+					
+						DMA_C1SrcAddr
+						DMA_C1SrcAddr.
+						0x200
+						
+							
+								SrcAddr
+								0
+								31
+							
+						
+					
+					
+						DMA_C1DstAddr
+						DMA_C1DstAddr.
+						0x204
+						
+							
+								DstAddr
+								0
+								31
+							
+						
+					
+					
+						DMA_C1LLI
+						DMA_C1LLI.
+						0x208
+						
+							
+								LLI
+								2
+								31
+							
+						
+					
+					
+						DMA_C1Control
+						DMA_C1Control.
+						0x20C
+						
+							
+								I
+								31
+								31
+							
+							
+								Prot
+								28
+								30
+							
+							
+								DI
+								27
+								27
+							
+							
+								SI
+								26
+								26
+							
+							
+								fix_cnt
+								23
+								24
+							
+							
+								DWidth
+								21
+								23
+							
+							
+								SWidth
+								18
+								20
+							
+							
+								dst_add_mode
+								17
+								17
+							
+							
+								DBSize
+								15
+								16
+							
+							
+								dst_min_mode
+								14
+								14
+							
+							
+								SBSize
+								12
+								13
+							
+							
+								TransferSize
+								0
+								11
+							
+						
+					
+					
+						DMA_C1Config
+						DMA_C1Config.
+						0x210
+						
+							
+								H
+								18
+								18
+							
+							
+								A
+								17
+								17
+							
+							
+								L
+								16
+								16
+							
+							
+								ITC
+								15
+								15
+							
+							
+								IE
+								14
+								14
+							
+							
+								FlowCntrl
+								11
+								13
+							
+							
+								DstPeripheral
+								6
+								10
+							
+							
+								SrcPeripheral
+								1
+								5
+							
+							
+								E
+								0
+								0
+							
+						
+					
+					
+						DMA_C2SrcAddr
+						DMA_C2SrcAddr.
+						0x300
+						
+							
+								SrcAddr
+								0
+								31
+							
+						
+					
+					
+						DMA_C2DstAddr
+						DMA_C2DstAddr.
+						0x304
+						
+							
+								DstAddr
+								0
+								31
+							
+						
+					
+					
+						DMA_C2LLI
+						DMA_C2LLI.
+						0x308
+						
+							
+								LLI
+								2
+								31
+							
+						
+					
+					
+						DMA_C2Control
+						DMA_C2Control.
+						0x30C
+						
+							
+								I
+								31
+								31
+							
+							
+								Prot
+								28
+								30
+							
+							
+								DI
+								27
+								27
+							
+							
+								SI
+								26
+								26
+							
+							
+								fix_cnt
+								23
+								24
+							
+							
+								DWidth
+								21
+								23
+							
+							
+								SWidth
+								18
+								20
+							
+							
+								dst_add_mode
+								17
+								17
+							
+							
+								DBSize
+								15
+								16
+							
+							
+								dst_min_mode
+								14
+								14
+							
+							
+								SBSize
+								12
+								13
+							
+							
+								TransferSize
+								0
+								11
+							
+						
+					
+					
+						DMA_C2Config
+						DMA_C2Config.
+						0x310
+						
+							
+								H
+								18
+								18
+							
+							
+								A
+								17
+								17
+							
+							
+								L
+								16
+								16
+							
+							
+								ITC
+								15
+								15
+							
+							
+								IE
+								14
+								14
+							
+							
+								FlowCntrl
+								11
+								13
+							
+							
+								DstPeripheral
+								6
+								10
+							
+							
+								SrcPeripheral
+								1
+								5
+							
+							
+								E
+								0
+								0
+							
+						
+					
+					
+						DMA_C3SrcAddr
+						DMA_C3SrcAddr.
+						0x400
+						
+							
+								SrcAddr
+								0
+								31
+							
+						
+					
+					
+						DMA_C3DstAddr
+						DMA_C3DstAddr.
+						0x404
+						
+							
+								DstAddr
+								0
+								31
+							
+						
+					
+					
+						DMA_C3LLI
+						DMA_C3LLI.
+						0x408
+						
+							
+								LLI
+								2
+								31
+							
+						
+					
+					
+						DMA_C3Control
+						DMA_C3Control.
+						0x40C
+						
+							
+								I
+								31
+								31
+							
+							
+								Prot
+								28
+								30
+							
+							
+								DI
+								27
+								27
+							
+							
+								SI
+								26
+								26
+							
+							
+								fix_cnt
+								23
+								24
+							
+							
+								DWidth
+								21
+								23
+							
+							
+								SWidth
+								18
+								20
+							
+							
+								dst_add_mode
+								17
+								17
+							
+							
+								DBSize
+								15
+								16
+							
+							
+								dst_min_mode
+								14
+								14
+							
+							
+								SBSize
+								12
+								13
+							
+							
+								TransferSize
+								0
+								11
+							
+						
+					
+					
+						DMA_C3Config
+						DMA_C3Config.
+						0x410
+						
+							
+								H
+								18
+								18
+							
+							
+								A
+								17
+								17
+							
+							
+								L
+								16
+								16
+							
+							
+								ITC
+								15
+								15
+							
+							
+								IE
+								14
+								14
+							
+							
+								FlowCntrl
+								11
+								13
+							
+							
+								DstPeripheral
+								6
+								10
+							
+							
+								SrcPeripheral
+								1
+								5
+							
+							
+								E
+								0
+								0
+							
+						
+					
+					
+						DMA_C4SrcAddr
+						DMA_C4SrcAddr.
+						0x500
+						
+							
+								SrcAddr
+								0
+								31
+							
+						
+					
+					
+						DMA_C4DstAddr
+						DMA_C4DstAddr.
+						0x504
+						
+							
+								DstAddr
+								0
+								31
+							
+						
+					
+					
+						DMA_C4LLI
+						DMA_C4LLI.
+						0x508
+						
+							
+								LLI
+								2
+								31
+							
+						
+					
+					
+						DMA_C4Control
+						DMA_C4Control.
+						0x50C
+						
+							
+								I
+								31
+								31
+							
+							
+								Prot
+								28
+								30
+							
+							
+								DI
+								27
+								27
+							
+							
+								SI
+								26
+								26
+							
+							
+								fix_cnt
+								23
+								24
+							
+							
+								DWidth
+								21
+								23
+							
+							
+								SWidth
+								18
+								20
+							
+							
+								dst_add_mode
+								17
+								17
+							
+							
+								DBSize
+								15
+								16
+							
+							
+								dst_min_mode
+								14
+								14
+							
+							
+								SBSize
+								12
+								13
+							
+							
+								TransferSize
+								0
+								11
+							
+						
+					
+					
+						DMA_C4Config
+						DMA_C4Config.
+						0x510
+						
+							
+								H
+								18
+								18
+							
+							
+								A
+								17
+								17
+							
+							
+								L
+								16
+								16
+							
+							
+								ITC
+								15
+								15
+							
+							
+								IE
+								14
+								14
+							
+							
+								FlowCntrl
+								11
+								13
+							
+							
+								DstPeripheral
+								6
+								10
+							
+							
+								SrcPeripheral
+								1
+								5
+							
+							
+								E
+								0
+								0
+							
+						
+					
+					
+						DMA_C5SrcAddr
+						DMA_C5SrcAddr.
+						0x600
+						
+							
+								SrcAddr
+								0
+								31
+							
+						
+					
+					
+						DMA_C5DstAddr
+						DMA_C5DstAddr.
+						0x604
+						
+							
+								DstAddr
+								0
+								31
+							
+						
+					
+					
+						DMA_C5LLI
+						DMA_C5LLI.
+						0x608
+						
+							
+								LLI
+								2
+								31
+							
+						
+					
+					
+						DMA_C5Control
+						DMA_C5Control.
+						0x60C
+						
+							
+								I
+								31
+								31
+							
+							
+								Prot
+								28
+								30
+							
+							
+								DI
+								27
+								27
+							
+							
+								SI
+								26
+								26
+							
+							
+								fix_cnt
+								23
+								24
+							
+							
+								DWidth
+								21
+								23
+							
+							
+								SWidth
+								18
+								20
+							
+							
+								dst_add_mode
+								17
+								17
+							
+							
+								DBSize
+								15
+								16
+							
+							
+								dst_min_mode
+								14
+								14
+							
+							
+								SBSize
+								12
+								13
+							
+							
+								TransferSize
+								0
+								11
+							
+						
+					
+					
+						DMA_C5Config
+						DMA_C5Config.
+						0x610
+						
+							
+								H
+								18
+								18
+							
+							
+								A
+								17
+								17
+							
+							
+								L
+								16
+								16
+							
+							
+								ITC
+								15
+								15
+							
+							
+								IE
+								14
+								14
+							
+							
+								FlowCntrl
+								11
+								13
+							
+							
+								DstPeripheral
+								6
+								10
+							
+							
+								SrcPeripheral
+								1
+								5
+							
+							
+								E
+								0
+								0
+							
+						
+					
+					
+						DMA_C6SrcAddr
+						DMA_C6SrcAddr.
+						0x700
+						
+							
+								SrcAddr
+								0
+								31
+							
+						
+					
+					
+						DMA_C6DstAddr
+						DMA_C6DstAddr.
+						0x704
+						
+							
+								DstAddr
+								0
+								31
+							
+						
+					
+					
+						DMA_C6LLI
+						DMA_C6LLI.
+						0x708
+						
+							
+								LLI
+								2
+								31
+							
+						
+					
+					
+						DMA_C6Control
+						DMA_C6Control.
+						0x70C
+						
+							
+								I
+								31
+								31
+							
+							
+								Prot
+								28
+								30
+							
+							
+								DI
+								27
+								27
+							
+							
+								SI
+								26
+								26
+							
+							
+								fix_cnt
+								23
+								24
+							
+							
+								DWidth
+								21
+								23
+							
+							
+								SWidth
+								18
+								20
+							
+							
+								dst_add_mode
+								17
+								17
+							
+							
+								DBSize
+								15
+								16
+							
+							
+								dst_min_mode
+								14
+								14
+							
+							
+								SBSize
+								12
+								13
+							
+							
+								TransferSize
+								0
+								11
+							
+						
+					
+					
+						DMA_C6Config
+						DMA_C6Config.
+						0x710
+						
+							
+								H
+								18
+								18
+							
+							
+								A
+								17
+								17
+							
+							
+								L
+								16
+								16
+							
+							
+								ITC
+								15
+								15
+							
+							
+								IE
+								14
+								14
+							
+							
+								FlowCntrl
+								11
+								13
+							
+							
+								DstPeripheral
+								6
+								10
+							
+							
+								SrcPeripheral
+								1
+								5
+							
+							
+								E
+								0
+								0
+							
+						
+					
+					
+						DMA_C7SrcAddr
+						DMA_C7SrcAddr.
+						0x800
+						
+							
+								SrcAddr
+								0
+								31
+							
+						
+					
+					
+						DMA_C7DstAddr
+						DMA_C7DstAddr.
+						0x804
+						
+							
+								DstAddr
+								0
+								31
+							
+						
+					
+					
+						DMA_C7LLI
+						DMA_C7LLI.
+						0x808
+						
+							
+								LLI
+								2
+								31
+							
+						
+					
+					
+						DMA_C7Control
+						DMA_C7Control.
+						0x80C
+						
+							
+								I
+								31
+								31
+							
+							
+								Prot
+								28
+								30
+							
+							
+								DI
+								27
+								27
+							
+							
+								SI
+								26
+								26
+							
+							
+								fix_cnt
+								23
+								24
+							
+							
+								DWidth
+								21
+								23
+							
+							
+								SWidth
+								18
+								20
+							
+							
+								dst_add_mode
+								17
+								17
+							
+							
+								DBSize
+								15
+								16
+							
+							
+								dst_min_mode
+								14
+								14
+							
+							
+								SBSize
+								12
+								13
+							
+							
+								TransferSize
+								0
+								11
+							
+						
+					
+					
+						DMA_C7Config
+						DMA_C7Config.
+						0x810
+						
+							
+								H
+								18
+								18
+							
+							
+								A
+								17
+								17
+							
+							
+								L
+								16
+								16
+							
+							
+								ITC
+								15
+								15
+							
+							
+								IE
+								14
+								14
+							
+							
+								FlowCntrl
+								11
+								13
+							
+							
+								DstPeripheral
+								6
+								10
+							
+							
+								SrcPeripheral
+								1
+								5
+							
+							
+								E
+								0
+								0
+							
+						
+					
+				
+			
+			
+				emac
+				emac.
+				0x4000D000
+				emac
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						MODE
+						MODE.
+						0x0
+						
+							
+								rsvd_23_18
+								18
+								23
+							
+							
+								RMII_EN
+								17
+								17
+							
+							
+								RECSMALL
+								16
+								16
+							
+							
+								PAD
+								15
+								15
+							
+							
+								HUGEN
+								14
+								14
+							
+							
+								CRCEN
+								13
+								13
+							
+							
+								rsvd_12_11
+								11
+								12
+							
+							
+								FULLD
+								10
+								10
+							
+							
+								rsvd_9_7
+								7
+								9
+							
+							
+								IFG
+								6
+								6
+							
+							
+								PRO
+								5
+								5
+							
+							
+								rsvd_4
+								4
+								4
+							
+							
+								BRO
+								3
+								3
+							
+							
+								NOPRE
+								2
+								2
+							
+							
+								TXEN
+								1
+								1
+							
+							
+								RXEN
+								0
+								0
+							
+						
+					
+					
+						INT_SOURCE
+						INT_SOURCE.
+						0x4
+						
+							
+								RXC
+								6
+								6
+							
+							
+								TXC
+								5
+								5
+							
+							
+								BUSY
+								4
+								4
+							
+							
+								RXE
+								3
+								3
+							
+							
+								RXB
+								2
+								2
+							
+							
+								TXE
+								1
+								1
+							
+							
+								TXB
+								0
+								0
+							
+						
+					
+					
+						INT_MASK
+						INT_MASK.
+						0x8
+						
+							
+								RXC_M
+								6
+								6
+							
+							
+								TXC_M
+								5
+								5
+							
+							
+								BUSY_M
+								4
+								4
+							
+							
+								RXE_M
+								3
+								3
+							
+							
+								RXB_M
+								2
+								2
+							
+							
+								TXE_M
+								1
+								1
+							
+							
+								TXB_M
+								0
+								0
+							
+						
+					
+					
+						IPGT
+						IPGT.
+						0xC
+						
+							
+								IPGT
+								0
+								6
+							
+						
+					
+					
+						PACKETLEN
+						PACKETLEN.
+						0x18
+						
+							
+								MINFL
+								16
+								31
+							
+							
+								MAXFL
+								0
+								15
+							
+						
+					
+					
+						COLLCONFIG
+						COLLCONFIG.
+						0x1C
+						
+							
+								MAXRET
+								16
+								19
+							
+							
+								COLLVALID
+								0
+								5
+							
+						
+					
+					
+						TX_BD_NUM
+						TX_BD_NUM.
+						0x20
+						
+							
+								RXBDPTR
+								24
+								30
+							
+							
+								TXBDPTR
+								16
+								22
+							
+							
+								TXBDNUM
+								0
+								7
+							
+						
+					
+					
+						MIIMODE
+						MIIMODE.
+						0x28
+						
+							
+								MIINOPRE
+								8
+								8
+							
+							
+								CLKDIV
+								0
+								7
+							
+						
+					
+					
+						MIICOMMAND
+						MIICOMMAND.
+						0x2C
+						
+							
+								WCTRLDATA
+								2
+								2
+							
+							
+								RSTAT
+								1
+								1
+							
+							
+								SCANSTAT
+								0
+								0
+							
+						
+					
+					
+						MIIADDRESS
+						MIIADDRESS.
+						0x30
+						
+							
+								RGAD
+								8
+								12
+							
+							
+								FIAD
+								0
+								4
+							
+						
+					
+					
+						MIITX_DATA
+						MIITX_DATA.
+						0x34
+						
+							
+								CTRLDATA
+								0
+								15
+							
+						
+					
+					
+						MIIRX_DATA
+						MIIRX_DATA.
+						0x38
+						
+							
+								PRSD
+								0
+								15
+							
+						
+					
+					
+						MIISTATUS
+						MIISTATUS.
+						0x3C
+						
+							
+								MIIM_BUSY
+								1
+								1
+							
+							
+								MIIM_LINKFAIL
+								0
+								0
+							
+						
+					
+					
+						MAC_ADDR0
+						MAC_ADDR0.
+						0x40
+						
+							
+								MAC_B2
+								24
+								31
+							
+							
+								MAC_B3
+								16
+								23
+							
+							
+								MAC_B4
+								8
+								15
+							
+							
+								MAC_B5
+								0
+								7
+							
+						
+					
+					
+						MAC_ADDR1
+						MAC_ADDR1.
+						0x44
+						
+							
+								MAC_B0
+								8
+								15
+							
+							
+								MAC_B1
+								0
+								7
+							
+						
+					
+					
+						HASH0_ADDR
+						HASH0_ADDR.
+						0x48
+						
+							
+								HASH0
+								0
+								31
+							
+						
+					
+					
+						HASH1_ADDR
+						HASH1_ADDR.
+						0x4C
+						
+							
+								HASH1
+								0
+								31
+							
+						
+					
+					
+						TXCTRL
+						TXCTRL.
+						0x50
+						
+							
+								TXPAUSERQ
+								16
+								16
+							
+							
+								TXPAUSETV
+								0
+								15
+							
+						
+					
+				
+			
+			
+				usb
+				usb.
+				0x4000D800
+				usb
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						usb_config
+						usb_config.
+						0x0
+						
+							
+								sts_usb_ep0_sw_rdy
+								28
+								28
+							
+							
+								cr_usb_ep0_sw_rdy
+								27
+								27
+							
+							
+								cr_usb_ep0_sw_nack_out
+								26
+								26
+							
+							
+								cr_usb_ep0_sw_nack_in
+								25
+								25
+							
+							
+								cr_usb_ep0_sw_stall
+								24
+								24
+							
+							
+								cr_usb_ep0_sw_size
+								16
+								23
+							
+							
+								cr_usb_ep0_sw_addr
+								9
+								15
+							
+							
+								cr_usb_ep0_sw_ctrl
+								8
+								8
+							
+							
+								cr_usb_rom_dct_en
+								4
+								4
+							
+							
+								cr_usb_en
+								0
+								0
+							
+						
+					
+					
+						usb_lpm_config
+						usb_lpm_config.
+						0x4
+						
+							
+								sts_lpm
+								31
+								31
+							
+							
+								sts_lpm_attr
+								20
+								30
+							
+							
+								cr_lpm_resp
+								2
+								3
+							
+							
+								cr_lpm_resp_upd
+								1
+								1
+							
+							
+								cr_lpm_en
+								0
+								0
+							
+						
+					
+					
+						usb_resume_config
+						usb_resume_config.
+						0x8
+						
+							
+								cr_res_force
+								31
+								31
+							
+							
+								cr_res_trig
+								12
+								12
+							
+							
+								cr_res_width
+								0
+								10
+							
+						
+					
+					
+						usb_setup_data_0
+						usb_setup_data_0.
+						0x10
+						
+							
+								sts_setup_data_b3
+								24
+								31
+							
+							
+								sts_setup_data_b2
+								16
+								23
+							
+							
+								sts_setup_data_b1
+								8
+								15
+							
+							
+								sts_setup_data_b0
+								0
+								7
+							
+						
+					
+					
+						usb_setup_data_1
+						usb_setup_data_1.
+						0x14
+						
+							
+								sts_setup_data_b7
+								24
+								31
+							
+							
+								sts_setup_data_b6
+								16
+								23
+							
+							
+								sts_setup_data_b5
+								8
+								15
+							
+							
+								sts_setup_data_b4
+								0
+								7
+							
+						
+					
+					
+						usb_frame_no
+						usb_frame_no.
+						0x18
+						
+							
+								sts_ep_no
+								16
+								19
+							
+							
+								sts_pid
+								12
+								15
+							
+							
+								sts_frame_no
+								0
+								10
+							
+						
+					
+					
+						usb_error
+						usb_error.
+						0x1C
+						
+							
+								crc16_err
+								6
+								6
+							
+							
+								crc5_err
+								5
+								5
+							
+							
+								pid_cks_err
+								4
+								4
+							
+							
+								pid_seq_err
+								3
+								3
+							
+							
+								ivld_ep_err
+								2
+								2
+							
+							
+								xfer_to_err
+								1
+								1
+							
+							
+								utmi_rx_err
+								0
+								0
+							
+						
+					
+					
+						usb_int_en
+						USB interrupt enable
+						0x20
+						
+							
+								cr_usb_err_en
+								31
+								31
+							
+							
+								cr_sof_3ms_en
+								30
+								30
+							
+							
+								cr_lpm_pkt_en
+								29
+								29
+							
+							
+								cr_lpm_wkup_en
+								28
+								28
+							
+							
+								rsvd_27_24
+								24
+								27
+							
+							
+								cr_ep7_done_en
+								23
+								23
+							
+							
+								cr_ep7_cmd_en
+								22
+								22
+							
+							
+								cr_ep6_done_en
+								21
+								21
+							
+							
+								cr_ep6_cmd_en
+								20
+								20
+							
+							
+								cr_ep5_done_en
+								19
+								19
+							
+							
+								cr_ep5_cmd_en
+								18
+								18
+							
+							
+								cr_ep4_done_en
+								17
+								17
+							
+							
+								cr_ep4_cmd_en
+								16
+								16
+							
+							
+								cr_ep3_done_en
+								15
+								15
+							
+							
+								cr_ep3_cmd_en
+								14
+								14
+							
+							
+								cr_ep2_done_en
+								13
+								13
+							
+							
+								cr_ep2_cmd_en
+								12
+								12
+							
+							
+								cr_ep1_done_en
+								11
+								11
+							
+							
+								cr_ep1_cmd_en
+								10
+								10
+							
+							
+								cr_ep0_out_done_en
+								9
+								9
+							
+							
+								cr_ep0_out_cmd_en
+								8
+								8
+							
+							
+								cr_ep0_in_done_en
+								7
+								7
+							
+							
+								cr_ep0_in_cmd_en
+								6
+								6
+							
+							
+								cr_ep0_setup_done_en
+								5
+								5
+							
+							
+								cr_ep0_setup_cmd_en
+								4
+								4
+							
+							
+								cr_get_dct_cmd_en
+								3
+								3
+							
+							
+								cr_vbus_tgl_en
+								2
+								2
+							
+							
+								cr_usb_reset_en
+								1
+								1
+							
+							
+								cr_sof_en
+								0
+								0
+							
+						
+					
+					
+						usb_int_sts
+						USB interrupt status
+						0x24
+						
+							
+								usb_err_int
+								31
+								31
+							
+							
+								sof_3ms_int
+								30
+								30
+							
+							
+								lpm_pkt_int
+								29
+								29
+							
+							
+								lpm_wkup_int
+								28
+								28
+							
+							
+								rsvd_27_24
+								24
+								27
+							
+							
+								ep7_done_int
+								23
+								23
+							
+							
+								ep7_cmd_int
+								22
+								22
+							
+							
+								ep6_done_int
+								21
+								21
+							
+							
+								ep6_cmd_int
+								20
+								20
+							
+							
+								ep5_done_int
+								19
+								19
+							
+							
+								ep5_cmd_int
+								18
+								18
+							
+							
+								ep4_done_int
+								17
+								17
+							
+							
+								ep4_cmd_int
+								16
+								16
+							
+							
+								ep3_done_int
+								15
+								15
+							
+							
+								ep3_cmd_int
+								14
+								14
+							
+							
+								ep2_done_int
+								13
+								13
+							
+							
+								ep2_cmd_int
+								12
+								12
+							
+							
+								ep1_done_int
+								11
+								11
+							
+							
+								ep1_cmd_int
+								10
+								10
+							
+							
+								ep0_out_done_int
+								9
+								9
+							
+							
+								ep0_out_cmd_int
+								8
+								8
+							
+							
+								ep0_in_done_int
+								7
+								7
+							
+							
+								ep0_in_cmd_int
+								6
+								6
+							
+							
+								ep0_setup_done_int
+								5
+								5
+							
+							
+								ep0_setup_cmd_int
+								4
+								4
+							
+							
+								get_dct_cmd_int
+								3
+								3
+							
+							
+								vbus_tgl_int
+								2
+								2
+							
+							
+								usb_reset_int
+								1
+								1
+							
+							
+								sof_int
+								0
+								0
+							
+						
+					
+					
+						usb_int_mask
+						USB interrupt mask
+						0x28
+						
+							
+								cr_usb_err_mask
+								31
+								31
+							
+							
+								cr_sof_3ms_mask
+								30
+								30
+							
+							
+								cr_lpm_pkt_mask
+								29
+								29
+							
+							
+								cr_lpm_wkup_mask
+								28
+								28
+							
+							
+								rsvd_27_24
+								24
+								27
+							
+							
+								cr_ep7_done_mask
+								23
+								23
+							
+							
+								cr_ep7_cmd_mask
+								22
+								22
+							
+							
+								cr_ep6_done_mask
+								21
+								21
+							
+							
+								cr_ep6_cmd_mask
+								20
+								20
+							
+							
+								cr_ep5_done_mask
+								19
+								19
+							
+							
+								cr_ep5_cmd_mask
+								18
+								18
+							
+							
+								cr_ep4_done_mask
+								17
+								17
+							
+							
+								cr_ep4_cmd_mask
+								16
+								16
+							
+							
+								cr_ep3_done_mask
+								15
+								15
+							
+							
+								cr_ep3_cmd_mask
+								14
+								14
+							
+							
+								cr_ep2_done_mask
+								13
+								13
+							
+							
+								cr_ep2_cmd_mask
+								12
+								12
+							
+							
+								cr_ep1_done_mask
+								11
+								11
+							
+							
+								cr_ep1_cmd_mask
+								10
+								10
+							
+							
+								cr_ep0_out_done_mask
+								9
+								9
+							
+							
+								cr_ep0_out_cmd_mask
+								8
+								8
+							
+							
+								cr_ep0_in_done_mask
+								7
+								7
+							
+							
+								cr_ep0_in_cmd_mask
+								6
+								6
+							
+							
+								cr_ep0_setup_done_mask
+								5
+								5
+							
+							
+								cr_ep0_setup_cmd_mask
+								4
+								4
+							
+							
+								cr_get_dct_cmd_mask
+								3
+								3
+							
+							
+								cr_vbus_tgl_mask
+								2
+								2
+							
+							
+								cr_usb_reset_mask
+								1
+								1
+							
+							
+								cr_sof_mask
+								0
+								0
+							
+						
+					
+					
+						usb_int_clear
+						USB interrupt clear
+						0x2C
+						
+							
+								cr_usb_err_clr
+								31
+								31
+							
+							
+								cr_sof_3ms_clr
+								30
+								30
+							
+							
+								cr_lpm_pkt_clr
+								29
+								29
+							
+							
+								cr_lpm_wkup_clr
+								28
+								28
+							
+							
+								rsvd_27_24
+								24
+								27
+							
+							
+								cr_ep7_done_clr
+								23
+								23
+							
+							
+								cr_ep7_cmd_clr
+								22
+								22
+							
+							
+								cr_ep6_done_clr
+								21
+								21
+							
+							
+								cr_ep6_cmd_clr
+								20
+								20
+							
+							
+								cr_ep5_done_clr
+								19
+								19
+							
+							
+								cr_ep5_cmd_clr
+								18
+								18
+							
+							
+								cr_ep4_done_clr
+								17
+								17
+							
+							
+								cr_ep4_cmd_clr
+								16
+								16
+							
+							
+								cr_ep3_done_clr
+								15
+								15
+							
+							
+								cr_ep3_cmd_clr
+								14
+								14
+							
+							
+								cr_ep2_done_clr
+								13
+								13
+							
+							
+								cr_ep2_cmd_clr
+								12
+								12
+							
+							
+								cr_ep1_done_clr
+								11
+								11
+							
+							
+								cr_ep1_cmd_clr
+								10
+								10
+							
+							
+								cr_ep0_out_done_clr
+								9
+								9
+							
+							
+								cr_ep0_out_cmd_clr
+								8
+								8
+							
+							
+								cr_ep0_in_done_clr
+								7
+								7
+							
+							
+								cr_ep0_in_cmd_clr
+								6
+								6
+							
+							
+								cr_ep0_setup_done_clr
+								5
+								5
+							
+							
+								cr_ep0_setup_cmd_clr
+								4
+								4
+							
+							
+								cr_get_dct_cmd_clr
+								3
+								3
+							
+							
+								cr_vbus_tgl_clr
+								2
+								2
+							
+							
+								cr_usb_reset_clr
+								1
+								1
+							
+							
+								cr_sof_clr
+								0
+								0
+							
+						
+					
+					
+						ep1_config
+						ep1_config.
+						0x40
+						
+							
+								sts_ep1_rdy
+								19
+								19
+							
+							
+								cr_ep1_rdy
+								18
+								18
+							
+							
+								cr_ep1_nack
+								17
+								17
+							
+							
+								cr_ep1_stall
+								16
+								16
+							
+							
+								cr_ep1_type
+								13
+								15
+							
+							
+								cr_ep1_dir
+								11
+								12
+							
+							
+								cr_ep1_size
+								0
+								10
+							
+						
+					
+					
+						ep2_config
+						ep2_config.
+						0x44
+						
+							
+								sts_ep2_rdy
+								19
+								19
+							
+							
+								cr_ep2_rdy
+								18
+								18
+							
+							
+								cr_ep2_nack
+								17
+								17
+							
+							
+								cr_ep2_stall
+								16
+								16
+							
+							
+								cr_ep2_type
+								13
+								15
+							
+							
+								cr_ep2_dir
+								11
+								12
+							
+							
+								cr_ep2_size
+								0
+								10
+							
+						
+					
+					
+						ep3_config
+						ep3_config.
+						0x48
+						
+							
+								sts_ep3_rdy
+								19
+								19
+							
+							
+								cr_ep3_rdy
+								18
+								18
+							
+							
+								cr_ep3_nack
+								17
+								17
+							
+							
+								cr_ep3_stall
+								16
+								16
+							
+							
+								cr_ep3_type
+								13
+								15
+							
+							
+								cr_ep3_dir
+								11
+								12
+							
+							
+								cr_ep3_size
+								0
+								10
+							
+						
+					
+					
+						ep4_config
+						ep4_config.
+						0x4C
+						
+							
+								sts_ep4_rdy
+								19
+								19
+							
+							
+								cr_ep4_rdy
+								18
+								18
+							
+							
+								cr_ep4_nack
+								17
+								17
+							
+							
+								cr_ep4_stall
+								16
+								16
+							
+							
+								cr_ep4_type
+								13
+								15
+							
+							
+								cr_ep4_dir
+								11
+								12
+							
+							
+								cr_ep4_size
+								0
+								10
+							
+						
+					
+					
+						ep5_config
+						ep5_config.
+						0x50
+						
+							
+								sts_ep5_rdy
+								19
+								19
+							
+							
+								cr_ep5_rdy
+								18
+								18
+							
+							
+								cr_ep5_nack
+								17
+								17
+							
+							
+								cr_ep5_stall
+								16
+								16
+							
+							
+								cr_ep5_type
+								13
+								15
+							
+							
+								cr_ep5_dir
+								11
+								12
+							
+							
+								cr_ep5_size
+								0
+								10
+							
+						
+					
+					
+						ep6_config
+						ep6_config.
+						0x54
+						
+							
+								sts_ep6_rdy
+								19
+								19
+							
+							
+								cr_ep6_rdy
+								18
+								18
+							
+							
+								cr_ep6_nack
+								17
+								17
+							
+							
+								cr_ep6_stall
+								16
+								16
+							
+							
+								cr_ep6_type
+								13
+								15
+							
+							
+								cr_ep6_dir
+								11
+								12
+							
+							
+								cr_ep6_size
+								0
+								10
+							
+						
+					
+					
+						ep7_config
+						ep7_config.
+						0x58
+						
+							
+								sts_ep7_rdy
+								19
+								19
+							
+							
+								cr_ep7_rdy
+								18
+								18
+							
+							
+								cr_ep7_nack
+								17
+								17
+							
+							
+								cr_ep7_stall
+								16
+								16
+							
+							
+								cr_ep7_type
+								13
+								15
+							
+							
+								cr_ep7_dir
+								11
+								12
+							
+							
+								cr_ep7_size
+								0
+								10
+							
+						
+					
+					
+						ep0_fifo_config
+						ep0_fifo_config.
+						0x100
+						
+							
+								ep0_rx_fifo_underflow
+								7
+								7
+							
+							
+								ep0_rx_fifo_overflow
+								6
+								6
+							
+							
+								ep0_tx_fifo_underflow
+								5
+								5
+							
+							
+								ep0_tx_fifo_overflow
+								4
+								4
+							
+							
+								ep0_rx_fifo_clr
+								3
+								3
+							
+							
+								ep0_tx_fifo_clr
+								2
+								2
+							
+							
+								ep0_dma_rx_en
+								1
+								1
+							
+							
+								ep0_dma_tx_en
+								0
+								0
+							
+						
+					
+					
+						ep0_fifo_status
+						ep0_fifo_status.
+						0x104
+						
+							
+								ep0_rx_fifo_full
+								31
+								31
+							
+							
+								ep0_rx_fifo_empty
+								30
+								30
+							
+							
+								ep0_rx_fifo_cnt
+								16
+								22
+							
+							
+								ep0_tx_fifo_full
+								15
+								15
+							
+							
+								ep0_tx_fifo_empty
+								14
+								14
+							
+							
+								ep0_tx_fifo_cnt
+								0
+								6
+							
+						
+					
+					
+						ep0_tx_fifo_wdata
+						ep0_tx_fifo_wdata.
+						0x108
+						
+							
+								ep0_tx_fifo_wdata
+								0
+								7
+							
+						
+					
+					
+						ep0_rx_fifo_rdata
+						ep0_rx_fifo_rdata.
+						0x10C
+						
+							
+								ep0_rx_fifo_rdata
+								0
+								7
+							
+						
+					
+					
+						ep1_fifo_config
+						ep1_fifo_config.
+						0x110
+						
+							
+								ep1_rx_fifo_underflow
+								7
+								7
+							
+							
+								ep1_rx_fifo_overflow
+								6
+								6
+							
+							
+								ep1_tx_fifo_underflow
+								5
+								5
+							
+							
+								ep1_tx_fifo_overflow
+								4
+								4
+							
+							
+								ep1_rx_fifo_clr
+								3
+								3
+							
+							
+								ep1_tx_fifo_clr
+								2
+								2
+							
+							
+								ep1_dma_rx_en
+								1
+								1
+							
+							
+								ep1_dma_tx_en
+								0
+								0
+							
+						
+					
+					
+						ep1_fifo_status
+						ep1_fifo_status.
+						0x114
+						
+							
+								ep1_rx_fifo_full
+								31
+								31
+							
+							
+								ep1_rx_fifo_empty
+								30
+								30
+							
+							
+								ep1_rx_fifo_cnt
+								16
+								22
+							
+							
+								ep1_tx_fifo_full
+								15
+								15
+							
+							
+								ep1_tx_fifo_empty
+								14
+								14
+							
+							
+								ep1_tx_fifo_cnt
+								0
+								6
+							
+						
+					
+					
+						ep1_tx_fifo_wdata
+						ep1_tx_fifo_wdata.
+						0x118
+						
+							
+								ep1_tx_fifo_wdata
+								0
+								7
+							
+						
+					
+					
+						ep1_rx_fifo_rdata
+						ep1_rx_fifo_rdata.
+						0x11C
+						
+							
+								ep1_rx_fifo_rdata
+								0
+								7
+							
+						
+					
+					
+						ep2_fifo_config
+						ep2_fifo_config.
+						0x120
+						
+							
+								ep2_rx_fifo_underflow
+								7
+								7
+							
+							
+								ep2_rx_fifo_overflow
+								6
+								6
+							
+							
+								ep2_tx_fifo_underflow
+								5
+								5
+							
+							
+								ep2_tx_fifo_overflow
+								4
+								4
+							
+							
+								ep2_rx_fifo_clr
+								3
+								3
+							
+							
+								ep2_tx_fifo_clr
+								2
+								2
+							
+							
+								ep2_dma_rx_en
+								1
+								1
+							
+							
+								ep2_dma_tx_en
+								0
+								0
+							
+						
+					
+					
+						ep2_fifo_status
+						ep2_fifo_status.
+						0x124
+						
+							
+								ep2_rx_fifo_full
+								31
+								31
+							
+							
+								ep2_rx_fifo_empty
+								30
+								30
+							
+							
+								ep2_rx_fifo_cnt
+								16
+								22
+							
+							
+								ep2_tx_fifo_full
+								15
+								15
+							
+							
+								ep2_tx_fifo_empty
+								14
+								14
+							
+							
+								ep2_tx_fifo_cnt
+								0
+								6
+							
+						
+					
+					
+						ep2_tx_fifo_wdata
+						ep2_tx_fifo_wdata.
+						0x128
+						
+							
+								ep2_tx_fifo_wdata
+								0
+								7
+							
+						
+					
+					
+						ep2_rx_fifo_rdata
+						ep2_rx_fifo_rdata.
+						0x12C
+						
+							
+								ep2_rx_fifo_rdata
+								0
+								7
+							
+						
+					
+					
+						ep3_fifo_config
+						ep3_fifo_config.
+						0x130
+						
+							
+								ep3_rx_fifo_underflow
+								7
+								7
+							
+							
+								ep3_rx_fifo_overflow
+								6
+								6
+							
+							
+								ep3_tx_fifo_underflow
+								5
+								5
+							
+							
+								ep3_tx_fifo_overflow
+								4
+								4
+							
+							
+								ep3_rx_fifo_clr
+								3
+								3
+							
+							
+								ep3_tx_fifo_clr
+								2
+								2
+							
+							
+								ep3_dma_rx_en
+								1
+								1
+							
+							
+								ep3_dma_tx_en
+								0
+								0
+							
+						
+					
+					
+						ep3_fifo_status
+						ep3_fifo_status.
+						0x134
+						
+							
+								ep3_rx_fifo_full
+								31
+								31
+							
+							
+								ep3_rx_fifo_empty
+								30
+								30
+							
+							
+								ep3_rx_fifo_cnt
+								16
+								22
+							
+							
+								ep3_tx_fifo_full
+								15
+								15
+							
+							
+								ep3_tx_fifo_empty
+								14
+								14
+							
+							
+								ep3_tx_fifo_cnt
+								0
+								6
+							
+						
+					
+					
+						ep3_tx_fifo_wdata
+						ep3_tx_fifo_wdata.
+						0x138
+						
+							
+								ep3_tx_fifo_wdata
+								0
+								7
+							
+						
+					
+					
+						ep3_rx_fifo_rdata
+						ep3_rx_fifo_rdata.
+						0x13C
+						
+							
+								ep3_rx_fifo_rdata
+								0
+								7
+							
+						
+					
+					
+						ep4_fifo_config
+						ep4_fifo_config.
+						0x140
+						
+							
+								ep4_rx_fifo_underflow
+								7
+								7
+							
+							
+								ep4_rx_fifo_overflow
+								6
+								6
+							
+							
+								ep4_tx_fifo_underflow
+								5
+								5
+							
+							
+								ep4_tx_fifo_overflow
+								4
+								4
+							
+							
+								ep4_rx_fifo_clr
+								3
+								3
+							
+							
+								ep4_tx_fifo_clr
+								2
+								2
+							
+							
+								ep4_dma_rx_en
+								1
+								1
+							
+							
+								ep4_dma_tx_en
+								0
+								0
+							
+						
+					
+					
+						ep4_fifo_status
+						ep4_fifo_status.
+						0x144
+						
+							
+								ep4_rx_fifo_full
+								31
+								31
+							
+							
+								ep4_rx_fifo_empty
+								30
+								30
+							
+							
+								ep4_rx_fifo_cnt
+								16
+								22
+							
+							
+								ep4_tx_fifo_full
+								15
+								15
+							
+							
+								ep4_tx_fifo_empty
+								14
+								14
+							
+							
+								ep4_tx_fifo_cnt
+								0
+								6
+							
+						
+					
+					
+						ep4_tx_fifo_wdata
+						ep4_tx_fifo_wdata.
+						0x148
+						
+							
+								ep4_tx_fifo_wdata
+								0
+								7
+							
+						
+					
+					
+						ep4_rx_fifo_rdata
+						ep4_rx_fifo_rdata.
+						0x14C
+						
+							
+								ep4_rx_fifo_rdata
+								0
+								7
+							
+						
+					
+					
+						ep5_fifo_config
+						ep5_fifo_config.
+						0x150
+						
+							
+								ep5_rx_fifo_underflow
+								7
+								7
+							
+							
+								ep5_rx_fifo_overflow
+								6
+								6
+							
+							
+								ep5_tx_fifo_underflow
+								5
+								5
+							
+							
+								ep5_tx_fifo_overflow
+								4
+								4
+							
+							
+								ep5_rx_fifo_clr
+								3
+								3
+							
+							
+								ep5_tx_fifo_clr
+								2
+								2
+							
+							
+								ep5_dma_rx_en
+								1
+								1
+							
+							
+								ep5_dma_tx_en
+								0
+								0
+							
+						
+					
+					
+						ep5_fifo_status
+						ep5_fifo_status.
+						0x154
+						
+							
+								ep5_rx_fifo_full
+								31
+								31
+							
+							
+								ep5_rx_fifo_empty
+								30
+								30
+							
+							
+								ep5_rx_fifo_cnt
+								16
+								22
+							
+							
+								ep5_tx_fifo_full
+								15
+								15
+							
+							
+								ep5_tx_fifo_empty
+								14
+								14
+							
+							
+								ep5_tx_fifo_cnt
+								0
+								6
+							
+						
+					
+					
+						ep5_tx_fifo_wdata
+						ep5_tx_fifo_wdata.
+						0x158
+						
+							
+								ep5_tx_fifo_wdata
+								0
+								7
+							
+						
+					
+					
+						ep5_rx_fifo_rdata
+						ep5_rx_fifo_rdata.
+						0x15C
+						
+							
+								ep5_rx_fifo_rdata
+								0
+								7
+							
+						
+					
+					
+						ep6_fifo_config
+						ep6_fifo_config.
+						0x160
+						
+							
+								ep6_rx_fifo_underflow
+								7
+								7
+							
+							
+								ep6_rx_fifo_overflow
+								6
+								6
+							
+							
+								ep6_tx_fifo_underflow
+								5
+								5
+							
+							
+								ep6_tx_fifo_overflow
+								4
+								4
+							
+							
+								ep6_rx_fifo_clr
+								3
+								3
+							
+							
+								ep6_tx_fifo_clr
+								2
+								2
+							
+							
+								ep6_dma_rx_en
+								1
+								1
+							
+							
+								ep6_dma_tx_en
+								0
+								0
+							
+						
+					
+					
+						ep6_fifo_status
+						ep6_fifo_status.
+						0x164
+						
+							
+								ep6_rx_fifo_full
+								31
+								31
+							
+							
+								ep6_rx_fifo_empty
+								30
+								30
+							
+							
+								ep6_rx_fifo_cnt
+								16
+								22
+							
+							
+								ep6_tx_fifo_full
+								15
+								15
+							
+							
+								ep6_tx_fifo_empty
+								14
+								14
+							
+							
+								ep6_tx_fifo_cnt
+								0
+								6
+							
+						
+					
+					
+						ep6_tx_fifo_wdata
+						ep6_tx_fifo_wdata.
+						0x168
+						
+							
+								ep6_tx_fifo_wdata
+								0
+								7
+							
+						
+					
+					
+						ep6_rx_fifo_rdata
+						ep6_rx_fifo_rdata.
+						0x16C
+						
+							
+								ep6_rx_fifo_rdata
+								0
+								7
+							
+						
+					
+					
+						ep7_fifo_config
+						ep7_fifo_config.
+						0x170
+						
+							
+								ep7_rx_fifo_underflow
+								7
+								7
+							
+							
+								ep7_rx_fifo_overflow
+								6
+								6
+							
+							
+								ep7_tx_fifo_underflow
+								5
+								5
+							
+							
+								ep7_tx_fifo_overflow
+								4
+								4
+							
+							
+								ep7_rx_fifo_clr
+								3
+								3
+							
+							
+								ep7_tx_fifo_clr
+								2
+								2
+							
+							
+								ep7_dma_rx_en
+								1
+								1
+							
+							
+								ep7_dma_tx_en
+								0
+								0
+							
+						
+					
+					
+						ep7_fifo_status
+						ep7_fifo_status.
+						0x174
+						
+							
+								ep7_rx_fifo_full
+								31
+								31
+							
+							
+								ep7_rx_fifo_empty
+								30
+								30
+							
+							
+								ep7_rx_fifo_cnt
+								16
+								22
+							
+							
+								ep7_tx_fifo_full
+								15
+								15
+							
+							
+								ep7_tx_fifo_empty
+								14
+								14
+							
+							
+								ep7_tx_fifo_cnt
+								0
+								6
+							
+						
+					
+					
+						ep7_tx_fifo_wdata
+						ep7_tx_fifo_wdata.
+						0x178
+						
+							
+								ep7_tx_fifo_wdata
+								0
+								7
+							
+						
+					
+					
+						ep7_rx_fifo_rdata
+						ep7_rx_fifo_rdata.
+						0x17C
+						
+							
+								ep7_rx_fifo_rdata
+								0
+								7
+							
+						
+					
+					
+						rsvd_0
+						rsvd_0.
+						0x1F0
+						
+							
+								rsvd_0
+								0
+								31
+							
+						
+					
+					
+						rsvd_1
+						rsvd_1.
+						0x1F4
+						
+							
+								rsvd_1
+								0
+								31
+							
+						
+					
+					
+						xcvr_if_config
+						xcvr_if_config.
+						0x1FC
+						
+							
+								sts_vbus_det
+								31
+								31
+							
+							
+								cr_xcvr_om_rx_dn
+								11
+								11
+							
+							
+								cr_xcvr_om_rx_dp
+								10
+								10
+							
+							
+								cr_xcvr_om_rx_d
+								9
+								9
+							
+							
+								cr_xcvr_om_rx_sel
+								8
+								8
+							
+							
+								cr_xcvr_force_rx_dn
+								7
+								7
+							
+							
+								cr_xcvr_force_rx_dp
+								6
+								6
+							
+							
+								cr_xcvr_force_rx_d
+								5
+								5
+							
+							
+								cr_xcvr_force_rx_en
+								4
+								4
+							
+							
+								cr_xcvr_force_tx_dn
+								3
+								3
+							
+							
+								cr_xcvr_force_tx_dp
+								2
+								2
+							
+							
+								cr_xcvr_force_tx_oe
+								1
+								1
+							
+							
+								cr_xcvr_force_tx_en
+								0
+								0
+							
+						
+					
+				
+			
+			
+				pds
+				pds.
+				0x4000E000
+				pds
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						PDS_CTL
+						PDS_CTL.
+						0x0
+						
+							
+								cr_pds_ctrl_pll
+								30
+								31
+							
+							
+								cr_pds_ctrl_rf
+								28
+								29
+							
+							
+								cr_pds_ldo_vol
+								24
+								27
+							
+							
+								cr_pds_force_ram_clk_en
+								23
+								23
+							
+							
+								cr_pds_pd_ldo11
+								22
+								22
+							
+							
+								cr_np_wfi_mask
+								21
+								21
+							
+							
+								cr_pds_ram_lp_with_clk_en
+								19
+								19
+							
+							
+								cr_pds_ldo_vsel_en
+								18
+								18
+							
+							
+								cr_pds_rc32m_off_dis
+								17
+								17
+							
+							
+								cr_pds_rst_soc_en
+								16
+								16
+							
+							
+								cr_pds_soc_enb_force_on
+								15
+								15
+							
+							
+								cr_pds_pd_xtal
+								14
+								14
+							
+							
+								cr_pds_pwr_off
+								13
+								13
+							
+							
+								cr_pds_wait_xtal_rdy
+								12
+								12
+							
+							
+								cr_pds_iso_en
+								11
+								11
+							
+							
+								cr_sw_pu_flash
+								10
+								10
+							
+							
+								cr_pds_mem_stby
+								9
+								9
+							
+							
+								cr_pds_gate_clk
+								8
+								8
+							
+							
+								cr_pds_ctrl_pu_flash
+								7
+								7
+							
+							
+								cr_pds_ctrl_gpio_ie_pu_pd
+								6
+								6
+							
+							
+								cr_pds_pd_bg_sys
+								5
+								5
+							
+							
+								cr_pds_pd_dcdc18
+								4
+								4
+							
+							
+								cr_wifi_pds_save_state
+								3
+								3
+							
+							
+								cr_xtal_force_off
+								2
+								2
+							
+							
+								cr_sleep_forever
+								1
+								1
+							
+							
+								pds_start_ps
+								0
+								0
+							
+						
+					
+					
+						PDS_TIME1
+						PDS_TIME1.
+						0x4
+						
+							
+								cr_sleep_duration
+								0
+								31
+							
+						
+					
+					
+						PDS_INT
+						PDS_INT.
+						0xC
+						
+							
+								ro_pds_wakeup_event
+								24
+								31
+							
+							
+								cr_pds_wakeup_src_en
+								16
+								23
+							
+							
+								cr_pds_int_clr
+								15
+								15
+							
+							
+								cr_pds_pll_done_int_mask
+								11
+								11
+							
+							
+								cr_pds_rf_done_int_mask
+								10
+								10
+							
+							
+								cr_pds_wake_int_mask
+								8
+								8
+							
+							
+								pds_clr_reset_event
+								7
+								7
+							
+							
+								pds_reset_event
+								4
+								6
+							
+							
+								ro_pds_pll_done_int
+								3
+								3
+							
+							
+								ro_pds_rf_done_int
+								2
+								2
+							
+							
+								ro_pds_wake_int
+								0
+								0
+							
+						
+					
+					
+						PDS_CTL2
+						PDS_CTL2.
+						0x10
+						
+							
+								cr_pds_force_usb_gate_clk
+								19
+								19
+							
+							
+								cr_pds_force_bz_gate_clk
+								18
+								18
+							
+							
+								cr_pds_force_np_gate_clk
+								16
+								16
+							
+							
+								cr_pds_force_usb_mem_stby
+								15
+								15
+							
+							
+								cr_pds_force_bz_mem_stby
+								14
+								14
+							
+							
+								cr_pds_force_np_mem_stby
+								12
+								12
+							
+							
+								cr_pds_force_usb_pds_rst
+								11
+								11
+							
+							
+								cr_pds_force_bz_pds_rst
+								10
+								10
+							
+							
+								cr_pds_force_np_pds_rst
+								8
+								8
+							
+							
+								cr_pds_force_usb_iso_en
+								7
+								7
+							
+							
+								cr_pds_force_bz_iso_en
+								6
+								6
+							
+							
+								cr_pds_force_np_iso_en
+								4
+								4
+							
+							
+								cr_pds_force_usb_pwr_off
+								3
+								3
+							
+							
+								cr_pds_force_bz_pwr_off
+								2
+								2
+							
+							
+								cr_pds_force_np_pwr_off
+								0
+								0
+							
+						
+					
+					
+						PDS_CTL3
+						PDS_CTL3.
+						0x14
+						
+							
+								cr_pds_misc_iso_en
+								30
+								30
+							
+							
+								cr_pds_usb_iso_en
+								29
+								29
+							
+							
+								cr_pds_ble_iso_en
+								28
+								28
+							
+							
+								cr_pds_bz_iso_en
+								27
+								27
+							
+							
+								cr_pds_np_iso_en
+								24
+								24
+							
+							
+								cr_pds_force_ble_gate_clk
+								14
+								14
+							
+							
+								cr_pds_force_misc_gate_clk
+								13
+								13
+							
+							
+								cr_pds_force_ble_mem_stby
+								11
+								11
+							
+							
+								cr_pds_force_misc_mem_stby
+								10
+								10
+							
+							
+								cr_pds_force_ble_pds_rst
+								8
+								8
+							
+							
+								cr_pds_force_misc_pds_rst
+								7
+								7
+							
+							
+								cr_pds_force_ble_iso_en
+								5
+								5
+							
+							
+								cr_pds_force_ble_pwr_off
+								2
+								2
+							
+							
+								cr_pds_force_misc_pwr_off
+								1
+								1
+							
+						
+					
+					
+						PDS_CTL4
+						PDS_CTL4.
+						0x18
+						
+							
+								cr_pds_misc_dig_pwr_off
+								31
+								31
+							
+							
+								cr_pds_misc_ana_pwr_off
+								30
+								30
+							
+							
+								cr_pds_misc_gate_clk
+								27
+								27
+							
+							
+								cr_pds_misc_mem_stby
+								26
+								26
+							
+							
+								cr_pds_misc_reset
+								25
+								25
+							
+							
+								cr_pds_misc_pwr_off
+								24
+								24
+							
+							
+								cr_pds_usb_gate_clk
+								23
+								23
+							
+							
+								cr_pds_usb_mem_stby
+								22
+								22
+							
+							
+								cr_pds_usb_reset
+								21
+								21
+							
+							
+								cr_pds_usb_pwr_off
+								20
+								20
+							
+							
+								cr_pds_ble_gate_clk
+								19
+								19
+							
+							
+								cr_pds_ble_mem_stby
+								18
+								18
+							
+							
+								cr_pds_ble_reset
+								17
+								17
+							
+							
+								cr_pds_ble_pwr_off
+								16
+								16
+							
+							
+								cr_pds_bz_gate_clk
+								15
+								15
+							
+							
+								cr_pds_bz_mem_stby
+								14
+								14
+							
+							
+								cr_pds_bz_reset
+								13
+								13
+							
+							
+								cr_pds_bz_pwr_off
+								12
+								12
+							
+							
+								cr_pds_np_gate_clk
+								3
+								3
+							
+							
+								cr_pds_np_mem_stby
+								2
+								2
+							
+							
+								cr_pds_np_reset
+								1
+								1
+							
+							
+								cr_pds_np_pwr_off
+								0
+								0
+							
+						
+					
+					
+						pds_stat
+						pds_stat.
+						0x1C
+						
+							
+								ro_pds_pll_state
+								16
+								17
+							
+							
+								ro_pds_rf_state
+								8
+								11
+							
+							
+								ro_pds_state
+								0
+								3
+							
+						
+					
+					
+						pds_ram1
+						pds_ram1.
+						0x20
+						
+							
+								cr_pds_ram_pgen
+								8
+								11
+							
+							
+								cr_pds_ram_ret2n
+								4
+								7
+							
+							
+								cr_pds_ram_ret1n
+								0
+								3
+							
+						
+					
+					
+						pds_gpio_set_pu_pd
+						pds_gpio_set_pu_pd.
+						0x30
+						
+							
+								cr_pds_gpio_28_23_pu
+								24
+								29
+							
+							
+								cr_pds_gpio_28_23_pd
+								16
+								21
+							
+							
+								cr_pds_gpio_22_17_pu
+								8
+								13
+							
+							
+								cr_pds_gpio_22_17_pd
+								0
+								5
+							
+						
+					
+					
+						pds_gpio_int
+						pds_gpio_int.
+						0x40
+						
+							
+								pds_gpio_int_select
+								8
+								10
+							
+							
+								pds_gpio_int_mode
+								4
+								6
+							
+							
+								pds_gpio_int_clr
+								2
+								2
+							
+							
+								pds_gpio_int_stat
+								1
+								1
+							
+							
+								pds_gpio_int_mask
+								0
+								0
+							
+						
+					
+					
+						rc32m_ctrl0
+						rc32m_ctrl0.
+						0x300
+						
+							
+								rc32m_code_fr_ext
+								22
+								29
+							
+							
+								rc32m_pd
+								21
+								21
+							
+							
+								rc32m_cal_en
+								20
+								20
+							
+							
+								rc32m_ext_code_en
+								19
+								19
+							
+							
+								rc32m_refclk_half
+								18
+								18
+							
+							
+								rc32m_allow_cal
+								17
+								17
+							
+							
+								rc32m_dig_code_fr_cal
+								6
+								13
+							
+							
+								rc32m_cal_precharge
+								5
+								5
+							
+							
+								rc32m_cal_div
+								3
+								4
+							
+							
+								rc32m_cal_inprogress
+								2
+								2
+							
+							
+								rc32m_rdy
+								1
+								1
+							
+							
+								rc32m_cal_done
+								0
+								0
+							
+						
+					
+					
+						rc32m_ctrl1
+						rc32m_ctrl1.
+						0x304
+						
+							
+								rc32m_reserved
+								24
+								31
+							
+							
+								rc32m_clk_force_on
+								4
+								4
+							
+							
+								rc32m_clk_inv
+								3
+								3
+							
+							
+								rc32m_clk_soft_rst
+								2
+								2
+							
+							
+								rc32m_soft_rst
+								1
+								1
+							
+							
+								rc32m_test_en
+								0
+								0
+							
+						
+					
+					
+						pu_rst_clkpll
+						pu_rst_clkpll.
+						0x400
+						
+							
+								pu_clkpll
+								10
+								10
+							
+							
+								pu_clkpll_sfreg
+								9
+								9
+							
+							
+								clkpll_pu_cp
+								8
+								8
+							
+							
+								clkpll_pu_pfd
+								7
+								7
+							
+							
+								clkpll_pu_clamp_op
+								6
+								6
+							
+							
+								clkpll_pu_fbdv
+								5
+								5
+							
+							
+								clkpll_pu_postdiv
+								4
+								4
+							
+							
+								clkpll_reset_refdiv
+								3
+								3
+							
+							
+								clkpll_reset_fbdv
+								2
+								2
+							
+							
+								clkpll_reset_postdiv
+								1
+								1
+							
+							
+								clkpll_sdm_reset
+								0
+								0
+							
+						
+					
+					
+						clkpll_top_ctrl
+						clkpll_top_ctrl.
+						0x404
+						
+							
+								clkpll_resv
+								24
+								25
+							
+							
+								clkpll_vg11_sel
+								20
+								21
+							
+							
+								clkpll_refclk_sel
+								16
+								16
+							
+							
+								clkpll_xtal_rc32m_sel
+								12
+								12
+							
+							
+								clkpll_refdiv_ratio
+								8
+								11
+							
+							
+								clkpll_postdiv
+								0
+								6
+							
+						
+					
+					
+						clkpll_cp
+						clkpll_cp.
+						0x408
+						
+							
+								clkpll_cp_opamp_en
+								10
+								10
+							
+							
+								clkpll_cp_startup_en
+								9
+								9
+							
+							
+								clkpll_int_frac_sw
+								8
+								8
+							
+							
+								clkpll_icp_1u
+								6
+								7
+							
+							
+								clkpll_icp_5u
+								4
+								5
+							
+							
+								clkpll_sel_cp_bias
+								0
+								0
+							
+						
+					
+					
+						clkpll_rz
+						clkpll_rz.
+						0x40C
+						
+							
+								clkpll_rz
+								16
+								18
+							
+							
+								clkpll_cz
+								14
+								15
+							
+							
+								clkpll_c3
+								12
+								13
+							
+							
+								clkpll_r4_short
+								8
+								8
+							
+							
+								clkpll_r4
+								4
+								5
+							
+							
+								clkpll_c4_en
+								0
+								0
+							
+						
+					
+					
+						clkpll_fbdv
+						clkpll_fbdv.
+						0x410
+						
+							
+								clkpll_sel_fb_clk
+								2
+								3
+							
+							
+								clkpll_sel_sample_clk
+								0
+								1
+							
+						
+					
+					
+						clkpll_vco
+						clkpll_vco.
+						0x414
+						
+							
+								clkpll_shrtr
+								3
+								3
+							
+							
+								clkpll_vco_speed
+								0
+								2
+							
+						
+					
+					
+						clkpll_sdm
+						clkpll_sdm.
+						0x418
+						
+							
+								clkpll_sdm_bypass
+								29
+								29
+							
+							
+								clkpll_sdm_flag
+								28
+								28
+							
+							
+								clkpll_dither_sel
+								24
+								25
+							
+							
+								clkpll_sdmin
+								0
+								23
+							
+						
+					
+					
+						clkpll_output_en
+						clkpll_output_en.
+						0x41C
+						
+							
+								clkpll_en_div2_480m
+								9
+								9
+							
+							
+								clkpll_en_32m
+								8
+								8
+							
+							
+								clkpll_en_48m
+								7
+								7
+							
+							
+								clkpll_en_80m
+								6
+								6
+							
+							
+								clkpll_en_96m
+								5
+								5
+							
+							
+								clkpll_en_120m
+								4
+								4
+							
+							
+								clkpll_en_160m
+								3
+								3
+							
+							
+								clkpll_en_192m
+								2
+								2
+							
+							
+								clkpll_en_240m
+								1
+								1
+							
+							
+								clkpll_en_480m
+								0
+								0
+							
+						
+					
+					
+						clkpll_test_enable
+						clkpll_test_enable.
+						0x420
+						
+							
+								clkpll_dc_tp_out_en
+								8
+								8
+							
+							
+								ten_clkpll
+								7
+								7
+							
+							
+								ten_clkpll_sfreg
+								6
+								6
+							
+							
+								dten_clkpll_fin
+								5
+								5
+							
+							
+								dten_clkpll_fref
+								4
+								4
+							
+							
+								dten_clkpll_fsdm
+								3
+								3
+							
+							
+								dten_clk32M
+								2
+								2
+							
+							
+								dten_clk96M
+								1
+								1
+							
+							
+								dten_clkpll_postdiv_clk
+								0
+								0
+							
+						
+					
+				
+			
+			
+				HBN
+				HBN.
+				0x4000F000
+				HBN
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						HBN_CTL
+						HBN_CTL.
+						0x0
+						
+							
+								hbn_state
+								28
+								31
+							
+							
+								sram_slp
+								27
+								27
+							
+							
+								sram_slp_option
+								26
+								26
+							
+							
+								pwr_on_option
+								25
+								25
+							
+							
+								rtc_dly_option
+								24
+								24
+							
+							
+								pu_dcdc18_aon
+								23
+								23
+							
+							
+								hbn_ldo11_aon_vout_sel
+								19
+								22
+							
+							
+								hbn_ldo11_rt_vout_sel
+								15
+								18
+							
+							
+								hbn_dis_pwr_off_ldo11_rt
+								14
+								14
+							
+							
+								hbn_dis_pwr_off_ldo11
+								13
+								13
+							
+							
+								sw_rst
+								12
+								12
+							
+							
+								pwrdn_hbn_rtc
+								11
+								11
+							
+							
+								pwrdn_hbn_core
+								9
+								9
+							
+							
+								trap_mode
+								8
+								8
+							
+							
+								hbn_mode
+								7
+								7
+							
+							
+								rtc_ctl
+								0
+								6
+							
+						
+					
+					
+						HBN_TIME_L
+						HBN_TIME_L.
+						0x4
+						
+							
+								hbn_time_l
+								0
+								31
+							
+						
+					
+					
+						HBN_TIME_H
+						HBN_TIME_H.
+						0x8
+						
+							
+								hbn_time_h
+								0
+								7
+							
+						
+					
+					
+						RTC_TIME_L
+						RTC_TIME_L.
+						0xC
+						
+							
+								rtc_time_latch_l
+								0
+								31
+							
+						
+					
+					
+						RTC_TIME_H
+						RTC_TIME_H.
+						0x10
+						
+							
+								rtc_time_latch
+								31
+								31
+							
+							
+								rtc_time_latch_h
+								0
+								7
+							
+						
+					
+					
+						HBN_IRQ_MODE
+						HBN_IRQ_MODE.
+						0x14
+						
+							
+								pin_wakeup_en
+								27
+								27
+							
+							
+								pin_wakeup_sel
+								24
+								26
+							
+							
+								irq_acomp1_en
+								22
+								23
+							
+							
+								irq_acomp0_en
+								20
+								21
+							
+							
+								irq_bor_en
+								18
+								18
+							
+							
+								reg_en_hw_pu_pd
+								16
+								16
+							
+							
+								reg_aon_pad_ie_smt
+								8
+								12
+							
+							
+								hbn_pin_wakeup_mask
+								3
+								7
+							
+							
+								hbn_pin_wakeup_mode
+								0
+								2
+							
+						
+					
+					
+						HBN_IRQ_STAT
+						HBN_IRQ_STAT.
+						0x18
+						
+							
+								irq_stat
+								0
+								31
+							
+						
+					
+					
+						HBN_IRQ_CLR
+						HBN_IRQ_CLR.
+						0x1C
+						
+							
+								irq_clr
+								0
+								31
+							
+						
+					
+					
+						HBN_PIR_CFG
+						HBN_PIR_CFG.
+						0x20
+						
+							
+								gpadc_nosync
+								9
+								9
+							
+							
+								gpadc_cgen
+								8
+								8
+							
+							
+								pir_en
+								7
+								7
+							
+							
+								pir_dis
+								4
+								5
+							
+							
+								pir_lpf_sel
+								2
+								2
+							
+							
+								pir_hpf_sel
+								0
+								1
+							
+						
+					
+					
+						HBN_PIR_VTH
+						HBN_PIR_VTH.
+						0x24
+						
+							
+								pir_vth
+								0
+								13
+							
+						
+					
+					
+						HBN_PIR_INTERVAL
+						HBN_PIR_INTERVAL.
+						0x28
+						
+							
+								pir_interval
+								0
+								11
+							
+						
+					
+					
+						HBN_MISC
+						HBN_MISC.
+						0x2C
+						
+							
+								hbn_flash_pulldown_aon
+								24
+								29
+							
+							
+								hbn_flash_pullup_aon
+								16
+								21
+							
+							
+								r_bor_out
+								3
+								3
+							
+							
+								pu_bor
+								2
+								2
+							
+							
+								bor_vth
+								1
+								1
+							
+							
+								bor_sel
+								0
+								0
+							
+						
+					
+					
+						HBN_GLB
+						HBN_GLB.
+						0x30
+						
+							
+								sw_ldo11_aon_vout_sel
+								28
+								31
+							
+							
+								sw_ldo11_rt_vout_sel
+								24
+								27
+							
+							
+								sw_ldo11soc_vout_sel_aon
+								16
+								19
+							
+							
+								hbn_clear_reset_event
+								13
+								13
+							
+							
+								hbn_reset_event
+								8
+								12
+							
+							
+								ldo11_rt_iload_sel
+								6
+								7
+							
+							
+								hbn_pu_rc32k
+								5
+								5
+							
+							
+								hbn_f32k_sel
+								3
+								4
+							
+							
+								hbn_uart_clk_sel
+								2
+								2
+							
+							
+								hbn_root_clk_sel
+								0
+								1
+							
+						
+					
+					
+						HBN_SRAM
+						HBN_SRAM.
+						0x34
+						
+							
+								retram_slp
+								7
+								7
+							
+							
+								retram_ret
+								6
+								6
+							
+							
+								retram_emaw
+								3
+								4
+							
+							
+								retram_ema
+								0
+								2
+							
+						
+					
+					
+						HBN_RSV0
+						HBN_RSV0.
+						0x100
+						
+							
+								HBN_RSV0
+								0
+								31
+							
+						
+					
+					
+						HBN_RSV1
+						HBN_RSV1.
+						0x104
+						
+							
+								HBN_RSV1
+								0
+								31
+							
+						
+					
+					
+						HBN_RSV2
+						HBN_RSV2.
+						0x108
+						
+							
+								HBN_RSV2
+								0
+								31
+							
+						
+					
+					
+						HBN_RSV3
+						HBN_RSV3.
+						0x10C
+						
+							
+								HBN_RSV3
+								0
+								31
+							
+						
+					
+					
+						rc32k_ctrl0
+						rc32k_ctrl0.
+						0x200
+						
+							
+								rc32k_code_fr_ext
+								22
+								31
+							
+							
+								rc32k_cal_en
+								20
+								20
+							
+							
+								rc32k_ext_code_en
+								19
+								19
+							
+							
+								rc32k_allow_cal
+								18
+								18
+							
+							
+								rc32k_vref_dly
+								16
+								17
+							
+							
+								rc32k_dig_code_fr_cal
+								6
+								15
+							
+							
+								rc32k_cal_precharge
+								5
+								5
+							
+							
+								rc32k_cal_div
+								3
+								4
+							
+							
+								rc32k_cal_inprogress
+								2
+								2
+							
+							
+								rc32k_rdy
+								1
+								1
+							
+							
+								rc32k_cal_done
+								0
+								0
+							
+						
+					
+					
+						xtal32k
+						xtal32k.
+						0x204
+						
+							
+								pu_xtal32k
+								19
+								19
+							
+							
+								pu_xtal32k_buf
+								18
+								18
+							
+							
+								xtal32k_ac_cap_short
+								17
+								17
+							
+							
+								xtal32k_capbank
+								11
+								16
+							
+							
+								xtal32k_inv_stre
+								9
+								10
+							
+							
+								xtal32k_otf_short
+								8
+								8
+							
+							
+								xtal32k_outbuf_stre
+								7
+								7
+							
+							
+								xtal32k_reg
+								5
+								6
+							
+							
+								xtal32k_amp_ctrl
+								3
+								4
+							
+							
+								xtal32k_ext_sel
+								2
+								2
+							
+							
+								xtal32k_lowv_en
+								1
+								1
+							
+							
+								xtal32k_hiz_en
+								0
+								0
+							
+						
+					
+				
+			
+			
+				AON
+				AON.
+				
+				AON
+				32
+				read-write
+				
+					0
+					0x1000
+					registers
+				
+				
+					
+						aon
+						aon.
+						0x800
+						
+							
+								sw_pu_ldo11_rt
+								22
+								22
+							
+							
+								ldo11_rt_pulldown_sel
+								21
+								21
+							
+							
+								ldo11_rt_pulldown
+								20
+								20
+							
+							
+								pu_aon_dc_tbuf
+								12
+								12
+							
+							
+								aon_resv
+								0
+								7
+							
+						
+					
+					
+						aon_common
+						aon_common.
+						0x804
+						
+							
+								ten_cip_misc_aon
+								20
+								20
+							
+							
+								ten_mbg_aon
+								19
+								19
+							
+							
+								dten_xtal_aon
+								18
+								18
+							
+							
+								ten_xtal_aon
+								17
+								17
+							
+							
+								ten_ldo15rf_aon
+								16
+								16
+							
+							
+								ten_bg_sys_aon
+								12
+								12
+							
+							
+								ten_dcdc18_1_aon
+								11
+								11
+							
+							
+								ten_dcdc18_0_aon
+								10
+								10
+							
+							
+								ten_ldo11soc_aon
+								9
+								9
+							
+							
+								ten_vddcore_aon
+								8
+								8
+							
+							
+								ten_xtal32k
+								6
+								6
+							
+							
+								dten_xtal32k
+								5
+								5
+							
+							
+								ten_aon
+								4
+								4
+							
+							
+								tmux_aon
+								0
+								2
+							
+						
+					
+					
+						aon_misc
+						aon_misc.
+						0x808
+						
+							
+								sw_bz_en_aon
+								1
+								1
+							
+							
+								sw_soc_en_aon
+								0
+								0
+							
+						
+					
+					
+						bg_sys_top
+						bg_sys_top.
+						0x810
+						
+							
+								bg_sys_start_ctrl_aon
+								12
+								12
+							
+							
+								pu_bg_sys_aon
+								8
+								8
+							
+							
+								pmip_resv
+								0
+								7
+							
+						
+					
+					
+						dcdc18_top_0
+						dcdc18_top_0.
+						0x814
+						
+							
+								dcdc18_rdy_aon
+								31
+								31
+							
+							
+								dcdc18_sstart_time_aon
+								28
+								29
+							
+							
+								dcdc18_osc_inhibit_t2_aon
+								27
+								27
+							
+							
+								dcdc18_slow_osc_aon
+								26
+								26
+							
+							
+								dcdc18_stop_osc_aon
+								25
+								25
+							
+							
+								dcdc18_slope_curr_sel_aon
+								20
+								24
+							
+							
+								dcdc18_osc_freq_trim_aon
+								16
+								19
+							
+							
+								dcdc18_osc_2m_mode_aon
+								12
+								12
+							
+							
+								dcdc18_vpfm_aon
+								8
+								11
+							
+							
+								dcdc18_vout_sel_aon
+								1
+								5
+							
+						
+					
+					
+						dcdc18_top_1
+						dcdc18_top_1.
+						0x818
+						
+							
+								dcdc18_pulldown_aon
+								29
+								29
+							
+							
+								dcdc18_en_antiring_aon
+								28
+								28
+							
+							
+								dcdc18_cfb_sel_aon
+								24
+								27
+							
+							
+								dcdc18_chf_sel_aon
+								20
+								23
+							
+							
+								dcdc18_rc_sel_aon
+								16
+								19
+							
+							
+								dcdc18_nonoverlap_td_aon
+								8
+								12
+							
+							
+								dcdc18_zvs_td_opt_aon
+								4
+								6
+							
+							
+								dcdc18_cs_delay_aon
+								1
+								3
+							
+							
+								dcdc18_force_cs_zvs_aon
+								0
+								0
+							
+						
+					
+					
+						ldo11soc_and_dctest
+						ldo11soc_and_dctest.
+						0x81C
+						
+							
+								pmip_dc_tp_out_en_aon
+								31
+								31
+							
+							
+								pu_vddcore_misc_aon
+								30
+								30
+							
+							
+								ldo11soc_power_good_aon
+								29
+								29
+							
+							
+								ldo11soc_rdy_aon
+								28
+								28
+							
+							
+								ldo11soc_cc_aon
+								24
+								25
+							
+							
+								ldo11soc_vth_sel_aon
+								12
+								13
+							
+							
+								ldo11soc_pulldown_sel_aon
+								11
+								11
+							
+							
+								ldo11soc_pulldown_aon
+								10
+								10
+							
+							
+								ldo11soc_sstart_delay_aon
+								8
+								9
+							
+							
+								ldo11soc_sstart_sel_aon
+								4
+								4
+							
+							
+								pu_ldo11soc_aon
+								0
+								0
+							
+						
+					
+					
+						psw_irrcv
+						psw_irrcv.
+						0x820
+						
+							
+								pu_ir_psw_aon
+								0
+								0
+							
+						
+					
+					
+						rf_top_aon
+						rf_top_aon.
+						0x880
+						
+							
+								ldo15rf_bypass_aon
+								28
+								28
+							
+							
+								ldo15rf_cc_aon
+								24
+								25
+							
+							
+								ldo15rf_vout_sel_aon
+								16
+								18
+							
+							
+								ldo15rf_pulldown_sel_aon
+								13
+								13
+							
+							
+								ldo15rf_pulldown_aon
+								12
+								12
+							
+							
+								ldo15rf_sstart_delay_aon
+								9
+								10
+							
+							
+								ldo15rf_sstart_sel_aon
+								8
+								8
+							
+							
+								pu_xtal_aon
+								5
+								5
+							
+							
+								pu_xtal_buf_aon
+								4
+								4
+							
+							
+								pu_sfreg_aon
+								2
+								2
+							
+							
+								pu_ldo15rf_aon
+								1
+								1
+							
+							
+								pu_mbg_aon
+								0
+								0
+							
+						
+					
+					
+						xtal_cfg
+						xtal_cfg.
+						0x884
+						
+							
+								xtal_rdy_sel_aon
+								30
+								31
+							
+							
+								xtal_gm_boost_aon
+								28
+								29
+							
+							
+								xtal_capcode_in_aon
+								22
+								27
+							
+							
+								xtal_capcode_out_aon
+								16
+								21
+							
+							
+								xtal_amp_ctrl_aon
+								14
+								15
+							
+							
+								xtal_sleep_aon
+								13
+								13
+							
+							
+								xtal_fast_startup_aon
+								12
+								12
+							
+							
+								xtal_buf_hp_aon
+								8
+								11
+							
+							
+								xtal_buf_en_aon
+								4
+								7
+							
+							
+								xtal_ext_sel_aon
+								3
+								3
+							
+							
+								xtal_capcode_extra_aon
+								2
+								2
+							
+							
+								xtal_bk_aon
+								0
+								1
+							
+						
+					
+					
+						tsen
+						tsen.
+						0x888
+						
+							
+								xtal_rdy_int_sel_aon
+								30
+								31
+							
+							
+								xtal_inn_cfg_en_aon
+								29
+								29
+							
+							
+								xtal_rdy
+								28
+								28
+							
+							
+								tsen_refcode_rfcal
+								16
+								27
+							
+							
+								tsen_refcode_corner
+								0
+								11
+							
+						
+					
+					
+						acomp0_ctrl
+						acomp0_ctrl.
+						0x900
+						
+							
+								acomp0_muxen
+								26
+								26
+							
+							
+								acomp0_pos_sel
+								22
+								25
+							
+							
+								acomp0_neg_sel
+								18
+								21
+							
+							
+								acomp0_level_sel
+								12
+								17
+							
+							
+								acomp0_bias_prog
+								10
+								11
+							
+							
+								acomp0_hyst_selp
+								7
+								9
+							
+							
+								acomp0_hyst_seln
+								4
+								6
+							
+							
+								acomp0_en
+								0
+								0
+							
+						
+					
+					
+						acomp1_ctrl
+						acomp1_ctrl.
+						0x904
+						
+							
+								acomp1_muxen
+								26
+								26
+							
+							
+								acomp1_pos_sel
+								22
+								25
+							
+							
+								acomp1_neg_sel
+								18
+								21
+							
+							
+								acomp1_level_sel
+								12
+								17
+							
+							
+								acomp1_bias_prog
+								10
+								11
+							
+							
+								acomp1_hyst_selp
+								7
+								9
+							
+							
+								acomp1_hyst_seln
+								4
+								6
+							
+							
+								acomp1_en
+								0
+								0
+							
+						
+					
+					
+						acomp_ctrl
+						acomp_ctrl.
+						0x908
+						
+							
+								acomp_reserved
+								24
+								31
+							
+							
+								acomp0_out_raw
+								19
+								19
+							
+							
+								acomp1_out_raw
+								17
+								17
+							
+							
+								acomp0_test_sel
+								12
+								13
+							
+							
+								acomp1_test_sel
+								10
+								11
+							
+							
+								acomp0_test_en
+								9
+								9
+							
+							
+								acomp1_test_en
+								8
+								8
+							
+							
+								acomp0_rstn_ana
+								1
+								1
+							
+							
+								acomp1_rstn_ana
+								0
+								0
+							
+						
+					
+					
+						gpadc_reg_cmd
+						gpadc_reg_cmd.
+						0x90C
+						
+							
+								gpadc_sen_test_en
+								30
+								30
+							
+							
+								gpadc_sen_sel
+								28
+								29
+							
+							
+								gpadc_chip_sen_pu
+								27
+								27
+							
+							
+								gpadc_micboost_32db_en
+								23
+								23
+							
+							
+								gpadc_mic_pga2_gain
+								21
+								22
+							
+							
+								gpadc_mic1_diff
+								20
+								20
+							
+							
+								gpadc_mic2_diff
+								19
+								19
+							
+							
+								gpadc_dwa_en
+								18
+								18
+							
+							
+								gpadc_byp_micboost
+								16
+								16
+							
+							
+								gpadc_micpga_en
+								15
+								15
+							
+							
+								gpadc_micbias_en
+								14
+								14
+							
+							
+								gpadc_neg_gnd
+								13
+								13
+							
+							
+								gpadc_pos_sel
+								8
+								12
+							
+							
+								gpadc_neg_sel
+								3
+								7
+							
+							
+								gpadc_soft_rst
+								2
+								2
+							
+							
+								gpadc_conv_start
+								1
+								1
+							
+							
+								gpadc_global_en
+								0
+								0
+							
+						
+					
+					
+						gpadc_reg_config1
+						gpadc_reg_config1.
+						0x910
+						
+							
+								gpadc_v18_sel
+								29
+								30
+							
+							
+								gpadc_v11_sel
+								27
+								28
+							
+							
+								gpadc_dither_en
+								26
+								26
+							
+							
+								gpadc_scan_en
+								25
+								25
+							
+							
+								gpadc_scan_length
+								21
+								24
+							
+							
+								gpadc_clk_div_ratio
+								18
+								20
+							
+							
+								gpadc_clk_ana_inv
+								17
+								17
+							
+							
+								gpadc_lowv_det_en
+								10
+								10
+							
+							
+								gpadc_vcm_hyst_sel
+								9
+								9
+							
+							
+								gpadc_vcm_sel_en
+								8
+								8
+							
+							
+								gpadc_res_sel
+								2
+								4
+							
+							
+								gpadc_cont_conv_en
+								1
+								1
+							
+							
+								gpadc_cal_os_en
+								0
+								0
+							
+						
+					
+					
+						gpadc_reg_config2
+						gpadc_reg_config2.
+						0x914
+						
+							
+								gpadc_tsvbe_low
+								31
+								31
+							
+							
+								gpadc_dly_sel
+								28
+								30
+							
+							
+								gpadc_pga1_gain
+								25
+								27
+							
+							
+								gpadc_pga2_gain
+								22
+								24
+							
+							
+								gpadc_test_sel
+								19
+								21
+							
+							
+								gpadc_test_en
+								18
+								18
+							
+							
+								gpadc_bias_sel
+								17
+								17
+							
+							
+								gpadc_chop_mode
+								15
+								16
+							
+							
+								gpadc_pga_vcmi_en
+								14
+								14
+							
+							
+								gpadc_pga_en
+								13
+								13
+							
+							
+								gpadc_pga_os_cal
+								9
+								12
+							
+							
+								gpadc_pga_vcm
+								7
+								8
+							
+							
+								gpadc_ts_en
+								6
+								6
+							
+							
+								gpadc_tsext_sel
+								5
+								5
+							
+							
+								gpadc_vbat_en
+								4
+								4
+							
+							
+								gpadc_vref_sel
+								3
+								3
+							
+							
+								gpadc_diff_mode
+								2
+								2
+							
+						
+					
+					
+						gpadc_reg_scn_pos1
+						adc converation sequence 1
+						0x918
+						
+							
+								gpadc_scan_pos_5
+								25
+								29
+							
+							
+								gpadc_scan_pos_4
+								20
+								24
+							
+							
+								gpadc_scan_pos_3
+								15
+								19
+							
+							
+								gpadc_scan_pos_2
+								10
+								14
+							
+							
+								gpadc_scan_pos_1
+								5
+								9
+							
+							
+								gpadc_scan_pos_0
+								0
+								4
+							
+						
+					
+					
+						gpadc_reg_scn_pos2
+						adc converation sequence 2
+						0x91C
+						
+							
+								gpadc_scan_pos_11
+								25
+								29
+							
+							
+								gpadc_scan_pos_10
+								20
+								24
+							
+							
+								gpadc_scan_pos_9
+								15
+								19
+							
+							
+								gpadc_scan_pos_8
+								10
+								14
+							
+							
+								gpadc_scan_pos_7
+								5
+								9
+							
+							
+								gpadc_scan_pos_6
+								0
+								4
+							
+						
+					
+					
+						gpadc_reg_scn_neg1
+						adc converation sequence 3
+						0x920
+						
+							
+								gpadc_scan_neg_5
+								25
+								29
+							
+							
+								gpadc_scan_neg_4
+								20
+								24
+							
+							
+								gpadc_scan_neg_3
+								15
+								19
+							
+							
+								gpadc_scan_neg_2
+								10
+								14
+							
+							
+								gpadc_scan_neg_1
+								5
+								9
+							
+							
+								gpadc_scan_neg_0
+								0
+								4
+							
+						
+					
+					
+						gpadc_reg_scn_neg2
+						adc converation sequence 4
+						0x924
+						
+							
+								gpadc_scan_neg_11
+								25
+								29
+							
+							
+								gpadc_scan_neg_10
+								20
+								24
+							
+							
+								gpadc_scan_neg_9
+								15
+								19
+							
+							
+								gpadc_scan_neg_8
+								10
+								14
+							
+							
+								gpadc_scan_neg_7
+								5
+								9
+							
+							
+								gpadc_scan_neg_6
+								0
+								4
+							
+						
+					
+					
+						gpadc_reg_status
+						gpadc_reg_status.
+						0x928
+						
+							
+								gpadc_reserved
+								16
+								31
+							
+							
+								gpadc_data_rdy
+								0
+								0
+							
+						
+					
+					
+						gpadc_reg_isr
+						gpadc_reg_isr.
+						0x92C
+						
+							
+								gpadc_pos_satur_mask
+								9
+								9
+							
+							
+								gpadc_neg_satur_mask
+								8
+								8
+							
+							
+								gpadc_pos_satur_clr
+								5
+								5
+							
+							
+								gpadc_neg_satur_clr
+								4
+								4
+							
+							
+								gpadc_pos_satur
+								1
+								1
+							
+							
+								gpadc_neg_satur
+								0
+								0
+							
+						
+					
+					
+						gpadc_reg_result
+						gpadc_reg_result.
+						0x930
+						
+							
+								gpadc_data_out
+								0
+								25
+							
+						
+					
+					
+						gpadc_reg_raw_result
+						gpadc_reg_raw_result.
+						0x934
+						
+							
+								gpadc_raw_data
+								0
+								11
+							
+						
+					
+					
+						gpadc_reg_define
+						gpadc_reg_define.
+						0x938
+						
+							
+								gpadc_os_cal_data
+								0
+								15
+							
+						
+					
+					
+						hbncore_resv0
+						hbncore_resv0.
+						0x93C
+						
+							
+								hbncore_resv0_data
+								0
+								31
+							
+						
+					
+					
+						hbncore_resv1
+						hbncore_resv1.
+						0x940
+						
+							
+								hbncore_resv1_data
+								0
+								31
+							
+						
+					
+				
+			
+		
+	
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/spi_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/spi_reg.h
new file mode 100644
index 00000000..0ad7b7d9
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/spi_reg.h
@@ -0,0 +1,521 @@
+/**
+  ******************************************************************************
+  * @file    spi_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __SPI_REG_H__
+#define __SPI_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : spi_config */
+#define SPI_CONFIG_OFFSET           (0x0)
+#define SPI_CR_SPI_M_EN             SPI_CR_SPI_M_EN
+#define SPI_CR_SPI_M_EN_POS         (0U)
+#define SPI_CR_SPI_M_EN_LEN         (1U)
+#define SPI_CR_SPI_M_EN_MSK         (((1U << SPI_CR_SPI_M_EN_LEN) - 1) << SPI_CR_SPI_M_EN_POS)
+#define SPI_CR_SPI_M_EN_UMSK        (~(((1U << SPI_CR_SPI_M_EN_LEN) - 1) << SPI_CR_SPI_M_EN_POS))
+#define SPI_CR_SPI_S_EN             SPI_CR_SPI_S_EN
+#define SPI_CR_SPI_S_EN_POS         (1U)
+#define SPI_CR_SPI_S_EN_LEN         (1U)
+#define SPI_CR_SPI_S_EN_MSK         (((1U << SPI_CR_SPI_S_EN_LEN) - 1) << SPI_CR_SPI_S_EN_POS)
+#define SPI_CR_SPI_S_EN_UMSK        (~(((1U << SPI_CR_SPI_S_EN_LEN) - 1) << SPI_CR_SPI_S_EN_POS))
+#define SPI_CR_SPI_FRAME_SIZE       SPI_CR_SPI_FRAME_SIZE
+#define SPI_CR_SPI_FRAME_SIZE_POS   (2U)
+#define SPI_CR_SPI_FRAME_SIZE_LEN   (2U)
+#define SPI_CR_SPI_FRAME_SIZE_MSK   (((1U << SPI_CR_SPI_FRAME_SIZE_LEN) - 1) << SPI_CR_SPI_FRAME_SIZE_POS)
+#define SPI_CR_SPI_FRAME_SIZE_UMSK  (~(((1U << SPI_CR_SPI_FRAME_SIZE_LEN) - 1) << SPI_CR_SPI_FRAME_SIZE_POS))
+#define SPI_CR_SPI_SCLK_POL         SPI_CR_SPI_SCLK_POL
+#define SPI_CR_SPI_SCLK_POL_POS     (4U)
+#define SPI_CR_SPI_SCLK_POL_LEN     (1U)
+#define SPI_CR_SPI_SCLK_POL_MSK     (((1U << SPI_CR_SPI_SCLK_POL_LEN) - 1) << SPI_CR_SPI_SCLK_POL_POS)
+#define SPI_CR_SPI_SCLK_POL_UMSK    (~(((1U << SPI_CR_SPI_SCLK_POL_LEN) - 1) << SPI_CR_SPI_SCLK_POL_POS))
+#define SPI_CR_SPI_SCLK_PH          SPI_CR_SPI_SCLK_PH
+#define SPI_CR_SPI_SCLK_PH_POS      (5U)
+#define SPI_CR_SPI_SCLK_PH_LEN      (1U)
+#define SPI_CR_SPI_SCLK_PH_MSK      (((1U << SPI_CR_SPI_SCLK_PH_LEN) - 1) << SPI_CR_SPI_SCLK_PH_POS)
+#define SPI_CR_SPI_SCLK_PH_UMSK     (~(((1U << SPI_CR_SPI_SCLK_PH_LEN) - 1) << SPI_CR_SPI_SCLK_PH_POS))
+#define SPI_CR_SPI_BIT_INV          SPI_CR_SPI_BIT_INV
+#define SPI_CR_SPI_BIT_INV_POS      (6U)
+#define SPI_CR_SPI_BIT_INV_LEN      (1U)
+#define SPI_CR_SPI_BIT_INV_MSK      (((1U << SPI_CR_SPI_BIT_INV_LEN) - 1) << SPI_CR_SPI_BIT_INV_POS)
+#define SPI_CR_SPI_BIT_INV_UMSK     (~(((1U << SPI_CR_SPI_BIT_INV_LEN) - 1) << SPI_CR_SPI_BIT_INV_POS))
+#define SPI_CR_SPI_BYTE_INV         SPI_CR_SPI_BYTE_INV
+#define SPI_CR_SPI_BYTE_INV_POS     (7U)
+#define SPI_CR_SPI_BYTE_INV_LEN     (1U)
+#define SPI_CR_SPI_BYTE_INV_MSK     (((1U << SPI_CR_SPI_BYTE_INV_LEN) - 1) << SPI_CR_SPI_BYTE_INV_POS)
+#define SPI_CR_SPI_BYTE_INV_UMSK    (~(((1U << SPI_CR_SPI_BYTE_INV_LEN) - 1) << SPI_CR_SPI_BYTE_INV_POS))
+#define SPI_CR_SPI_RXD_IGNR_EN      SPI_CR_SPI_RXD_IGNR_EN
+#define SPI_CR_SPI_RXD_IGNR_EN_POS  (8U)
+#define SPI_CR_SPI_RXD_IGNR_EN_LEN  (1U)
+#define SPI_CR_SPI_RXD_IGNR_EN_MSK  (((1U << SPI_CR_SPI_RXD_IGNR_EN_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_EN_POS)
+#define SPI_CR_SPI_RXD_IGNR_EN_UMSK (~(((1U << SPI_CR_SPI_RXD_IGNR_EN_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_EN_POS))
+#define SPI_CR_SPI_M_CONT_EN        SPI_CR_SPI_M_CONT_EN
+#define SPI_CR_SPI_M_CONT_EN_POS    (9U)
+#define SPI_CR_SPI_M_CONT_EN_LEN    (1U)
+#define SPI_CR_SPI_M_CONT_EN_MSK    (((1U << SPI_CR_SPI_M_CONT_EN_LEN) - 1) << SPI_CR_SPI_M_CONT_EN_POS)
+#define SPI_CR_SPI_M_CONT_EN_UMSK   (~(((1U << SPI_CR_SPI_M_CONT_EN_LEN) - 1) << SPI_CR_SPI_M_CONT_EN_POS))
+#define SPI_CR_SPI_DEG_EN           SPI_CR_SPI_DEG_EN
+#define SPI_CR_SPI_DEG_EN_POS       (11U)
+#define SPI_CR_SPI_DEG_EN_LEN       (1U)
+#define SPI_CR_SPI_DEG_EN_MSK       (((1U << SPI_CR_SPI_DEG_EN_LEN) - 1) << SPI_CR_SPI_DEG_EN_POS)
+#define SPI_CR_SPI_DEG_EN_UMSK      (~(((1U << SPI_CR_SPI_DEG_EN_LEN) - 1) << SPI_CR_SPI_DEG_EN_POS))
+#define SPI_CR_SPI_DEG_CNT          SPI_CR_SPI_DEG_CNT
+#define SPI_CR_SPI_DEG_CNT_POS      (12U)
+#define SPI_CR_SPI_DEG_CNT_LEN      (4U)
+#define SPI_CR_SPI_DEG_CNT_MSK      (((1U << SPI_CR_SPI_DEG_CNT_LEN) - 1) << SPI_CR_SPI_DEG_CNT_POS)
+#define SPI_CR_SPI_DEG_CNT_UMSK     (~(((1U << SPI_CR_SPI_DEG_CNT_LEN) - 1) << SPI_CR_SPI_DEG_CNT_POS))
+
+/* 0x4 : spi_int_sts */
+#define SPI_INT_STS_OFFSET       (0x4)
+#define SPI_END_INT              SPI_END_INT
+#define SPI_END_INT_POS          (0U)
+#define SPI_END_INT_LEN          (1U)
+#define SPI_END_INT_MSK          (((1U << SPI_END_INT_LEN) - 1) << SPI_END_INT_POS)
+#define SPI_END_INT_UMSK         (~(((1U << SPI_END_INT_LEN) - 1) << SPI_END_INT_POS))
+#define SPI_TXF_INT              SPI_TXF_INT
+#define SPI_TXF_INT_POS          (1U)
+#define SPI_TXF_INT_LEN          (1U)
+#define SPI_TXF_INT_MSK          (((1U << SPI_TXF_INT_LEN) - 1) << SPI_TXF_INT_POS)
+#define SPI_TXF_INT_UMSK         (~(((1U << SPI_TXF_INT_LEN) - 1) << SPI_TXF_INT_POS))
+#define SPI_RXF_INT              SPI_RXF_INT
+#define SPI_RXF_INT_POS          (2U)
+#define SPI_RXF_INT_LEN          (1U)
+#define SPI_RXF_INT_MSK          (((1U << SPI_RXF_INT_LEN) - 1) << SPI_RXF_INT_POS)
+#define SPI_RXF_INT_UMSK         (~(((1U << SPI_RXF_INT_LEN) - 1) << SPI_RXF_INT_POS))
+#define SPI_STO_INT              SPI_STO_INT
+#define SPI_STO_INT_POS          (3U)
+#define SPI_STO_INT_LEN          (1U)
+#define SPI_STO_INT_MSK          (((1U << SPI_STO_INT_LEN) - 1) << SPI_STO_INT_POS)
+#define SPI_STO_INT_UMSK         (~(((1U << SPI_STO_INT_LEN) - 1) << SPI_STO_INT_POS))
+#define SPI_TXU_INT              SPI_TXU_INT
+#define SPI_TXU_INT_POS          (4U)
+#define SPI_TXU_INT_LEN          (1U)
+#define SPI_TXU_INT_MSK          (((1U << SPI_TXU_INT_LEN) - 1) << SPI_TXU_INT_POS)
+#define SPI_TXU_INT_UMSK         (~(((1U << SPI_TXU_INT_LEN) - 1) << SPI_TXU_INT_POS))
+#define SPI_FER_INT              SPI_FER_INT
+#define SPI_FER_INT_POS          (5U)
+#define SPI_FER_INT_LEN          (1U)
+#define SPI_FER_INT_MSK          (((1U << SPI_FER_INT_LEN) - 1) << SPI_FER_INT_POS)
+#define SPI_FER_INT_UMSK         (~(((1U << SPI_FER_INT_LEN) - 1) << SPI_FER_INT_POS))
+#define SPI_CR_SPI_END_MASK      SPI_CR_SPI_END_MASK
+#define SPI_CR_SPI_END_MASK_POS  (8U)
+#define SPI_CR_SPI_END_MASK_LEN  (1U)
+#define SPI_CR_SPI_END_MASK_MSK  (((1U << SPI_CR_SPI_END_MASK_LEN) - 1) << SPI_CR_SPI_END_MASK_POS)
+#define SPI_CR_SPI_END_MASK_UMSK (~(((1U << SPI_CR_SPI_END_MASK_LEN) - 1) << SPI_CR_SPI_END_MASK_POS))
+#define SPI_CR_SPI_TXF_MASK      SPI_CR_SPI_TXF_MASK
+#define SPI_CR_SPI_TXF_MASK_POS  (9U)
+#define SPI_CR_SPI_TXF_MASK_LEN  (1U)
+#define SPI_CR_SPI_TXF_MASK_MSK  (((1U << SPI_CR_SPI_TXF_MASK_LEN) - 1) << SPI_CR_SPI_TXF_MASK_POS)
+#define SPI_CR_SPI_TXF_MASK_UMSK (~(((1U << SPI_CR_SPI_TXF_MASK_LEN) - 1) << SPI_CR_SPI_TXF_MASK_POS))
+#define SPI_CR_SPI_RXF_MASK      SPI_CR_SPI_RXF_MASK
+#define SPI_CR_SPI_RXF_MASK_POS  (10U)
+#define SPI_CR_SPI_RXF_MASK_LEN  (1U)
+#define SPI_CR_SPI_RXF_MASK_MSK  (((1U << SPI_CR_SPI_RXF_MASK_LEN) - 1) << SPI_CR_SPI_RXF_MASK_POS)
+#define SPI_CR_SPI_RXF_MASK_UMSK (~(((1U << SPI_CR_SPI_RXF_MASK_LEN) - 1) << SPI_CR_SPI_RXF_MASK_POS))
+#define SPI_CR_SPI_STO_MASK      SPI_CR_SPI_STO_MASK
+#define SPI_CR_SPI_STO_MASK_POS  (11U)
+#define SPI_CR_SPI_STO_MASK_LEN  (1U)
+#define SPI_CR_SPI_STO_MASK_MSK  (((1U << SPI_CR_SPI_STO_MASK_LEN) - 1) << SPI_CR_SPI_STO_MASK_POS)
+#define SPI_CR_SPI_STO_MASK_UMSK (~(((1U << SPI_CR_SPI_STO_MASK_LEN) - 1) << SPI_CR_SPI_STO_MASK_POS))
+#define SPI_CR_SPI_TXU_MASK      SPI_CR_SPI_TXU_MASK
+#define SPI_CR_SPI_TXU_MASK_POS  (12U)
+#define SPI_CR_SPI_TXU_MASK_LEN  (1U)
+#define SPI_CR_SPI_TXU_MASK_MSK  (((1U << SPI_CR_SPI_TXU_MASK_LEN) - 1) << SPI_CR_SPI_TXU_MASK_POS)
+#define SPI_CR_SPI_TXU_MASK_UMSK (~(((1U << SPI_CR_SPI_TXU_MASK_LEN) - 1) << SPI_CR_SPI_TXU_MASK_POS))
+#define SPI_CR_SPI_FER_MASK      SPI_CR_SPI_FER_MASK
+#define SPI_CR_SPI_FER_MASK_POS  (13U)
+#define SPI_CR_SPI_FER_MASK_LEN  (1U)
+#define SPI_CR_SPI_FER_MASK_MSK  (((1U << SPI_CR_SPI_FER_MASK_LEN) - 1) << SPI_CR_SPI_FER_MASK_POS)
+#define SPI_CR_SPI_FER_MASK_UMSK (~(((1U << SPI_CR_SPI_FER_MASK_LEN) - 1) << SPI_CR_SPI_FER_MASK_POS))
+#define SPI_CR_SPI_END_CLR       SPI_CR_SPI_END_CLR
+#define SPI_CR_SPI_END_CLR_POS   (16U)
+#define SPI_CR_SPI_END_CLR_LEN   (1U)
+#define SPI_CR_SPI_END_CLR_MSK   (((1U << SPI_CR_SPI_END_CLR_LEN) - 1) << SPI_CR_SPI_END_CLR_POS)
+#define SPI_CR_SPI_END_CLR_UMSK  (~(((1U << SPI_CR_SPI_END_CLR_LEN) - 1) << SPI_CR_SPI_END_CLR_POS))
+#define SPI_CR_SPI_STO_CLR       SPI_CR_SPI_STO_CLR
+#define SPI_CR_SPI_STO_CLR_POS   (19U)
+#define SPI_CR_SPI_STO_CLR_LEN   (1U)
+#define SPI_CR_SPI_STO_CLR_MSK   (((1U << SPI_CR_SPI_STO_CLR_LEN) - 1) << SPI_CR_SPI_STO_CLR_POS)
+#define SPI_CR_SPI_STO_CLR_UMSK  (~(((1U << SPI_CR_SPI_STO_CLR_LEN) - 1) << SPI_CR_SPI_STO_CLR_POS))
+#define SPI_CR_SPI_TXU_CLR       SPI_CR_SPI_TXU_CLR
+#define SPI_CR_SPI_TXU_CLR_POS   (20U)
+#define SPI_CR_SPI_TXU_CLR_LEN   (1U)
+#define SPI_CR_SPI_TXU_CLR_MSK   (((1U << SPI_CR_SPI_TXU_CLR_LEN) - 1) << SPI_CR_SPI_TXU_CLR_POS)
+#define SPI_CR_SPI_TXU_CLR_UMSK  (~(((1U << SPI_CR_SPI_TXU_CLR_LEN) - 1) << SPI_CR_SPI_TXU_CLR_POS))
+#define SPI_CR_SPI_END_EN        SPI_CR_SPI_END_EN
+#define SPI_CR_SPI_END_EN_POS    (24U)
+#define SPI_CR_SPI_END_EN_LEN    (1U)
+#define SPI_CR_SPI_END_EN_MSK    (((1U << SPI_CR_SPI_END_EN_LEN) - 1) << SPI_CR_SPI_END_EN_POS)
+#define SPI_CR_SPI_END_EN_UMSK   (~(((1U << SPI_CR_SPI_END_EN_LEN) - 1) << SPI_CR_SPI_END_EN_POS))
+#define SPI_CR_SPI_TXF_EN        SPI_CR_SPI_TXF_EN
+#define SPI_CR_SPI_TXF_EN_POS    (25U)
+#define SPI_CR_SPI_TXF_EN_LEN    (1U)
+#define SPI_CR_SPI_TXF_EN_MSK    (((1U << SPI_CR_SPI_TXF_EN_LEN) - 1) << SPI_CR_SPI_TXF_EN_POS)
+#define SPI_CR_SPI_TXF_EN_UMSK   (~(((1U << SPI_CR_SPI_TXF_EN_LEN) - 1) << SPI_CR_SPI_TXF_EN_POS))
+#define SPI_CR_SPI_RXF_EN        SPI_CR_SPI_RXF_EN
+#define SPI_CR_SPI_RXF_EN_POS    (26U)
+#define SPI_CR_SPI_RXF_EN_LEN    (1U)
+#define SPI_CR_SPI_RXF_EN_MSK    (((1U << SPI_CR_SPI_RXF_EN_LEN) - 1) << SPI_CR_SPI_RXF_EN_POS)
+#define SPI_CR_SPI_RXF_EN_UMSK   (~(((1U << SPI_CR_SPI_RXF_EN_LEN) - 1) << SPI_CR_SPI_RXF_EN_POS))
+#define SPI_CR_SPI_STO_EN        SPI_CR_SPI_STO_EN
+#define SPI_CR_SPI_STO_EN_POS    (27U)
+#define SPI_CR_SPI_STO_EN_LEN    (1U)
+#define SPI_CR_SPI_STO_EN_MSK    (((1U << SPI_CR_SPI_STO_EN_LEN) - 1) << SPI_CR_SPI_STO_EN_POS)
+#define SPI_CR_SPI_STO_EN_UMSK   (~(((1U << SPI_CR_SPI_STO_EN_LEN) - 1) << SPI_CR_SPI_STO_EN_POS))
+#define SPI_CR_SPI_TXU_EN        SPI_CR_SPI_TXU_EN
+#define SPI_CR_SPI_TXU_EN_POS    (28U)
+#define SPI_CR_SPI_TXU_EN_LEN    (1U)
+#define SPI_CR_SPI_TXU_EN_MSK    (((1U << SPI_CR_SPI_TXU_EN_LEN) - 1) << SPI_CR_SPI_TXU_EN_POS)
+#define SPI_CR_SPI_TXU_EN_UMSK   (~(((1U << SPI_CR_SPI_TXU_EN_LEN) - 1) << SPI_CR_SPI_TXU_EN_POS))
+#define SPI_CR_SPI_FER_EN        SPI_CR_SPI_FER_EN
+#define SPI_CR_SPI_FER_EN_POS    (29U)
+#define SPI_CR_SPI_FER_EN_LEN    (1U)
+#define SPI_CR_SPI_FER_EN_MSK    (((1U << SPI_CR_SPI_FER_EN_LEN) - 1) << SPI_CR_SPI_FER_EN_POS)
+#define SPI_CR_SPI_FER_EN_UMSK   (~(((1U << SPI_CR_SPI_FER_EN_LEN) - 1) << SPI_CR_SPI_FER_EN_POS))
+
+/* 0x8 : spi_bus_busy */
+#define SPI_BUS_BUSY_OFFSET       (0x8)
+#define SPI_STS_SPI_BUS_BUSY      SPI_STS_SPI_BUS_BUSY
+#define SPI_STS_SPI_BUS_BUSY_POS  (0U)
+#define SPI_STS_SPI_BUS_BUSY_LEN  (1U)
+#define SPI_STS_SPI_BUS_BUSY_MSK  (((1U << SPI_STS_SPI_BUS_BUSY_LEN) - 1) << SPI_STS_SPI_BUS_BUSY_POS)
+#define SPI_STS_SPI_BUS_BUSY_UMSK (~(((1U << SPI_STS_SPI_BUS_BUSY_LEN) - 1) << SPI_STS_SPI_BUS_BUSY_POS))
+
+/* 0x10 : spi_prd_0 */
+#define SPI_PRD_0_OFFSET           (0x10)
+#define SPI_CR_SPI_PRD_S           SPI_CR_SPI_PRD_S
+#define SPI_CR_SPI_PRD_S_POS       (0U)
+#define SPI_CR_SPI_PRD_S_LEN       (8U)
+#define SPI_CR_SPI_PRD_S_MSK       (((1U << SPI_CR_SPI_PRD_S_LEN) - 1) << SPI_CR_SPI_PRD_S_POS)
+#define SPI_CR_SPI_PRD_S_UMSK      (~(((1U << SPI_CR_SPI_PRD_S_LEN) - 1) << SPI_CR_SPI_PRD_S_POS))
+#define SPI_CR_SPI_PRD_P           SPI_CR_SPI_PRD_P
+#define SPI_CR_SPI_PRD_P_POS       (8U)
+#define SPI_CR_SPI_PRD_P_LEN       (8U)
+#define SPI_CR_SPI_PRD_P_MSK       (((1U << SPI_CR_SPI_PRD_P_LEN) - 1) << SPI_CR_SPI_PRD_P_POS)
+#define SPI_CR_SPI_PRD_P_UMSK      (~(((1U << SPI_CR_SPI_PRD_P_LEN) - 1) << SPI_CR_SPI_PRD_P_POS))
+#define SPI_CR_SPI_PRD_D_PH_0      SPI_CR_SPI_PRD_D_PH_0
+#define SPI_CR_SPI_PRD_D_PH_0_POS  (16U)
+#define SPI_CR_SPI_PRD_D_PH_0_LEN  (8U)
+#define SPI_CR_SPI_PRD_D_PH_0_MSK  (((1U << SPI_CR_SPI_PRD_D_PH_0_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_0_POS)
+#define SPI_CR_SPI_PRD_D_PH_0_UMSK (~(((1U << SPI_CR_SPI_PRD_D_PH_0_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_0_POS))
+#define SPI_CR_SPI_PRD_D_PH_1      SPI_CR_SPI_PRD_D_PH_1
+#define SPI_CR_SPI_PRD_D_PH_1_POS  (24U)
+#define SPI_CR_SPI_PRD_D_PH_1_LEN  (8U)
+#define SPI_CR_SPI_PRD_D_PH_1_MSK  (((1U << SPI_CR_SPI_PRD_D_PH_1_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_1_POS)
+#define SPI_CR_SPI_PRD_D_PH_1_UMSK (~(((1U << SPI_CR_SPI_PRD_D_PH_1_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_1_POS))
+
+/* 0x14 : spi_prd_1 */
+#define SPI_PRD_1_OFFSET      (0x14)
+#define SPI_CR_SPI_PRD_I      SPI_CR_SPI_PRD_I
+#define SPI_CR_SPI_PRD_I_POS  (0U)
+#define SPI_CR_SPI_PRD_I_LEN  (8U)
+#define SPI_CR_SPI_PRD_I_MSK  (((1U << SPI_CR_SPI_PRD_I_LEN) - 1) << SPI_CR_SPI_PRD_I_POS)
+#define SPI_CR_SPI_PRD_I_UMSK (~(((1U << SPI_CR_SPI_PRD_I_LEN) - 1) << SPI_CR_SPI_PRD_I_POS))
+
+/* 0x18 : spi_rxd_ignr */
+#define SPI_RXD_IGNR_OFFSET        (0x18)
+#define SPI_CR_SPI_RXD_IGNR_P      SPI_CR_SPI_RXD_IGNR_P
+#define SPI_CR_SPI_RXD_IGNR_P_POS  (0U)
+#define SPI_CR_SPI_RXD_IGNR_P_LEN  (5U)
+#define SPI_CR_SPI_RXD_IGNR_P_MSK  (((1U << SPI_CR_SPI_RXD_IGNR_P_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_P_POS)
+#define SPI_CR_SPI_RXD_IGNR_P_UMSK (~(((1U << SPI_CR_SPI_RXD_IGNR_P_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_P_POS))
+#define SPI_CR_SPI_RXD_IGNR_S      SPI_CR_SPI_RXD_IGNR_S
+#define SPI_CR_SPI_RXD_IGNR_S_POS  (16U)
+#define SPI_CR_SPI_RXD_IGNR_S_LEN  (5U)
+#define SPI_CR_SPI_RXD_IGNR_S_MSK  (((1U << SPI_CR_SPI_RXD_IGNR_S_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_S_POS)
+#define SPI_CR_SPI_RXD_IGNR_S_UMSK (~(((1U << SPI_CR_SPI_RXD_IGNR_S_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_S_POS))
+
+/* 0x1C : spi_sto_value */
+#define SPI_STO_VALUE_OFFSET      (0x1C)
+#define SPI_CR_SPI_STO_VALUE      SPI_CR_SPI_STO_VALUE
+#define SPI_CR_SPI_STO_VALUE_POS  (0U)
+#define SPI_CR_SPI_STO_VALUE_LEN  (12U)
+#define SPI_CR_SPI_STO_VALUE_MSK  (((1U << SPI_CR_SPI_STO_VALUE_LEN) - 1) << SPI_CR_SPI_STO_VALUE_POS)
+#define SPI_CR_SPI_STO_VALUE_UMSK (~(((1U << SPI_CR_SPI_STO_VALUE_LEN) - 1) << SPI_CR_SPI_STO_VALUE_POS))
+
+/* 0x80 : spi_fifo_config_0 */
+#define SPI_FIFO_CONFIG_0_OFFSET   (0x80)
+#define SPI_DMA_TX_EN              SPI_DMA_TX_EN
+#define SPI_DMA_TX_EN_POS          (0U)
+#define SPI_DMA_TX_EN_LEN          (1U)
+#define SPI_DMA_TX_EN_MSK          (((1U << SPI_DMA_TX_EN_LEN) - 1) << SPI_DMA_TX_EN_POS)
+#define SPI_DMA_TX_EN_UMSK         (~(((1U << SPI_DMA_TX_EN_LEN) - 1) << SPI_DMA_TX_EN_POS))
+#define SPI_DMA_RX_EN              SPI_DMA_RX_EN
+#define SPI_DMA_RX_EN_POS          (1U)
+#define SPI_DMA_RX_EN_LEN          (1U)
+#define SPI_DMA_RX_EN_MSK          (((1U << SPI_DMA_RX_EN_LEN) - 1) << SPI_DMA_RX_EN_POS)
+#define SPI_DMA_RX_EN_UMSK         (~(((1U << SPI_DMA_RX_EN_LEN) - 1) << SPI_DMA_RX_EN_POS))
+#define SPI_TX_FIFO_CLR            SPI_TX_FIFO_CLR
+#define SPI_TX_FIFO_CLR_POS        (2U)
+#define SPI_TX_FIFO_CLR_LEN        (1U)
+#define SPI_TX_FIFO_CLR_MSK        (((1U << SPI_TX_FIFO_CLR_LEN) - 1) << SPI_TX_FIFO_CLR_POS)
+#define SPI_TX_FIFO_CLR_UMSK       (~(((1U << SPI_TX_FIFO_CLR_LEN) - 1) << SPI_TX_FIFO_CLR_POS))
+#define SPI_RX_FIFO_CLR            SPI_RX_FIFO_CLR
+#define SPI_RX_FIFO_CLR_POS        (3U)
+#define SPI_RX_FIFO_CLR_LEN        (1U)
+#define SPI_RX_FIFO_CLR_MSK        (((1U << SPI_RX_FIFO_CLR_LEN) - 1) << SPI_RX_FIFO_CLR_POS)
+#define SPI_RX_FIFO_CLR_UMSK       (~(((1U << SPI_RX_FIFO_CLR_LEN) - 1) << SPI_RX_FIFO_CLR_POS))
+#define SPI_TX_FIFO_OVERFLOW       SPI_TX_FIFO_OVERFLOW
+#define SPI_TX_FIFO_OVERFLOW_POS   (4U)
+#define SPI_TX_FIFO_OVERFLOW_LEN   (1U)
+#define SPI_TX_FIFO_OVERFLOW_MSK   (((1U << SPI_TX_FIFO_OVERFLOW_LEN) - 1) << SPI_TX_FIFO_OVERFLOW_POS)
+#define SPI_TX_FIFO_OVERFLOW_UMSK  (~(((1U << SPI_TX_FIFO_OVERFLOW_LEN) - 1) << SPI_TX_FIFO_OVERFLOW_POS))
+#define SPI_TX_FIFO_UNDERFLOW      SPI_TX_FIFO_UNDERFLOW
+#define SPI_TX_FIFO_UNDERFLOW_POS  (5U)
+#define SPI_TX_FIFO_UNDERFLOW_LEN  (1U)
+#define SPI_TX_FIFO_UNDERFLOW_MSK  (((1U << SPI_TX_FIFO_UNDERFLOW_LEN) - 1) << SPI_TX_FIFO_UNDERFLOW_POS)
+#define SPI_TX_FIFO_UNDERFLOW_UMSK (~(((1U << SPI_TX_FIFO_UNDERFLOW_LEN) - 1) << SPI_TX_FIFO_UNDERFLOW_POS))
+#define SPI_RX_FIFO_OVERFLOW       SPI_RX_FIFO_OVERFLOW
+#define SPI_RX_FIFO_OVERFLOW_POS   (6U)
+#define SPI_RX_FIFO_OVERFLOW_LEN   (1U)
+#define SPI_RX_FIFO_OVERFLOW_MSK   (((1U << SPI_RX_FIFO_OVERFLOW_LEN) - 1) << SPI_RX_FIFO_OVERFLOW_POS)
+#define SPI_RX_FIFO_OVERFLOW_UMSK  (~(((1U << SPI_RX_FIFO_OVERFLOW_LEN) - 1) << SPI_RX_FIFO_OVERFLOW_POS))
+#define SPI_RX_FIFO_UNDERFLOW      SPI_RX_FIFO_UNDERFLOW
+#define SPI_RX_FIFO_UNDERFLOW_POS  (7U)
+#define SPI_RX_FIFO_UNDERFLOW_LEN  (1U)
+#define SPI_RX_FIFO_UNDERFLOW_MSK  (((1U << SPI_RX_FIFO_UNDERFLOW_LEN) - 1) << SPI_RX_FIFO_UNDERFLOW_POS)
+#define SPI_RX_FIFO_UNDERFLOW_UMSK (~(((1U << SPI_RX_FIFO_UNDERFLOW_LEN) - 1) << SPI_RX_FIFO_UNDERFLOW_POS))
+
+/* 0x84 : spi_fifo_config_1 */
+#define SPI_FIFO_CONFIG_1_OFFSET (0x84)
+#define SPI_TX_FIFO_CNT          SPI_TX_FIFO_CNT
+#define SPI_TX_FIFO_CNT_POS      (0U)
+#define SPI_TX_FIFO_CNT_LEN      (3U)
+#define SPI_TX_FIFO_CNT_MSK      (((1U << SPI_TX_FIFO_CNT_LEN) - 1) << SPI_TX_FIFO_CNT_POS)
+#define SPI_TX_FIFO_CNT_UMSK     (~(((1U << SPI_TX_FIFO_CNT_LEN) - 1) << SPI_TX_FIFO_CNT_POS))
+#define SPI_RX_FIFO_CNT          SPI_RX_FIFO_CNT
+#define SPI_RX_FIFO_CNT_POS      (8U)
+#define SPI_RX_FIFO_CNT_LEN      (3U)
+#define SPI_RX_FIFO_CNT_MSK      (((1U << SPI_RX_FIFO_CNT_LEN) - 1) << SPI_RX_FIFO_CNT_POS)
+#define SPI_RX_FIFO_CNT_UMSK     (~(((1U << SPI_RX_FIFO_CNT_LEN) - 1) << SPI_RX_FIFO_CNT_POS))
+#define SPI_TX_FIFO_TH           SPI_TX_FIFO_TH
+#define SPI_TX_FIFO_TH_POS       (16U)
+#define SPI_TX_FIFO_TH_LEN       (2U)
+#define SPI_TX_FIFO_TH_MSK       (((1U << SPI_TX_FIFO_TH_LEN) - 1) << SPI_TX_FIFO_TH_POS)
+#define SPI_TX_FIFO_TH_UMSK      (~(((1U << SPI_TX_FIFO_TH_LEN) - 1) << SPI_TX_FIFO_TH_POS))
+#define SPI_RX_FIFO_TH           SPI_RX_FIFO_TH
+#define SPI_RX_FIFO_TH_POS       (24U)
+#define SPI_RX_FIFO_TH_LEN       (2U)
+#define SPI_RX_FIFO_TH_MSK       (((1U << SPI_RX_FIFO_TH_LEN) - 1) << SPI_RX_FIFO_TH_POS)
+#define SPI_RX_FIFO_TH_UMSK      (~(((1U << SPI_RX_FIFO_TH_LEN) - 1) << SPI_RX_FIFO_TH_POS))
+
+/* 0x88 : spi_fifo_wdata */
+#define SPI_FIFO_WDATA_OFFSET (0x88)
+#define SPI_FIFO_WDATA        SPI_FIFO_WDATA
+#define SPI_FIFO_WDATA_POS    (0U)
+#define SPI_FIFO_WDATA_LEN    (32U)
+#define SPI_FIFO_WDATA_MSK    (((1U << SPI_FIFO_WDATA_LEN) - 1) << SPI_FIFO_WDATA_POS)
+#define SPI_FIFO_WDATA_UMSK   (~(((1U << SPI_FIFO_WDATA_LEN) - 1) << SPI_FIFO_WDATA_POS))
+
+/* 0x8C : spi_fifo_rdata */
+#define SPI_FIFO_RDATA_OFFSET (0x8C)
+#define SPI_FIFO_RDATA        SPI_FIFO_RDATA
+#define SPI_FIFO_RDATA_POS    (0U)
+#define SPI_FIFO_RDATA_LEN    (32U)
+#define SPI_FIFO_RDATA_MSK    (((1U << SPI_FIFO_RDATA_LEN) - 1) << SPI_FIFO_RDATA_POS)
+#define SPI_FIFO_RDATA_UMSK   (~(((1U << SPI_FIFO_RDATA_LEN) - 1) << SPI_FIFO_RDATA_POS))
+
+struct spi_reg {
+    /* 0x0 : spi_config */
+    union {
+        struct
+        {
+            uint32_t cr_spi_m_en        : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t cr_spi_s_en        : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t cr_spi_frame_size  : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t cr_spi_sclk_pol    : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t cr_spi_sclk_ph     : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t cr_spi_bit_inv     : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t cr_spi_byte_inv    : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t cr_spi_rxd_ignr_en : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t cr_spi_m_cont_en   : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t reserved_10        : 1;  /* [   10],       rsvd,        0x0 */
+            uint32_t cr_spi_deg_en      : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t cr_spi_deg_cnt     : 4;  /* [15:12],        r/w,        0x0 */
+            uint32_t reserved_16_31     : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } spi_config;
+
+    /* 0x4 : spi_int_sts */
+    union {
+        struct
+        {
+            uint32_t spi_end_int     : 1; /* [    0],          r,        0x0 */
+            uint32_t spi_txf_int     : 1; /* [    1],          r,        0x0 */
+            uint32_t spi_rxf_int     : 1; /* [    2],          r,        0x0 */
+            uint32_t spi_sto_int     : 1; /* [    3],          r,        0x0 */
+            uint32_t spi_txu_int     : 1; /* [    4],          r,        0x0 */
+            uint32_t spi_fer_int     : 1; /* [    5],          r,        0x0 */
+            uint32_t reserved_6_7    : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t cr_spi_end_mask : 1; /* [    8],        r/w,        0x1 */
+            uint32_t cr_spi_txf_mask : 1; /* [    9],        r/w,        0x1 */
+            uint32_t cr_spi_rxf_mask : 1; /* [   10],        r/w,        0x1 */
+            uint32_t cr_spi_sto_mask : 1; /* [   11],        r/w,        0x1 */
+            uint32_t cr_spi_txu_mask : 1; /* [   12],        r/w,        0x1 */
+            uint32_t cr_spi_fer_mask : 1; /* [   13],        r/w,        0x1 */
+            uint32_t reserved_14_15  : 2; /* [15:14],       rsvd,        0x0 */
+            uint32_t cr_spi_end_clr  : 1; /* [   16],        w1c,        0x0 */
+            uint32_t rsvd_17         : 1; /* [   17],       rsvd,        0x0 */
+            uint32_t rsvd_18         : 1; /* [   18],       rsvd,        0x0 */
+            uint32_t cr_spi_sto_clr  : 1; /* [   19],        w1c,        0x0 */
+            uint32_t cr_spi_txu_clr  : 1; /* [   20],        w1c,        0x0 */
+            uint32_t rsvd_21         : 1; /* [   21],       rsvd,        0x0 */
+            uint32_t reserved_22_23  : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t cr_spi_end_en   : 1; /* [   24],        r/w,        0x1 */
+            uint32_t cr_spi_txf_en   : 1; /* [   25],        r/w,        0x1 */
+            uint32_t cr_spi_rxf_en   : 1; /* [   26],        r/w,        0x1 */
+            uint32_t cr_spi_sto_en   : 1; /* [   27],        r/w,        0x1 */
+            uint32_t cr_spi_txu_en   : 1; /* [   28],        r/w,        0x1 */
+            uint32_t cr_spi_fer_en   : 1; /* [   29],        r/w,        0x1 */
+            uint32_t reserved_30_31  : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } spi_int_sts;
+
+    /* 0x8 : spi_bus_busy */
+    union {
+        struct
+        {
+            uint32_t sts_spi_bus_busy : 1;  /* [    0],          r,        0x0 */
+            uint32_t reserved_1_31    : 31; /* [31: 1],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } spi_bus_busy;
+
+    /* 0xc  reserved */
+    uint8_t RESERVED0xc[4];
+
+    /* 0x10 : spi_prd_0 */
+    union {
+        struct
+        {
+            uint32_t cr_spi_prd_s      : 8; /* [ 7: 0],        r/w,        0xf */
+            uint32_t cr_spi_prd_p      : 8; /* [15: 8],        r/w,        0xf */
+            uint32_t cr_spi_prd_d_ph_0 : 8; /* [23:16],        r/w,        0xf */
+            uint32_t cr_spi_prd_d_ph_1 : 8; /* [31:24],        r/w,        0xf */
+        } BF;
+        uint32_t WORD;
+    } spi_prd_0;
+
+    /* 0x14 : spi_prd_1 */
+    union {
+        struct
+        {
+            uint32_t cr_spi_prd_i  : 8;  /* [ 7: 0],        r/w,        0xf */
+            uint32_t reserved_8_31 : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } spi_prd_1;
+
+    /* 0x18 : spi_rxd_ignr */
+    union {
+        struct
+        {
+            uint32_t cr_spi_rxd_ignr_p : 5;  /* [ 4: 0],        r/w,        0x0 */
+            uint32_t reserved_5_15     : 11; /* [15: 5],       rsvd,        0x0 */
+            uint32_t cr_spi_rxd_ignr_s : 5;  /* [20:16],        r/w,        0x0 */
+            uint32_t reserved_21_31    : 11; /* [31:21],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } spi_rxd_ignr;
+
+    /* 0x1C : spi_sto_value */
+    union {
+        struct
+        {
+            uint32_t cr_spi_sto_value : 12; /* [11: 0],        r/w,      0xfff */
+            uint32_t reserved_12_31   : 20; /* [31:12],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } spi_sto_value;
+
+    /* 0x20  reserved */
+    uint8_t RESERVED0x20[96];
+
+    /* 0x80 : spi_fifo_config_0 */
+    union {
+        struct
+        {
+            uint32_t spi_dma_tx_en     : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t spi_dma_rx_en     : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t tx_fifo_clr       : 1;  /* [    2],        w1c,        0x0 */
+            uint32_t rx_fifo_clr       : 1;  /* [    3],        w1c,        0x0 */
+            uint32_t tx_fifo_overflow  : 1;  /* [    4],          r,        0x0 */
+            uint32_t tx_fifo_underflow : 1;  /* [    5],          r,        0x0 */
+            uint32_t rx_fifo_overflow  : 1;  /* [    6],          r,        0x0 */
+            uint32_t rx_fifo_underflow : 1;  /* [    7],          r,        0x0 */
+            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } spi_fifo_config_0;
+
+    /* 0x84 : spi_fifo_config_1 */
+    union {
+        struct
+        {
+            uint32_t tx_fifo_cnt    : 3; /* [ 2: 0],          r,        0x4 */
+            uint32_t reserved_3_7   : 5; /* [ 7: 3],       rsvd,        0x0 */
+            uint32_t rx_fifo_cnt    : 3; /* [10: 8],          r,        0x0 */
+            uint32_t reserved_11_15 : 5; /* [15:11],       rsvd,        0x0 */
+            uint32_t tx_fifo_th     : 2; /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_23 : 6; /* [23:18],       rsvd,        0x0 */
+            uint32_t rx_fifo_th     : 2; /* [25:24],        r/w,        0x0 */
+            uint32_t reserved_26_31 : 6; /* [31:26],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } spi_fifo_config_1;
+
+    /* 0x88 : spi_fifo_wdata */
+    union {
+        struct
+        {
+            uint32_t spi_fifo_wdata : 32; /* [31: 0],          w,          x */
+        } BF;
+        uint32_t WORD;
+    } spi_fifo_wdata;
+
+    /* 0x8C : spi_fifo_rdata */
+    union {
+        struct
+        {
+            uint32_t spi_fifo_rdata : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } spi_fifo_rdata;
+};
+
+typedef volatile struct spi_reg spi_reg_t;
+
+#endif /* __SPI_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/timer_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/timer_reg.h
new file mode 100644
index 00000000..49870bba
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/timer_reg.h
@@ -0,0 +1,852 @@
+/**
+  ******************************************************************************
+  * @file    timer_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __TIMER_REG_H__
+#define __TIMER_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : TCCR */
+#define TIMER_TCCR_OFFSET (0x0)
+#define TIMER_CS_1        TIMER_CS_1
+#define TIMER_CS_1_POS    (2U)
+#define TIMER_CS_1_LEN    (2U)
+#define TIMER_CS_1_MSK    (((1U << TIMER_CS_1_LEN) - 1) << TIMER_CS_1_POS)
+#define TIMER_CS_1_UMSK   (~(((1U << TIMER_CS_1_LEN) - 1) << TIMER_CS_1_POS))
+#define TIMER_CS_2        TIMER_CS_2
+#define TIMER_CS_2_POS    (5U)
+#define TIMER_CS_2_LEN    (2U)
+#define TIMER_CS_2_MSK    (((1U << TIMER_CS_2_LEN) - 1) << TIMER_CS_2_POS)
+#define TIMER_CS_2_UMSK   (~(((1U << TIMER_CS_2_LEN) - 1) << TIMER_CS_2_POS))
+#define TIMER_CS_WDT      TIMER_CS_WDT
+#define TIMER_CS_WDT_POS  (8U)
+#define TIMER_CS_WDT_LEN  (2U)
+#define TIMER_CS_WDT_MSK  (((1U << TIMER_CS_WDT_LEN) - 1) << TIMER_CS_WDT_POS)
+#define TIMER_CS_WDT_UMSK (~(((1U << TIMER_CS_WDT_LEN) - 1) << TIMER_CS_WDT_POS))
+
+/* 0x10 : TMR2_0 */
+#define TIMER_TMR2_0_OFFSET (0x10)
+#define TIMER_TMR           TIMER_TMR
+#define TIMER_TMR_POS       (0U)
+#define TIMER_TMR_LEN       (32U)
+#define TIMER_TMR_MSK       (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
+#define TIMER_TMR_UMSK      (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))
+
+/* 0x14 : TMR2_1 */
+#define TIMER_TMR2_1_OFFSET (0x14)
+#define TIMER_TMR           TIMER_TMR
+#define TIMER_TMR_POS       (0U)
+#define TIMER_TMR_LEN       (32U)
+#define TIMER_TMR_MSK       (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
+#define TIMER_TMR_UMSK      (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))
+
+/* 0x18 : TMR2_2 */
+#define TIMER_TMR2_2_OFFSET (0x18)
+#define TIMER_TMR           TIMER_TMR
+#define TIMER_TMR_POS       (0U)
+#define TIMER_TMR_LEN       (32U)
+#define TIMER_TMR_MSK       (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
+#define TIMER_TMR_UMSK      (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))
+
+/* 0x1C : TMR3_0 */
+#define TIMER_TMR3_0_OFFSET (0x1C)
+#define TIMER_TMR           TIMER_TMR
+#define TIMER_TMR_POS       (0U)
+#define TIMER_TMR_LEN       (32U)
+#define TIMER_TMR_MSK       (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
+#define TIMER_TMR_UMSK      (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))
+
+/* 0x20 : TMR3_1 */
+#define TIMER_TMR3_1_OFFSET (0x20)
+#define TIMER_TMR           TIMER_TMR
+#define TIMER_TMR_POS       (0U)
+#define TIMER_TMR_LEN       (32U)
+#define TIMER_TMR_MSK       (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
+#define TIMER_TMR_UMSK      (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))
+
+/* 0x24 : TMR3_2 */
+#define TIMER_TMR3_2_OFFSET (0x24)
+#define TIMER_TMR           TIMER_TMR
+#define TIMER_TMR_POS       (0U)
+#define TIMER_TMR_LEN       (32U)
+#define TIMER_TMR_MSK       (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
+#define TIMER_TMR_UMSK      (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))
+
+/* 0x2C : TCR2 */
+#define TIMER_TCR2_OFFSET (0x2C)
+#define TIMER_TCR         TIMER_TCR
+#define TIMER_TCR_POS     (0U)
+#define TIMER_TCR_LEN     (32U)
+#define TIMER_TCR_MSK     (((1U << TIMER_TCR_LEN) - 1) << TIMER_TCR_POS)
+#define TIMER_TCR_UMSK    (~(((1U << TIMER_TCR_LEN) - 1) << TIMER_TCR_POS))
+
+/* 0x30 : TCR3 */
+#define TIMER_TCR3_OFFSET (0x30)
+#define TIMER_TCR         TIMER_TCR
+#define TIMER_TCR_POS     (0U)
+#define TIMER_TCR_LEN     (32U)
+#define TIMER_TCR_MSK     (((1U << TIMER_TCR_LEN) - 1) << TIMER_TCR_POS)
+#define TIMER_TCR_UMSK    (~(((1U << TIMER_TCR_LEN) - 1) << TIMER_TCR_POS))
+
+/* 0x38 : TMSR2 */
+#define TIMER_TMSR2_OFFSET (0x38)
+#define TIMER_TMSR_0       TIMER_TMSR_0
+#define TIMER_TMSR_0_POS   (0U)
+#define TIMER_TMSR_0_LEN   (1U)
+#define TIMER_TMSR_0_MSK   (((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS)
+#define TIMER_TMSR_0_UMSK  (~(((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS))
+#define TIMER_TMSR_1       TIMER_TMSR_1
+#define TIMER_TMSR_1_POS   (1U)
+#define TIMER_TMSR_1_LEN   (1U)
+#define TIMER_TMSR_1_MSK   (((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS)
+#define TIMER_TMSR_1_UMSK  (~(((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS))
+#define TIMER_TMSR_2       TIMER_TMSR_2
+#define TIMER_TMSR_2_POS   (2U)
+#define TIMER_TMSR_2_LEN   (1U)
+#define TIMER_TMSR_2_MSK   (((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS)
+#define TIMER_TMSR_2_UMSK  (~(((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS))
+
+/* 0x3C : TMSR3 */
+#define TIMER_TMSR3_OFFSET (0x3C)
+#define TIMER_TMSR_0       TIMER_TMSR_0
+#define TIMER_TMSR_0_POS   (0U)
+#define TIMER_TMSR_0_LEN   (1U)
+#define TIMER_TMSR_0_MSK   (((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS)
+#define TIMER_TMSR_0_UMSK  (~(((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS))
+#define TIMER_TMSR_1       TIMER_TMSR_1
+#define TIMER_TMSR_1_POS   (1U)
+#define TIMER_TMSR_1_LEN   (1U)
+#define TIMER_TMSR_1_MSK   (((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS)
+#define TIMER_TMSR_1_UMSK  (~(((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS))
+#define TIMER_TMSR_2       TIMER_TMSR_2
+#define TIMER_TMSR_2_POS   (2U)
+#define TIMER_TMSR_2_LEN   (1U)
+#define TIMER_TMSR_2_MSK   (((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS)
+#define TIMER_TMSR_2_UMSK  (~(((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS))
+
+/* 0x44 : TIER2 */
+#define TIMER_TIER2_OFFSET (0x44)
+#define TIMER_TIER_0       TIMER_TIER_0
+#define TIMER_TIER_0_POS   (0U)
+#define TIMER_TIER_0_LEN   (1U)
+#define TIMER_TIER_0_MSK   (((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS)
+#define TIMER_TIER_0_UMSK  (~(((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS))
+#define TIMER_TIER_1       TIMER_TIER_1
+#define TIMER_TIER_1_POS   (1U)
+#define TIMER_TIER_1_LEN   (1U)
+#define TIMER_TIER_1_MSK   (((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS)
+#define TIMER_TIER_1_UMSK  (~(((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS))
+#define TIMER_TIER_2       TIMER_TIER_2
+#define TIMER_TIER_2_POS   (2U)
+#define TIMER_TIER_2_LEN   (1U)
+#define TIMER_TIER_2_MSK   (((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS)
+#define TIMER_TIER_2_UMSK  (~(((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS))
+
+/* 0x48 : TIER3 */
+#define TIMER_TIER3_OFFSET (0x48)
+#define TIMER_TIER_0       TIMER_TIER_0
+#define TIMER_TIER_0_POS   (0U)
+#define TIMER_TIER_0_LEN   (1U)
+#define TIMER_TIER_0_MSK   (((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS)
+#define TIMER_TIER_0_UMSK  (~(((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS))
+#define TIMER_TIER_1       TIMER_TIER_1
+#define TIMER_TIER_1_POS   (1U)
+#define TIMER_TIER_1_LEN   (1U)
+#define TIMER_TIER_1_MSK   (((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS)
+#define TIMER_TIER_1_UMSK  (~(((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS))
+#define TIMER_TIER_2       TIMER_TIER_2
+#define TIMER_TIER_2_POS   (2U)
+#define TIMER_TIER_2_LEN   (1U)
+#define TIMER_TIER_2_MSK   (((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS)
+#define TIMER_TIER_2_UMSK  (~(((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS))
+
+/* 0x50 : TPLVR2 */
+#define TIMER_TPLVR2_OFFSET (0x50)
+#define TIMER_TPLVR         TIMER_TPLVR
+#define TIMER_TPLVR_POS     (0U)
+#define TIMER_TPLVR_LEN     (32U)
+#define TIMER_TPLVR_MSK     (((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS)
+#define TIMER_TPLVR_UMSK    (~(((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS))
+
+/* 0x54 : TPLVR3 */
+#define TIMER_TPLVR3_OFFSET (0x54)
+#define TIMER_TPLVR         TIMER_TPLVR
+#define TIMER_TPLVR_POS     (0U)
+#define TIMER_TPLVR_LEN     (32U)
+#define TIMER_TPLVR_MSK     (((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS)
+#define TIMER_TPLVR_UMSK    (~(((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS))
+
+/* 0x5C : TPLCR2 */
+#define TIMER_TPLCR2_OFFSET (0x5C)
+#define TIMER_TPLCR         TIMER_TPLCR
+#define TIMER_TPLCR_POS     (0U)
+#define TIMER_TPLCR_LEN     (2U)
+#define TIMER_TPLCR_MSK     (((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS)
+#define TIMER_TPLCR_UMSK    (~(((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS))
+
+/* 0x60 : TPLCR3 */
+#define TIMER_TPLCR3_OFFSET (0x60)
+#define TIMER_TPLCR         TIMER_TPLCR
+#define TIMER_TPLCR_POS     (0U)
+#define TIMER_TPLCR_LEN     (2U)
+#define TIMER_TPLCR_MSK     (((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS)
+#define TIMER_TPLCR_UMSK    (~(((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS))
+
+/* 0x64 : WMER */
+#define TIMER_WMER_OFFSET (0x64)
+#define TIMER_WE          TIMER_WE
+#define TIMER_WE_POS      (0U)
+#define TIMER_WE_LEN      (1U)
+#define TIMER_WE_MSK      (((1U << TIMER_WE_LEN) - 1) << TIMER_WE_POS)
+#define TIMER_WE_UMSK     (~(((1U << TIMER_WE_LEN) - 1) << TIMER_WE_POS))
+#define TIMER_WRIE        TIMER_WRIE
+#define TIMER_WRIE_POS    (1U)
+#define TIMER_WRIE_LEN    (1U)
+#define TIMER_WRIE_MSK    (((1U << TIMER_WRIE_LEN) - 1) << TIMER_WRIE_POS)
+#define TIMER_WRIE_UMSK   (~(((1U << TIMER_WRIE_LEN) - 1) << TIMER_WRIE_POS))
+
+/* 0x68 : WMR */
+#define TIMER_WMR_OFFSET (0x68)
+#define TIMER_WMR        TIMER_WMR
+#define TIMER_WMR_POS    (0U)
+#define TIMER_WMR_LEN    (16U)
+#define TIMER_WMR_MSK    (((1U << TIMER_WMR_LEN) - 1) << TIMER_WMR_POS)
+#define TIMER_WMR_UMSK   (~(((1U << TIMER_WMR_LEN) - 1) << TIMER_WMR_POS))
+
+/* 0x6C : WVR */
+#define TIMER_WVR_OFFSET (0x6C)
+#define TIMER_WVR        TIMER_WVR
+#define TIMER_WVR_POS    (0U)
+#define TIMER_WVR_LEN    (16U)
+#define TIMER_WVR_MSK    (((1U << TIMER_WVR_LEN) - 1) << TIMER_WVR_POS)
+#define TIMER_WVR_UMSK   (~(((1U << TIMER_WVR_LEN) - 1) << TIMER_WVR_POS))
+
+/* 0x70 : WSR */
+#define TIMER_WSR_OFFSET (0x70)
+#define TIMER_WTS        TIMER_WTS
+#define TIMER_WTS_POS    (0U)
+#define TIMER_WTS_LEN    (1U)
+#define TIMER_WTS_MSK    (((1U << TIMER_WTS_LEN) - 1) << TIMER_WTS_POS)
+#define TIMER_WTS_UMSK   (~(((1U << TIMER_WTS_LEN) - 1) << TIMER_WTS_POS))
+
+/* 0x78 : TICR2 */
+#define TIMER_TICR2_OFFSET (0x78)
+#define TIMER_TCLR_0       TIMER_TCLR_0
+#define TIMER_TCLR_0_POS   (0U)
+#define TIMER_TCLR_0_LEN   (1U)
+#define TIMER_TCLR_0_MSK   (((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS)
+#define TIMER_TCLR_0_UMSK  (~(((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS))
+#define TIMER_TCLR_1       TIMER_TCLR_1
+#define TIMER_TCLR_1_POS   (1U)
+#define TIMER_TCLR_1_LEN   (1U)
+#define TIMER_TCLR_1_MSK   (((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS)
+#define TIMER_TCLR_1_UMSK  (~(((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS))
+#define TIMER_TCLR_2       TIMER_TCLR_2
+#define TIMER_TCLR_2_POS   (2U)
+#define TIMER_TCLR_2_LEN   (1U)
+#define TIMER_TCLR_2_MSK   (((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS)
+#define TIMER_TCLR_2_UMSK  (~(((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS))
+
+/* 0x7C : TICR3 */
+#define TIMER_TICR3_OFFSET (0x7C)
+#define TIMER_TCLR_0       TIMER_TCLR_0
+#define TIMER_TCLR_0_POS   (0U)
+#define TIMER_TCLR_0_LEN   (1U)
+#define TIMER_TCLR_0_MSK   (((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS)
+#define TIMER_TCLR_0_UMSK  (~(((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS))
+#define TIMER_TCLR_1       TIMER_TCLR_1
+#define TIMER_TCLR_1_POS   (1U)
+#define TIMER_TCLR_1_LEN   (1U)
+#define TIMER_TCLR_1_MSK   (((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS)
+#define TIMER_TCLR_1_UMSK  (~(((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS))
+#define TIMER_TCLR_2       TIMER_TCLR_2
+#define TIMER_TCLR_2_POS   (2U)
+#define TIMER_TCLR_2_LEN   (1U)
+#define TIMER_TCLR_2_MSK   (((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS)
+#define TIMER_TCLR_2_UMSK  (~(((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS))
+
+/* 0x80 : WICR */
+#define TIMER_WICR_OFFSET (0x80)
+#define TIMER_WICLR       TIMER_WICLR
+#define TIMER_WICLR_POS   (0U)
+#define TIMER_WICLR_LEN   (1U)
+#define TIMER_WICLR_MSK   (((1U << TIMER_WICLR_LEN) - 1) << TIMER_WICLR_POS)
+#define TIMER_WICLR_UMSK  (~(((1U << TIMER_WICLR_LEN) - 1) << TIMER_WICLR_POS))
+
+/* 0x84 : TCER */
+#define TIMER_TCER_OFFSET (0x84)
+#define TIMER2_EN         TIMER2_EN
+#define TIMER2_EN_POS     (1U)
+#define TIMER2_EN_LEN     (1U)
+#define TIMER2_EN_MSK     (((1U << TIMER2_EN_LEN) - 1) << TIMER2_EN_POS)
+#define TIMER2_EN_UMSK    (~(((1U << TIMER2_EN_LEN) - 1) << TIMER2_EN_POS))
+#define TIMER3_EN         TIMER3_EN
+#define TIMER3_EN_POS     (2U)
+#define TIMER3_EN_LEN     (1U)
+#define TIMER3_EN_MSK     (((1U << TIMER3_EN_LEN) - 1) << TIMER3_EN_POS)
+#define TIMER3_EN_UMSK    (~(((1U << TIMER3_EN_LEN) - 1) << TIMER3_EN_POS))
+
+/* 0x88 : TCMR */
+#define TIMER_TCMR_OFFSET (0x88)
+#define TIMER2_MODE       TIMER2_MODE
+#define TIMER2_MODE_POS   (1U)
+#define TIMER2_MODE_LEN   (1U)
+#define TIMER2_MODE_MSK   (((1U << TIMER2_MODE_LEN) - 1) << TIMER2_MODE_POS)
+#define TIMER2_MODE_UMSK  (~(((1U << TIMER2_MODE_LEN) - 1) << TIMER2_MODE_POS))
+#define TIMER3_MODE       TIMER3_MODE
+#define TIMER3_MODE_POS   (2U)
+#define TIMER3_MODE_LEN   (1U)
+#define TIMER3_MODE_MSK   (((1U << TIMER3_MODE_LEN) - 1) << TIMER3_MODE_POS)
+#define TIMER3_MODE_UMSK  (~(((1U << TIMER3_MODE_LEN) - 1) << TIMER3_MODE_POS))
+
+/* 0x90 : TILR2 */
+#define TIMER_TILR2_OFFSET (0x90)
+#define TIMER_TILR_0       TIMER_TILR_0
+#define TIMER_TILR_0_POS   (0U)
+#define TIMER_TILR_0_LEN   (1U)
+#define TIMER_TILR_0_MSK   (((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS)
+#define TIMER_TILR_0_UMSK  (~(((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS))
+#define TIMER_TILR_1       TIMER_TILR_1
+#define TIMER_TILR_1_POS   (1U)
+#define TIMER_TILR_1_LEN   (1U)
+#define TIMER_TILR_1_MSK   (((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS)
+#define TIMER_TILR_1_UMSK  (~(((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS))
+#define TIMER_TILR_2       TIMER_TILR_2
+#define TIMER_TILR_2_POS   (2U)
+#define TIMER_TILR_2_LEN   (1U)
+#define TIMER_TILR_2_MSK   (((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS)
+#define TIMER_TILR_2_UMSK  (~(((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS))
+
+/* 0x94 : TILR3 */
+#define TIMER_TILR3_OFFSET (0x94)
+#define TIMER_TILR_0       TIMER_TILR_0
+#define TIMER_TILR_0_POS   (0U)
+#define TIMER_TILR_0_LEN   (1U)
+#define TIMER_TILR_0_MSK   (((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS)
+#define TIMER_TILR_0_UMSK  (~(((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS))
+#define TIMER_TILR_1       TIMER_TILR_1
+#define TIMER_TILR_1_POS   (1U)
+#define TIMER_TILR_1_LEN   (1U)
+#define TIMER_TILR_1_MSK   (((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS)
+#define TIMER_TILR_1_UMSK  (~(((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS))
+#define TIMER_TILR_2       TIMER_TILR_2
+#define TIMER_TILR_2_POS   (2U)
+#define TIMER_TILR_2_LEN   (1U)
+#define TIMER_TILR_2_MSK   (((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS)
+#define TIMER_TILR_2_UMSK  (~(((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS))
+
+/* 0x98 : WCR */
+#define TIMER_WCR_OFFSET (0x98)
+#define TIMER_WCR        TIMER_WCR
+#define TIMER_WCR_POS    (0U)
+#define TIMER_WCR_LEN    (1U)
+#define TIMER_WCR_MSK    (((1U << TIMER_WCR_LEN) - 1) << TIMER_WCR_POS)
+#define TIMER_WCR_UMSK   (~(((1U << TIMER_WCR_LEN) - 1) << TIMER_WCR_POS))
+
+/* 0x9C : WFAR */
+#define TIMER_WFAR_OFFSET (0x9C)
+#define TIMER_WFAR        TIMER_WFAR
+#define TIMER_WFAR_POS    (0U)
+#define TIMER_WFAR_LEN    (16U)
+#define TIMER_WFAR_MSK    (((1U << TIMER_WFAR_LEN) - 1) << TIMER_WFAR_POS)
+#define TIMER_WFAR_UMSK   (~(((1U << TIMER_WFAR_LEN) - 1) << TIMER_WFAR_POS))
+
+/* 0xA0 : WSAR */
+#define TIMER_WSAR_OFFSET (0xA0)
+#define TIMER_WSAR        TIMER_WSAR
+#define TIMER_WSAR_POS    (0U)
+#define TIMER_WSAR_LEN    (16U)
+#define TIMER_WSAR_MSK    (((1U << TIMER_WSAR_LEN) - 1) << TIMER_WSAR_POS)
+#define TIMER_WSAR_UMSK   (~(((1U << TIMER_WSAR_LEN) - 1) << TIMER_WSAR_POS))
+
+/* 0xA8 : TCVWR2 */
+#define TIMER_TCVWR2_OFFSET (0xA8)
+#define TIMER_TCVWR         TIMER_TCVWR
+#define TIMER_TCVWR_POS     (0U)
+#define TIMER_TCVWR_LEN     (32U)
+#define TIMER_TCVWR_MSK     (((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS)
+#define TIMER_TCVWR_UMSK    (~(((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS))
+
+/* 0xAC : TCVWR3 */
+#define TIMER_TCVWR3_OFFSET (0xAC)
+#define TIMER_TCVWR         TIMER_TCVWR
+#define TIMER_TCVWR_POS     (0U)
+#define TIMER_TCVWR_LEN     (32U)
+#define TIMER_TCVWR_MSK     (((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS)
+#define TIMER_TCVWR_UMSK    (~(((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS))
+
+/* 0xB4 : TCVSYN2 */
+#define TIMER_TCVSYN2_OFFSET (0xB4)
+#define TIMER_TCVSYN2        TIMER_TCVSYN2
+#define TIMER_TCVSYN2_POS    (0U)
+#define TIMER_TCVSYN2_LEN    (32U)
+#define TIMER_TCVSYN2_MSK    (((1U << TIMER_TCVSYN2_LEN) - 1) << TIMER_TCVSYN2_POS)
+#define TIMER_TCVSYN2_UMSK   (~(((1U << TIMER_TCVSYN2_LEN) - 1) << TIMER_TCVSYN2_POS))
+
+/* 0xB8 : TCVSYN3 */
+#define TIMER_TCVSYN3_OFFSET (0xB8)
+#define TIMER_TCVSYN3        TIMER_TCVSYN3
+#define TIMER_TCVSYN3_POS    (0U)
+#define TIMER_TCVSYN3_LEN    (32U)
+#define TIMER_TCVSYN3_MSK    (((1U << TIMER_TCVSYN3_LEN) - 1) << TIMER_TCVSYN3_POS)
+#define TIMER_TCVSYN3_UMSK   (~(((1U << TIMER_TCVSYN3_LEN) - 1) << TIMER_TCVSYN3_POS))
+
+/* 0xBC : TCDR */
+#define TIMER_TCDR_OFFSET (0xBC)
+#define TIMER_TCDR2       TIMER_TCDR2
+#define TIMER_TCDR2_POS   (8U)
+#define TIMER_TCDR2_LEN   (8U)
+#define TIMER_TCDR2_MSK   (((1U << TIMER_TCDR2_LEN) - 1) << TIMER_TCDR2_POS)
+#define TIMER_TCDR2_UMSK  (~(((1U << TIMER_TCDR2_LEN) - 1) << TIMER_TCDR2_POS))
+#define TIMER_TCDR3       TIMER_TCDR3
+#define TIMER_TCDR3_POS   (16U)
+#define TIMER_TCDR3_LEN   (8U)
+#define TIMER_TCDR3_MSK   (((1U << TIMER_TCDR3_LEN) - 1) << TIMER_TCDR3_POS)
+#define TIMER_TCDR3_UMSK  (~(((1U << TIMER_TCDR3_LEN) - 1) << TIMER_TCDR3_POS))
+#define TIMER_WCDR        TIMER_WCDR
+#define TIMER_WCDR_POS    (24U)
+#define TIMER_WCDR_LEN    (8U)
+#define TIMER_WCDR_MSK    (((1U << TIMER_WCDR_LEN) - 1) << TIMER_WCDR_POS)
+#define TIMER_WCDR_UMSK   (~(((1U << TIMER_WCDR_LEN) - 1) << TIMER_WCDR_POS))
+
+struct timer_reg {
+    /* 0x0 : TCCR */
+    union {
+        struct
+        {
+            uint32_t reserved_0_1   : 2;  /* [ 1: 0],       rsvd,        0x0 */
+            uint32_t cs_1           : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t RESERVED_4     : 1;  /* [    4],       rsvd,        0x0 */
+            uint32_t cs_2           : 2;  /* [ 6: 5],        r/w,        0x0 */
+            uint32_t RESERVED_7     : 1;  /* [    7],       rsvd,        0x0 */
+            uint32_t cs_wdt         : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_31 : 22; /* [31:10],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TCCR;
+
+    /* 0x4  reserved */
+    uint8_t RESERVED0x4[12];
+
+    /* 0x10 : TMR2_0 */
+    union {
+        struct
+        {
+            uint32_t tmr : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } TMR2_0;
+
+    /* 0x14 : TMR2_1 */
+    union {
+        struct
+        {
+            uint32_t tmr : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } TMR2_1;
+
+    /* 0x18 : TMR2_2 */
+    union {
+        struct
+        {
+            uint32_t tmr : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } TMR2_2;
+
+    /* 0x1C : TMR3_0 */
+    union {
+        struct
+        {
+            uint32_t tmr : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } TMR3_0;
+
+    /* 0x20 : TMR3_1 */
+    union {
+        struct
+        {
+            uint32_t tmr : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } TMR3_1;
+
+    /* 0x24 : TMR3_2 */
+    union {
+        struct
+        {
+            uint32_t tmr : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } TMR3_2;
+
+    /* 0x28  reserved */
+    uint8_t RESERVED0x28[4];
+
+    /* 0x2C : TCR2 */
+    union {
+        struct
+        {
+            uint32_t tcr : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TCR2;
+
+    /* 0x30 : TCR3 */
+    union {
+        struct
+        {
+            uint32_t tcr : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TCR3;
+
+    /* 0x34  reserved */
+    uint8_t RESERVED0x34[4];
+
+    /* 0x38 : TMSR2 */
+    union {
+        struct
+        {
+            uint32_t tmsr_0        : 1;  /* [    0],          r,        0x0 */
+            uint32_t tmsr_1        : 1;  /* [    1],          r,        0x0 */
+            uint32_t tmsr_2        : 1;  /* [    2],          r,        0x0 */
+            uint32_t reserved_3_31 : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TMSR2;
+
+    /* 0x3C : TMSR3 */
+    union {
+        struct
+        {
+            uint32_t tmsr_0        : 1;  /* [    0],          r,        0x0 */
+            uint32_t tmsr_1        : 1;  /* [    1],          r,        0x0 */
+            uint32_t tmsr_2        : 1;  /* [    2],          r,        0x0 */
+            uint32_t reserved_3_31 : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TMSR3;
+
+    /* 0x40  reserved */
+    uint8_t RESERVED0x40[4];
+
+    /* 0x44 : TIER2 */
+    union {
+        struct
+        {
+            uint32_t tier_0        : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t tier_1        : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t tier_2        : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3_31 : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TIER2;
+
+    /* 0x48 : TIER3 */
+    union {
+        struct
+        {
+            uint32_t tier_0        : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t tier_1        : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t tier_2        : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3_31 : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TIER3;
+
+    /* 0x4c  reserved */
+    uint8_t RESERVED0x4c[4];
+
+    /* 0x50 : TPLVR2 */
+    union {
+        struct
+        {
+            uint32_t tplvr : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TPLVR2;
+
+    /* 0x54 : TPLVR3 */
+    union {
+        struct
+        {
+            uint32_t tplvr : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TPLVR3;
+
+    /* 0x58  reserved */
+    uint8_t RESERVED0x58[4];
+
+    /* 0x5C : TPLCR2 */
+    union {
+        struct
+        {
+            uint32_t tplcr         : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_31 : 30; /* [31: 2],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TPLCR2;
+
+    /* 0x60 : TPLCR3 */
+    union {
+        struct
+        {
+            uint32_t tplcr         : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_31 : 30; /* [31: 2],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TPLCR3;
+
+    /* 0x64 : WMER */
+    union {
+        struct
+        {
+            uint32_t we            : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t wrie          : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_31 : 30; /* [31: 2],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } WMER;
+
+    /* 0x68 : WMR */
+    union {
+        struct
+        {
+            uint32_t wmr            : 16; /* [15: 0],        r/w,     0xffff */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } WMR;
+
+    /* 0x6C : WVR */
+    union {
+        struct
+        {
+            uint32_t wvr            : 16; /* [15: 0],          r,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } WVR;
+
+    /* 0x70 : WSR */
+    union {
+        struct
+        {
+            uint32_t wts           : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_31 : 31; /* [31: 1],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } WSR;
+
+    /* 0x74  reserved */
+    uint8_t RESERVED0x74[4];
+
+    /* 0x78 : TICR2 */
+    union {
+        struct
+        {
+            uint32_t tclr_0        : 1;  /* [    0],          w,        0x0 */
+            uint32_t tclr_1        : 1;  /* [    1],          w,        0x0 */
+            uint32_t tclr_2        : 1;  /* [    2],          w,        0x0 */
+            uint32_t reserved_3_31 : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TICR2;
+
+    /* 0x7C : TICR3 */
+    union {
+        struct
+        {
+            uint32_t tclr_0        : 1;  /* [    0],          w,        0x0 */
+            uint32_t tclr_1        : 1;  /* [    1],          w,        0x0 */
+            uint32_t tclr_2        : 1;  /* [    2],          w,        0x0 */
+            uint32_t reserved_3_31 : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TICR3;
+
+    /* 0x80 : WICR */
+    union {
+        struct
+        {
+            uint32_t wiclr         : 1;  /* [    0],          w,        0x0 */
+            uint32_t reserved_1_31 : 31; /* [31: 1],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } WICR;
+
+    /* 0x84 : TCER */
+    union {
+        struct
+        {
+            uint32_t reserved_0    : 1;  /* [    0],       rsvd,        0x0 */
+            uint32_t timer2_en     : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t timer3_en     : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3_31 : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TCER;
+
+    /* 0x88 : TCMR */
+    union {
+        struct
+        {
+            uint32_t reserved_0    : 1;  /* [    0],       rsvd,        0x0 */
+            uint32_t timer2_mode   : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t timer3_mode   : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3_31 : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TCMR;
+
+    /* 0x8c  reserved */
+    uint8_t RESERVED0x8c[4];
+
+    /* 0x90 : TILR2 */
+    union {
+        struct
+        {
+            uint32_t tilr_0        : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t tilr_1        : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t tilr_2        : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3_31 : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TILR2;
+
+    /* 0x94 : TILR3 */
+    union {
+        struct
+        {
+            uint32_t tilr_0        : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t tilr_1        : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t tilr_2        : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3_31 : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TILR3;
+
+    /* 0x98 : WCR */
+    union {
+        struct
+        {
+            uint32_t wcr           : 1;  /* [    0],          w,        0x0 */
+            uint32_t reserved_1_31 : 31; /* [31: 1],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } WCR;
+
+    /* 0x9C : WFAR */
+    union {
+        struct
+        {
+            uint32_t wfar           : 16; /* [15: 0],          w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } WFAR;
+
+    /* 0xA0 : WSAR */
+    union {
+        struct
+        {
+            uint32_t wsar           : 16; /* [15: 0],          w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } WSAR;
+
+    /* 0xa4  reserved */
+    uint8_t RESERVED0xa4[4];
+
+    /* 0xA8 : TCVWR2 */
+    union {
+        struct
+        {
+            uint32_t tcvwr : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TCVWR2;
+
+    /* 0xAC : TCVWR3 */
+    union {
+        struct
+        {
+            uint32_t tcvwr : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TCVWR3;
+
+    /* 0xb0  reserved */
+    uint8_t RESERVED0xb0[4];
+
+    /* 0xB4 : TCVSYN2 */
+    union {
+        struct
+        {
+            uint32_t tcvsyn2 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TCVSYN2;
+
+    /* 0xB8 : TCVSYN3 */
+    union {
+        struct
+        {
+            uint32_t tcvsyn3 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TCVSYN3;
+
+    /* 0xBC : TCDR */
+    union {
+        struct
+        {
+            uint32_t reserved_0_7 : 8; /* [ 7: 0],       rsvd,        0x0 */
+            uint32_t tcdr2        : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t tcdr3        : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t wcdr         : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TCDR;
+};
+
+typedef volatile struct timer_reg timer_reg_t;
+
+#endif /* __TIMER_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/tzc_sec_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/tzc_sec_reg.h
new file mode 100644
index 00000000..e436b8c4
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/tzc_sec_reg.h
@@ -0,0 +1,256 @@
+/**
+  ******************************************************************************
+  * @file    tzc_sec_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __TZC_SEC_REG_H__
+#define __TZC_SEC_REG_H__
+
+#include "bl702.h"
+
+/* 0x40 : tzc_rom_ctrl */
+#define TZC_SEC_TZC_ROM_CTRL_OFFSET     (0x40)
+#define TZC_SEC_TZC_ROM0_R0_ID0_EN      TZC_SEC_TZC_ROM0_R0_ID0_EN
+#define TZC_SEC_TZC_ROM0_R0_ID0_EN_POS  (0U)
+#define TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN  (1U)
+#define TZC_SEC_TZC_ROM0_R0_ID0_EN_MSK  (((1U << TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID0_EN_POS)
+#define TZC_SEC_TZC_ROM0_R0_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID0_EN_POS))
+#define TZC_SEC_TZC_ROM0_R1_ID0_EN      TZC_SEC_TZC_ROM0_R1_ID0_EN
+#define TZC_SEC_TZC_ROM0_R1_ID0_EN_POS  (1U)
+#define TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN  (1U)
+#define TZC_SEC_TZC_ROM0_R1_ID0_EN_MSK  (((1U << TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID0_EN_POS)
+#define TZC_SEC_TZC_ROM0_R1_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID0_EN_POS))
+#define TZC_SEC_TZC_ROM1_R0_ID0_EN      TZC_SEC_TZC_ROM1_R0_ID0_EN
+#define TZC_SEC_TZC_ROM1_R0_ID0_EN_POS  (2U)
+#define TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN  (1U)
+#define TZC_SEC_TZC_ROM1_R0_ID0_EN_MSK  (((1U << TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID0_EN_POS)
+#define TZC_SEC_TZC_ROM1_R0_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID0_EN_POS))
+#define TZC_SEC_TZC_ROM1_R1_ID0_EN      TZC_SEC_TZC_ROM1_R1_ID0_EN
+#define TZC_SEC_TZC_ROM1_R1_ID0_EN_POS  (3U)
+#define TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN  (1U)
+#define TZC_SEC_TZC_ROM1_R1_ID0_EN_MSK  (((1U << TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID0_EN_POS)
+#define TZC_SEC_TZC_ROM1_R1_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID0_EN_POS))
+#define TZC_SEC_TZC_ROM0_R0_ID1_EN      TZC_SEC_TZC_ROM0_R0_ID1_EN
+#define TZC_SEC_TZC_ROM0_R0_ID1_EN_POS  (8U)
+#define TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN  (1U)
+#define TZC_SEC_TZC_ROM0_R0_ID1_EN_MSK  (((1U << TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID1_EN_POS)
+#define TZC_SEC_TZC_ROM0_R0_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID1_EN_POS))
+#define TZC_SEC_TZC_ROM0_R1_ID1_EN      TZC_SEC_TZC_ROM0_R1_ID1_EN
+#define TZC_SEC_TZC_ROM0_R1_ID1_EN_POS  (9U)
+#define TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN  (1U)
+#define TZC_SEC_TZC_ROM0_R1_ID1_EN_MSK  (((1U << TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID1_EN_POS)
+#define TZC_SEC_TZC_ROM0_R1_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID1_EN_POS))
+#define TZC_SEC_TZC_ROM1_R0_ID1_EN      TZC_SEC_TZC_ROM1_R0_ID1_EN
+#define TZC_SEC_TZC_ROM1_R0_ID1_EN_POS  (10U)
+#define TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN  (1U)
+#define TZC_SEC_TZC_ROM1_R0_ID1_EN_MSK  (((1U << TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID1_EN_POS)
+#define TZC_SEC_TZC_ROM1_R0_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID1_EN_POS))
+#define TZC_SEC_TZC_ROM1_R1_ID1_EN      TZC_SEC_TZC_ROM1_R1_ID1_EN
+#define TZC_SEC_TZC_ROM1_R1_ID1_EN_POS  (11U)
+#define TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN  (1U)
+#define TZC_SEC_TZC_ROM1_R1_ID1_EN_MSK  (((1U << TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID1_EN_POS)
+#define TZC_SEC_TZC_ROM1_R1_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID1_EN_POS))
+#define TZC_SEC_TZC_ROM0_R0_EN          TZC_SEC_TZC_ROM0_R0_EN
+#define TZC_SEC_TZC_ROM0_R0_EN_POS      (16U)
+#define TZC_SEC_TZC_ROM0_R0_EN_LEN      (1U)
+#define TZC_SEC_TZC_ROM0_R0_EN_MSK      (((1U << TZC_SEC_TZC_ROM0_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_EN_POS)
+#define TZC_SEC_TZC_ROM0_R0_EN_UMSK     (~(((1U << TZC_SEC_TZC_ROM0_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_EN_POS))
+#define TZC_SEC_TZC_ROM0_R1_EN          TZC_SEC_TZC_ROM0_R1_EN
+#define TZC_SEC_TZC_ROM0_R1_EN_POS      (17U)
+#define TZC_SEC_TZC_ROM0_R1_EN_LEN      (1U)
+#define TZC_SEC_TZC_ROM0_R1_EN_MSK      (((1U << TZC_SEC_TZC_ROM0_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_EN_POS)
+#define TZC_SEC_TZC_ROM0_R1_EN_UMSK     (~(((1U << TZC_SEC_TZC_ROM0_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_EN_POS))
+#define TZC_SEC_TZC_ROM1_R0_EN          TZC_SEC_TZC_ROM1_R0_EN
+#define TZC_SEC_TZC_ROM1_R0_EN_POS      (18U)
+#define TZC_SEC_TZC_ROM1_R0_EN_LEN      (1U)
+#define TZC_SEC_TZC_ROM1_R0_EN_MSK      (((1U << TZC_SEC_TZC_ROM1_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_EN_POS)
+#define TZC_SEC_TZC_ROM1_R0_EN_UMSK     (~(((1U << TZC_SEC_TZC_ROM1_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_EN_POS))
+#define TZC_SEC_TZC_ROM1_R1_EN          TZC_SEC_TZC_ROM1_R1_EN
+#define TZC_SEC_TZC_ROM1_R1_EN_POS      (19U)
+#define TZC_SEC_TZC_ROM1_R1_EN_LEN      (1U)
+#define TZC_SEC_TZC_ROM1_R1_EN_MSK      (((1U << TZC_SEC_TZC_ROM1_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_EN_POS)
+#define TZC_SEC_TZC_ROM1_R1_EN_UMSK     (~(((1U << TZC_SEC_TZC_ROM1_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_EN_POS))
+#define TZC_SEC_TZC_ROM0_R0_LOCK        TZC_SEC_TZC_ROM0_R0_LOCK
+#define TZC_SEC_TZC_ROM0_R0_LOCK_POS    (24U)
+#define TZC_SEC_TZC_ROM0_R0_LOCK_LEN    (1U)
+#define TZC_SEC_TZC_ROM0_R0_LOCK_MSK    (((1U << TZC_SEC_TZC_ROM0_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_LOCK_POS)
+#define TZC_SEC_TZC_ROM0_R0_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_ROM0_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_LOCK_POS))
+#define TZC_SEC_TZC_ROM0_R1_LOCK        TZC_SEC_TZC_ROM0_R1_LOCK
+#define TZC_SEC_TZC_ROM0_R1_LOCK_POS    (25U)
+#define TZC_SEC_TZC_ROM0_R1_LOCK_LEN    (1U)
+#define TZC_SEC_TZC_ROM0_R1_LOCK_MSK    (((1U << TZC_SEC_TZC_ROM0_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_LOCK_POS)
+#define TZC_SEC_TZC_ROM0_R1_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_ROM0_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_LOCK_POS))
+#define TZC_SEC_TZC_ROM1_R0_LOCK        TZC_SEC_TZC_ROM1_R0_LOCK
+#define TZC_SEC_TZC_ROM1_R0_LOCK_POS    (26U)
+#define TZC_SEC_TZC_ROM1_R0_LOCK_LEN    (1U)
+#define TZC_SEC_TZC_ROM1_R0_LOCK_MSK    (((1U << TZC_SEC_TZC_ROM1_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_LOCK_POS)
+#define TZC_SEC_TZC_ROM1_R0_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_ROM1_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_LOCK_POS))
+#define TZC_SEC_TZC_ROM1_R1_LOCK        TZC_SEC_TZC_ROM1_R1_LOCK
+#define TZC_SEC_TZC_ROM1_R1_LOCK_POS    (27U)
+#define TZC_SEC_TZC_ROM1_R1_LOCK_LEN    (1U)
+#define TZC_SEC_TZC_ROM1_R1_LOCK_MSK    (((1U << TZC_SEC_TZC_ROM1_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_LOCK_POS)
+#define TZC_SEC_TZC_ROM1_R1_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_ROM1_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_LOCK_POS))
+#define TZC_SEC_TZC_SBOOT_DONE          TZC_SEC_TZC_SBOOT_DONE
+#define TZC_SEC_TZC_SBOOT_DONE_POS      (28U)
+#define TZC_SEC_TZC_SBOOT_DONE_LEN      (4U)
+#define TZC_SEC_TZC_SBOOT_DONE_MSK      (((1U << TZC_SEC_TZC_SBOOT_DONE_LEN) - 1) << TZC_SEC_TZC_SBOOT_DONE_POS)
+#define TZC_SEC_TZC_SBOOT_DONE_UMSK     (~(((1U << TZC_SEC_TZC_SBOOT_DONE_LEN) - 1) << TZC_SEC_TZC_SBOOT_DONE_POS))
+
+/* 0x44 : tzc_rom0_r0 */
+#define TZC_SEC_TZC_ROM0_R0_OFFSET     (0x44)
+#define TZC_SEC_TZC_ROM0_R0_END        TZC_SEC_TZC_ROM0_R0_END
+#define TZC_SEC_TZC_ROM0_R0_END_POS    (0U)
+#define TZC_SEC_TZC_ROM0_R0_END_LEN    (16U)
+#define TZC_SEC_TZC_ROM0_R0_END_MSK    (((1U << TZC_SEC_TZC_ROM0_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_END_POS)
+#define TZC_SEC_TZC_ROM0_R0_END_UMSK   (~(((1U << TZC_SEC_TZC_ROM0_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_END_POS))
+#define TZC_SEC_TZC_ROM0_R0_START      TZC_SEC_TZC_ROM0_R0_START
+#define TZC_SEC_TZC_ROM0_R0_START_POS  (16U)
+#define TZC_SEC_TZC_ROM0_R0_START_LEN  (16U)
+#define TZC_SEC_TZC_ROM0_R0_START_MSK  (((1U << TZC_SEC_TZC_ROM0_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_START_POS)
+#define TZC_SEC_TZC_ROM0_R0_START_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_START_POS))
+
+/* 0x48 : tzc_rom0_r1 */
+#define TZC_SEC_TZC_ROM0_R1_OFFSET     (0x48)
+#define TZC_SEC_TZC_ROM0_R1_END        TZC_SEC_TZC_ROM0_R1_END
+#define TZC_SEC_TZC_ROM0_R1_END_POS    (0U)
+#define TZC_SEC_TZC_ROM0_R1_END_LEN    (16U)
+#define TZC_SEC_TZC_ROM0_R1_END_MSK    (((1U << TZC_SEC_TZC_ROM0_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_END_POS)
+#define TZC_SEC_TZC_ROM0_R1_END_UMSK   (~(((1U << TZC_SEC_TZC_ROM0_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_END_POS))
+#define TZC_SEC_TZC_ROM0_R1_START      TZC_SEC_TZC_ROM0_R1_START
+#define TZC_SEC_TZC_ROM0_R1_START_POS  (16U)
+#define TZC_SEC_TZC_ROM0_R1_START_LEN  (16U)
+#define TZC_SEC_TZC_ROM0_R1_START_MSK  (((1U << TZC_SEC_TZC_ROM0_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_START_POS)
+#define TZC_SEC_TZC_ROM0_R1_START_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_START_POS))
+
+/* 0x4C : tzc_rom1_r0 */
+#define TZC_SEC_TZC_ROM1_R0_OFFSET     (0x4C)
+#define TZC_SEC_TZC_ROM1_R0_END        TZC_SEC_TZC_ROM1_R0_END
+#define TZC_SEC_TZC_ROM1_R0_END_POS    (0U)
+#define TZC_SEC_TZC_ROM1_R0_END_LEN    (16U)
+#define TZC_SEC_TZC_ROM1_R0_END_MSK    (((1U << TZC_SEC_TZC_ROM1_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_END_POS)
+#define TZC_SEC_TZC_ROM1_R0_END_UMSK   (~(((1U << TZC_SEC_TZC_ROM1_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_END_POS))
+#define TZC_SEC_TZC_ROM1_R0_START      TZC_SEC_TZC_ROM1_R0_START
+#define TZC_SEC_TZC_ROM1_R0_START_POS  (16U)
+#define TZC_SEC_TZC_ROM1_R0_START_LEN  (16U)
+#define TZC_SEC_TZC_ROM1_R0_START_MSK  (((1U << TZC_SEC_TZC_ROM1_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_START_POS)
+#define TZC_SEC_TZC_ROM1_R0_START_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_START_POS))
+
+/* 0x50 : tzc_rom1_r1 */
+#define TZC_SEC_TZC_ROM1_R1_OFFSET     (0x50)
+#define TZC_SEC_TZC_ROM1_R1_END        TZC_SEC_TZC_ROM1_R1_END
+#define TZC_SEC_TZC_ROM1_R1_END_POS    (0U)
+#define TZC_SEC_TZC_ROM1_R1_END_LEN    (16U)
+#define TZC_SEC_TZC_ROM1_R1_END_MSK    (((1U << TZC_SEC_TZC_ROM1_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_END_POS)
+#define TZC_SEC_TZC_ROM1_R1_END_UMSK   (~(((1U << TZC_SEC_TZC_ROM1_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_END_POS))
+#define TZC_SEC_TZC_ROM1_R1_START      TZC_SEC_TZC_ROM1_R1_START
+#define TZC_SEC_TZC_ROM1_R1_START_POS  (16U)
+#define TZC_SEC_TZC_ROM1_R1_START_LEN  (16U)
+#define TZC_SEC_TZC_ROM1_R1_START_MSK  (((1U << TZC_SEC_TZC_ROM1_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_START_POS)
+#define TZC_SEC_TZC_ROM1_R1_START_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_START_POS))
+
+struct tzc_sec_reg {
+    /* 0x0  reserved */
+    uint8_t RESERVED0x0[64];
+
+    /* 0x40 : tzc_rom_ctrl */
+    union {
+        struct
+        {
+            uint32_t tzc_rom0_r0_id0_en : 1; /* [    0],        r/w,        0x1 */
+            uint32_t tzc_rom0_r1_id0_en : 1; /* [    1],        r/w,        0x1 */
+            uint32_t tzc_rom1_r0_id0_en : 1; /* [    2],        r/w,        0x1 */
+            uint32_t tzc_rom1_r1_id0_en : 1; /* [    3],        r/w,        0x1 */
+            uint32_t reserved_4_7       : 4; /* [ 7: 4],       rsvd,        0x0 */
+            uint32_t tzc_rom0_r0_id1_en : 1; /* [    8],        r/w,        0x1 */
+            uint32_t tzc_rom0_r1_id1_en : 1; /* [    9],        r/w,        0x1 */
+            uint32_t tzc_rom1_r0_id1_en : 1; /* [   10],        r/w,        0x1 */
+            uint32_t tzc_rom1_r1_id1_en : 1; /* [   11],        r/w,        0x1 */
+            uint32_t reserved_12_15     : 4; /* [15:12],       rsvd,        0x0 */
+            uint32_t tzc_rom0_r0_en     : 1; /* [   16],        r/w,        0x0 */
+            uint32_t tzc_rom0_r1_en     : 1; /* [   17],        r/w,        0x0 */
+            uint32_t tzc_rom1_r0_en     : 1; /* [   18],        r/w,        0x0 */
+            uint32_t tzc_rom1_r1_en     : 1; /* [   19],        r/w,        0x0 */
+            uint32_t reserved_20_23     : 4; /* [23:20],       rsvd,        0x0 */
+            uint32_t tzc_rom0_r0_lock   : 1; /* [   24],        r/w,        0x0 */
+            uint32_t tzc_rom0_r1_lock   : 1; /* [   25],        r/w,        0x0 */
+            uint32_t tzc_rom1_r0_lock   : 1; /* [   26],        r/w,        0x0 */
+            uint32_t tzc_rom1_r1_lock   : 1; /* [   27],        r/w,        0x0 */
+            uint32_t tzc_sboot_done     : 4; /* [31:28],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_rom_ctrl;
+
+    /* 0x44 : tzc_rom0_r0 */
+    union {
+        struct
+        {
+            uint32_t tzc_rom0_r0_end   : 16; /* [15: 0],        r/w,     0xffff */
+            uint32_t tzc_rom0_r0_start : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_rom0_r0;
+
+    /* 0x48 : tzc_rom0_r1 */
+    union {
+        struct
+        {
+            uint32_t tzc_rom0_r1_end   : 16; /* [15: 0],        r/w,     0xffff */
+            uint32_t tzc_rom0_r1_start : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_rom0_r1;
+
+    /* 0x4C : tzc_rom1_r0 */
+    union {
+        struct
+        {
+            uint32_t tzc_rom1_r0_end   : 16; /* [15: 0],        r/w,     0xffff */
+            uint32_t tzc_rom1_r0_start : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_rom1_r0;
+
+    /* 0x50 : tzc_rom1_r1 */
+    union {
+        struct
+        {
+            uint32_t tzc_rom1_r1_end   : 16; /* [15: 0],        r/w,     0xffff */
+            uint32_t tzc_rom1_r1_start : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_rom1_r1;
+};
+
+typedef volatile struct tzc_sec_reg tzc_sec_reg_t;
+
+#endif /* __TZC_SEC_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/uart_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/uart_reg.h
new file mode 100644
index 00000000..6a53957c
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/uart_reg.h
@@ -0,0 +1,769 @@
+/**
+  ******************************************************************************
+  * @file    uart_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __UART_REG_H__
+#define __UART_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : utx_config */
+#define UART_UTX_CONFIG_OFFSET     (0x0)
+#define UART_CR_UTX_EN             UART_CR_UTX_EN
+#define UART_CR_UTX_EN_POS         (0U)
+#define UART_CR_UTX_EN_LEN         (1U)
+#define UART_CR_UTX_EN_MSK         (((1U << UART_CR_UTX_EN_LEN) - 1) << UART_CR_UTX_EN_POS)
+#define UART_CR_UTX_EN_UMSK        (~(((1U << UART_CR_UTX_EN_LEN) - 1) << UART_CR_UTX_EN_POS))
+#define UART_CR_UTX_CTS_EN         UART_CR_UTX_CTS_EN
+#define UART_CR_UTX_CTS_EN_POS     (1U)
+#define UART_CR_UTX_CTS_EN_LEN     (1U)
+#define UART_CR_UTX_CTS_EN_MSK     (((1U << UART_CR_UTX_CTS_EN_LEN) - 1) << UART_CR_UTX_CTS_EN_POS)
+#define UART_CR_UTX_CTS_EN_UMSK    (~(((1U << UART_CR_UTX_CTS_EN_LEN) - 1) << UART_CR_UTX_CTS_EN_POS))
+#define UART_CR_UTX_FRM_EN         UART_CR_UTX_FRM_EN
+#define UART_CR_UTX_FRM_EN_POS     (2U)
+#define UART_CR_UTX_FRM_EN_LEN     (1U)
+#define UART_CR_UTX_FRM_EN_MSK     (((1U << UART_CR_UTX_FRM_EN_LEN) - 1) << UART_CR_UTX_FRM_EN_POS)
+#define UART_CR_UTX_FRM_EN_UMSK    (~(((1U << UART_CR_UTX_FRM_EN_LEN) - 1) << UART_CR_UTX_FRM_EN_POS))
+#define UART_CR_UTX_LIN_EN         UART_CR_UTX_LIN_EN
+#define UART_CR_UTX_LIN_EN_POS     (3U)
+#define UART_CR_UTX_LIN_EN_LEN     (1U)
+#define UART_CR_UTX_LIN_EN_MSK     (((1U << UART_CR_UTX_LIN_EN_LEN) - 1) << UART_CR_UTX_LIN_EN_POS)
+#define UART_CR_UTX_LIN_EN_UMSK    (~(((1U << UART_CR_UTX_LIN_EN_LEN) - 1) << UART_CR_UTX_LIN_EN_POS))
+#define UART_CR_UTX_PRT_EN         UART_CR_UTX_PRT_EN
+#define UART_CR_UTX_PRT_EN_POS     (4U)
+#define UART_CR_UTX_PRT_EN_LEN     (1U)
+#define UART_CR_UTX_PRT_EN_MSK     (((1U << UART_CR_UTX_PRT_EN_LEN) - 1) << UART_CR_UTX_PRT_EN_POS)
+#define UART_CR_UTX_PRT_EN_UMSK    (~(((1U << UART_CR_UTX_PRT_EN_LEN) - 1) << UART_CR_UTX_PRT_EN_POS))
+#define UART_CR_UTX_PRT_SEL        UART_CR_UTX_PRT_SEL
+#define UART_CR_UTX_PRT_SEL_POS    (5U)
+#define UART_CR_UTX_PRT_SEL_LEN    (1U)
+#define UART_CR_UTX_PRT_SEL_MSK    (((1U << UART_CR_UTX_PRT_SEL_LEN) - 1) << UART_CR_UTX_PRT_SEL_POS)
+#define UART_CR_UTX_PRT_SEL_UMSK   (~(((1U << UART_CR_UTX_PRT_SEL_LEN) - 1) << UART_CR_UTX_PRT_SEL_POS))
+#define UART_CR_UTX_IR_EN          UART_CR_UTX_IR_EN
+#define UART_CR_UTX_IR_EN_POS      (6U)
+#define UART_CR_UTX_IR_EN_LEN      (1U)
+#define UART_CR_UTX_IR_EN_MSK      (((1U << UART_CR_UTX_IR_EN_LEN) - 1) << UART_CR_UTX_IR_EN_POS)
+#define UART_CR_UTX_IR_EN_UMSK     (~(((1U << UART_CR_UTX_IR_EN_LEN) - 1) << UART_CR_UTX_IR_EN_POS))
+#define UART_CR_UTX_IR_INV         UART_CR_UTX_IR_INV
+#define UART_CR_UTX_IR_INV_POS     (7U)
+#define UART_CR_UTX_IR_INV_LEN     (1U)
+#define UART_CR_UTX_IR_INV_MSK     (((1U << UART_CR_UTX_IR_INV_LEN) - 1) << UART_CR_UTX_IR_INV_POS)
+#define UART_CR_UTX_IR_INV_UMSK    (~(((1U << UART_CR_UTX_IR_INV_LEN) - 1) << UART_CR_UTX_IR_INV_POS))
+#define UART_CR_UTX_BIT_CNT_D      UART_CR_UTX_BIT_CNT_D
+#define UART_CR_UTX_BIT_CNT_D_POS  (8U)
+#define UART_CR_UTX_BIT_CNT_D_LEN  (3U)
+#define UART_CR_UTX_BIT_CNT_D_MSK  (((1U << UART_CR_UTX_BIT_CNT_D_LEN) - 1) << UART_CR_UTX_BIT_CNT_D_POS)
+#define UART_CR_UTX_BIT_CNT_D_UMSK (~(((1U << UART_CR_UTX_BIT_CNT_D_LEN) - 1) << UART_CR_UTX_BIT_CNT_D_POS))
+#define UART_CR_UTX_BIT_CNT_P      UART_CR_UTX_BIT_CNT_P
+#define UART_CR_UTX_BIT_CNT_P_POS  (11U)
+#define UART_CR_UTX_BIT_CNT_P_LEN  (2U)
+#define UART_CR_UTX_BIT_CNT_P_MSK  (((1U << UART_CR_UTX_BIT_CNT_P_LEN) - 1) << UART_CR_UTX_BIT_CNT_P_POS)
+#define UART_CR_UTX_BIT_CNT_P_UMSK (~(((1U << UART_CR_UTX_BIT_CNT_P_LEN) - 1) << UART_CR_UTX_BIT_CNT_P_POS))
+#define UART_CR_UTX_BIT_CNT_B      UART_CR_UTX_BIT_CNT_B
+#define UART_CR_UTX_BIT_CNT_B_POS  (13U)
+#define UART_CR_UTX_BIT_CNT_B_LEN  (3U)
+#define UART_CR_UTX_BIT_CNT_B_MSK  (((1U << UART_CR_UTX_BIT_CNT_B_LEN) - 1) << UART_CR_UTX_BIT_CNT_B_POS)
+#define UART_CR_UTX_BIT_CNT_B_UMSK (~(((1U << UART_CR_UTX_BIT_CNT_B_LEN) - 1) << UART_CR_UTX_BIT_CNT_B_POS))
+#define UART_CR_UTX_LEN            UART_CR_UTX_LEN
+#define UART_CR_UTX_LEN_POS        (16U)
+#define UART_CR_UTX_LEN_LEN        (16U)
+#define UART_CR_UTX_LEN_MSK        (((1U << UART_CR_UTX_LEN_LEN) - 1) << UART_CR_UTX_LEN_POS)
+#define UART_CR_UTX_LEN_UMSK       (~(((1U << UART_CR_UTX_LEN_LEN) - 1) << UART_CR_UTX_LEN_POS))
+
+/* 0x4 : urx_config */
+#define UART_URX_CONFIG_OFFSET     (0x4)
+#define UART_CR_URX_EN             UART_CR_URX_EN
+#define UART_CR_URX_EN_POS         (0U)
+#define UART_CR_URX_EN_LEN         (1U)
+#define UART_CR_URX_EN_MSK         (((1U << UART_CR_URX_EN_LEN) - 1) << UART_CR_URX_EN_POS)
+#define UART_CR_URX_EN_UMSK        (~(((1U << UART_CR_URX_EN_LEN) - 1) << UART_CR_URX_EN_POS))
+#define UART_CR_URX_ABR_EN         UART_CR_URX_ABR_EN
+#define UART_CR_URX_ABR_EN_POS     (1U)
+#define UART_CR_URX_ABR_EN_LEN     (1U)
+#define UART_CR_URX_ABR_EN_MSK     (((1U << UART_CR_URX_ABR_EN_LEN) - 1) << UART_CR_URX_ABR_EN_POS)
+#define UART_CR_URX_ABR_EN_UMSK    (~(((1U << UART_CR_URX_ABR_EN_LEN) - 1) << UART_CR_URX_ABR_EN_POS))
+#define UART_CR_URX_LIN_EN         UART_CR_URX_LIN_EN
+#define UART_CR_URX_LIN_EN_POS     (3U)
+#define UART_CR_URX_LIN_EN_LEN     (1U)
+#define UART_CR_URX_LIN_EN_MSK     (((1U << UART_CR_URX_LIN_EN_LEN) - 1) << UART_CR_URX_LIN_EN_POS)
+#define UART_CR_URX_LIN_EN_UMSK    (~(((1U << UART_CR_URX_LIN_EN_LEN) - 1) << UART_CR_URX_LIN_EN_POS))
+#define UART_CR_URX_PRT_EN         UART_CR_URX_PRT_EN
+#define UART_CR_URX_PRT_EN_POS     (4U)
+#define UART_CR_URX_PRT_EN_LEN     (1U)
+#define UART_CR_URX_PRT_EN_MSK     (((1U << UART_CR_URX_PRT_EN_LEN) - 1) << UART_CR_URX_PRT_EN_POS)
+#define UART_CR_URX_PRT_EN_UMSK    (~(((1U << UART_CR_URX_PRT_EN_LEN) - 1) << UART_CR_URX_PRT_EN_POS))
+#define UART_CR_URX_PRT_SEL        UART_CR_URX_PRT_SEL
+#define UART_CR_URX_PRT_SEL_POS    (5U)
+#define UART_CR_URX_PRT_SEL_LEN    (1U)
+#define UART_CR_URX_PRT_SEL_MSK    (((1U << UART_CR_URX_PRT_SEL_LEN) - 1) << UART_CR_URX_PRT_SEL_POS)
+#define UART_CR_URX_PRT_SEL_UMSK   (~(((1U << UART_CR_URX_PRT_SEL_LEN) - 1) << UART_CR_URX_PRT_SEL_POS))
+#define UART_CR_URX_IR_EN          UART_CR_URX_IR_EN
+#define UART_CR_URX_IR_EN_POS      (6U)
+#define UART_CR_URX_IR_EN_LEN      (1U)
+#define UART_CR_URX_IR_EN_MSK      (((1U << UART_CR_URX_IR_EN_LEN) - 1) << UART_CR_URX_IR_EN_POS)
+#define UART_CR_URX_IR_EN_UMSK     (~(((1U << UART_CR_URX_IR_EN_LEN) - 1) << UART_CR_URX_IR_EN_POS))
+#define UART_CR_URX_IR_INV         UART_CR_URX_IR_INV
+#define UART_CR_URX_IR_INV_POS     (7U)
+#define UART_CR_URX_IR_INV_LEN     (1U)
+#define UART_CR_URX_IR_INV_MSK     (((1U << UART_CR_URX_IR_INV_LEN) - 1) << UART_CR_URX_IR_INV_POS)
+#define UART_CR_URX_IR_INV_UMSK    (~(((1U << UART_CR_URX_IR_INV_LEN) - 1) << UART_CR_URX_IR_INV_POS))
+#define UART_CR_URX_BIT_CNT_D      UART_CR_URX_BIT_CNT_D
+#define UART_CR_URX_BIT_CNT_D_POS  (8U)
+#define UART_CR_URX_BIT_CNT_D_LEN  (3U)
+#define UART_CR_URX_BIT_CNT_D_MSK  (((1U << UART_CR_URX_BIT_CNT_D_LEN) - 1) << UART_CR_URX_BIT_CNT_D_POS)
+#define UART_CR_URX_BIT_CNT_D_UMSK (~(((1U << UART_CR_URX_BIT_CNT_D_LEN) - 1) << UART_CR_URX_BIT_CNT_D_POS))
+#define UART_CR_URX_DEG_EN         UART_CR_URX_DEG_EN
+#define UART_CR_URX_DEG_EN_POS     (11U)
+#define UART_CR_URX_DEG_EN_LEN     (1U)
+#define UART_CR_URX_DEG_EN_MSK     (((1U << UART_CR_URX_DEG_EN_LEN) - 1) << UART_CR_URX_DEG_EN_POS)
+#define UART_CR_URX_DEG_EN_UMSK    (~(((1U << UART_CR_URX_DEG_EN_LEN) - 1) << UART_CR_URX_DEG_EN_POS))
+#define UART_CR_URX_DEG_CNT        UART_CR_URX_DEG_CNT
+#define UART_CR_URX_DEG_CNT_POS    (12U)
+#define UART_CR_URX_DEG_CNT_LEN    (4U)
+#define UART_CR_URX_DEG_CNT_MSK    (((1U << UART_CR_URX_DEG_CNT_LEN) - 1) << UART_CR_URX_DEG_CNT_POS)
+#define UART_CR_URX_DEG_CNT_UMSK   (~(((1U << UART_CR_URX_DEG_CNT_LEN) - 1) << UART_CR_URX_DEG_CNT_POS))
+#define UART_CR_URX_LEN            UART_CR_URX_LEN
+#define UART_CR_URX_LEN_POS        (16U)
+#define UART_CR_URX_LEN_LEN        (16U)
+#define UART_CR_URX_LEN_MSK        (((1U << UART_CR_URX_LEN_LEN) - 1) << UART_CR_URX_LEN_POS)
+#define UART_CR_URX_LEN_UMSK       (~(((1U << UART_CR_URX_LEN_LEN) - 1) << UART_CR_URX_LEN_POS))
+
+/* 0x8 : uart_bit_prd */
+#define UART_BIT_PRD_OFFSET      (0x8)
+#define UART_CR_UTX_BIT_PRD      UART_CR_UTX_BIT_PRD
+#define UART_CR_UTX_BIT_PRD_POS  (0U)
+#define UART_CR_UTX_BIT_PRD_LEN  (16U)
+#define UART_CR_UTX_BIT_PRD_MSK  (((1U << UART_CR_UTX_BIT_PRD_LEN) - 1) << UART_CR_UTX_BIT_PRD_POS)
+#define UART_CR_UTX_BIT_PRD_UMSK (~(((1U << UART_CR_UTX_BIT_PRD_LEN) - 1) << UART_CR_UTX_BIT_PRD_POS))
+#define UART_CR_URX_BIT_PRD      UART_CR_URX_BIT_PRD
+#define UART_CR_URX_BIT_PRD_POS  (16U)
+#define UART_CR_URX_BIT_PRD_LEN  (16U)
+#define UART_CR_URX_BIT_PRD_MSK  (((1U << UART_CR_URX_BIT_PRD_LEN) - 1) << UART_CR_URX_BIT_PRD_POS)
+#define UART_CR_URX_BIT_PRD_UMSK (~(((1U << UART_CR_URX_BIT_PRD_LEN) - 1) << UART_CR_URX_BIT_PRD_POS))
+
+/* 0xC : data_config */
+#define UART_DATA_CONFIG_OFFSET   (0xC)
+#define UART_CR_UART_BIT_INV      UART_CR_UART_BIT_INV
+#define UART_CR_UART_BIT_INV_POS  (0U)
+#define UART_CR_UART_BIT_INV_LEN  (1U)
+#define UART_CR_UART_BIT_INV_MSK  (((1U << UART_CR_UART_BIT_INV_LEN) - 1) << UART_CR_UART_BIT_INV_POS)
+#define UART_CR_UART_BIT_INV_UMSK (~(((1U << UART_CR_UART_BIT_INV_LEN) - 1) << UART_CR_UART_BIT_INV_POS))
+
+/* 0x10 : utx_ir_position */
+#define UART_UTX_IR_POSITION_OFFSET (0x10)
+#define UART_CR_UTX_IR_POS_S        UART_CR_UTX_IR_POS_S
+#define UART_CR_UTX_IR_POS_S_POS    (0U)
+#define UART_CR_UTX_IR_POS_S_LEN    (16U)
+#define UART_CR_UTX_IR_POS_S_MSK    (((1U << UART_CR_UTX_IR_POS_S_LEN) - 1) << UART_CR_UTX_IR_POS_S_POS)
+#define UART_CR_UTX_IR_POS_S_UMSK   (~(((1U << UART_CR_UTX_IR_POS_S_LEN) - 1) << UART_CR_UTX_IR_POS_S_POS))
+#define UART_CR_UTX_IR_POS_P        UART_CR_UTX_IR_POS_P
+#define UART_CR_UTX_IR_POS_P_POS    (16U)
+#define UART_CR_UTX_IR_POS_P_LEN    (16U)
+#define UART_CR_UTX_IR_POS_P_MSK    (((1U << UART_CR_UTX_IR_POS_P_LEN) - 1) << UART_CR_UTX_IR_POS_P_POS)
+#define UART_CR_UTX_IR_POS_P_UMSK   (~(((1U << UART_CR_UTX_IR_POS_P_LEN) - 1) << UART_CR_UTX_IR_POS_P_POS))
+
+/* 0x14 : urx_ir_position */
+#define UART_URX_IR_POSITION_OFFSET (0x14)
+#define UART_CR_URX_IR_POS_S        UART_CR_URX_IR_POS_S
+#define UART_CR_URX_IR_POS_S_POS    (0U)
+#define UART_CR_URX_IR_POS_S_LEN    (16U)
+#define UART_CR_URX_IR_POS_S_MSK    (((1U << UART_CR_URX_IR_POS_S_LEN) - 1) << UART_CR_URX_IR_POS_S_POS)
+#define UART_CR_URX_IR_POS_S_UMSK   (~(((1U << UART_CR_URX_IR_POS_S_LEN) - 1) << UART_CR_URX_IR_POS_S_POS))
+
+/* 0x18 : urx_rto_timer */
+#define UART_URX_RTO_TIMER_OFFSET  (0x18)
+#define UART_CR_URX_RTO_VALUE      UART_CR_URX_RTO_VALUE
+#define UART_CR_URX_RTO_VALUE_POS  (0U)
+#define UART_CR_URX_RTO_VALUE_LEN  (8U)
+#define UART_CR_URX_RTO_VALUE_MSK  (((1U << UART_CR_URX_RTO_VALUE_LEN) - 1) << UART_CR_URX_RTO_VALUE_POS)
+#define UART_CR_URX_RTO_VALUE_UMSK (~(((1U << UART_CR_URX_RTO_VALUE_LEN) - 1) << UART_CR_URX_RTO_VALUE_POS))
+
+/* 0x1C : uart_sw_mode */
+#define UART_SW_MODE_OFFSET          (0x1C)
+#define UART_CR_UTX_TXD_SW_MODE      UART_CR_UTX_TXD_SW_MODE
+#define UART_CR_UTX_TXD_SW_MODE_POS  (0U)
+#define UART_CR_UTX_TXD_SW_MODE_LEN  (1U)
+#define UART_CR_UTX_TXD_SW_MODE_MSK  (((1U << UART_CR_UTX_TXD_SW_MODE_LEN) - 1) << UART_CR_UTX_TXD_SW_MODE_POS)
+#define UART_CR_UTX_TXD_SW_MODE_UMSK (~(((1U << UART_CR_UTX_TXD_SW_MODE_LEN) - 1) << UART_CR_UTX_TXD_SW_MODE_POS))
+#define UART_CR_UTX_TXD_SW_VAL       UART_CR_UTX_TXD_SW_VAL
+#define UART_CR_UTX_TXD_SW_VAL_POS   (1U)
+#define UART_CR_UTX_TXD_SW_VAL_LEN   (1U)
+#define UART_CR_UTX_TXD_SW_VAL_MSK   (((1U << UART_CR_UTX_TXD_SW_VAL_LEN) - 1) << UART_CR_UTX_TXD_SW_VAL_POS)
+#define UART_CR_UTX_TXD_SW_VAL_UMSK  (~(((1U << UART_CR_UTX_TXD_SW_VAL_LEN) - 1) << UART_CR_UTX_TXD_SW_VAL_POS))
+#define UART_CR_URX_RTS_SW_MODE      UART_CR_URX_RTS_SW_MODE
+#define UART_CR_URX_RTS_SW_MODE_POS  (2U)
+#define UART_CR_URX_RTS_SW_MODE_LEN  (1U)
+#define UART_CR_URX_RTS_SW_MODE_MSK  (((1U << UART_CR_URX_RTS_SW_MODE_LEN) - 1) << UART_CR_URX_RTS_SW_MODE_POS)
+#define UART_CR_URX_RTS_SW_MODE_UMSK (~(((1U << UART_CR_URX_RTS_SW_MODE_LEN) - 1) << UART_CR_URX_RTS_SW_MODE_POS))
+#define UART_CR_URX_RTS_SW_VAL       UART_CR_URX_RTS_SW_VAL
+#define UART_CR_URX_RTS_SW_VAL_POS   (3U)
+#define UART_CR_URX_RTS_SW_VAL_LEN   (1U)
+#define UART_CR_URX_RTS_SW_VAL_MSK   (((1U << UART_CR_URX_RTS_SW_VAL_LEN) - 1) << UART_CR_URX_RTS_SW_VAL_POS)
+#define UART_CR_URX_RTS_SW_VAL_UMSK  (~(((1U << UART_CR_URX_RTS_SW_VAL_LEN) - 1) << UART_CR_URX_RTS_SW_VAL_POS))
+
+/* 0x20 : UART interrupt status */
+#define UART_INT_STS_OFFSET    (0x20)
+#define UART_UTX_END_INT       UART_UTX_END_INT
+#define UART_UTX_END_INT_POS   (0U)
+#define UART_UTX_END_INT_LEN   (1U)
+#define UART_UTX_END_INT_MSK   (((1U << UART_UTX_END_INT_LEN) - 1) << UART_UTX_END_INT_POS)
+#define UART_UTX_END_INT_UMSK  (~(((1U << UART_UTX_END_INT_LEN) - 1) << UART_UTX_END_INT_POS))
+#define UART_URX_END_INT       UART_URX_END_INT
+#define UART_URX_END_INT_POS   (1U)
+#define UART_URX_END_INT_LEN   (1U)
+#define UART_URX_END_INT_MSK   (((1U << UART_URX_END_INT_LEN) - 1) << UART_URX_END_INT_POS)
+#define UART_URX_END_INT_UMSK  (~(((1U << UART_URX_END_INT_LEN) - 1) << UART_URX_END_INT_POS))
+#define UART_UTX_FIFO_INT      UART_UTX_FIFO_INT
+#define UART_UTX_FIFO_INT_POS  (2U)
+#define UART_UTX_FIFO_INT_LEN  (1U)
+#define UART_UTX_FIFO_INT_MSK  (((1U << UART_UTX_FIFO_INT_LEN) - 1) << UART_UTX_FIFO_INT_POS)
+#define UART_UTX_FIFO_INT_UMSK (~(((1U << UART_UTX_FIFO_INT_LEN) - 1) << UART_UTX_FIFO_INT_POS))
+#define UART_URX_FIFO_INT      UART_URX_FIFO_INT
+#define UART_URX_FIFO_INT_POS  (3U)
+#define UART_URX_FIFO_INT_LEN  (1U)
+#define UART_URX_FIFO_INT_MSK  (((1U << UART_URX_FIFO_INT_LEN) - 1) << UART_URX_FIFO_INT_POS)
+#define UART_URX_FIFO_INT_UMSK (~(((1U << UART_URX_FIFO_INT_LEN) - 1) << UART_URX_FIFO_INT_POS))
+#define UART_URX_RTO_INT       UART_URX_RTO_INT
+#define UART_URX_RTO_INT_POS   (4U)
+#define UART_URX_RTO_INT_LEN   (1U)
+#define UART_URX_RTO_INT_MSK   (((1U << UART_URX_RTO_INT_LEN) - 1) << UART_URX_RTO_INT_POS)
+#define UART_URX_RTO_INT_UMSK  (~(((1U << UART_URX_RTO_INT_LEN) - 1) << UART_URX_RTO_INT_POS))
+#define UART_URX_PCE_INT       UART_URX_PCE_INT
+#define UART_URX_PCE_INT_POS   (5U)
+#define UART_URX_PCE_INT_LEN   (1U)
+#define UART_URX_PCE_INT_MSK   (((1U << UART_URX_PCE_INT_LEN) - 1) << UART_URX_PCE_INT_POS)
+#define UART_URX_PCE_INT_UMSK  (~(((1U << UART_URX_PCE_INT_LEN) - 1) << UART_URX_PCE_INT_POS))
+#define UART_UTX_FER_INT       UART_UTX_FER_INT
+#define UART_UTX_FER_INT_POS   (6U)
+#define UART_UTX_FER_INT_LEN   (1U)
+#define UART_UTX_FER_INT_MSK   (((1U << UART_UTX_FER_INT_LEN) - 1) << UART_UTX_FER_INT_POS)
+#define UART_UTX_FER_INT_UMSK  (~(((1U << UART_UTX_FER_INT_LEN) - 1) << UART_UTX_FER_INT_POS))
+#define UART_URX_FER_INT       UART_URX_FER_INT
+#define UART_URX_FER_INT_POS   (7U)
+#define UART_URX_FER_INT_LEN   (1U)
+#define UART_URX_FER_INT_MSK   (((1U << UART_URX_FER_INT_LEN) - 1) << UART_URX_FER_INT_POS)
+#define UART_URX_FER_INT_UMSK  (~(((1U << UART_URX_FER_INT_LEN) - 1) << UART_URX_FER_INT_POS))
+#define UART_URX_LSE_INT       UART_URX_LSE_INT
+#define UART_URX_LSE_INT_POS   (8U)
+#define UART_URX_LSE_INT_LEN   (1U)
+#define UART_URX_LSE_INT_MSK   (((1U << UART_URX_LSE_INT_LEN) - 1) << UART_URX_LSE_INT_POS)
+#define UART_URX_LSE_INT_UMSK  (~(((1U << UART_URX_LSE_INT_LEN) - 1) << UART_URX_LSE_INT_POS))
+
+/* 0x24 : UART interrupt mask */
+#define UART_INT_MASK_OFFSET       (0x24)
+#define UART_CR_UTX_END_MASK       UART_CR_UTX_END_MASK
+#define UART_CR_UTX_END_MASK_POS   (0U)
+#define UART_CR_UTX_END_MASK_LEN   (1U)
+#define UART_CR_UTX_END_MASK_MSK   (((1U << UART_CR_UTX_END_MASK_LEN) - 1) << UART_CR_UTX_END_MASK_POS)
+#define UART_CR_UTX_END_MASK_UMSK  (~(((1U << UART_CR_UTX_END_MASK_LEN) - 1) << UART_CR_UTX_END_MASK_POS))
+#define UART_CR_URX_END_MASK       UART_CR_URX_END_MASK
+#define UART_CR_URX_END_MASK_POS   (1U)
+#define UART_CR_URX_END_MASK_LEN   (1U)
+#define UART_CR_URX_END_MASK_MSK   (((1U << UART_CR_URX_END_MASK_LEN) - 1) << UART_CR_URX_END_MASK_POS)
+#define UART_CR_URX_END_MASK_UMSK  (~(((1U << UART_CR_URX_END_MASK_LEN) - 1) << UART_CR_URX_END_MASK_POS))
+#define UART_CR_UTX_FIFO_MASK      UART_CR_UTX_FIFO_MASK
+#define UART_CR_UTX_FIFO_MASK_POS  (2U)
+#define UART_CR_UTX_FIFO_MASK_LEN  (1U)
+#define UART_CR_UTX_FIFO_MASK_MSK  (((1U << UART_CR_UTX_FIFO_MASK_LEN) - 1) << UART_CR_UTX_FIFO_MASK_POS)
+#define UART_CR_UTX_FIFO_MASK_UMSK (~(((1U << UART_CR_UTX_FIFO_MASK_LEN) - 1) << UART_CR_UTX_FIFO_MASK_POS))
+#define UART_CR_URX_FIFO_MASK      UART_CR_URX_FIFO_MASK
+#define UART_CR_URX_FIFO_MASK_POS  (3U)
+#define UART_CR_URX_FIFO_MASK_LEN  (1U)
+#define UART_CR_URX_FIFO_MASK_MSK  (((1U << UART_CR_URX_FIFO_MASK_LEN) - 1) << UART_CR_URX_FIFO_MASK_POS)
+#define UART_CR_URX_FIFO_MASK_UMSK (~(((1U << UART_CR_URX_FIFO_MASK_LEN) - 1) << UART_CR_URX_FIFO_MASK_POS))
+#define UART_CR_URX_RTO_MASK       UART_CR_URX_RTO_MASK
+#define UART_CR_URX_RTO_MASK_POS   (4U)
+#define UART_CR_URX_RTO_MASK_LEN   (1U)
+#define UART_CR_URX_RTO_MASK_MSK   (((1U << UART_CR_URX_RTO_MASK_LEN) - 1) << UART_CR_URX_RTO_MASK_POS)
+#define UART_CR_URX_RTO_MASK_UMSK  (~(((1U << UART_CR_URX_RTO_MASK_LEN) - 1) << UART_CR_URX_RTO_MASK_POS))
+#define UART_CR_URX_PCE_MASK       UART_CR_URX_PCE_MASK
+#define UART_CR_URX_PCE_MASK_POS   (5U)
+#define UART_CR_URX_PCE_MASK_LEN   (1U)
+#define UART_CR_URX_PCE_MASK_MSK   (((1U << UART_CR_URX_PCE_MASK_LEN) - 1) << UART_CR_URX_PCE_MASK_POS)
+#define UART_CR_URX_PCE_MASK_UMSK  (~(((1U << UART_CR_URX_PCE_MASK_LEN) - 1) << UART_CR_URX_PCE_MASK_POS))
+#define UART_CR_UTX_FER_MASK       UART_CR_UTX_FER_MASK
+#define UART_CR_UTX_FER_MASK_POS   (6U)
+#define UART_CR_UTX_FER_MASK_LEN   (1U)
+#define UART_CR_UTX_FER_MASK_MSK   (((1U << UART_CR_UTX_FER_MASK_LEN) - 1) << UART_CR_UTX_FER_MASK_POS)
+#define UART_CR_UTX_FER_MASK_UMSK  (~(((1U << UART_CR_UTX_FER_MASK_LEN) - 1) << UART_CR_UTX_FER_MASK_POS))
+#define UART_CR_URX_FER_MASK       UART_CR_URX_FER_MASK
+#define UART_CR_URX_FER_MASK_POS   (7U)
+#define UART_CR_URX_FER_MASK_LEN   (1U)
+#define UART_CR_URX_FER_MASK_MSK   (((1U << UART_CR_URX_FER_MASK_LEN) - 1) << UART_CR_URX_FER_MASK_POS)
+#define UART_CR_URX_FER_MASK_UMSK  (~(((1U << UART_CR_URX_FER_MASK_LEN) - 1) << UART_CR_URX_FER_MASK_POS))
+#define UART_CR_URX_LSE_MASK       UART_CR_URX_LSE_MASK
+#define UART_CR_URX_LSE_MASK_POS   (8U)
+#define UART_CR_URX_LSE_MASK_LEN   (1U)
+#define UART_CR_URX_LSE_MASK_MSK   (((1U << UART_CR_URX_LSE_MASK_LEN) - 1) << UART_CR_URX_LSE_MASK_POS)
+#define UART_CR_URX_LSE_MASK_UMSK  (~(((1U << UART_CR_URX_LSE_MASK_LEN) - 1) << UART_CR_URX_LSE_MASK_POS))
+
+/* 0x28 : UART interrupt clear */
+#define UART_INT_CLEAR_OFFSET    (0x28)
+#define UART_CR_UTX_END_CLR      UART_CR_UTX_END_CLR
+#define UART_CR_UTX_END_CLR_POS  (0U)
+#define UART_CR_UTX_END_CLR_LEN  (1U)
+#define UART_CR_UTX_END_CLR_MSK  (((1U << UART_CR_UTX_END_CLR_LEN) - 1) << UART_CR_UTX_END_CLR_POS)
+#define UART_CR_UTX_END_CLR_UMSK (~(((1U << UART_CR_UTX_END_CLR_LEN) - 1) << UART_CR_UTX_END_CLR_POS))
+#define UART_CR_URX_END_CLR      UART_CR_URX_END_CLR
+#define UART_CR_URX_END_CLR_POS  (1U)
+#define UART_CR_URX_END_CLR_LEN  (1U)
+#define UART_CR_URX_END_CLR_MSK  (((1U << UART_CR_URX_END_CLR_LEN) - 1) << UART_CR_URX_END_CLR_POS)
+#define UART_CR_URX_END_CLR_UMSK (~(((1U << UART_CR_URX_END_CLR_LEN) - 1) << UART_CR_URX_END_CLR_POS))
+#define UART_CR_URX_RTO_CLR      UART_CR_URX_RTO_CLR
+#define UART_CR_URX_RTO_CLR_POS  (4U)
+#define UART_CR_URX_RTO_CLR_LEN  (1U)
+#define UART_CR_URX_RTO_CLR_MSK  (((1U << UART_CR_URX_RTO_CLR_LEN) - 1) << UART_CR_URX_RTO_CLR_POS)
+#define UART_CR_URX_RTO_CLR_UMSK (~(((1U << UART_CR_URX_RTO_CLR_LEN) - 1) << UART_CR_URX_RTO_CLR_POS))
+#define UART_CR_URX_PCE_CLR      UART_CR_URX_PCE_CLR
+#define UART_CR_URX_PCE_CLR_POS  (5U)
+#define UART_CR_URX_PCE_CLR_LEN  (1U)
+#define UART_CR_URX_PCE_CLR_MSK  (((1U << UART_CR_URX_PCE_CLR_LEN) - 1) << UART_CR_URX_PCE_CLR_POS)
+#define UART_CR_URX_PCE_CLR_UMSK (~(((1U << UART_CR_URX_PCE_CLR_LEN) - 1) << UART_CR_URX_PCE_CLR_POS))
+#define UART_CR_URX_LSE_CLR      UART_CR_URX_LSE_CLR
+#define UART_CR_URX_LSE_CLR_POS  (8U)
+#define UART_CR_URX_LSE_CLR_LEN  (1U)
+#define UART_CR_URX_LSE_CLR_MSK  (((1U << UART_CR_URX_LSE_CLR_LEN) - 1) << UART_CR_URX_LSE_CLR_POS)
+#define UART_CR_URX_LSE_CLR_UMSK (~(((1U << UART_CR_URX_LSE_CLR_LEN) - 1) << UART_CR_URX_LSE_CLR_POS))
+
+/* 0x2C : UART interrupt enable */
+#define UART_INT_EN_OFFSET       (0x2C)
+#define UART_CR_UTX_END_EN       UART_CR_UTX_END_EN
+#define UART_CR_UTX_END_EN_POS   (0U)
+#define UART_CR_UTX_END_EN_LEN   (1U)
+#define UART_CR_UTX_END_EN_MSK   (((1U << UART_CR_UTX_END_EN_LEN) - 1) << UART_CR_UTX_END_EN_POS)
+#define UART_CR_UTX_END_EN_UMSK  (~(((1U << UART_CR_UTX_END_EN_LEN) - 1) << UART_CR_UTX_END_EN_POS))
+#define UART_CR_URX_END_EN       UART_CR_URX_END_EN
+#define UART_CR_URX_END_EN_POS   (1U)
+#define UART_CR_URX_END_EN_LEN   (1U)
+#define UART_CR_URX_END_EN_MSK   (((1U << UART_CR_URX_END_EN_LEN) - 1) << UART_CR_URX_END_EN_POS)
+#define UART_CR_URX_END_EN_UMSK  (~(((1U << UART_CR_URX_END_EN_LEN) - 1) << UART_CR_URX_END_EN_POS))
+#define UART_CR_UTX_FIFO_EN      UART_CR_UTX_FIFO_EN
+#define UART_CR_UTX_FIFO_EN_POS  (2U)
+#define UART_CR_UTX_FIFO_EN_LEN  (1U)
+#define UART_CR_UTX_FIFO_EN_MSK  (((1U << UART_CR_UTX_FIFO_EN_LEN) - 1) << UART_CR_UTX_FIFO_EN_POS)
+#define UART_CR_UTX_FIFO_EN_UMSK (~(((1U << UART_CR_UTX_FIFO_EN_LEN) - 1) << UART_CR_UTX_FIFO_EN_POS))
+#define UART_CR_URX_FIFO_EN      UART_CR_URX_FIFO_EN
+#define UART_CR_URX_FIFO_EN_POS  (3U)
+#define UART_CR_URX_FIFO_EN_LEN  (1U)
+#define UART_CR_URX_FIFO_EN_MSK  (((1U << UART_CR_URX_FIFO_EN_LEN) - 1) << UART_CR_URX_FIFO_EN_POS)
+#define UART_CR_URX_FIFO_EN_UMSK (~(((1U << UART_CR_URX_FIFO_EN_LEN) - 1) << UART_CR_URX_FIFO_EN_POS))
+#define UART_CR_URX_RTO_EN       UART_CR_URX_RTO_EN
+#define UART_CR_URX_RTO_EN_POS   (4U)
+#define UART_CR_URX_RTO_EN_LEN   (1U)
+#define UART_CR_URX_RTO_EN_MSK   (((1U << UART_CR_URX_RTO_EN_LEN) - 1) << UART_CR_URX_RTO_EN_POS)
+#define UART_CR_URX_RTO_EN_UMSK  (~(((1U << UART_CR_URX_RTO_EN_LEN) - 1) << UART_CR_URX_RTO_EN_POS))
+#define UART_CR_URX_PCE_EN       UART_CR_URX_PCE_EN
+#define UART_CR_URX_PCE_EN_POS   (5U)
+#define UART_CR_URX_PCE_EN_LEN   (1U)
+#define UART_CR_URX_PCE_EN_MSK   (((1U << UART_CR_URX_PCE_EN_LEN) - 1) << UART_CR_URX_PCE_EN_POS)
+#define UART_CR_URX_PCE_EN_UMSK  (~(((1U << UART_CR_URX_PCE_EN_LEN) - 1) << UART_CR_URX_PCE_EN_POS))
+#define UART_CR_UTX_FER_EN       UART_CR_UTX_FER_EN
+#define UART_CR_UTX_FER_EN_POS   (6U)
+#define UART_CR_UTX_FER_EN_LEN   (1U)
+#define UART_CR_UTX_FER_EN_MSK   (((1U << UART_CR_UTX_FER_EN_LEN) - 1) << UART_CR_UTX_FER_EN_POS)
+#define UART_CR_UTX_FER_EN_UMSK  (~(((1U << UART_CR_UTX_FER_EN_LEN) - 1) << UART_CR_UTX_FER_EN_POS))
+#define UART_CR_URX_FER_EN       UART_CR_URX_FER_EN
+#define UART_CR_URX_FER_EN_POS   (7U)
+#define UART_CR_URX_FER_EN_LEN   (1U)
+#define UART_CR_URX_FER_EN_MSK   (((1U << UART_CR_URX_FER_EN_LEN) - 1) << UART_CR_URX_FER_EN_POS)
+#define UART_CR_URX_FER_EN_UMSK  (~(((1U << UART_CR_URX_FER_EN_LEN) - 1) << UART_CR_URX_FER_EN_POS))
+#define UART_CR_URX_LSE_EN       UART_CR_URX_LSE_EN
+#define UART_CR_URX_LSE_EN_POS   (8U)
+#define UART_CR_URX_LSE_EN_LEN   (1U)
+#define UART_CR_URX_LSE_EN_MSK   (((1U << UART_CR_URX_LSE_EN_LEN) - 1) << UART_CR_URX_LSE_EN_POS)
+#define UART_CR_URX_LSE_EN_UMSK  (~(((1U << UART_CR_URX_LSE_EN_LEN) - 1) << UART_CR_URX_LSE_EN_POS))
+
+/* 0x30 : uart_status */
+#define UART_STATUS_OFFSET         (0x30)
+#define UART_STS_UTX_BUS_BUSY      UART_STS_UTX_BUS_BUSY
+#define UART_STS_UTX_BUS_BUSY_POS  (0U)
+#define UART_STS_UTX_BUS_BUSY_LEN  (1U)
+#define UART_STS_UTX_BUS_BUSY_MSK  (((1U << UART_STS_UTX_BUS_BUSY_LEN) - 1) << UART_STS_UTX_BUS_BUSY_POS)
+#define UART_STS_UTX_BUS_BUSY_UMSK (~(((1U << UART_STS_UTX_BUS_BUSY_LEN) - 1) << UART_STS_UTX_BUS_BUSY_POS))
+#define UART_STS_URX_BUS_BUSY      UART_STS_URX_BUS_BUSY
+#define UART_STS_URX_BUS_BUSY_POS  (1U)
+#define UART_STS_URX_BUS_BUSY_LEN  (1U)
+#define UART_STS_URX_BUS_BUSY_MSK  (((1U << UART_STS_URX_BUS_BUSY_LEN) - 1) << UART_STS_URX_BUS_BUSY_POS)
+#define UART_STS_URX_BUS_BUSY_UMSK (~(((1U << UART_STS_URX_BUS_BUSY_LEN) - 1) << UART_STS_URX_BUS_BUSY_POS))
+
+/* 0x34 : sts_urx_abr_prd */
+#define UART_STS_URX_ABR_PRD_OFFSET     (0x34)
+#define UART_STS_URX_ABR_PRD_START      UART_STS_URX_ABR_PRD_START
+#define UART_STS_URX_ABR_PRD_START_POS  (0U)
+#define UART_STS_URX_ABR_PRD_START_LEN  (16U)
+#define UART_STS_URX_ABR_PRD_START_MSK  (((1U << UART_STS_URX_ABR_PRD_START_LEN) - 1) << UART_STS_URX_ABR_PRD_START_POS)
+#define UART_STS_URX_ABR_PRD_START_UMSK (~(((1U << UART_STS_URX_ABR_PRD_START_LEN) - 1) << UART_STS_URX_ABR_PRD_START_POS))
+#define UART_STS_URX_ABR_PRD_0X55       UART_STS_URX_ABR_PRD_0X55
+#define UART_STS_URX_ABR_PRD_0X55_POS   (16U)
+#define UART_STS_URX_ABR_PRD_0X55_LEN   (16U)
+#define UART_STS_URX_ABR_PRD_0X55_MSK   (((1U << UART_STS_URX_ABR_PRD_0X55_LEN) - 1) << UART_STS_URX_ABR_PRD_0X55_POS)
+#define UART_STS_URX_ABR_PRD_0X55_UMSK  (~(((1U << UART_STS_URX_ABR_PRD_0X55_LEN) - 1) << UART_STS_URX_ABR_PRD_0X55_POS))
+
+/* 0x80 : uart_fifo_config_0 */
+#define UART_FIFO_CONFIG_0_OFFSET   (0x80)
+#define UART_DMA_TX_EN              UART_DMA_TX_EN
+#define UART_DMA_TX_EN_POS          (0U)
+#define UART_DMA_TX_EN_LEN          (1U)
+#define UART_DMA_TX_EN_MSK          (((1U << UART_DMA_TX_EN_LEN) - 1) << UART_DMA_TX_EN_POS)
+#define UART_DMA_TX_EN_UMSK         (~(((1U << UART_DMA_TX_EN_LEN) - 1) << UART_DMA_TX_EN_POS))
+#define UART_DMA_RX_EN              UART_DMA_RX_EN
+#define UART_DMA_RX_EN_POS          (1U)
+#define UART_DMA_RX_EN_LEN          (1U)
+#define UART_DMA_RX_EN_MSK          (((1U << UART_DMA_RX_EN_LEN) - 1) << UART_DMA_RX_EN_POS)
+#define UART_DMA_RX_EN_UMSK         (~(((1U << UART_DMA_RX_EN_LEN) - 1) << UART_DMA_RX_EN_POS))
+#define UART_TX_FIFO_CLR            UART_TX_FIFO_CLR
+#define UART_TX_FIFO_CLR_POS        (2U)
+#define UART_TX_FIFO_CLR_LEN        (1U)
+#define UART_TX_FIFO_CLR_MSK        (((1U << UART_TX_FIFO_CLR_LEN) - 1) << UART_TX_FIFO_CLR_POS)
+#define UART_TX_FIFO_CLR_UMSK       (~(((1U << UART_TX_FIFO_CLR_LEN) - 1) << UART_TX_FIFO_CLR_POS))
+#define UART_RX_FIFO_CLR            UART_RX_FIFO_CLR
+#define UART_RX_FIFO_CLR_POS        (3U)
+#define UART_RX_FIFO_CLR_LEN        (1U)
+#define UART_RX_FIFO_CLR_MSK        (((1U << UART_RX_FIFO_CLR_LEN) - 1) << UART_RX_FIFO_CLR_POS)
+#define UART_RX_FIFO_CLR_UMSK       (~(((1U << UART_RX_FIFO_CLR_LEN) - 1) << UART_RX_FIFO_CLR_POS))
+#define UART_TX_FIFO_OVERFLOW       UART_TX_FIFO_OVERFLOW
+#define UART_TX_FIFO_OVERFLOW_POS   (4U)
+#define UART_TX_FIFO_OVERFLOW_LEN   (1U)
+#define UART_TX_FIFO_OVERFLOW_MSK   (((1U << UART_TX_FIFO_OVERFLOW_LEN) - 1) << UART_TX_FIFO_OVERFLOW_POS)
+#define UART_TX_FIFO_OVERFLOW_UMSK  (~(((1U << UART_TX_FIFO_OVERFLOW_LEN) - 1) << UART_TX_FIFO_OVERFLOW_POS))
+#define UART_TX_FIFO_UNDERFLOW      UART_TX_FIFO_UNDERFLOW
+#define UART_TX_FIFO_UNDERFLOW_POS  (5U)
+#define UART_TX_FIFO_UNDERFLOW_LEN  (1U)
+#define UART_TX_FIFO_UNDERFLOW_MSK  (((1U << UART_TX_FIFO_UNDERFLOW_LEN) - 1) << UART_TX_FIFO_UNDERFLOW_POS)
+#define UART_TX_FIFO_UNDERFLOW_UMSK (~(((1U << UART_TX_FIFO_UNDERFLOW_LEN) - 1) << UART_TX_FIFO_UNDERFLOW_POS))
+#define UART_RX_FIFO_OVERFLOW       UART_RX_FIFO_OVERFLOW
+#define UART_RX_FIFO_OVERFLOW_POS   (6U)
+#define UART_RX_FIFO_OVERFLOW_LEN   (1U)
+#define UART_RX_FIFO_OVERFLOW_MSK   (((1U << UART_RX_FIFO_OVERFLOW_LEN) - 1) << UART_RX_FIFO_OVERFLOW_POS)
+#define UART_RX_FIFO_OVERFLOW_UMSK  (~(((1U << UART_RX_FIFO_OVERFLOW_LEN) - 1) << UART_RX_FIFO_OVERFLOW_POS))
+#define UART_RX_FIFO_UNDERFLOW      UART_RX_FIFO_UNDERFLOW
+#define UART_RX_FIFO_UNDERFLOW_POS  (7U)
+#define UART_RX_FIFO_UNDERFLOW_LEN  (1U)
+#define UART_RX_FIFO_UNDERFLOW_MSK  (((1U << UART_RX_FIFO_UNDERFLOW_LEN) - 1) << UART_RX_FIFO_UNDERFLOW_POS)
+#define UART_RX_FIFO_UNDERFLOW_UMSK (~(((1U << UART_RX_FIFO_UNDERFLOW_LEN) - 1) << UART_RX_FIFO_UNDERFLOW_POS))
+
+/* 0x84 : uart_fifo_config_1 */
+#define UART_FIFO_CONFIG_1_OFFSET (0x84)
+#define UART_TX_FIFO_CNT          UART_TX_FIFO_CNT
+#define UART_TX_FIFO_CNT_POS      (0U)
+#define UART_TX_FIFO_CNT_LEN      (8U)
+#define UART_TX_FIFO_CNT_MSK      (((1U << UART_TX_FIFO_CNT_LEN) - 1) << UART_TX_FIFO_CNT_POS)
+#define UART_TX_FIFO_CNT_UMSK     (~(((1U << UART_TX_FIFO_CNT_LEN) - 1) << UART_TX_FIFO_CNT_POS))
+#define UART_RX_FIFO_CNT          UART_RX_FIFO_CNT
+#define UART_RX_FIFO_CNT_POS      (8U)
+#define UART_RX_FIFO_CNT_LEN      (8U)
+#define UART_RX_FIFO_CNT_MSK      (((1U << UART_RX_FIFO_CNT_LEN) - 1) << UART_RX_FIFO_CNT_POS)
+#define UART_RX_FIFO_CNT_UMSK     (~(((1U << UART_RX_FIFO_CNT_LEN) - 1) << UART_RX_FIFO_CNT_POS))
+#define UART_TX_FIFO_TH           UART_TX_FIFO_TH
+#define UART_TX_FIFO_TH_POS       (16U)
+#define UART_TX_FIFO_TH_LEN       (7U)
+#define UART_TX_FIFO_TH_MSK       (((1U << UART_TX_FIFO_TH_LEN) - 1) << UART_TX_FIFO_TH_POS)
+#define UART_TX_FIFO_TH_UMSK      (~(((1U << UART_TX_FIFO_TH_LEN) - 1) << UART_TX_FIFO_TH_POS))
+#define UART_RX_FIFO_TH           UART_RX_FIFO_TH
+#define UART_RX_FIFO_TH_POS       (24U)
+#define UART_RX_FIFO_TH_LEN       (7U)
+#define UART_RX_FIFO_TH_MSK       (((1U << UART_RX_FIFO_TH_LEN) - 1) << UART_RX_FIFO_TH_POS)
+#define UART_RX_FIFO_TH_UMSK      (~(((1U << UART_RX_FIFO_TH_LEN) - 1) << UART_RX_FIFO_TH_POS))
+
+/* 0x88 : uart_fifo_wdata */
+#define UART_FIFO_WDATA_OFFSET (0x88)
+#define UART_FIFO_WDATA        UART_FIFO_WDATA
+#define UART_FIFO_WDATA_POS    (0U)
+#define UART_FIFO_WDATA_LEN    (8U)
+#define UART_FIFO_WDATA_MSK    (((1U << UART_FIFO_WDATA_LEN) - 1) << UART_FIFO_WDATA_POS)
+#define UART_FIFO_WDATA_UMSK   (~(((1U << UART_FIFO_WDATA_LEN) - 1) << UART_FIFO_WDATA_POS))
+
+/* 0x8C : uart_fifo_rdata */
+#define UART_FIFO_RDATA_OFFSET (0x8C)
+#define UART_FIFO_RDATA        UART_FIFO_RDATA
+#define UART_FIFO_RDATA_POS    (0U)
+#define UART_FIFO_RDATA_LEN    (8U)
+#define UART_FIFO_RDATA_MSK    (((1U << UART_FIFO_RDATA_LEN) - 1) << UART_FIFO_RDATA_POS)
+#define UART_FIFO_RDATA_UMSK   (~(((1U << UART_FIFO_RDATA_LEN) - 1) << UART_FIFO_RDATA_POS))
+
+struct uart_reg {
+    /* 0x0 : utx_config */
+    union {
+        struct
+        {
+            uint32_t cr_utx_en        : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t cr_utx_cts_en    : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t cr_utx_frm_en    : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t cr_utx_lin_en    : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t cr_utx_prt_en    : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t cr_utx_prt_sel   : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t cr_utx_ir_en     : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t cr_utx_ir_inv    : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t cr_utx_bit_cnt_d : 3;  /* [10: 8],        r/w,        0x7 */
+            uint32_t cr_utx_bit_cnt_p : 2;  /* [12:11],        r/w,        0x1 */
+            uint32_t cr_utx_bit_cnt_b : 3;  /* [15:13],        r/w,        0x4 */
+            uint32_t cr_utx_len       : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } utx_config;
+
+    /* 0x4 : urx_config */
+    union {
+        struct
+        {
+            uint32_t cr_urx_en        : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t cr_urx_abr_en    : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2       : 1;  /* [    2],       rsvd,        0x0 */
+            uint32_t cr_urx_lin_en    : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t cr_urx_prt_en    : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t cr_urx_prt_sel   : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t cr_urx_ir_en     : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t cr_urx_ir_inv    : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t cr_urx_bit_cnt_d : 3;  /* [10: 8],        r/w,        0x7 */
+            uint32_t cr_urx_deg_en    : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t cr_urx_deg_cnt   : 4;  /* [15:12],        r/w,        0x0 */
+            uint32_t cr_urx_len       : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } urx_config;
+
+    /* 0x8 : uart_bit_prd */
+    union {
+        struct
+        {
+            uint32_t cr_utx_bit_prd : 16; /* [15: 0],        r/w,       0xff */
+            uint32_t cr_urx_bit_prd : 16; /* [31:16],        r/w,       0xff */
+        } BF;
+        uint32_t WORD;
+    } uart_bit_prd;
+
+    /* 0xC : data_config */
+    union {
+        struct
+        {
+            uint32_t cr_uart_bit_inv : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_31   : 31; /* [31: 1],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } data_config;
+
+    /* 0x10 : utx_ir_position */
+    union {
+        struct
+        {
+            uint32_t cr_utx_ir_pos_s : 16; /* [15: 0],        r/w,       0x70 */
+            uint32_t cr_utx_ir_pos_p : 16; /* [31:16],        r/w,       0x9f */
+        } BF;
+        uint32_t WORD;
+    } utx_ir_position;
+
+    /* 0x14 : urx_ir_position */
+    union {
+        struct
+        {
+            uint32_t cr_urx_ir_pos_s : 16; /* [15: 0],        r/w,       0x6f */
+            uint32_t reserved_16_31  : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } urx_ir_position;
+
+    /* 0x18 : urx_rto_timer */
+    union {
+        struct
+        {
+            uint32_t cr_urx_rto_value : 8;  /* [ 7: 0],        r/w,        0xf */
+            uint32_t reserved_8_31    : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } urx_rto_timer;
+
+    /* 0x1C : uart_sw_mode */
+    union {
+        struct
+        {
+            uint32_t cr_utx_txd_sw_mode : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t cr_utx_txd_sw_val  : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t cr_urx_rts_sw_mode : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t cr_urx_rts_sw_val  : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t reserved_4_31      : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } uart_sw_mode;
+
+    /* 0x20 : UART interrupt status */
+    union {
+        struct
+        {
+            uint32_t utx_end_int   : 1;  /* [    0],          r,        0x0 */
+            uint32_t urx_end_int   : 1;  /* [    1],          r,        0x0 */
+            uint32_t utx_fifo_int  : 1;  /* [    2],          r,        0x0 */
+            uint32_t urx_fifo_int  : 1;  /* [    3],          r,        0x0 */
+            uint32_t urx_rto_int   : 1;  /* [    4],          r,        0x0 */
+            uint32_t urx_pce_int   : 1;  /* [    5],          r,        0x0 */
+            uint32_t utx_fer_int   : 1;  /* [    6],          r,        0x0 */
+            uint32_t urx_fer_int   : 1;  /* [    7],          r,        0x0 */
+            uint32_t urx_lse_int   : 1;  /* [    8],          r,        0x0 */
+            uint32_t reserved_9_31 : 23; /* [31: 9],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } uart_int_sts;
+
+    /* 0x24 : UART interrupt mask */
+    union {
+        struct
+        {
+            uint32_t cr_utx_end_mask  : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t cr_urx_end_mask  : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t cr_utx_fifo_mask : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t cr_urx_fifo_mask : 1;  /* [    3],        r/w,        0x1 */
+            uint32_t cr_urx_rto_mask  : 1;  /* [    4],        r/w,        0x1 */
+            uint32_t cr_urx_pce_mask  : 1;  /* [    5],        r/w,        0x1 */
+            uint32_t cr_utx_fer_mask  : 1;  /* [    6],        r/w,        0x1 */
+            uint32_t cr_urx_fer_mask  : 1;  /* [    7],        r/w,        0x1 */
+            uint32_t cr_urx_lse_mask  : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t reserved_9_31    : 23; /* [31: 9],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } uart_int_mask;
+
+    /* 0x28 : UART interrupt clear */
+    union {
+        struct
+        {
+            uint32_t cr_utx_end_clr : 1;  /* [    0],        w1c,        0x0 */
+            uint32_t cr_urx_end_clr : 1;  /* [    1],        w1c,        0x0 */
+            uint32_t rsvd_2         : 1;  /* [    2],       rsvd,        0x0 */
+            uint32_t rsvd_3         : 1;  /* [    3],       rsvd,        0x0 */
+            uint32_t cr_urx_rto_clr : 1;  /* [    4],        w1c,        0x0 */
+            uint32_t cr_urx_pce_clr : 1;  /* [    5],        w1c,        0x0 */
+            uint32_t rsvd_6         : 1;  /* [    6],       rsvd,        0x0 */
+            uint32_t rsvd_7         : 1;  /* [    7],       rsvd,        0x0 */
+            uint32_t cr_urx_lse_clr : 1;  /* [    8],        w1c,        0x0 */
+            uint32_t reserved_9_31  : 23; /* [31: 9],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } uart_int_clear;
+
+    /* 0x2C : UART interrupt enable */
+    union {
+        struct
+        {
+            uint32_t cr_utx_end_en  : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t cr_urx_end_en  : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t cr_utx_fifo_en : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t cr_urx_fifo_en : 1;  /* [    3],        r/w,        0x1 */
+            uint32_t cr_urx_rto_en  : 1;  /* [    4],        r/w,        0x1 */
+            uint32_t cr_urx_pce_en  : 1;  /* [    5],        r/w,        0x1 */
+            uint32_t cr_utx_fer_en  : 1;  /* [    6],        r/w,        0x1 */
+            uint32_t cr_urx_fer_en  : 1;  /* [    7],        r/w,        0x1 */
+            uint32_t cr_urx_lse_en  : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t reserved_9_31  : 23; /* [31: 9],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } uart_int_en;
+
+    /* 0x30 : uart_status */
+    union {
+        struct
+        {
+            uint32_t sts_utx_bus_busy : 1;  /* [    0],          r,        0x0 */
+            uint32_t sts_urx_bus_busy : 1;  /* [    1],          r,        0x0 */
+            uint32_t reserved_2_31    : 30; /* [31: 2],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } uart_status;
+
+    /* 0x34 : sts_urx_abr_prd */
+    union {
+        struct
+        {
+            uint32_t sts_urx_abr_prd_start : 16; /* [15: 0],          r,        0x0 */
+            uint32_t sts_urx_abr_prd_0x55  : 16; /* [31:16],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sts_urx_abr_prd;
+
+    /* 0x38  reserved */
+    uint8_t RESERVED0x38[72];
+
+    /* 0x80 : uart_fifo_config_0 */
+    union {
+        struct
+        {
+            uint32_t uart_dma_tx_en    : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t uart_dma_rx_en    : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t tx_fifo_clr       : 1;  /* [    2],        w1c,        0x0 */
+            uint32_t rx_fifo_clr       : 1;  /* [    3],        w1c,        0x0 */
+            uint32_t tx_fifo_overflow  : 1;  /* [    4],          r,        0x0 */
+            uint32_t tx_fifo_underflow : 1;  /* [    5],          r,        0x0 */
+            uint32_t rx_fifo_overflow  : 1;  /* [    6],          r,        0x0 */
+            uint32_t rx_fifo_underflow : 1;  /* [    7],          r,        0x0 */
+            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } uart_fifo_config_0;
+
+    /* 0x84 : uart_fifo_config_1 */
+    union {
+        struct
+        {
+            uint32_t tx_fifo_cnt : 8; /* [ 7: 0],          r,       0x80 */
+            uint32_t rx_fifo_cnt : 8; /* [15: 8],          r,        0x0 */
+            uint32_t tx_fifo_th  : 7; /* [22:16],        r/w,        0x0 */
+            uint32_t reserved_23 : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t rx_fifo_th  : 7; /* [30:24],        r/w,        0x0 */
+            uint32_t reserved_31 : 1; /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } uart_fifo_config_1;
+
+    /* 0x88 : uart_fifo_wdata */
+    union {
+        struct
+        {
+            uint32_t uart_fifo_wdata : 8;  /* [ 7: 0],          w,          x */
+            uint32_t reserved_8_31   : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } uart_fifo_wdata;
+
+    /* 0x8C : uart_fifo_rdata */
+    union {
+        struct
+        {
+            uint32_t uart_fifo_rdata : 8;  /* [ 7: 0],          r,        0x0 */
+            uint32_t reserved_8_31   : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } uart_fifo_rdata;
+};
+
+typedef volatile struct uart_reg uart_reg_t;
+
+#endif /* __UART_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/usb_reg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/usb_reg.h
new file mode 100644
index 00000000..94120664
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/usb_reg.h
@@ -0,0 +1,2758 @@
+/**
+  ******************************************************************************
+  * @file    usb_reg.h
+  * @version V1.2
+  * @date    2020-09-04
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __USB_REG_H__
+#define __USB_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : usb_config */
+#define USB_CONFIG_OFFSET               (0x0)
+#define USB_CR_USB_EN                   USB_CR_USB_EN
+#define USB_CR_USB_EN_POS               (0U)
+#define USB_CR_USB_EN_LEN               (1U)
+#define USB_CR_USB_EN_MSK               (((1U << USB_CR_USB_EN_LEN) - 1) << USB_CR_USB_EN_POS)
+#define USB_CR_USB_EN_UMSK              (~(((1U << USB_CR_USB_EN_LEN) - 1) << USB_CR_USB_EN_POS))
+#define USB_CR_USB_ROM_DCT_EN           USB_CR_USB_ROM_DCT_EN
+#define USB_CR_USB_ROM_DCT_EN_POS       (4U)
+#define USB_CR_USB_ROM_DCT_EN_LEN       (1U)
+#define USB_CR_USB_ROM_DCT_EN_MSK       (((1U << USB_CR_USB_ROM_DCT_EN_LEN) - 1) << USB_CR_USB_ROM_DCT_EN_POS)
+#define USB_CR_USB_ROM_DCT_EN_UMSK      (~(((1U << USB_CR_USB_ROM_DCT_EN_LEN) - 1) << USB_CR_USB_ROM_DCT_EN_POS))
+#define USB_CR_USB_EP0_SW_CTRL          USB_CR_USB_EP0_SW_CTRL
+#define USB_CR_USB_EP0_SW_CTRL_POS      (8U)
+#define USB_CR_USB_EP0_SW_CTRL_LEN      (1U)
+#define USB_CR_USB_EP0_SW_CTRL_MSK      (((1U << USB_CR_USB_EP0_SW_CTRL_LEN) - 1) << USB_CR_USB_EP0_SW_CTRL_POS)
+#define USB_CR_USB_EP0_SW_CTRL_UMSK     (~(((1U << USB_CR_USB_EP0_SW_CTRL_LEN) - 1) << USB_CR_USB_EP0_SW_CTRL_POS))
+#define USB_CR_USB_EP0_SW_ADDR          USB_CR_USB_EP0_SW_ADDR
+#define USB_CR_USB_EP0_SW_ADDR_POS      (9U)
+#define USB_CR_USB_EP0_SW_ADDR_LEN      (7U)
+#define USB_CR_USB_EP0_SW_ADDR_MSK      (((1U << USB_CR_USB_EP0_SW_ADDR_LEN) - 1) << USB_CR_USB_EP0_SW_ADDR_POS)
+#define USB_CR_USB_EP0_SW_ADDR_UMSK     (~(((1U << USB_CR_USB_EP0_SW_ADDR_LEN) - 1) << USB_CR_USB_EP0_SW_ADDR_POS))
+#define USB_CR_USB_EP0_SW_SIZE          USB_CR_USB_EP0_SW_SIZE
+#define USB_CR_USB_EP0_SW_SIZE_POS      (16U)
+#define USB_CR_USB_EP0_SW_SIZE_LEN      (8U)
+#define USB_CR_USB_EP0_SW_SIZE_MSK      (((1U << USB_CR_USB_EP0_SW_SIZE_LEN) - 1) << USB_CR_USB_EP0_SW_SIZE_POS)
+#define USB_CR_USB_EP0_SW_SIZE_UMSK     (~(((1U << USB_CR_USB_EP0_SW_SIZE_LEN) - 1) << USB_CR_USB_EP0_SW_SIZE_POS))
+#define USB_CR_USB_EP0_SW_STALL         USB_CR_USB_EP0_SW_STALL
+#define USB_CR_USB_EP0_SW_STALL_POS     (24U)
+#define USB_CR_USB_EP0_SW_STALL_LEN     (1U)
+#define USB_CR_USB_EP0_SW_STALL_MSK     (((1U << USB_CR_USB_EP0_SW_STALL_LEN) - 1) << USB_CR_USB_EP0_SW_STALL_POS)
+#define USB_CR_USB_EP0_SW_STALL_UMSK    (~(((1U << USB_CR_USB_EP0_SW_STALL_LEN) - 1) << USB_CR_USB_EP0_SW_STALL_POS))
+#define USB_CR_USB_EP0_SW_NACK_IN       USB_CR_USB_EP0_SW_NACK_IN
+#define USB_CR_USB_EP0_SW_NACK_IN_POS   (25U)
+#define USB_CR_USB_EP0_SW_NACK_IN_LEN   (1U)
+#define USB_CR_USB_EP0_SW_NACK_IN_MSK   (((1U << USB_CR_USB_EP0_SW_NACK_IN_LEN) - 1) << USB_CR_USB_EP0_SW_NACK_IN_POS)
+#define USB_CR_USB_EP0_SW_NACK_IN_UMSK  (~(((1U << USB_CR_USB_EP0_SW_NACK_IN_LEN) - 1) << USB_CR_USB_EP0_SW_NACK_IN_POS))
+#define USB_CR_USB_EP0_SW_NACK_OUT      USB_CR_USB_EP0_SW_NACK_OUT
+#define USB_CR_USB_EP0_SW_NACK_OUT_POS  (26U)
+#define USB_CR_USB_EP0_SW_NACK_OUT_LEN  (1U)
+#define USB_CR_USB_EP0_SW_NACK_OUT_MSK  (((1U << USB_CR_USB_EP0_SW_NACK_OUT_LEN) - 1) << USB_CR_USB_EP0_SW_NACK_OUT_POS)
+#define USB_CR_USB_EP0_SW_NACK_OUT_UMSK (~(((1U << USB_CR_USB_EP0_SW_NACK_OUT_LEN) - 1) << USB_CR_USB_EP0_SW_NACK_OUT_POS))
+#define USB_CR_USB_EP0_SW_RDY           USB_CR_USB_EP0_SW_RDY
+#define USB_CR_USB_EP0_SW_RDY_POS       (27U)
+#define USB_CR_USB_EP0_SW_RDY_LEN       (1U)
+#define USB_CR_USB_EP0_SW_RDY_MSK       (((1U << USB_CR_USB_EP0_SW_RDY_LEN) - 1) << USB_CR_USB_EP0_SW_RDY_POS)
+#define USB_CR_USB_EP0_SW_RDY_UMSK      (~(((1U << USB_CR_USB_EP0_SW_RDY_LEN) - 1) << USB_CR_USB_EP0_SW_RDY_POS))
+#define USB_STS_USB_EP0_SW_RDY          USB_STS_USB_EP0_SW_RDY
+#define USB_STS_USB_EP0_SW_RDY_POS      (28U)
+#define USB_STS_USB_EP0_SW_RDY_LEN      (1U)
+#define USB_STS_USB_EP0_SW_RDY_MSK      (((1U << USB_STS_USB_EP0_SW_RDY_LEN) - 1) << USB_STS_USB_EP0_SW_RDY_POS)
+#define USB_STS_USB_EP0_SW_RDY_UMSK     (~(((1U << USB_STS_USB_EP0_SW_RDY_LEN) - 1) << USB_STS_USB_EP0_SW_RDY_POS))
+
+/* 0x4 : usb_lpm_config */
+#define USB_LPM_CONFIG_OFFSET    (0x4)
+#define USB_CR_LPM_EN            USB_CR_LPM_EN
+#define USB_CR_LPM_EN_POS        (0U)
+#define USB_CR_LPM_EN_LEN        (1U)
+#define USB_CR_LPM_EN_MSK        (((1U << USB_CR_LPM_EN_LEN) - 1) << USB_CR_LPM_EN_POS)
+#define USB_CR_LPM_EN_UMSK       (~(((1U << USB_CR_LPM_EN_LEN) - 1) << USB_CR_LPM_EN_POS))
+#define USB_CR_LPM_RESP_UPD      USB_CR_LPM_RESP_UPD
+#define USB_CR_LPM_RESP_UPD_POS  (1U)
+#define USB_CR_LPM_RESP_UPD_LEN  (1U)
+#define USB_CR_LPM_RESP_UPD_MSK  (((1U << USB_CR_LPM_RESP_UPD_LEN) - 1) << USB_CR_LPM_RESP_UPD_POS)
+#define USB_CR_LPM_RESP_UPD_UMSK (~(((1U << USB_CR_LPM_RESP_UPD_LEN) - 1) << USB_CR_LPM_RESP_UPD_POS))
+#define USB_CR_LPM_RESP          USB_CR_LPM_RESP
+#define USB_CR_LPM_RESP_POS      (2U)
+#define USB_CR_LPM_RESP_LEN      (2U)
+#define USB_CR_LPM_RESP_MSK      (((1U << USB_CR_LPM_RESP_LEN) - 1) << USB_CR_LPM_RESP_POS)
+#define USB_CR_LPM_RESP_UMSK     (~(((1U << USB_CR_LPM_RESP_LEN) - 1) << USB_CR_LPM_RESP_POS))
+#define USB_STS_LPM_ATTR         USB_STS_LPM_ATTR
+#define USB_STS_LPM_ATTR_POS     (20U)
+#define USB_STS_LPM_ATTR_LEN     (11U)
+#define USB_STS_LPM_ATTR_MSK     (((1U << USB_STS_LPM_ATTR_LEN) - 1) << USB_STS_LPM_ATTR_POS)
+#define USB_STS_LPM_ATTR_UMSK    (~(((1U << USB_STS_LPM_ATTR_LEN) - 1) << USB_STS_LPM_ATTR_POS))
+#define USB_STS_LPM              USB_STS_LPM
+#define USB_STS_LPM_POS          (31U)
+#define USB_STS_LPM_LEN          (1U)
+#define USB_STS_LPM_MSK          (((1U << USB_STS_LPM_LEN) - 1) << USB_STS_LPM_POS)
+#define USB_STS_LPM_UMSK         (~(((1U << USB_STS_LPM_LEN) - 1) << USB_STS_LPM_POS))
+
+/* 0x8 : usb_resume_config */
+#define USB_RESUME_CONFIG_OFFSET (0x8)
+#define USB_CR_RES_WIDTH         USB_CR_RES_WIDTH
+#define USB_CR_RES_WIDTH_POS     (0U)
+#define USB_CR_RES_WIDTH_LEN     (11U)
+#define USB_CR_RES_WIDTH_MSK     (((1U << USB_CR_RES_WIDTH_LEN) - 1) << USB_CR_RES_WIDTH_POS)
+#define USB_CR_RES_WIDTH_UMSK    (~(((1U << USB_CR_RES_WIDTH_LEN) - 1) << USB_CR_RES_WIDTH_POS))
+#define USB_CR_RES_TRIG          USB_CR_RES_TRIG
+#define USB_CR_RES_TRIG_POS      (12U)
+#define USB_CR_RES_TRIG_LEN      (1U)
+#define USB_CR_RES_TRIG_MSK      (((1U << USB_CR_RES_TRIG_LEN) - 1) << USB_CR_RES_TRIG_POS)
+#define USB_CR_RES_TRIG_UMSK     (~(((1U << USB_CR_RES_TRIG_LEN) - 1) << USB_CR_RES_TRIG_POS))
+#define USB_CR_RES_FORCE         USB_CR_RES_FORCE
+#define USB_CR_RES_FORCE_POS     (31U)
+#define USB_CR_RES_FORCE_LEN     (1U)
+#define USB_CR_RES_FORCE_MSK     (((1U << USB_CR_RES_FORCE_LEN) - 1) << USB_CR_RES_FORCE_POS)
+#define USB_CR_RES_FORCE_UMSK    (~(((1U << USB_CR_RES_FORCE_LEN) - 1) << USB_CR_RES_FORCE_POS))
+
+/* 0x10 : usb_setup_data_0 */
+#define USB_SETUP_DATA_0_OFFSET    (0x10)
+#define USB_STS_SETUP_DATA_B0      USB_STS_SETUP_DATA_B0
+#define USB_STS_SETUP_DATA_B0_POS  (0U)
+#define USB_STS_SETUP_DATA_B0_LEN  (8U)
+#define USB_STS_SETUP_DATA_B0_MSK  (((1U << USB_STS_SETUP_DATA_B0_LEN) - 1) << USB_STS_SETUP_DATA_B0_POS)
+#define USB_STS_SETUP_DATA_B0_UMSK (~(((1U << USB_STS_SETUP_DATA_B0_LEN) - 1) << USB_STS_SETUP_DATA_B0_POS))
+#define USB_STS_SETUP_DATA_B1      USB_STS_SETUP_DATA_B1
+#define USB_STS_SETUP_DATA_B1_POS  (8U)
+#define USB_STS_SETUP_DATA_B1_LEN  (8U)
+#define USB_STS_SETUP_DATA_B1_MSK  (((1U << USB_STS_SETUP_DATA_B1_LEN) - 1) << USB_STS_SETUP_DATA_B1_POS)
+#define USB_STS_SETUP_DATA_B1_UMSK (~(((1U << USB_STS_SETUP_DATA_B1_LEN) - 1) << USB_STS_SETUP_DATA_B1_POS))
+#define USB_STS_SETUP_DATA_B2      USB_STS_SETUP_DATA_B2
+#define USB_STS_SETUP_DATA_B2_POS  (16U)
+#define USB_STS_SETUP_DATA_B2_LEN  (8U)
+#define USB_STS_SETUP_DATA_B2_MSK  (((1U << USB_STS_SETUP_DATA_B2_LEN) - 1) << USB_STS_SETUP_DATA_B2_POS)
+#define USB_STS_SETUP_DATA_B2_UMSK (~(((1U << USB_STS_SETUP_DATA_B2_LEN) - 1) << USB_STS_SETUP_DATA_B2_POS))
+#define USB_STS_SETUP_DATA_B3      USB_STS_SETUP_DATA_B3
+#define USB_STS_SETUP_DATA_B3_POS  (24U)
+#define USB_STS_SETUP_DATA_B3_LEN  (8U)
+#define USB_STS_SETUP_DATA_B3_MSK  (((1U << USB_STS_SETUP_DATA_B3_LEN) - 1) << USB_STS_SETUP_DATA_B3_POS)
+#define USB_STS_SETUP_DATA_B3_UMSK (~(((1U << USB_STS_SETUP_DATA_B3_LEN) - 1) << USB_STS_SETUP_DATA_B3_POS))
+
+/* 0x14 : usb_setup_data_1 */
+#define USB_SETUP_DATA_1_OFFSET    (0x14)
+#define USB_STS_SETUP_DATA_B4      USB_STS_SETUP_DATA_B4
+#define USB_STS_SETUP_DATA_B4_POS  (0U)
+#define USB_STS_SETUP_DATA_B4_LEN  (8U)
+#define USB_STS_SETUP_DATA_B4_MSK  (((1U << USB_STS_SETUP_DATA_B4_LEN) - 1) << USB_STS_SETUP_DATA_B4_POS)
+#define USB_STS_SETUP_DATA_B4_UMSK (~(((1U << USB_STS_SETUP_DATA_B4_LEN) - 1) << USB_STS_SETUP_DATA_B4_POS))
+#define USB_STS_SETUP_DATA_B5      USB_STS_SETUP_DATA_B5
+#define USB_STS_SETUP_DATA_B5_POS  (8U)
+#define USB_STS_SETUP_DATA_B5_LEN  (8U)
+#define USB_STS_SETUP_DATA_B5_MSK  (((1U << USB_STS_SETUP_DATA_B5_LEN) - 1) << USB_STS_SETUP_DATA_B5_POS)
+#define USB_STS_SETUP_DATA_B5_UMSK (~(((1U << USB_STS_SETUP_DATA_B5_LEN) - 1) << USB_STS_SETUP_DATA_B5_POS))
+#define USB_STS_SETUP_DATA_B6      USB_STS_SETUP_DATA_B6
+#define USB_STS_SETUP_DATA_B6_POS  (16U)
+#define USB_STS_SETUP_DATA_B6_LEN  (8U)
+#define USB_STS_SETUP_DATA_B6_MSK  (((1U << USB_STS_SETUP_DATA_B6_LEN) - 1) << USB_STS_SETUP_DATA_B6_POS)
+#define USB_STS_SETUP_DATA_B6_UMSK (~(((1U << USB_STS_SETUP_DATA_B6_LEN) - 1) << USB_STS_SETUP_DATA_B6_POS))
+#define USB_STS_SETUP_DATA_B7      USB_STS_SETUP_DATA_B7
+#define USB_STS_SETUP_DATA_B7_POS  (24U)
+#define USB_STS_SETUP_DATA_B7_LEN  (8U)
+#define USB_STS_SETUP_DATA_B7_MSK  (((1U << USB_STS_SETUP_DATA_B7_LEN) - 1) << USB_STS_SETUP_DATA_B7_POS)
+#define USB_STS_SETUP_DATA_B7_UMSK (~(((1U << USB_STS_SETUP_DATA_B7_LEN) - 1) << USB_STS_SETUP_DATA_B7_POS))
+
+/* 0x18 : usb_frame_no */
+#define USB_FRAME_NO_OFFSET   (0x18)
+#define USB_STS_FRAME_NO      USB_STS_FRAME_NO
+#define USB_STS_FRAME_NO_POS  (0U)
+#define USB_STS_FRAME_NO_LEN  (11U)
+#define USB_STS_FRAME_NO_MSK  (((1U << USB_STS_FRAME_NO_LEN) - 1) << USB_STS_FRAME_NO_POS)
+#define USB_STS_FRAME_NO_UMSK (~(((1U << USB_STS_FRAME_NO_LEN) - 1) << USB_STS_FRAME_NO_POS))
+#define USB_STS_PID           USB_STS_PID
+#define USB_STS_PID_POS       (12U)
+#define USB_STS_PID_LEN       (4U)
+#define USB_STS_PID_MSK       (((1U << USB_STS_PID_LEN) - 1) << USB_STS_PID_POS)
+#define USB_STS_PID_UMSK      (~(((1U << USB_STS_PID_LEN) - 1) << USB_STS_PID_POS))
+#define USB_STS_EP_NO         USB_STS_EP_NO
+#define USB_STS_EP_NO_POS     (16U)
+#define USB_STS_EP_NO_LEN     (4U)
+#define USB_STS_EP_NO_MSK     (((1U << USB_STS_EP_NO_LEN) - 1) << USB_STS_EP_NO_POS)
+#define USB_STS_EP_NO_UMSK    (~(((1U << USB_STS_EP_NO_LEN) - 1) << USB_STS_EP_NO_POS))
+
+/* 0x1C : usb_error */
+#define USB_ERROR_OFFSET     (0x1C)
+#define USB_UTMI_RX_ERR      USB_UTMI_RX_ERR
+#define USB_UTMI_RX_ERR_POS  (0U)
+#define USB_UTMI_RX_ERR_LEN  (1U)
+#define USB_UTMI_RX_ERR_MSK  (((1U << USB_UTMI_RX_ERR_LEN) - 1) << USB_UTMI_RX_ERR_POS)
+#define USB_UTMI_RX_ERR_UMSK (~(((1U << USB_UTMI_RX_ERR_LEN) - 1) << USB_UTMI_RX_ERR_POS))
+#define USB_XFER_TO_ERR      USB_XFER_TO_ERR
+#define USB_XFER_TO_ERR_POS  (1U)
+#define USB_XFER_TO_ERR_LEN  (1U)
+#define USB_XFER_TO_ERR_MSK  (((1U << USB_XFER_TO_ERR_LEN) - 1) << USB_XFER_TO_ERR_POS)
+#define USB_XFER_TO_ERR_UMSK (~(((1U << USB_XFER_TO_ERR_LEN) - 1) << USB_XFER_TO_ERR_POS))
+#define USB_IVLD_EP_ERR      USB_IVLD_EP_ERR
+#define USB_IVLD_EP_ERR_POS  (2U)
+#define USB_IVLD_EP_ERR_LEN  (1U)
+#define USB_IVLD_EP_ERR_MSK  (((1U << USB_IVLD_EP_ERR_LEN) - 1) << USB_IVLD_EP_ERR_POS)
+#define USB_IVLD_EP_ERR_UMSK (~(((1U << USB_IVLD_EP_ERR_LEN) - 1) << USB_IVLD_EP_ERR_POS))
+#define USB_PID_SEQ_ERR      USB_PID_SEQ_ERR
+#define USB_PID_SEQ_ERR_POS  (3U)
+#define USB_PID_SEQ_ERR_LEN  (1U)
+#define USB_PID_SEQ_ERR_MSK  (((1U << USB_PID_SEQ_ERR_LEN) - 1) << USB_PID_SEQ_ERR_POS)
+#define USB_PID_SEQ_ERR_UMSK (~(((1U << USB_PID_SEQ_ERR_LEN) - 1) << USB_PID_SEQ_ERR_POS))
+#define USB_PID_CKS_ERR      USB_PID_CKS_ERR
+#define USB_PID_CKS_ERR_POS  (4U)
+#define USB_PID_CKS_ERR_LEN  (1U)
+#define USB_PID_CKS_ERR_MSK  (((1U << USB_PID_CKS_ERR_LEN) - 1) << USB_PID_CKS_ERR_POS)
+#define USB_PID_CKS_ERR_UMSK (~(((1U << USB_PID_CKS_ERR_LEN) - 1) << USB_PID_CKS_ERR_POS))
+#define USB_CRC5_ERR         USB_CRC5_ERR
+#define USB_CRC5_ERR_POS     (5U)
+#define USB_CRC5_ERR_LEN     (1U)
+#define USB_CRC5_ERR_MSK     (((1U << USB_CRC5_ERR_LEN) - 1) << USB_CRC5_ERR_POS)
+#define USB_CRC5_ERR_UMSK    (~(((1U << USB_CRC5_ERR_LEN) - 1) << USB_CRC5_ERR_POS))
+#define USB_CRC16_ERR        USB_CRC16_ERR
+#define USB_CRC16_ERR_POS    (6U)
+#define USB_CRC16_ERR_LEN    (1U)
+#define USB_CRC16_ERR_MSK    (((1U << USB_CRC16_ERR_LEN) - 1) << USB_CRC16_ERR_POS)
+#define USB_CRC16_ERR_UMSK   (~(((1U << USB_CRC16_ERR_LEN) - 1) << USB_CRC16_ERR_POS))
+
+/* 0x20 : USB interrupt enable */
+#define USB_INT_EN_OFFSET             (0x20)
+#define USB_CR_SOF_EN                 USB_CR_SOF_EN
+#define USB_CR_SOF_EN_POS             (0U)
+#define USB_CR_SOF_EN_LEN             (1U)
+#define USB_CR_SOF_EN_MSK             (((1U << USB_CR_SOF_EN_LEN) - 1) << USB_CR_SOF_EN_POS)
+#define USB_CR_SOF_EN_UMSK            (~(((1U << USB_CR_SOF_EN_LEN) - 1) << USB_CR_SOF_EN_POS))
+#define USB_CR_USB_RESET_EN           USB_CR_USB_RESET_EN
+#define USB_CR_USB_RESET_EN_POS       (1U)
+#define USB_CR_USB_RESET_EN_LEN       (1U)
+#define USB_CR_USB_RESET_EN_MSK       (((1U << USB_CR_USB_RESET_EN_LEN) - 1) << USB_CR_USB_RESET_EN_POS)
+#define USB_CR_USB_RESET_EN_UMSK      (~(((1U << USB_CR_USB_RESET_EN_LEN) - 1) << USB_CR_USB_RESET_EN_POS))
+#define USB_CR_VBUS_TGL_EN            USB_CR_VBUS_TGL_EN
+#define USB_CR_VBUS_TGL_EN_POS        (2U)
+#define USB_CR_VBUS_TGL_EN_LEN        (1U)
+#define USB_CR_VBUS_TGL_EN_MSK        (((1U << USB_CR_VBUS_TGL_EN_LEN) - 1) << USB_CR_VBUS_TGL_EN_POS)
+#define USB_CR_VBUS_TGL_EN_UMSK       (~(((1U << USB_CR_VBUS_TGL_EN_LEN) - 1) << USB_CR_VBUS_TGL_EN_POS))
+#define USB_CR_GET_DCT_CMD_EN         USB_CR_GET_DCT_CMD_EN
+#define USB_CR_GET_DCT_CMD_EN_POS     (3U)
+#define USB_CR_GET_DCT_CMD_EN_LEN     (1U)
+#define USB_CR_GET_DCT_CMD_EN_MSK     (((1U << USB_CR_GET_DCT_CMD_EN_LEN) - 1) << USB_CR_GET_DCT_CMD_EN_POS)
+#define USB_CR_GET_DCT_CMD_EN_UMSK    (~(((1U << USB_CR_GET_DCT_CMD_EN_LEN) - 1) << USB_CR_GET_DCT_CMD_EN_POS))
+#define USB_CR_EP0_SETUP_CMD_EN       USB_CR_EP0_SETUP_CMD_EN
+#define USB_CR_EP0_SETUP_CMD_EN_POS   (4U)
+#define USB_CR_EP0_SETUP_CMD_EN_LEN   (1U)
+#define USB_CR_EP0_SETUP_CMD_EN_MSK   (((1U << USB_CR_EP0_SETUP_CMD_EN_LEN) - 1) << USB_CR_EP0_SETUP_CMD_EN_POS)
+#define USB_CR_EP0_SETUP_CMD_EN_UMSK  (~(((1U << USB_CR_EP0_SETUP_CMD_EN_LEN) - 1) << USB_CR_EP0_SETUP_CMD_EN_POS))
+#define USB_CR_EP0_SETUP_DONE_EN      USB_CR_EP0_SETUP_DONE_EN
+#define USB_CR_EP0_SETUP_DONE_EN_POS  (5U)
+#define USB_CR_EP0_SETUP_DONE_EN_LEN  (1U)
+#define USB_CR_EP0_SETUP_DONE_EN_MSK  (((1U << USB_CR_EP0_SETUP_DONE_EN_LEN) - 1) << USB_CR_EP0_SETUP_DONE_EN_POS)
+#define USB_CR_EP0_SETUP_DONE_EN_UMSK (~(((1U << USB_CR_EP0_SETUP_DONE_EN_LEN) - 1) << USB_CR_EP0_SETUP_DONE_EN_POS))
+#define USB_CR_EP0_IN_CMD_EN          USB_CR_EP0_IN_CMD_EN
+#define USB_CR_EP0_IN_CMD_EN_POS      (6U)
+#define USB_CR_EP0_IN_CMD_EN_LEN      (1U)
+#define USB_CR_EP0_IN_CMD_EN_MSK      (((1U << USB_CR_EP0_IN_CMD_EN_LEN) - 1) << USB_CR_EP0_IN_CMD_EN_POS)
+#define USB_CR_EP0_IN_CMD_EN_UMSK     (~(((1U << USB_CR_EP0_IN_CMD_EN_LEN) - 1) << USB_CR_EP0_IN_CMD_EN_POS))
+#define USB_CR_EP0_IN_DONE_EN         USB_CR_EP0_IN_DONE_EN
+#define USB_CR_EP0_IN_DONE_EN_POS     (7U)
+#define USB_CR_EP0_IN_DONE_EN_LEN     (1U)
+#define USB_CR_EP0_IN_DONE_EN_MSK     (((1U << USB_CR_EP0_IN_DONE_EN_LEN) - 1) << USB_CR_EP0_IN_DONE_EN_POS)
+#define USB_CR_EP0_IN_DONE_EN_UMSK    (~(((1U << USB_CR_EP0_IN_DONE_EN_LEN) - 1) << USB_CR_EP0_IN_DONE_EN_POS))
+#define USB_CR_EP0_OUT_CMD_EN         USB_CR_EP0_OUT_CMD_EN
+#define USB_CR_EP0_OUT_CMD_EN_POS     (8U)
+#define USB_CR_EP0_OUT_CMD_EN_LEN     (1U)
+#define USB_CR_EP0_OUT_CMD_EN_MSK     (((1U << USB_CR_EP0_OUT_CMD_EN_LEN) - 1) << USB_CR_EP0_OUT_CMD_EN_POS)
+#define USB_CR_EP0_OUT_CMD_EN_UMSK    (~(((1U << USB_CR_EP0_OUT_CMD_EN_LEN) - 1) << USB_CR_EP0_OUT_CMD_EN_POS))
+#define USB_CR_EP0_OUT_DONE_EN        USB_CR_EP0_OUT_DONE_EN
+#define USB_CR_EP0_OUT_DONE_EN_POS    (9U)
+#define USB_CR_EP0_OUT_DONE_EN_LEN    (1U)
+#define USB_CR_EP0_OUT_DONE_EN_MSK    (((1U << USB_CR_EP0_OUT_DONE_EN_LEN) - 1) << USB_CR_EP0_OUT_DONE_EN_POS)
+#define USB_CR_EP0_OUT_DONE_EN_UMSK   (~(((1U << USB_CR_EP0_OUT_DONE_EN_LEN) - 1) << USB_CR_EP0_OUT_DONE_EN_POS))
+#define USB_CR_EP1_CMD_EN             USB_CR_EP1_CMD_EN
+#define USB_CR_EP1_CMD_EN_POS         (10U)
+#define USB_CR_EP1_CMD_EN_LEN         (1U)
+#define USB_CR_EP1_CMD_EN_MSK         (((1U << USB_CR_EP1_CMD_EN_LEN) - 1) << USB_CR_EP1_CMD_EN_POS)
+#define USB_CR_EP1_CMD_EN_UMSK        (~(((1U << USB_CR_EP1_CMD_EN_LEN) - 1) << USB_CR_EP1_CMD_EN_POS))
+#define USB_CR_EP1_DONE_EN            USB_CR_EP1_DONE_EN
+#define USB_CR_EP1_DONE_EN_POS        (11U)
+#define USB_CR_EP1_DONE_EN_LEN        (1U)
+#define USB_CR_EP1_DONE_EN_MSK        (((1U << USB_CR_EP1_DONE_EN_LEN) - 1) << USB_CR_EP1_DONE_EN_POS)
+#define USB_CR_EP1_DONE_EN_UMSK       (~(((1U << USB_CR_EP1_DONE_EN_LEN) - 1) << USB_CR_EP1_DONE_EN_POS))
+#define USB_CR_EP2_CMD_EN             USB_CR_EP2_CMD_EN
+#define USB_CR_EP2_CMD_EN_POS         (12U)
+#define USB_CR_EP2_CMD_EN_LEN         (1U)
+#define USB_CR_EP2_CMD_EN_MSK         (((1U << USB_CR_EP2_CMD_EN_LEN) - 1) << USB_CR_EP2_CMD_EN_POS)
+#define USB_CR_EP2_CMD_EN_UMSK        (~(((1U << USB_CR_EP2_CMD_EN_LEN) - 1) << USB_CR_EP2_CMD_EN_POS))
+#define USB_CR_EP2_DONE_EN            USB_CR_EP2_DONE_EN
+#define USB_CR_EP2_DONE_EN_POS        (13U)
+#define USB_CR_EP2_DONE_EN_LEN        (1U)
+#define USB_CR_EP2_DONE_EN_MSK        (((1U << USB_CR_EP2_DONE_EN_LEN) - 1) << USB_CR_EP2_DONE_EN_POS)
+#define USB_CR_EP2_DONE_EN_UMSK       (~(((1U << USB_CR_EP2_DONE_EN_LEN) - 1) << USB_CR_EP2_DONE_EN_POS))
+#define USB_CR_EP3_CMD_EN             USB_CR_EP3_CMD_EN
+#define USB_CR_EP3_CMD_EN_POS         (14U)
+#define USB_CR_EP3_CMD_EN_LEN         (1U)
+#define USB_CR_EP3_CMD_EN_MSK         (((1U << USB_CR_EP3_CMD_EN_LEN) - 1) << USB_CR_EP3_CMD_EN_POS)
+#define USB_CR_EP3_CMD_EN_UMSK        (~(((1U << USB_CR_EP3_CMD_EN_LEN) - 1) << USB_CR_EP3_CMD_EN_POS))
+#define USB_CR_EP3_DONE_EN            USB_CR_EP3_DONE_EN
+#define USB_CR_EP3_DONE_EN_POS        (15U)
+#define USB_CR_EP3_DONE_EN_LEN        (1U)
+#define USB_CR_EP3_DONE_EN_MSK        (((1U << USB_CR_EP3_DONE_EN_LEN) - 1) << USB_CR_EP3_DONE_EN_POS)
+#define USB_CR_EP3_DONE_EN_UMSK       (~(((1U << USB_CR_EP3_DONE_EN_LEN) - 1) << USB_CR_EP3_DONE_EN_POS))
+#define USB_CR_EP4_CMD_EN             USB_CR_EP4_CMD_EN
+#define USB_CR_EP4_CMD_EN_POS         (16U)
+#define USB_CR_EP4_CMD_EN_LEN         (1U)
+#define USB_CR_EP4_CMD_EN_MSK         (((1U << USB_CR_EP4_CMD_EN_LEN) - 1) << USB_CR_EP4_CMD_EN_POS)
+#define USB_CR_EP4_CMD_EN_UMSK        (~(((1U << USB_CR_EP4_CMD_EN_LEN) - 1) << USB_CR_EP4_CMD_EN_POS))
+#define USB_CR_EP4_DONE_EN            USB_CR_EP4_DONE_EN
+#define USB_CR_EP4_DONE_EN_POS        (17U)
+#define USB_CR_EP4_DONE_EN_LEN        (1U)
+#define USB_CR_EP4_DONE_EN_MSK        (((1U << USB_CR_EP4_DONE_EN_LEN) - 1) << USB_CR_EP4_DONE_EN_POS)
+#define USB_CR_EP4_DONE_EN_UMSK       (~(((1U << USB_CR_EP4_DONE_EN_LEN) - 1) << USB_CR_EP4_DONE_EN_POS))
+#define USB_CR_EP5_CMD_EN             USB_CR_EP5_CMD_EN
+#define USB_CR_EP5_CMD_EN_POS         (18U)
+#define USB_CR_EP5_CMD_EN_LEN         (1U)
+#define USB_CR_EP5_CMD_EN_MSK         (((1U << USB_CR_EP5_CMD_EN_LEN) - 1) << USB_CR_EP5_CMD_EN_POS)
+#define USB_CR_EP5_CMD_EN_UMSK        (~(((1U << USB_CR_EP5_CMD_EN_LEN) - 1) << USB_CR_EP5_CMD_EN_POS))
+#define USB_CR_EP5_DONE_EN            USB_CR_EP5_DONE_EN
+#define USB_CR_EP5_DONE_EN_POS        (19U)
+#define USB_CR_EP5_DONE_EN_LEN        (1U)
+#define USB_CR_EP5_DONE_EN_MSK        (((1U << USB_CR_EP5_DONE_EN_LEN) - 1) << USB_CR_EP5_DONE_EN_POS)
+#define USB_CR_EP5_DONE_EN_UMSK       (~(((1U << USB_CR_EP5_DONE_EN_LEN) - 1) << USB_CR_EP5_DONE_EN_POS))
+#define USB_CR_EP6_CMD_EN             USB_CR_EP6_CMD_EN
+#define USB_CR_EP6_CMD_EN_POS         (20U)
+#define USB_CR_EP6_CMD_EN_LEN         (1U)
+#define USB_CR_EP6_CMD_EN_MSK         (((1U << USB_CR_EP6_CMD_EN_LEN) - 1) << USB_CR_EP6_CMD_EN_POS)
+#define USB_CR_EP6_CMD_EN_UMSK        (~(((1U << USB_CR_EP6_CMD_EN_LEN) - 1) << USB_CR_EP6_CMD_EN_POS))
+#define USB_CR_EP6_DONE_EN            USB_CR_EP6_DONE_EN
+#define USB_CR_EP6_DONE_EN_POS        (21U)
+#define USB_CR_EP6_DONE_EN_LEN        (1U)
+#define USB_CR_EP6_DONE_EN_MSK        (((1U << USB_CR_EP6_DONE_EN_LEN) - 1) << USB_CR_EP6_DONE_EN_POS)
+#define USB_CR_EP6_DONE_EN_UMSK       (~(((1U << USB_CR_EP6_DONE_EN_LEN) - 1) << USB_CR_EP6_DONE_EN_POS))
+#define USB_CR_EP7_CMD_EN             USB_CR_EP7_CMD_EN
+#define USB_CR_EP7_CMD_EN_POS         (22U)
+#define USB_CR_EP7_CMD_EN_LEN         (1U)
+#define USB_CR_EP7_CMD_EN_MSK         (((1U << USB_CR_EP7_CMD_EN_LEN) - 1) << USB_CR_EP7_CMD_EN_POS)
+#define USB_CR_EP7_CMD_EN_UMSK        (~(((1U << USB_CR_EP7_CMD_EN_LEN) - 1) << USB_CR_EP7_CMD_EN_POS))
+#define USB_CR_EP7_DONE_EN            USB_CR_EP7_DONE_EN
+#define USB_CR_EP7_DONE_EN_POS        (23U)
+#define USB_CR_EP7_DONE_EN_LEN        (1U)
+#define USB_CR_EP7_DONE_EN_MSK        (((1U << USB_CR_EP7_DONE_EN_LEN) - 1) << USB_CR_EP7_DONE_EN_POS)
+#define USB_CR_EP7_DONE_EN_UMSK       (~(((1U << USB_CR_EP7_DONE_EN_LEN) - 1) << USB_CR_EP7_DONE_EN_POS))
+#define USB_CR_USB_REND_EN            USB_CR_USB_REND_EN
+#define USB_CR_USB_REND_EN_POS        (27U)
+#define USB_CR_USB_REND_EN_LEN        (1U)
+#define USB_CR_USB_REND_EN_MSK        (((1U << USB_CR_USB_REND_EN_LEN) - 1) << USB_CR_USB_REND_EN_POS)
+#define USB_CR_USB_REND_EN_UMSK       (~(((1U << USB_CR_USB_REND_EN_LEN) - 1) << USB_CR_USB_REND_EN_POS))
+#define USB_CR_LPM_WKUP_EN            USB_CR_LPM_WKUP_EN
+#define USB_CR_LPM_WKUP_EN_POS        (28U)
+#define USB_CR_LPM_WKUP_EN_LEN        (1U)
+#define USB_CR_LPM_WKUP_EN_MSK        (((1U << USB_CR_LPM_WKUP_EN_LEN) - 1) << USB_CR_LPM_WKUP_EN_POS)
+#define USB_CR_LPM_WKUP_EN_UMSK       (~(((1U << USB_CR_LPM_WKUP_EN_LEN) - 1) << USB_CR_LPM_WKUP_EN_POS))
+#define USB_CR_LPM_PKT_EN             USB_CR_LPM_PKT_EN
+#define USB_CR_LPM_PKT_EN_POS         (29U)
+#define USB_CR_LPM_PKT_EN_LEN         (1U)
+#define USB_CR_LPM_PKT_EN_MSK         (((1U << USB_CR_LPM_PKT_EN_LEN) - 1) << USB_CR_LPM_PKT_EN_POS)
+#define USB_CR_LPM_PKT_EN_UMSK        (~(((1U << USB_CR_LPM_PKT_EN_LEN) - 1) << USB_CR_LPM_PKT_EN_POS))
+#define USB_CR_SOF_3MS_EN             USB_CR_SOF_3MS_EN
+#define USB_CR_SOF_3MS_EN_POS         (30U)
+#define USB_CR_SOF_3MS_EN_LEN         (1U)
+#define USB_CR_SOF_3MS_EN_MSK         (((1U << USB_CR_SOF_3MS_EN_LEN) - 1) << USB_CR_SOF_3MS_EN_POS)
+#define USB_CR_SOF_3MS_EN_UMSK        (~(((1U << USB_CR_SOF_3MS_EN_LEN) - 1) << USB_CR_SOF_3MS_EN_POS))
+#define USB_CR_USB_ERR_EN             USB_CR_USB_ERR_EN
+#define USB_CR_USB_ERR_EN_POS         (31U)
+#define USB_CR_USB_ERR_EN_LEN         (1U)
+#define USB_CR_USB_ERR_EN_MSK         (((1U << USB_CR_USB_ERR_EN_LEN) - 1) << USB_CR_USB_ERR_EN_POS)
+#define USB_CR_USB_ERR_EN_UMSK        (~(((1U << USB_CR_USB_ERR_EN_LEN) - 1) << USB_CR_USB_ERR_EN_POS))
+
+/* 0x24 : USB interrupt status */
+#define USB_INT_STS_OFFSET          (0x24)
+#define USB_SOF_INT                 USB_SOF_INT
+#define USB_SOF_INT_POS             (0U)
+#define USB_SOF_INT_LEN             (1U)
+#define USB_SOF_INT_MSK             (((1U << USB_SOF_INT_LEN) - 1) << USB_SOF_INT_POS)
+#define USB_SOF_INT_UMSK            (~(((1U << USB_SOF_INT_LEN) - 1) << USB_SOF_INT_POS))
+#define USB_RESET_INT               USB_RESET_INT
+#define USB_RESET_INT_POS           (1U)
+#define USB_RESET_INT_LEN           (1U)
+#define USB_RESET_INT_MSK           (((1U << USB_RESET_INT_LEN) - 1) << USB_RESET_INT_POS)
+#define USB_RESET_INT_UMSK          (~(((1U << USB_RESET_INT_LEN) - 1) << USB_RESET_INT_POS))
+#define USB_VBUS_TGL_INT            USB_VBUS_TGL_INT
+#define USB_VBUS_TGL_INT_POS        (2U)
+#define USB_VBUS_TGL_INT_LEN        (1U)
+#define USB_VBUS_TGL_INT_MSK        (((1U << USB_VBUS_TGL_INT_LEN) - 1) << USB_VBUS_TGL_INT_POS)
+#define USB_VBUS_TGL_INT_UMSK       (~(((1U << USB_VBUS_TGL_INT_LEN) - 1) << USB_VBUS_TGL_INT_POS))
+#define USB_GET_DCT_CMD_INT         USB_GET_DCT_CMD_INT
+#define USB_GET_DCT_CMD_INT_POS     (3U)
+#define USB_GET_DCT_CMD_INT_LEN     (1U)
+#define USB_GET_DCT_CMD_INT_MSK     (((1U << USB_GET_DCT_CMD_INT_LEN) - 1) << USB_GET_DCT_CMD_INT_POS)
+#define USB_GET_DCT_CMD_INT_UMSK    (~(((1U << USB_GET_DCT_CMD_INT_LEN) - 1) << USB_GET_DCT_CMD_INT_POS))
+#define USB_EP0_SETUP_CMD_INT       USB_EP0_SETUP_CMD_INT
+#define USB_EP0_SETUP_CMD_INT_POS   (4U)
+#define USB_EP0_SETUP_CMD_INT_LEN   (1U)
+#define USB_EP0_SETUP_CMD_INT_MSK   (((1U << USB_EP0_SETUP_CMD_INT_LEN) - 1) << USB_EP0_SETUP_CMD_INT_POS)
+#define USB_EP0_SETUP_CMD_INT_UMSK  (~(((1U << USB_EP0_SETUP_CMD_INT_LEN) - 1) << USB_EP0_SETUP_CMD_INT_POS))
+#define USB_EP0_SETUP_DONE_INT      USB_EP0_SETUP_DONE_INT
+#define USB_EP0_SETUP_DONE_INT_POS  (5U)
+#define USB_EP0_SETUP_DONE_INT_LEN  (1U)
+#define USB_EP0_SETUP_DONE_INT_MSK  (((1U << USB_EP0_SETUP_DONE_INT_LEN) - 1) << USB_EP0_SETUP_DONE_INT_POS)
+#define USB_EP0_SETUP_DONE_INT_UMSK (~(((1U << USB_EP0_SETUP_DONE_INT_LEN) - 1) << USB_EP0_SETUP_DONE_INT_POS))
+#define USB_EP0_IN_CMD_INT          USB_EP0_IN_CMD_INT
+#define USB_EP0_IN_CMD_INT_POS      (6U)
+#define USB_EP0_IN_CMD_INT_LEN      (1U)
+#define USB_EP0_IN_CMD_INT_MSK      (((1U << USB_EP0_IN_CMD_INT_LEN) - 1) << USB_EP0_IN_CMD_INT_POS)
+#define USB_EP0_IN_CMD_INT_UMSK     (~(((1U << USB_EP0_IN_CMD_INT_LEN) - 1) << USB_EP0_IN_CMD_INT_POS))
+#define USB_EP0_IN_DONE_INT         USB_EP0_IN_DONE_INT
+#define USB_EP0_IN_DONE_INT_POS     (7U)
+#define USB_EP0_IN_DONE_INT_LEN     (1U)
+#define USB_EP0_IN_DONE_INT_MSK     (((1U << USB_EP0_IN_DONE_INT_LEN) - 1) << USB_EP0_IN_DONE_INT_POS)
+#define USB_EP0_IN_DONE_INT_UMSK    (~(((1U << USB_EP0_IN_DONE_INT_LEN) - 1) << USB_EP0_IN_DONE_INT_POS))
+#define USB_EP0_OUT_CMD_INT         USB_EP0_OUT_CMD_INT
+#define USB_EP0_OUT_CMD_INT_POS     (8U)
+#define USB_EP0_OUT_CMD_INT_LEN     (1U)
+#define USB_EP0_OUT_CMD_INT_MSK     (((1U << USB_EP0_OUT_CMD_INT_LEN) - 1) << USB_EP0_OUT_CMD_INT_POS)
+#define USB_EP0_OUT_CMD_INT_UMSK    (~(((1U << USB_EP0_OUT_CMD_INT_LEN) - 1) << USB_EP0_OUT_CMD_INT_POS))
+#define USB_EP0_OUT_DONE_INT        USB_EP0_OUT_DONE_INT
+#define USB_EP0_OUT_DONE_INT_POS    (9U)
+#define USB_EP0_OUT_DONE_INT_LEN    (1U)
+#define USB_EP0_OUT_DONE_INT_MSK    (((1U << USB_EP0_OUT_DONE_INT_LEN) - 1) << USB_EP0_OUT_DONE_INT_POS)
+#define USB_EP0_OUT_DONE_INT_UMSK   (~(((1U << USB_EP0_OUT_DONE_INT_LEN) - 1) << USB_EP0_OUT_DONE_INT_POS))
+#define USB_EP1_CMD_INT             USB_EP1_CMD_INT
+#define USB_EP1_CMD_INT_POS         (10U)
+#define USB_EP1_CMD_INT_LEN         (1U)
+#define USB_EP1_CMD_INT_MSK         (((1U << USB_EP1_CMD_INT_LEN) - 1) << USB_EP1_CMD_INT_POS)
+#define USB_EP1_CMD_INT_UMSK        (~(((1U << USB_EP1_CMD_INT_LEN) - 1) << USB_EP1_CMD_INT_POS))
+#define USB_EP1_DONE_INT            USB_EP1_DONE_INT
+#define USB_EP1_DONE_INT_POS        (11U)
+#define USB_EP1_DONE_INT_LEN        (1U)
+#define USB_EP1_DONE_INT_MSK        (((1U << USB_EP1_DONE_INT_LEN) - 1) << USB_EP1_DONE_INT_POS)
+#define USB_EP1_DONE_INT_UMSK       (~(((1U << USB_EP1_DONE_INT_LEN) - 1) << USB_EP1_DONE_INT_POS))
+#define USB_EP2_CMD_INT             USB_EP2_CMD_INT
+#define USB_EP2_CMD_INT_POS         (12U)
+#define USB_EP2_CMD_INT_LEN         (1U)
+#define USB_EP2_CMD_INT_MSK         (((1U << USB_EP2_CMD_INT_LEN) - 1) << USB_EP2_CMD_INT_POS)
+#define USB_EP2_CMD_INT_UMSK        (~(((1U << USB_EP2_CMD_INT_LEN) - 1) << USB_EP2_CMD_INT_POS))
+#define USB_EP2_DONE_INT            USB_EP2_DONE_INT
+#define USB_EP2_DONE_INT_POS        (13U)
+#define USB_EP2_DONE_INT_LEN        (1U)
+#define USB_EP2_DONE_INT_MSK        (((1U << USB_EP2_DONE_INT_LEN) - 1) << USB_EP2_DONE_INT_POS)
+#define USB_EP2_DONE_INT_UMSK       (~(((1U << USB_EP2_DONE_INT_LEN) - 1) << USB_EP2_DONE_INT_POS))
+#define USB_EP3_CMD_INT             USB_EP3_CMD_INT
+#define USB_EP3_CMD_INT_POS         (14U)
+#define USB_EP3_CMD_INT_LEN         (1U)
+#define USB_EP3_CMD_INT_MSK         (((1U << USB_EP3_CMD_INT_LEN) - 1) << USB_EP3_CMD_INT_POS)
+#define USB_EP3_CMD_INT_UMSK        (~(((1U << USB_EP3_CMD_INT_LEN) - 1) << USB_EP3_CMD_INT_POS))
+#define USB_EP3_DONE_INT            USB_EP3_DONE_INT
+#define USB_EP3_DONE_INT_POS        (15U)
+#define USB_EP3_DONE_INT_LEN        (1U)
+#define USB_EP3_DONE_INT_MSK        (((1U << USB_EP3_DONE_INT_LEN) - 1) << USB_EP3_DONE_INT_POS)
+#define USB_EP3_DONE_INT_UMSK       (~(((1U << USB_EP3_DONE_INT_LEN) - 1) << USB_EP3_DONE_INT_POS))
+#define USB_EP4_CMD_INT             USB_EP4_CMD_INT
+#define USB_EP4_CMD_INT_POS         (16U)
+#define USB_EP4_CMD_INT_LEN         (1U)
+#define USB_EP4_CMD_INT_MSK         (((1U << USB_EP4_CMD_INT_LEN) - 1) << USB_EP4_CMD_INT_POS)
+#define USB_EP4_CMD_INT_UMSK        (~(((1U << USB_EP4_CMD_INT_LEN) - 1) << USB_EP4_CMD_INT_POS))
+#define USB_EP4_DONE_INT            USB_EP4_DONE_INT
+#define USB_EP4_DONE_INT_POS        (17U)
+#define USB_EP4_DONE_INT_LEN        (1U)
+#define USB_EP4_DONE_INT_MSK        (((1U << USB_EP4_DONE_INT_LEN) - 1) << USB_EP4_DONE_INT_POS)
+#define USB_EP4_DONE_INT_UMSK       (~(((1U << USB_EP4_DONE_INT_LEN) - 1) << USB_EP4_DONE_INT_POS))
+#define USB_EP5_CMD_INT             USB_EP5_CMD_INT
+#define USB_EP5_CMD_INT_POS         (18U)
+#define USB_EP5_CMD_INT_LEN         (1U)
+#define USB_EP5_CMD_INT_MSK         (((1U << USB_EP5_CMD_INT_LEN) - 1) << USB_EP5_CMD_INT_POS)
+#define USB_EP5_CMD_INT_UMSK        (~(((1U << USB_EP5_CMD_INT_LEN) - 1) << USB_EP5_CMD_INT_POS))
+#define USB_EP5_DONE_INT            USB_EP5_DONE_INT
+#define USB_EP5_DONE_INT_POS        (19U)
+#define USB_EP5_DONE_INT_LEN        (1U)
+#define USB_EP5_DONE_INT_MSK        (((1U << USB_EP5_DONE_INT_LEN) - 1) << USB_EP5_DONE_INT_POS)
+#define USB_EP5_DONE_INT_UMSK       (~(((1U << USB_EP5_DONE_INT_LEN) - 1) << USB_EP5_DONE_INT_POS))
+#define USB_EP6_CMD_INT             USB_EP6_CMD_INT
+#define USB_EP6_CMD_INT_POS         (20U)
+#define USB_EP6_CMD_INT_LEN         (1U)
+#define USB_EP6_CMD_INT_MSK         (((1U << USB_EP6_CMD_INT_LEN) - 1) << USB_EP6_CMD_INT_POS)
+#define USB_EP6_CMD_INT_UMSK        (~(((1U << USB_EP6_CMD_INT_LEN) - 1) << USB_EP6_CMD_INT_POS))
+#define USB_EP6_DONE_INT            USB_EP6_DONE_INT
+#define USB_EP6_DONE_INT_POS        (21U)
+#define USB_EP6_DONE_INT_LEN        (1U)
+#define USB_EP6_DONE_INT_MSK        (((1U << USB_EP6_DONE_INT_LEN) - 1) << USB_EP6_DONE_INT_POS)
+#define USB_EP6_DONE_INT_UMSK       (~(((1U << USB_EP6_DONE_INT_LEN) - 1) << USB_EP6_DONE_INT_POS))
+#define USB_EP7_CMD_INT             USB_EP7_CMD_INT
+#define USB_EP7_CMD_INT_POS         (22U)
+#define USB_EP7_CMD_INT_LEN         (1U)
+#define USB_EP7_CMD_INT_MSK         (((1U << USB_EP7_CMD_INT_LEN) - 1) << USB_EP7_CMD_INT_POS)
+#define USB_EP7_CMD_INT_UMSK        (~(((1U << USB_EP7_CMD_INT_LEN) - 1) << USB_EP7_CMD_INT_POS))
+#define USB_EP7_DONE_INT            USB_EP7_DONE_INT
+#define USB_EP7_DONE_INT_POS        (23U)
+#define USB_EP7_DONE_INT_LEN        (1U)
+#define USB_EP7_DONE_INT_MSK        (((1U << USB_EP7_DONE_INT_LEN) - 1) << USB_EP7_DONE_INT_POS)
+#define USB_EP7_DONE_INT_UMSK       (~(((1U << USB_EP7_DONE_INT_LEN) - 1) << USB_EP7_DONE_INT_POS))
+#define USB_REND_INT                USB_REND_INT
+#define USB_REND_INT_POS            (27U)
+#define USB_REND_INT_LEN            (1U)
+#define USB_REND_INT_MSK            (((1U << USB_REND_INT_LEN) - 1) << USB_REND_INT_POS)
+#define USB_REND_INT_UMSK           (~(((1U << USB_REND_INT_LEN) - 1) << USB_REND_INT_POS))
+#define USB_LPM_WKUP_INT            USB_LPM_WKUP_INT
+#define USB_LPM_WKUP_INT_POS        (28U)
+#define USB_LPM_WKUP_INT_LEN        (1U)
+#define USB_LPM_WKUP_INT_MSK        (((1U << USB_LPM_WKUP_INT_LEN) - 1) << USB_LPM_WKUP_INT_POS)
+#define USB_LPM_WKUP_INT_UMSK       (~(((1U << USB_LPM_WKUP_INT_LEN) - 1) << USB_LPM_WKUP_INT_POS))
+#define USB_LPM_PKT_INT             USB_LPM_PKT_INT
+#define USB_LPM_PKT_INT_POS         (29U)
+#define USB_LPM_PKT_INT_LEN         (1U)
+#define USB_LPM_PKT_INT_MSK         (((1U << USB_LPM_PKT_INT_LEN) - 1) << USB_LPM_PKT_INT_POS)
+#define USB_LPM_PKT_INT_UMSK        (~(((1U << USB_LPM_PKT_INT_LEN) - 1) << USB_LPM_PKT_INT_POS))
+#define USB_SOF_3MS_INT             USB_SOF_3MS_INT
+#define USB_SOF_3MS_INT_POS         (30U)
+#define USB_SOF_3MS_INT_LEN         (1U)
+#define USB_SOF_3MS_INT_MSK         (((1U << USB_SOF_3MS_INT_LEN) - 1) << USB_SOF_3MS_INT_POS)
+#define USB_SOF_3MS_INT_UMSK        (~(((1U << USB_SOF_3MS_INT_LEN) - 1) << USB_SOF_3MS_INT_POS))
+#define USB_ERR_INT                 USB_ERR_INT
+#define USB_ERR_INT_POS             (31U)
+#define USB_ERR_INT_LEN             (1U)
+#define USB_ERR_INT_MSK             (((1U << USB_ERR_INT_LEN) - 1) << USB_ERR_INT_POS)
+#define USB_ERR_INT_UMSK            (~(((1U << USB_ERR_INT_LEN) - 1) << USB_ERR_INT_POS))
+
+/* 0x28 : USB interrupt mask */
+#define USB_INT_MASK_OFFSET             (0x28)
+#define USB_CR_SOF_MASK                 USB_CR_SOF_MASK
+#define USB_CR_SOF_MASK_POS             (0U)
+#define USB_CR_SOF_MASK_LEN             (1U)
+#define USB_CR_SOF_MASK_MSK             (((1U << USB_CR_SOF_MASK_LEN) - 1) << USB_CR_SOF_MASK_POS)
+#define USB_CR_SOF_MASK_UMSK            (~(((1U << USB_CR_SOF_MASK_LEN) - 1) << USB_CR_SOF_MASK_POS))
+#define USB_CR_USB_RESET_MASK           USB_CR_USB_RESET_MASK
+#define USB_CR_USB_RESET_MASK_POS       (1U)
+#define USB_CR_USB_RESET_MASK_LEN       (1U)
+#define USB_CR_USB_RESET_MASK_MSK       (((1U << USB_CR_USB_RESET_MASK_LEN) - 1) << USB_CR_USB_RESET_MASK_POS)
+#define USB_CR_USB_RESET_MASK_UMSK      (~(((1U << USB_CR_USB_RESET_MASK_LEN) - 1) << USB_CR_USB_RESET_MASK_POS))
+#define USB_CR_VBUS_TGL_MASK            USB_CR_VBUS_TGL_MASK
+#define USB_CR_VBUS_TGL_MASK_POS        (2U)
+#define USB_CR_VBUS_TGL_MASK_LEN        (1U)
+#define USB_CR_VBUS_TGL_MASK_MSK        (((1U << USB_CR_VBUS_TGL_MASK_LEN) - 1) << USB_CR_VBUS_TGL_MASK_POS)
+#define USB_CR_VBUS_TGL_MASK_UMSK       (~(((1U << USB_CR_VBUS_TGL_MASK_LEN) - 1) << USB_CR_VBUS_TGL_MASK_POS))
+#define USB_CR_GET_DCT_CMD_MASK         USB_CR_GET_DCT_CMD_MASK
+#define USB_CR_GET_DCT_CMD_MASK_POS     (3U)
+#define USB_CR_GET_DCT_CMD_MASK_LEN     (1U)
+#define USB_CR_GET_DCT_CMD_MASK_MSK     (((1U << USB_CR_GET_DCT_CMD_MASK_LEN) - 1) << USB_CR_GET_DCT_CMD_MASK_POS)
+#define USB_CR_GET_DCT_CMD_MASK_UMSK    (~(((1U << USB_CR_GET_DCT_CMD_MASK_LEN) - 1) << USB_CR_GET_DCT_CMD_MASK_POS))
+#define USB_CR_EP0_SETUP_CMD_MASK       USB_CR_EP0_SETUP_CMD_MASK
+#define USB_CR_EP0_SETUP_CMD_MASK_POS   (4U)
+#define USB_CR_EP0_SETUP_CMD_MASK_LEN   (1U)
+#define USB_CR_EP0_SETUP_CMD_MASK_MSK   (((1U << USB_CR_EP0_SETUP_CMD_MASK_LEN) - 1) << USB_CR_EP0_SETUP_CMD_MASK_POS)
+#define USB_CR_EP0_SETUP_CMD_MASK_UMSK  (~(((1U << USB_CR_EP0_SETUP_CMD_MASK_LEN) - 1) << USB_CR_EP0_SETUP_CMD_MASK_POS))
+#define USB_CR_EP0_SETUP_DONE_MASK      USB_CR_EP0_SETUP_DONE_MASK
+#define USB_CR_EP0_SETUP_DONE_MASK_POS  (5U)
+#define USB_CR_EP0_SETUP_DONE_MASK_LEN  (1U)
+#define USB_CR_EP0_SETUP_DONE_MASK_MSK  (((1U << USB_CR_EP0_SETUP_DONE_MASK_LEN) - 1) << USB_CR_EP0_SETUP_DONE_MASK_POS)
+#define USB_CR_EP0_SETUP_DONE_MASK_UMSK (~(((1U << USB_CR_EP0_SETUP_DONE_MASK_LEN) - 1) << USB_CR_EP0_SETUP_DONE_MASK_POS))
+#define USB_CR_EP0_IN_CMD_MASK          USB_CR_EP0_IN_CMD_MASK
+#define USB_CR_EP0_IN_CMD_MASK_POS      (6U)
+#define USB_CR_EP0_IN_CMD_MASK_LEN      (1U)
+#define USB_CR_EP0_IN_CMD_MASK_MSK      (((1U << USB_CR_EP0_IN_CMD_MASK_LEN) - 1) << USB_CR_EP0_IN_CMD_MASK_POS)
+#define USB_CR_EP0_IN_CMD_MASK_UMSK     (~(((1U << USB_CR_EP0_IN_CMD_MASK_LEN) - 1) << USB_CR_EP0_IN_CMD_MASK_POS))
+#define USB_CR_EP0_IN_DONE_MASK         USB_CR_EP0_IN_DONE_MASK
+#define USB_CR_EP0_IN_DONE_MASK_POS     (7U)
+#define USB_CR_EP0_IN_DONE_MASK_LEN     (1U)
+#define USB_CR_EP0_IN_DONE_MASK_MSK     (((1U << USB_CR_EP0_IN_DONE_MASK_LEN) - 1) << USB_CR_EP0_IN_DONE_MASK_POS)
+#define USB_CR_EP0_IN_DONE_MASK_UMSK    (~(((1U << USB_CR_EP0_IN_DONE_MASK_LEN) - 1) << USB_CR_EP0_IN_DONE_MASK_POS))
+#define USB_CR_EP0_OUT_CMD_MASK         USB_CR_EP0_OUT_CMD_MASK
+#define USB_CR_EP0_OUT_CMD_MASK_POS     (8U)
+#define USB_CR_EP0_OUT_CMD_MASK_LEN     (1U)
+#define USB_CR_EP0_OUT_CMD_MASK_MSK     (((1U << USB_CR_EP0_OUT_CMD_MASK_LEN) - 1) << USB_CR_EP0_OUT_CMD_MASK_POS)
+#define USB_CR_EP0_OUT_CMD_MASK_UMSK    (~(((1U << USB_CR_EP0_OUT_CMD_MASK_LEN) - 1) << USB_CR_EP0_OUT_CMD_MASK_POS))
+#define USB_CR_EP0_OUT_DONE_MASK        USB_CR_EP0_OUT_DONE_MASK
+#define USB_CR_EP0_OUT_DONE_MASK_POS    (9U)
+#define USB_CR_EP0_OUT_DONE_MASK_LEN    (1U)
+#define USB_CR_EP0_OUT_DONE_MASK_MSK    (((1U << USB_CR_EP0_OUT_DONE_MASK_LEN) - 1) << USB_CR_EP0_OUT_DONE_MASK_POS)
+#define USB_CR_EP0_OUT_DONE_MASK_UMSK   (~(((1U << USB_CR_EP0_OUT_DONE_MASK_LEN) - 1) << USB_CR_EP0_OUT_DONE_MASK_POS))
+#define USB_CR_EP1_CMD_MASK             USB_CR_EP1_CMD_MASK
+#define USB_CR_EP1_CMD_MASK_POS         (10U)
+#define USB_CR_EP1_CMD_MASK_LEN         (1U)
+#define USB_CR_EP1_CMD_MASK_MSK         (((1U << USB_CR_EP1_CMD_MASK_LEN) - 1) << USB_CR_EP1_CMD_MASK_POS)
+#define USB_CR_EP1_CMD_MASK_UMSK        (~(((1U << USB_CR_EP1_CMD_MASK_LEN) - 1) << USB_CR_EP1_CMD_MASK_POS))
+#define USB_CR_EP1_DONE_MASK            USB_CR_EP1_DONE_MASK
+#define USB_CR_EP1_DONE_MASK_POS        (11U)
+#define USB_CR_EP1_DONE_MASK_LEN        (1U)
+#define USB_CR_EP1_DONE_MASK_MSK        (((1U << USB_CR_EP1_DONE_MASK_LEN) - 1) << USB_CR_EP1_DONE_MASK_POS)
+#define USB_CR_EP1_DONE_MASK_UMSK       (~(((1U << USB_CR_EP1_DONE_MASK_LEN) - 1) << USB_CR_EP1_DONE_MASK_POS))
+#define USB_CR_EP2_CMD_MASK             USB_CR_EP2_CMD_MASK
+#define USB_CR_EP2_CMD_MASK_POS         (12U)
+#define USB_CR_EP2_CMD_MASK_LEN         (1U)
+#define USB_CR_EP2_CMD_MASK_MSK         (((1U << USB_CR_EP2_CMD_MASK_LEN) - 1) << USB_CR_EP2_CMD_MASK_POS)
+#define USB_CR_EP2_CMD_MASK_UMSK        (~(((1U << USB_CR_EP2_CMD_MASK_LEN) - 1) << USB_CR_EP2_CMD_MASK_POS))
+#define USB_CR_EP2_DONE_MASK            USB_CR_EP2_DONE_MASK
+#define USB_CR_EP2_DONE_MASK_POS        (13U)
+#define USB_CR_EP2_DONE_MASK_LEN        (1U)
+#define USB_CR_EP2_DONE_MASK_MSK        (((1U << USB_CR_EP2_DONE_MASK_LEN) - 1) << USB_CR_EP2_DONE_MASK_POS)
+#define USB_CR_EP2_DONE_MASK_UMSK       (~(((1U << USB_CR_EP2_DONE_MASK_LEN) - 1) << USB_CR_EP2_DONE_MASK_POS))
+#define USB_CR_EP3_CMD_MASK             USB_CR_EP3_CMD_MASK
+#define USB_CR_EP3_CMD_MASK_POS         (14U)
+#define USB_CR_EP3_CMD_MASK_LEN         (1U)
+#define USB_CR_EP3_CMD_MASK_MSK         (((1U << USB_CR_EP3_CMD_MASK_LEN) - 1) << USB_CR_EP3_CMD_MASK_POS)
+#define USB_CR_EP3_CMD_MASK_UMSK        (~(((1U << USB_CR_EP3_CMD_MASK_LEN) - 1) << USB_CR_EP3_CMD_MASK_POS))
+#define USB_CR_EP3_DONE_MASK            USB_CR_EP3_DONE_MASK
+#define USB_CR_EP3_DONE_MASK_POS        (15U)
+#define USB_CR_EP3_DONE_MASK_LEN        (1U)
+#define USB_CR_EP3_DONE_MASK_MSK        (((1U << USB_CR_EP3_DONE_MASK_LEN) - 1) << USB_CR_EP3_DONE_MASK_POS)
+#define USB_CR_EP3_DONE_MASK_UMSK       (~(((1U << USB_CR_EP3_DONE_MASK_LEN) - 1) << USB_CR_EP3_DONE_MASK_POS))
+#define USB_CR_EP4_CMD_MASK             USB_CR_EP4_CMD_MASK
+#define USB_CR_EP4_CMD_MASK_POS         (16U)
+#define USB_CR_EP4_CMD_MASK_LEN         (1U)
+#define USB_CR_EP4_CMD_MASK_MSK         (((1U << USB_CR_EP4_CMD_MASK_LEN) - 1) << USB_CR_EP4_CMD_MASK_POS)
+#define USB_CR_EP4_CMD_MASK_UMSK        (~(((1U << USB_CR_EP4_CMD_MASK_LEN) - 1) << USB_CR_EP4_CMD_MASK_POS))
+#define USB_CR_EP4_DONE_MASK            USB_CR_EP4_DONE_MASK
+#define USB_CR_EP4_DONE_MASK_POS        (17U)
+#define USB_CR_EP4_DONE_MASK_LEN        (1U)
+#define USB_CR_EP4_DONE_MASK_MSK        (((1U << USB_CR_EP4_DONE_MASK_LEN) - 1) << USB_CR_EP4_DONE_MASK_POS)
+#define USB_CR_EP4_DONE_MASK_UMSK       (~(((1U << USB_CR_EP4_DONE_MASK_LEN) - 1) << USB_CR_EP4_DONE_MASK_POS))
+#define USB_CR_EP5_CMD_MASK             USB_CR_EP5_CMD_MASK
+#define USB_CR_EP5_CMD_MASK_POS         (18U)
+#define USB_CR_EP5_CMD_MASK_LEN         (1U)
+#define USB_CR_EP5_CMD_MASK_MSK         (((1U << USB_CR_EP5_CMD_MASK_LEN) - 1) << USB_CR_EP5_CMD_MASK_POS)
+#define USB_CR_EP5_CMD_MASK_UMSK        (~(((1U << USB_CR_EP5_CMD_MASK_LEN) - 1) << USB_CR_EP5_CMD_MASK_POS))
+#define USB_CR_EP5_DONE_MASK            USB_CR_EP5_DONE_MASK
+#define USB_CR_EP5_DONE_MASK_POS        (19U)
+#define USB_CR_EP5_DONE_MASK_LEN        (1U)
+#define USB_CR_EP5_DONE_MASK_MSK        (((1U << USB_CR_EP5_DONE_MASK_LEN) - 1) << USB_CR_EP5_DONE_MASK_POS)
+#define USB_CR_EP5_DONE_MASK_UMSK       (~(((1U << USB_CR_EP5_DONE_MASK_LEN) - 1) << USB_CR_EP5_DONE_MASK_POS))
+#define USB_CR_EP6_CMD_MASK             USB_CR_EP6_CMD_MASK
+#define USB_CR_EP6_CMD_MASK_POS         (20U)
+#define USB_CR_EP6_CMD_MASK_LEN         (1U)
+#define USB_CR_EP6_CMD_MASK_MSK         (((1U << USB_CR_EP6_CMD_MASK_LEN) - 1) << USB_CR_EP6_CMD_MASK_POS)
+#define USB_CR_EP6_CMD_MASK_UMSK        (~(((1U << USB_CR_EP6_CMD_MASK_LEN) - 1) << USB_CR_EP6_CMD_MASK_POS))
+#define USB_CR_EP6_DONE_MASK            USB_CR_EP6_DONE_MASK
+#define USB_CR_EP6_DONE_MASK_POS        (21U)
+#define USB_CR_EP6_DONE_MASK_LEN        (1U)
+#define USB_CR_EP6_DONE_MASK_MSK        (((1U << USB_CR_EP6_DONE_MASK_LEN) - 1) << USB_CR_EP6_DONE_MASK_POS)
+#define USB_CR_EP6_DONE_MASK_UMSK       (~(((1U << USB_CR_EP6_DONE_MASK_LEN) - 1) << USB_CR_EP6_DONE_MASK_POS))
+#define USB_CR_EP7_CMD_MASK             USB_CR_EP7_CMD_MASK
+#define USB_CR_EP7_CMD_MASK_POS         (22U)
+#define USB_CR_EP7_CMD_MASK_LEN         (1U)
+#define USB_CR_EP7_CMD_MASK_MSK         (((1U << USB_CR_EP7_CMD_MASK_LEN) - 1) << USB_CR_EP7_CMD_MASK_POS)
+#define USB_CR_EP7_CMD_MASK_UMSK        (~(((1U << USB_CR_EP7_CMD_MASK_LEN) - 1) << USB_CR_EP7_CMD_MASK_POS))
+#define USB_CR_EP7_DONE_MASK            USB_CR_EP7_DONE_MASK
+#define USB_CR_EP7_DONE_MASK_POS        (23U)
+#define USB_CR_EP7_DONE_MASK_LEN        (1U)
+#define USB_CR_EP7_DONE_MASK_MSK        (((1U << USB_CR_EP7_DONE_MASK_LEN) - 1) << USB_CR_EP7_DONE_MASK_POS)
+#define USB_CR_EP7_DONE_MASK_UMSK       (~(((1U << USB_CR_EP7_DONE_MASK_LEN) - 1) << USB_CR_EP7_DONE_MASK_POS))
+#define USB_CR_USB_REND_MASK            USB_CR_USB_REND_MASK
+#define USB_CR_USB_REND_MASK_POS        (27U)
+#define USB_CR_USB_REND_MASK_LEN        (1U)
+#define USB_CR_USB_REND_MASK_MSK        (((1U << USB_CR_USB_REND_MASK_LEN) - 1) << USB_CR_USB_REND_MASK_POS)
+#define USB_CR_USB_REND_MASK_UMSK       (~(((1U << USB_CR_USB_REND_MASK_LEN) - 1) << USB_CR_USB_REND_MASK_POS))
+#define USB_CR_LPM_WKUP_MASK            USB_CR_LPM_WKUP_MASK
+#define USB_CR_LPM_WKUP_MASK_POS        (28U)
+#define USB_CR_LPM_WKUP_MASK_LEN        (1U)
+#define USB_CR_LPM_WKUP_MASK_MSK        (((1U << USB_CR_LPM_WKUP_MASK_LEN) - 1) << USB_CR_LPM_WKUP_MASK_POS)
+#define USB_CR_LPM_WKUP_MASK_UMSK       (~(((1U << USB_CR_LPM_WKUP_MASK_LEN) - 1) << USB_CR_LPM_WKUP_MASK_POS))
+#define USB_CR_LPM_PKT_MASK             USB_CR_LPM_PKT_MASK
+#define USB_CR_LPM_PKT_MASK_POS         (29U)
+#define USB_CR_LPM_PKT_MASK_LEN         (1U)
+#define USB_CR_LPM_PKT_MASK_MSK         (((1U << USB_CR_LPM_PKT_MASK_LEN) - 1) << USB_CR_LPM_PKT_MASK_POS)
+#define USB_CR_LPM_PKT_MASK_UMSK        (~(((1U << USB_CR_LPM_PKT_MASK_LEN) - 1) << USB_CR_LPM_PKT_MASK_POS))
+#define USB_CR_SOF_3MS_MASK             USB_CR_SOF_3MS_MASK
+#define USB_CR_SOF_3MS_MASK_POS         (30U)
+#define USB_CR_SOF_3MS_MASK_LEN         (1U)
+#define USB_CR_SOF_3MS_MASK_MSK         (((1U << USB_CR_SOF_3MS_MASK_LEN) - 1) << USB_CR_SOF_3MS_MASK_POS)
+#define USB_CR_SOF_3MS_MASK_UMSK        (~(((1U << USB_CR_SOF_3MS_MASK_LEN) - 1) << USB_CR_SOF_3MS_MASK_POS))
+#define USB_CR_USB_ERR_MASK             USB_CR_USB_ERR_MASK
+#define USB_CR_USB_ERR_MASK_POS         (31U)
+#define USB_CR_USB_ERR_MASK_LEN         (1U)
+#define USB_CR_USB_ERR_MASK_MSK         (((1U << USB_CR_USB_ERR_MASK_LEN) - 1) << USB_CR_USB_ERR_MASK_POS)
+#define USB_CR_USB_ERR_MASK_UMSK        (~(((1U << USB_CR_USB_ERR_MASK_LEN) - 1) << USB_CR_USB_ERR_MASK_POS))
+
+/* 0x2C : USB interrupt clear */
+#define USB_INT_CLEAR_OFFSET           (0x2C)
+#define USB_CR_SOF_CLR                 USB_CR_SOF_CLR
+#define USB_CR_SOF_CLR_POS             (0U)
+#define USB_CR_SOF_CLR_LEN             (1U)
+#define USB_CR_SOF_CLR_MSK             (((1U << USB_CR_SOF_CLR_LEN) - 1) << USB_CR_SOF_CLR_POS)
+#define USB_CR_SOF_CLR_UMSK            (~(((1U << USB_CR_SOF_CLR_LEN) - 1) << USB_CR_SOF_CLR_POS))
+#define USB_CR_USB_RESET_CLR           USB_CR_USB_RESET_CLR
+#define USB_CR_USB_RESET_CLR_POS       (1U)
+#define USB_CR_USB_RESET_CLR_LEN       (1U)
+#define USB_CR_USB_RESET_CLR_MSK       (((1U << USB_CR_USB_RESET_CLR_LEN) - 1) << USB_CR_USB_RESET_CLR_POS)
+#define USB_CR_USB_RESET_CLR_UMSK      (~(((1U << USB_CR_USB_RESET_CLR_LEN) - 1) << USB_CR_USB_RESET_CLR_POS))
+#define USB_CR_VBUS_TGL_CLR            USB_CR_VBUS_TGL_CLR
+#define USB_CR_VBUS_TGL_CLR_POS        (2U)
+#define USB_CR_VBUS_TGL_CLR_LEN        (1U)
+#define USB_CR_VBUS_TGL_CLR_MSK        (((1U << USB_CR_VBUS_TGL_CLR_LEN) - 1) << USB_CR_VBUS_TGL_CLR_POS)
+#define USB_CR_VBUS_TGL_CLR_UMSK       (~(((1U << USB_CR_VBUS_TGL_CLR_LEN) - 1) << USB_CR_VBUS_TGL_CLR_POS))
+#define USB_CR_GET_DCT_CMD_CLR         USB_CR_GET_DCT_CMD_CLR
+#define USB_CR_GET_DCT_CMD_CLR_POS     (3U)
+#define USB_CR_GET_DCT_CMD_CLR_LEN     (1U)
+#define USB_CR_GET_DCT_CMD_CLR_MSK     (((1U << USB_CR_GET_DCT_CMD_CLR_LEN) - 1) << USB_CR_GET_DCT_CMD_CLR_POS)
+#define USB_CR_GET_DCT_CMD_CLR_UMSK    (~(((1U << USB_CR_GET_DCT_CMD_CLR_LEN) - 1) << USB_CR_GET_DCT_CMD_CLR_POS))
+#define USB_CR_EP0_SETUP_CMD_CLR       USB_CR_EP0_SETUP_CMD_CLR
+#define USB_CR_EP0_SETUP_CMD_CLR_POS   (4U)
+#define USB_CR_EP0_SETUP_CMD_CLR_LEN   (1U)
+#define USB_CR_EP0_SETUP_CMD_CLR_MSK   (((1U << USB_CR_EP0_SETUP_CMD_CLR_LEN) - 1) << USB_CR_EP0_SETUP_CMD_CLR_POS)
+#define USB_CR_EP0_SETUP_CMD_CLR_UMSK  (~(((1U << USB_CR_EP0_SETUP_CMD_CLR_LEN) - 1) << USB_CR_EP0_SETUP_CMD_CLR_POS))
+#define USB_CR_EP0_SETUP_DONE_CLR      USB_CR_EP0_SETUP_DONE_CLR
+#define USB_CR_EP0_SETUP_DONE_CLR_POS  (5U)
+#define USB_CR_EP0_SETUP_DONE_CLR_LEN  (1U)
+#define USB_CR_EP0_SETUP_DONE_CLR_MSK  (((1U << USB_CR_EP0_SETUP_DONE_CLR_LEN) - 1) << USB_CR_EP0_SETUP_DONE_CLR_POS)
+#define USB_CR_EP0_SETUP_DONE_CLR_UMSK (~(((1U << USB_CR_EP0_SETUP_DONE_CLR_LEN) - 1) << USB_CR_EP0_SETUP_DONE_CLR_POS))
+#define USB_CR_EP0_IN_CMD_CLR          USB_CR_EP0_IN_CMD_CLR
+#define USB_CR_EP0_IN_CMD_CLR_POS      (6U)
+#define USB_CR_EP0_IN_CMD_CLR_LEN      (1U)
+#define USB_CR_EP0_IN_CMD_CLR_MSK      (((1U << USB_CR_EP0_IN_CMD_CLR_LEN) - 1) << USB_CR_EP0_IN_CMD_CLR_POS)
+#define USB_CR_EP0_IN_CMD_CLR_UMSK     (~(((1U << USB_CR_EP0_IN_CMD_CLR_LEN) - 1) << USB_CR_EP0_IN_CMD_CLR_POS))
+#define USB_CR_EP0_IN_DONE_CLR         USB_CR_EP0_IN_DONE_CLR
+#define USB_CR_EP0_IN_DONE_CLR_POS     (7U)
+#define USB_CR_EP0_IN_DONE_CLR_LEN     (1U)
+#define USB_CR_EP0_IN_DONE_CLR_MSK     (((1U << USB_CR_EP0_IN_DONE_CLR_LEN) - 1) << USB_CR_EP0_IN_DONE_CLR_POS)
+#define USB_CR_EP0_IN_DONE_CLR_UMSK    (~(((1U << USB_CR_EP0_IN_DONE_CLR_LEN) - 1) << USB_CR_EP0_IN_DONE_CLR_POS))
+#define USB_CR_EP0_OUT_CMD_CLR         USB_CR_EP0_OUT_CMD_CLR
+#define USB_CR_EP0_OUT_CMD_CLR_POS     (8U)
+#define USB_CR_EP0_OUT_CMD_CLR_LEN     (1U)
+#define USB_CR_EP0_OUT_CMD_CLR_MSK     (((1U << USB_CR_EP0_OUT_CMD_CLR_LEN) - 1) << USB_CR_EP0_OUT_CMD_CLR_POS)
+#define USB_CR_EP0_OUT_CMD_CLR_UMSK    (~(((1U << USB_CR_EP0_OUT_CMD_CLR_LEN) - 1) << USB_CR_EP0_OUT_CMD_CLR_POS))
+#define USB_CR_EP0_OUT_DONE_CLR        USB_CR_EP0_OUT_DONE_CLR
+#define USB_CR_EP0_OUT_DONE_CLR_POS    (9U)
+#define USB_CR_EP0_OUT_DONE_CLR_LEN    (1U)
+#define USB_CR_EP0_OUT_DONE_CLR_MSK    (((1U << USB_CR_EP0_OUT_DONE_CLR_LEN) - 1) << USB_CR_EP0_OUT_DONE_CLR_POS)
+#define USB_CR_EP0_OUT_DONE_CLR_UMSK   (~(((1U << USB_CR_EP0_OUT_DONE_CLR_LEN) - 1) << USB_CR_EP0_OUT_DONE_CLR_POS))
+#define USB_CR_EP1_CMD_CLR             USB_CR_EP1_CMD_CLR
+#define USB_CR_EP1_CMD_CLR_POS         (10U)
+#define USB_CR_EP1_CMD_CLR_LEN         (1U)
+#define USB_CR_EP1_CMD_CLR_MSK         (((1U << USB_CR_EP1_CMD_CLR_LEN) - 1) << USB_CR_EP1_CMD_CLR_POS)
+#define USB_CR_EP1_CMD_CLR_UMSK        (~(((1U << USB_CR_EP1_CMD_CLR_LEN) - 1) << USB_CR_EP1_CMD_CLR_POS))
+#define USB_CR_EP1_DONE_CLR            USB_CR_EP1_DONE_CLR
+#define USB_CR_EP1_DONE_CLR_POS        (11U)
+#define USB_CR_EP1_DONE_CLR_LEN        (1U)
+#define USB_CR_EP1_DONE_CLR_MSK        (((1U << USB_CR_EP1_DONE_CLR_LEN) - 1) << USB_CR_EP1_DONE_CLR_POS)
+#define USB_CR_EP1_DONE_CLR_UMSK       (~(((1U << USB_CR_EP1_DONE_CLR_LEN) - 1) << USB_CR_EP1_DONE_CLR_POS))
+#define USB_CR_EP2_CMD_CLR             USB_CR_EP2_CMD_CLR
+#define USB_CR_EP2_CMD_CLR_POS         (12U)
+#define USB_CR_EP2_CMD_CLR_LEN         (1U)
+#define USB_CR_EP2_CMD_CLR_MSK         (((1U << USB_CR_EP2_CMD_CLR_LEN) - 1) << USB_CR_EP2_CMD_CLR_POS)
+#define USB_CR_EP2_CMD_CLR_UMSK        (~(((1U << USB_CR_EP2_CMD_CLR_LEN) - 1) << USB_CR_EP2_CMD_CLR_POS))
+#define USB_CR_EP2_DONE_CLR            USB_CR_EP2_DONE_CLR
+#define USB_CR_EP2_DONE_CLR_POS        (13U)
+#define USB_CR_EP2_DONE_CLR_LEN        (1U)
+#define USB_CR_EP2_DONE_CLR_MSK        (((1U << USB_CR_EP2_DONE_CLR_LEN) - 1) << USB_CR_EP2_DONE_CLR_POS)
+#define USB_CR_EP2_DONE_CLR_UMSK       (~(((1U << USB_CR_EP2_DONE_CLR_LEN) - 1) << USB_CR_EP2_DONE_CLR_POS))
+#define USB_CR_EP3_CMD_CLR             USB_CR_EP3_CMD_CLR
+#define USB_CR_EP3_CMD_CLR_POS         (14U)
+#define USB_CR_EP3_CMD_CLR_LEN         (1U)
+#define USB_CR_EP3_CMD_CLR_MSK         (((1U << USB_CR_EP3_CMD_CLR_LEN) - 1) << USB_CR_EP3_CMD_CLR_POS)
+#define USB_CR_EP3_CMD_CLR_UMSK        (~(((1U << USB_CR_EP3_CMD_CLR_LEN) - 1) << USB_CR_EP3_CMD_CLR_POS))
+#define USB_CR_EP3_DONE_CLR            USB_CR_EP3_DONE_CLR
+#define USB_CR_EP3_DONE_CLR_POS        (15U)
+#define USB_CR_EP3_DONE_CLR_LEN        (1U)
+#define USB_CR_EP3_DONE_CLR_MSK        (((1U << USB_CR_EP3_DONE_CLR_LEN) - 1) << USB_CR_EP3_DONE_CLR_POS)
+#define USB_CR_EP3_DONE_CLR_UMSK       (~(((1U << USB_CR_EP3_DONE_CLR_LEN) - 1) << USB_CR_EP3_DONE_CLR_POS))
+#define USB_CR_EP4_CMD_CLR             USB_CR_EP4_CMD_CLR
+#define USB_CR_EP4_CMD_CLR_POS         (16U)
+#define USB_CR_EP4_CMD_CLR_LEN         (1U)
+#define USB_CR_EP4_CMD_CLR_MSK         (((1U << USB_CR_EP4_CMD_CLR_LEN) - 1) << USB_CR_EP4_CMD_CLR_POS)
+#define USB_CR_EP4_CMD_CLR_UMSK        (~(((1U << USB_CR_EP4_CMD_CLR_LEN) - 1) << USB_CR_EP4_CMD_CLR_POS))
+#define USB_CR_EP4_DONE_CLR            USB_CR_EP4_DONE_CLR
+#define USB_CR_EP4_DONE_CLR_POS        (17U)
+#define USB_CR_EP4_DONE_CLR_LEN        (1U)
+#define USB_CR_EP4_DONE_CLR_MSK        (((1U << USB_CR_EP4_DONE_CLR_LEN) - 1) << USB_CR_EP4_DONE_CLR_POS)
+#define USB_CR_EP4_DONE_CLR_UMSK       (~(((1U << USB_CR_EP4_DONE_CLR_LEN) - 1) << USB_CR_EP4_DONE_CLR_POS))
+#define USB_CR_EP5_CMD_CLR             USB_CR_EP5_CMD_CLR
+#define USB_CR_EP5_CMD_CLR_POS         (18U)
+#define USB_CR_EP5_CMD_CLR_LEN         (1U)
+#define USB_CR_EP5_CMD_CLR_MSK         (((1U << USB_CR_EP5_CMD_CLR_LEN) - 1) << USB_CR_EP5_CMD_CLR_POS)
+#define USB_CR_EP5_CMD_CLR_UMSK        (~(((1U << USB_CR_EP5_CMD_CLR_LEN) - 1) << USB_CR_EP5_CMD_CLR_POS))
+#define USB_CR_EP5_DONE_CLR            USB_CR_EP5_DONE_CLR
+#define USB_CR_EP5_DONE_CLR_POS        (19U)
+#define USB_CR_EP5_DONE_CLR_LEN        (1U)
+#define USB_CR_EP5_DONE_CLR_MSK        (((1U << USB_CR_EP5_DONE_CLR_LEN) - 1) << USB_CR_EP5_DONE_CLR_POS)
+#define USB_CR_EP5_DONE_CLR_UMSK       (~(((1U << USB_CR_EP5_DONE_CLR_LEN) - 1) << USB_CR_EP5_DONE_CLR_POS))
+#define USB_CR_EP6_CMD_CLR             USB_CR_EP6_CMD_CLR
+#define USB_CR_EP6_CMD_CLR_POS         (20U)
+#define USB_CR_EP6_CMD_CLR_LEN         (1U)
+#define USB_CR_EP6_CMD_CLR_MSK         (((1U << USB_CR_EP6_CMD_CLR_LEN) - 1) << USB_CR_EP6_CMD_CLR_POS)
+#define USB_CR_EP6_CMD_CLR_UMSK        (~(((1U << USB_CR_EP6_CMD_CLR_LEN) - 1) << USB_CR_EP6_CMD_CLR_POS))
+#define USB_CR_EP6_DONE_CLR            USB_CR_EP6_DONE_CLR
+#define USB_CR_EP6_DONE_CLR_POS        (21U)
+#define USB_CR_EP6_DONE_CLR_LEN        (1U)
+#define USB_CR_EP6_DONE_CLR_MSK        (((1U << USB_CR_EP6_DONE_CLR_LEN) - 1) << USB_CR_EP6_DONE_CLR_POS)
+#define USB_CR_EP6_DONE_CLR_UMSK       (~(((1U << USB_CR_EP6_DONE_CLR_LEN) - 1) << USB_CR_EP6_DONE_CLR_POS))
+#define USB_CR_EP7_CMD_CLR             USB_CR_EP7_CMD_CLR
+#define USB_CR_EP7_CMD_CLR_POS         (22U)
+#define USB_CR_EP7_CMD_CLR_LEN         (1U)
+#define USB_CR_EP7_CMD_CLR_MSK         (((1U << USB_CR_EP7_CMD_CLR_LEN) - 1) << USB_CR_EP7_CMD_CLR_POS)
+#define USB_CR_EP7_CMD_CLR_UMSK        (~(((1U << USB_CR_EP7_CMD_CLR_LEN) - 1) << USB_CR_EP7_CMD_CLR_POS))
+#define USB_CR_EP7_DONE_CLR            USB_CR_EP7_DONE_CLR
+#define USB_CR_EP7_DONE_CLR_POS        (23U)
+#define USB_CR_EP7_DONE_CLR_LEN        (1U)
+#define USB_CR_EP7_DONE_CLR_MSK        (((1U << USB_CR_EP7_DONE_CLR_LEN) - 1) << USB_CR_EP7_DONE_CLR_POS)
+#define USB_CR_EP7_DONE_CLR_UMSK       (~(((1U << USB_CR_EP7_DONE_CLR_LEN) - 1) << USB_CR_EP7_DONE_CLR_POS))
+#define USB_CR_USB_REND_CLR            USB_CR_USB_REND_CLR
+#define USB_CR_USB_REND_CLR_POS        (27U)
+#define USB_CR_USB_REND_CLR_LEN        (1U)
+#define USB_CR_USB_REND_CLR_MSK        (((1U << USB_CR_USB_REND_CLR_LEN) - 1) << USB_CR_USB_REND_CLR_POS)
+#define USB_CR_USB_REND_CLR_UMSK       (~(((1U << USB_CR_USB_REND_CLR_LEN) - 1) << USB_CR_USB_REND_CLR_POS))
+#define USB_CR_LPM_WKUP_CLR            USB_CR_LPM_WKUP_CLR
+#define USB_CR_LPM_WKUP_CLR_POS        (28U)
+#define USB_CR_LPM_WKUP_CLR_LEN        (1U)
+#define USB_CR_LPM_WKUP_CLR_MSK        (((1U << USB_CR_LPM_WKUP_CLR_LEN) - 1) << USB_CR_LPM_WKUP_CLR_POS)
+#define USB_CR_LPM_WKUP_CLR_UMSK       (~(((1U << USB_CR_LPM_WKUP_CLR_LEN) - 1) << USB_CR_LPM_WKUP_CLR_POS))
+#define USB_CR_LPM_PKT_CLR             USB_CR_LPM_PKT_CLR
+#define USB_CR_LPM_PKT_CLR_POS         (29U)
+#define USB_CR_LPM_PKT_CLR_LEN         (1U)
+#define USB_CR_LPM_PKT_CLR_MSK         (((1U << USB_CR_LPM_PKT_CLR_LEN) - 1) << USB_CR_LPM_PKT_CLR_POS)
+#define USB_CR_LPM_PKT_CLR_UMSK        (~(((1U << USB_CR_LPM_PKT_CLR_LEN) - 1) << USB_CR_LPM_PKT_CLR_POS))
+#define USB_CR_SOF_3MS_CLR             USB_CR_SOF_3MS_CLR
+#define USB_CR_SOF_3MS_CLR_POS         (30U)
+#define USB_CR_SOF_3MS_CLR_LEN         (1U)
+#define USB_CR_SOF_3MS_CLR_MSK         (((1U << USB_CR_SOF_3MS_CLR_LEN) - 1) << USB_CR_SOF_3MS_CLR_POS)
+#define USB_CR_SOF_3MS_CLR_UMSK        (~(((1U << USB_CR_SOF_3MS_CLR_LEN) - 1) << USB_CR_SOF_3MS_CLR_POS))
+#define USB_CR_USB_ERR_CLR             USB_CR_USB_ERR_CLR
+#define USB_CR_USB_ERR_CLR_POS         (31U)
+#define USB_CR_USB_ERR_CLR_LEN         (1U)
+#define USB_CR_USB_ERR_CLR_MSK         (((1U << USB_CR_USB_ERR_CLR_LEN) - 1) << USB_CR_USB_ERR_CLR_POS)
+#define USB_CR_USB_ERR_CLR_UMSK        (~(((1U << USB_CR_USB_ERR_CLR_LEN) - 1) << USB_CR_USB_ERR_CLR_POS))
+
+/* 0x40 : ep1_config */
+#define USB_EP1_CONFIG_OFFSET (0x40)
+#define USB_CR_EP1_SIZE       USB_CR_EP1_SIZE
+#define USB_CR_EP1_SIZE_POS   (0U)
+#define USB_CR_EP1_SIZE_LEN   (11U)
+#define USB_CR_EP1_SIZE_MSK   (((1U << USB_CR_EP1_SIZE_LEN) - 1) << USB_CR_EP1_SIZE_POS)
+#define USB_CR_EP1_SIZE_UMSK  (~(((1U << USB_CR_EP1_SIZE_LEN) - 1) << USB_CR_EP1_SIZE_POS))
+#define USB_CR_EP1_DIR        USB_CR_EP1_DIR
+#define USB_CR_EP1_DIR_POS    (11U)
+#define USB_CR_EP1_DIR_LEN    (2U)
+#define USB_CR_EP1_DIR_MSK    (((1U << USB_CR_EP1_DIR_LEN) - 1) << USB_CR_EP1_DIR_POS)
+#define USB_CR_EP1_DIR_UMSK   (~(((1U << USB_CR_EP1_DIR_LEN) - 1) << USB_CR_EP1_DIR_POS))
+#define USB_CR_EP1_TYPE       USB_CR_EP1_TYPE
+#define USB_CR_EP1_TYPE_POS   (13U)
+#define USB_CR_EP1_TYPE_LEN   (3U)
+#define USB_CR_EP1_TYPE_MSK   (((1U << USB_CR_EP1_TYPE_LEN) - 1) << USB_CR_EP1_TYPE_POS)
+#define USB_CR_EP1_TYPE_UMSK  (~(((1U << USB_CR_EP1_TYPE_LEN) - 1) << USB_CR_EP1_TYPE_POS))
+#define USB_CR_EP1_STALL      USB_CR_EP1_STALL
+#define USB_CR_EP1_STALL_POS  (16U)
+#define USB_CR_EP1_STALL_LEN  (1U)
+#define USB_CR_EP1_STALL_MSK  (((1U << USB_CR_EP1_STALL_LEN) - 1) << USB_CR_EP1_STALL_POS)
+#define USB_CR_EP1_STALL_UMSK (~(((1U << USB_CR_EP1_STALL_LEN) - 1) << USB_CR_EP1_STALL_POS))
+#define USB_CR_EP1_NACK       USB_CR_EP1_NACK
+#define USB_CR_EP1_NACK_POS   (17U)
+#define USB_CR_EP1_NACK_LEN   (1U)
+#define USB_CR_EP1_NACK_MSK   (((1U << USB_CR_EP1_NACK_LEN) - 1) << USB_CR_EP1_NACK_POS)
+#define USB_CR_EP1_NACK_UMSK  (~(((1U << USB_CR_EP1_NACK_LEN) - 1) << USB_CR_EP1_NACK_POS))
+#define USB_CR_EP1_RDY        USB_CR_EP1_RDY
+#define USB_CR_EP1_RDY_POS    (18U)
+#define USB_CR_EP1_RDY_LEN    (1U)
+#define USB_CR_EP1_RDY_MSK    (((1U << USB_CR_EP1_RDY_LEN) - 1) << USB_CR_EP1_RDY_POS)
+#define USB_CR_EP1_RDY_UMSK   (~(((1U << USB_CR_EP1_RDY_LEN) - 1) << USB_CR_EP1_RDY_POS))
+#define USB_STS_EP1_RDY       USB_STS_EP1_RDY
+#define USB_STS_EP1_RDY_POS   (19U)
+#define USB_STS_EP1_RDY_LEN   (1U)
+#define USB_STS_EP1_RDY_MSK   (((1U << USB_STS_EP1_RDY_LEN) - 1) << USB_STS_EP1_RDY_POS)
+#define USB_STS_EP1_RDY_UMSK  (~(((1U << USB_STS_EP1_RDY_LEN) - 1) << USB_STS_EP1_RDY_POS))
+
+/* 0x44 : ep2_config */
+#define USB_EP2_CONFIG_OFFSET (0x44)
+#define USB_CR_EP2_SIZE       USB_CR_EP2_SIZE
+#define USB_CR_EP2_SIZE_POS   (0U)
+#define USB_CR_EP2_SIZE_LEN   (11U)
+#define USB_CR_EP2_SIZE_MSK   (((1U << USB_CR_EP2_SIZE_LEN) - 1) << USB_CR_EP2_SIZE_POS)
+#define USB_CR_EP2_SIZE_UMSK  (~(((1U << USB_CR_EP2_SIZE_LEN) - 1) << USB_CR_EP2_SIZE_POS))
+#define USB_CR_EP2_DIR        USB_CR_EP2_DIR
+#define USB_CR_EP2_DIR_POS    (11U)
+#define USB_CR_EP2_DIR_LEN    (2U)
+#define USB_CR_EP2_DIR_MSK    (((1U << USB_CR_EP2_DIR_LEN) - 1) << USB_CR_EP2_DIR_POS)
+#define USB_CR_EP2_DIR_UMSK   (~(((1U << USB_CR_EP2_DIR_LEN) - 1) << USB_CR_EP2_DIR_POS))
+#define USB_CR_EP2_TYPE       USB_CR_EP2_TYPE
+#define USB_CR_EP2_TYPE_POS   (13U)
+#define USB_CR_EP2_TYPE_LEN   (3U)
+#define USB_CR_EP2_TYPE_MSK   (((1U << USB_CR_EP2_TYPE_LEN) - 1) << USB_CR_EP2_TYPE_POS)
+#define USB_CR_EP2_TYPE_UMSK  (~(((1U << USB_CR_EP2_TYPE_LEN) - 1) << USB_CR_EP2_TYPE_POS))
+#define USB_CR_EP2_STALL      USB_CR_EP2_STALL
+#define USB_CR_EP2_STALL_POS  (16U)
+#define USB_CR_EP2_STALL_LEN  (1U)
+#define USB_CR_EP2_STALL_MSK  (((1U << USB_CR_EP2_STALL_LEN) - 1) << USB_CR_EP2_STALL_POS)
+#define USB_CR_EP2_STALL_UMSK (~(((1U << USB_CR_EP2_STALL_LEN) - 1) << USB_CR_EP2_STALL_POS))
+#define USB_CR_EP2_NACK       USB_CR_EP2_NACK
+#define USB_CR_EP2_NACK_POS   (17U)
+#define USB_CR_EP2_NACK_LEN   (1U)
+#define USB_CR_EP2_NACK_MSK   (((1U << USB_CR_EP2_NACK_LEN) - 1) << USB_CR_EP2_NACK_POS)
+#define USB_CR_EP2_NACK_UMSK  (~(((1U << USB_CR_EP2_NACK_LEN) - 1) << USB_CR_EP2_NACK_POS))
+#define USB_CR_EP2_RDY        USB_CR_EP2_RDY
+#define USB_CR_EP2_RDY_POS    (18U)
+#define USB_CR_EP2_RDY_LEN    (1U)
+#define USB_CR_EP2_RDY_MSK    (((1U << USB_CR_EP2_RDY_LEN) - 1) << USB_CR_EP2_RDY_POS)
+#define USB_CR_EP2_RDY_UMSK   (~(((1U << USB_CR_EP2_RDY_LEN) - 1) << USB_CR_EP2_RDY_POS))
+#define USB_STS_EP2_RDY       USB_STS_EP2_RDY
+#define USB_STS_EP2_RDY_POS   (19U)
+#define USB_STS_EP2_RDY_LEN   (1U)
+#define USB_STS_EP2_RDY_MSK   (((1U << USB_STS_EP2_RDY_LEN) - 1) << USB_STS_EP2_RDY_POS)
+#define USB_STS_EP2_RDY_UMSK  (~(((1U << USB_STS_EP2_RDY_LEN) - 1) << USB_STS_EP2_RDY_POS))
+
+/* 0x48 : ep3_config */
+#define USB_EP3_CONFIG_OFFSET (0x48)
+#define USB_CR_EP3_SIZE       USB_CR_EP3_SIZE
+#define USB_CR_EP3_SIZE_POS   (0U)
+#define USB_CR_EP3_SIZE_LEN   (11U)
+#define USB_CR_EP3_SIZE_MSK   (((1U << USB_CR_EP3_SIZE_LEN) - 1) << USB_CR_EP3_SIZE_POS)
+#define USB_CR_EP3_SIZE_UMSK  (~(((1U << USB_CR_EP3_SIZE_LEN) - 1) << USB_CR_EP3_SIZE_POS))
+#define USB_CR_EP3_DIR        USB_CR_EP3_DIR
+#define USB_CR_EP3_DIR_POS    (11U)
+#define USB_CR_EP3_DIR_LEN    (2U)
+#define USB_CR_EP3_DIR_MSK    (((1U << USB_CR_EP3_DIR_LEN) - 1) << USB_CR_EP3_DIR_POS)
+#define USB_CR_EP3_DIR_UMSK   (~(((1U << USB_CR_EP3_DIR_LEN) - 1) << USB_CR_EP3_DIR_POS))
+#define USB_CR_EP3_TYPE       USB_CR_EP3_TYPE
+#define USB_CR_EP3_TYPE_POS   (13U)
+#define USB_CR_EP3_TYPE_LEN   (3U)
+#define USB_CR_EP3_TYPE_MSK   (((1U << USB_CR_EP3_TYPE_LEN) - 1) << USB_CR_EP3_TYPE_POS)
+#define USB_CR_EP3_TYPE_UMSK  (~(((1U << USB_CR_EP3_TYPE_LEN) - 1) << USB_CR_EP3_TYPE_POS))
+#define USB_CR_EP3_STALL      USB_CR_EP3_STALL
+#define USB_CR_EP3_STALL_POS  (16U)
+#define USB_CR_EP3_STALL_LEN  (1U)
+#define USB_CR_EP3_STALL_MSK  (((1U << USB_CR_EP3_STALL_LEN) - 1) << USB_CR_EP3_STALL_POS)
+#define USB_CR_EP3_STALL_UMSK (~(((1U << USB_CR_EP3_STALL_LEN) - 1) << USB_CR_EP3_STALL_POS))
+#define USB_CR_EP3_NACK       USB_CR_EP3_NACK
+#define USB_CR_EP3_NACK_POS   (17U)
+#define USB_CR_EP3_NACK_LEN   (1U)
+#define USB_CR_EP3_NACK_MSK   (((1U << USB_CR_EP3_NACK_LEN) - 1) << USB_CR_EP3_NACK_POS)
+#define USB_CR_EP3_NACK_UMSK  (~(((1U << USB_CR_EP3_NACK_LEN) - 1) << USB_CR_EP3_NACK_POS))
+#define USB_CR_EP3_RDY        USB_CR_EP3_RDY
+#define USB_CR_EP3_RDY_POS    (18U)
+#define USB_CR_EP3_RDY_LEN    (1U)
+#define USB_CR_EP3_RDY_MSK    (((1U << USB_CR_EP3_RDY_LEN) - 1) << USB_CR_EP3_RDY_POS)
+#define USB_CR_EP3_RDY_UMSK   (~(((1U << USB_CR_EP3_RDY_LEN) - 1) << USB_CR_EP3_RDY_POS))
+#define USB_STS_EP3_RDY       USB_STS_EP3_RDY
+#define USB_STS_EP3_RDY_POS   (19U)
+#define USB_STS_EP3_RDY_LEN   (1U)
+#define USB_STS_EP3_RDY_MSK   (((1U << USB_STS_EP3_RDY_LEN) - 1) << USB_STS_EP3_RDY_POS)
+#define USB_STS_EP3_RDY_UMSK  (~(((1U << USB_STS_EP3_RDY_LEN) - 1) << USB_STS_EP3_RDY_POS))
+
+/* 0x4C : ep4_config */
+#define USB_EP4_CONFIG_OFFSET (0x4C)
+#define USB_CR_EP4_SIZE       USB_CR_EP4_SIZE
+#define USB_CR_EP4_SIZE_POS   (0U)
+#define USB_CR_EP4_SIZE_LEN   (11U)
+#define USB_CR_EP4_SIZE_MSK   (((1U << USB_CR_EP4_SIZE_LEN) - 1) << USB_CR_EP4_SIZE_POS)
+#define USB_CR_EP4_SIZE_UMSK  (~(((1U << USB_CR_EP4_SIZE_LEN) - 1) << USB_CR_EP4_SIZE_POS))
+#define USB_CR_EP4_DIR        USB_CR_EP4_DIR
+#define USB_CR_EP4_DIR_POS    (11U)
+#define USB_CR_EP4_DIR_LEN    (2U)
+#define USB_CR_EP4_DIR_MSK    (((1U << USB_CR_EP4_DIR_LEN) - 1) << USB_CR_EP4_DIR_POS)
+#define USB_CR_EP4_DIR_UMSK   (~(((1U << USB_CR_EP4_DIR_LEN) - 1) << USB_CR_EP4_DIR_POS))
+#define USB_CR_EP4_TYPE       USB_CR_EP4_TYPE
+#define USB_CR_EP4_TYPE_POS   (13U)
+#define USB_CR_EP4_TYPE_LEN   (3U)
+#define USB_CR_EP4_TYPE_MSK   (((1U << USB_CR_EP4_TYPE_LEN) - 1) << USB_CR_EP4_TYPE_POS)
+#define USB_CR_EP4_TYPE_UMSK  (~(((1U << USB_CR_EP4_TYPE_LEN) - 1) << USB_CR_EP4_TYPE_POS))
+#define USB_CR_EP4_STALL      USB_CR_EP4_STALL
+#define USB_CR_EP4_STALL_POS  (16U)
+#define USB_CR_EP4_STALL_LEN  (1U)
+#define USB_CR_EP4_STALL_MSK  (((1U << USB_CR_EP4_STALL_LEN) - 1) << USB_CR_EP4_STALL_POS)
+#define USB_CR_EP4_STALL_UMSK (~(((1U << USB_CR_EP4_STALL_LEN) - 1) << USB_CR_EP4_STALL_POS))
+#define USB_CR_EP4_NACK       USB_CR_EP4_NACK
+#define USB_CR_EP4_NACK_POS   (17U)
+#define USB_CR_EP4_NACK_LEN   (1U)
+#define USB_CR_EP4_NACK_MSK   (((1U << USB_CR_EP4_NACK_LEN) - 1) << USB_CR_EP4_NACK_POS)
+#define USB_CR_EP4_NACK_UMSK  (~(((1U << USB_CR_EP4_NACK_LEN) - 1) << USB_CR_EP4_NACK_POS))
+#define USB_CR_EP4_RDY        USB_CR_EP4_RDY
+#define USB_CR_EP4_RDY_POS    (18U)
+#define USB_CR_EP4_RDY_LEN    (1U)
+#define USB_CR_EP4_RDY_MSK    (((1U << USB_CR_EP4_RDY_LEN) - 1) << USB_CR_EP4_RDY_POS)
+#define USB_CR_EP4_RDY_UMSK   (~(((1U << USB_CR_EP4_RDY_LEN) - 1) << USB_CR_EP4_RDY_POS))
+#define USB_STS_EP4_RDY       USB_STS_EP4_RDY
+#define USB_STS_EP4_RDY_POS   (19U)
+#define USB_STS_EP4_RDY_LEN   (1U)
+#define USB_STS_EP4_RDY_MSK   (((1U << USB_STS_EP4_RDY_LEN) - 1) << USB_STS_EP4_RDY_POS)
+#define USB_STS_EP4_RDY_UMSK  (~(((1U << USB_STS_EP4_RDY_LEN) - 1) << USB_STS_EP4_RDY_POS))
+
+/* 0x50 : ep5_config */
+#define USB_EP5_CONFIG_OFFSET (0x50)
+#define USB_CR_EP5_SIZE       USB_CR_EP5_SIZE
+#define USB_CR_EP5_SIZE_POS   (0U)
+#define USB_CR_EP5_SIZE_LEN   (11U)
+#define USB_CR_EP5_SIZE_MSK   (((1U << USB_CR_EP5_SIZE_LEN) - 1) << USB_CR_EP5_SIZE_POS)
+#define USB_CR_EP5_SIZE_UMSK  (~(((1U << USB_CR_EP5_SIZE_LEN) - 1) << USB_CR_EP5_SIZE_POS))
+#define USB_CR_EP5_DIR        USB_CR_EP5_DIR
+#define USB_CR_EP5_DIR_POS    (11U)
+#define USB_CR_EP5_DIR_LEN    (2U)
+#define USB_CR_EP5_DIR_MSK    (((1U << USB_CR_EP5_DIR_LEN) - 1) << USB_CR_EP5_DIR_POS)
+#define USB_CR_EP5_DIR_UMSK   (~(((1U << USB_CR_EP5_DIR_LEN) - 1) << USB_CR_EP5_DIR_POS))
+#define USB_CR_EP5_TYPE       USB_CR_EP5_TYPE
+#define USB_CR_EP5_TYPE_POS   (13U)
+#define USB_CR_EP5_TYPE_LEN   (3U)
+#define USB_CR_EP5_TYPE_MSK   (((1U << USB_CR_EP5_TYPE_LEN) - 1) << USB_CR_EP5_TYPE_POS)
+#define USB_CR_EP5_TYPE_UMSK  (~(((1U << USB_CR_EP5_TYPE_LEN) - 1) << USB_CR_EP5_TYPE_POS))
+#define USB_CR_EP5_STALL      USB_CR_EP5_STALL
+#define USB_CR_EP5_STALL_POS  (16U)
+#define USB_CR_EP5_STALL_LEN  (1U)
+#define USB_CR_EP5_STALL_MSK  (((1U << USB_CR_EP5_STALL_LEN) - 1) << USB_CR_EP5_STALL_POS)
+#define USB_CR_EP5_STALL_UMSK (~(((1U << USB_CR_EP5_STALL_LEN) - 1) << USB_CR_EP5_STALL_POS))
+#define USB_CR_EP5_NACK       USB_CR_EP5_NACK
+#define USB_CR_EP5_NACK_POS   (17U)
+#define USB_CR_EP5_NACK_LEN   (1U)
+#define USB_CR_EP5_NACK_MSK   (((1U << USB_CR_EP5_NACK_LEN) - 1) << USB_CR_EP5_NACK_POS)
+#define USB_CR_EP5_NACK_UMSK  (~(((1U << USB_CR_EP5_NACK_LEN) - 1) << USB_CR_EP5_NACK_POS))
+#define USB_CR_EP5_RDY        USB_CR_EP5_RDY
+#define USB_CR_EP5_RDY_POS    (18U)
+#define USB_CR_EP5_RDY_LEN    (1U)
+#define USB_CR_EP5_RDY_MSK    (((1U << USB_CR_EP5_RDY_LEN) - 1) << USB_CR_EP5_RDY_POS)
+#define USB_CR_EP5_RDY_UMSK   (~(((1U << USB_CR_EP5_RDY_LEN) - 1) << USB_CR_EP5_RDY_POS))
+#define USB_STS_EP5_RDY       USB_STS_EP5_RDY
+#define USB_STS_EP5_RDY_POS   (19U)
+#define USB_STS_EP5_RDY_LEN   (1U)
+#define USB_STS_EP5_RDY_MSK   (((1U << USB_STS_EP5_RDY_LEN) - 1) << USB_STS_EP5_RDY_POS)
+#define USB_STS_EP5_RDY_UMSK  (~(((1U << USB_STS_EP5_RDY_LEN) - 1) << USB_STS_EP5_RDY_POS))
+
+/* 0x54 : ep6_config */
+#define USB_EP6_CONFIG_OFFSET (0x54)
+#define USB_CR_EP6_SIZE       USB_CR_EP6_SIZE
+#define USB_CR_EP6_SIZE_POS   (0U)
+#define USB_CR_EP6_SIZE_LEN   (11U)
+#define USB_CR_EP6_SIZE_MSK   (((1U << USB_CR_EP6_SIZE_LEN) - 1) << USB_CR_EP6_SIZE_POS)
+#define USB_CR_EP6_SIZE_UMSK  (~(((1U << USB_CR_EP6_SIZE_LEN) - 1) << USB_CR_EP6_SIZE_POS))
+#define USB_CR_EP6_DIR        USB_CR_EP6_DIR
+#define USB_CR_EP6_DIR_POS    (11U)
+#define USB_CR_EP6_DIR_LEN    (2U)
+#define USB_CR_EP6_DIR_MSK    (((1U << USB_CR_EP6_DIR_LEN) - 1) << USB_CR_EP6_DIR_POS)
+#define USB_CR_EP6_DIR_UMSK   (~(((1U << USB_CR_EP6_DIR_LEN) - 1) << USB_CR_EP6_DIR_POS))
+#define USB_CR_EP6_TYPE       USB_CR_EP6_TYPE
+#define USB_CR_EP6_TYPE_POS   (13U)
+#define USB_CR_EP6_TYPE_LEN   (3U)
+#define USB_CR_EP6_TYPE_MSK   (((1U << USB_CR_EP6_TYPE_LEN) - 1) << USB_CR_EP6_TYPE_POS)
+#define USB_CR_EP6_TYPE_UMSK  (~(((1U << USB_CR_EP6_TYPE_LEN) - 1) << USB_CR_EP6_TYPE_POS))
+#define USB_CR_EP6_STALL      USB_CR_EP6_STALL
+#define USB_CR_EP6_STALL_POS  (16U)
+#define USB_CR_EP6_STALL_LEN  (1U)
+#define USB_CR_EP6_STALL_MSK  (((1U << USB_CR_EP6_STALL_LEN) - 1) << USB_CR_EP6_STALL_POS)
+#define USB_CR_EP6_STALL_UMSK (~(((1U << USB_CR_EP6_STALL_LEN) - 1) << USB_CR_EP6_STALL_POS))
+#define USB_CR_EP6_NACK       USB_CR_EP6_NACK
+#define USB_CR_EP6_NACK_POS   (17U)
+#define USB_CR_EP6_NACK_LEN   (1U)
+#define USB_CR_EP6_NACK_MSK   (((1U << USB_CR_EP6_NACK_LEN) - 1) << USB_CR_EP6_NACK_POS)
+#define USB_CR_EP6_NACK_UMSK  (~(((1U << USB_CR_EP6_NACK_LEN) - 1) << USB_CR_EP6_NACK_POS))
+#define USB_CR_EP6_RDY        USB_CR_EP6_RDY
+#define USB_CR_EP6_RDY_POS    (18U)
+#define USB_CR_EP6_RDY_LEN    (1U)
+#define USB_CR_EP6_RDY_MSK    (((1U << USB_CR_EP6_RDY_LEN) - 1) << USB_CR_EP6_RDY_POS)
+#define USB_CR_EP6_RDY_UMSK   (~(((1U << USB_CR_EP6_RDY_LEN) - 1) << USB_CR_EP6_RDY_POS))
+#define USB_STS_EP6_RDY       USB_STS_EP6_RDY
+#define USB_STS_EP6_RDY_POS   (19U)
+#define USB_STS_EP6_RDY_LEN   (1U)
+#define USB_STS_EP6_RDY_MSK   (((1U << USB_STS_EP6_RDY_LEN) - 1) << USB_STS_EP6_RDY_POS)
+#define USB_STS_EP6_RDY_UMSK  (~(((1U << USB_STS_EP6_RDY_LEN) - 1) << USB_STS_EP6_RDY_POS))
+
+/* 0x58 : ep7_config */
+#define USB_EP7_CONFIG_OFFSET (0x58)
+#define USB_CR_EP7_SIZE       USB_CR_EP7_SIZE
+#define USB_CR_EP7_SIZE_POS   (0U)
+#define USB_CR_EP7_SIZE_LEN   (11U)
+#define USB_CR_EP7_SIZE_MSK   (((1U << USB_CR_EP7_SIZE_LEN) - 1) << USB_CR_EP7_SIZE_POS)
+#define USB_CR_EP7_SIZE_UMSK  (~(((1U << USB_CR_EP7_SIZE_LEN) - 1) << USB_CR_EP7_SIZE_POS))
+#define USB_CR_EP7_DIR        USB_CR_EP7_DIR
+#define USB_CR_EP7_DIR_POS    (11U)
+#define USB_CR_EP7_DIR_LEN    (2U)
+#define USB_CR_EP7_DIR_MSK    (((1U << USB_CR_EP7_DIR_LEN) - 1) << USB_CR_EP7_DIR_POS)
+#define USB_CR_EP7_DIR_UMSK   (~(((1U << USB_CR_EP7_DIR_LEN) - 1) << USB_CR_EP7_DIR_POS))
+#define USB_CR_EP7_TYPE       USB_CR_EP7_TYPE
+#define USB_CR_EP7_TYPE_POS   (13U)
+#define USB_CR_EP7_TYPE_LEN   (3U)
+#define USB_CR_EP7_TYPE_MSK   (((1U << USB_CR_EP7_TYPE_LEN) - 1) << USB_CR_EP7_TYPE_POS)
+#define USB_CR_EP7_TYPE_UMSK  (~(((1U << USB_CR_EP7_TYPE_LEN) - 1) << USB_CR_EP7_TYPE_POS))
+#define USB_CR_EP7_STALL      USB_CR_EP7_STALL
+#define USB_CR_EP7_STALL_POS  (16U)
+#define USB_CR_EP7_STALL_LEN  (1U)
+#define USB_CR_EP7_STALL_MSK  (((1U << USB_CR_EP7_STALL_LEN) - 1) << USB_CR_EP7_STALL_POS)
+#define USB_CR_EP7_STALL_UMSK (~(((1U << USB_CR_EP7_STALL_LEN) - 1) << USB_CR_EP7_STALL_POS))
+#define USB_CR_EP7_NACK       USB_CR_EP7_NACK
+#define USB_CR_EP7_NACK_POS   (17U)
+#define USB_CR_EP7_NACK_LEN   (1U)
+#define USB_CR_EP7_NACK_MSK   (((1U << USB_CR_EP7_NACK_LEN) - 1) << USB_CR_EP7_NACK_POS)
+#define USB_CR_EP7_NACK_UMSK  (~(((1U << USB_CR_EP7_NACK_LEN) - 1) << USB_CR_EP7_NACK_POS))
+#define USB_CR_EP7_RDY        USB_CR_EP7_RDY
+#define USB_CR_EP7_RDY_POS    (18U)
+#define USB_CR_EP7_RDY_LEN    (1U)
+#define USB_CR_EP7_RDY_MSK    (((1U << USB_CR_EP7_RDY_LEN) - 1) << USB_CR_EP7_RDY_POS)
+#define USB_CR_EP7_RDY_UMSK   (~(((1U << USB_CR_EP7_RDY_LEN) - 1) << USB_CR_EP7_RDY_POS))
+#define USB_STS_EP7_RDY       USB_STS_EP7_RDY
+#define USB_STS_EP7_RDY_POS   (19U)
+#define USB_STS_EP7_RDY_LEN   (1U)
+#define USB_STS_EP7_RDY_MSK   (((1U << USB_STS_EP7_RDY_LEN) - 1) << USB_STS_EP7_RDY_POS)
+#define USB_STS_EP7_RDY_UMSK  (~(((1U << USB_STS_EP7_RDY_LEN) - 1) << USB_STS_EP7_RDY_POS))
+
+/* 0x100 : ep0_fifo_config */
+#define USB_EP0_FIFO_CONFIG_OFFSET     (0x100)
+#define USB_EP0_DMA_TX_EN              USB_EP0_DMA_TX_EN
+#define USB_EP0_DMA_TX_EN_POS          (0U)
+#define USB_EP0_DMA_TX_EN_LEN          (1U)
+#define USB_EP0_DMA_TX_EN_MSK          (((1U << USB_EP0_DMA_TX_EN_LEN) - 1) << USB_EP0_DMA_TX_EN_POS)
+#define USB_EP0_DMA_TX_EN_UMSK         (~(((1U << USB_EP0_DMA_TX_EN_LEN) - 1) << USB_EP0_DMA_TX_EN_POS))
+#define USB_EP0_DMA_RX_EN              USB_EP0_DMA_RX_EN
+#define USB_EP0_DMA_RX_EN_POS          (1U)
+#define USB_EP0_DMA_RX_EN_LEN          (1U)
+#define USB_EP0_DMA_RX_EN_MSK          (((1U << USB_EP0_DMA_RX_EN_LEN) - 1) << USB_EP0_DMA_RX_EN_POS)
+#define USB_EP0_DMA_RX_EN_UMSK         (~(((1U << USB_EP0_DMA_RX_EN_LEN) - 1) << USB_EP0_DMA_RX_EN_POS))
+#define USB_EP0_TX_FIFO_CLR            USB_EP0_TX_FIFO_CLR
+#define USB_EP0_TX_FIFO_CLR_POS        (2U)
+#define USB_EP0_TX_FIFO_CLR_LEN        (1U)
+#define USB_EP0_TX_FIFO_CLR_MSK        (((1U << USB_EP0_TX_FIFO_CLR_LEN) - 1) << USB_EP0_TX_FIFO_CLR_POS)
+#define USB_EP0_TX_FIFO_CLR_UMSK       (~(((1U << USB_EP0_TX_FIFO_CLR_LEN) - 1) << USB_EP0_TX_FIFO_CLR_POS))
+#define USB_EP0_RX_FIFO_CLR            USB_EP0_RX_FIFO_CLR
+#define USB_EP0_RX_FIFO_CLR_POS        (3U)
+#define USB_EP0_RX_FIFO_CLR_LEN        (1U)
+#define USB_EP0_RX_FIFO_CLR_MSK        (((1U << USB_EP0_RX_FIFO_CLR_LEN) - 1) << USB_EP0_RX_FIFO_CLR_POS)
+#define USB_EP0_RX_FIFO_CLR_UMSK       (~(((1U << USB_EP0_RX_FIFO_CLR_LEN) - 1) << USB_EP0_RX_FIFO_CLR_POS))
+#define USB_EP0_TX_FIFO_OVERFLOW       USB_EP0_TX_FIFO_OVERFLOW
+#define USB_EP0_TX_FIFO_OVERFLOW_POS   (4U)
+#define USB_EP0_TX_FIFO_OVERFLOW_LEN   (1U)
+#define USB_EP0_TX_FIFO_OVERFLOW_MSK   (((1U << USB_EP0_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP0_TX_FIFO_OVERFLOW_POS)
+#define USB_EP0_TX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP0_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP0_TX_FIFO_OVERFLOW_POS))
+#define USB_EP0_TX_FIFO_UNDERFLOW      USB_EP0_TX_FIFO_UNDERFLOW
+#define USB_EP0_TX_FIFO_UNDERFLOW_POS  (5U)
+#define USB_EP0_TX_FIFO_UNDERFLOW_LEN  (1U)
+#define USB_EP0_TX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP0_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP0_TX_FIFO_UNDERFLOW_POS)
+#define USB_EP0_TX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP0_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP0_TX_FIFO_UNDERFLOW_POS))
+#define USB_EP0_RX_FIFO_OVERFLOW       USB_EP0_RX_FIFO_OVERFLOW
+#define USB_EP0_RX_FIFO_OVERFLOW_POS   (6U)
+#define USB_EP0_RX_FIFO_OVERFLOW_LEN   (1U)
+#define USB_EP0_RX_FIFO_OVERFLOW_MSK   (((1U << USB_EP0_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP0_RX_FIFO_OVERFLOW_POS)
+#define USB_EP0_RX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP0_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP0_RX_FIFO_OVERFLOW_POS))
+#define USB_EP0_RX_FIFO_UNDERFLOW      USB_EP0_RX_FIFO_UNDERFLOW
+#define USB_EP0_RX_FIFO_UNDERFLOW_POS  (7U)
+#define USB_EP0_RX_FIFO_UNDERFLOW_LEN  (1U)
+#define USB_EP0_RX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP0_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP0_RX_FIFO_UNDERFLOW_POS)
+#define USB_EP0_RX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP0_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP0_RX_FIFO_UNDERFLOW_POS))
+
+/* 0x104 : ep0_fifo_status */
+#define USB_EP0_FIFO_STATUS_OFFSET (0x104)
+#define USB_EP0_TX_FIFO_CNT        USB_EP0_TX_FIFO_CNT
+#define USB_EP0_TX_FIFO_CNT_POS    (0U)
+#define USB_EP0_TX_FIFO_CNT_LEN    (7U)
+#define USB_EP0_TX_FIFO_CNT_MSK    (((1U << USB_EP0_TX_FIFO_CNT_LEN) - 1) << USB_EP0_TX_FIFO_CNT_POS)
+#define USB_EP0_TX_FIFO_CNT_UMSK   (~(((1U << USB_EP0_TX_FIFO_CNT_LEN) - 1) << USB_EP0_TX_FIFO_CNT_POS))
+#define USB_EP0_TX_FIFO_EMPTY      USB_EP0_TX_FIFO_EMPTY
+#define USB_EP0_TX_FIFO_EMPTY_POS  (14U)
+#define USB_EP0_TX_FIFO_EMPTY_LEN  (1U)
+#define USB_EP0_TX_FIFO_EMPTY_MSK  (((1U << USB_EP0_TX_FIFO_EMPTY_LEN) - 1) << USB_EP0_TX_FIFO_EMPTY_POS)
+#define USB_EP0_TX_FIFO_EMPTY_UMSK (~(((1U << USB_EP0_TX_FIFO_EMPTY_LEN) - 1) << USB_EP0_TX_FIFO_EMPTY_POS))
+#define USB_EP0_TX_FIFO_FULL       USB_EP0_TX_FIFO_FULL
+#define USB_EP0_TX_FIFO_FULL_POS   (15U)
+#define USB_EP0_TX_FIFO_FULL_LEN   (1U)
+#define USB_EP0_TX_FIFO_FULL_MSK   (((1U << USB_EP0_TX_FIFO_FULL_LEN) - 1) << USB_EP0_TX_FIFO_FULL_POS)
+#define USB_EP0_TX_FIFO_FULL_UMSK  (~(((1U << USB_EP0_TX_FIFO_FULL_LEN) - 1) << USB_EP0_TX_FIFO_FULL_POS))
+#define USB_EP0_RX_FIFO_CNT        USB_EP0_RX_FIFO_CNT
+#define USB_EP0_RX_FIFO_CNT_POS    (16U)
+#define USB_EP0_RX_FIFO_CNT_LEN    (7U)
+#define USB_EP0_RX_FIFO_CNT_MSK    (((1U << USB_EP0_RX_FIFO_CNT_LEN) - 1) << USB_EP0_RX_FIFO_CNT_POS)
+#define USB_EP0_RX_FIFO_CNT_UMSK   (~(((1U << USB_EP0_RX_FIFO_CNT_LEN) - 1) << USB_EP0_RX_FIFO_CNT_POS))
+#define USB_EP0_RX_FIFO_EMPTY      USB_EP0_RX_FIFO_EMPTY
+#define USB_EP0_RX_FIFO_EMPTY_POS  (30U)
+#define USB_EP0_RX_FIFO_EMPTY_LEN  (1U)
+#define USB_EP0_RX_FIFO_EMPTY_MSK  (((1U << USB_EP0_RX_FIFO_EMPTY_LEN) - 1) << USB_EP0_RX_FIFO_EMPTY_POS)
+#define USB_EP0_RX_FIFO_EMPTY_UMSK (~(((1U << USB_EP0_RX_FIFO_EMPTY_LEN) - 1) << USB_EP0_RX_FIFO_EMPTY_POS))
+#define USB_EP0_RX_FIFO_FULL       USB_EP0_RX_FIFO_FULL
+#define USB_EP0_RX_FIFO_FULL_POS   (31U)
+#define USB_EP0_RX_FIFO_FULL_LEN   (1U)
+#define USB_EP0_RX_FIFO_FULL_MSK   (((1U << USB_EP0_RX_FIFO_FULL_LEN) - 1) << USB_EP0_RX_FIFO_FULL_POS)
+#define USB_EP0_RX_FIFO_FULL_UMSK  (~(((1U << USB_EP0_RX_FIFO_FULL_LEN) - 1) << USB_EP0_RX_FIFO_FULL_POS))
+
+/* 0x108 : ep0_tx_fifo_wdata */
+#define USB_EP0_TX_FIFO_WDATA_OFFSET (0x108)
+#define USB_EP0_TX_FIFO_WDATA        USB_EP0_TX_FIFO_WDATA
+#define USB_EP0_TX_FIFO_WDATA_POS    (0U)
+#define USB_EP0_TX_FIFO_WDATA_LEN    (8U)
+#define USB_EP0_TX_FIFO_WDATA_MSK    (((1U << USB_EP0_TX_FIFO_WDATA_LEN) - 1) << USB_EP0_TX_FIFO_WDATA_POS)
+#define USB_EP0_TX_FIFO_WDATA_UMSK   (~(((1U << USB_EP0_TX_FIFO_WDATA_LEN) - 1) << USB_EP0_TX_FIFO_WDATA_POS))
+
+/* 0x10C : ep0_rx_fifo_rdata */
+#define USB_EP0_RX_FIFO_RDATA_OFFSET (0x10C)
+#define USB_EP0_RX_FIFO_RDATA        USB_EP0_RX_FIFO_RDATA
+#define USB_EP0_RX_FIFO_RDATA_POS    (0U)
+#define USB_EP0_RX_FIFO_RDATA_LEN    (8U)
+#define USB_EP0_RX_FIFO_RDATA_MSK    (((1U << USB_EP0_RX_FIFO_RDATA_LEN) - 1) << USB_EP0_RX_FIFO_RDATA_POS)
+#define USB_EP0_RX_FIFO_RDATA_UMSK   (~(((1U << USB_EP0_RX_FIFO_RDATA_LEN) - 1) << USB_EP0_RX_FIFO_RDATA_POS))
+
+/* 0x110 : ep1_fifo_config */
+#define USB_EP1_FIFO_CONFIG_OFFSET     (0x110)
+#define USB_EP1_DMA_TX_EN              USB_EP1_DMA_TX_EN
+#define USB_EP1_DMA_TX_EN_POS          (0U)
+#define USB_EP1_DMA_TX_EN_LEN          (1U)
+#define USB_EP1_DMA_TX_EN_MSK          (((1U << USB_EP1_DMA_TX_EN_LEN) - 1) << USB_EP1_DMA_TX_EN_POS)
+#define USB_EP1_DMA_TX_EN_UMSK         (~(((1U << USB_EP1_DMA_TX_EN_LEN) - 1) << USB_EP1_DMA_TX_EN_POS))
+#define USB_EP1_DMA_RX_EN              USB_EP1_DMA_RX_EN
+#define USB_EP1_DMA_RX_EN_POS          (1U)
+#define USB_EP1_DMA_RX_EN_LEN          (1U)
+#define USB_EP1_DMA_RX_EN_MSK          (((1U << USB_EP1_DMA_RX_EN_LEN) - 1) << USB_EP1_DMA_RX_EN_POS)
+#define USB_EP1_DMA_RX_EN_UMSK         (~(((1U << USB_EP1_DMA_RX_EN_LEN) - 1) << USB_EP1_DMA_RX_EN_POS))
+#define USB_EP1_TX_FIFO_CLR            USB_EP1_TX_FIFO_CLR
+#define USB_EP1_TX_FIFO_CLR_POS        (2U)
+#define USB_EP1_TX_FIFO_CLR_LEN        (1U)
+#define USB_EP1_TX_FIFO_CLR_MSK        (((1U << USB_EP1_TX_FIFO_CLR_LEN) - 1) << USB_EP1_TX_FIFO_CLR_POS)
+#define USB_EP1_TX_FIFO_CLR_UMSK       (~(((1U << USB_EP1_TX_FIFO_CLR_LEN) - 1) << USB_EP1_TX_FIFO_CLR_POS))
+#define USB_EP1_RX_FIFO_CLR            USB_EP1_RX_FIFO_CLR
+#define USB_EP1_RX_FIFO_CLR_POS        (3U)
+#define USB_EP1_RX_FIFO_CLR_LEN        (1U)
+#define USB_EP1_RX_FIFO_CLR_MSK        (((1U << USB_EP1_RX_FIFO_CLR_LEN) - 1) << USB_EP1_RX_FIFO_CLR_POS)
+#define USB_EP1_RX_FIFO_CLR_UMSK       (~(((1U << USB_EP1_RX_FIFO_CLR_LEN) - 1) << USB_EP1_RX_FIFO_CLR_POS))
+#define USB_EP1_TX_FIFO_OVERFLOW       USB_EP1_TX_FIFO_OVERFLOW
+#define USB_EP1_TX_FIFO_OVERFLOW_POS   (4U)
+#define USB_EP1_TX_FIFO_OVERFLOW_LEN   (1U)
+#define USB_EP1_TX_FIFO_OVERFLOW_MSK   (((1U << USB_EP1_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP1_TX_FIFO_OVERFLOW_POS)
+#define USB_EP1_TX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP1_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP1_TX_FIFO_OVERFLOW_POS))
+#define USB_EP1_TX_FIFO_UNDERFLOW      USB_EP1_TX_FIFO_UNDERFLOW
+#define USB_EP1_TX_FIFO_UNDERFLOW_POS  (5U)
+#define USB_EP1_TX_FIFO_UNDERFLOW_LEN  (1U)
+#define USB_EP1_TX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP1_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP1_TX_FIFO_UNDERFLOW_POS)
+#define USB_EP1_TX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP1_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP1_TX_FIFO_UNDERFLOW_POS))
+#define USB_EP1_RX_FIFO_OVERFLOW       USB_EP1_RX_FIFO_OVERFLOW
+#define USB_EP1_RX_FIFO_OVERFLOW_POS   (6U)
+#define USB_EP1_RX_FIFO_OVERFLOW_LEN   (1U)
+#define USB_EP1_RX_FIFO_OVERFLOW_MSK   (((1U << USB_EP1_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP1_RX_FIFO_OVERFLOW_POS)
+#define USB_EP1_RX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP1_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP1_RX_FIFO_OVERFLOW_POS))
+#define USB_EP1_RX_FIFO_UNDERFLOW      USB_EP1_RX_FIFO_UNDERFLOW
+#define USB_EP1_RX_FIFO_UNDERFLOW_POS  (7U)
+#define USB_EP1_RX_FIFO_UNDERFLOW_LEN  (1U)
+#define USB_EP1_RX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP1_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP1_RX_FIFO_UNDERFLOW_POS)
+#define USB_EP1_RX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP1_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP1_RX_FIFO_UNDERFLOW_POS))
+
+/* 0x114 : ep1_fifo_status */
+#define USB_EP1_FIFO_STATUS_OFFSET (0x114)
+#define USB_EP1_TX_FIFO_CNT        USB_EP1_TX_FIFO_CNT
+#define USB_EP1_TX_FIFO_CNT_POS    (0U)
+#define USB_EP1_TX_FIFO_CNT_LEN    (7U)
+#define USB_EP1_TX_FIFO_CNT_MSK    (((1U << USB_EP1_TX_FIFO_CNT_LEN) - 1) << USB_EP1_TX_FIFO_CNT_POS)
+#define USB_EP1_TX_FIFO_CNT_UMSK   (~(((1U << USB_EP1_TX_FIFO_CNT_LEN) - 1) << USB_EP1_TX_FIFO_CNT_POS))
+#define USB_EP1_TX_FIFO_EMPTY      USB_EP1_TX_FIFO_EMPTY
+#define USB_EP1_TX_FIFO_EMPTY_POS  (14U)
+#define USB_EP1_TX_FIFO_EMPTY_LEN  (1U)
+#define USB_EP1_TX_FIFO_EMPTY_MSK  (((1U << USB_EP1_TX_FIFO_EMPTY_LEN) - 1) << USB_EP1_TX_FIFO_EMPTY_POS)
+#define USB_EP1_TX_FIFO_EMPTY_UMSK (~(((1U << USB_EP1_TX_FIFO_EMPTY_LEN) - 1) << USB_EP1_TX_FIFO_EMPTY_POS))
+#define USB_EP1_TX_FIFO_FULL       USB_EP1_TX_FIFO_FULL
+#define USB_EP1_TX_FIFO_FULL_POS   (15U)
+#define USB_EP1_TX_FIFO_FULL_LEN   (1U)
+#define USB_EP1_TX_FIFO_FULL_MSK   (((1U << USB_EP1_TX_FIFO_FULL_LEN) - 1) << USB_EP1_TX_FIFO_FULL_POS)
+#define USB_EP1_TX_FIFO_FULL_UMSK  (~(((1U << USB_EP1_TX_FIFO_FULL_LEN) - 1) << USB_EP1_TX_FIFO_FULL_POS))
+#define USB_EP1_RX_FIFO_CNT        USB_EP1_RX_FIFO_CNT
+#define USB_EP1_RX_FIFO_CNT_POS    (16U)
+#define USB_EP1_RX_FIFO_CNT_LEN    (7U)
+#define USB_EP1_RX_FIFO_CNT_MSK    (((1U << USB_EP1_RX_FIFO_CNT_LEN) - 1) << USB_EP1_RX_FIFO_CNT_POS)
+#define USB_EP1_RX_FIFO_CNT_UMSK   (~(((1U << USB_EP1_RX_FIFO_CNT_LEN) - 1) << USB_EP1_RX_FIFO_CNT_POS))
+#define USB_EP1_RX_FIFO_EMPTY      USB_EP1_RX_FIFO_EMPTY
+#define USB_EP1_RX_FIFO_EMPTY_POS  (30U)
+#define USB_EP1_RX_FIFO_EMPTY_LEN  (1U)
+#define USB_EP1_RX_FIFO_EMPTY_MSK  (((1U << USB_EP1_RX_FIFO_EMPTY_LEN) - 1) << USB_EP1_RX_FIFO_EMPTY_POS)
+#define USB_EP1_RX_FIFO_EMPTY_UMSK (~(((1U << USB_EP1_RX_FIFO_EMPTY_LEN) - 1) << USB_EP1_RX_FIFO_EMPTY_POS))
+#define USB_EP1_RX_FIFO_FULL       USB_EP1_RX_FIFO_FULL
+#define USB_EP1_RX_FIFO_FULL_POS   (31U)
+#define USB_EP1_RX_FIFO_FULL_LEN   (1U)
+#define USB_EP1_RX_FIFO_FULL_MSK   (((1U << USB_EP1_RX_FIFO_FULL_LEN) - 1) << USB_EP1_RX_FIFO_FULL_POS)
+#define USB_EP1_RX_FIFO_FULL_UMSK  (~(((1U << USB_EP1_RX_FIFO_FULL_LEN) - 1) << USB_EP1_RX_FIFO_FULL_POS))
+
+/* 0x118 : ep1_tx_fifo_wdata */
+#define USB_EP1_TX_FIFO_WDATA_OFFSET (0x118)
+#define USB_EP1_TX_FIFO_WDATA        USB_EP1_TX_FIFO_WDATA
+#define USB_EP1_TX_FIFO_WDATA_POS    (0U)
+#define USB_EP1_TX_FIFO_WDATA_LEN    (8U)
+#define USB_EP1_TX_FIFO_WDATA_MSK    (((1U << USB_EP1_TX_FIFO_WDATA_LEN) - 1) << USB_EP1_TX_FIFO_WDATA_POS)
+#define USB_EP1_TX_FIFO_WDATA_UMSK   (~(((1U << USB_EP1_TX_FIFO_WDATA_LEN) - 1) << USB_EP1_TX_FIFO_WDATA_POS))
+
+/* 0x11C : ep1_rx_fifo_rdata */
+#define USB_EP1_RX_FIFO_RDATA_OFFSET (0x11C)
+#define USB_EP1_RX_FIFO_RDATA        USB_EP1_RX_FIFO_RDATA
+#define USB_EP1_RX_FIFO_RDATA_POS    (0U)
+#define USB_EP1_RX_FIFO_RDATA_LEN    (8U)
+#define USB_EP1_RX_FIFO_RDATA_MSK    (((1U << USB_EP1_RX_FIFO_RDATA_LEN) - 1) << USB_EP1_RX_FIFO_RDATA_POS)
+#define USB_EP1_RX_FIFO_RDATA_UMSK   (~(((1U << USB_EP1_RX_FIFO_RDATA_LEN) - 1) << USB_EP1_RX_FIFO_RDATA_POS))
+
+/* 0x120 : ep2_fifo_config */
+#define USB_EP2_FIFO_CONFIG_OFFSET     (0x120)
+#define USB_EP2_DMA_TX_EN              USB_EP2_DMA_TX_EN
+#define USB_EP2_DMA_TX_EN_POS          (0U)
+#define USB_EP2_DMA_TX_EN_LEN          (1U)
+#define USB_EP2_DMA_TX_EN_MSK          (((1U << USB_EP2_DMA_TX_EN_LEN) - 1) << USB_EP2_DMA_TX_EN_POS)
+#define USB_EP2_DMA_TX_EN_UMSK         (~(((1U << USB_EP2_DMA_TX_EN_LEN) - 1) << USB_EP2_DMA_TX_EN_POS))
+#define USB_EP2_DMA_RX_EN              USB_EP2_DMA_RX_EN
+#define USB_EP2_DMA_RX_EN_POS          (1U)
+#define USB_EP2_DMA_RX_EN_LEN          (1U)
+#define USB_EP2_DMA_RX_EN_MSK          (((1U << USB_EP2_DMA_RX_EN_LEN) - 1) << USB_EP2_DMA_RX_EN_POS)
+#define USB_EP2_DMA_RX_EN_UMSK         (~(((1U << USB_EP2_DMA_RX_EN_LEN) - 1) << USB_EP2_DMA_RX_EN_POS))
+#define USB_EP2_TX_FIFO_CLR            USB_EP2_TX_FIFO_CLR
+#define USB_EP2_TX_FIFO_CLR_POS        (2U)
+#define USB_EP2_TX_FIFO_CLR_LEN        (1U)
+#define USB_EP2_TX_FIFO_CLR_MSK        (((1U << USB_EP2_TX_FIFO_CLR_LEN) - 1) << USB_EP2_TX_FIFO_CLR_POS)
+#define USB_EP2_TX_FIFO_CLR_UMSK       (~(((1U << USB_EP2_TX_FIFO_CLR_LEN) - 1) << USB_EP2_TX_FIFO_CLR_POS))
+#define USB_EP2_RX_FIFO_CLR            USB_EP2_RX_FIFO_CLR
+#define USB_EP2_RX_FIFO_CLR_POS        (3U)
+#define USB_EP2_RX_FIFO_CLR_LEN        (1U)
+#define USB_EP2_RX_FIFO_CLR_MSK        (((1U << USB_EP2_RX_FIFO_CLR_LEN) - 1) << USB_EP2_RX_FIFO_CLR_POS)
+#define USB_EP2_RX_FIFO_CLR_UMSK       (~(((1U << USB_EP2_RX_FIFO_CLR_LEN) - 1) << USB_EP2_RX_FIFO_CLR_POS))
+#define USB_EP2_TX_FIFO_OVERFLOW       USB_EP2_TX_FIFO_OVERFLOW
+#define USB_EP2_TX_FIFO_OVERFLOW_POS   (4U)
+#define USB_EP2_TX_FIFO_OVERFLOW_LEN   (1U)
+#define USB_EP2_TX_FIFO_OVERFLOW_MSK   (((1U << USB_EP2_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP2_TX_FIFO_OVERFLOW_POS)
+#define USB_EP2_TX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP2_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP2_TX_FIFO_OVERFLOW_POS))
+#define USB_EP2_TX_FIFO_UNDERFLOW      USB_EP2_TX_FIFO_UNDERFLOW
+#define USB_EP2_TX_FIFO_UNDERFLOW_POS  (5U)
+#define USB_EP2_TX_FIFO_UNDERFLOW_LEN  (1U)
+#define USB_EP2_TX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP2_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP2_TX_FIFO_UNDERFLOW_POS)
+#define USB_EP2_TX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP2_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP2_TX_FIFO_UNDERFLOW_POS))
+#define USB_EP2_RX_FIFO_OVERFLOW       USB_EP2_RX_FIFO_OVERFLOW
+#define USB_EP2_RX_FIFO_OVERFLOW_POS   (6U)
+#define USB_EP2_RX_FIFO_OVERFLOW_LEN   (1U)
+#define USB_EP2_RX_FIFO_OVERFLOW_MSK   (((1U << USB_EP2_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP2_RX_FIFO_OVERFLOW_POS)
+#define USB_EP2_RX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP2_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP2_RX_FIFO_OVERFLOW_POS))
+#define USB_EP2_RX_FIFO_UNDERFLOW      USB_EP2_RX_FIFO_UNDERFLOW
+#define USB_EP2_RX_FIFO_UNDERFLOW_POS  (7U)
+#define USB_EP2_RX_FIFO_UNDERFLOW_LEN  (1U)
+#define USB_EP2_RX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP2_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP2_RX_FIFO_UNDERFLOW_POS)
+#define USB_EP2_RX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP2_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP2_RX_FIFO_UNDERFLOW_POS))
+
+/* 0x124 : ep2_fifo_status */
+#define USB_EP2_FIFO_STATUS_OFFSET (0x124)
+#define USB_EP2_TX_FIFO_CNT        USB_EP2_TX_FIFO_CNT
+#define USB_EP2_TX_FIFO_CNT_POS    (0U)
+#define USB_EP2_TX_FIFO_CNT_LEN    (7U)
+#define USB_EP2_TX_FIFO_CNT_MSK    (((1U << USB_EP2_TX_FIFO_CNT_LEN) - 1) << USB_EP2_TX_FIFO_CNT_POS)
+#define USB_EP2_TX_FIFO_CNT_UMSK   (~(((1U << USB_EP2_TX_FIFO_CNT_LEN) - 1) << USB_EP2_TX_FIFO_CNT_POS))
+#define USB_EP2_TX_FIFO_EMPTY      USB_EP2_TX_FIFO_EMPTY
+#define USB_EP2_TX_FIFO_EMPTY_POS  (14U)
+#define USB_EP2_TX_FIFO_EMPTY_LEN  (1U)
+#define USB_EP2_TX_FIFO_EMPTY_MSK  (((1U << USB_EP2_TX_FIFO_EMPTY_LEN) - 1) << USB_EP2_TX_FIFO_EMPTY_POS)
+#define USB_EP2_TX_FIFO_EMPTY_UMSK (~(((1U << USB_EP2_TX_FIFO_EMPTY_LEN) - 1) << USB_EP2_TX_FIFO_EMPTY_POS))
+#define USB_EP2_TX_FIFO_FULL       USB_EP2_TX_FIFO_FULL
+#define USB_EP2_TX_FIFO_FULL_POS   (15U)
+#define USB_EP2_TX_FIFO_FULL_LEN   (1U)
+#define USB_EP2_TX_FIFO_FULL_MSK   (((1U << USB_EP2_TX_FIFO_FULL_LEN) - 1) << USB_EP2_TX_FIFO_FULL_POS)
+#define USB_EP2_TX_FIFO_FULL_UMSK  (~(((1U << USB_EP2_TX_FIFO_FULL_LEN) - 1) << USB_EP2_TX_FIFO_FULL_POS))
+#define USB_EP2_RX_FIFO_CNT        USB_EP2_RX_FIFO_CNT
+#define USB_EP2_RX_FIFO_CNT_POS    (16U)
+#define USB_EP2_RX_FIFO_CNT_LEN    (7U)
+#define USB_EP2_RX_FIFO_CNT_MSK    (((1U << USB_EP2_RX_FIFO_CNT_LEN) - 1) << USB_EP2_RX_FIFO_CNT_POS)
+#define USB_EP2_RX_FIFO_CNT_UMSK   (~(((1U << USB_EP2_RX_FIFO_CNT_LEN) - 1) << USB_EP2_RX_FIFO_CNT_POS))
+#define USB_EP2_RX_FIFO_EMPTY      USB_EP2_RX_FIFO_EMPTY
+#define USB_EP2_RX_FIFO_EMPTY_POS  (30U)
+#define USB_EP2_RX_FIFO_EMPTY_LEN  (1U)
+#define USB_EP2_RX_FIFO_EMPTY_MSK  (((1U << USB_EP2_RX_FIFO_EMPTY_LEN) - 1) << USB_EP2_RX_FIFO_EMPTY_POS)
+#define USB_EP2_RX_FIFO_EMPTY_UMSK (~(((1U << USB_EP2_RX_FIFO_EMPTY_LEN) - 1) << USB_EP2_RX_FIFO_EMPTY_POS))
+#define USB_EP2_RX_FIFO_FULL       USB_EP2_RX_FIFO_FULL
+#define USB_EP2_RX_FIFO_FULL_POS   (31U)
+#define USB_EP2_RX_FIFO_FULL_LEN   (1U)
+#define USB_EP2_RX_FIFO_FULL_MSK   (((1U << USB_EP2_RX_FIFO_FULL_LEN) - 1) << USB_EP2_RX_FIFO_FULL_POS)
+#define USB_EP2_RX_FIFO_FULL_UMSK  (~(((1U << USB_EP2_RX_FIFO_FULL_LEN) - 1) << USB_EP2_RX_FIFO_FULL_POS))
+
+/* 0x128 : ep2_tx_fifo_wdata */
+#define USB_EP2_TX_FIFO_WDATA_OFFSET (0x128)
+#define USB_EP2_TX_FIFO_WDATA        USB_EP2_TX_FIFO_WDATA
+#define USB_EP2_TX_FIFO_WDATA_POS    (0U)
+#define USB_EP2_TX_FIFO_WDATA_LEN    (8U)
+#define USB_EP2_TX_FIFO_WDATA_MSK    (((1U << USB_EP2_TX_FIFO_WDATA_LEN) - 1) << USB_EP2_TX_FIFO_WDATA_POS)
+#define USB_EP2_TX_FIFO_WDATA_UMSK   (~(((1U << USB_EP2_TX_FIFO_WDATA_LEN) - 1) << USB_EP2_TX_FIFO_WDATA_POS))
+
+/* 0x12C : ep2_rx_fifo_rdata */
+#define USB_EP2_RX_FIFO_RDATA_OFFSET (0x12C)
+#define USB_EP2_RX_FIFO_RDATA        USB_EP2_RX_FIFO_RDATA
+#define USB_EP2_RX_FIFO_RDATA_POS    (0U)
+#define USB_EP2_RX_FIFO_RDATA_LEN    (8U)
+#define USB_EP2_RX_FIFO_RDATA_MSK    (((1U << USB_EP2_RX_FIFO_RDATA_LEN) - 1) << USB_EP2_RX_FIFO_RDATA_POS)
+#define USB_EP2_RX_FIFO_RDATA_UMSK   (~(((1U << USB_EP2_RX_FIFO_RDATA_LEN) - 1) << USB_EP2_RX_FIFO_RDATA_POS))
+
+/* 0x130 : ep3_fifo_config */
+#define USB_EP3_FIFO_CONFIG_OFFSET     (0x130)
+#define USB_EP3_DMA_TX_EN              USB_EP3_DMA_TX_EN
+#define USB_EP3_DMA_TX_EN_POS          (0U)
+#define USB_EP3_DMA_TX_EN_LEN          (1U)
+#define USB_EP3_DMA_TX_EN_MSK          (((1U << USB_EP3_DMA_TX_EN_LEN) - 1) << USB_EP3_DMA_TX_EN_POS)
+#define USB_EP3_DMA_TX_EN_UMSK         (~(((1U << USB_EP3_DMA_TX_EN_LEN) - 1) << USB_EP3_DMA_TX_EN_POS))
+#define USB_EP3_DMA_RX_EN              USB_EP3_DMA_RX_EN
+#define USB_EP3_DMA_RX_EN_POS          (1U)
+#define USB_EP3_DMA_RX_EN_LEN          (1U)
+#define USB_EP3_DMA_RX_EN_MSK          (((1U << USB_EP3_DMA_RX_EN_LEN) - 1) << USB_EP3_DMA_RX_EN_POS)
+#define USB_EP3_DMA_RX_EN_UMSK         (~(((1U << USB_EP3_DMA_RX_EN_LEN) - 1) << USB_EP3_DMA_RX_EN_POS))
+#define USB_EP3_TX_FIFO_CLR            USB_EP3_TX_FIFO_CLR
+#define USB_EP3_TX_FIFO_CLR_POS        (2U)
+#define USB_EP3_TX_FIFO_CLR_LEN        (1U)
+#define USB_EP3_TX_FIFO_CLR_MSK        (((1U << USB_EP3_TX_FIFO_CLR_LEN) - 1) << USB_EP3_TX_FIFO_CLR_POS)
+#define USB_EP3_TX_FIFO_CLR_UMSK       (~(((1U << USB_EP3_TX_FIFO_CLR_LEN) - 1) << USB_EP3_TX_FIFO_CLR_POS))
+#define USB_EP3_RX_FIFO_CLR            USB_EP3_RX_FIFO_CLR
+#define USB_EP3_RX_FIFO_CLR_POS        (3U)
+#define USB_EP3_RX_FIFO_CLR_LEN        (1U)
+#define USB_EP3_RX_FIFO_CLR_MSK        (((1U << USB_EP3_RX_FIFO_CLR_LEN) - 1) << USB_EP3_RX_FIFO_CLR_POS)
+#define USB_EP3_RX_FIFO_CLR_UMSK       (~(((1U << USB_EP3_RX_FIFO_CLR_LEN) - 1) << USB_EP3_RX_FIFO_CLR_POS))
+#define USB_EP3_TX_FIFO_OVERFLOW       USB_EP3_TX_FIFO_OVERFLOW
+#define USB_EP3_TX_FIFO_OVERFLOW_POS   (4U)
+#define USB_EP3_TX_FIFO_OVERFLOW_LEN   (1U)
+#define USB_EP3_TX_FIFO_OVERFLOW_MSK   (((1U << USB_EP3_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP3_TX_FIFO_OVERFLOW_POS)
+#define USB_EP3_TX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP3_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP3_TX_FIFO_OVERFLOW_POS))
+#define USB_EP3_TX_FIFO_UNDERFLOW      USB_EP3_TX_FIFO_UNDERFLOW
+#define USB_EP3_TX_FIFO_UNDERFLOW_POS  (5U)
+#define USB_EP3_TX_FIFO_UNDERFLOW_LEN  (1U)
+#define USB_EP3_TX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP3_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP3_TX_FIFO_UNDERFLOW_POS)
+#define USB_EP3_TX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP3_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP3_TX_FIFO_UNDERFLOW_POS))
+#define USB_EP3_RX_FIFO_OVERFLOW       USB_EP3_RX_FIFO_OVERFLOW
+#define USB_EP3_RX_FIFO_OVERFLOW_POS   (6U)
+#define USB_EP3_RX_FIFO_OVERFLOW_LEN   (1U)
+#define USB_EP3_RX_FIFO_OVERFLOW_MSK   (((1U << USB_EP3_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP3_RX_FIFO_OVERFLOW_POS)
+#define USB_EP3_RX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP3_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP3_RX_FIFO_OVERFLOW_POS))
+#define USB_EP3_RX_FIFO_UNDERFLOW      USB_EP3_RX_FIFO_UNDERFLOW
+#define USB_EP3_RX_FIFO_UNDERFLOW_POS  (7U)
+#define USB_EP3_RX_FIFO_UNDERFLOW_LEN  (1U)
+#define USB_EP3_RX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP3_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP3_RX_FIFO_UNDERFLOW_POS)
+#define USB_EP3_RX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP3_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP3_RX_FIFO_UNDERFLOW_POS))
+
+/* 0x134 : ep3_fifo_status */
+#define USB_EP3_FIFO_STATUS_OFFSET (0x134)
+#define USB_EP3_TX_FIFO_CNT        USB_EP3_TX_FIFO_CNT
+#define USB_EP3_TX_FIFO_CNT_POS    (0U)
+#define USB_EP3_TX_FIFO_CNT_LEN    (7U)
+#define USB_EP3_TX_FIFO_CNT_MSK    (((1U << USB_EP3_TX_FIFO_CNT_LEN) - 1) << USB_EP3_TX_FIFO_CNT_POS)
+#define USB_EP3_TX_FIFO_CNT_UMSK   (~(((1U << USB_EP3_TX_FIFO_CNT_LEN) - 1) << USB_EP3_TX_FIFO_CNT_POS))
+#define USB_EP3_TX_FIFO_EMPTY      USB_EP3_TX_FIFO_EMPTY
+#define USB_EP3_TX_FIFO_EMPTY_POS  (14U)
+#define USB_EP3_TX_FIFO_EMPTY_LEN  (1U)
+#define USB_EP3_TX_FIFO_EMPTY_MSK  (((1U << USB_EP3_TX_FIFO_EMPTY_LEN) - 1) << USB_EP3_TX_FIFO_EMPTY_POS)
+#define USB_EP3_TX_FIFO_EMPTY_UMSK (~(((1U << USB_EP3_TX_FIFO_EMPTY_LEN) - 1) << USB_EP3_TX_FIFO_EMPTY_POS))
+#define USB_EP3_TX_FIFO_FULL       USB_EP3_TX_FIFO_FULL
+#define USB_EP3_TX_FIFO_FULL_POS   (15U)
+#define USB_EP3_TX_FIFO_FULL_LEN   (1U)
+#define USB_EP3_TX_FIFO_FULL_MSK   (((1U << USB_EP3_TX_FIFO_FULL_LEN) - 1) << USB_EP3_TX_FIFO_FULL_POS)
+#define USB_EP3_TX_FIFO_FULL_UMSK  (~(((1U << USB_EP3_TX_FIFO_FULL_LEN) - 1) << USB_EP3_TX_FIFO_FULL_POS))
+#define USB_EP3_RX_FIFO_CNT        USB_EP3_RX_FIFO_CNT
+#define USB_EP3_RX_FIFO_CNT_POS    (16U)
+#define USB_EP3_RX_FIFO_CNT_LEN    (7U)
+#define USB_EP3_RX_FIFO_CNT_MSK    (((1U << USB_EP3_RX_FIFO_CNT_LEN) - 1) << USB_EP3_RX_FIFO_CNT_POS)
+#define USB_EP3_RX_FIFO_CNT_UMSK   (~(((1U << USB_EP3_RX_FIFO_CNT_LEN) - 1) << USB_EP3_RX_FIFO_CNT_POS))
+#define USB_EP3_RX_FIFO_EMPTY      USB_EP3_RX_FIFO_EMPTY
+#define USB_EP3_RX_FIFO_EMPTY_POS  (30U)
+#define USB_EP3_RX_FIFO_EMPTY_LEN  (1U)
+#define USB_EP3_RX_FIFO_EMPTY_MSK  (((1U << USB_EP3_RX_FIFO_EMPTY_LEN) - 1) << USB_EP3_RX_FIFO_EMPTY_POS)
+#define USB_EP3_RX_FIFO_EMPTY_UMSK (~(((1U << USB_EP3_RX_FIFO_EMPTY_LEN) - 1) << USB_EP3_RX_FIFO_EMPTY_POS))
+#define USB_EP3_RX_FIFO_FULL       USB_EP3_RX_FIFO_FULL
+#define USB_EP3_RX_FIFO_FULL_POS   (31U)
+#define USB_EP3_RX_FIFO_FULL_LEN   (1U)
+#define USB_EP3_RX_FIFO_FULL_MSK   (((1U << USB_EP3_RX_FIFO_FULL_LEN) - 1) << USB_EP3_RX_FIFO_FULL_POS)
+#define USB_EP3_RX_FIFO_FULL_UMSK  (~(((1U << USB_EP3_RX_FIFO_FULL_LEN) - 1) << USB_EP3_RX_FIFO_FULL_POS))
+
+/* 0x138 : ep3_tx_fifo_wdata */
+#define USB_EP3_TX_FIFO_WDATA_OFFSET (0x138)
+#define USB_EP3_TX_FIFO_WDATA        USB_EP3_TX_FIFO_WDATA
+#define USB_EP3_TX_FIFO_WDATA_POS    (0U)
+#define USB_EP3_TX_FIFO_WDATA_LEN    (8U)
+#define USB_EP3_TX_FIFO_WDATA_MSK    (((1U << USB_EP3_TX_FIFO_WDATA_LEN) - 1) << USB_EP3_TX_FIFO_WDATA_POS)
+#define USB_EP3_TX_FIFO_WDATA_UMSK   (~(((1U << USB_EP3_TX_FIFO_WDATA_LEN) - 1) << USB_EP3_TX_FIFO_WDATA_POS))
+
+/* 0x13C : ep3_rx_fifo_rdata */
+#define USB_EP3_RX_FIFO_RDATA_OFFSET (0x13C)
+#define USB_EP3_RX_FIFO_RDATA        USB_EP3_RX_FIFO_RDATA
+#define USB_EP3_RX_FIFO_RDATA_POS    (0U)
+#define USB_EP3_RX_FIFO_RDATA_LEN    (8U)
+#define USB_EP3_RX_FIFO_RDATA_MSK    (((1U << USB_EP3_RX_FIFO_RDATA_LEN) - 1) << USB_EP3_RX_FIFO_RDATA_POS)
+#define USB_EP3_RX_FIFO_RDATA_UMSK   (~(((1U << USB_EP3_RX_FIFO_RDATA_LEN) - 1) << USB_EP3_RX_FIFO_RDATA_POS))
+
+/* 0x140 : ep4_fifo_config */
+#define USB_EP4_FIFO_CONFIG_OFFSET     (0x140)
+#define USB_EP4_DMA_TX_EN              USB_EP4_DMA_TX_EN
+#define USB_EP4_DMA_TX_EN_POS          (0U)
+#define USB_EP4_DMA_TX_EN_LEN          (1U)
+#define USB_EP4_DMA_TX_EN_MSK          (((1U << USB_EP4_DMA_TX_EN_LEN) - 1) << USB_EP4_DMA_TX_EN_POS)
+#define USB_EP4_DMA_TX_EN_UMSK         (~(((1U << USB_EP4_DMA_TX_EN_LEN) - 1) << USB_EP4_DMA_TX_EN_POS))
+#define USB_EP4_DMA_RX_EN              USB_EP4_DMA_RX_EN
+#define USB_EP4_DMA_RX_EN_POS          (1U)
+#define USB_EP4_DMA_RX_EN_LEN          (1U)
+#define USB_EP4_DMA_RX_EN_MSK          (((1U << USB_EP4_DMA_RX_EN_LEN) - 1) << USB_EP4_DMA_RX_EN_POS)
+#define USB_EP4_DMA_RX_EN_UMSK         (~(((1U << USB_EP4_DMA_RX_EN_LEN) - 1) << USB_EP4_DMA_RX_EN_POS))
+#define USB_EP4_TX_FIFO_CLR            USB_EP4_TX_FIFO_CLR
+#define USB_EP4_TX_FIFO_CLR_POS        (2U)
+#define USB_EP4_TX_FIFO_CLR_LEN        (1U)
+#define USB_EP4_TX_FIFO_CLR_MSK        (((1U << USB_EP4_TX_FIFO_CLR_LEN) - 1) << USB_EP4_TX_FIFO_CLR_POS)
+#define USB_EP4_TX_FIFO_CLR_UMSK       (~(((1U << USB_EP4_TX_FIFO_CLR_LEN) - 1) << USB_EP4_TX_FIFO_CLR_POS))
+#define USB_EP4_RX_FIFO_CLR            USB_EP4_RX_FIFO_CLR
+#define USB_EP4_RX_FIFO_CLR_POS        (3U)
+#define USB_EP4_RX_FIFO_CLR_LEN        (1U)
+#define USB_EP4_RX_FIFO_CLR_MSK        (((1U << USB_EP4_RX_FIFO_CLR_LEN) - 1) << USB_EP4_RX_FIFO_CLR_POS)
+#define USB_EP4_RX_FIFO_CLR_UMSK       (~(((1U << USB_EP4_RX_FIFO_CLR_LEN) - 1) << USB_EP4_RX_FIFO_CLR_POS))
+#define USB_EP4_TX_FIFO_OVERFLOW       USB_EP4_TX_FIFO_OVERFLOW
+#define USB_EP4_TX_FIFO_OVERFLOW_POS   (4U)
+#define USB_EP4_TX_FIFO_OVERFLOW_LEN   (1U)
+#define USB_EP4_TX_FIFO_OVERFLOW_MSK   (((1U << USB_EP4_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP4_TX_FIFO_OVERFLOW_POS)
+#define USB_EP4_TX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP4_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP4_TX_FIFO_OVERFLOW_POS))
+#define USB_EP4_TX_FIFO_UNDERFLOW      USB_EP4_TX_FIFO_UNDERFLOW
+#define USB_EP4_TX_FIFO_UNDERFLOW_POS  (5U)
+#define USB_EP4_TX_FIFO_UNDERFLOW_LEN  (1U)
+#define USB_EP4_TX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP4_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP4_TX_FIFO_UNDERFLOW_POS)
+#define USB_EP4_TX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP4_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP4_TX_FIFO_UNDERFLOW_POS))
+#define USB_EP4_RX_FIFO_OVERFLOW       USB_EP4_RX_FIFO_OVERFLOW
+#define USB_EP4_RX_FIFO_OVERFLOW_POS   (6U)
+#define USB_EP4_RX_FIFO_OVERFLOW_LEN   (1U)
+#define USB_EP4_RX_FIFO_OVERFLOW_MSK   (((1U << USB_EP4_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP4_RX_FIFO_OVERFLOW_POS)
+#define USB_EP4_RX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP4_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP4_RX_FIFO_OVERFLOW_POS))
+#define USB_EP4_RX_FIFO_UNDERFLOW      USB_EP4_RX_FIFO_UNDERFLOW
+#define USB_EP4_RX_FIFO_UNDERFLOW_POS  (7U)
+#define USB_EP4_RX_FIFO_UNDERFLOW_LEN  (1U)
+#define USB_EP4_RX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP4_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP4_RX_FIFO_UNDERFLOW_POS)
+#define USB_EP4_RX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP4_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP4_RX_FIFO_UNDERFLOW_POS))
+
+/* 0x144 : ep4_fifo_status */
+#define USB_EP4_FIFO_STATUS_OFFSET (0x144)
+#define USB_EP4_TX_FIFO_CNT        USB_EP4_TX_FIFO_CNT
+#define USB_EP4_TX_FIFO_CNT_POS    (0U)
+#define USB_EP4_TX_FIFO_CNT_LEN    (7U)
+#define USB_EP4_TX_FIFO_CNT_MSK    (((1U << USB_EP4_TX_FIFO_CNT_LEN) - 1) << USB_EP4_TX_FIFO_CNT_POS)
+#define USB_EP4_TX_FIFO_CNT_UMSK   (~(((1U << USB_EP4_TX_FIFO_CNT_LEN) - 1) << USB_EP4_TX_FIFO_CNT_POS))
+#define USB_EP4_TX_FIFO_EMPTY      USB_EP4_TX_FIFO_EMPTY
+#define USB_EP4_TX_FIFO_EMPTY_POS  (14U)
+#define USB_EP4_TX_FIFO_EMPTY_LEN  (1U)
+#define USB_EP4_TX_FIFO_EMPTY_MSK  (((1U << USB_EP4_TX_FIFO_EMPTY_LEN) - 1) << USB_EP4_TX_FIFO_EMPTY_POS)
+#define USB_EP4_TX_FIFO_EMPTY_UMSK (~(((1U << USB_EP4_TX_FIFO_EMPTY_LEN) - 1) << USB_EP4_TX_FIFO_EMPTY_POS))
+#define USB_EP4_TX_FIFO_FULL       USB_EP4_TX_FIFO_FULL
+#define USB_EP4_TX_FIFO_FULL_POS   (15U)
+#define USB_EP4_TX_FIFO_FULL_LEN   (1U)
+#define USB_EP4_TX_FIFO_FULL_MSK   (((1U << USB_EP4_TX_FIFO_FULL_LEN) - 1) << USB_EP4_TX_FIFO_FULL_POS)
+#define USB_EP4_TX_FIFO_FULL_UMSK  (~(((1U << USB_EP4_TX_FIFO_FULL_LEN) - 1) << USB_EP4_TX_FIFO_FULL_POS))
+#define USB_EP4_RX_FIFO_CNT        USB_EP4_RX_FIFO_CNT
+#define USB_EP4_RX_FIFO_CNT_POS    (16U)
+#define USB_EP4_RX_FIFO_CNT_LEN    (7U)
+#define USB_EP4_RX_FIFO_CNT_MSK    (((1U << USB_EP4_RX_FIFO_CNT_LEN) - 1) << USB_EP4_RX_FIFO_CNT_POS)
+#define USB_EP4_RX_FIFO_CNT_UMSK   (~(((1U << USB_EP4_RX_FIFO_CNT_LEN) - 1) << USB_EP4_RX_FIFO_CNT_POS))
+#define USB_EP4_RX_FIFO_EMPTY      USB_EP4_RX_FIFO_EMPTY
+#define USB_EP4_RX_FIFO_EMPTY_POS  (30U)
+#define USB_EP4_RX_FIFO_EMPTY_LEN  (1U)
+#define USB_EP4_RX_FIFO_EMPTY_MSK  (((1U << USB_EP4_RX_FIFO_EMPTY_LEN) - 1) << USB_EP4_RX_FIFO_EMPTY_POS)
+#define USB_EP4_RX_FIFO_EMPTY_UMSK (~(((1U << USB_EP4_RX_FIFO_EMPTY_LEN) - 1) << USB_EP4_RX_FIFO_EMPTY_POS))
+#define USB_EP4_RX_FIFO_FULL       USB_EP4_RX_FIFO_FULL
+#define USB_EP4_RX_FIFO_FULL_POS   (31U)
+#define USB_EP4_RX_FIFO_FULL_LEN   (1U)
+#define USB_EP4_RX_FIFO_FULL_MSK   (((1U << USB_EP4_RX_FIFO_FULL_LEN) - 1) << USB_EP4_RX_FIFO_FULL_POS)
+#define USB_EP4_RX_FIFO_FULL_UMSK  (~(((1U << USB_EP4_RX_FIFO_FULL_LEN) - 1) << USB_EP4_RX_FIFO_FULL_POS))
+
+/* 0x148 : ep4_tx_fifo_wdata */
+#define USB_EP4_TX_FIFO_WDATA_OFFSET (0x148)
+#define USB_EP4_TX_FIFO_WDATA        USB_EP4_TX_FIFO_WDATA
+#define USB_EP4_TX_FIFO_WDATA_POS    (0U)
+#define USB_EP4_TX_FIFO_WDATA_LEN    (8U)
+#define USB_EP4_TX_FIFO_WDATA_MSK    (((1U << USB_EP4_TX_FIFO_WDATA_LEN) - 1) << USB_EP4_TX_FIFO_WDATA_POS)
+#define USB_EP4_TX_FIFO_WDATA_UMSK   (~(((1U << USB_EP4_TX_FIFO_WDATA_LEN) - 1) << USB_EP4_TX_FIFO_WDATA_POS))
+
+/* 0x14C : ep4_rx_fifo_rdata */
+#define USB_EP4_RX_FIFO_RDATA_OFFSET (0x14C)
+#define USB_EP4_RX_FIFO_RDATA        USB_EP4_RX_FIFO_RDATA
+#define USB_EP4_RX_FIFO_RDATA_POS    (0U)
+#define USB_EP4_RX_FIFO_RDATA_LEN    (8U)
+#define USB_EP4_RX_FIFO_RDATA_MSK    (((1U << USB_EP4_RX_FIFO_RDATA_LEN) - 1) << USB_EP4_RX_FIFO_RDATA_POS)
+#define USB_EP4_RX_FIFO_RDATA_UMSK   (~(((1U << USB_EP4_RX_FIFO_RDATA_LEN) - 1) << USB_EP4_RX_FIFO_RDATA_POS))
+
+/* 0x150 : ep5_fifo_config */
+#define USB_EP5_FIFO_CONFIG_OFFSET     (0x150)
+#define USB_EP5_DMA_TX_EN              USB_EP5_DMA_TX_EN
+#define USB_EP5_DMA_TX_EN_POS          (0U)
+#define USB_EP5_DMA_TX_EN_LEN          (1U)
+#define USB_EP5_DMA_TX_EN_MSK          (((1U << USB_EP5_DMA_TX_EN_LEN) - 1) << USB_EP5_DMA_TX_EN_POS)
+#define USB_EP5_DMA_TX_EN_UMSK         (~(((1U << USB_EP5_DMA_TX_EN_LEN) - 1) << USB_EP5_DMA_TX_EN_POS))
+#define USB_EP5_DMA_RX_EN              USB_EP5_DMA_RX_EN
+#define USB_EP5_DMA_RX_EN_POS          (1U)
+#define USB_EP5_DMA_RX_EN_LEN          (1U)
+#define USB_EP5_DMA_RX_EN_MSK          (((1U << USB_EP5_DMA_RX_EN_LEN) - 1) << USB_EP5_DMA_RX_EN_POS)
+#define USB_EP5_DMA_RX_EN_UMSK         (~(((1U << USB_EP5_DMA_RX_EN_LEN) - 1) << USB_EP5_DMA_RX_EN_POS))
+#define USB_EP5_TX_FIFO_CLR            USB_EP5_TX_FIFO_CLR
+#define USB_EP5_TX_FIFO_CLR_POS        (2U)
+#define USB_EP5_TX_FIFO_CLR_LEN        (1U)
+#define USB_EP5_TX_FIFO_CLR_MSK        (((1U << USB_EP5_TX_FIFO_CLR_LEN) - 1) << USB_EP5_TX_FIFO_CLR_POS)
+#define USB_EP5_TX_FIFO_CLR_UMSK       (~(((1U << USB_EP5_TX_FIFO_CLR_LEN) - 1) << USB_EP5_TX_FIFO_CLR_POS))
+#define USB_EP5_RX_FIFO_CLR            USB_EP5_RX_FIFO_CLR
+#define USB_EP5_RX_FIFO_CLR_POS        (3U)
+#define USB_EP5_RX_FIFO_CLR_LEN        (1U)
+#define USB_EP5_RX_FIFO_CLR_MSK        (((1U << USB_EP5_RX_FIFO_CLR_LEN) - 1) << USB_EP5_RX_FIFO_CLR_POS)
+#define USB_EP5_RX_FIFO_CLR_UMSK       (~(((1U << USB_EP5_RX_FIFO_CLR_LEN) - 1) << USB_EP5_RX_FIFO_CLR_POS))
+#define USB_EP5_TX_FIFO_OVERFLOW       USB_EP5_TX_FIFO_OVERFLOW
+#define USB_EP5_TX_FIFO_OVERFLOW_POS   (4U)
+#define USB_EP5_TX_FIFO_OVERFLOW_LEN   (1U)
+#define USB_EP5_TX_FIFO_OVERFLOW_MSK   (((1U << USB_EP5_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP5_TX_FIFO_OVERFLOW_POS)
+#define USB_EP5_TX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP5_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP5_TX_FIFO_OVERFLOW_POS))
+#define USB_EP5_TX_FIFO_UNDERFLOW      USB_EP5_TX_FIFO_UNDERFLOW
+#define USB_EP5_TX_FIFO_UNDERFLOW_POS  (5U)
+#define USB_EP5_TX_FIFO_UNDERFLOW_LEN  (1U)
+#define USB_EP5_TX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP5_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP5_TX_FIFO_UNDERFLOW_POS)
+#define USB_EP5_TX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP5_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP5_TX_FIFO_UNDERFLOW_POS))
+#define USB_EP5_RX_FIFO_OVERFLOW       USB_EP5_RX_FIFO_OVERFLOW
+#define USB_EP5_RX_FIFO_OVERFLOW_POS   (6U)
+#define USB_EP5_RX_FIFO_OVERFLOW_LEN   (1U)
+#define USB_EP5_RX_FIFO_OVERFLOW_MSK   (((1U << USB_EP5_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP5_RX_FIFO_OVERFLOW_POS)
+#define USB_EP5_RX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP5_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP5_RX_FIFO_OVERFLOW_POS))
+#define USB_EP5_RX_FIFO_UNDERFLOW      USB_EP5_RX_FIFO_UNDERFLOW
+#define USB_EP5_RX_FIFO_UNDERFLOW_POS  (7U)
+#define USB_EP5_RX_FIFO_UNDERFLOW_LEN  (1U)
+#define USB_EP5_RX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP5_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP5_RX_FIFO_UNDERFLOW_POS)
+#define USB_EP5_RX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP5_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP5_RX_FIFO_UNDERFLOW_POS))
+
+/* 0x154 : ep5_fifo_status */
+#define USB_EP5_FIFO_STATUS_OFFSET (0x154)
+#define USB_EP5_TX_FIFO_CNT        USB_EP5_TX_FIFO_CNT
+#define USB_EP5_TX_FIFO_CNT_POS    (0U)
+#define USB_EP5_TX_FIFO_CNT_LEN    (7U)
+#define USB_EP5_TX_FIFO_CNT_MSK    (((1U << USB_EP5_TX_FIFO_CNT_LEN) - 1) << USB_EP5_TX_FIFO_CNT_POS)
+#define USB_EP5_TX_FIFO_CNT_UMSK   (~(((1U << USB_EP5_TX_FIFO_CNT_LEN) - 1) << USB_EP5_TX_FIFO_CNT_POS))
+#define USB_EP5_TX_FIFO_EMPTY      USB_EP5_TX_FIFO_EMPTY
+#define USB_EP5_TX_FIFO_EMPTY_POS  (14U)
+#define USB_EP5_TX_FIFO_EMPTY_LEN  (1U)
+#define USB_EP5_TX_FIFO_EMPTY_MSK  (((1U << USB_EP5_TX_FIFO_EMPTY_LEN) - 1) << USB_EP5_TX_FIFO_EMPTY_POS)
+#define USB_EP5_TX_FIFO_EMPTY_UMSK (~(((1U << USB_EP5_TX_FIFO_EMPTY_LEN) - 1) << USB_EP5_TX_FIFO_EMPTY_POS))
+#define USB_EP5_TX_FIFO_FULL       USB_EP5_TX_FIFO_FULL
+#define USB_EP5_TX_FIFO_FULL_POS   (15U)
+#define USB_EP5_TX_FIFO_FULL_LEN   (1U)
+#define USB_EP5_TX_FIFO_FULL_MSK   (((1U << USB_EP5_TX_FIFO_FULL_LEN) - 1) << USB_EP5_TX_FIFO_FULL_POS)
+#define USB_EP5_TX_FIFO_FULL_UMSK  (~(((1U << USB_EP5_TX_FIFO_FULL_LEN) - 1) << USB_EP5_TX_FIFO_FULL_POS))
+#define USB_EP5_RX_FIFO_CNT        USB_EP5_RX_FIFO_CNT
+#define USB_EP5_RX_FIFO_CNT_POS    (16U)
+#define USB_EP5_RX_FIFO_CNT_LEN    (7U)
+#define USB_EP5_RX_FIFO_CNT_MSK    (((1U << USB_EP5_RX_FIFO_CNT_LEN) - 1) << USB_EP5_RX_FIFO_CNT_POS)
+#define USB_EP5_RX_FIFO_CNT_UMSK   (~(((1U << USB_EP5_RX_FIFO_CNT_LEN) - 1) << USB_EP5_RX_FIFO_CNT_POS))
+#define USB_EP5_RX_FIFO_EMPTY      USB_EP5_RX_FIFO_EMPTY
+#define USB_EP5_RX_FIFO_EMPTY_POS  (30U)
+#define USB_EP5_RX_FIFO_EMPTY_LEN  (1U)
+#define USB_EP5_RX_FIFO_EMPTY_MSK  (((1U << USB_EP5_RX_FIFO_EMPTY_LEN) - 1) << USB_EP5_RX_FIFO_EMPTY_POS)
+#define USB_EP5_RX_FIFO_EMPTY_UMSK (~(((1U << USB_EP5_RX_FIFO_EMPTY_LEN) - 1) << USB_EP5_RX_FIFO_EMPTY_POS))
+#define USB_EP5_RX_FIFO_FULL       USB_EP5_RX_FIFO_FULL
+#define USB_EP5_RX_FIFO_FULL_POS   (31U)
+#define USB_EP5_RX_FIFO_FULL_LEN   (1U)
+#define USB_EP5_RX_FIFO_FULL_MSK   (((1U << USB_EP5_RX_FIFO_FULL_LEN) - 1) << USB_EP5_RX_FIFO_FULL_POS)
+#define USB_EP5_RX_FIFO_FULL_UMSK  (~(((1U << USB_EP5_RX_FIFO_FULL_LEN) - 1) << USB_EP5_RX_FIFO_FULL_POS))
+
+/* 0x158 : ep5_tx_fifo_wdata */
+#define USB_EP5_TX_FIFO_WDATA_OFFSET (0x158)
+#define USB_EP5_TX_FIFO_WDATA        USB_EP5_TX_FIFO_WDATA
+#define USB_EP5_TX_FIFO_WDATA_POS    (0U)
+#define USB_EP5_TX_FIFO_WDATA_LEN    (8U)
+#define USB_EP5_TX_FIFO_WDATA_MSK    (((1U << USB_EP5_TX_FIFO_WDATA_LEN) - 1) << USB_EP5_TX_FIFO_WDATA_POS)
+#define USB_EP5_TX_FIFO_WDATA_UMSK   (~(((1U << USB_EP5_TX_FIFO_WDATA_LEN) - 1) << USB_EP5_TX_FIFO_WDATA_POS))
+
+/* 0x15C : ep5_rx_fifo_rdata */
+#define USB_EP5_RX_FIFO_RDATA_OFFSET (0x15C)
+#define USB_EP5_RX_FIFO_RDATA        USB_EP5_RX_FIFO_RDATA
+#define USB_EP5_RX_FIFO_RDATA_POS    (0U)
+#define USB_EP5_RX_FIFO_RDATA_LEN    (8U)
+#define USB_EP5_RX_FIFO_RDATA_MSK    (((1U << USB_EP5_RX_FIFO_RDATA_LEN) - 1) << USB_EP5_RX_FIFO_RDATA_POS)
+#define USB_EP5_RX_FIFO_RDATA_UMSK   (~(((1U << USB_EP5_RX_FIFO_RDATA_LEN) - 1) << USB_EP5_RX_FIFO_RDATA_POS))
+
+/* 0x160 : ep6_fifo_config */
+#define USB_EP6_FIFO_CONFIG_OFFSET     (0x160)
+#define USB_EP6_DMA_TX_EN              USB_EP6_DMA_TX_EN
+#define USB_EP6_DMA_TX_EN_POS          (0U)
+#define USB_EP6_DMA_TX_EN_LEN          (1U)
+#define USB_EP6_DMA_TX_EN_MSK          (((1U << USB_EP6_DMA_TX_EN_LEN) - 1) << USB_EP6_DMA_TX_EN_POS)
+#define USB_EP6_DMA_TX_EN_UMSK         (~(((1U << USB_EP6_DMA_TX_EN_LEN) - 1) << USB_EP6_DMA_TX_EN_POS))
+#define USB_EP6_DMA_RX_EN              USB_EP6_DMA_RX_EN
+#define USB_EP6_DMA_RX_EN_POS          (1U)
+#define USB_EP6_DMA_RX_EN_LEN          (1U)
+#define USB_EP6_DMA_RX_EN_MSK          (((1U << USB_EP6_DMA_RX_EN_LEN) - 1) << USB_EP6_DMA_RX_EN_POS)
+#define USB_EP6_DMA_RX_EN_UMSK         (~(((1U << USB_EP6_DMA_RX_EN_LEN) - 1) << USB_EP6_DMA_RX_EN_POS))
+#define USB_EP6_TX_FIFO_CLR            USB_EP6_TX_FIFO_CLR
+#define USB_EP6_TX_FIFO_CLR_POS        (2U)
+#define USB_EP6_TX_FIFO_CLR_LEN        (1U)
+#define USB_EP6_TX_FIFO_CLR_MSK        (((1U << USB_EP6_TX_FIFO_CLR_LEN) - 1) << USB_EP6_TX_FIFO_CLR_POS)
+#define USB_EP6_TX_FIFO_CLR_UMSK       (~(((1U << USB_EP6_TX_FIFO_CLR_LEN) - 1) << USB_EP6_TX_FIFO_CLR_POS))
+#define USB_EP6_RX_FIFO_CLR            USB_EP6_RX_FIFO_CLR
+#define USB_EP6_RX_FIFO_CLR_POS        (3U)
+#define USB_EP6_RX_FIFO_CLR_LEN        (1U)
+#define USB_EP6_RX_FIFO_CLR_MSK        (((1U << USB_EP6_RX_FIFO_CLR_LEN) - 1) << USB_EP6_RX_FIFO_CLR_POS)
+#define USB_EP6_RX_FIFO_CLR_UMSK       (~(((1U << USB_EP6_RX_FIFO_CLR_LEN) - 1) << USB_EP6_RX_FIFO_CLR_POS))
+#define USB_EP6_TX_FIFO_OVERFLOW       USB_EP6_TX_FIFO_OVERFLOW
+#define USB_EP6_TX_FIFO_OVERFLOW_POS   (4U)
+#define USB_EP6_TX_FIFO_OVERFLOW_LEN   (1U)
+#define USB_EP6_TX_FIFO_OVERFLOW_MSK   (((1U << USB_EP6_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP6_TX_FIFO_OVERFLOW_POS)
+#define USB_EP6_TX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP6_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP6_TX_FIFO_OVERFLOW_POS))
+#define USB_EP6_TX_FIFO_UNDERFLOW      USB_EP6_TX_FIFO_UNDERFLOW
+#define USB_EP6_TX_FIFO_UNDERFLOW_POS  (5U)
+#define USB_EP6_TX_FIFO_UNDERFLOW_LEN  (1U)
+#define USB_EP6_TX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP6_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP6_TX_FIFO_UNDERFLOW_POS)
+#define USB_EP6_TX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP6_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP6_TX_FIFO_UNDERFLOW_POS))
+#define USB_EP6_RX_FIFO_OVERFLOW       USB_EP6_RX_FIFO_OVERFLOW
+#define USB_EP6_RX_FIFO_OVERFLOW_POS   (6U)
+#define USB_EP6_RX_FIFO_OVERFLOW_LEN   (1U)
+#define USB_EP6_RX_FIFO_OVERFLOW_MSK   (((1U << USB_EP6_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP6_RX_FIFO_OVERFLOW_POS)
+#define USB_EP6_RX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP6_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP6_RX_FIFO_OVERFLOW_POS))
+#define USB_EP6_RX_FIFO_UNDERFLOW      USB_EP6_RX_FIFO_UNDERFLOW
+#define USB_EP6_RX_FIFO_UNDERFLOW_POS  (7U)
+#define USB_EP6_RX_FIFO_UNDERFLOW_LEN  (1U)
+#define USB_EP6_RX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP6_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP6_RX_FIFO_UNDERFLOW_POS)
+#define USB_EP6_RX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP6_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP6_RX_FIFO_UNDERFLOW_POS))
+
+/* 0x164 : ep6_fifo_status */
+#define USB_EP6_FIFO_STATUS_OFFSET (0x164)
+#define USB_EP6_TX_FIFO_CNT        USB_EP6_TX_FIFO_CNT
+#define USB_EP6_TX_FIFO_CNT_POS    (0U)
+#define USB_EP6_TX_FIFO_CNT_LEN    (7U)
+#define USB_EP6_TX_FIFO_CNT_MSK    (((1U << USB_EP6_TX_FIFO_CNT_LEN) - 1) << USB_EP6_TX_FIFO_CNT_POS)
+#define USB_EP6_TX_FIFO_CNT_UMSK   (~(((1U << USB_EP6_TX_FIFO_CNT_LEN) - 1) << USB_EP6_TX_FIFO_CNT_POS))
+#define USB_EP6_TX_FIFO_EMPTY      USB_EP6_TX_FIFO_EMPTY
+#define USB_EP6_TX_FIFO_EMPTY_POS  (14U)
+#define USB_EP6_TX_FIFO_EMPTY_LEN  (1U)
+#define USB_EP6_TX_FIFO_EMPTY_MSK  (((1U << USB_EP6_TX_FIFO_EMPTY_LEN) - 1) << USB_EP6_TX_FIFO_EMPTY_POS)
+#define USB_EP6_TX_FIFO_EMPTY_UMSK (~(((1U << USB_EP6_TX_FIFO_EMPTY_LEN) - 1) << USB_EP6_TX_FIFO_EMPTY_POS))
+#define USB_EP6_TX_FIFO_FULL       USB_EP6_TX_FIFO_FULL
+#define USB_EP6_TX_FIFO_FULL_POS   (15U)
+#define USB_EP6_TX_FIFO_FULL_LEN   (1U)
+#define USB_EP6_TX_FIFO_FULL_MSK   (((1U << USB_EP6_TX_FIFO_FULL_LEN) - 1) << USB_EP6_TX_FIFO_FULL_POS)
+#define USB_EP6_TX_FIFO_FULL_UMSK  (~(((1U << USB_EP6_TX_FIFO_FULL_LEN) - 1) << USB_EP6_TX_FIFO_FULL_POS))
+#define USB_EP6_RX_FIFO_CNT        USB_EP6_RX_FIFO_CNT
+#define USB_EP6_RX_FIFO_CNT_POS    (16U)
+#define USB_EP6_RX_FIFO_CNT_LEN    (7U)
+#define USB_EP6_RX_FIFO_CNT_MSK    (((1U << USB_EP6_RX_FIFO_CNT_LEN) - 1) << USB_EP6_RX_FIFO_CNT_POS)
+#define USB_EP6_RX_FIFO_CNT_UMSK   (~(((1U << USB_EP6_RX_FIFO_CNT_LEN) - 1) << USB_EP6_RX_FIFO_CNT_POS))
+#define USB_EP6_RX_FIFO_EMPTY      USB_EP6_RX_FIFO_EMPTY
+#define USB_EP6_RX_FIFO_EMPTY_POS  (30U)
+#define USB_EP6_RX_FIFO_EMPTY_LEN  (1U)
+#define USB_EP6_RX_FIFO_EMPTY_MSK  (((1U << USB_EP6_RX_FIFO_EMPTY_LEN) - 1) << USB_EP6_RX_FIFO_EMPTY_POS)
+#define USB_EP6_RX_FIFO_EMPTY_UMSK (~(((1U << USB_EP6_RX_FIFO_EMPTY_LEN) - 1) << USB_EP6_RX_FIFO_EMPTY_POS))
+#define USB_EP6_RX_FIFO_FULL       USB_EP6_RX_FIFO_FULL
+#define USB_EP6_RX_FIFO_FULL_POS   (31U)
+#define USB_EP6_RX_FIFO_FULL_LEN   (1U)
+#define USB_EP6_RX_FIFO_FULL_MSK   (((1U << USB_EP6_RX_FIFO_FULL_LEN) - 1) << USB_EP6_RX_FIFO_FULL_POS)
+#define USB_EP6_RX_FIFO_FULL_UMSK  (~(((1U << USB_EP6_RX_FIFO_FULL_LEN) - 1) << USB_EP6_RX_FIFO_FULL_POS))
+
+/* 0x168 : ep6_tx_fifo_wdata */
+#define USB_EP6_TX_FIFO_WDATA_OFFSET (0x168)
+#define USB_EP6_TX_FIFO_WDATA        USB_EP6_TX_FIFO_WDATA
+#define USB_EP6_TX_FIFO_WDATA_POS    (0U)
+#define USB_EP6_TX_FIFO_WDATA_LEN    (8U)
+#define USB_EP6_TX_FIFO_WDATA_MSK    (((1U << USB_EP6_TX_FIFO_WDATA_LEN) - 1) << USB_EP6_TX_FIFO_WDATA_POS)
+#define USB_EP6_TX_FIFO_WDATA_UMSK   (~(((1U << USB_EP6_TX_FIFO_WDATA_LEN) - 1) << USB_EP6_TX_FIFO_WDATA_POS))
+
+/* 0x16C : ep6_rx_fifo_rdata */
+#define USB_EP6_RX_FIFO_RDATA_OFFSET (0x16C)
+#define USB_EP6_RX_FIFO_RDATA        USB_EP6_RX_FIFO_RDATA
+#define USB_EP6_RX_FIFO_RDATA_POS    (0U)
+#define USB_EP6_RX_FIFO_RDATA_LEN    (8U)
+#define USB_EP6_RX_FIFO_RDATA_MSK    (((1U << USB_EP6_RX_FIFO_RDATA_LEN) - 1) << USB_EP6_RX_FIFO_RDATA_POS)
+#define USB_EP6_RX_FIFO_RDATA_UMSK   (~(((1U << USB_EP6_RX_FIFO_RDATA_LEN) - 1) << USB_EP6_RX_FIFO_RDATA_POS))
+
+/* 0x170 : ep7_fifo_config */
+#define USB_EP7_FIFO_CONFIG_OFFSET     (0x170)
+#define USB_EP7_DMA_TX_EN              USB_EP7_DMA_TX_EN
+#define USB_EP7_DMA_TX_EN_POS          (0U)
+#define USB_EP7_DMA_TX_EN_LEN          (1U)
+#define USB_EP7_DMA_TX_EN_MSK          (((1U << USB_EP7_DMA_TX_EN_LEN) - 1) << USB_EP7_DMA_TX_EN_POS)
+#define USB_EP7_DMA_TX_EN_UMSK         (~(((1U << USB_EP7_DMA_TX_EN_LEN) - 1) << USB_EP7_DMA_TX_EN_POS))
+#define USB_EP7_DMA_RX_EN              USB_EP7_DMA_RX_EN
+#define USB_EP7_DMA_RX_EN_POS          (1U)
+#define USB_EP7_DMA_RX_EN_LEN          (1U)
+#define USB_EP7_DMA_RX_EN_MSK          (((1U << USB_EP7_DMA_RX_EN_LEN) - 1) << USB_EP7_DMA_RX_EN_POS)
+#define USB_EP7_DMA_RX_EN_UMSK         (~(((1U << USB_EP7_DMA_RX_EN_LEN) - 1) << USB_EP7_DMA_RX_EN_POS))
+#define USB_EP7_TX_FIFO_CLR            USB_EP7_TX_FIFO_CLR
+#define USB_EP7_TX_FIFO_CLR_POS        (2U)
+#define USB_EP7_TX_FIFO_CLR_LEN        (1U)
+#define USB_EP7_TX_FIFO_CLR_MSK        (((1U << USB_EP7_TX_FIFO_CLR_LEN) - 1) << USB_EP7_TX_FIFO_CLR_POS)
+#define USB_EP7_TX_FIFO_CLR_UMSK       (~(((1U << USB_EP7_TX_FIFO_CLR_LEN) - 1) << USB_EP7_TX_FIFO_CLR_POS))
+#define USB_EP7_RX_FIFO_CLR            USB_EP7_RX_FIFO_CLR
+#define USB_EP7_RX_FIFO_CLR_POS        (3U)
+#define USB_EP7_RX_FIFO_CLR_LEN        (1U)
+#define USB_EP7_RX_FIFO_CLR_MSK        (((1U << USB_EP7_RX_FIFO_CLR_LEN) - 1) << USB_EP7_RX_FIFO_CLR_POS)
+#define USB_EP7_RX_FIFO_CLR_UMSK       (~(((1U << USB_EP7_RX_FIFO_CLR_LEN) - 1) << USB_EP7_RX_FIFO_CLR_POS))
+#define USB_EP7_TX_FIFO_OVERFLOW       USB_EP7_TX_FIFO_OVERFLOW
+#define USB_EP7_TX_FIFO_OVERFLOW_POS   (4U)
+#define USB_EP7_TX_FIFO_OVERFLOW_LEN   (1U)
+#define USB_EP7_TX_FIFO_OVERFLOW_MSK   (((1U << USB_EP7_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP7_TX_FIFO_OVERFLOW_POS)
+#define USB_EP7_TX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP7_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP7_TX_FIFO_OVERFLOW_POS))
+#define USB_EP7_TX_FIFO_UNDERFLOW      USB_EP7_TX_FIFO_UNDERFLOW
+#define USB_EP7_TX_FIFO_UNDERFLOW_POS  (5U)
+#define USB_EP7_TX_FIFO_UNDERFLOW_LEN  (1U)
+#define USB_EP7_TX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP7_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP7_TX_FIFO_UNDERFLOW_POS)
+#define USB_EP7_TX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP7_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP7_TX_FIFO_UNDERFLOW_POS))
+#define USB_EP7_RX_FIFO_OVERFLOW       USB_EP7_RX_FIFO_OVERFLOW
+#define USB_EP7_RX_FIFO_OVERFLOW_POS   (6U)
+#define USB_EP7_RX_FIFO_OVERFLOW_LEN   (1U)
+#define USB_EP7_RX_FIFO_OVERFLOW_MSK   (((1U << USB_EP7_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP7_RX_FIFO_OVERFLOW_POS)
+#define USB_EP7_RX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP7_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP7_RX_FIFO_OVERFLOW_POS))
+#define USB_EP7_RX_FIFO_UNDERFLOW      USB_EP7_RX_FIFO_UNDERFLOW
+#define USB_EP7_RX_FIFO_UNDERFLOW_POS  (7U)
+#define USB_EP7_RX_FIFO_UNDERFLOW_LEN  (1U)
+#define USB_EP7_RX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP7_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP7_RX_FIFO_UNDERFLOW_POS)
+#define USB_EP7_RX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP7_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP7_RX_FIFO_UNDERFLOW_POS))
+
+/* 0x174 : ep7_fifo_status */
+#define USB_EP7_FIFO_STATUS_OFFSET (0x174)
+#define USB_EP7_TX_FIFO_CNT        USB_EP7_TX_FIFO_CNT
+#define USB_EP7_TX_FIFO_CNT_POS    (0U)
+#define USB_EP7_TX_FIFO_CNT_LEN    (7U)
+#define USB_EP7_TX_FIFO_CNT_MSK    (((1U << USB_EP7_TX_FIFO_CNT_LEN) - 1) << USB_EP7_TX_FIFO_CNT_POS)
+#define USB_EP7_TX_FIFO_CNT_UMSK   (~(((1U << USB_EP7_TX_FIFO_CNT_LEN) - 1) << USB_EP7_TX_FIFO_CNT_POS))
+#define USB_EP7_TX_FIFO_EMPTY      USB_EP7_TX_FIFO_EMPTY
+#define USB_EP7_TX_FIFO_EMPTY_POS  (14U)
+#define USB_EP7_TX_FIFO_EMPTY_LEN  (1U)
+#define USB_EP7_TX_FIFO_EMPTY_MSK  (((1U << USB_EP7_TX_FIFO_EMPTY_LEN) - 1) << USB_EP7_TX_FIFO_EMPTY_POS)
+#define USB_EP7_TX_FIFO_EMPTY_UMSK (~(((1U << USB_EP7_TX_FIFO_EMPTY_LEN) - 1) << USB_EP7_TX_FIFO_EMPTY_POS))
+#define USB_EP7_TX_FIFO_FULL       USB_EP7_TX_FIFO_FULL
+#define USB_EP7_TX_FIFO_FULL_POS   (15U)
+#define USB_EP7_TX_FIFO_FULL_LEN   (1U)
+#define USB_EP7_TX_FIFO_FULL_MSK   (((1U << USB_EP7_TX_FIFO_FULL_LEN) - 1) << USB_EP7_TX_FIFO_FULL_POS)
+#define USB_EP7_TX_FIFO_FULL_UMSK  (~(((1U << USB_EP7_TX_FIFO_FULL_LEN) - 1) << USB_EP7_TX_FIFO_FULL_POS))
+#define USB_EP7_RX_FIFO_CNT        USB_EP7_RX_FIFO_CNT
+#define USB_EP7_RX_FIFO_CNT_POS    (16U)
+#define USB_EP7_RX_FIFO_CNT_LEN    (7U)
+#define USB_EP7_RX_FIFO_CNT_MSK    (((1U << USB_EP7_RX_FIFO_CNT_LEN) - 1) << USB_EP7_RX_FIFO_CNT_POS)
+#define USB_EP7_RX_FIFO_CNT_UMSK   (~(((1U << USB_EP7_RX_FIFO_CNT_LEN) - 1) << USB_EP7_RX_FIFO_CNT_POS))
+#define USB_EP7_RX_FIFO_EMPTY      USB_EP7_RX_FIFO_EMPTY
+#define USB_EP7_RX_FIFO_EMPTY_POS  (30U)
+#define USB_EP7_RX_FIFO_EMPTY_LEN  (1U)
+#define USB_EP7_RX_FIFO_EMPTY_MSK  (((1U << USB_EP7_RX_FIFO_EMPTY_LEN) - 1) << USB_EP7_RX_FIFO_EMPTY_POS)
+#define USB_EP7_RX_FIFO_EMPTY_UMSK (~(((1U << USB_EP7_RX_FIFO_EMPTY_LEN) - 1) << USB_EP7_RX_FIFO_EMPTY_POS))
+#define USB_EP7_RX_FIFO_FULL       USB_EP7_RX_FIFO_FULL
+#define USB_EP7_RX_FIFO_FULL_POS   (31U)
+#define USB_EP7_RX_FIFO_FULL_LEN   (1U)
+#define USB_EP7_RX_FIFO_FULL_MSK   (((1U << USB_EP7_RX_FIFO_FULL_LEN) - 1) << USB_EP7_RX_FIFO_FULL_POS)
+#define USB_EP7_RX_FIFO_FULL_UMSK  (~(((1U << USB_EP7_RX_FIFO_FULL_LEN) - 1) << USB_EP7_RX_FIFO_FULL_POS))
+
+/* 0x178 : ep7_tx_fifo_wdata */
+#define USB_EP7_TX_FIFO_WDATA_OFFSET (0x178)
+#define USB_EP7_TX_FIFO_WDATA        USB_EP7_TX_FIFO_WDATA
+#define USB_EP7_TX_FIFO_WDATA_POS    (0U)
+#define USB_EP7_TX_FIFO_WDATA_LEN    (8U)
+#define USB_EP7_TX_FIFO_WDATA_MSK    (((1U << USB_EP7_TX_FIFO_WDATA_LEN) - 1) << USB_EP7_TX_FIFO_WDATA_POS)
+#define USB_EP7_TX_FIFO_WDATA_UMSK   (~(((1U << USB_EP7_TX_FIFO_WDATA_LEN) - 1) << USB_EP7_TX_FIFO_WDATA_POS))
+
+/* 0x17C : ep7_rx_fifo_rdata */
+#define USB_EP7_RX_FIFO_RDATA_OFFSET (0x17C)
+#define USB_EP7_RX_FIFO_RDATA        USB_EP7_RX_FIFO_RDATA
+#define USB_EP7_RX_FIFO_RDATA_POS    (0U)
+#define USB_EP7_RX_FIFO_RDATA_LEN    (8U)
+#define USB_EP7_RX_FIFO_RDATA_MSK    (((1U << USB_EP7_RX_FIFO_RDATA_LEN) - 1) << USB_EP7_RX_FIFO_RDATA_POS)
+#define USB_EP7_RX_FIFO_RDATA_UMSK   (~(((1U << USB_EP7_RX_FIFO_RDATA_LEN) - 1) << USB_EP7_RX_FIFO_RDATA_POS))
+
+/* 0x1F0 : rsvd_0 */
+#define USB_RSVD_0_OFFSET (0x1F0)
+
+/* 0x1F4 : rsvd_1 */
+#define USB_RSVD_1_OFFSET (0x1F4)
+
+/* 0x1FC : xcvr_if_config */
+#define USB_XCVR_IF_CONFIG_OFFSET    (0x1FC)
+#define USB_CR_XCVR_FORCE_TX_EN      USB_CR_XCVR_FORCE_TX_EN
+#define USB_CR_XCVR_FORCE_TX_EN_POS  (0U)
+#define USB_CR_XCVR_FORCE_TX_EN_LEN  (1U)
+#define USB_CR_XCVR_FORCE_TX_EN_MSK  (((1U << USB_CR_XCVR_FORCE_TX_EN_LEN) - 1) << USB_CR_XCVR_FORCE_TX_EN_POS)
+#define USB_CR_XCVR_FORCE_TX_EN_UMSK (~(((1U << USB_CR_XCVR_FORCE_TX_EN_LEN) - 1) << USB_CR_XCVR_FORCE_TX_EN_POS))
+#define USB_CR_XCVR_FORCE_TX_OE      USB_CR_XCVR_FORCE_TX_OE
+#define USB_CR_XCVR_FORCE_TX_OE_POS  (1U)
+#define USB_CR_XCVR_FORCE_TX_OE_LEN  (1U)
+#define USB_CR_XCVR_FORCE_TX_OE_MSK  (((1U << USB_CR_XCVR_FORCE_TX_OE_LEN) - 1) << USB_CR_XCVR_FORCE_TX_OE_POS)
+#define USB_CR_XCVR_FORCE_TX_OE_UMSK (~(((1U << USB_CR_XCVR_FORCE_TX_OE_LEN) - 1) << USB_CR_XCVR_FORCE_TX_OE_POS))
+#define USB_CR_XCVR_FORCE_TX_DP      USB_CR_XCVR_FORCE_TX_DP
+#define USB_CR_XCVR_FORCE_TX_DP_POS  (2U)
+#define USB_CR_XCVR_FORCE_TX_DP_LEN  (1U)
+#define USB_CR_XCVR_FORCE_TX_DP_MSK  (((1U << USB_CR_XCVR_FORCE_TX_DP_LEN) - 1) << USB_CR_XCVR_FORCE_TX_DP_POS)
+#define USB_CR_XCVR_FORCE_TX_DP_UMSK (~(((1U << USB_CR_XCVR_FORCE_TX_DP_LEN) - 1) << USB_CR_XCVR_FORCE_TX_DP_POS))
+#define USB_CR_XCVR_FORCE_TX_DN      USB_CR_XCVR_FORCE_TX_DN
+#define USB_CR_XCVR_FORCE_TX_DN_POS  (3U)
+#define USB_CR_XCVR_FORCE_TX_DN_LEN  (1U)
+#define USB_CR_XCVR_FORCE_TX_DN_MSK  (((1U << USB_CR_XCVR_FORCE_TX_DN_LEN) - 1) << USB_CR_XCVR_FORCE_TX_DN_POS)
+#define USB_CR_XCVR_FORCE_TX_DN_UMSK (~(((1U << USB_CR_XCVR_FORCE_TX_DN_LEN) - 1) << USB_CR_XCVR_FORCE_TX_DN_POS))
+#define USB_CR_XCVR_FORCE_RX_EN      USB_CR_XCVR_FORCE_RX_EN
+#define USB_CR_XCVR_FORCE_RX_EN_POS  (4U)
+#define USB_CR_XCVR_FORCE_RX_EN_LEN  (1U)
+#define USB_CR_XCVR_FORCE_RX_EN_MSK  (((1U << USB_CR_XCVR_FORCE_RX_EN_LEN) - 1) << USB_CR_XCVR_FORCE_RX_EN_POS)
+#define USB_CR_XCVR_FORCE_RX_EN_UMSK (~(((1U << USB_CR_XCVR_FORCE_RX_EN_LEN) - 1) << USB_CR_XCVR_FORCE_RX_EN_POS))
+#define USB_CR_XCVR_FORCE_RX_D       USB_CR_XCVR_FORCE_RX_D
+#define USB_CR_XCVR_FORCE_RX_D_POS   (5U)
+#define USB_CR_XCVR_FORCE_RX_D_LEN   (1U)
+#define USB_CR_XCVR_FORCE_RX_D_MSK   (((1U << USB_CR_XCVR_FORCE_RX_D_LEN) - 1) << USB_CR_XCVR_FORCE_RX_D_POS)
+#define USB_CR_XCVR_FORCE_RX_D_UMSK  (~(((1U << USB_CR_XCVR_FORCE_RX_D_LEN) - 1) << USB_CR_XCVR_FORCE_RX_D_POS))
+#define USB_CR_XCVR_FORCE_RX_DP      USB_CR_XCVR_FORCE_RX_DP
+#define USB_CR_XCVR_FORCE_RX_DP_POS  (6U)
+#define USB_CR_XCVR_FORCE_RX_DP_LEN  (1U)
+#define USB_CR_XCVR_FORCE_RX_DP_MSK  (((1U << USB_CR_XCVR_FORCE_RX_DP_LEN) - 1) << USB_CR_XCVR_FORCE_RX_DP_POS)
+#define USB_CR_XCVR_FORCE_RX_DP_UMSK (~(((1U << USB_CR_XCVR_FORCE_RX_DP_LEN) - 1) << USB_CR_XCVR_FORCE_RX_DP_POS))
+#define USB_CR_XCVR_FORCE_RX_DN      USB_CR_XCVR_FORCE_RX_DN
+#define USB_CR_XCVR_FORCE_RX_DN_POS  (7U)
+#define USB_CR_XCVR_FORCE_RX_DN_LEN  (1U)
+#define USB_CR_XCVR_FORCE_RX_DN_MSK  (((1U << USB_CR_XCVR_FORCE_RX_DN_LEN) - 1) << USB_CR_XCVR_FORCE_RX_DN_POS)
+#define USB_CR_XCVR_FORCE_RX_DN_UMSK (~(((1U << USB_CR_XCVR_FORCE_RX_DN_LEN) - 1) << USB_CR_XCVR_FORCE_RX_DN_POS))
+#define USB_CR_XCVR_OM_RX_SEL        USB_CR_XCVR_OM_RX_SEL
+#define USB_CR_XCVR_OM_RX_SEL_POS    (8U)
+#define USB_CR_XCVR_OM_RX_SEL_LEN    (1U)
+#define USB_CR_XCVR_OM_RX_SEL_MSK    (((1U << USB_CR_XCVR_OM_RX_SEL_LEN) - 1) << USB_CR_XCVR_OM_RX_SEL_POS)
+#define USB_CR_XCVR_OM_RX_SEL_UMSK   (~(((1U << USB_CR_XCVR_OM_RX_SEL_LEN) - 1) << USB_CR_XCVR_OM_RX_SEL_POS))
+#define USB_CR_XCVR_OM_RX_D          USB_CR_XCVR_OM_RX_D
+#define USB_CR_XCVR_OM_RX_D_POS      (9U)
+#define USB_CR_XCVR_OM_RX_D_LEN      (1U)
+#define USB_CR_XCVR_OM_RX_D_MSK      (((1U << USB_CR_XCVR_OM_RX_D_LEN) - 1) << USB_CR_XCVR_OM_RX_D_POS)
+#define USB_CR_XCVR_OM_RX_D_UMSK     (~(((1U << USB_CR_XCVR_OM_RX_D_LEN) - 1) << USB_CR_XCVR_OM_RX_D_POS))
+#define USB_CR_XCVR_OM_RX_DP         USB_CR_XCVR_OM_RX_DP
+#define USB_CR_XCVR_OM_RX_DP_POS     (10U)
+#define USB_CR_XCVR_OM_RX_DP_LEN     (1U)
+#define USB_CR_XCVR_OM_RX_DP_MSK     (((1U << USB_CR_XCVR_OM_RX_DP_LEN) - 1) << USB_CR_XCVR_OM_RX_DP_POS)
+#define USB_CR_XCVR_OM_RX_DP_UMSK    (~(((1U << USB_CR_XCVR_OM_RX_DP_LEN) - 1) << USB_CR_XCVR_OM_RX_DP_POS))
+#define USB_CR_XCVR_OM_RX_DN         USB_CR_XCVR_OM_RX_DN
+#define USB_CR_XCVR_OM_RX_DN_POS     (11U)
+#define USB_CR_XCVR_OM_RX_DN_LEN     (1U)
+#define USB_CR_XCVR_OM_RX_DN_MSK     (((1U << USB_CR_XCVR_OM_RX_DN_LEN) - 1) << USB_CR_XCVR_OM_RX_DN_POS)
+#define USB_CR_XCVR_OM_RX_DN_UMSK    (~(((1U << USB_CR_XCVR_OM_RX_DN_LEN) - 1) << USB_CR_XCVR_OM_RX_DN_POS))
+#define USB_STS_VBUS_DET             USB_STS_VBUS_DET
+#define USB_STS_VBUS_DET_POS         (31U)
+#define USB_STS_VBUS_DET_LEN         (1U)
+#define USB_STS_VBUS_DET_MSK         (((1U << USB_STS_VBUS_DET_LEN) - 1) << USB_STS_VBUS_DET_POS)
+#define USB_STS_VBUS_DET_UMSK        (~(((1U << USB_STS_VBUS_DET_LEN) - 1) << USB_STS_VBUS_DET_POS))
+
+struct usb_reg {
+    /* 0x0 : usb_config */
+    union {
+        struct
+        {
+            uint32_t cr_usb_en              : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3           : 3; /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t cr_usb_rom_dct_en      : 1; /* [    4],        r/w,        0x1 */
+            uint32_t reserved_5_7           : 3; /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t cr_usb_ep0_sw_ctrl     : 1; /* [    8],        r/w,        0x0 */
+            uint32_t cr_usb_ep0_sw_addr     : 7; /* [15: 9],        r/w,        0x0 */
+            uint32_t cr_usb_ep0_sw_size     : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t cr_usb_ep0_sw_stall    : 1; /* [   24],        w1c,        0x0 */
+            uint32_t cr_usb_ep0_sw_nack_in  : 1; /* [   25],        r/w,        0x1 */
+            uint32_t cr_usb_ep0_sw_nack_out : 1; /* [   26],        r/w,        0x0 */
+            uint32_t cr_usb_ep0_sw_rdy      : 1; /* [   27],        w1c,        0x0 */
+            uint32_t sts_usb_ep0_sw_rdy     : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29_31         : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } usb_config;
+
+    /* 0x4 : usb_lpm_config */
+    union {
+        struct
+        {
+            uint32_t cr_lpm_en       : 1;  /* [    0],        w1c,        0x0 */
+            uint32_t cr_lpm_resp_upd : 1;  /* [    1],        w1c,        0x0 */
+            uint32_t cr_lpm_resp     : 2;  /* [ 3: 2],        r/w,        0x2 */
+            uint32_t reserved_4_19   : 16; /* [19: 4],       rsvd,        0x0 */
+            uint32_t sts_lpm_attr    : 11; /* [30:20],          r,        0x0 */
+            uint32_t sts_lpm         : 1;  /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } usb_lpm_config;
+
+    /* 0x8 : usb_resume_config */
+    union {
+        struct
+        {
+            uint32_t cr_res_width   : 11; /* [10: 0],        r/w,       0x1a */
+            uint32_t reserved_11    : 1;  /* [   11],       rsvd,        0x0 */
+            uint32_t cr_res_trig    : 1;  /* [   12],        w1c,        0x0 */
+            uint32_t reserved_13_30 : 18; /* [30:13],       rsvd,        0x0 */
+            uint32_t cr_res_force   : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } usb_resume_config;
+
+    /* 0xc  reserved */
+    uint8_t RESERVED0xc[4];
+
+    /* 0x10 : usb_setup_data_0 */
+    union {
+        struct
+        {
+            uint32_t sts_setup_data_b0 : 8; /* [ 7: 0],          r,        0x0 */
+            uint32_t sts_setup_data_b1 : 8; /* [15: 8],          r,        0x0 */
+            uint32_t sts_setup_data_b2 : 8; /* [23:16],          r,        0x0 */
+            uint32_t sts_setup_data_b3 : 8; /* [31:24],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } usb_setup_data_0;
+
+    /* 0x14 : usb_setup_data_1 */
+    union {
+        struct
+        {
+            uint32_t sts_setup_data_b4 : 8; /* [ 7: 0],          r,        0x0 */
+            uint32_t sts_setup_data_b5 : 8; /* [15: 8],          r,        0x0 */
+            uint32_t sts_setup_data_b6 : 8; /* [23:16],          r,        0x0 */
+            uint32_t sts_setup_data_b7 : 8; /* [31:24],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } usb_setup_data_1;
+
+    /* 0x18 : usb_frame_no */
+    union {
+        struct
+        {
+            uint32_t sts_frame_no   : 11; /* [10: 0],          r,        0x0 */
+            uint32_t reserved_11    : 1;  /* [   11],       rsvd,        0x0 */
+            uint32_t sts_pid        : 4;  /* [15:12],          r,        0x0 */
+            uint32_t sts_ep_no      : 4;  /* [19:16],          r,        0x0 */
+            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } usb_frame_no;
+
+    /* 0x1C : usb_error */
+    union {
+        struct
+        {
+            uint32_t utmi_rx_err   : 1;  /* [    0],          r,        0x0 */
+            uint32_t xfer_to_err   : 1;  /* [    1],          r,        0x0 */
+            uint32_t ivld_ep_err   : 1;  /* [    2],          r,        0x0 */
+            uint32_t pid_seq_err   : 1;  /* [    3],          r,        0x0 */
+            uint32_t pid_cks_err   : 1;  /* [    4],          r,        0x0 */
+            uint32_t crc5_err      : 1;  /* [    5],          r,        0x0 */
+            uint32_t crc16_err     : 1;  /* [    6],          r,        0x0 */
+            uint32_t reserved_7_31 : 25; /* [31: 7],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } usb_error;
+
+    /* 0x20 : USB interrupt enable */
+    union {
+        struct
+        {
+            uint32_t cr_sof_en            : 1; /* [    0],        r/w,        0x1 */
+            uint32_t cr_usb_reset_en      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t cr_vbus_tgl_en       : 1; /* [    2],        r/w,        0x1 */
+            uint32_t cr_get_dct_cmd_en    : 1; /* [    3],        r/w,        0x1 */
+            uint32_t cr_ep0_setup_cmd_en  : 1; /* [    4],        r/w,        0x1 */
+            uint32_t cr_ep0_setup_done_en : 1; /* [    5],        r/w,        0x1 */
+            uint32_t cr_ep0_in_cmd_en     : 1; /* [    6],        r/w,        0x1 */
+            uint32_t cr_ep0_in_done_en    : 1; /* [    7],        r/w,        0x1 */
+            uint32_t cr_ep0_out_cmd_en    : 1; /* [    8],        r/w,        0x1 */
+            uint32_t cr_ep0_out_done_en   : 1; /* [    9],        r/w,        0x1 */
+            uint32_t cr_ep1_cmd_en        : 1; /* [   10],        r/w,        0x1 */
+            uint32_t cr_ep1_done_en       : 1; /* [   11],        r/w,        0x1 */
+            uint32_t cr_ep2_cmd_en        : 1; /* [   12],        r/w,        0x1 */
+            uint32_t cr_ep2_done_en       : 1; /* [   13],        r/w,        0x1 */
+            uint32_t cr_ep3_cmd_en        : 1; /* [   14],        r/w,        0x1 */
+            uint32_t cr_ep3_done_en       : 1; /* [   15],        r/w,        0x1 */
+            uint32_t cr_ep4_cmd_en        : 1; /* [   16],        r/w,        0x1 */
+            uint32_t cr_ep4_done_en       : 1; /* [   17],        r/w,        0x1 */
+            uint32_t cr_ep5_cmd_en        : 1; /* [   18],        r/w,        0x1 */
+            uint32_t cr_ep5_done_en       : 1; /* [   19],        r/w,        0x1 */
+            uint32_t cr_ep6_cmd_en        : 1; /* [   20],        r/w,        0x1 */
+            uint32_t cr_ep6_done_en       : 1; /* [   21],        r/w,        0x1 */
+            uint32_t cr_ep7_cmd_en        : 1; /* [   22],        r/w,        0x1 */
+            uint32_t cr_ep7_done_en       : 1; /* [   23],        r/w,        0x1 */
+            uint32_t rsvd_26_24           : 3; /* [26:24],       rsvd,        0x0 */
+            uint32_t cr_usb_rend_en       : 1; /* [   27],        r/w,        0x0 */
+            uint32_t cr_lpm_wkup_en       : 1; /* [   28],        r/w,        0x0 */
+            uint32_t cr_lpm_pkt_en        : 1; /* [   29],        r/w,        0x0 */
+            uint32_t cr_sof_3ms_en        : 1; /* [   30],        r/w,        0x0 */
+            uint32_t cr_usb_err_en        : 1; /* [   31],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } usb_int_en;
+
+    /* 0x24 : USB interrupt status */
+    union {
+        struct
+        {
+            uint32_t sof_int            : 1; /* [    0],          r,        0x0 */
+            uint32_t usb_reset_int      : 1; /* [    1],          r,        0x0 */
+            uint32_t vbus_tgl_int       : 1; /* [    2],          r,        0x0 */
+            uint32_t get_dct_cmd_int    : 1; /* [    3],          r,        0x0 */
+            uint32_t ep0_setup_cmd_int  : 1; /* [    4],          r,        0x0 */
+            uint32_t ep0_setup_done_int : 1; /* [    5],          r,        0x0 */
+            uint32_t ep0_in_cmd_int     : 1; /* [    6],          r,        0x0 */
+            uint32_t ep0_in_done_int    : 1; /* [    7],          r,        0x0 */
+            uint32_t ep0_out_cmd_int    : 1; /* [    8],          r,        0x0 */
+            uint32_t ep0_out_done_int   : 1; /* [    9],          r,        0x0 */
+            uint32_t ep1_cmd_int        : 1; /* [   10],          r,        0x0 */
+            uint32_t ep1_done_int       : 1; /* [   11],          r,        0x0 */
+            uint32_t ep2_cmd_int        : 1; /* [   12],          r,        0x0 */
+            uint32_t ep2_done_int       : 1; /* [   13],          r,        0x0 */
+            uint32_t ep3_cmd_int        : 1; /* [   14],          r,        0x0 */
+            uint32_t ep3_done_int       : 1; /* [   15],          r,        0x0 */
+            uint32_t ep4_cmd_int        : 1; /* [   16],          r,        0x0 */
+            uint32_t ep4_done_int       : 1; /* [   17],          r,        0x0 */
+            uint32_t ep5_cmd_int        : 1; /* [   18],          r,        0x0 */
+            uint32_t ep5_done_int       : 1; /* [   19],          r,        0x0 */
+            uint32_t ep6_cmd_int        : 1; /* [   20],          r,        0x0 */
+            uint32_t ep6_done_int       : 1; /* [   21],          r,        0x0 */
+            uint32_t ep7_cmd_int        : 1; /* [   22],          r,        0x0 */
+            uint32_t ep7_done_int       : 1; /* [   23],          r,        0x0 */
+            uint32_t rsvd_26_24         : 3; /* [26:24],       rsvd,        0x0 */
+            uint32_t usb_rend_int       : 1; /* [   27],          r,        0x0 */
+            uint32_t lpm_wkup_int       : 1; /* [   28],          r,        0x0 */
+            uint32_t lpm_pkt_int        : 1; /* [   29],          r,        0x0 */
+            uint32_t sof_3ms_int        : 1; /* [   30],          r,        0x0 */
+            uint32_t usb_err_int        : 1; /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } usb_int_sts;
+
+    /* 0x28 : USB interrupt mask */
+    union {
+        struct
+        {
+            uint32_t cr_sof_mask            : 1; /* [    0],        r/w,        0x1 */
+            uint32_t cr_usb_reset_mask      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t cr_vbus_tgl_mask       : 1; /* [    2],        r/w,        0x1 */
+            uint32_t cr_get_dct_cmd_mask    : 1; /* [    3],        r/w,        0x1 */
+            uint32_t cr_ep0_setup_cmd_mask  : 1; /* [    4],        r/w,        0x1 */
+            uint32_t cr_ep0_setup_done_mask : 1; /* [    5],        r/w,        0x1 */
+            uint32_t cr_ep0_in_cmd_mask     : 1; /* [    6],        r/w,        0x1 */
+            uint32_t cr_ep0_in_done_mask    : 1; /* [    7],        r/w,        0x1 */
+            uint32_t cr_ep0_out_cmd_mask    : 1; /* [    8],        r/w,        0x1 */
+            uint32_t cr_ep0_out_done_mask   : 1; /* [    9],        r/w,        0x1 */
+            uint32_t cr_ep1_cmd_mask        : 1; /* [   10],        r/w,        0x1 */
+            uint32_t cr_ep1_done_mask       : 1; /* [   11],        r/w,        0x1 */
+            uint32_t cr_ep2_cmd_mask        : 1; /* [   12],        r/w,        0x1 */
+            uint32_t cr_ep2_done_mask       : 1; /* [   13],        r/w,        0x1 */
+            uint32_t cr_ep3_cmd_mask        : 1; /* [   14],        r/w,        0x1 */
+            uint32_t cr_ep3_done_mask       : 1; /* [   15],        r/w,        0x1 */
+            uint32_t cr_ep4_cmd_mask        : 1; /* [   16],        r/w,        0x1 */
+            uint32_t cr_ep4_done_mask       : 1; /* [   17],        r/w,        0x1 */
+            uint32_t cr_ep5_cmd_mask        : 1; /* [   18],        r/w,        0x1 */
+            uint32_t cr_ep5_done_mask       : 1; /* [   19],        r/w,        0x1 */
+            uint32_t cr_ep6_cmd_mask        : 1; /* [   20],        r/w,        0x1 */
+            uint32_t cr_ep6_done_mask       : 1; /* [   21],        r/w,        0x1 */
+            uint32_t cr_ep7_cmd_mask        : 1; /* [   22],        r/w,        0x1 */
+            uint32_t cr_ep7_done_mask       : 1; /* [   23],        r/w,        0x1 */
+            uint32_t rsvd_26_24             : 3; /* [26:24],       rsvd,        0x0 */
+            uint32_t cr_usb_rend_mask       : 1; /* [   27],        r/w,        0x1 */
+            uint32_t cr_lpm_wkup_mask       : 1; /* [   28],        r/w,        0x1 */
+            uint32_t cr_lpm_pkt_mask        : 1; /* [   29],        r/w,        0x1 */
+            uint32_t cr_sof_3ms_mask        : 1; /* [   30],        r/w,        0x1 */
+            uint32_t cr_usb_err_mask        : 1; /* [   31],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } usb_int_mask;
+
+    /* 0x2C : USB interrupt clear */
+    union {
+        struct
+        {
+            uint32_t cr_sof_clr            : 1; /* [    0],        w1c,        0x0 */
+            uint32_t cr_usb_reset_clr      : 1; /* [    1],        w1c,        0x0 */
+            uint32_t cr_vbus_tgl_clr       : 1; /* [    2],        w1c,        0x0 */
+            uint32_t cr_get_dct_cmd_clr    : 1; /* [    3],        w1c,        0x0 */
+            uint32_t cr_ep0_setup_cmd_clr  : 1; /* [    4],        w1c,        0x0 */
+            uint32_t cr_ep0_setup_done_clr : 1; /* [    5],        w1c,        0x0 */
+            uint32_t cr_ep0_in_cmd_clr     : 1; /* [    6],        w1c,        0x0 */
+            uint32_t cr_ep0_in_done_clr    : 1; /* [    7],        w1c,        0x0 */
+            uint32_t cr_ep0_out_cmd_clr    : 1; /* [    8],        w1c,        0x0 */
+            uint32_t cr_ep0_out_done_clr   : 1; /* [    9],        w1c,        0x0 */
+            uint32_t cr_ep1_cmd_clr        : 1; /* [   10],        w1c,        0x0 */
+            uint32_t cr_ep1_done_clr       : 1; /* [   11],        w1c,        0x0 */
+            uint32_t cr_ep2_cmd_clr        : 1; /* [   12],        w1c,        0x0 */
+            uint32_t cr_ep2_done_clr       : 1; /* [   13],        w1c,        0x0 */
+            uint32_t cr_ep3_cmd_clr        : 1; /* [   14],        w1c,        0x0 */
+            uint32_t cr_ep3_done_clr       : 1; /* [   15],        w1c,        0x0 */
+            uint32_t cr_ep4_cmd_clr        : 1; /* [   16],        w1c,        0x0 */
+            uint32_t cr_ep4_done_clr       : 1; /* [   17],        w1c,        0x0 */
+            uint32_t cr_ep5_cmd_clr        : 1; /* [   18],        w1c,        0x0 */
+            uint32_t cr_ep5_done_clr       : 1; /* [   19],        w1c,        0x0 */
+            uint32_t cr_ep6_cmd_clr        : 1; /* [   20],        w1c,        0x0 */
+            uint32_t cr_ep6_done_clr       : 1; /* [   21],        w1c,        0x0 */
+            uint32_t cr_ep7_cmd_clr        : 1; /* [   22],        w1c,        0x0 */
+            uint32_t cr_ep7_done_clr       : 1; /* [   23],        w1c,        0x0 */
+            uint32_t rsvd_26_24            : 3; /* [26:24],       rsvd,        0x0 */
+            uint32_t cr_usb_rend_clr       : 1; /* [   27],        w1c,        0x0 */
+            uint32_t cr_lpm_wkup_clr       : 1; /* [   28],        w1c,        0x0 */
+            uint32_t cr_lpm_pkt_clr        : 1; /* [   29],        w1c,        0x0 */
+            uint32_t cr_sof_3ms_clr        : 1; /* [   30],        w1c,        0x0 */
+            uint32_t cr_usb_err_clr        : 1; /* [   31],        w1c,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } usb_int_clear;
+
+    /* 0x30  reserved */
+    uint8_t RESERVED0x30[16];
+
+    /* 0x40 : ep1_config */
+    union {
+        struct
+        {
+            uint32_t cr_ep1_size    : 11; /* [10: 0],        r/w,       0x40 */
+            uint32_t cr_ep1_dir     : 2;  /* [12:11],        r/w,        0x1 */
+            uint32_t cr_ep1_type    : 3;  /* [15:13],        r/w,        0x4 */
+            uint32_t cr_ep1_stall   : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t cr_ep1_nack    : 1;  /* [   17],        r/w,        0x1 */
+            uint32_t cr_ep1_rdy     : 1;  /* [   18],        w1c,        0x0 */
+            uint32_t sts_ep1_rdy    : 1;  /* [   19],          r,        0x0 */
+            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep1_config;
+
+    /* 0x44 : ep2_config */
+    union {
+        struct
+        {
+            uint32_t cr_ep2_size    : 11; /* [10: 0],        r/w,       0x40 */
+            uint32_t cr_ep2_dir     : 2;  /* [12:11],        r/w,        0x1 */
+            uint32_t cr_ep2_type    : 3;  /* [15:13],        r/w,        0x4 */
+            uint32_t cr_ep2_stall   : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t cr_ep2_nack    : 1;  /* [   17],        r/w,        0x1 */
+            uint32_t cr_ep2_rdy     : 1;  /* [   18],        w1c,        0x0 */
+            uint32_t sts_ep2_rdy    : 1;  /* [   19],          r,        0x0 */
+            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep2_config;
+
+    /* 0x48 : ep3_config */
+    union {
+        struct
+        {
+            uint32_t cr_ep3_size    : 11; /* [10: 0],        r/w,       0x40 */
+            uint32_t cr_ep3_dir     : 2;  /* [12:11],        r/w,        0x1 */
+            uint32_t cr_ep3_type    : 3;  /* [15:13],        r/w,        0x4 */
+            uint32_t cr_ep3_stall   : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t cr_ep3_nack    : 1;  /* [   17],        r/w,        0x1 */
+            uint32_t cr_ep3_rdy     : 1;  /* [   18],        w1c,        0x0 */
+            uint32_t sts_ep3_rdy    : 1;  /* [   19],          r,        0x0 */
+            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep3_config;
+
+    /* 0x4C : ep4_config */
+    union {
+        struct
+        {
+            uint32_t cr_ep4_size    : 11; /* [10: 0],        r/w,       0x40 */
+            uint32_t cr_ep4_dir     : 2;  /* [12:11],        r/w,        0x1 */
+            uint32_t cr_ep4_type    : 3;  /* [15:13],        r/w,        0x4 */
+            uint32_t cr_ep4_stall   : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t cr_ep4_nack    : 1;  /* [   17],        r/w,        0x1 */
+            uint32_t cr_ep4_rdy     : 1;  /* [   18],        w1c,        0x0 */
+            uint32_t sts_ep4_rdy    : 1;  /* [   19],          r,        0x0 */
+            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep4_config;
+
+    /* 0x50 : ep5_config */
+    union {
+        struct
+        {
+            uint32_t cr_ep5_size    : 11; /* [10: 0],        r/w,       0x40 */
+            uint32_t cr_ep5_dir     : 2;  /* [12:11],        r/w,        0x1 */
+            uint32_t cr_ep5_type    : 3;  /* [15:13],        r/w,        0x4 */
+            uint32_t cr_ep5_stall   : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t cr_ep5_nack    : 1;  /* [   17],        r/w,        0x1 */
+            uint32_t cr_ep5_rdy     : 1;  /* [   18],        w1c,        0x0 */
+            uint32_t sts_ep5_rdy    : 1;  /* [   19],          r,        0x0 */
+            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep5_config;
+
+    /* 0x54 : ep6_config */
+    union {
+        struct
+        {
+            uint32_t cr_ep6_size    : 11; /* [10: 0],        r/w,       0x40 */
+            uint32_t cr_ep6_dir     : 2;  /* [12:11],        r/w,        0x1 */
+            uint32_t cr_ep6_type    : 3;  /* [15:13],        r/w,        0x4 */
+            uint32_t cr_ep6_stall   : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t cr_ep6_nack    : 1;  /* [   17],        r/w,        0x1 */
+            uint32_t cr_ep6_rdy     : 1;  /* [   18],        w1c,        0x0 */
+            uint32_t sts_ep6_rdy    : 1;  /* [   19],          r,        0x0 */
+            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep6_config;
+
+    /* 0x58 : ep7_config */
+    union {
+        struct
+        {
+            uint32_t cr_ep7_size    : 11; /* [10: 0],        r/w,       0x40 */
+            uint32_t cr_ep7_dir     : 2;  /* [12:11],        r/w,        0x1 */
+            uint32_t cr_ep7_type    : 3;  /* [15:13],        r/w,        0x4 */
+            uint32_t cr_ep7_stall   : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t cr_ep7_nack    : 1;  /* [   17],        r/w,        0x1 */
+            uint32_t cr_ep7_rdy     : 1;  /* [   18],        w1c,        0x0 */
+            uint32_t sts_ep7_rdy    : 1;  /* [   19],          r,        0x0 */
+            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep7_config;
+
+    /* 0x5c  reserved */
+    uint8_t RESERVED0x5c[164];
+
+    /* 0x100 : ep0_fifo_config */
+    union {
+        struct
+        {
+            uint32_t ep0_dma_tx_en         : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t ep0_dma_rx_en         : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t ep0_tx_fifo_clr       : 1;  /* [    2],        w1c,        0x0 */
+            uint32_t ep0_rx_fifo_clr       : 1;  /* [    3],        w1c,        0x0 */
+            uint32_t ep0_tx_fifo_overflow  : 1;  /* [    4],          r,        0x0 */
+            uint32_t ep0_tx_fifo_underflow : 1;  /* [    5],          r,        0x0 */
+            uint32_t ep0_rx_fifo_overflow  : 1;  /* [    6],          r,        0x0 */
+            uint32_t ep0_rx_fifo_underflow : 1;  /* [    7],          r,        0x0 */
+            uint32_t reserved_8_31         : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep0_fifo_config;
+
+    /* 0x104 : ep0_fifo_status */
+    union {
+        struct
+        {
+            uint32_t ep0_tx_fifo_cnt   : 7; /* [ 6: 0],          r,       0x40 */
+            uint32_t reserved_7_13     : 7; /* [13: 7],       rsvd,        0x0 */
+            uint32_t ep0_tx_fifo_empty : 1; /* [   14],          r,        0x1 */
+            uint32_t ep0_tx_fifo_full  : 1; /* [   15],          r,        0x0 */
+            uint32_t ep0_rx_fifo_cnt   : 7; /* [22:16],          r,        0x0 */
+            uint32_t reserved_23_29    : 7; /* [29:23],       rsvd,        0x0 */
+            uint32_t ep0_rx_fifo_empty : 1; /* [   30],          r,        0x1 */
+            uint32_t ep0_rx_fifo_full  : 1; /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep0_fifo_status;
+
+    /* 0x108 : ep0_tx_fifo_wdata */
+    union {
+        struct
+        {
+            uint32_t ep0_tx_fifo_wdata : 8;  /* [ 7: 0],          w,          x */
+            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep0_tx_fifo_wdata;
+
+    /* 0x10C : ep0_rx_fifo_rdata */
+    union {
+        struct
+        {
+            uint32_t ep0_rx_fifo_rdata : 8;  /* [ 7: 0],          r,        0x0 */
+            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep0_rx_fifo_rdata;
+
+    /* 0x110 : ep1_fifo_config */
+    union {
+        struct
+        {
+            uint32_t ep1_dma_tx_en         : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t ep1_dma_rx_en         : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t ep1_tx_fifo_clr       : 1;  /* [    2],        w1c,        0x0 */
+            uint32_t ep1_rx_fifo_clr       : 1;  /* [    3],        w1c,        0x0 */
+            uint32_t ep1_tx_fifo_overflow  : 1;  /* [    4],          r,        0x0 */
+            uint32_t ep1_tx_fifo_underflow : 1;  /* [    5],          r,        0x0 */
+            uint32_t ep1_rx_fifo_overflow  : 1;  /* [    6],          r,        0x0 */
+            uint32_t ep1_rx_fifo_underflow : 1;  /* [    7],          r,        0x0 */
+            uint32_t reserved_8_31         : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep1_fifo_config;
+
+    /* 0x114 : ep1_fifo_status */
+    union {
+        struct
+        {
+            uint32_t ep1_tx_fifo_cnt   : 7; /* [ 6: 0],          r,       0x40 */
+            uint32_t reserved_7_13     : 7; /* [13: 7],       rsvd,        0x0 */
+            uint32_t ep1_tx_fifo_empty : 1; /* [   14],          r,        0x1 */
+            uint32_t ep1_tx_fifo_full  : 1; /* [   15],          r,        0x0 */
+            uint32_t ep1_rx_fifo_cnt   : 7; /* [22:16],          r,        0x0 */
+            uint32_t reserved_23_29    : 7; /* [29:23],       rsvd,        0x0 */
+            uint32_t ep1_rx_fifo_empty : 1; /* [   30],          r,        0x1 */
+            uint32_t ep1_rx_fifo_full  : 1; /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep1_fifo_status;
+
+    /* 0x118 : ep1_tx_fifo_wdata */
+    union {
+        struct
+        {
+            uint32_t ep1_tx_fifo_wdata : 8;  /* [ 7: 0],          w,          x */
+            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep1_tx_fifo_wdata;
+
+    /* 0x11C : ep1_rx_fifo_rdata */
+    union {
+        struct
+        {
+            uint32_t ep1_rx_fifo_rdata : 8;  /* [ 7: 0],          r,        0x0 */
+            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep1_rx_fifo_rdata;
+
+    /* 0x120 : ep2_fifo_config */
+    union {
+        struct
+        {
+            uint32_t ep2_dma_tx_en         : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t ep2_dma_rx_en         : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t ep2_tx_fifo_clr       : 1;  /* [    2],        w1c,        0x0 */
+            uint32_t ep2_rx_fifo_clr       : 1;  /* [    3],        w1c,        0x0 */
+            uint32_t ep2_tx_fifo_overflow  : 1;  /* [    4],          r,        0x0 */
+            uint32_t ep2_tx_fifo_underflow : 1;  /* [    5],          r,        0x0 */
+            uint32_t ep2_rx_fifo_overflow  : 1;  /* [    6],          r,        0x0 */
+            uint32_t ep2_rx_fifo_underflow : 1;  /* [    7],          r,        0x0 */
+            uint32_t reserved_8_31         : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep2_fifo_config;
+
+    /* 0x124 : ep2_fifo_status */
+    union {
+        struct
+        {
+            uint32_t ep2_tx_fifo_cnt   : 7; /* [ 6: 0],          r,       0x40 */
+            uint32_t reserved_7_13     : 7; /* [13: 7],       rsvd,        0x0 */
+            uint32_t ep2_tx_fifo_empty : 1; /* [   14],          r,        0x1 */
+            uint32_t ep2_tx_fifo_full  : 1; /* [   15],          r,        0x0 */
+            uint32_t ep2_rx_fifo_cnt   : 7; /* [22:16],          r,        0x0 */
+            uint32_t reserved_23_29    : 7; /* [29:23],       rsvd,        0x0 */
+            uint32_t ep2_rx_fifo_empty : 1; /* [   30],          r,        0x1 */
+            uint32_t ep2_rx_fifo_full  : 1; /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep2_fifo_status;
+
+    /* 0x128 : ep2_tx_fifo_wdata */
+    union {
+        struct
+        {
+            uint32_t ep2_tx_fifo_wdata : 8;  /* [ 7: 0],          w,          x */
+            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep2_tx_fifo_wdata;
+
+    /* 0x12C : ep2_rx_fifo_rdata */
+    union {
+        struct
+        {
+            uint32_t ep2_rx_fifo_rdata : 8;  /* [ 7: 0],          r,        0x0 */
+            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep2_rx_fifo_rdata;
+
+    /* 0x130 : ep3_fifo_config */
+    union {
+        struct
+        {
+            uint32_t ep3_dma_tx_en         : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t ep3_dma_rx_en         : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t ep3_tx_fifo_clr       : 1;  /* [    2],        w1c,        0x0 */
+            uint32_t ep3_rx_fifo_clr       : 1;  /* [    3],        w1c,        0x0 */
+            uint32_t ep3_tx_fifo_overflow  : 1;  /* [    4],          r,        0x0 */
+            uint32_t ep3_tx_fifo_underflow : 1;  /* [    5],          r,        0x0 */
+            uint32_t ep3_rx_fifo_overflow  : 1;  /* [    6],          r,        0x0 */
+            uint32_t ep3_rx_fifo_underflow : 1;  /* [    7],          r,        0x0 */
+            uint32_t reserved_8_31         : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep3_fifo_config;
+
+    /* 0x134 : ep3_fifo_status */
+    union {
+        struct
+        {
+            uint32_t ep3_tx_fifo_cnt   : 7; /* [ 6: 0],          r,       0x40 */
+            uint32_t reserved_7_13     : 7; /* [13: 7],       rsvd,        0x0 */
+            uint32_t ep3_tx_fifo_empty : 1; /* [   14],          r,        0x1 */
+            uint32_t ep3_tx_fifo_full  : 1; /* [   15],          r,        0x0 */
+            uint32_t ep3_rx_fifo_cnt   : 7; /* [22:16],          r,        0x0 */
+            uint32_t reserved_23_29    : 7; /* [29:23],       rsvd,        0x0 */
+            uint32_t ep3_rx_fifo_empty : 1; /* [   30],          r,        0x1 */
+            uint32_t ep3_rx_fifo_full  : 1; /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep3_fifo_status;
+
+    /* 0x138 : ep3_tx_fifo_wdata */
+    union {
+        struct
+        {
+            uint32_t ep3_tx_fifo_wdata : 8;  /* [ 7: 0],          w,          x */
+            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep3_tx_fifo_wdata;
+
+    /* 0x13C : ep3_rx_fifo_rdata */
+    union {
+        struct
+        {
+            uint32_t ep3_rx_fifo_rdata : 8;  /* [ 7: 0],          r,        0x0 */
+            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep3_rx_fifo_rdata;
+
+    /* 0x140 : ep4_fifo_config */
+    union {
+        struct
+        {
+            uint32_t ep4_dma_tx_en         : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t ep4_dma_rx_en         : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t ep4_tx_fifo_clr       : 1;  /* [    2],        w1c,        0x0 */
+            uint32_t ep4_rx_fifo_clr       : 1;  /* [    3],        w1c,        0x0 */
+            uint32_t ep4_tx_fifo_overflow  : 1;  /* [    4],          r,        0x0 */
+            uint32_t ep4_tx_fifo_underflow : 1;  /* [    5],          r,        0x0 */
+            uint32_t ep4_rx_fifo_overflow  : 1;  /* [    6],          r,        0x0 */
+            uint32_t ep4_rx_fifo_underflow : 1;  /* [    7],          r,        0x0 */
+            uint32_t reserved_8_31         : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep4_fifo_config;
+
+    /* 0x144 : ep4_fifo_status */
+    union {
+        struct
+        {
+            uint32_t ep4_tx_fifo_cnt   : 7; /* [ 6: 0],          r,       0x40 */
+            uint32_t reserved_7_13     : 7; /* [13: 7],       rsvd,        0x0 */
+            uint32_t ep4_tx_fifo_empty : 1; /* [   14],          r,        0x1 */
+            uint32_t ep4_tx_fifo_full  : 1; /* [   15],          r,        0x0 */
+            uint32_t ep4_rx_fifo_cnt   : 7; /* [22:16],          r,        0x0 */
+            uint32_t reserved_23_29    : 7; /* [29:23],       rsvd,        0x0 */
+            uint32_t ep4_rx_fifo_empty : 1; /* [   30],          r,        0x1 */
+            uint32_t ep4_rx_fifo_full  : 1; /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep4_fifo_status;
+
+    /* 0x148 : ep4_tx_fifo_wdata */
+    union {
+        struct
+        {
+            uint32_t ep4_tx_fifo_wdata : 8;  /* [ 7: 0],          w,          x */
+            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep4_tx_fifo_wdata;
+
+    /* 0x14C : ep4_rx_fifo_rdata */
+    union {
+        struct
+        {
+            uint32_t ep4_rx_fifo_rdata : 8;  /* [ 7: 0],          r,        0x0 */
+            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep4_rx_fifo_rdata;
+
+    /* 0x150 : ep5_fifo_config */
+    union {
+        struct
+        {
+            uint32_t ep5_dma_tx_en         : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t ep5_dma_rx_en         : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t ep5_tx_fifo_clr       : 1;  /* [    2],        w1c,        0x0 */
+            uint32_t ep5_rx_fifo_clr       : 1;  /* [    3],        w1c,        0x0 */
+            uint32_t ep5_tx_fifo_overflow  : 1;  /* [    4],          r,        0x0 */
+            uint32_t ep5_tx_fifo_underflow : 1;  /* [    5],          r,        0x0 */
+            uint32_t ep5_rx_fifo_overflow  : 1;  /* [    6],          r,        0x0 */
+            uint32_t ep5_rx_fifo_underflow : 1;  /* [    7],          r,        0x0 */
+            uint32_t reserved_8_31         : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep5_fifo_config;
+
+    /* 0x154 : ep5_fifo_status */
+    union {
+        struct
+        {
+            uint32_t ep5_tx_fifo_cnt   : 7; /* [ 6: 0],          r,       0x40 */
+            uint32_t reserved_7_13     : 7; /* [13: 7],       rsvd,        0x0 */
+            uint32_t ep5_tx_fifo_empty : 1; /* [   14],          r,        0x1 */
+            uint32_t ep5_tx_fifo_full  : 1; /* [   15],          r,        0x0 */
+            uint32_t ep5_rx_fifo_cnt   : 7; /* [22:16],          r,        0x0 */
+            uint32_t reserved_23_29    : 7; /* [29:23],       rsvd,        0x0 */
+            uint32_t ep5_rx_fifo_empty : 1; /* [   30],          r,        0x1 */
+            uint32_t ep5_rx_fifo_full  : 1; /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep5_fifo_status;
+
+    /* 0x158 : ep5_tx_fifo_wdata */
+    union {
+        struct
+        {
+            uint32_t ep5_tx_fifo_wdata : 8;  /* [ 7: 0],          w,          x */
+            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep5_tx_fifo_wdata;
+
+    /* 0x15C : ep5_rx_fifo_rdata */
+    union {
+        struct
+        {
+            uint32_t ep5_rx_fifo_rdata : 8;  /* [ 7: 0],          r,        0x0 */
+            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep5_rx_fifo_rdata;
+
+    /* 0x160 : ep6_fifo_config */
+    union {
+        struct
+        {
+            uint32_t ep6_dma_tx_en         : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t ep6_dma_rx_en         : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t ep6_tx_fifo_clr       : 1;  /* [    2],        w1c,        0x0 */
+            uint32_t ep6_rx_fifo_clr       : 1;  /* [    3],        w1c,        0x0 */
+            uint32_t ep6_tx_fifo_overflow  : 1;  /* [    4],          r,        0x0 */
+            uint32_t ep6_tx_fifo_underflow : 1;  /* [    5],          r,        0x0 */
+            uint32_t ep6_rx_fifo_overflow  : 1;  /* [    6],          r,        0x0 */
+            uint32_t ep6_rx_fifo_underflow : 1;  /* [    7],          r,        0x0 */
+            uint32_t reserved_8_31         : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep6_fifo_config;
+
+    /* 0x164 : ep6_fifo_status */
+    union {
+        struct
+        {
+            uint32_t ep6_tx_fifo_cnt   : 7; /* [ 6: 0],          r,       0x40 */
+            uint32_t reserved_7_13     : 7; /* [13: 7],       rsvd,        0x0 */
+            uint32_t ep6_tx_fifo_empty : 1; /* [   14],          r,        0x1 */
+            uint32_t ep6_tx_fifo_full  : 1; /* [   15],          r,        0x0 */
+            uint32_t ep6_rx_fifo_cnt   : 7; /* [22:16],          r,        0x0 */
+            uint32_t reserved_23_29    : 7; /* [29:23],       rsvd,        0x0 */
+            uint32_t ep6_rx_fifo_empty : 1; /* [   30],          r,        0x1 */
+            uint32_t ep6_rx_fifo_full  : 1; /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep6_fifo_status;
+
+    /* 0x168 : ep6_tx_fifo_wdata */
+    union {
+        struct
+        {
+            uint32_t ep6_tx_fifo_wdata : 8;  /* [ 7: 0],          w,          x */
+            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep6_tx_fifo_wdata;
+
+    /* 0x16C : ep6_rx_fifo_rdata */
+    union {
+        struct
+        {
+            uint32_t ep6_rx_fifo_rdata : 8;  /* [ 7: 0],          r,        0x0 */
+            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep6_rx_fifo_rdata;
+
+    /* 0x170 : ep7_fifo_config */
+    union {
+        struct
+        {
+            uint32_t ep7_dma_tx_en         : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t ep7_dma_rx_en         : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t ep7_tx_fifo_clr       : 1;  /* [    2],        w1c,        0x0 */
+            uint32_t ep7_rx_fifo_clr       : 1;  /* [    3],        w1c,        0x0 */
+            uint32_t ep7_tx_fifo_overflow  : 1;  /* [    4],          r,        0x0 */
+            uint32_t ep7_tx_fifo_underflow : 1;  /* [    5],          r,        0x0 */
+            uint32_t ep7_rx_fifo_overflow  : 1;  /* [    6],          r,        0x0 */
+            uint32_t ep7_rx_fifo_underflow : 1;  /* [    7],          r,        0x0 */
+            uint32_t reserved_8_31         : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep7_fifo_config;
+
+    /* 0x174 : ep7_fifo_status */
+    union {
+        struct
+        {
+            uint32_t ep7_tx_fifo_cnt   : 7; /* [ 6: 0],          r,       0x40 */
+            uint32_t reserved_7_13     : 7; /* [13: 7],       rsvd,        0x0 */
+            uint32_t ep7_tx_fifo_empty : 1; /* [   14],          r,        0x1 */
+            uint32_t ep7_tx_fifo_full  : 1; /* [   15],          r,        0x0 */
+            uint32_t ep7_rx_fifo_cnt   : 7; /* [22:16],          r,        0x0 */
+            uint32_t reserved_23_29    : 7; /* [29:23],       rsvd,        0x0 */
+            uint32_t ep7_rx_fifo_empty : 1; /* [   30],          r,        0x1 */
+            uint32_t ep7_rx_fifo_full  : 1; /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep7_fifo_status;
+
+    /* 0x178 : ep7_tx_fifo_wdata */
+    union {
+        struct
+        {
+            uint32_t ep7_tx_fifo_wdata : 8;  /* [ 7: 0],          w,          x */
+            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep7_tx_fifo_wdata;
+
+    /* 0x17C : ep7_rx_fifo_rdata */
+    union {
+        struct
+        {
+            uint32_t ep7_rx_fifo_rdata : 8;  /* [ 7: 0],          r,        0x0 */
+            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ep7_rx_fifo_rdata;
+
+    /* 0x180  reserved */
+    uint8_t RESERVED0x180[112];
+
+    /* 0x1F0 : rsvd_0 */
+    union {
+        struct
+        {
+            uint32_t rsvd_0 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } rsvd_0;
+
+    /* 0x1F4 : rsvd_1 */
+    union {
+        struct
+        {
+            uint32_t rsvd_1 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } rsvd_1;
+
+    /* 0x1f8  reserved */
+    uint8_t RESERVED0x1f8[4];
+
+    /* 0x1FC : xcvr_if_config */
+    union {
+        struct
+        {
+            uint32_t cr_xcvr_force_tx_en : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t cr_xcvr_force_tx_oe : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t cr_xcvr_force_tx_dp : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t cr_xcvr_force_tx_dn : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t cr_xcvr_force_rx_en : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t cr_xcvr_force_rx_d  : 1;  /* [    5],        r/w,        0x1 */
+            uint32_t cr_xcvr_force_rx_dp : 1;  /* [    6],        r/w,        0x1 */
+            uint32_t cr_xcvr_force_rx_dn : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t cr_xcvr_om_rx_sel   : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t cr_xcvr_om_rx_d     : 1;  /* [    9],        r/w,        0x1 */
+            uint32_t cr_xcvr_om_rx_dp    : 1;  /* [   10],        r/w,        0x1 */
+            uint32_t cr_xcvr_om_rx_dn    : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t reserved_12_30      : 19; /* [30:12],       rsvd,        0x0 */
+            uint32_t sts_vbus_det        : 1;  /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } xcvr_if_config;
+};
+
+typedef volatile struct usb_reg usb_reg_t;
+
+#endif /* __USB_REG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/clic.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/clic.h
new file mode 100644
index 00000000..3ea51390
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/clic.h
@@ -0,0 +1,21 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_CLIC_H
+#define _SIFIVE_CLIC_H
+
+#define CLIC_CTRL_ADDR  0x02000000UL
+#define CLIC_HART0_ADDR 0x02800000UL
+
+#define CLIC_MSIP          0x0000
+#define CLIC_MSIP_size     0x4
+#define CLIC_MTIMECMP      0x4000
+#define CLIC_MTIMECMP_size 0x8
+#define CLIC_MTIME         0xBFF8
+#define CLIC_MTIME_size    0x8
+
+#define CLIC_INTIP  0x000
+#define CLIC_INTIE  0x400
+#define CLIC_INTCFG 0x800
+#define CLIC_CFG    0xc00
+
+#endif /* _SIFIVE_CLIC_H */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/riscv_bits.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/riscv_bits.h
new file mode 100644
index 00000000..16b15bcd
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/riscv_bits.h
@@ -0,0 +1,36 @@
+// See LICENSE for license details.
+#ifndef _RISCV_BITS_H
+#define _RISCV_BITS_H
+
+#define likely(x)   __builtin_expect((x), 1)
+#define unlikely(x) __builtin_expect((x), 0)
+
+#define ROUNDUP(a, b)   ((((a)-1) / (b) + 1) * (b))
+#define ROUNDDOWN(a, b) ((a) / (b) * (b))
+
+#define MAX(a, b)        ((a) > (b) ? (a) : (b))
+#define MIN(a, b)        ((a) < (b) ? (a) : (b))
+#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
+
+#define EXTRACT_FIELD(val, which)          (((val) & (which)) / ((which) & ~((which)-1)))
+#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
+
+#define STR(x)  XSTR(x)
+#define XSTR(x) #x
+
+#if __riscv_xlen == 64
+#define SLL32        sllw
+#define STORE        sd
+#define LOAD         ld
+#define LWU          lwu
+#define LOG_REGBYTES 3
+#else
+#define SLL32        sll
+#define STORE        sw
+#define LOAD         lw
+#define LWU          lw
+#define LOG_REGBYTES 2
+#endif
+#define REGBYTES (1 << LOG_REGBYTES)
+
+#endif
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/riscv_const.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/riscv_const.h
new file mode 100644
index 00000000..109d1dff
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/riscv_const.h
@@ -0,0 +1,18 @@
+// See LICENSE for license details.
+/* Derived from  */
+
+#ifndef _RISCV_CONST_H
+#define _RISCV_CONST_H
+
+#ifdef __ASSEMBLER__
+#define _AC(X, Y) X
+#define _AT(T, X) X
+#else
+#define _AC(X, Y) (X##Y)
+#define _AT(T, X) ((T)(X))
+#endif /* !__ASSEMBLER__*/
+
+#define _BITUL(x)  (_AC(1, UL) << (x))
+#define _BITULL(x) (_AC(1, ULL) << (x))
+
+#endif /* _NUCLEI_CONST_H */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/riscv_encoding.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/riscv_encoding.h
new file mode 100644
index 00000000..4987ac26
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/riscv_encoding.h
@@ -0,0 +1,1360 @@
+// See LICENSE for license details.
+
+#ifndef RISCV_CSR_ENCODING_H
+#define RISCV_CSR_ENCODING_H
+
+#define MSTATUS_UIE  0x00000001
+#define MSTATUS_SIE  0x00000002
+#define MSTATUS_HIE  0x00000004
+#define MSTATUS_MIE  0x00000008
+#define MSTATUS_UPIE 0x00000010
+#define MSTATUS_SPIE 0x00000020
+#define MSTATUS_HPIE 0x00000040
+#define MSTATUS_MPIE 0x00000080
+#define MSTATUS_SPP  0x00000100
+#define MSTATUS_MPP  0x00001800
+#define MSTATUS_FS   0x00006000
+#define MSTATUS_XS   0x00018000
+#define MSTATUS_MPRV 0x00020000
+#define MSTATUS_PUM  0x00040000
+#define MSTATUS_MXR  0x00080000
+#define MSTATUS_VM   0x1F000000
+#define MSTATUS32_SD 0x80000000
+#define MSTATUS64_SD 0x8000000000000000
+
+#define SSTATUS_UIE  0x00000001
+#define SSTATUS_SIE  0x00000002
+#define SSTATUS_UPIE 0x00000010
+#define SSTATUS_SPIE 0x00000020
+#define SSTATUS_SPP  0x00000100
+#define SSTATUS_FS   0x00006000
+#define SSTATUS_XS   0x00018000
+#define SSTATUS_PUM  0x00040000
+#define SSTATUS32_SD 0x80000000
+#define SSTATUS64_SD 0x8000000000000000
+
+#define DCSR_XDEBUGVER (3U << 30)
+#define DCSR_NDRESET   (1 << 29)
+#define DCSR_FULLRESET (1 << 28)
+#define DCSR_EBREAKM   (1 << 15)
+#define DCSR_EBREAKH   (1 << 14)
+#define DCSR_EBREAKS   (1 << 13)
+#define DCSR_EBREAKU   (1 << 12)
+#define DCSR_STOPCYCLE (1 << 10)
+#define DCSR_STOPTIME  (1 << 9)
+#define DCSR_CAUSE     (7 << 6)
+#define DCSR_DEBUGINT  (1 << 5)
+#define DCSR_HALT      (1 << 3)
+#define DCSR_STEP      (1 << 2)
+#define DCSR_PRV       (3 << 0)
+
+#define DCSR_CAUSE_NONE     0
+#define DCSR_CAUSE_SWBP     1
+#define DCSR_CAUSE_HWBP     2
+#define DCSR_CAUSE_DEBUGINT 3
+#define DCSR_CAUSE_STEP     4
+#define DCSR_CAUSE_HALT     5
+
+#define MCONTROL_TYPE(xlen)    (0xfULL << ((xlen)-4))
+#define MCONTROL_DMODE(xlen)   (1ULL << ((xlen)-5))
+#define MCONTROL_MASKMAX(xlen) (0x3fULL << ((xlen)-11))
+
+#define MCONTROL_SELECT  (1 << 19)
+#define MCONTROL_TIMING  (1 << 18)
+#define MCONTROL_ACTION  (0x3f << 12)
+#define MCONTROL_CHAIN   (1 << 11)
+#define MCONTROL_MATCH   (0xf << 7)
+#define MCONTROL_M       (1 << 6)
+#define MCONTROL_H       (1 << 5)
+#define MCONTROL_S       (1 << 4)
+#define MCONTROL_U       (1 << 3)
+#define MCONTROL_EXECUTE (1 << 2)
+#define MCONTROL_STORE   (1 << 1)
+#define MCONTROL_LOAD    (1 << 0)
+
+#define MCONTROL_TYPE_NONE  0
+#define MCONTROL_TYPE_MATCH 2
+
+#define MCONTROL_ACTION_DEBUG_EXCEPTION 0
+#define MCONTROL_ACTION_DEBUG_MODE      1
+#define MCONTROL_ACTION_TRACE_START     2
+#define MCONTROL_ACTION_TRACE_STOP      3
+#define MCONTROL_ACTION_TRACE_EMIT      4
+
+#define MCONTROL_MATCH_EQUAL     0
+#define MCONTROL_MATCH_NAPOT     1
+#define MCONTROL_MATCH_GE        2
+#define MCONTROL_MATCH_LT        3
+#define MCONTROL_MATCH_MASK_LOW  4
+#define MCONTROL_MATCH_MASK_HIGH 5
+
+#define MIP_SSIP (1 << IRQ_S_SOFT)
+#define MIP_HSIP (1 << IRQ_H_SOFT)
+#define MIP_MSIP (1 << IRQ_M_SOFT)
+#define MIP_STIP (1 << IRQ_S_TIMER)
+#define MIP_HTIP (1 << IRQ_H_TIMER)
+#define MIP_MTIP (1 << IRQ_M_TIMER)
+#define MIP_SEIP (1 << IRQ_S_EXT)
+#define MIP_HEIP (1 << IRQ_H_EXT)
+#define MIP_MEIP (1 << IRQ_M_EXT)
+
+#define MIE_SSIE MIP_SSIP
+#define MIE_HSIE MIP_HSIP
+#define MIE_MSIE MIP_MSIP
+#define MIE_STIE MIP_STIP
+#define MIE_HTIE MIP_HTIP
+#define MIE_MTIE MIP_MTIP
+#define MIE_SEIE MIP_SEIP
+#define MIE_HEIE MIP_HEIP
+#define MIE_MEIE MIP_MEIP
+
+#define SIP_SSIP MIP_SSIP
+#define SIP_STIP MIP_STIP
+
+#define PRV_U 0
+#define PRV_S 1
+#define PRV_H 2
+#define PRV_M 3
+
+#define VM_MBARE 0
+#define VM_MBB   1
+#define VM_MBBID 2
+#define VM_SV32  8
+#define VM_SV39  9
+#define VM_SV48  10
+
+#define IRQ_S_SOFT  1
+#define IRQ_H_SOFT  2
+#define IRQ_M_SOFT  3
+#define IRQ_S_TIMER 5
+#define IRQ_H_TIMER 6
+#define IRQ_M_TIMER 7
+#define IRQ_S_EXT   9
+#define IRQ_H_EXT   10
+#define IRQ_M_EXT   11
+#define IRQ_COP     12
+#define IRQ_HOST    13
+
+#define DEFAULT_RSTVEC     0x00001000
+#define DEFAULT_NMIVEC     0x00001004
+#define DEFAULT_MTVEC      0x00001010
+#define CONFIG_STRING_ADDR 0x0000100C
+#define EXT_IO_BASE        0x40000000
+#define DRAM_BASE          0x80000000
+
+// page table entry (PTE) fields
+#define PTE_V    0x001 // Valid
+#define PTE_R    0x002 // Read
+#define PTE_W    0x004 // Write
+#define PTE_X    0x008 // Execute
+#define PTE_U    0x010 // User
+#define PTE_G    0x020 // Global
+#define PTE_A    0x040 // Accessed
+#define PTE_D    0x080 // Dirty
+#define PTE_SOFT 0x300 // Reserved for Software
+
+#define PTE_PPN_SHIFT 10
+
+#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
+
+#ifdef __riscv
+
+#ifdef __riscv64
+#define MSTATUS_SD         MSTATUS64_SD
+#define SSTATUS_SD         SSTATUS64_SD
+#define RISCV_PGLEVEL_BITS 9
+#else
+#define MSTATUS_SD         MSTATUS32_SD
+#define SSTATUS_SD         SSTATUS32_SD
+#define RISCV_PGLEVEL_BITS 10
+#endif
+#define RISCV_PGSHIFT 12
+#define RISCV_PGSIZE  (1 << RISCV_PGSHIFT)
+
+#ifndef __ASSEMBLER__
+
+#ifdef __GNUC__
+
+#define asm __asm
+
+#define read_fpu(reg) ({ unsigned long __tmp; \
+        asm volatile ("fmv.x.w %0, " #reg : "=r"(__tmp)); \
+        __tmp; })
+
+#define write_fpu(reg, val) ({ \
+        if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+            asm volatile ("fmv.w.x " #reg ", %0" :: "i"(val)); \
+        else \
+            asm volatile ("fmv.w.x " #reg ", %0" :: "r"(val)); })
+
+#define read_csr(reg) ({ unsigned long __tmp; \
+        asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+        __tmp; })
+
+#define write_csr(reg, val) ({ \
+        if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+            asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
+        else \
+            asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
+
+#define swap_csr(reg, val) ({ unsigned long __tmp; \
+        if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+            asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
+        else \
+            asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
+        __tmp; })
+
+#define set_csr(reg, bit) ({ unsigned long __tmp; \
+        if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+            asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+        else \
+            asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+        __tmp; })
+
+#define clear_csr(reg, bit) ({ unsigned long __tmp; \
+        if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+            asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+        else \
+            asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+        __tmp; })
+
+#define rdtime()    read_csr(time)
+#define rdcycle()   read_csr(cycle)
+#define rdinstret() read_csr(instret)
+
+#endif
+
+#endif
+
+#endif
+
+#endif
+/* Automatically generated by parse-opcodes */
+#ifndef RISCV_ENCODING_H
+#define RISCV_ENCODING_H
+#define MATCH_BEQ                0x63
+#define MASK_BEQ                 0x707f
+#define MATCH_BNE                0x1063
+#define MASK_BNE                 0x707f
+#define MATCH_BLT                0x4063
+#define MASK_BLT                 0x707f
+#define MATCH_BGE                0x5063
+#define MASK_BGE                 0x707f
+#define MATCH_BLTU               0x6063
+#define MASK_BLTU                0x707f
+#define MATCH_BGEU               0x7063
+#define MASK_BGEU                0x707f
+#define MATCH_JALR               0x67
+#define MASK_JALR                0x707f
+#define MATCH_JAL                0x6f
+#define MASK_JAL                 0x7f
+#define MATCH_LUI                0x37
+#define MASK_LUI                 0x7f
+#define MATCH_AUIPC              0x17
+#define MASK_AUIPC               0x7f
+#define MATCH_ADDI               0x13
+#define MASK_ADDI                0x707f
+#define MATCH_SLLI               0x1013
+#define MASK_SLLI                0xfc00707f
+#define MATCH_SLTI               0x2013
+#define MASK_SLTI                0x707f
+#define MATCH_SLTIU              0x3013
+#define MASK_SLTIU               0x707f
+#define MATCH_XORI               0x4013
+#define MASK_XORI                0x707f
+#define MATCH_SRLI               0x5013
+#define MASK_SRLI                0xfc00707f
+#define MATCH_SRAI               0x40005013
+#define MASK_SRAI                0xfc00707f
+#define MATCH_ORI                0x6013
+#define MASK_ORI                 0x707f
+#define MATCH_ANDI               0x7013
+#define MASK_ANDI                0x707f
+#define MATCH_ADD                0x33
+#define MASK_ADD                 0xfe00707f
+#define MATCH_SUB                0x40000033
+#define MASK_SUB                 0xfe00707f
+#define MATCH_SLL                0x1033
+#define MASK_SLL                 0xfe00707f
+#define MATCH_SLT                0x2033
+#define MASK_SLT                 0xfe00707f
+#define MATCH_SLTU               0x3033
+#define MASK_SLTU                0xfe00707f
+#define MATCH_XOR                0x4033
+#define MASK_XOR                 0xfe00707f
+#define MATCH_SRL                0x5033
+#define MASK_SRL                 0xfe00707f
+#define MATCH_SRA                0x40005033
+#define MASK_SRA                 0xfe00707f
+#define MATCH_OR                 0x6033
+#define MASK_OR                  0xfe00707f
+#define MATCH_AND                0x7033
+#define MASK_AND                 0xfe00707f
+#define MATCH_ADDIW              0x1b
+#define MASK_ADDIW               0x707f
+#define MATCH_SLLIW              0x101b
+#define MASK_SLLIW               0xfe00707f
+#define MATCH_SRLIW              0x501b
+#define MASK_SRLIW               0xfe00707f
+#define MATCH_SRAIW              0x4000501b
+#define MASK_SRAIW               0xfe00707f
+#define MATCH_ADDW               0x3b
+#define MASK_ADDW                0xfe00707f
+#define MATCH_SUBW               0x4000003b
+#define MASK_SUBW                0xfe00707f
+#define MATCH_SLLW               0x103b
+#define MASK_SLLW                0xfe00707f
+#define MATCH_SRLW               0x503b
+#define MASK_SRLW                0xfe00707f
+#define MATCH_SRAW               0x4000503b
+#define MASK_SRAW                0xfe00707f
+#define MATCH_LB                 0x3
+#define MASK_LB                  0x707f
+#define MATCH_LH                 0x1003
+#define MASK_LH                  0x707f
+#define MATCH_LW                 0x2003
+#define MASK_LW                  0x707f
+#define MATCH_LD                 0x3003
+#define MASK_LD                  0x707f
+#define MATCH_LBU                0x4003
+#define MASK_LBU                 0x707f
+#define MATCH_LHU                0x5003
+#define MASK_LHU                 0x707f
+#define MATCH_LWU                0x6003
+#define MASK_LWU                 0x707f
+#define MATCH_SB                 0x23
+#define MASK_SB                  0x707f
+#define MATCH_SH                 0x1023
+#define MASK_SH                  0x707f
+#define MATCH_SW                 0x2023
+#define MASK_SW                  0x707f
+#define MATCH_SD                 0x3023
+#define MASK_SD                  0x707f
+#define MATCH_FENCE              0xf
+#define MASK_FENCE               0x707f
+#define MATCH_FENCE_I            0x100f
+#define MASK_FENCE_I             0x707f
+#define MATCH_MUL                0x2000033
+#define MASK_MUL                 0xfe00707f
+#define MATCH_MULH               0x2001033
+#define MASK_MULH                0xfe00707f
+#define MATCH_MULHSU             0x2002033
+#define MASK_MULHSU              0xfe00707f
+#define MATCH_MULHU              0x2003033
+#define MASK_MULHU               0xfe00707f
+#define MATCH_DIV                0x2004033
+#define MASK_DIV                 0xfe00707f
+#define MATCH_DIVU               0x2005033
+#define MASK_DIVU                0xfe00707f
+#define MATCH_REM                0x2006033
+#define MASK_REM                 0xfe00707f
+#define MATCH_REMU               0x2007033
+#define MASK_REMU                0xfe00707f
+#define MATCH_MULW               0x200003b
+#define MASK_MULW                0xfe00707f
+#define MATCH_DIVW               0x200403b
+#define MASK_DIVW                0xfe00707f
+#define MATCH_DIVUW              0x200503b
+#define MASK_DIVUW               0xfe00707f
+#define MATCH_REMW               0x200603b
+#define MASK_REMW                0xfe00707f
+#define MATCH_REMUW              0x200703b
+#define MASK_REMUW               0xfe00707f
+#define MATCH_AMOADD_W           0x202f
+#define MASK_AMOADD_W            0xf800707f
+#define MATCH_AMOXOR_W           0x2000202f
+#define MASK_AMOXOR_W            0xf800707f
+#define MATCH_AMOOR_W            0x4000202f
+#define MASK_AMOOR_W             0xf800707f
+#define MATCH_AMOAND_W           0x6000202f
+#define MASK_AMOAND_W            0xf800707f
+#define MATCH_AMOMIN_W           0x8000202f
+#define MASK_AMOMIN_W            0xf800707f
+#define MATCH_AMOMAX_W           0xa000202f
+#define MASK_AMOMAX_W            0xf800707f
+#define MATCH_AMOMINU_W          0xc000202f
+#define MASK_AMOMINU_W           0xf800707f
+#define MATCH_AMOMAXU_W          0xe000202f
+#define MASK_AMOMAXU_W           0xf800707f
+#define MATCH_AMOSWAP_W          0x800202f
+#define MASK_AMOSWAP_W           0xf800707f
+#define MATCH_LR_W               0x1000202f
+#define MASK_LR_W                0xf9f0707f
+#define MATCH_SC_W               0x1800202f
+#define MASK_SC_W                0xf800707f
+#define MATCH_AMOADD_D           0x302f
+#define MASK_AMOADD_D            0xf800707f
+#define MATCH_AMOXOR_D           0x2000302f
+#define MASK_AMOXOR_D            0xf800707f
+#define MATCH_AMOOR_D            0x4000302f
+#define MASK_AMOOR_D             0xf800707f
+#define MATCH_AMOAND_D           0x6000302f
+#define MASK_AMOAND_D            0xf800707f
+#define MATCH_AMOMIN_D           0x8000302f
+#define MASK_AMOMIN_D            0xf800707f
+#define MATCH_AMOMAX_D           0xa000302f
+#define MASK_AMOMAX_D            0xf800707f
+#define MATCH_AMOMINU_D          0xc000302f
+#define MASK_AMOMINU_D           0xf800707f
+#define MATCH_AMOMAXU_D          0xe000302f
+#define MASK_AMOMAXU_D           0xf800707f
+#define MATCH_AMOSWAP_D          0x800302f
+#define MASK_AMOSWAP_D           0xf800707f
+#define MATCH_LR_D               0x1000302f
+#define MASK_LR_D                0xf9f0707f
+#define MATCH_SC_D               0x1800302f
+#define MASK_SC_D                0xf800707f
+#define MATCH_ECALL              0x73
+#define MASK_ECALL               0xffffffff
+#define MATCH_EBREAK             0x100073
+#define MASK_EBREAK              0xffffffff
+#define MATCH_URET               0x200073
+#define MASK_URET                0xffffffff
+#define MATCH_SRET               0x10200073
+#define MASK_SRET                0xffffffff
+#define MATCH_HRET               0x20200073
+#define MASK_HRET                0xffffffff
+#define MATCH_MRET               0x30200073
+#define MASK_MRET                0xffffffff
+#define MATCH_DRET               0x7b200073
+#define MASK_DRET                0xffffffff
+#define MATCH_SFENCE_VM          0x10400073
+#define MASK_SFENCE_VM           0xfff07fff
+#define MATCH_WFI                0x10500073
+#define MASK_WFI                 0xffffffff
+#define MATCH_CSRRW              0x1073
+#define MASK_CSRRW               0x707f
+#define MATCH_CSRRS              0x2073
+#define MASK_CSRRS               0x707f
+#define MATCH_CSRRC              0x3073
+#define MASK_CSRRC               0x707f
+#define MATCH_CSRRWI             0x5073
+#define MASK_CSRRWI              0x707f
+#define MATCH_CSRRSI             0x6073
+#define MASK_CSRRSI              0x707f
+#define MATCH_CSRRCI             0x7073
+#define MASK_CSRRCI              0x707f
+#define MATCH_FADD_S             0x53
+#define MASK_FADD_S              0xfe00007f
+#define MATCH_FSUB_S             0x8000053
+#define MASK_FSUB_S              0xfe00007f
+#define MATCH_FMUL_S             0x10000053
+#define MASK_FMUL_S              0xfe00007f
+#define MATCH_FDIV_S             0x18000053
+#define MASK_FDIV_S              0xfe00007f
+#define MATCH_FSGNJ_S            0x20000053
+#define MASK_FSGNJ_S             0xfe00707f
+#define MATCH_FSGNJN_S           0x20001053
+#define MASK_FSGNJN_S            0xfe00707f
+#define MATCH_FSGNJX_S           0x20002053
+#define MASK_FSGNJX_S            0xfe00707f
+#define MATCH_FMIN_S             0x28000053
+#define MASK_FMIN_S              0xfe00707f
+#define MATCH_FMAX_S             0x28001053
+#define MASK_FMAX_S              0xfe00707f
+#define MATCH_FSQRT_S            0x58000053
+#define MASK_FSQRT_S             0xfff0007f
+#define MATCH_FADD_D             0x2000053
+#define MASK_FADD_D              0xfe00007f
+#define MATCH_FSUB_D             0xa000053
+#define MASK_FSUB_D              0xfe00007f
+#define MATCH_FMUL_D             0x12000053
+#define MASK_FMUL_D              0xfe00007f
+#define MATCH_FDIV_D             0x1a000053
+#define MASK_FDIV_D              0xfe00007f
+#define MATCH_FSGNJ_D            0x22000053
+#define MASK_FSGNJ_D             0xfe00707f
+#define MATCH_FSGNJN_D           0x22001053
+#define MASK_FSGNJN_D            0xfe00707f
+#define MATCH_FSGNJX_D           0x22002053
+#define MASK_FSGNJX_D            0xfe00707f
+#define MATCH_FMIN_D             0x2a000053
+#define MASK_FMIN_D              0xfe00707f
+#define MATCH_FMAX_D             0x2a001053
+#define MASK_FMAX_D              0xfe00707f
+#define MATCH_FCVT_S_D           0x40100053
+#define MASK_FCVT_S_D            0xfff0007f
+#define MATCH_FCVT_D_S           0x42000053
+#define MASK_FCVT_D_S            0xfff0007f
+#define MATCH_FSQRT_D            0x5a000053
+#define MASK_FSQRT_D             0xfff0007f
+#define MATCH_FLE_S              0xa0000053
+#define MASK_FLE_S               0xfe00707f
+#define MATCH_FLT_S              0xa0001053
+#define MASK_FLT_S               0xfe00707f
+#define MATCH_FEQ_S              0xa0002053
+#define MASK_FEQ_S               0xfe00707f
+#define MATCH_FLE_D              0xa2000053
+#define MASK_FLE_D               0xfe00707f
+#define MATCH_FLT_D              0xa2001053
+#define MASK_FLT_D               0xfe00707f
+#define MATCH_FEQ_D              0xa2002053
+#define MASK_FEQ_D               0xfe00707f
+#define MATCH_FCVT_W_S           0xc0000053
+#define MASK_FCVT_W_S            0xfff0007f
+#define MATCH_FCVT_WU_S          0xc0100053
+#define MASK_FCVT_WU_S           0xfff0007f
+#define MATCH_FCVT_L_S           0xc0200053
+#define MASK_FCVT_L_S            0xfff0007f
+#define MATCH_FCVT_LU_S          0xc0300053
+#define MASK_FCVT_LU_S           0xfff0007f
+#define MATCH_FMV_X_S            0xe0000053
+#define MASK_FMV_X_S             0xfff0707f
+#define MATCH_FCLASS_S           0xe0001053
+#define MASK_FCLASS_S            0xfff0707f
+#define MATCH_FCVT_W_D           0xc2000053
+#define MASK_FCVT_W_D            0xfff0007f
+#define MATCH_FCVT_WU_D          0xc2100053
+#define MASK_FCVT_WU_D           0xfff0007f
+#define MATCH_FCVT_L_D           0xc2200053
+#define MASK_FCVT_L_D            0xfff0007f
+#define MATCH_FCVT_LU_D          0xc2300053
+#define MASK_FCVT_LU_D           0xfff0007f
+#define MATCH_FMV_X_D            0xe2000053
+#define MASK_FMV_X_D             0xfff0707f
+#define MATCH_FCLASS_D           0xe2001053
+#define MASK_FCLASS_D            0xfff0707f
+#define MATCH_FCVT_S_W           0xd0000053
+#define MASK_FCVT_S_W            0xfff0007f
+#define MATCH_FCVT_S_WU          0xd0100053
+#define MASK_FCVT_S_WU           0xfff0007f
+#define MATCH_FCVT_S_L           0xd0200053
+#define MASK_FCVT_S_L            0xfff0007f
+#define MATCH_FCVT_S_LU          0xd0300053
+#define MASK_FCVT_S_LU           0xfff0007f
+#define MATCH_FMV_S_X            0xf0000053
+#define MASK_FMV_S_X             0xfff0707f
+#define MATCH_FCVT_D_W           0xd2000053
+#define MASK_FCVT_D_W            0xfff0007f
+#define MATCH_FCVT_D_WU          0xd2100053
+#define MASK_FCVT_D_WU           0xfff0007f
+#define MATCH_FCVT_D_L           0xd2200053
+#define MASK_FCVT_D_L            0xfff0007f
+#define MATCH_FCVT_D_LU          0xd2300053
+#define MASK_FCVT_D_LU           0xfff0007f
+#define MATCH_FMV_D_X            0xf2000053
+#define MASK_FMV_D_X             0xfff0707f
+#define MATCH_FLW                0x2007
+#define MASK_FLW                 0x707f
+#define MATCH_FLD                0x3007
+#define MASK_FLD                 0x707f
+#define MATCH_FSW                0x2027
+#define MASK_FSW                 0x707f
+#define MATCH_FSD                0x3027
+#define MASK_FSD                 0x707f
+#define MATCH_FMADD_S            0x43
+#define MASK_FMADD_S             0x600007f
+#define MATCH_FMSUB_S            0x47
+#define MASK_FMSUB_S             0x600007f
+#define MATCH_FNMSUB_S           0x4b
+#define MASK_FNMSUB_S            0x600007f
+#define MATCH_FNMADD_S           0x4f
+#define MASK_FNMADD_S            0x600007f
+#define MATCH_FMADD_D            0x2000043
+#define MASK_FMADD_D             0x600007f
+#define MATCH_FMSUB_D            0x2000047
+#define MASK_FMSUB_D             0x600007f
+#define MATCH_FNMSUB_D           0x200004b
+#define MASK_FNMSUB_D            0x600007f
+#define MATCH_FNMADD_D           0x200004f
+#define MASK_FNMADD_D            0x600007f
+#define MATCH_C_NOP              0x1
+#define MASK_C_NOP               0xffff
+#define MATCH_C_ADDI16SP         0x6101
+#define MASK_C_ADDI16SP          0xef83
+#define MATCH_C_JR               0x8002
+#define MASK_C_JR                0xf07f
+#define MATCH_C_JALR             0x9002
+#define MASK_C_JALR              0xf07f
+#define MATCH_C_EBREAK           0x9002
+#define MASK_C_EBREAK            0xffff
+#define MATCH_C_LD               0x6000
+#define MASK_C_LD                0xe003
+#define MATCH_C_SD               0xe000
+#define MASK_C_SD                0xe003
+#define MATCH_C_ADDIW            0x2001
+#define MASK_C_ADDIW             0xe003
+#define MATCH_C_LDSP             0x6002
+#define MASK_C_LDSP              0xe003
+#define MATCH_C_SDSP             0xe002
+#define MASK_C_SDSP              0xe003
+#define MATCH_C_ADDI4SPN         0x0
+#define MASK_C_ADDI4SPN          0xe003
+#define MATCH_C_FLD              0x2000
+#define MASK_C_FLD               0xe003
+#define MATCH_C_LW               0x4000
+#define MASK_C_LW                0xe003
+#define MATCH_C_FLW              0x6000
+#define MASK_C_FLW               0xe003
+#define MATCH_C_FSD              0xa000
+#define MASK_C_FSD               0xe003
+#define MATCH_C_SW               0xc000
+#define MASK_C_SW                0xe003
+#define MATCH_C_FSW              0xe000
+#define MASK_C_FSW               0xe003
+#define MATCH_C_ADDI             0x1
+#define MASK_C_ADDI              0xe003
+#define MATCH_C_JAL              0x2001
+#define MASK_C_JAL               0xe003
+#define MATCH_C_LI               0x4001
+#define MASK_C_LI                0xe003
+#define MATCH_C_LUI              0x6001
+#define MASK_C_LUI               0xe003
+#define MATCH_C_SRLI             0x8001
+#define MASK_C_SRLI              0xec03
+#define MATCH_C_SRAI             0x8401
+#define MASK_C_SRAI              0xec03
+#define MATCH_C_ANDI             0x8801
+#define MASK_C_ANDI              0xec03
+#define MATCH_C_SUB              0x8c01
+#define MASK_C_SUB               0xfc63
+#define MATCH_C_XOR              0x8c21
+#define MASK_C_XOR               0xfc63
+#define MATCH_C_OR               0x8c41
+#define MASK_C_OR                0xfc63
+#define MATCH_C_AND              0x8c61
+#define MASK_C_AND               0xfc63
+#define MATCH_C_SUBW             0x9c01
+#define MASK_C_SUBW              0xfc63
+#define MATCH_C_ADDW             0x9c21
+#define MASK_C_ADDW              0xfc63
+#define MATCH_C_J                0xa001
+#define MASK_C_J                 0xe003
+#define MATCH_C_BEQZ             0xc001
+#define MASK_C_BEQZ              0xe003
+#define MATCH_C_BNEZ             0xe001
+#define MASK_C_BNEZ              0xe003
+#define MATCH_C_SLLI             0x2
+#define MASK_C_SLLI              0xe003
+#define MATCH_C_FLDSP            0x2002
+#define MASK_C_FLDSP             0xe003
+#define MATCH_C_LWSP             0x4002
+#define MASK_C_LWSP              0xe003
+#define MATCH_C_FLWSP            0x6002
+#define MASK_C_FLWSP             0xe003
+#define MATCH_C_MV               0x8002
+#define MASK_C_MV                0xf003
+#define MATCH_C_ADD              0x9002
+#define MASK_C_ADD               0xf003
+#define MATCH_C_FSDSP            0xa002
+#define MASK_C_FSDSP             0xe003
+#define MATCH_C_SWSP             0xc002
+#define MASK_C_SWSP              0xe003
+#define MATCH_C_FSWSP            0xe002
+#define MASK_C_FSWSP             0xe003
+#define MATCH_CUSTOM0            0xb
+#define MASK_CUSTOM0             0x707f
+#define MATCH_CUSTOM0_RS1        0x200b
+#define MASK_CUSTOM0_RS1         0x707f
+#define MATCH_CUSTOM0_RS1_RS2    0x300b
+#define MASK_CUSTOM0_RS1_RS2     0x707f
+#define MATCH_CUSTOM0_RD         0x400b
+#define MASK_CUSTOM0_RD          0x707f
+#define MATCH_CUSTOM0_RD_RS1     0x600b
+#define MASK_CUSTOM0_RD_RS1      0x707f
+#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
+#define MASK_CUSTOM0_RD_RS1_RS2  0x707f
+#define MATCH_CUSTOM1            0x2b
+#define MASK_CUSTOM1             0x707f
+#define MATCH_CUSTOM1_RS1        0x202b
+#define MASK_CUSTOM1_RS1         0x707f
+#define MATCH_CUSTOM1_RS1_RS2    0x302b
+#define MASK_CUSTOM1_RS1_RS2     0x707f
+#define MATCH_CUSTOM1_RD         0x402b
+#define MASK_CUSTOM1_RD          0x707f
+#define MATCH_CUSTOM1_RD_RS1     0x602b
+#define MASK_CUSTOM1_RD_RS1      0x707f
+#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
+#define MASK_CUSTOM1_RD_RS1_RS2  0x707f
+#define MATCH_CUSTOM2            0x5b
+#define MASK_CUSTOM2             0x707f
+#define MATCH_CUSTOM2_RS1        0x205b
+#define MASK_CUSTOM2_RS1         0x707f
+#define MATCH_CUSTOM2_RS1_RS2    0x305b
+#define MASK_CUSTOM2_RS1_RS2     0x707f
+#define MATCH_CUSTOM2_RD         0x405b
+#define MASK_CUSTOM2_RD          0x707f
+#define MATCH_CUSTOM2_RD_RS1     0x605b
+#define MASK_CUSTOM2_RD_RS1      0x707f
+#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
+#define MASK_CUSTOM2_RD_RS1_RS2  0x707f
+#define MATCH_CUSTOM3            0x7b
+#define MASK_CUSTOM3             0x707f
+#define MATCH_CUSTOM3_RS1        0x207b
+#define MASK_CUSTOM3_RS1         0x707f
+#define MATCH_CUSTOM3_RS1_RS2    0x307b
+#define MASK_CUSTOM3_RS1_RS2     0x707f
+#define MATCH_CUSTOM3_RD         0x407b
+#define MASK_CUSTOM3_RD          0x707f
+#define MATCH_CUSTOM3_RD_RS1     0x607b
+#define MASK_CUSTOM3_RD_RS1      0x707f
+#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
+#define MASK_CUSTOM3_RD_RS1_RS2  0x707f
+#define CSR_FFLAGS               0x1
+#define CSR_FRM                  0x2
+#define CSR_FCSR                 0x3
+#define CSR_CYCLE                0xc00
+#define CSR_TIME                 0xc01
+#define CSR_INSTRET              0xc02
+#define CSR_HPMCOUNTER3          0xc03
+#define CSR_HPMCOUNTER4          0xc04
+#define CSR_HPMCOUNTER5          0xc05
+#define CSR_HPMCOUNTER6          0xc06
+#define CSR_HPMCOUNTER7          0xc07
+#define CSR_HPMCOUNTER8          0xc08
+#define CSR_HPMCOUNTER9          0xc09
+#define CSR_HPMCOUNTER10         0xc0a
+#define CSR_HPMCOUNTER11         0xc0b
+#define CSR_HPMCOUNTER12         0xc0c
+#define CSR_HPMCOUNTER13         0xc0d
+#define CSR_HPMCOUNTER14         0xc0e
+#define CSR_HPMCOUNTER15         0xc0f
+#define CSR_HPMCOUNTER16         0xc10
+#define CSR_HPMCOUNTER17         0xc11
+#define CSR_HPMCOUNTER18         0xc12
+#define CSR_HPMCOUNTER19         0xc13
+#define CSR_HPMCOUNTER20         0xc14
+#define CSR_HPMCOUNTER21         0xc15
+#define CSR_HPMCOUNTER22         0xc16
+#define CSR_HPMCOUNTER23         0xc17
+#define CSR_HPMCOUNTER24         0xc18
+#define CSR_HPMCOUNTER25         0xc19
+#define CSR_HPMCOUNTER26         0xc1a
+#define CSR_HPMCOUNTER27         0xc1b
+#define CSR_HPMCOUNTER28         0xc1c
+#define CSR_HPMCOUNTER29         0xc1d
+#define CSR_HPMCOUNTER30         0xc1e
+#define CSR_HPMCOUNTER31         0xc1f
+#define CSR_SSTATUS              0x100
+#define CSR_SIE                  0x104
+#define CSR_STVEC                0x105
+#define CSR_SSCRATCH             0x140
+#define CSR_SEPC                 0x141
+#define CSR_SCAUSE               0x142
+#define CSR_SBADADDR             0x143
+#define CSR_SIP                  0x144
+#define CSR_SPTBR                0x180
+#define CSR_MSTATUS              0x300
+#define CSR_MISA                 0x301
+#define CSR_MEDELEG              0x302
+#define CSR_MIDELEG              0x303
+#define CSR_MIE                  0x304
+#define CSR_MTVEC                0x305
+#define CSR_MCOUNTEREN           0x306
+#define CSR_MSCRATCH             0x340
+#define CSR_MEPC                 0x341
+#define CSR_MCAUSE               0x342
+#define CSR_MBADADDR             0x343
+#define CSR_MIP                  0x344
+#define CSR_TSELECT              0x7a0
+#define CSR_TDATA1               0x7a1
+#define CSR_TDATA2               0x7a2
+#define CSR_TDATA3               0x7a3
+#define CSR_DCSR                 0x7b0
+#define CSR_DPC                  0x7b1
+#define CSR_DSCRATCH             0x7b2
+#define CSR_MCYCLE               0xb00
+#define CSR_MINSTRET             0xb02
+#define CSR_MHPMCOUNTER3         0xb03
+#define CSR_MHPMCOUNTER4         0xb04
+#define CSR_MHPMCOUNTER5         0xb05
+#define CSR_MHPMCOUNTER6         0xb06
+#define CSR_MHPMCOUNTER7         0xb07
+#define CSR_MHPMCOUNTER8         0xb08
+#define CSR_MHPMCOUNTER9         0xb09
+#define CSR_MHPMCOUNTER10        0xb0a
+#define CSR_MHPMCOUNTER11        0xb0b
+#define CSR_MHPMCOUNTER12        0xb0c
+#define CSR_MHPMCOUNTER13        0xb0d
+#define CSR_MHPMCOUNTER14        0xb0e
+#define CSR_MHPMCOUNTER15        0xb0f
+#define CSR_MHPMCOUNTER16        0xb10
+#define CSR_MHPMCOUNTER17        0xb11
+#define CSR_MHPMCOUNTER18        0xb12
+#define CSR_MHPMCOUNTER19        0xb13
+#define CSR_MHPMCOUNTER20        0xb14
+#define CSR_MHPMCOUNTER21        0xb15
+#define CSR_MHPMCOUNTER22        0xb16
+#define CSR_MHPMCOUNTER23        0xb17
+#define CSR_MHPMCOUNTER24        0xb18
+#define CSR_MHPMCOUNTER25        0xb19
+#define CSR_MHPMCOUNTER26        0xb1a
+#define CSR_MHPMCOUNTER27        0xb1b
+#define CSR_MHPMCOUNTER28        0xb1c
+#define CSR_MHPMCOUNTER29        0xb1d
+#define CSR_MHPMCOUNTER30        0xb1e
+#define CSR_MHPMCOUNTER31        0xb1f
+#define CSR_MUCOUNTEREN          0x320
+#define CSR_MSCOUNTEREN          0x321
+#define CSR_MHPMEVENT3           0x323
+#define CSR_MHPMEVENT4           0x324
+#define CSR_MHPMEVENT5           0x325
+#define CSR_MHPMEVENT6           0x326
+#define CSR_MHPMEVENT7           0x327
+#define CSR_MHPMEVENT8           0x328
+#define CSR_MHPMEVENT9           0x329
+#define CSR_MHPMEVENT10          0x32a
+#define CSR_MHPMEVENT11          0x32b
+#define CSR_MHPMEVENT12          0x32c
+#define CSR_MHPMEVENT13          0x32d
+#define CSR_MHPMEVENT14          0x32e
+#define CSR_MHPMEVENT15          0x32f
+#define CSR_MHPMEVENT16          0x330
+#define CSR_MHPMEVENT17          0x331
+#define CSR_MHPMEVENT18          0x332
+#define CSR_MHPMEVENT19          0x333
+#define CSR_MHPMEVENT20          0x334
+#define CSR_MHPMEVENT21          0x335
+#define CSR_MHPMEVENT22          0x336
+#define CSR_MHPMEVENT23          0x337
+#define CSR_MHPMEVENT24          0x338
+#define CSR_MHPMEVENT25          0x339
+#define CSR_MHPMEVENT26          0x33a
+#define CSR_MHPMEVENT27          0x33b
+#define CSR_MHPMEVENT28          0x33c
+#define CSR_MHPMEVENT29          0x33d
+#define CSR_MHPMEVENT30          0x33e
+#define CSR_MHPMEVENT31          0x33f
+#define CSR_MVENDORID            0xf11
+#define CSR_MARCHID              0xf12
+#define CSR_MIMPID               0xf13
+#define CSR_MHARTID              0xf14
+#define CSR_CYCLEH               0xc80
+#define CSR_TIMEH                0xc81
+#define CSR_INSTRETH             0xc82
+#define CSR_HPMCOUNTER3H         0xc83
+#define CSR_HPMCOUNTER4H         0xc84
+#define CSR_HPMCOUNTER5H         0xc85
+#define CSR_HPMCOUNTER6H         0xc86
+#define CSR_HPMCOUNTER7H         0xc87
+#define CSR_HPMCOUNTER8H         0xc88
+#define CSR_HPMCOUNTER9H         0xc89
+#define CSR_HPMCOUNTER10H        0xc8a
+#define CSR_HPMCOUNTER11H        0xc8b
+#define CSR_HPMCOUNTER12H        0xc8c
+#define CSR_HPMCOUNTER13H        0xc8d
+#define CSR_HPMCOUNTER14H        0xc8e
+#define CSR_HPMCOUNTER15H        0xc8f
+#define CSR_HPMCOUNTER16H        0xc90
+#define CSR_HPMCOUNTER17H        0xc91
+#define CSR_HPMCOUNTER18H        0xc92
+#define CSR_HPMCOUNTER19H        0xc93
+#define CSR_HPMCOUNTER20H        0xc94
+#define CSR_HPMCOUNTER21H        0xc95
+#define CSR_HPMCOUNTER22H        0xc96
+#define CSR_HPMCOUNTER23H        0xc97
+#define CSR_HPMCOUNTER24H        0xc98
+#define CSR_HPMCOUNTER25H        0xc99
+#define CSR_HPMCOUNTER26H        0xc9a
+#define CSR_HPMCOUNTER27H        0xc9b
+#define CSR_HPMCOUNTER28H        0xc9c
+#define CSR_HPMCOUNTER29H        0xc9d
+#define CSR_HPMCOUNTER30H        0xc9e
+#define CSR_HPMCOUNTER31H        0xc9f
+#define CSR_MCYCLEH              0xb80
+#define CSR_MINSTRETH            0xb82
+#define CSR_MHPMCOUNTER3H        0xb83
+#define CSR_MHPMCOUNTER4H        0xb84
+#define CSR_MHPMCOUNTER5H        0xb85
+#define CSR_MHPMCOUNTER6H        0xb86
+#define CSR_MHPMCOUNTER7H        0xb87
+#define CSR_MHPMCOUNTER8H        0xb88
+#define CSR_MHPMCOUNTER9H        0xb89
+#define CSR_MHPMCOUNTER10H       0xb8a
+#define CSR_MHPMCOUNTER11H       0xb8b
+#define CSR_MHPMCOUNTER12H       0xb8c
+#define CSR_MHPMCOUNTER13H       0xb8d
+#define CSR_MHPMCOUNTER14H       0xb8e
+#define CSR_MHPMCOUNTER15H       0xb8f
+#define CSR_MHPMCOUNTER16H       0xb90
+#define CSR_MHPMCOUNTER17H       0xb91
+#define CSR_MHPMCOUNTER18H       0xb92
+#define CSR_MHPMCOUNTER19H       0xb93
+#define CSR_MHPMCOUNTER20H       0xb94
+#define CSR_MHPMCOUNTER21H       0xb95
+#define CSR_MHPMCOUNTER22H       0xb96
+#define CSR_MHPMCOUNTER23H       0xb97
+#define CSR_MHPMCOUNTER24H       0xb98
+#define CSR_MHPMCOUNTER25H       0xb99
+#define CSR_MHPMCOUNTER26H       0xb9a
+#define CSR_MHPMCOUNTER27H       0xb9b
+#define CSR_MHPMCOUNTER28H       0xb9c
+#define CSR_MHPMCOUNTER29H       0xb9d
+#define CSR_MHPMCOUNTER30H       0xb9e
+#define CSR_MHPMCOUNTER31H       0xb9f
+
+#define CSR_MTVT  0x307
+#define CSR_MNXTI 0x345
+
+#define CSR_MCOUNTINHIBIT 0x320
+
+#define CSR_MNVEC 0x7C3
+
+#define CSR_MTVT2      0x7EC
+#define CSR_JALMNXTI   0x7ED
+#define CSR_PUSHMCAUSE 0x7EE
+#define CSR_PUSHMEPC   0x7EF
+#define CSR_PUSHMSUBM  0x7EB
+
+#define CSR_WFE        0x810
+#define CSR_SLEEPVALUE 0x811
+#define CSR_TXEVT      0x812
+
+#define CSR_MMISC_CTL 0x7d0
+#define CSR_MSUBM     0x7c4
+
+#define CAUSE_MISALIGNED_FETCH    0x0
+#define CAUSE_FAULT_FETCH         0x1
+#define CAUSE_ILLEGAL_INSTRUCTION 0x2
+#define CAUSE_BREAKPOINT          0x3
+#define CAUSE_MISALIGNED_LOAD     0x4
+#define CAUSE_FAULT_LOAD          0x5
+#define CAUSE_MISALIGNED_STORE    0x6
+#define CAUSE_FAULT_STORE         0x7
+#define CAUSE_USER_ECALL          0x8
+#define CAUSE_SUPERVISOR_ECALL    0x9
+#define CAUSE_HYPERVISOR_ECALL    0xa
+#define CAUSE_MACHINE_ECALL       0xb
+#endif
+#ifdef DECLARE_INSN
+DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
+DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
+DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
+DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
+DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
+DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
+DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
+DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
+DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
+DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
+DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
+DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
+DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
+DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
+DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
+DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
+DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
+DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
+DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
+DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
+DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
+DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
+DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
+DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
+DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
+DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
+DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
+DECLARE_INSN(or, MATCH_OR, MASK_OR)
+DECLARE_INSN(and, MATCH_AND, MASK_AND)
+DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
+DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
+DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
+DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
+DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
+DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
+DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
+DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
+DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
+DECLARE_INSN(lb, MATCH_LB, MASK_LB)
+DECLARE_INSN(lh, MATCH_LH, MASK_LH)
+DECLARE_INSN(lw, MATCH_LW, MASK_LW)
+DECLARE_INSN(ld, MATCH_LD, MASK_LD)
+DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
+DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
+DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
+DECLARE_INSN(sb, MATCH_SB, MASK_SB)
+DECLARE_INSN(sh, MATCH_SH, MASK_SH)
+DECLARE_INSN(sw, MATCH_SW, MASK_SW)
+DECLARE_INSN(sd, MATCH_SD, MASK_SD)
+DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
+DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
+DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
+DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
+DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
+DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
+DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
+DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
+DECLARE_INSN(rem, MATCH_REM, MASK_REM)
+DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
+DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
+DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
+DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
+DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
+DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
+DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
+DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
+DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
+DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
+DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
+DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
+DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
+DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
+DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
+DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
+DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
+DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
+DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
+DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
+DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
+DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
+DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
+DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
+DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
+DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
+DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
+DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
+DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
+DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
+DECLARE_INSN(uret, MATCH_URET, MASK_URET)
+DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
+DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
+DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
+DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
+DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
+DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
+DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
+DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
+DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
+DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
+DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
+DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
+DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
+DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
+DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
+DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
+DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
+DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
+DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
+DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
+DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
+DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
+DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
+DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
+DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
+DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
+DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
+DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
+DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
+DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
+DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
+DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
+DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
+DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
+DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
+DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
+DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
+DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
+DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
+DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
+DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
+DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
+DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
+DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
+DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
+DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
+DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
+DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
+DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
+DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
+DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
+DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
+DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
+DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
+DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
+DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
+DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
+DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
+DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
+DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
+DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
+DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
+DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
+DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
+DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
+DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
+DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
+DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
+DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
+DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
+DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
+DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
+DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
+DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
+DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
+DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
+DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
+DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
+DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
+DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
+DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
+DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
+DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
+DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
+DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
+DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
+DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
+DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
+DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
+DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
+DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
+DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
+DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
+DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
+DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
+DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
+DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
+DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
+DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
+DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
+DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
+DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
+DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
+DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
+DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
+DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
+DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
+DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
+DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
+DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
+DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
+DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
+DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
+DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
+DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
+DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
+DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
+DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
+DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
+DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
+DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
+DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2,
+             MASK_CUSTOM0_RD_RS1_RS2)
+DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
+DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
+DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
+DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
+DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
+DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2,
+             MASK_CUSTOM1_RD_RS1_RS2)
+DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
+DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
+DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
+DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
+DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
+DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2,
+             MASK_CUSTOM2_RD_RS1_RS2)
+DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
+DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
+DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
+DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
+DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
+DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2,
+             MASK_CUSTOM3_RD_RS1_RS2)
+#endif
+#ifdef DECLARE_CSR
+DECLARE_CSR(fflags, CSR_FFLAGS)
+DECLARE_CSR(frm, CSR_FRM)
+DECLARE_CSR(fcsr, CSR_FCSR)
+DECLARE_CSR(cycle, CSR_CYCLE)
+DECLARE_CSR(time, CSR_TIME)
+DECLARE_CSR(instret, CSR_INSTRET)
+DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)
+DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)
+DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)
+DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)
+DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)
+DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)
+DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)
+DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)
+DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)
+DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)
+DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)
+DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)
+DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)
+DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)
+DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)
+DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)
+DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)
+DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)
+DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)
+DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)
+DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)
+DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)
+DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)
+DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)
+DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)
+DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
+DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
+DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
+DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
+DECLARE_CSR(sstatus, CSR_SSTATUS)
+DECLARE_CSR(sie, CSR_SIE)
+DECLARE_CSR(stvec, CSR_STVEC)
+DECLARE_CSR(sscratch, CSR_SSCRATCH)
+DECLARE_CSR(sepc, CSR_SEPC)
+DECLARE_CSR(scause, CSR_SCAUSE)
+DECLARE_CSR(sbadaddr, CSR_SBADADDR)
+DECLARE_CSR(sip, CSR_SIP)
+DECLARE_CSR(sptbr, CSR_SPTBR)
+DECLARE_CSR(mstatus, CSR_MSTATUS)
+DECLARE_CSR(misa, CSR_MISA)
+DECLARE_CSR(medeleg, CSR_MEDELEG)
+DECLARE_CSR(mideleg, CSR_MIDELEG)
+DECLARE_CSR(mie, CSR_MIE)
+DECLARE_CSR(mtvec, CSR_MTVEC)
+DECLARE_CSR(mscratch, CSR_MSCRATCH)
+DECLARE_CSR(mepc, CSR_MEPC)
+DECLARE_CSR(mcause, CSR_MCAUSE)
+DECLARE_CSR(mbadaddr, CSR_MBADADDR)
+DECLARE_CSR(mip, CSR_MIP)
+DECLARE_CSR(tselect, CSR_TSELECT)
+DECLARE_CSR(tdata1, CSR_TDATA1)
+DECLARE_CSR(tdata2, CSR_TDATA2)
+DECLARE_CSR(tdata3, CSR_TDATA3)
+DECLARE_CSR(dcsr, CSR_DCSR)
+DECLARE_CSR(dpc, CSR_DPC)
+DECLARE_CSR(dscratch, CSR_DSCRATCH)
+DECLARE_CSR(mcycle, CSR_MCYCLE)
+DECLARE_CSR(minstret, CSR_MINSTRET)
+DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
+DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)
+DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)
+DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)
+DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)
+DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)
+DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)
+DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)
+DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)
+DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)
+DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)
+DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)
+DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)
+DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)
+DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)
+DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)
+DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)
+DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)
+DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)
+DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)
+DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)
+DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)
+DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)
+DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)
+DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)
+DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
+DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
+DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
+DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
+DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
+DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
+DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
+DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
+DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
+DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
+DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
+DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
+DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
+DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
+DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
+DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
+DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
+DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
+DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
+DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
+DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
+DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
+DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
+DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
+DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
+DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
+DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
+DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
+DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
+DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
+DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
+DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
+DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
+DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
+DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
+DECLARE_CSR(mvendorid, CSR_MVENDORID)
+DECLARE_CSR(marchid, CSR_MARCHID)
+DECLARE_CSR(mimpid, CSR_MIMPID)
+DECLARE_CSR(mhartid, CSR_MHARTID)
+DECLARE_CSR(cycleh, CSR_CYCLEH)
+DECLARE_CSR(timeh, CSR_TIMEH)
+DECLARE_CSR(instreth, CSR_INSTRETH)
+DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
+DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
+DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
+DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
+DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
+DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
+DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
+DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
+DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
+DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
+DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
+DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
+DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
+DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
+DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
+DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
+DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
+DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
+DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
+DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
+DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
+DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
+DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
+DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
+DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
+DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
+DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
+DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
+DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
+DECLARE_CSR(mcycleh, CSR_MCYCLEH)
+DECLARE_CSR(minstreth, CSR_MINSTRETH)
+DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
+DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)
+DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)
+DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)
+DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)
+DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)
+DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)
+DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)
+DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)
+DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)
+DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)
+DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)
+DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)
+DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)
+DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)
+DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)
+DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)
+DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)
+DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)
+DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)
+DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)
+DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)
+DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)
+DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)
+DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)
+DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
+DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
+DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
+DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
+#endif
+#ifdef DECLARE_CAUSE
+DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
+DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)
+DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
+DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
+DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
+DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)
+DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
+DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)
+DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
+DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
+DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
+DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
+#endif
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/GCC/entry.S b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/GCC/entry.S
new file mode 100644
index 00000000..0e102199
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/GCC/entry.S
@@ -0,0 +1,131 @@
+/* Copyright 2018 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+#include "risc-v/Core/Include/riscv_encoding.h"
+
+/* This code executes before _start, which is contained inside the C library.
+ * In embedded systems we want to ensure that _enter, which contains the first
+ * code to be executed, can be loaded at a specific address.  To enable this
+ * feature we provide the '.text.metal.init.enter' section, which is
+ * defined to have the first address being where execution should start. */
+.section .text.metal.init.enter
+.global _enter
+_enter:
+    .cfi_startproc
+
+    /* Inform the debugger that there is nowhere to backtrace past _enter. */
+    .cfi_undefined ra
+
+    /* The absolute first thing that must happen is configuring the global
+     * pointer register, which must be done with relaxation disabled because
+     * it's not valid to obtain the address of any symbol without GP
+     * configured.  The C environment might go ahead and do this again, but
+     * that's safe as it's a fixed register. */
+.option push
+.option norelax
+    la gp, __global_pointer$
+.option pop
+
+    /* Disable global interrupt */
+    /*clear_csr(mstatus, MSTATUS_MIE);*/
+    csrci mstatus,8
+
+    /* Set up a simple trap vector to catch anything that goes wrong early in
+     * the boot process. */
+    la t0, Trap_Handler_Stub
+    /* enable CLIC Vectored mode */
+    ori	t0,t0,3
+    csrw mtvec, t0
+    /* enable chicken bit if core is bullet series*/
+    la t0, __metal_chicken_bit
+    beqz t0, 1f
+    csrwi 0x7C1, 0
+1:
+
+    /* There may be pre-initialization routines inside the MBI code that run in
+     * C, so here we set up a C environment.  First we set up a stack pointer,
+     * which is left as a weak reference in order to allow initialization
+     * routines that do not need a stack to be set up to transparently be
+     * called. */
+    .weak __StackTop
+    la sp, __StackTop
+
+    /* Intial the mtvt, MUST BE 64 bytes aligned*/
+    .weak __Vectors
+    la t0, __Vectors
+    // From drivers/bl702_driver/risc-v/Core/Include/riscv_encoding.h
+    csrw CSR_MTVT, t0
+
+#ifdef __riscv_float_abi_single
+    /* deal with FP */
+    /* Is F extension present? */
+    csrr t0, misa
+    andi t0, t0, (1 << ('F' - 'A'))
+    beqz t0, 1f
+    /* If so, enable it */
+    li t0, MSTATUS_FS
+    csrs mstatus, t0
+    fssr x0
+1:
+#endif
+
+    /* Check for an initialization routine and call it if one exists, otherwise
+     * just skip over the call entirely.   Note that __metal_initialize isn't
+     * actually a full C function, as it doesn't end up with the .bss or .data
+     * segments having been initialized.  This is done to avoid putting a
+     * burden on systems that can be initialized without having a C environment
+     * set up. */
+    call SystemInit
+
+    /* start load code to itcm like. */
+    call start_load
+    // Register at exit cleanup (not required for embedded)
+    // la a0, __libc_fini_array
+    // call atexit
+    /* Call C/C++ constructor start up code */
+    call __libc_init_array
+
+
+    jal System_Post_Init
+
+    /* At this point we can enter the C runtime's startup file.  The arguments
+     * to this function are designed to match those provided to the SEE, just
+     * so we don't have to write another ABI. */
+    
+    //Sets argv,argc to 0/null
+    csrr a0, mhartid
+    li a1, 0
+    li a2, 0
+    call main
+
+    csrci mstatus, (1 << 3)
+
+__exit:
+    j __exit
+
+    .cfi_endproc
+
+/* For sanity's sake we set up an early trap vector that just does nothing.  If
+ * you end up here then there's a bug in the early boot code somewhere. */
+.weak Trap_Handler_Stub
+.section .text.metal.init.trapvec
+.align 2
+Trap_Handler_Stub:
+    .cfi_startproc
+    csrr t0, mcause
+    csrr t1, mepc
+    csrr t2, mtval
+    j Trap_Handler_Stub
+    .cfi_endproc
+
+/* The GCC port might not emit a __register_frame_info symbol, which eventually
+ * results in a weak undefined reference that eventually causes crash when it
+ * is dereference early in boot.  We really shouldn't need to put this here,
+ * but to deal with what I think is probably a bug in the linker script I'm
+ * going to leave this in for now.  At least it's fairly cheap :) */
+.weak __register_frame_info
+.global __register_frame_info
+.section .text.metal.init.__register_frame_info
+__register_frame_info:
+    .cfi_startproc
+    ret
+    .cfi_endproc
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/GCC/start_load.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/GCC/start_load.c
new file mode 100644
index 00000000..eec6d9f5
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/GCC/start_load.c
@@ -0,0 +1,114 @@
+/**
+ * @file start_load.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+
+#include "bl702.h"
+#include 
+
+#define __STARTUP_CLEAR_BSS 1
+
+/*----------------------------------------------------------------------------
+  Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t __itcm_load_addr;
+extern uint32_t __dtcm_load_addr;
+extern uint32_t __system_ram_load_addr;
+extern uint32_t __ram_load_addr;
+
+extern uint32_t __text_code_start__;
+extern uint32_t __text_code_end__;
+extern uint32_t __tcm_code_start__;
+extern uint32_t __tcm_code_end__;
+extern uint32_t __tcm_data_start__;
+extern uint32_t __tcm_data_end__;
+extern uint32_t __system_ram_data_start__;
+extern uint32_t __system_ram_data_end__;
+extern uint32_t __ram_data_start__;
+extern uint32_t __ram_data_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __noinit_data_start__;
+extern uint32_t __noinit_data_end__;
+
+extern uint32_t __StackTop;
+extern uint32_t __StackLimit;
+extern uint32_t __HeapBase;
+extern uint32_t __HeapLimit;
+
+// extern uint32_t __copy_table_start__;
+// extern uint32_t __copy_table_end__;
+// extern uint32_t __zero_table_start__;
+// extern uint32_t __zero_table_end__;
+
+void start_load(void) {
+  uint32_t *pSrc, *pDest;
+  uint32_t *pTable __attribute__((unused));
+
+  /* Copy ITCM code */
+  pSrc  = &__itcm_load_addr;
+  pDest = &__tcm_code_start__;
+
+  for (; pDest < &__tcm_code_end__;) {
+    *pDest++ = *pSrc++;
+  }
+
+  /* Copy DTCM code */
+  pSrc  = &__dtcm_load_addr;
+  pDest = &__tcm_data_start__;
+
+  for (; pDest < &__tcm_data_end__;) {
+    *pDest++ = *pSrc++;
+  }
+
+  /* BF Add system RAM data copy */
+  pSrc  = &__system_ram_load_addr;
+  pDest = &__system_ram_data_start__;
+
+  for (; pDest < &__system_ram_data_end__;) {
+    *pDest++ = *pSrc++;
+  }
+
+  /* BF Add OCARAM data copy */
+  pSrc  = &__ram_load_addr;
+  pDest = &__ram_data_start__;
+
+  for (; pDest < &__ram_data_end__;) {
+    *pDest++ = *pSrc++;
+  }
+
+  // #ifdef __STARTUP_CLEAR_BSS
+  /*  Single BSS section scheme.
+   *
+   *  The BSS section is specified by following symbols
+   *    __bss_start__: start of the BSS section.
+   *    __bss_end__: end of the BSS section.
+   *
+   *  Both addresses must be aligned to 4 bytes boundary.
+   */
+  pDest = &__bss_start__;
+
+  for (; pDest < &__bss_end__;) {
+    *pDest++ = 0ul;
+  }
+
+  // #endif
+}
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/interrupt.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/interrupt.c
new file mode 100644
index 00000000..e23b18d2
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/interrupt.c
@@ -0,0 +1,368 @@
+/**
+ * @file interrupt.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "bl702_common.h"
+#include "bflb_platform.h"
+#include "risc-v/Core/Include/clic.h"
+#include "risc-v/Core/Include/riscv_encoding.h"
+
+pFunc __Interrupt_Handlers[IRQn_LAST] = { 0 };
+
+void Interrupt_Handler_Stub(void);
+
+void clic_msip_handler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void clic_mtimer_handler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void clic_mext_handler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void clic_csoft_handler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void BMX_TO_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void L1C_BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void L1C_BMX_TO_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void SEC_BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void RF_TOP_INT0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void RF_TOP_INT1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void DMA_BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void SEC_GMAC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void SEC_CDET_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void SEC_PKA_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void SEC_TRNG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void SEC_AES_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void SEC_SHA_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void DMA_ALL_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void MJPEG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void CAM_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void I2S_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void IRTX_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void IRRX_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void USB_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void EMAC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void SF_CTRL_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void GPADC_DMA_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void EFUSE_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void SPI_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void UART0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void UART1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void I2C_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void PWM_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void TIMER_CH0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void TIMER_CH1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void TIMER_WDT_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void KYS_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void QDEC0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void QDEC1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void QDEC2_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void GPIO_INT0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void TOUCH_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void M154_REQ_ENH_ACK_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void M154_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void M154_AES_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void PDS_WAKEUP_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void HBN_OUT0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void HBN_OUT1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void BOR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void WIFI_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void BZ_PHY_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void BLE_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void MAC_TXRX_TIMER_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void MAC_TXRX_MISC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void MAC_RX_TRG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void MAC_TX_TRG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void MAC_GEN_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void MAC_PORT_TRG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+void WIFI_IPC_PUBLIC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
+
+const pFunc __Vectors[] __attribute__((section(".init"), aligned(64))) = {
+    0,                                   /*         */
+    0,                                   /*         */
+    0,                                   /*         */
+    clic_msip_handler_Wrapper,           /* 3       */
+    0,                                   /*         */
+    0,                                   /*         */
+    0,                                   /*         */
+    clic_mtimer_handler_Wrapper,         /* 7       */
+    (pFunc)0x00000001,                   /*         */
+    0,                                   /*         */
+    (pFunc)0x00000102, /*         */     //disable log as default
+    clic_mext_handler_Wrapper,           /* 11      */
+    clic_csoft_handler_Wrapper,          /* 12      */
+    0,                                   /*         */
+    0,                                   /*         */
+    0,                                   /*         */
+    BMX_ERR_IRQHandler_Wrapper,          /* 16 +  0 */
+    BMX_TO_IRQHandler_Wrapper,           /* 16 +  1 */
+    L1C_BMX_ERR_IRQHandler_Wrapper,      /* 16 +  2 */
+    L1C_BMX_TO_IRQHandler_Wrapper,       /* 16 +  3 */
+    SEC_BMX_ERR_IRQHandler_Wrapper,      /* 16 +  4 */
+    RF_TOP_INT0_IRQHandler_Wrapper,      /* 16 +  5 */
+    RF_TOP_INT1_IRQHandler_Wrapper,      /* 16 +  6 */
+    0,                                   /* 16 +  7 */
+    DMA_BMX_ERR_IRQHandler_Wrapper,      /* 16 +  8 */
+    SEC_GMAC_IRQHandler_Wrapper,         /* 16 +  9 */
+    SEC_CDET_IRQHandler_Wrapper,         /* 16 + 10 */
+    SEC_PKA_IRQHandler_Wrapper,          /* 16 + 11 */
+    SEC_TRNG_IRQHandler_Wrapper,         /* 16 + 12 */
+    SEC_AES_IRQHandler_Wrapper,          /* 16 + 13 */
+    SEC_SHA_IRQHandler_Wrapper,          /* 16 + 14 */
+    DMA_ALL_IRQHandler_Wrapper,          /* 16 + 15 */
+    MJPEG_IRQHandler_Wrapper,            /* 16 + 16 */
+    CAM_IRQHandler_Wrapper,              /* 16 + 17 */
+    I2S_IRQHandler_Wrapper,              /* 16 + 18 */
+    IRTX_IRQHandler_Wrapper,             /* 16 + 19 */
+    IRRX_IRQHandler_Wrapper,             /* 16 + 20 */
+    USB_IRQHandler_Wrapper,              /* 16 + 21 */
+    EMAC_IRQHandler_Wrapper,             /* 16 + 22 */
+    SF_CTRL_IRQHandler_Wrapper,          /* 16 + 23 */
+    0,                                   /* 16 + 24 */
+    GPADC_DMA_IRQHandler_Wrapper,        /* 16 + 25 */
+    EFUSE_IRQHandler_Wrapper,            /* 16 + 26 */
+    SPI_IRQHandler_Wrapper,              /* 16 + 27 */
+    0,                                   /* 16 + 28 */
+    UART0_IRQHandler_Wrapper,            /* 16 + 29 */
+    UART1_IRQHandler_Wrapper,            /* 16 + 30 */
+    0,                                   /* 16 + 31 */
+    I2C_IRQHandler_Wrapper,              /* 16 + 32 */
+    0,                                   /* 16 + 33 */
+    PWM_IRQHandler_Wrapper,              /* 16 + 34 */
+    0,                                   /* 16 + 35 */
+    TIMER_CH0_IRQHandler_Wrapper,        /* 16 + 36 */
+    TIMER_CH1_IRQHandler_Wrapper,        /* 16 + 37 */
+    TIMER_WDT_IRQHandler_Wrapper,        /* 16 + 38 */
+    KYS_IRQHandler_Wrapper,              /* 16 + 39 */
+    QDEC0_IRQHandler_Wrapper,            /* 16 + 40 */
+    QDEC1_IRQHandler_Wrapper,            /* 16 + 41 */
+    QDEC2_IRQHandler_Wrapper,            /* 16 + 42 */
+    0,                                   /* 16 + 43 */
+    GPIO_INT0_IRQHandler_Wrapper,        /* 16 + 44 */
+    TOUCH_IRQHandler_Wrapper,            /* 16 + 45 */
+    0,                                   /* 16 + 46 */
+    M154_REQ_ENH_ACK_IRQHandler_Wrapper, /* 16 + 47 */
+    M154_IRQHandler_Wrapper,             /* 16 + 48 */
+    M154_AES_IRQHandler_Wrapper,         /* 16 + 49 */
+    PDS_WAKEUP_IRQHandler_Wrapper,       /* 16 + 50 */
+    HBN_OUT0_IRQHandler_Wrapper,         /* 16 + 51 */
+    HBN_OUT1_IRQHandler_Wrapper,         /* 16 + 52 */
+    BOR_IRQHandler_Wrapper,              /* 16 + 53 */
+    WIFI_IRQHandler_Wrapper,             /* 16 + 54 */
+    BZ_PHY_IRQHandler_Wrapper,           /* 16 + 55 */
+    BLE_IRQHandler_Wrapper,              /* 16 + 56 */
+    MAC_TXRX_TIMER_IRQHandler_Wrapper,   /* 16 + 57 */
+    MAC_TXRX_MISC_IRQHandler_Wrapper,    /* 16 + 58 */
+    MAC_RX_TRG_IRQHandler_Wrapper,       /* 16 + 59 */
+    MAC_TX_TRG_IRQHandler_Wrapper,       /* 16 + 60 */
+    MAC_GEN_IRQHandler_Wrapper,          /* 16 + 61 */
+    MAC_PORT_TRG_IRQHandler_Wrapper,     /* 16 + 62 */
+    WIFI_IPC_PUBLIC_IRQHandler_Wrapper,  /* 16 + 63 */
+};
+
+void Trap_Handler(void)
+{
+    unsigned long cause;
+    unsigned long epc;
+    unsigned long tval;
+    uint8_t isecall = 0;
+
+    MSG("Trap_Handler\r\n");
+
+    cause = read_csr(mcause);
+    MSG("mcause=%08x\r\n", (uint32_t)cause);
+    epc = read_csr(mepc);
+    MSG("mepc:%08x\r\n", (uint32_t)epc);
+    tval = read_csr(mtval);
+    MSG("mtval:%08x\r\n", (uint32_t)tval);
+
+    cause = (cause & 0x3ff);
+
+    switch (cause) {
+        case 1:
+            MSG("Instruction access fault\r\n");
+            break;
+
+        case 2:
+            MSG("Illegal instruction\r\n");
+            break;
+
+        case 3:
+            MSG("Breakpoint\r\n");
+            break;
+
+        case 4:
+            MSG("Load address misaligned\r\n");
+            break;
+
+        case 5:
+            MSG("Load access fault\r\n");
+            break;
+
+        case 6:
+            MSG("Store/AMO address misaligned\r\n");
+            break;
+
+        case 7:
+            MSG("Store/AMO access fault\r\n");
+            break;
+
+        case 8:
+            MSG("Environment call from U-mode\r\n");
+            epc += 4;
+            write_csr(mepc, epc);
+            break;
+
+        case 11:
+            MSG("Environment call from M-mode\r\n");
+            epc += 4;
+            write_csr(mepc, epc);
+            isecall = 1;
+            break;
+
+        default:
+            MSG("Cause num=%d\r\n", (uint32_t)cause);
+            epc += 4;
+            write_csr(mepc, epc);
+            break;
+    }
+
+    if (!isecall) {
+        while (1)
+            ;
+    }
+}
+
+void Interrupt_Handler(void)
+{
+    pFunc interruptFun;
+    uint32_t num = 0;
+    volatile uint32_t ulMEPC = 0UL, ulMCAUSE = 0UL;
+
+    /* Store a few register values that might be useful when determining why this
+    function was called. */
+    __asm volatile("csrr %0, mepc"
+                   : "=r"(ulMEPC));
+    __asm volatile("csrr %0, mcause"
+                   : "=r"(ulMCAUSE));
+
+    if ((ulMCAUSE & 0x80000000) == 0) {
+        /*Exception*/
+        MSG("Exception should not be here\r\n");
+    } else {
+        num = ulMCAUSE & 0x3FF;
+
+        if (num < IRQn_LAST) {
+            interruptFun = __Interrupt_Handlers[num];
+
+            if (NULL != interruptFun) {
+                interruptFun();
+            } else {
+                MSG("Interrupt num:%d IRQHandler not installed\r\n", (unsigned int)num);
+
+                if (num >= IRQ_NUM_BASE) {
+                    MSG("Peripheral Interrupt num:%d \r\n", (unsigned int)num - IRQ_NUM_BASE);
+                }
+
+                while (1)
+                    ;
+            }
+        } else {
+            MSG("Unexpected interrupt num:%d\r\n", (unsigned int)num);
+        }
+    }
+}
+
+void handle_trap(void)
+{
+#define MCAUSE_INT_MASK  0x80000000 // [31]=1 interrupt, else exception
+#define MCAUSE_CODE_MASK 0x7FFFFFFF // low bits show code
+
+    unsigned long mcause_value = read_csr(mcause);
+    if (mcause_value & MCAUSE_INT_MASK) {
+        // Branch to interrupt handler here
+        Interrupt_Handler();
+    } else {
+        // Branch to exception handle
+        Trap_Handler();
+    }
+}
+
+void __IRQ_ALIGN64 Trap_Handler_Stub(void)
+{
+    Trap_Handler();
+}
+
+void __IRQ Interrupt_Handler_Stub(void)
+{
+    Interrupt_Handler();
+}
+
+void FreeRTOS_Interrupt_Handler(void)
+{
+    Interrupt_Handler();
+}
+
+void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun)
+{
+    if (irq < IRQn_LAST) {
+        __Interrupt_Handlers[irq] = interruptFun;
+    }
+}
+
+void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+}
+
+void clic_enable_interrupt(uint32_t source)
+{
+    *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 1;
+}
+
+void clic_disable_interrupt(uint32_t source)
+{
+    *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 0;
+}
+
+void clic_clear_pending(uint32_t source)
+{
+    *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 0;
+}
+
+void clic_set_pending(uint32_t source)
+{
+    *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 1;
+}
+
+void clic_set_intcfg(uint32_t source, uint32_t intcfg)
+{
+    *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTCFG + source) = intcfg;
+}
+
+uint8_t clic_get_intcfg(uint32_t source)
+{
+    return *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTCFG + source);
+}
+
+void clic_set_cliccfg(uint32_t cfg)
+{
+    *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_CFG) = cfg;
+}
+
+uint8_t clic_get_cliccfg(void)
+{
+    return *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_CFG);
+}
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/system_bl702.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/system_bl702.c
new file mode 100644
index 00000000..49acc266
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/system_bl702.c
@@ -0,0 +1,139 @@
+/**
+ * @file system_bl702.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "bl702.h"
+#include "bl702_glb.h"
+#include "bl702_hbn.h"
+#include "risc-v/Core/Include/clic.h"
+
+#ifdef BFLB_EFLASH_LOADER
+#include "bl702_usb.h"
+void USB_DoNothing_IRQHandler(void) {
+  /* clear all USB int sts */
+  USB_Clr_IntStatus(32);
+}
+#endif
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define SYSTEM_CLOCK (32000000UL)
+
+/*----------------------------------------------------------------------------
+  Vector Table
+ *----------------------------------------------------------------------------*/
+#define VECT_TAB_OFFSET                     \
+  0x00 /*!< Vector Table base offset field. \
+             This value must be a multiple of 0x200. */
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+
+void system_bor_init(void) {
+  HBN_BOR_CFG_Type borCfg = {0 /* pu_bor */, 0 /* irq_bor_en */, 1 /* bor_vth */, 0 /* bor_sel */};
+  HBN_Set_BOR_Cfg(&borCfg);
+}
+
+void SystemInit(void) {
+  uint32_t *p;
+  uint32_t  i               = 0;
+  uint32_t  tmpVal          = 0;
+  uint8_t   flashCfg        = 0;
+  uint8_t   psramCfg        = 0;
+  uint8_t   isInternalFlash = 0;
+  uint8_t   isInternalPsram = 0;
+
+  /* global IRQ disable */
+  __disable_irq();
+
+  tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+  tmpVal |= (1 << 8);      /*mask pds wakeup*/
+  tmpVal |= (1 << 10);     /*mask rf done*/
+  tmpVal |= (1 << 11);     /*mask pll done*/
+  tmpVal &= ~(0xff << 16); /*mask all pds wakeup source int*/
+  BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+  /* GLB_Set_EM_Sel(GLB_EM_0KB); */
+  tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, GLB_EM_0KB);
+  BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal);
+
+  /* Restore default setting*/
+  /* GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); */
+  tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, UART_SIG_SWAP_NONE);
+  BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+  /* fix 57.6M */
+  if (SystemCoreClockGet() == 57 * 6000 * 1000) {
+    SystemCoreClockSet(57.6 * 1000 * 1000)
+  }
+
+  /* CLear all interrupt */
+  p = (uint32_t *)(CLIC_HART0_ADDR + CLIC_INTIE);
+
+  for (i = 0; i < (IRQn_LAST + 3) / 4; i++) {
+    p[i] = 0;
+  }
+
+  p = (uint32_t *)(CLIC_HART0_ADDR + CLIC_INTIP);
+
+  for (i = 0; i < (IRQn_LAST + 3) / 4; i++) {
+    p[i] = 0;
+  }
+
+  /* SF io select from efuse value */
+  tmpVal   = BL_RD_WORD(0x40007074);
+  flashCfg = ((tmpVal >> 26) & 7);
+  psramCfg = ((tmpVal >> 24) & 3);
+  if (flashCfg == 1 || flashCfg == 2) {
+    isInternalFlash = 1;
+  } else {
+    isInternalFlash = 0;
+  }
+  if (psramCfg == 1) {
+    isInternalPsram = 1;
+  } else {
+    isInternalPsram = 0;
+  }
+  tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO);
+  if (isInternalFlash == 1 && isInternalPsram == 0) {
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x3f);
+  } else {
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x00);
+  }
+  BL_WR_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO, tmpVal);
+
+#ifdef BFLB_EFLASH_LOADER
+  Interrupt_Handler_Register(USB_IRQn, USB_DoNothing_IRQHandler);
+#endif
+  /* init for for all platform */
+  system_bor_init();
+  /* global IRQ enable */
+  __enable_irq();
+}
+
+void System_Post_Init(void) {
+  PDS_Trim_RC32M();
+  HBN_Trim_RC32K();
+}
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/system_bl702.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/system_bl702.h
new file mode 100644
index 00000000..138bc5b9
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/system_bl702.h
@@ -0,0 +1,45 @@
+/**
+ * @file system_bl702.h
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+
+#ifndef __SYSTEM_BL702_H__
+#define __SYSTEM_BL702_H__
+
+/**
+ *  @brief PLL Clock type definition
+ */
+
+extern uint32_t SystemCoreClock;
+typedef void (*pFunc)(void);
+
+#define CPU_Interrupt_Enable        clic_enable_interrupt
+#define CPU_Interrupt_Disable       clic_disable_interrupt
+#define CPU_Interrupt_Pending_Clear clic_clear_pending
+
+extern void SystemCoreClockUpdate(void);
+extern void SystemInit(void);
+void clic_enable_interrupt(uint32_t source);
+void clic_disable_interrupt(uint32_t source);
+void clic_clear_pending(uint32_t source);
+void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun);
+void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+#endif
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_acomp.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_acomp.h
new file mode 100644
index 00000000..7cd0b43b
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_acomp.h
@@ -0,0 +1,213 @@
+/**
+  ******************************************************************************
+  * @file    bl702_acomp.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_ACOMP_H__
+#define __BL702_ACOMP_H__
+
+#include "aon_reg.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  ACOMP
+ *  @{
+ */
+
+/** @defgroup  ACOMP_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief Analog compare id type definition
+ */
+typedef enum {
+    AON_ACOMP0_ID, /*!< Analog compare 0 */
+    AON_ACOMP1_ID, /*!< Analog compare 1 */
+} AON_ACOMP_ID_Type;
+
+/**
+ *  @brief Analog compare level type definition
+ */
+typedef enum {
+    AON_ACOMP_LEVEL_FACTOR_0P25, /*!< Analog compare level scaling factor 0.25 */
+    AON_ACOMP_LEVEL_FACTOR_0P5,  /*!< Analog compare level scaling factor 0.5 */
+    AON_ACOMP_LEVEL_FACTOR_0P75, /*!< Analog compare level scaling factor 0.75 */
+    AON_ACOMP_LEVEL_FACTOR_1,    /*!< Analog compare level scaling factor 1 */
+} AON_ACOMP_Level_Factor_Type;
+
+/**
+ *  @brief Analog compare channel type definition
+ */
+typedef enum {
+    AON_ACOMP_CHAN_ADC0,              /*!< Analog compare channel,ADC input channel 0 */
+    AON_ACOMP_CHAN_ADC1,              /*!< Analog compare channel,ADC input channel 1 */
+    AON_ACOMP_CHAN_ADC2,              /*!< Analog compare channel,ADC input channel 2 */
+    AON_ACOMP_CHAN_ADC3,              /*!< Analog compare channel,ADC input channel 3 */
+    AON_ACOMP_CHAN_ADC4,              /*!< Analog compare channel,ADC input channel 4 */
+    AON_ACOMP_CHAN_ADC5,              /*!< Analog compare channel,ADC input channel 5 */
+    AON_ACOMP_CHAN_ADC6,              /*!< Analog compare channel,ADC input channel 6 */
+    AON_ACOMP_CHAN_ADC7,              /*!< Analog compare channel,ADC input channel 7 */
+    AON_ACOMP_CHAN_DACA,              /*!< Analog compare channel,DAC output channel A */
+    AON_ACOMP_CHAN_DACB,              /*!< Analog compare channel,DAC output channel B */
+    AON_ACOMP_CHAN_VREF_1P2V,         /*!< Analog compare channel,1.2V ref voltage */
+    AON_ACOMP_CHAN_0P375VBAT_NOT_IMP, /*!< Analog compare channel,6/16Vbat */
+    AON_ACOMP_CHAN_0P25VBAT,          /*!< Analog compare channel,4/16Vbat */
+    AON_ACOMP_CHAN_0P1875VBAT,        /*!< Analog compare channel,3/16Vbat */
+    AON_ACOMP_CHAN_0P3125VBAT,        /*!< Analog compare channel,5/16Vbat */
+    AON_ACOMP_CHAN_VSS,               /*!< Analog compare channel,vss */
+} AON_ACOMP_Chan_Type;
+
+/**
+ *  @brief Analog compare bias current control type definition
+ */
+typedef enum {
+    AON_ACOMP_BIAS_POWER_MODE1, /*!< Analog compare power mode 1,slow response mode */
+    AON_ACOMP_BIAS_POWER_MODE2, /*!< Analog compare power mode 2,medium response mode */
+    AON_ACOMP_BIAS_POWER_MODE3, /*!< Analog compare power mode 3,fast response mode */
+    AON_ACOMP_BIAS_POWER_NONE,  /*!< Analog compare power mode none */
+} AON_ACOMP_Bias_Prog_Type;
+
+/**
+ *  @brief Analog compare hysteresis voltage type definition
+ */
+typedef enum {
+    AON_ACOMP_HYSTERESIS_VOLT_NONE, /*!< Analog compare hysteresis voltage none */
+    AON_ACOMP_HYSTERESIS_VOLT_10MV, /*!< Analog compare hysteresis voltage 10mv */
+    AON_ACOMP_HYSTERESIS_VOLT_20MV, /*!< Analog compare hysteresis voltage 20mv */
+    AON_ACOMP_HYSTERESIS_VOLT_30MV, /*!< Analog compare hysteresis voltage 30mv */
+    AON_ACOMP_HYSTERESIS_VOLT_40MV, /*!< Analog compare hysteresis voltage 40mv */
+    AON_ACOMP_HYSTERESIS_VOLT_50MV, /*!< Analog compare hysteresis voltage 50mv */
+    AON_ACOMP_HYSTERESIS_VOLT_60MV, /*!< Analog compare hysteresis voltage 60mv */
+    AON_ACOMP_HYSTERESIS_VOLT_70MV, /*!< Analog compare hysteresis voltage 70mv */
+} AON_ACOMP_Hysteresis_Volt_Type;
+
+/**
+ *  @brief AON ACOMP configuration type definition
+ */
+typedef struct
+{
+    BL_Fun_Type muxEn;                                /*!< ACOMP mux enable */
+    uint8_t posChanSel;                               /*!< ACOMP positive channel select */
+    uint8_t negChanSel;                               /*!< ACOMP negtive channel select */
+    AON_ACOMP_Level_Factor_Type levelFactor;          /*!< ACOMP level select factor */
+    AON_ACOMP_Bias_Prog_Type biasProg;                /*!< ACOMP bias current control */
+    AON_ACOMP_Hysteresis_Volt_Type hysteresisPosVolt; /*!< ACOMP hysteresis voltage for positive */
+    AON_ACOMP_Hysteresis_Volt_Type hysteresisNegVolt; /*!< ACOMP hysteresis voltage for negtive */
+} AON_ACOMP_CFG_Type;
+
+/*@} end of group ACOMP_Public_Types */
+
+/** @defgroup  ACOMP_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  AON_ACOMP_ID_TYPE
+ *  @{
+ */
+#define IS_AON_ACOMP_ID_TYPE(type) (((type) == AON_ACOMP0_ID) || \
+                                    ((type) == AON_ACOMP1_ID))
+
+/** @defgroup  AON_ACOMP_LEVEL_FACTOR_TYPE
+ *  @{
+ */
+#define IS_AON_ACOMP_LEVEL_FACTOR_TYPE(type) (((type) == AON_ACOMP_LEVEL_FACTOR_0P25) || \
+                                              ((type) == AON_ACOMP_LEVEL_FACTOR_0P5) ||  \
+                                              ((type) == AON_ACOMP_LEVEL_FACTOR_0P75) || \
+                                              ((type) == AON_ACOMP_LEVEL_FACTOR_1))
+
+/** @defgroup  AON_ACOMP_CHAN_TYPE
+ *  @{
+ */
+#define IS_AON_ACOMP_CHAN_TYPE(type) (((type) == AON_ACOMP_CHAN_ADC0) ||              \
+                                      ((type) == AON_ACOMP_CHAN_ADC1) ||              \
+                                      ((type) == AON_ACOMP_CHAN_ADC2) ||              \
+                                      ((type) == AON_ACOMP_CHAN_ADC3) ||              \
+                                      ((type) == AON_ACOMP_CHAN_ADC4) ||              \
+                                      ((type) == AON_ACOMP_CHAN_ADC5) ||              \
+                                      ((type) == AON_ACOMP_CHAN_ADC6) ||              \
+                                      ((type) == AON_ACOMP_CHAN_ADC7) ||              \
+                                      ((type) == AON_ACOMP_CHAN_DACA) ||              \
+                                      ((type) == AON_ACOMP_CHAN_DACB) ||              \
+                                      ((type) == AON_ACOMP_CHAN_VREF_1P2V) ||         \
+                                      ((type) == AON_ACOMP_CHAN_0P375VBAT_NOT_IMP) || \
+                                      ((type) == AON_ACOMP_CHAN_0P25VBAT) ||          \
+                                      ((type) == AON_ACOMP_CHAN_0P1875VBAT) ||        \
+                                      ((type) == AON_ACOMP_CHAN_0P3125VBAT) ||        \
+                                      ((type) == AON_ACOMP_CHAN_VSS))
+
+/** @defgroup  AON_ACOMP_BIAS_PROG_TYPE
+ *  @{
+ */
+#define IS_AON_ACOMP_BIAS_PROG_TYPE(type) (((type) == AON_ACOMP_BIAS_POWER_MODE1) || \
+                                           ((type) == AON_ACOMP_BIAS_POWER_MODE2) || \
+                                           ((type) == AON_ACOMP_BIAS_POWER_MODE3) || \
+                                           ((type) == AON_ACOMP_BIAS_POWER_NONE))
+
+/** @defgroup  AON_ACOMP_HYSTERESIS_VOLT_TYPE
+ *  @{
+ */
+#define IS_AON_ACOMP_HYSTERESIS_VOLT_TYPE(type) (((type) == AON_ACOMP_HYSTERESIS_VOLT_NONE) || \
+                                                 ((type) == AON_ACOMP_HYSTERESIS_VOLT_10MV) || \
+                                                 ((type) == AON_ACOMP_HYSTERESIS_VOLT_20MV) || \
+                                                 ((type) == AON_ACOMP_HYSTERESIS_VOLT_30MV) || \
+                                                 ((type) == AON_ACOMP_HYSTERESIS_VOLT_40MV) || \
+                                                 ((type) == AON_ACOMP_HYSTERESIS_VOLT_50MV) || \
+                                                 ((type) == AON_ACOMP_HYSTERESIS_VOLT_60MV) || \
+                                                 ((type) == AON_ACOMP_HYSTERESIS_VOLT_70MV))
+
+/*@} end of group ACOMP_Public_Constants */
+
+/** @defgroup  ACOMP_Public_Macros
+ *  @{
+ */
+
+/*@} end of group ACOMP_Public_Macros */
+
+/** @defgroup  ACOMP_Public_Functions
+ *  @{
+ */
+void AON_ACOMP_Init(AON_ACOMP_ID_Type acompNo, AON_ACOMP_CFG_Type *cfg);
+void AON_ACOMP_Enable(AON_ACOMP_ID_Type acompNo);
+BL_Sts_Type AON_ACOMP_Get_Result(AON_ACOMP_ID_Type acompNo);
+
+/*@} end of group ACOMP_Public_Functions */
+
+/*@} end of group ACOMP */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_ACOMP_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_adc.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_adc.h
new file mode 100644
index 00000000..8619541f
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_adc.h
@@ -0,0 +1,485 @@
+/**
+ ******************************************************************************
+ * @file    bl702_adc.h
+ * @version V1.0
+ * @date
+ * @brief   This file is the standard driver header file
+ ******************************************************************************
+ * @attention
+ *
+ * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __BL702_ADC_H__
+#define __BL702_ADC_H__
+
+#include "aon_reg.h"
+#include "bl702_common.h"
+#include "gpip_reg.h"
+
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  ADC
+ *  @{
+ */
+
+/** @defgroup  ADC_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief ADC channel type definition
+ */
+typedef enum {
+  ADC_CHAN0,          /*!< ADC channel 0 */
+  ADC_CHAN1,          /*!< ADC channel 1 */
+  ADC_CHAN2,          /*!< ADC channel 2 */
+  ADC_CHAN3,          /*!< ADC channel 3 */
+  ADC_CHAN4,          /*!< ADC channel 4 */
+  ADC_CHAN5,          /*!< ADC channel 5 */
+  ADC_CHAN6,          /*!< ADC channel 6 */
+  ADC_CHAN7,          /*!< ADC channel 7 */
+  ADC_CHAN8,          /*!< ADC channel 8 */
+  ADC_CHAN9,          /*!< ADC channel 9 */
+  ADC_CHAN10,         /*!< ADC channel 10 */
+  ADC_CHAN11,         /*!< ADC channel 11 */
+  ADC_CHAN_DAC_OUTA,  /*!< DACA, ADC channel 12 */
+  ADC_CHAN_DAC_OUTB,  /*!< DACB, ADC channel 13 */
+  ADC_CHAN_TSEN_P,    /*!< TSenp, ADC channel 14 */
+  ADC_CHAN_TSEN_N,    /*!< TSenn, ADC channel 15 */
+  ADC_CHAN_VREF,      /*!< Vref, ADC channel 16 */
+  ADC_CHAN_DCTEST,    /*!< DCTest, ADC channel 17 */
+  ADC_CHAN_VABT_HALF, /*!< VBAT/2, ADC channel 18 */
+  ADC_CHAN_SENP3,     /*!< SenVP3, ADC channel 19 */
+  ADC_CHAN_SENP2,     /*!< SenVP2, ADC channel 20 */
+  ADC_CHAN_SENP1,     /*!< SenVP1, ADC channel 21 */
+  ADC_CHAN_SENP0,     /*!< SenVP0, ADC channel 22 */
+  ADC_CHAN_GND,       /*!< GND, ADC channel 23 */
+} ADC_Chan_Type;
+
+/**
+ *  @brief ADC V18 selection type definition
+ */
+typedef enum {
+  ADC_V18_SEL_1P62V, /*!< V18 select 1.62V */
+  ADC_V18_SEL_1P72V, /*!< V18 select 1.72V */
+  ADC_V18_SEL_1P82V, /*!< V18 select 1.82V */
+  ADC_V18_SEL_1P92V, /*!< V18 select 1.92V */
+} ADC_V18_SEL_Type;
+
+/**
+ *  @brief ADC V11 selection type definition
+ */
+typedef enum {
+  ADC_V11_SEL_1P0V,  /*!< V11 select 1.0V */
+  ADC_V11_SEL_1P1V,  /*!< V11 select 1.1V */
+  ADC_V11_SEL_1P18V, /*!< V11 select 1.18V */
+  ADC_V11_SEL_1P26V, /*!< V11 select 1.26V */
+} ADC_V11_SEL_Type;
+
+/**
+ *  @brief ADC clock type definition
+ */
+typedef enum {
+  ADC_CLK_DIV_1,  /*!< ADC clock:on 32M clock is 32M */
+  ADC_CLK_DIV_4,  /*!< ADC clock:on 32M clock is 8M */
+  ADC_CLK_DIV_8,  /*!< ADC clock:on 32M clock is 4M */
+  ADC_CLK_DIV_12, /*!< ADC clock:on 32M clock is 2.666M */
+  ADC_CLK_DIV_16, /*!< ADC clock:on 32M clock is 2M */
+  ADC_CLK_DIV_20, /*!< ADC clock:on 32M clock is 1.6M */
+  ADC_CLK_DIV_24, /*!< ADC clock:on 32M clock is 1.333M */
+  ADC_CLK_DIV_32, /*!< ADC clock:on 32M clock is 1M */
+} ADC_CLK_Type;
+
+/**
+ *  @brief ADC conversion speed type definition
+ */
+typedef enum {
+  ADC_DELAY_SEL_0, /*!< Select delay 0 */
+  ADC_DELAY_SEL_1, /*!< Select delay 1 */
+  ADC_DELAY_SEL_2, /*!< Select delay 2 */
+  ADC_DELAY_SEL_3, /*!< Select delay 3 */
+  ADC_DELAY_SEL_4, /*!< Select delay 4, not recommend */
+  ADC_DELAY_SEL_5, /*!< Select delay 5, not recommend */
+  ADC_DELAY_SEL_6, /*!< Select delay 6, not recommend */
+  ADC_DELAY_SEL_7, /*!< Select delay 7, not recommend */
+} ADC_DELAY_SEL_Type;
+
+/**
+ *  @brief ADC PGA gain type definition
+ */
+typedef enum {
+  ADC_PGA_GAIN_NONE, /*!< No PGA gain */
+  ADC_PGA_GAIN_1,    /*!< PGA gain 1 */
+  ADC_PGA_GAIN_2,    /*!< PGA gain 2 */
+  ADC_PGA_GAIN_4,    /*!< PGA gain 4 */
+  ADC_PGA_GAIN_8,    /*!< PGA gain 8 */
+  ADC_PGA_GAIN_16,   /*!< PGA gain 16 */
+  ADC_PGA_GAIN_32,   /*!< PGA gain 32 */
+} ADC_PGA_GAIN_Type;
+
+/**
+ *  @brief ADC analog portion low power mode selection type definition
+ */
+typedef enum {
+  ADC_BIAS_SEL_MAIN_BANDGAP, /*!< ADC current from main bandgap */
+  ADC_BIAS_SEL_AON_BANDGAP,  /*!< ADC current from aon bandgap for HBN mode */
+} ADC_BIAS_SEL_Type;
+
+/**
+ *  @brief ADC chop mode type definition
+ */
+typedef enum {
+  ADC_CHOP_MOD_ALL_OFF,       /*!< all off */
+  ADC_CHOP_MOD_AZ_ON,         /*!< Vref AZ on */
+  ADC_CHOP_MOD_AZ_PGA_ON,     /*!< Vref AZ and PGA chop on */
+  ADC_CHOP_MOD_AZ_PGA_RPC_ON, /*!< Vref AZ and PGA chop+RPC on */
+} ADC_CHOP_MOD_Type;
+
+/**
+ *  @brief ADC audio PGA output common mode control type definition
+ */
+typedef enum {
+  ADC_PGA_VCM_1V,   /*!< ADC VCM=1V */
+  ADC_PGA_VCM_1P2V, /*!< ADC VCM=1.2V */
+  ADC_PGA_VCM_1P4V, /*!< ADC VCM=1.4V */
+  ADC_PGA_VCM_1P6V, /*!< ADC VCM=1.6V */
+} ADC_PGA_VCM_Type;
+
+/**
+ *  @brief ADC tsen diode mode type definition
+ */
+typedef enum {
+  ADC_TSEN_MOD_INTERNAL_DIODE, /*!< Internal diode mode */
+  ADC_TSEN_MOD_EXTERNAL_DIODE, /*!< External diode mode */
+} ADC_TSEN_MOD_Type;
+
+/**
+ *  @brief ADC voltage reference type definition
+ */
+typedef enum {
+  ADC_VREF_3P2V, /*!< ADC select 3.2V as reference voltage */
+  ADC_VREF_2P0V, /*!< ADC select 2V as reference voltage */
+} ADC_VREF_Type;
+
+/**
+ *  @brief ADC signal input type definition
+ */
+typedef enum {
+  ADC_INPUT_SINGLE_END, /*!< ADC signal is single end */
+  ADC_INPUT_DIFF,       /*!< ADC signal is differential */
+} ADC_SIG_INPUT_Type;
+
+/**
+ *  @brief ADC data width type definition
+ */
+typedef enum {
+  ADC_DATA_WIDTH_12,                  /*!< ADC 12 bits */
+  ADC_DATA_WIDTH_14_WITH_16_AVERAGE,  /*!< ADC 14 bits,and the value is average of 16 converts */
+  ADC_DATA_WIDTH_14_WITH_64_AVERAGE,  /*!< ADC 14 bits,and the value is average of 64 converts */
+  ADC_DATA_WIDTH_16_WITH_128_AVERAGE, /*!< ADC 16 bits,and the value is average of 128 converts */
+  ADC_DATA_WIDTH_16_WITH_256_AVERAGE, /*!< ADC 16 bits,and the value is average of 256 converts */
+} ADC_Data_Width_Type;
+
+/**
+ *  @brief ADC micboost 32db type definition
+ */
+typedef enum {
+  ADC_MICBOOST_DB_16DB, /*!< MIC boost 16db */
+  ADC_MICBOOST_DB_32DB, /*!< MIC boost 32db */
+} ADC_MICBOOST_DB_Type;
+
+/**
+ *  @brief ADC pga2 gain type definition
+ */
+typedef enum {
+  ADC_PGA2_GAIN_0DB,  /*!< MIC pga2 gain 0db */
+  ADC_PGA2_GAIN_6DB,  /*!< MIC pga2 gain 6db */
+  ADC_PGA2_GAIN_N6DB, /*!< MIC pga2 gain -6db */
+  ADC_PGA2_GAIN_12DB, /*!< MIC pga2 gain 12db */
+} ADC_PGA2_GAIN_Type;
+
+/**
+ *  @brief ADC mic mode type definition
+ */
+typedef enum {
+  ADC_MIC_MODE_SINGLE, /*!< MIC single mode */
+  ADC_MIC_MODE_DIFF,   /*!< MIC diff mode */
+} ADC_MIC_MODE_Type;
+
+/**
+ *  @brief ADC mic type definition
+ */
+typedef struct {
+  ADC_MICBOOST_DB_Type micboostDb;       /*!< MIC boost db */
+  ADC_PGA2_GAIN_Type   micPga2Gain;      /*!< MIC pga2 gain */
+  ADC_MIC_MODE_Type    mic1Mode;         /*!< MIC1 single or diff */
+  ADC_MIC_MODE_Type    mic2Mode;         /*!< MIC2 single or diff */
+  BL_Fun_Type          dwaEn;            /*!< Improve dynamic performance */
+  BL_Fun_Type          micboostBypassEn; /*!< MIC boost amp bypass enable or disable */
+  BL_Fun_Type          micPgaEn;         /*!< MIC pga enable or disable */
+  BL_Fun_Type          micBiasEn;        /*!< MIC bias enable or disable */
+} ADC_MIC_Type;
+
+/**
+ *  @brief ADC configuration type definition
+ */
+typedef struct {
+  ADC_V18_SEL_Type    v18Sel;         /*!< ADC 1.8V select */
+  ADC_V11_SEL_Type    v11Sel;         /*!< ADC 1.1V select */
+  ADC_CLK_Type        clkDiv;         /*!< Clock divider */
+  ADC_PGA_GAIN_Type   gain1;          /*!< PGA gain 1 */
+  ADC_PGA_GAIN_Type   gain2;          /*!< PGA gain 2 */
+  ADC_CHOP_MOD_Type   chopMode;       /*!< ADC chop mode select */
+  ADC_BIAS_SEL_Type   biasSel;        /*!< ADC current form main bandgap or aon bandgap */
+  ADC_PGA_VCM_Type    vcm;            /*!< ADC VCM value */
+  ADC_VREF_Type       vref;           /*!< ADC voltage reference */
+  ADC_SIG_INPUT_Type  inputMode;      /*!< ADC input signal type */
+  ADC_Data_Width_Type resWidth;       /*!< ADC resolution and oversample rate */
+  BL_Fun_Type         offsetCalibEn;  /*!< Offset calibration enable */
+  int16_t             offsetCalibVal; /*!< Offset calibration value */
+} ADC_CFG_Type;
+
+/**
+ *  @brief ADC configuration type definition
+ */
+typedef struct {
+  int8_t   posChan; /*!< Positive channel */
+  int8_t   negChan; /*!< Negative channel */
+  uint16_t value;   /*!< ADC value */
+  float    volt;    /*!< ADC voltage result */
+} ADC_Result_Type;
+
+/**
+ *  @brief ADC FIFO threshold type definition
+ */
+typedef enum {
+  ADC_FIFO_THRESHOLD_1,  /*!< ADC FIFO threshold is 1 */
+  ADC_FIFO_THRESHOLD_4,  /*!< ADC FIFO threshold is 4 */
+  ADC_FIFO_THRESHOLD_8,  /*!< ADC FIFO threshold is 8 */
+  ADC_FIFO_THRESHOLD_16, /*!< ADC FIFO threshold is 16 */
+} ADC_FIFO_Threshold_Type;
+
+/**
+ *  @brief ADC interrupt type definition
+ */
+typedef enum {
+  ADC_INT_POS_SATURATION, /*!< ADC positive channel saturation */
+  ADC_INT_NEG_SATURATION, /*!< ADC negative channel saturation */
+  ADC_INT_FIFO_UNDERRUN,  /*!< ADC FIFO underrun interrupt */
+  ADC_INT_FIFO_OVERRUN,   /*!< ADC FIFO overrun interrupt */
+  ADC_INT_ADC_READY,      /*!< ADC data ready interrupt */
+  ADC_INT_FIFO_READY,     /*!< ADC FIFO count upper to threhold interrupt */
+  ADC_INT_ALL,            /*!< ADC all the interrupt */
+} ADC_INT_Type;
+
+/**
+ *  @brief ADC FIFO configuration structure type definition
+ */
+typedef struct {
+  ADC_FIFO_Threshold_Type fifoThreshold; /*!< ADC FIFO threshold */
+  BL_Fun_Type             dmaEn;         /*!< ADC DMA enable */
+} ADC_FIFO_Cfg_Type;
+
+/**
+ *  @brief ADC REG GAIN CAL
+ */
+typedef struct {
+  BL_Fun_Type adcGainCoeffEnable; /*!< ADC_Gain_Coeff enable */
+  uint16_t    adcgainCoeffVal;    /*!< ADC_Gain_Coeff value */
+  float       coe;                /*!< ADC_Gain_Coeff result */
+} ADC_Gain_Coeff_Type;
+
+/*@} end of group ADC_Public_Types */
+
+/** @defgroup  ADC_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  ADC_CHAN_TYPE
+ *  @{
+ */
+#define IS_ADC_CHAN_TYPE(type)                                                                                                                                                                      \
+  (((type) == ADC_CHAN0) || ((type) == ADC_CHAN1) || ((type) == ADC_CHAN2) || ((type) == ADC_CHAN3) || ((type) == ADC_CHAN4) || ((type) == ADC_CHAN5) || ((type) == ADC_CHAN6)                      \
+   || ((type) == ADC_CHAN7) || ((type) == ADC_CHAN8) || ((type) == ADC_CHAN9) || ((type) == ADC_CHAN10) || ((type) == ADC_CHAN11) || ((type) == ADC_CHAN_DAC_OUTA) || ((type) == ADC_CHAN_DAC_OUTB) \
+   || ((type) == ADC_CHAN_TSEN_P) || ((type) == ADC_CHAN_TSEN_N) || ((type) == ADC_CHAN_VREF) || ((type) == ADC_CHAN_DCTEST) || ((type) == ADC_CHAN_VABT_HALF) || ((type) == ADC_CHAN_SENP3)        \
+   || ((type) == ADC_CHAN_SENP2) || ((type) == ADC_CHAN_SENP1) || ((type) == ADC_CHAN_SENP0) || ((type) == ADC_CHAN_GND))
+
+/** @defgroup  ADC_V18_SEL_TYPE
+ *  @{
+ */
+#define IS_ADC_V18_SEL_TYPE(type) (((type) == ADC_V18_SEL_1P62V) || ((type) == ADC_V18_SEL_1P72V) || ((type) == ADC_V18_SEL_1P82V) || ((type) == ADC_V18_SEL_1P92V))
+
+/** @defgroup  ADC_V11_SEL_TYPE
+ *  @{
+ */
+#define IS_ADC_V11_SEL_TYPE(type) (((type) == ADC_V11_SEL_1P0V) || ((type) == ADC_V11_SEL_1P1V) || ((type) == ADC_V11_SEL_1P18V) || ((type) == ADC_V11_SEL_1P26V))
+
+/** @defgroup  ADC_CLK_TYPE
+ *  @{
+ */
+#define IS_ADC_CLK_TYPE(type)                                                                                                                                                    \
+  (((type) == ADC_CLK_DIV_1) || ((type) == ADC_CLK_DIV_4) || ((type) == ADC_CLK_DIV_8) || ((type) == ADC_CLK_DIV_12) || ((type) == ADC_CLK_DIV_16) || ((type) == ADC_CLK_DIV_20) \
+   || ((type) == ADC_CLK_DIV_24) || ((type) == ADC_CLK_DIV_32))
+
+/** @defgroup  ADC_DELAY_SEL_TYPE
+ *  @{
+ */
+#define IS_ADC_DELAY_SEL_TYPE(type)                                                                                                                                                       \
+  (((type) == ADC_DELAY_SEL_0) || ((type) == ADC_DELAY_SEL_1) || ((type) == ADC_DELAY_SEL_2) || ((type) == ADC_DELAY_SEL_3) || ((type) == ADC_DELAY_SEL_4) || ((type) == ADC_DELAY_SEL_5) \
+   || ((type) == ADC_DELAY_SEL_6) || ((type) == ADC_DELAY_SEL_7))
+
+/** @defgroup  ADC_PGA_GAIN_TYPE
+ *  @{
+ */
+#define IS_ADC_PGA_GAIN_TYPE(type)                                                                                                                                                      \
+  (((type) == ADC_PGA_GAIN_NONE) || ((type) == ADC_PGA_GAIN_1) || ((type) == ADC_PGA_GAIN_2) || ((type) == ADC_PGA_GAIN_4) || ((type) == ADC_PGA_GAIN_8) || ((type) == ADC_PGA_GAIN_16) \
+   || ((type) == ADC_PGA_GAIN_32))
+
+/** @defgroup  ADC_BIAS_SEL_TYPE
+ *  @{
+ */
+#define IS_ADC_BIAS_SEL_TYPE(type) (((type) == ADC_BIAS_SEL_MAIN_BANDGAP) || ((type) == ADC_BIAS_SEL_AON_BANDGAP))
+
+/** @defgroup  ADC_CHOP_MOD_TYPE
+ *  @{
+ */
+#define IS_ADC_CHOP_MOD_TYPE(type) (((type) == ADC_CHOP_MOD_ALL_OFF) || ((type) == ADC_CHOP_MOD_AZ_ON) || ((type) == ADC_CHOP_MOD_AZ_PGA_ON) || ((type) == ADC_CHOP_MOD_AZ_PGA_RPC_ON))
+
+/** @defgroup  ADC_PGA_VCM_TYPE
+ *  @{
+ */
+#define IS_ADC_PGA_VCM_TYPE(type) (((type) == ADC_PGA_VCM_1V) || ((type) == ADC_PGA_VCM_1P2V) || ((type) == ADC_PGA_VCM_1P4V) || ((type) == ADC_PGA_VCM_1P6V))
+
+/** @defgroup  ADC_TSEN_MOD_TYPE
+ *  @{
+ */
+#define IS_ADC_TSEN_MOD_TYPE(type) (((type) == ADC_TSEN_MOD_INTERNAL_DIODE) || ((type) == ADC_TSEN_MOD_EXTERNAL_DIODE))
+
+/** @defgroup  ADC_VREF_TYPE
+ *  @{
+ */
+#define IS_ADC_VREF_TYPE(type) (((type) == ADC_VREF_3P3V) || ((type) == ADC_VREF_2V))
+
+/** @defgroup  ADC_SIG_INPUT_TYPE
+ *  @{
+ */
+#define IS_ADC_SIG_INPUT_TYPE(type) (((type) == ADC_INPUT_SINGLE_END) || ((type) == ADC_INPUT_DIFF))
+
+/** @defgroup  ADC_DATA_WIDTH_TYPE
+ *  @{
+ */
+#define IS_ADC_DATA_WIDTH_TYPE(type)                                                                                                                                                 \
+  (((type) == ADC_DATA_WIDTH_12) || ((type) == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) || ((type) == ADC_DATA_WIDTH_14_WITH_64_AVERAGE) || ((type) == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) \
+   || ((type) == ADC_DATA_WIDTH_16_WITH_256_AVERAGE))
+
+/** @defgroup  ADC_MICBOOST_DB_TYPE
+ *  @{
+ */
+#define IS_ADC_MICBOOST_DB_TYPE(type) (((type) == ADC_MICBOOST_DB_16DB) || ((type) == ADC_MICBOOST_DB_32DB))
+
+/** @defgroup  ADC_PGA2_GAIN_TYPE
+ *  @{
+ */
+#define IS_ADC_PGA2_GAIN_TYPE(type) (((type) == ADC_PGA2_GAIN_0DB) || ((type) == ADC_PGA2_GAIN_6DB) || ((type) == ADC_PGA2_GAIN_N6DB) || ((type) == ADC_PGA2_GAIN_12DB))
+
+/** @defgroup  ADC_MIC_MODE_TYPE
+ *  @{
+ */
+#define IS_ADC_MIC_MODE_TYPE(type) (((type) == ADC_MIC_MODE_SINGLE) || ((type) == ADC_MIC_MODE_DIFF))
+
+/** @defgroup  ADC_FIFO_THRESHOLD_TYPE
+ *  @{
+ */
+#define IS_ADC_FIFO_THRESHOLD_TYPE(type) (((type) == ADC_FIFO_THRESHOLD_1) || ((type) == ADC_FIFO_THRESHOLD_4) || ((type) == ADC_FIFO_THRESHOLD_8) || ((type) == ADC_FIFO_THRESHOLD_16))
+
+/** @defgroup  ADC_INT_TYPE
+ *  @{
+ */
+#define IS_ADC_INT_TYPE(type)                                                                                                                                                         \
+  (((type) == ADC_INT_POS_SATURATION) || ((type) == ADC_INT_NEG_SATURATION) || ((type) == ADC_INT_FIFO_UNDERRUN) || ((type) == ADC_INT_FIFO_OVERRUN) || ((type) == ADC_INT_ADC_READY) \
+   || ((type) == ADC_INT_FIFO_READY) || ((type) == ADC_INT_ALL))
+
+/*@} end of group ADC_Public_Constants */
+
+/** @defgroup  ADC_Public_Macros
+ *  @{
+ */
+
+/*@} end of group ADC_Public_Macros */
+
+/** @defgroup  ADC_Public_Functions
+ *  @{
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+void GPADC_DMA_IRQHandler(void);
+#endif
+void         ADC_Vbat_Enable(void);
+void         ADC_Vbat_Disable(void);
+void         ADC_Reset(void);
+void         ADC_Enable(void);
+void         ADC_Disable(void);
+void         ADC_Init(ADC_CFG_Type *cfg);
+void         ADC_Channel_Config(ADC_Chan_Type posCh, ADC_Chan_Type negCh, BL_Fun_Type contEn);
+void         ADC_Scan_Channel_Config(const ADC_Chan_Type posChList[], const ADC_Chan_Type negChList[], uint8_t scanLength, BL_Fun_Type contEn);
+void         ADC_Start(void);
+void         ADC_Stop(void);
+void         ADC_FIFO_Cfg(ADC_FIFO_Cfg_Type *fifoCfg);
+uint8_t      ADC_Get_FIFO_Count(void);
+BL_Sts_Type  ADC_FIFO_Is_Empty(void);
+BL_Sts_Type  ADC_FIFO_Is_Full(void);
+void         ADC_FIFO_Clear(void);
+uint32_t     ADC_Read_FIFO(void);
+void         ADC_Parse_Result(uint32_t *orgVal, uint32_t len, ADC_Result_Type *result);
+void         ADC_IntClr(ADC_INT_Type intType);
+BL_Mask_Type ADC_IntGetMask(ADC_INT_Type intType);
+BL_Sts_Type  ADC_GetIntStatus(ADC_INT_Type intType);
+void         ADC_Int_Callback_Install(ADC_INT_Type intType, intCallback_Type *cbFun);
+void         ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask);
+void         ADC_SET_TSVBE_LOW(void);
+void         ADC_SET_TSVBE_HIGH(void);
+void         ADC_Tsen_Init(ADC_TSEN_MOD_Type tsenMod);
+void         ADC_Tsen_Enable(void);
+void         ADC_Tsen_Disable(void);
+void         ADC_PGA_Config(uint8_t pga_vcmi_enable, uint8_t pga_os_cal);
+BL_Err_Type  ADC_Mic_Init(ADC_MIC_Type *adc_mic_config);
+void         ADC_MIC_Bias_Disable(void);
+void         ADC_MIC_Bias_Enable(void);
+BL_Err_Type  ADC_Trim_TSEN(uint16_t *tsen_offset);
+BL_Err_Type  ADC_Gain_Trim(void);
+uint32_t     ADC_Cal_Reg_Coeff_Value(uint32_t raw_reg);
+float        TSEN_Get_Temp(uint32_t tsen_offset);
+
+/*@} end of group ADC_Public_Functions */
+
+/*@} end of group ADC */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_ADC_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_aon.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_aon.h
new file mode 100644
index 00000000..0c2ef2f2
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_aon.h
@@ -0,0 +1,112 @@
+/**
+  ******************************************************************************
+  * @file    bl702_aon.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_AON_H__
+#define __BL702_AON_H__
+
+#include "aon_reg.h"
+#include "glb_reg.h"
+#include "hbn_reg.h"
+#include "pds_reg.h"
+#include "bl702_ef_ctrl.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  AON
+ *  @{
+ */
+
+/** @defgroup  AON_Public_Types
+ *  @{
+ */
+
+/*@} end of group AON_Public_Types */
+
+/** @defgroup  AON_Public_Constants
+ *  @{
+ */
+
+/*@} end of group AON_Public_Constants */
+
+/** @defgroup  AON_Public_Macros
+ *  @{
+ */
+
+/*@} end of group AON_Public_Macros */
+
+/** @defgroup  AON_Public_Functions
+ *  @{
+ */
+/*----------*/
+BL_Err_Type AON_Power_On_MBG(void);
+BL_Err_Type AON_Power_Off_MBG(void);
+/*----------*/
+BL_Err_Type AON_Power_On_XTAL(void);
+BL_Err_Type AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut);
+uint8_t AON_Get_Xtal_CapCode(void);
+BL_Err_Type AON_Set_Xtal_CapCode_Extra(uint8_t extra);
+BL_Err_Type AON_Power_Off_XTAL(void);
+/*----------*/
+BL_Err_Type AON_Power_On_BG(void);
+BL_Err_Type AON_Power_Off_BG(void);
+/*----------*/
+BL_Err_Type AON_Power_On_LDO11_SOC(void);
+BL_Err_Type AON_Power_Off_LDO11_SOC(void);
+/*----------*/
+BL_Err_Type AON_Power_On_LDO15_RF(void);
+BL_Err_Type AON_Power_Off_LDO15_RF(void);
+/*----------*/
+BL_Err_Type AON_Power_On_SFReg(void);
+BL_Err_Type AON_Power_Off_SFReg(void);
+/*----------*/
+BL_Err_Type AON_LowPower_Enter_PDS0(void);
+BL_Err_Type AON_LowPower_Exit_PDS0(void);
+/*----------*/
+BL_Err_Type AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay);
+/*----------*/
+BL_Err_Type AON_Set_DCDC18_Top_0(uint8_t voutSel, uint8_t vpfm);
+BL_Err_Type AON_Set_Xtal_Cfg(uint8_t gmBoost, uint8_t ampCtrl, uint8_t fastStartup);
+/*----------*/
+
+/*@} end of group AON_Public_Functions */
+
+/*@} end of group AON */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_AON_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_cam.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_cam.h
new file mode 100644
index 00000000..d1ed9527
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_cam.h
@@ -0,0 +1,293 @@
+/**
+  ******************************************************************************
+  * @file    bl702_cam.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_CAM_H__
+#define __BL702_CAM_H__
+
+#include "cam_reg.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  CAM
+ *  @{
+ */
+
+/** @defgroup  CAM_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief CAM AHB burst type definition
+ */
+typedef enum {
+    CAM_BURST_TYPE_SINGLE, /*!< Camera AHB burst type:single */
+    CAM_BURST_TYPE_INCR4,  /*!< Camera AHB burst type:incrementing 4 */
+    CAM_BURST_TYPE_INCR8,  /*!< Camera AHB burst type:incrementing 8 */
+    CAM_BURST_TYPE_INCR16, /*!< Camera AHB burst type:incrementing 16 */
+} CAM_Burst_Type;
+
+/**
+ *  @brief CAM software mode type definition
+ */
+typedef enum {
+    CAM_SW_MODE_AUTO,   /*!< CAM auto mode with mjpeg */
+    CAM_SW_MODE_MANUAL, /*!< CAM manual mode(software mode) */
+} CAM_SW_Mode_Type;
+
+/**
+ *  @brief CAM frame mode type definition
+ */
+typedef enum {
+    CAM_PLANAR_MODE,     /*!< CAM planar mode(YYYY.../UVUV...) */
+    CAM_INTERLEAVE_MODE, /*!< CAM interleave mode(YUYVYUYV...) */
+} CAM_Frame_Mode_Type;
+
+/**
+ *  @brief CAM YUV mode type definition
+ */
+typedef enum {
+    CAM_YUV422,      /*!< CAM YUV422 mode */
+    CAM_YUV420_EVEN, /*!< CAM YUV420 mode(raw data:YUYV YUYV..., processed data:YUYV YY...) which dropped odd pix data in
+                                                 odd rows */
+    CAM_YUV420_ODD,  /*!< CAM YUV420 mode(raw data:UYVY UYVY..., processed data:UYVY YY...) which dropped even pix data
+                                                 in odd rows */
+    CAM_YUV400_EVEN, /*!< CAM YUV400 mode(raw data:YUYV YUYV..., processed data:YY YY...) which dropped odd pix data */
+    CAM_YUV400_ODD,  /*!< CAM YUV400 mode(raw data:UYVY UYVY..., processed data:YY YY...) which dropped even pix data */
+} CAM_YUV_Mode_Type;
+
+/**
+ *  @brief CAM line active polarity type definition
+ */
+typedef enum {
+    CAM_LINE_ACTIVE_POLARITY_LOW,  /*!< CAM line active polarity low */
+    CAM_LINE_ACTIVE_POLARITY_HIGH, /*!< CAM line active polarity high */
+} CAM_Line_Active_Pol;
+
+/**
+ *  @brief CAM frame active polarity type definition
+ */
+typedef enum {
+    CAM_FRAME_ACTIVE_POLARITY_LOW,  /*!< CAM frame active polarity low */
+    CAM_FRAME_ACTIVE_POLARITY_HIGH, /*!< CAM frame active polarity high */
+} CAM_Frame_Active_Pol;
+
+/**
+ *  @brief CAM sensor mode type definition
+ */
+typedef enum {
+    CAM_SENSOR_MODE_V_AND_H, /*!< CAM sensor type v and h */
+    CAM_SENSOR_MODE_V_OR_H,  /*!< CAM sensor type v  or h */
+    CAM_SENSOR_MODE_V,       /*!< CAM sensor type v */
+    CAM_SENSOR_MODE_H,       /*!< CAM sensor type h */
+} CAM_Sensor_Mode_Type;
+
+/**
+ *  @brief CAM interrupt type definition
+ */
+typedef enum {
+    CAM_INT_NORMAL_0,           /*!< Interleave mode: normal write interrupt,     planar mode:even byte normal write interrupt */
+    CAM_INT_NORMAL_1,           /*!< Interleave mode: no use,                     planar mode:odd byte normal write interrupt */
+    CAM_INT_MEMORY_OVERWRITE_0, /*!< Interleave mode: memory overwrite interrupt, planar mode:even byte memory overwrite interrupt */
+    CAM_INT_MEMORY_OVERWRITE_1, /*!< Interleave mode: no use,                     planar mode:odd byte memory overwrite interrupt */
+    CAM_INT_FRAME_OVERWRITE_0,  /*!< Interleave mode: frame overwrite interrupt,  planar mode:even byte frame overwrite interrupt */
+    CAM_INT_FRAME_OVERWRITE_1,  /*!< Interleave mode: no use,                     planar mode:odd byte frame overwrite interrupt */
+    CAM_INT_FIFO_OVERWRITE_0,   /*!< Interleave mode: fifo overwrite interrupt,   planar mode:even byte fifo overwrite interrupt */
+    CAM_INT_FIFO_OVERWRITE_1,   /*!< Interleave mode: no use,                     planar mode:odd byte fifo overwrite interrupt */
+    CAM_INT_VSYNC_CNT_ERROR,    /*!< Vsync valid line count non-match interrupt */
+    CAM_INT_HSYNC_CNT_ERROR,    /*!< Hsync valid pixel count non-match interrupt */
+    CAM_INT_ALL,                /*!< All of interrupt */
+} CAM_INT_Type;
+
+/**
+ *  @brief CAM configuration strcut definition
+ */
+typedef struct
+{
+    CAM_SW_Mode_Type swMode;            /*!< Software mode */
+    uint8_t swIntCnt;                   /*!< Set frame count to issue interrupt at software mode */
+    CAM_Frame_Mode_Type frameMode;      /*!< Frame mode */
+    CAM_YUV_Mode_Type yuvMode;          /*!< YUV mode */
+    CAM_Frame_Active_Pol framePol;      /*!< Frame polarity */
+    CAM_Line_Active_Pol linePol;        /*!< Line polarity */
+    CAM_Burst_Type burstType;           /*!< AHB burst type */
+    CAM_Sensor_Mode_Type camSensorMode; /*!< CAM sensor mode */
+    uint8_t waitCount;                  /*!< cycles in FSM wait mode, default value:0x40 */
+    uint32_t memStart0;                 /*!< Interleave mode:data start address,   planar mode:even byte start address */
+    uint32_t memSize0;                  /*!< Interleave mode:memory size in burst, planar mode:even byte memory size in burst */
+    uint32_t frameSize0;                /*!< Interleave mode:frame size in burst,  planar mode:even byte frame size in burst */
+    uint32_t memStart1;                 /*!< Interleave mode:no use,               planar mode:odd byte start address */
+    uint32_t memSize1;                  /*!< Interleave mode:no use,               planar mode:odd byte memory size in burst */
+    uint32_t frameSize1;                /*!< Interleave mode:no use,               planar mode:odd byte frame size in burst */
+} CAM_CFG_Type;
+
+/**
+ *  @brief CAM interleave mode frame information strcut definition
+ */
+typedef struct
+{
+    uint8_t validFrames;    /*!< Valid frames */
+    uint32_t curFrameAddr;  /*!< Current frame address */
+    uint32_t curFrameBytes; /*!< Current frame bytes */
+    uint32_t status;        /*!< CAM module status */
+} CAM_Interleave_Frame_Info;
+
+/**
+ *  @brief CAM planar mode frame information strcut definition
+ */
+typedef struct
+{
+    uint8_t validFrames0;    /*!< Even byte frame counts in memory */
+    uint8_t validFrames1;    /*!< Odd byte frame counts in memory */
+    uint32_t curFrameAddr0;  /*!< Current even frame address */
+    uint32_t curFrameAddr1;  /*!< Current odd frame address */
+    uint32_t curFrameBytes0; /*!< Current even frame bytes */
+    uint32_t curFrameBytes1; /*!< Current odd frame bytes */
+    uint32_t status;         /*!< CAM module status */
+} CAM_Planar_Frame_Info;
+
+/*@} end of group CAM_Public_Types */
+
+/** @defgroup  CAM_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  CAM_BURST_TYPE
+ *  @{
+ */
+#define IS_CAM_BURST_TYPE(type) (((type) == CAM_BURST_TYPE_SINGLE) || \
+                                 ((type) == CAM_BURST_TYPE_INCR4) ||  \
+                                 ((type) == CAM_BURST_TYPE_INCR8) ||  \
+                                 ((type) == CAM_BURST_TYPE_INCR16))
+
+/** @defgroup  CAM_SW_MODE_TYPE
+ *  @{
+ */
+#define IS_CAM_SW_MODE_TYPE(type) (((type) == CAM_SW_MODE_AUTO) || \
+                                   ((type) == CAM_SW_MODE_MANUAL))
+
+/** @defgroup  CAM_FRAME_MODE_TYPE
+ *  @{
+ */
+#define IS_CAM_FRAME_MODE_TYPE(type) (((type) == CAM_PLANAR_MODE) || \
+                                      ((type) == CAM_INTERLEAVE_MODE))
+
+/** @defgroup  CAM_YUV_MODE_TYPE
+ *  @{
+ */
+#define IS_CAM_YUV_MODE_TYPE(type) (((type) == CAM_YUV422) ||      \
+                                    ((type) == CAM_YUV420_EVEN) || \
+                                    ((type) == CAM_YUV420_ODD) ||  \
+                                    ((type) == CAM_YUV400_EVEN) || \
+                                    ((type) == CAM_YUV400_ODD))
+
+/** @defgroup  CAM_LINE_ACTIVE_POL
+ *  @{
+ */
+#define IS_CAM_LINE_ACTIVE_POL(type) (((type) == CAM_LINE_ACTIVE_POLARITY_LOW) || \
+                                      ((type) == CAM_LINE_ACTIVE_POLARITY_HIGH))
+
+/** @defgroup  CAM_FRAME_ACTIVE_POL
+ *  @{
+ */
+#define IS_CAM_FRAME_ACTIVE_POL(type) (((type) == CAM_FRAME_ACTIVE_POLARITY_LOW) || \
+                                       ((type) == CAM_FRAME_ACTIVE_POLARITY_HIGH))
+
+/** @defgroup  CAM_SENSOR_MODE_TYPE
+ *  @{
+ */
+#define IS_CAM_SENSOR_MODE_TYPE(type) (((type) == CAM_SENSOR_MODE_V_AND_H) || \
+                                       ((type) == CAM_SENSOR_MODE_V_OR_H) ||  \
+                                       ((type) == CAM_SENSOR_MODE_V) ||       \
+                                       ((type) == CAM_SENSOR_MODE_H))
+
+/** @defgroup  CAM_INT_TYPE
+ *  @{
+ */
+#define IS_CAM_INT_TYPE(type) (((type) == CAM_INT_NORMAL_0) ||           \
+                               ((type) == CAM_INT_NORMAL_1) ||           \
+                               ((type) == CAM_INT_MEMORY_OVERWRITE_0) || \
+                               ((type) == CAM_INT_MEMORY_OVERWRITE_1) || \
+                               ((type) == CAM_INT_FRAME_OVERWRITE_0) ||  \
+                               ((type) == CAM_INT_FRAME_OVERWRITE_1) ||  \
+                               ((type) == CAM_INT_FIFO_OVERWRITE_0) ||   \
+                               ((type) == CAM_INT_FIFO_OVERWRITE_1) ||   \
+                               ((type) == CAM_INT_VSYNC_CNT_ERROR) ||    \
+                               ((type) == CAM_INT_HSYNC_CNT_ERROR) ||    \
+                               ((type) == CAM_INT_ALL))
+
+/*@} end of group CAM_Public_Constants */
+
+/** @defgroup  CAM_Public_Macros
+ *  @{
+ */
+
+/*@} end of group CAM_Public_Macros */
+
+/** @defgroup  CAM_Public_Functions
+ *  @{
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+void CAM_IRQHandler(void);
+#endif
+void CAM_Init(CAM_CFG_Type *cfg);
+void CAM_Deinit(void);
+void CAM_Enable(void);
+void CAM_Disable(void);
+void CAM_Clock_Gate(BL_Fun_Type enable);
+void CAM_Hsync_Crop(uint16_t start, uint16_t end);
+void CAM_Vsync_Crop(uint16_t start, uint16_t end);
+void CAM_Set_Hsync_Total_Count(uint16_t count);
+void CAM_Set_Vsync_Total_Count(uint16_t count);
+void CAM_Interleave_Get_Frame_Info(CAM_Interleave_Frame_Info *info);
+void CAM_Planar_Get_Frame_Info(CAM_Planar_Frame_Info *info);
+uint8_t CAM_Get_Frame_Count_0(void);
+uint8_t CAM_Get_Frame_Count_1(void);
+void CAM_Interleave_Pop_Frame(void);
+void CAM_Planar_Pop_Frame(void);
+void CAM_IntMask(CAM_INT_Type intType, BL_Mask_Type intMask);
+void CAM_IntClr(CAM_INT_Type intType);
+void CAM_Int_Callback_Install(CAM_INT_Type intType, intCallback_Type *cbFun);
+void CAM_HW_Mode_Wrap(BL_Fun_Type enable);
+
+/*@} end of group CAM_Public_Functions */
+
+/*@} end of group CAM */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_CAM_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_clock.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_clock.h
new file mode 100644
index 00000000..91df7b28
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_clock.h
@@ -0,0 +1,115 @@
+/**
+  ******************************************************************************
+  * @file    bl702_clock.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_CLOCK_H__
+#define __BL702_CLOCK_H__
+
+#include "glb_reg.h"
+#include "bl702_hbn.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  CLOCK
+ *  @{
+ */
+
+/** @defgroup  CLOCK_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief System clock type definition
+ */
+typedef enum {
+    BL_SYSTEM_CLOCK_FCLK, /*!< Fast clock/CPU clock */
+    BL_SYSTEM_CLOCK_BCLK, /*!< BUS clock */
+    BL_SYSTEM_CLOCK_F32K, /*!< F32K clock */
+    BL_SYSTEM_CLOCK_XCLK, /*!< XCLK:RC32M or XTAL */
+    BL_SYSTEM_CLOCK_XTAL, /*!< XTAL clock */
+    BL_SYSTEM_CLOCK_MAX,  /*!< MAX type of system clock */
+} BL_System_Clock_Type;
+
+/**
+ *  @brief SOC clock config type
+ */
+typedef struct
+{
+    uint16_t systemClock[BL_SYSTEM_CLOCK_MAX];   /*!< System lock value */
+    uint16_t peripheralClock[BL_AHB_SLAVE1_MAX]; /*!< Pewripherals clock value */
+    uint32_t i2sClock;                           /*!< I2S clock */
+} Clock_Cfg_Type;
+
+/*@} end of group CLOCK_Public_Types */
+
+/** @defgroup  CLOCK_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  BL_SYSTEM_CLOCK_TYPE
+ *  @{
+ */
+#define IS_BL_SYSTEM_CLOCK_TYPE(type) (((type) == BL_SYSTEM_CLOCK_FCLK) || \
+                                       ((type) == BL_SYSTEM_CLOCK_BCLK) || \
+                                       ((type) == BL_SYSTEM_CLOCK_F32K) || \
+                                       ((type) == BL_SYSTEM_CLOCK_XCLK) || \
+                                       ((type) == BL_SYSTEM_CLOCK_XTAL) || \
+                                       ((type) == BL_SYSTEM_CLOCK_MAX))
+
+/*@} end of group CLOCK_Public_Constants */
+
+/** @defgroup  CLOCK_Public_Macros
+ *  @{
+ */
+
+/*@} end of group CLOCK_Public_Macros */
+
+/** @defgroup  CLOCK_Public_Functions
+ *  @{
+ */
+void Clock_System_Clock_Set(BL_System_Clock_Type type, uint32_t clock);
+void Clock_Peripheral_Clock_Set(BL_AHB_Slave1_Type type, uint32_t clock);
+uint32_t Clock_System_Clock_Get(BL_System_Clock_Type type);
+uint32_t Clock_Peripheral_Clock_Get(BL_AHB_Slave1_Type type);
+
+/*@} end of group CLOCK_Public_Functions */
+
+/*@} end of group CLOCK */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_CLOCK_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_common.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_common.h
new file mode 100644
index 00000000..8867dbf7
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_common.h
@@ -0,0 +1,82 @@
+#ifndef __BL702_COMMON_H__
+#define __BL702_COMMON_H__
+
+#include "bl702.h"
+#include "misc.h"
+
+#ifndef __NOP
+#define __NOP() __ASM volatile("nop") /* This implementation generates debug information */
+#endif
+#ifndef __WFI
+#define __WFI() __ASM volatile("wfi") /* This implementation generates debug information */
+#endif
+#ifndef __WFE
+#define __WFE() __ASM volatile("wfe") /* This implementation generates debug information */
+#endif
+#ifndef __SEV
+#define __SEV() __ASM volatile("sev") /* This implementation generates debug information */
+#endif
+#ifndef __set_MSP
+#define __set_MSP(msp) __ASM volatile("add sp, x0, %0" ::"r"(msp))
+#endif
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) {
+  // return __builtin_bswap32(value);
+  uint32_t res = 0;
+
+  res = (value << 24) | (value >> 24);
+  res &= 0xFF0000FF; /* only for sure */
+  res |= ((value >> 8) & 0x0000FF00) | ((value << 8) & 0x00FF0000);
+
+  return res;
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) { return __builtin_bswap16(value); }
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by setting the IE-bit in the PSR.
+           Can only be executed in Privileged modes.
+ */
+__ALWAYS_STATIC_INLINE void __enable_irq(void) { __ASM volatile("csrs mstatus, 8"); }
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by clearing the IE-bit in the PSR.
+  Can only be executed in Privileged modes.
+ */
+__ALWAYS_STATIC_INLINE void __disable_irq(void) { __ASM volatile("csrc mstatus, 8"); }
+
+/** @defgroup  COMMON_Public_Constants
+ *  @{
+ */
+
+/** @defgroup DRIVER_INT_PERIPH
+ *  @{
+ */
+#define IS_INT_PERIPH(INT_PERIPH) ((INT_PERIPH) < IRQn_LAST)
+
+/*@} end of group DRIVER_INT_PERIPH */
+
+/** @defgroup DRIVER_INT_MASK
+ *  @{
+ */
+#define IS_BL_MASK_TYPE(type) (((type) == MASK) || ((type) == UNMASK))
+
+/*@} end of group COMMON_Public_Constants */
+
+/*@} end of group DRIVER_Public_Macro */
+#define BL702_MemCpy      arch_memcpy
+#define BL702_MemSet      arch_memset
+#define BL702_MemCmp      arch_memcmp
+#define BL702_MemCpy4     arch_memcpy4
+#define BL702_MemCpy_Fast arch_memcpy_fast
+#define BL702_MemSet4     arch_memset4
+
+#define arch_delay_us BL702_Delay_US
+#define arch_delay_ms BL702_Delay_MS
+
+void BL702_Delay_US(uint32_t cnt);
+void BL702_Delay_MS(uint32_t cnt);
+void ASM_Delay_Us(uint32_t core, uint32_t cnt);
+#endif
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_dac.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_dac.h
new file mode 100644
index 00000000..1b82dad8
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_dac.h
@@ -0,0 +1,290 @@
+/**
+  ******************************************************************************
+  * @file    bl702_dac.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_DAC_H__
+#define __BL702_DAC_H__
+
+#include "aon_reg.h"
+#include "glb_reg.h"
+#include "gpip_reg.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  DAC
+ *  @{
+ */
+
+/** @defgroup  DAC_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief DAC reference voltage definition
+ */
+typedef enum {
+    GLB_DAC_REF_SEL_INTERNAL, /*!< DAC reference select internal */
+    GLB_DAC_REF_SEL_EXTERNAL, /*!< DAC reference select external */
+} GLB_DAC_Ref_Sel_Type;
+
+/**
+ *  @brief DAC reference voltage definition
+ */
+typedef enum {
+    GLB_DAC_Output_Volt_0P2_1,       /*!< DAC output voltage is 0.2-1V */
+    GLB_DAC_Output_Volt_0P225_1P425, /*!< DAC output voltage is 0.225-1.425V */
+    GLB_DAC_Output_Volt_RESEVED,     /*!< DAC output voltage is 0.225-1.425V */
+    GLB_DAC_Output_Volt_0P2_1P8,     /*!< DAC output voltage is 0.2-1.8V */
+} GLB_DAC_Output_Volt_Range_Type;
+
+/**
+ *  @brief DAC channel type definition
+ */
+typedef enum {
+    GLB_DAC_CHAN0,    /*!< DAC channel 0 */
+    GLB_DAC_CHAN1,    /*!< DAC channel 1 */
+    GLB_DAC_CHAN2,    /*!< DAC channel 2 */
+    GLB_DAC_CHAN3,    /*!< DAC channel 3 */
+    GLB_DAC_CHAN4,    /*!< DAC channel 4 */
+    GLB_DAC_CHAN5,    /*!< DAC channel 5 */
+    GLB_DAC_CHAN6,    /*!< DAC channel 6 */
+    GLB_DAC_CHAN7,    /*!< DAC channel 7 */
+    GLB_DAC_CHAN_ALL, /*!< DAC channel all */
+} GLB_DAC_Chan_Type;
+
+/**
+ *  @brief DAC channel configuration structure type definition
+ */
+typedef struct
+{
+    BL_Fun_Type chanEn;                      /*!< Enable this channel or not */
+    BL_Fun_Type outputEn;                    /*!< Output this channel result to PAD */
+    GLB_DAC_Chan_Type outMux;                /*!< DAC output mux,NOT implement yet,DAC use fixed GPIO9 and GPIO10 */
+    GLB_DAC_Output_Volt_Range_Type outRange; /*!< DAC output voltage range */
+} GLB_DAC_Chan_Cfg_Type;
+
+/**
+ *  @brief DAC configuration structure type definition
+ */
+typedef struct
+{
+    GLB_DAC_Ref_Sel_Type refSel; /*!< DAC reference voltage select */
+    BL_Fun_Type resetChanA;      /*!< Reset DAC channel A */
+    BL_Fun_Type resetChanB;      /*!< Reset DAC channel B */
+} GLB_DAC_Cfg_Type;
+
+/**
+ *  @brief DAC channel B source selection type definition
+ */
+typedef enum {
+    GPIP_DAC_ChanB_SRC_REG,             /*!< select Reg as source of DAC channel B */
+    GPIP_DAC_ChanB_SRC_DMA,             /*!< select DMA as source of DAC channel B */
+    GPIP_DAC_ChanB_SRC_DMA_WITH_FILTER, /*!< select DMA with Filter as source of DAC channel B */
+    GPIP_DAC_ChanB_SRC_SIN_GEN,         /*!< select Sin Gen as source of DAC channel B */
+    GPIP_DAC_ChanB_SRC_A,               /*!< select channel A as source of DAC channel B */
+    GPIP_DAC_ChanB_SRC_INVERSE_A,       /*!< select inverse of channel A as source of DAC channel B */
+} GPIP_DAC_ChanB_SRC_Type;
+
+/**
+ *  @brief DAC channel A source selection type definition
+ */
+typedef enum {
+    GPIP_DAC_ChanA_SRC_REG,             /*!< select Reg as source of DAC channel A */
+    GPIP_DAC_ChanA_SRC_DMA,             /*!< select DMA as source of DAC channel A */
+    GPIP_DAC_ChanA_SRC_DMA_WITH_FILTER, /*!< select DMA with Filter as source of DAC channel A */
+    GPIP_DAC_ChanA_SRC_SIN_GEN,         /*!< select Sin Gen as source of DAC channel A */
+} GPIP_DAC_ChanA_SRC_Type;
+
+/**
+ *  @brief DAC clock divider type definition
+ */
+typedef enum {
+    DAC_CLK_DIV_16,      /*!< ADC clock:on 32M clock is 2M */
+    DAC_CLK_DIV_32,      /*!< ADC clock:on 32M clock is 1M */
+    DAC_CLK_DIV_RESERVE, /*!< reserved */
+    DAC_CLK_DIV_64,      /*!< ADC clock:on 32M clock is 0.5M */
+    DAC_CLK_DIV_1,       /*!< ADC clock:on 32M clock is 32M */
+} DAC_CLK_Type;
+
+/**
+ *  @brief DAC DMA TX format selection type definition
+ */
+typedef enum {
+    GPIP_DAC_DMA_FORMAT_0, /*!< {A0},{A1},{A2},... */
+    GPIP_DAC_DMA_FORMAT_1, /*!< {B0,A0},{B1,A1},{B2,A2},... */
+    GPIP_DAC_DMA_FORMAT_2, /*!< {A1,A0},{A3,A2},{A5,A4},... */
+} GPIP_DAC_DMA_TX_FORMAT_Type;
+
+/**
+ *  @brief AON and GPIP DAC configuration structure type definition
+ */
+typedef struct
+{
+    GLB_DAC_Ref_Sel_Type refSel;        /*!< DAC reference voltage select */
+    BL_Fun_Type resetChanA;             /*!< Reset DAC channel A */
+    BL_Fun_Type resetChanB;             /*!< Reset DAC channel B */
+    DAC_CLK_Type div;                   /*!< DAC clock div */
+    BL_Fun_Type dmaEn;                  /*!< DAC DMA transfer enable */
+    GPIP_DAC_DMA_TX_FORMAT_Type dmaFmt; /*!< DAC DMA TX format selection */
+} GLB_GPIP_DAC_Cfg_Type;
+
+/**
+ *  @brief AON and GPIP DAC channel A configuration structure type definition
+ */
+typedef struct
+{
+    BL_Fun_Type chanCovtEn;      /*!< Enable this channel conversion or not */
+    BL_Fun_Type outputEn;        /*!< Output this channel result to PAD */
+    BL_Fun_Type chanEn;          /*!< Enable this channel or not */
+    GPIP_DAC_ChanA_SRC_Type src; /*!< DAC channel A source */
+} GLB_GPIP_DAC_ChanA_Cfg_Type;
+
+/**
+ *  @brief AON and GPIP DAC channel B configuration structure type definition
+ */
+typedef struct
+{
+    BL_Fun_Type chanCovtEn;      /*!< Enable this channel conversion or not */
+    BL_Fun_Type outputEn;        /*!< Output this channel result to PAD */
+    BL_Fun_Type chanEn;          /*!< Enable this channel or not */
+    GPIP_DAC_ChanB_SRC_Type src; /*!< DAC channel B source */
+} GLB_GPIP_DAC_ChanB_Cfg_Type;
+
+/*@} end of group DAC_Public_Types */
+
+/** @defgroup  DAC_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  GLB_DAC_REF_SEL_TYPE
+ *  @{
+ */
+#define IS_GLB_DAC_REF_SEL_TYPE(type) (((type) == GLB_DAC_REF_SEL_INTERNAL) || \
+                                       ((type) == GLB_DAC_REF_SEL_EXTERNAL))
+
+/** @defgroup  GLB_DAC_OUTPUT_VOLT_RANGE_TYPE
+ *  @{
+ */
+#define IS_GLB_DAC_OUTPUT_VOLT_RANGE_TYPE(type) (((type) == GLB_DAC_Output_Volt_0P2_1) ||       \
+                                                 ((type) == GLB_DAC_Output_Volt_0P225_1P425) || \
+                                                 ((type) == GLB_DAC_Output_Volt_RESEVED) ||     \
+                                                 ((type) == GLB_DAC_Output_Volt_0P2_1P8))
+
+/** @defgroup  GLB_DAC_CHAN_TYPE
+ *  @{
+ */
+#define IS_GLB_DAC_CHAN_TYPE(type) (((type) == GLB_DAC_CHAN0) || \
+                                    ((type) == GLB_DAC_CHAN1) || \
+                                    ((type) == GLB_DAC_CHAN2) || \
+                                    ((type) == GLB_DAC_CHAN3) || \
+                                    ((type) == GLB_DAC_CHAN4) || \
+                                    ((type) == GLB_DAC_CHAN5) || \
+                                    ((type) == GLB_DAC_CHAN6) || \
+                                    ((type) == GLB_DAC_CHAN7) || \
+                                    ((type) == GLB_DAC_CHAN_ALL))
+
+/** @defgroup  GPIP_DAC_CHANB_SRC_TYPE
+ *  @{
+ */
+#define IS_GPIP_DAC_CHANB_SRC_TYPE(type) (((type) == GPIP_DAC_ChanB_SRC_REG) ||             \
+                                          ((type) == GPIP_DAC_ChanB_SRC_DMA) ||             \
+                                          ((type) == GPIP_DAC_ChanB_SRC_DMA_WITH_FILTER) || \
+                                          ((type) == GPIP_DAC_ChanB_SRC_SIN_GEN) ||         \
+                                          ((type) == GPIP_DAC_ChanB_SRC_A) ||               \
+                                          ((type) == GPIP_DAC_ChanB_SRC_INVERSE_A))
+
+/** @defgroup  GPIP_DAC_CHANA_SRC_TYPE
+ *  @{
+ */
+#define IS_GPIP_DAC_CHANA_SRC_TYPE(type) (((type) == GPIP_DAC_ChanA_SRC_REG) ||             \
+                                          ((type) == GPIP_DAC_ChanA_SRC_DMA) ||             \
+                                          ((type) == GPIP_DAC_ChanA_SRC_DMA_WITH_FILTER) || \
+                                          ((type) == GPIP_DAC_ChanA_SRC_SIN_GEN))
+
+/** @defgroup  DAC_CLK_TYPE
+ *  @{
+ */
+#define IS_DAC_CLK_TYPE(type) (((type) == DAC_CLK_DIV_16) ||      \
+                               ((type) == DAC_CLK_DIV_32) ||      \
+                               ((type) == DAC_CLK_DIV_RESERVE) || \
+                               ((type) == DAC_CLK_DIV_64) ||      \
+                               ((type) == DAC_CLK_DIV_1))
+
+/** @defgroup  GPIP_DAC_DMA_TX_FORMAT_TYPE
+ *  @{
+ */
+#define IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(type) (((type) == GPIP_DAC_DMA_FORMAT_0) || \
+                                              ((type) == GPIP_DAC_DMA_FORMAT_1) || \
+                                              ((type) == GPIP_DAC_DMA_FORMAT_2))
+
+/*@} end of group DAC_Public_Constants */
+
+/** @defgroup  DAC_Public_Macros
+ *  @{
+ */
+
+/*@} end of group DAC_Public_Macros */
+
+/** @defgroup  DAC_Public_Functions
+ *  @{
+ */
+void GLB_DAC_Init(GLB_DAC_Cfg_Type *cfg);
+void GLB_DAC_Set_ChanA_Config(GLB_DAC_Chan_Cfg_Type *cfg);
+void GLB_DAC_Set_ChanB_Config(GLB_DAC_Chan_Cfg_Type *cfg);
+void GPIP_Set_DAC_ChanB_SRC_SEL(GPIP_DAC_ChanB_SRC_Type src);
+void GPIP_Set_DAC_ChanA_SRC_SEL(GPIP_DAC_ChanA_SRC_Type src);
+void GPIP_DAC_ChanB_Enable(void);
+void GPIP_DAC_ChanB_Disable(void);
+void GPIP_DAC_ChanA_Enable(void);
+void GPIP_DAC_ChanA_Disable(void);
+void GPIP_Set_DAC_DMA_TX_FORMAT_SEL(GPIP_DAC_DMA_TX_FORMAT_Type fmt);
+void GPIP_Set_DAC_DMA_TX_Enable(void);
+void GPIP_Set_DAC_DMA_TX_Disable(void);
+void GPIP_DAC_DMA_WriteData(uint32_t data);
+BL_Err_Type GLB_GPIP_DAC_Init(GLB_GPIP_DAC_Cfg_Type *cfg);
+void GLB_GPIP_DAC_Set_ChanA_Config(GLB_GPIP_DAC_ChanA_Cfg_Type *cfg);
+void GLB_GPIP_DAC_Set_ChanB_Config(GLB_GPIP_DAC_ChanB_Cfg_Type *cfg);
+void GLB_DAC_Set_ChanA_Value(uint16_t val);
+void GLB_DAC_Set_ChanB_Value(uint16_t val);
+
+/*@} end of group DAC_Public_Functions */
+
+/*@} end of group DAC */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_DAC_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_dma.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_dma.h
new file mode 100644
index 00000000..e94927bb
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_dma.h
@@ -0,0 +1,366 @@
+/**
+  ******************************************************************************
+  * @file    bl702_dma.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_DMA_H__
+#define __BL702_DMA_H__
+
+#include "dma_reg.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  DMA
+ *  @{
+ */
+
+/** @defgroup  DMA_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief DMA endian type definition
+ */
+typedef enum {
+    DMA_LITTLE_ENDIAN = 0, /*!< DMA use little endian */
+    DMA_BIG_ENDIAN,        /*!< DMA use big endian */
+} DMA_Endian_Type;
+
+/**
+ *  @brief DMA synchronization logic  type definition
+ */
+typedef enum {
+    DMA_SYNC_LOGIC_ENABLE = 0, /*!< DMA synchronization logic enable */
+    DMA_SYNC_LOGIC_DISABLE,    /*!< DMA synchronization logic disable */
+} DMA_Sync_Logic_Type;
+
+/**
+ *  @brief DMA transfer width type definition
+ */
+typedef enum {
+    DMA_TRNS_WIDTH_8BITS = 0, /*!< DMA transfer width:8 bits */
+    DMA_TRNS_WIDTH_16BITS,    /*!< DMA transfer width:16 bits */
+    DMA_TRNS_WIDTH_32BITS,    /*!< DMA transfer width:32 bits */
+} DMA_Trans_Width_Type;
+
+/**
+ *  @brief DMA transfer direction type definition
+ */
+typedef enum {
+    DMA_TRNS_M2M = 0, /*!< DMA transfer tyep:memory to memory */
+    DMA_TRNS_M2P,     /*!< DMA transfer tyep:memory to peripheral */
+    DMA_TRNS_P2M,     /*!< DMA transfer tyep:peripheral to memory */
+    DMA_TRNS_P2P,     /*!< DMA transfer tyep:peripheral to peripheral */
+} DMA_Trans_Dir_Type;
+
+/**
+ *  @brief DMA burst size type definition
+ */
+typedef enum {
+    DMA_BURST_SIZE_1 = 0, /*!< DMA transfer width:8 bits */
+    DMA_BURST_SIZE_4,     /*!< DMA transfer width:16 bits */
+    DMA_BURST_SIZE_8,     /*!< DMA transfer width:32 bits */
+    DMA_BURST_SIZE_16,    /*!< DMA transfer width:64 bits */
+} DMA_Burst_Size_Type;
+
+/**
+ *  @brief DMA destination peripheral type definition
+ */
+typedef enum {
+    DMA_REQ_UART0_RX = 0, /*!< DMA request peripheral:UART0 RX */
+    DMA_REQ_UART0_TX,     /*!< DMA request peripheral:UART0 TX */
+    DMA_REQ_UART1_RX,     /*!< DMA request peripheral:UART1 RX */
+    DMA_REQ_UART1_TX,     /*!< DMA request peripheral:UART1 TX */
+    DMA_REQ_I2C_RX = 6,   /*!< DMA request peripheral:I2C RX */
+    DMA_REQ_I2C_TX,       /*!< DMA request peripheral:I2C TX */
+    DMA_REQ_SPI_RX = 10,  /*!< DMA request peripheral:SPI RX */
+    DMA_REQ_SPI_TX,       /*!< DMA request peripheral:SPI TX */
+    DMA_REQ_I2S_RX = 20,  /*!< DMA request peripheral:SPI RX */
+    DMA_REQ_I2S_TX,       /*!< DMA request peripheral:SPI TX */
+    DMA_REQ_GPADC0 = 22,  /*!< DMA request peripheral:GPADC0 */
+    DMA_REQ_GPADC1,       /*!< DMA request peripheral:GPADC1 */
+    DMA_REQ_NONE = 0,     /*!< DMA request peripheral:None */
+} DMA_Periph_Req_Type;
+
+/**
+ *  @brief DMA channel type definition
+ */
+typedef enum {
+    DMA_CH0 = 0, /*!< DMA channel 0 */
+    DMA_CH1,     /*!< DMA channel 1 */
+    DMA_CH2,     /*!< DMA channel 2 */
+    DMA_CH3,     /*!< DMA channel 3 */
+    DMA_CH4,     /*!< DMA channel 4 */
+    DMA_CH5,     /*!< DMA channel 5 */
+    DMA_CH6,     /*!< DMA channel 6 */
+    DMA_CH7,     /*!< DMA channel 7 */
+    DMA_CH_MAX,  /*!<  */
+} DMA_Chan_Type;
+
+/**
+ *  @brief DMA LLI Structure PING-PONG
+ */
+typedef enum {
+    PING_INDEX = 0, /*!< PING INDEX */
+    PONG_INDEX,     /*!< PONG INDEX */
+} DMA_LLI_PP_Index_Type;
+
+/**
+ *  @brief DMA interrupt type definition
+ */
+typedef enum {
+    DMA_INT_TCOMPLETED = 0, /*!< DMA completed interrupt */
+    DMA_INT_ERR,            /*!< DMA error interrupt */
+    DMA_INT_ALL,            /*!< All the interrupt */
+} DMA_INT_Type;
+
+/**
+ *  @brief DMA Configuration Structure type definition
+ */
+typedef struct
+{
+    DMA_Endian_Type endian;        /*!< DMA endian type */
+    DMA_Sync_Logic_Type syncLogic; /*!< DMA synchronization logic */
+} DMA_Cfg_Type;
+
+/**
+ *  @brief DMA channel Configuration Structure type definition
+ */
+typedef struct
+{
+    uint32_t srcDmaAddr;                 /*!< Source address of DMA transfer */
+    uint32_t destDmaAddr;                /*!< Destination address of DMA transfer */
+    uint32_t transfLength;               /*!< Transfer length, 0~4095, this is burst count */
+    DMA_Trans_Dir_Type dir;              /*!< Transfer dir control. 0: Memory to Memory, 1: Memory to peripheral, 2: Peripheral to memory */
+    DMA_Chan_Type ch;                    /*!< Channel select 0-7 */
+    DMA_Trans_Width_Type srcTransfWidth; /*!< Transfer width. 0: 8  bits, 1: 16  bits, 2: 32  bits */
+    DMA_Trans_Width_Type dstTransfWidth; /*!< Transfer width. 0: 8  bits, 1: 16  bits, 2: 32  bits */
+    DMA_Burst_Size_Type srcBurstSzie;    /*!< Number of data items for burst transaction length. Each item width is as same as tansfer width.
+                                                 0: 1 item, 1: 4 items, 2: 8 items, 3: 16 items */
+    DMA_Burst_Size_Type dstBurstSzie;    /*!< Number of data items for burst transaction length. Each item width is as same as tansfer width.
+                                                 0: 1 item, 1: 4 items, 2: 8 items, 3: 16 items */
+    BL_Fun_Type dstAddMode;              /*!<  */
+    BL_Fun_Type dstMinMode;              /*!<  */
+    uint8_t fixCnt;                      /*!<  */
+    uint8_t srcAddrInc;                  /*!< Source address increment. 0: No change, 1: Increment */
+    uint8_t destAddrInc;                 /*!< Destination address increment. 0: No change, 1: Increment */
+    DMA_Periph_Req_Type srcPeriph;       /*!< Source peripheral select */
+    DMA_Periph_Req_Type dstPeriph;       /*!< Destination peripheral select */
+} DMA_Channel_Cfg_Type;
+
+/**
+ *  @brief DMA LLI control structure type definition
+ */
+typedef struct
+{
+    uint32_t srcDmaAddr;            /*!< Source address of DMA transfer */
+    uint32_t destDmaAddr;           /*!< Destination address of DMA transfer */
+    uint32_t nextLLI;               /*!< Next LLI address */
+    struct DMA_Control_Reg dmaCtrl; /*!< DMA transaction control */
+} DMA_LLI_Ctrl_Type;
+
+/**
+ *  @brief DMA LLI configuration structure type definition
+ */
+typedef struct
+{
+    DMA_Trans_Dir_Type dir;        /*!< Transfer dir control. 0: Memory to Memory, 1: Memory to peripheral, 2: Peripheral to memory */
+    DMA_Periph_Req_Type srcPeriph; /*!< Source peripheral select */
+    DMA_Periph_Req_Type dstPeriph; /*!< Destination peripheral select */
+} DMA_LLI_Cfg_Type;
+
+/**
+ *  @brief DMA LLI Ping-Pong Buf definition
+ */
+typedef struct
+{
+    uint8_t idleIndex;                             /*!< Index Idle lliListHeader */
+    uint8_t dmaChan;                               /*!< DMA LLI Channel used */
+    DMA_LLI_Ctrl_Type *lliListHeader[2];           /*!< Ping-Pong BUf List Header */
+    void (*onTransCompleted)(DMA_LLI_Ctrl_Type *); /*!< Completed Transmit One List Callback Function */
+} DMA_LLI_PP_Buf;
+
+/**
+ *  @brief DMA LLI Ping-Pong Structure definition
+ */
+typedef struct
+{
+    uint8_t trans_index;                  /*!< Ping or Pong Trigger TC */
+    uint8_t dmaChan;                      /*!< DMA LLI Channel used */
+    struct DMA_Control_Reg dmaCtrlRegVal; /*!< DMA Basic Pararmeter */
+    DMA_LLI_Cfg_Type *DMA_LLI_Cfg;        /*!< LLI Config parameter */
+    uint32_t operatePeriphAddr;           /*!< Operate Peripheral register address */
+    uint32_t chache_buf_addr[2];          /*!< Ping-Pong structure chache */
+    BL_Fun_Type is_single_mode;           /*!< is Ping-pong running forever or single mode ,if is single mode ping-pong will run only once
+                                                 after one start */
+} DMA_LLI_PP_Struct;
+
+/*@} end of group DMA_Public_Types */
+
+/** @defgroup  DMA_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  DMA_ENDIAN_TYPE
+ *  @{
+ */
+#define IS_DMA_ENDIAN_TYPE(type) (((type) == DMA_LITTLE_ENDIAN) || \
+                                  ((type) == DMA_BIG_ENDIAN))
+
+/** @defgroup  DMA_SYNC_LOGIC_TYPE
+ *  @{
+ */
+#define IS_DMA_SYNC_LOGIC_TYPE(type) (((type) == DMA_SYNC_LOGIC_ENABLE) || \
+                                      ((type) == DMA_SYNC_LOGIC_DISABLE))
+
+/** @defgroup  DMA_TRANS_WIDTH_TYPE
+ *  @{
+ */
+#define IS_DMA_TRANS_WIDTH_TYPE(type) (((type) == DMA_TRNS_WIDTH_8BITS) ||  \
+                                       ((type) == DMA_TRNS_WIDTH_16BITS) || \
+                                       ((type) == DMA_TRNS_WIDTH_32BITS))
+
+/** @defgroup  DMA_TRANS_DIR_TYPE
+ *  @{
+ */
+#define IS_DMA_TRANS_DIR_TYPE(type) (((type) == DMA_TRNS_M2M) || \
+                                     ((type) == DMA_TRNS_M2P) || \
+                                     ((type) == DMA_TRNS_P2M) || \
+                                     ((type) == DMA_TRNS_P2P))
+
+/** @defgroup  DMA_BURST_SIZE_TYPE
+ *  @{
+ */
+#define IS_DMA_BURST_SIZE_TYPE(type) (((type) == DMA_BURST_SIZE_1) || \
+                                      ((type) == DMA_BURST_SIZE_4) || \
+                                      ((type) == DMA_BURST_SIZE_8) || \
+                                      ((type) == DMA_BURST_SIZE_16))
+
+/** @defgroup  DMA_PERIPH_REQ_TYPE
+ *  @{
+ */
+#define IS_DMA_PERIPH_REQ_TYPE(type) (((type) == DMA_REQ_UART0_RX) || \
+                                      ((type) == DMA_REQ_UART0_TX) || \
+                                      ((type) == DMA_REQ_UART1_RX) || \
+                                      ((type) == DMA_REQ_UART1_TX) || \
+                                      ((type) == DMA_REQ_I2C_RX) ||   \
+                                      ((type) == DMA_REQ_I2C_TX) ||   \
+                                      ((type) == DMA_REQ_SPI_RX) ||   \
+                                      ((type) == DMA_REQ_SPI_TX) ||   \
+                                      ((type) == DMA_REQ_I2S_RX) ||   \
+                                      ((type) == DMA_REQ_I2S_TX) ||   \
+                                      ((type) == DMA_REQ_GPADC0) ||   \
+                                      ((type) == DMA_REQ_GPADC1) ||   \
+                                      ((type) == DMA_REQ_NONE))
+
+/** @defgroup  DMA_CHAN_TYPE
+ *  @{
+ */
+#define IS_DMA_CHAN_TYPE(type) (((type) == DMA_CH0) || \
+                                ((type) == DMA_CH1) || \
+                                ((type) == DMA_CH2) || \
+                                ((type) == DMA_CH3) || \
+                                ((type) == DMA_CH4) || \
+                                ((type) == DMA_CH5) || \
+                                ((type) == DMA_CH6) || \
+                                ((type) == DMA_CH7) || \
+                                ((type) == DMA_CH_MAX))
+
+/** @defgroup  DMA_LLI_PP_INDEX_TYPE
+ *  @{
+ */
+#define IS_DMA_LLI_PP_INDEX_TYPE(type) (((type) == PING_INDEX) || \
+                                        ((type) == PONG_INDEX))
+
+/** @defgroup  DMA_INT_TYPE
+ *  @{
+ */
+#define IS_DMA_INT_TYPE(type) (((type) == DMA_INT_TCOMPLETED) || \
+                               ((type) == DMA_INT_ERR) ||        \
+                               ((type) == DMA_INT_ALL))
+
+/*@} end of group DMA_Public_Constants */
+
+/** @defgroup  DMA_Public_Macros
+ *  @{
+ */
+#define DMA_PINC_ENABLE  1
+#define DMA_PINC_DISABLE 0
+#define DMA_MINC_ENABLE  1
+#define DMA_MINC_DISABLE 0
+
+/*@} end of group DMA_Public_Macros */
+
+/** @defgroup  DMA_Public_Functions
+ *  @{
+ */
+
+/**
+ *  @brief DMA Functions
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+void DMA_ALL_IRQHandler(void);
+#endif
+void DMA_Enable(void);
+void DMA_Disable(void);
+void DMA_Channel_Init(DMA_Channel_Cfg_Type *chCfg);
+void DMA_Channel_Update_SrcMemcfg(uint8_t ch, uint32_t memAddr, uint32_t len);
+void DMA_Channel_Update_DstMemcfg(uint8_t ch, uint32_t memAddr, uint32_t len);
+uint32_t DMA_Channel_TranferSize(uint8_t ch);
+BL_Sts_Type DMA_Channel_Is_Busy(uint8_t ch);
+void DMA_Channel_Enable(uint8_t ch);
+void DMA_Channel_Disable(uint8_t ch);
+void DMA_LLI_Init(uint8_t ch, DMA_LLI_Cfg_Type *lliCfg);
+void DMA_LLI_Update(uint8_t ch, uint32_t LLI);
+void DMA_IntMask(uint8_t ch, DMA_INT_Type intType, BL_Mask_Type intMask);
+void DMA_LLI_PpBuf_Start_New_Transmit(DMA_LLI_PP_Buf *dmaPpBuf);
+DMA_LLI_Ctrl_Type *DMA_LLI_PpBuf_Remove_Completed_List(DMA_LLI_PP_Buf *dmaPpBuf);
+void DMA_LLI_PpBuf_Append(DMA_LLI_PP_Buf *dmaPpBuf, DMA_LLI_Ctrl_Type *dmaLliList);
+void DMA_LLI_PpBuf_Destroy(DMA_LLI_PP_Buf *dmaPpBuf);
+void DMA_Int_Callback_Install(DMA_Chan_Type dmaChan, DMA_INT_Type intType, intCallback_Type *cbFun);
+void DMA_LLI_PpStruct_Start(DMA_LLI_PP_Struct *dmaPpStruct);
+void DMA_LLI_PpStruct_Stop(DMA_LLI_PP_Struct *dmaPpStruct);
+BL_Err_Type DMA_LLI_PpStruct_Init(DMA_LLI_PP_Struct *dmaPpStruct);
+BL_Err_Type DMA_LLI_PpStruct_Set_Transfer_Len(DMA_LLI_PP_Struct *dmaPpStruct,
+                                              uint16_t Ping_Transfer_len, uint16_t Pong_Transfer_len);
+
+/*@} end of group DMA_Public_Functions */
+
+/*@} end of group DMA */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_DMA_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_ef_ctrl.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_ef_ctrl.h
new file mode 100644
index 00000000..81739155
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_ef_ctrl.h
@@ -0,0 +1,310 @@
+/**
+ ******************************************************************************
+ * @file    bl702_ef_ctrl.h
+ * @version V1.0
+ * @date
+ * @brief   This file is the standard driver header file
+ ******************************************************************************
+ * @attention
+ *
+ * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __BL702_EF_CTRL_H__
+#define __BL702_EF_CTRL_H__
+
+#include "bl702_common.h"
+#include "ef_ctrl_reg.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  EF_CTRL
+ *  @{
+ */
+
+/** @defgroup  EF_CTRL_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief Efuse Ctrl key slot type definition
+ */
+typedef enum {
+  EF_CTRL_KEY_SLOT0, /*!< key slot 0 */
+  EF_CTRL_KEY_SLOT1, /*!< key slot 1 */
+  EF_CTRL_KEY_SLOT2, /*!< key slot 2 */
+  EF_CTRL_KEY_SLOT3, /*!< key slot 3 */
+  EF_CTRL_KEY_SLOT4, /*!< key slot 4 */
+  EF_CTRL_KEY_SLOT5, /*!< key slot 5 */
+  EF_CTRL_KEY_MAX,   /*!<  */
+} EF_Ctrl_Key_Type;
+
+/**
+ *  @brief Efuse Ctrl sign type definition
+ */
+typedef enum {
+  EF_CTRL_SIGN_NONE, /*!< no sign */
+  EF_CTRL_SIGN_RSA,  /*!< use RSA to sign */
+  EF_CTRL_SIGN_ECC,  /*!< use ECC to sign */
+} EF_Ctrl_Sign_Type;
+
+/**
+ *  @brief Efuse Ctrl flash AES type definition
+ */
+typedef enum {
+  EF_CTRL_SF_AES_NONE, /*!< No AES */
+  EF_CTRL_SF_AES_128,  /*!< AES 128 */
+  EF_CTRL_SF_AES_192,  /*!< AES 192 */
+  EF_CTRL_SF_AES_256,  /*!< AES 256 */
+} EF_Ctrl_SF_AES_Type;
+
+/**
+ *  @brief Efuse Ctrl Dbg type definition
+ */
+typedef enum {
+  EF_CTRL_DBG_OPEN = 0,  /*!< Open debug */
+  EF_CTRL_DBG_PASSWORD,  /*!< Open debug with password */
+  EF_CTRL_DBG_CLOSE = 4, /*!< Close debug */
+} EF_Ctrl_Dbg_Mode_Type;
+
+/**
+ *  @brief Efuse Ctrl clock type definition
+ */
+typedef enum {
+  EF_CTRL_EF_CLK,   /*!< Select efuse clock */
+  EF_CTRL_SAHB_CLK, /*!< Select SAHB clock */
+} EF_Ctrl_CLK_Type;
+
+/**
+ *  @brief Efuse Ctrl clock type definition
+ */
+typedef enum {
+  EF_CTRL_PARA_DFT,    /*!< Select default cyc parameter */
+  EF_CTRL_PARA_MANUAL, /*!< Select manual cyc parameter */
+} EF_Ctrl_CYC_PARA_Type;
+
+/**
+ *  @brief Efuse Ctrl clock type definition
+ */
+typedef enum {
+  EF_CTRL_OP_MODE_AUTO,   /*!< Select efuse program auto mode */
+  EF_CTRL_OP_MODE_MANUAL, /*!< Select efuse program manual mode */
+} EF_Ctrl_OP_MODE_Type;
+
+/**
+ *  @brief Efuse Ctrl secure configuration structure type definition
+ */
+typedef struct {
+  EF_Ctrl_Dbg_Mode_Type ef_dbg_mode;       /*!< Efuse debug mode */
+  uint8_t               ef_dbg_jtag_0_dis; /*!< Jtag debug disable config value */
+  uint8_t               ef_sboot_en;       /*!< Secure boot enable config value */
+} EF_Ctrl_Sec_Param_Type;
+
+/**
+ *  @brief Efuse analog RC32M trim type definition
+ */
+typedef struct {
+  uint32_t trimRc32mCodeFrExt : 8;       /*!< Efuse analog trim:trim_rc32m_code_fr_ext */
+  uint32_t trimRc32mCodeFrExtParity : 1; /*!< Efuse analog trim:trim_rc32m_ext_code_en_parity */
+  uint32_t trimRc32mExtCodeEn : 1;       /*!< Efuse analog trim:trim_rc32m_ext_code_en */
+  uint32_t reserved : 22;                /*!< Efuse analog trim:reserved */
+} Efuse_Ana_RC32M_Trim_Type;
+
+/**
+ *  @brief Efuse analog RC32K trim type definition
+ */
+typedef struct {
+  uint32_t trimRc32kCodeFrExt : 10;      /*!< Efuse analog trim:trim_rc32k_code_fr_ext */
+  uint32_t trimRc32kCodeFrExtParity : 1; /*!< Efuse analog trim:trim_rc32k_code_fr_ext_parity */
+  uint32_t trimRc32kExtCodeEn : 1;       /*!< Efuse analog trim:trim_rc32k_ext_code_en */
+  uint32_t reserved : 20;                /*!< Efuse analog trim:reserved */
+} Efuse_Ana_RC32K_Trim_Type;
+
+/**
+ *  @brief Efuse analog TSEN trim type definition
+ */
+typedef struct {
+  uint32_t tsenRefcodeCorner : 12;       /*!< TSEN refcode */
+  uint32_t tsenRefcodeCornerParity : 1;  /*!< TSEN refcode parity */
+  uint32_t tsenRefcodeCornerEn : 1;      /*!< TSEN refcode enable */
+  uint32_t tsenRefcodeCornerVersion : 1; /*!< TSEN ATE Version */
+  uint32_t reserved : 18;                /*!< TSEN analog trim:reserved */
+} Efuse_TSEN_Refcode_Corner_Type;
+
+/**
+ *  @brief Efuse analog ADC Gain trim type definition
+ */
+typedef struct {
+  uint32_t adcGainCoeff : 12;      /*!< ADC gain coeff */
+  uint32_t adcGainCoeffParity : 1; /*!< ADC gain coeff parity */
+  uint32_t adcGainCoeffEn : 1;     /*!< ADC gain coeff enable */
+  uint32_t reserved : 18;          /*!< ADC gain coeff:reserved */
+} Efuse_ADC_Gain_Coeff_Type;
+
+/**
+ *  @brief Efuse analog device info type definition
+ */
+typedef struct {
+  uint32_t rsvd_21_0 : 22;  /*!< Reserved */
+  uint32_t sf_swap_cfg : 2; /*!< 0:swap none, 1:swap SF2_CS & SF2_IO2, 2:swap SF2_IO0 & SF2_IO3, 3:swap both */
+  uint32_t psram_cfg : 2;   /*!< 0:no psram, 1:2MB psram, 2:external psram, 3:reserved */
+  uint32_t flash_cfg : 3;   /*!< 0:external flash SF2, 1:0.5MB flash, 2:1MB flash, 3:external flash SF1 */
+  uint32_t rsvd_29 : 1;     /*!< Reserved */
+  uint32_t pkg_info : 2;    /*!< 0:QFN32, 1:QFN40, 2:QFN48, 3:reserved */
+} Efuse_Device_Info_Type;
+
+/**
+ *  @brief Efuse Capcode type definition
+ */
+typedef struct {
+  uint32_t capCode : 6; /*!< Cap code value */
+  uint32_t parity : 1;  /*!< Parity of capcode */
+  uint32_t en : 1;      /*!< Enable status */
+  uint32_t rsvd : 24;   /*!< Reserved */
+} Efuse_Capcode_Info_Type;
+
+/*@} end of group EF_CTRL_Public_Types */
+
+/** @defgroup  EF_CTRL_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  EF_CTRL_KEY_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_KEY_TYPE(type)                                                                                                                                                                     \
+  (((type) == EF_CTRL_KEY_SLOT0) || ((type) == EF_CTRL_KEY_SLOT1) || ((type) == EF_CTRL_KEY_SLOT2) || ((type) == EF_CTRL_KEY_SLOT3) || ((type) == EF_CTRL_KEY_SLOT4) || ((type) == EF_CTRL_KEY_SLOT5) \
+   || ((type) == EF_CTRL_KEY_MAX))
+
+/** @defgroup  EF_CTRL_SIGN_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_SIGN_TYPE(type) (((type) == EF_CTRL_SIGN_NONE) || ((type) == EF_CTRL_SIGN_RSA) || ((type) == EF_CTRL_SIGN_ECC))
+
+/** @defgroup  EF_CTRL_SF_AES_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_SF_AES_TYPE(type) (((type) == EF_CTRL_SF_AES_NONE) || ((type) == EF_CTRL_SF_AES_128) || ((type) == EF_CTRL_SF_AES_192) || ((type) == EF_CTRL_SF_AES_256))
+
+/** @defgroup  EF_CTRL_DBG_MODE_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_DBG_MODE_TYPE(type) (((type) == EF_CTRL_DBG_OPEN) || ((type) == EF_CTRL_DBG_PASSWORD) || ((type) == EF_CTRL_DBG_CLOSE))
+
+/** @defgroup  EF_CTRL_CLK_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_CLK_TYPE(type) (((type) == EF_CTRL_EF_CLK) || ((type) == EF_CTRL_SAHB_CLK))
+
+/** @defgroup  EF_CTRL_CYC_PARA_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_CYC_PARA_TYPE(type) (((type) == EF_CTRL_PARA_DFT) || ((type) == EF_CTRL_PARA_MANUAL))
+
+/** @defgroup  EF_CTRL_OP_MODE_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_OP_MODE_TYPE(type) (((type) == EF_CTRL_OP_MODE_AUTO) || ((type) == EF_CTRL_OP_MODE_MANUAL))
+
+/*@} end of group EF_CTRL_Public_Constants */
+
+/** @defgroup  EF_CTRL_Public_Macros
+ *  @{
+ */
+#define EF_CTRL_EFUSE_R0_SIZE 128
+
+/*@} end of group EF_CTRL_Public_Macros */
+
+/** @defgroup  EF_CTRL_Public_Functions
+ *  @{
+ */
+void        EF_Ctrl_Load_Efuse_R0(void);
+BL_Sts_Type EF_Ctrl_Busy(void);
+BL_Sts_Type EF_Ctrl_AutoLoad_Done(void);
+void        EF_Ctrl_Write_Dbg_Pwd(uint32_t passWdLow, uint32_t passWdHigh, uint8_t program);
+void        EF_Ctrl_Read_Dbg_Pwd(uint32_t *passWdLow, uint32_t *passWdHigh);
+void        EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program);
+void        EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program);
+void        EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg, uint8_t program);
+void        EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg);
+void        EF_Ctrl_Write_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1], uint8_t program);
+void        EF_Ctrl_Read_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1]);
+void        EF_Ctrl_Read_CPU_Cfg(uint8_t *apDisabled, uint8_t *npDisabled, uint8_t *npCpuType);
+uint8_t     EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len);
+void        EF_Ctrl_Write_Ana_Trim(uint32_t index, uint32_t trim, uint8_t program);
+void        EF_Ctrl_Read_Ana_Trim(uint32_t index, uint32_t *trim);
+void        EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim);
+void        EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim);
+void        EF_Ctrl_Read_TSEN_Trim(Efuse_TSEN_Refcode_Corner_Type *trim);
+void        EF_Ctrl_Read_ADC_Gain_Trim(Efuse_ADC_Gain_Coeff_Type *trim);
+void        EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage, uint8_t program);
+void        EF_Ctrl_Read_Sw_Usage(uint32_t index, uint32_t *usage);
+void        EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program);
+void        EF_Ctrl_Write_MAC_Address(uint8_t mac[6], uint8_t program);
+BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[8]);
+BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7]);
+void        EF_Ctrl_Writelock_MAC_Address(uint8_t program);
+uint8_t     EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload);
+BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[8], uint8_t program);
+BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[8], uint8_t reload);
+BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t id[8]);
+/*----------*/
+BL_Err_Type EF_Ctrl_Get_Chip_PIDVID(uint16_t pid[1], uint16_t vid[1]);
+uint32_t    EF_Ctrl_Get_Key_Slot_w0();
+uint32_t    EF_Ctrl_Get_Key_Slot_w1();
+BL_Err_Type EF_Ctrl_Get_Customer_PIDVID(uint16_t pid[1], uint16_t vid[1]);
+/*----------*/
+void        EF_Ctrl_Read_Device_Info(Efuse_Device_Info_Type *deviceInfo);
+uint8_t     EF_Ctrl_Is_CapCode_Empty(uint8_t slot, uint8_t reload);
+BL_Err_Type EF_Ctrl_Write_CapCode_Opt(uint8_t slot, uint8_t code, uint8_t program);
+BL_Err_Type EF_Ctrl_Read_CapCode_Opt(uint8_t slot, uint8_t *code, uint8_t reload);
+uint8_t     EF_Ctrl_Is_PowerOffset_Slot_Empty(uint8_t slot, uint8_t reload);
+BL_Err_Type EF_Ctrl_Write_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[2], uint8_t program);
+BL_Err_Type EF_Ctrl_Read_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[2], uint8_t reload);
+void        EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program);
+void        EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len);
+void        EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program);
+void        EF_Ctrl_Readlock_AES_Key(uint8_t index, uint8_t program);
+void        EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len);
+void        EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len);
+void        EF_Ctrl_Program_Direct(uint32_t index, uint32_t *data, uint32_t len);
+void        EF_Ctrl_Read_Direct(uint32_t index, uint32_t *data, uint32_t len);
+void        EF_Ctrl_Clear(uint32_t index, uint32_t len);
+void        EF_Ctrl_Crc_Enable(void);
+BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void);
+void        EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue);
+BL_Err_Type EF_Ctrl_Crc_Result(void);
+void        EF_Ctrl_Sw_AHB_Clk_0(void);
+
+/*@} end of group EF_CTRL_Public_Functions */
+
+/*@} end of group EF_CTRL */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_EF_CTRL_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_emac.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_emac.h
new file mode 100644
index 00000000..20a60b82
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_emac.h
@@ -0,0 +1,306 @@
+/**
+  ******************************************************************************
+  * @file    bl702_emac.h
+  * @version V1.2
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2018 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_EMAC_H__
+#define __BL702_EMAC_H__
+
+#include "emac_reg.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  EMAC
+ *  @{
+ */
+
+/** @defgroup  EMAC_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief EMAC half/full-duplex type definition
+ */
+typedef enum {
+    EMAC_MODE_HALFDUPLEX, /*!< ETH half-duplex */
+    EMAC_MODE_FULLDUPLEX, /*!< ETH full-duplex */
+} EMAC_Duplex_Type;
+
+/**
+ *  @brief EMAC speed type definition
+ */
+typedef enum {
+    EMAC_SPEED_10M,  /*!< ETH speed 10M */
+    EMAC_SPEED_100M, /*!< ETH speed 100M */
+} EMAC_Speed_Type;
+
+/**
+ *  @brief EMAC interrupt type definition
+ */
+typedef enum {
+    EMAC_INT_TX_DONE = 0x01,  /*!< Transmit one frame done */
+    EMAC_INT_TX_ERROR = 0x02, /*!< Transmit error occur */
+    EMAC_INT_RX_DONE = 0x04,  /*!< Receive one frame done */
+    EMAC_INT_RX_ERROR = 0x08, /*!< Receive error occur */
+    EMAC_INT_RX_BUSY = 0x10,  /*!< Receive busy due to no free RX buffer Descripter */
+    EMAC_INT_TX_CTRL = 0x20,  /*!< Transmit control frame */
+    EMAC_INT_RX_CTRL = 0x40,  /*!< Receive control frame */
+    EMAC_INT_ALL = 0x7F,      /*!<  */
+} EMAC_INT_Type;
+
+/**
+ *  @brief EMAC interrupt Index
+ */
+typedef enum {
+    EMAC_INT_TX_DONE_IDX = 0x0,  /*!< Transmit one frame done */
+    EMAC_INT_TX_ERROR_IDX = 0x1, /*!< Transmit error occur */
+    EMAC_INT_RX_DONE_IDX = 0x2,  /*!< Receive one frame done */
+    EMAC_INT_RX_ERROR_IDX = 0x3, /*!< Receive error occur */
+    EMAC_INT_RX_BUSY_IDX = 0x4,  /*!< Receive busy due to no free RX buffer Descripter */
+    EMAC_INT_TX_CTRL_IDX = 0x5,  /*!< Transmit control frame */
+    EMAC_INT_RX_CTRL_IDX = 0x6,  /*!< Receive control frame */
+    EMAC_INT_CNT,                /*!< EMAC INT source count */
+} EMAC_INT_Index;
+
+/**
+ *  @brief EMAC configuration type definition
+ */
+typedef struct
+{
+    BL_Fun_Type recvSmallFrame;     /*!< Receive small frmae or not */
+    BL_Fun_Type recvHugeFrame;      /*!< Receive huge frmae(>64K bytes) or not */
+    BL_Fun_Type padEnable;          /*!< Enable padding for frame which is less than MINFL or not */
+    BL_Fun_Type crcEnable;          /*!< Enable hardware CRC or not */
+    BL_Fun_Type noPreamble;         /*!< Enable preamble or not */
+    BL_Fun_Type recvBroadCast;      /*!< Receive broadcast frame or not */
+    BL_Fun_Type interFrameGapCheck; /*!< Check inter frame gap or not */
+    BL_Fun_Type miiNoPreamble;      /*!< Enable MII interface preamble or not */
+    uint8_t miiClkDiv;              /*!< MII interface clock divider from bus clock */
+    uint8_t maxTxRetry;             /*!< Maximum tx retry count */
+    uint16_t interFrameGapValue;    /*!< Inter frame gap vaule in clock cycles(default 24),which equals 9.6 us for 10 Mbps and 0.96 us
+                                                 for 100 Mbps mode */
+    uint16_t minFrameLen;           /*!< Minimum frame length */
+    uint16_t maxFrameLen;           /*!< Maximum frame length */
+    uint16_t collisionValid;        /*!< Collision valid value */
+    uint8_t macAddr[6];             /*!< MAC Address */
+} EMAC_CFG_Type;
+
+/**
+ *  @brief EMAC TX DMA description type definition
+ */
+/**
+ * Note: Always write DWORD1 (buffer addr) first then DWORD0 for racing concern.
+ */
+typedef struct
+{
+    uint32_t C_S_L;  /*!< Buffer Descriptors(BD) control,status,length */
+    uint32_t Buffer; /*!< BD buffer address */
+} EMAC_BD_Desc_Type;
+
+/**
+ *  @brief EMAC Handle type definition
+ */
+typedef struct
+{
+    EMAC_BD_Desc_Type *bd; /*!< Tx descriptor header pointer */
+    uint8_t txIndexEMAC;   /*!< TX index: EMAC */
+    uint8_t txIndexCPU;    /*!< TX index: CPU/SW */
+    uint8_t txBuffLimit;   /*!< TX index max */
+    uint8_t rsv0;
+    uint8_t rxIndexEMAC; /*!< RX index: EMAC */
+    uint8_t rxIndexCPU;  /*!< RX index: CPU/SW */
+    uint8_t rxBuffLimit; /*!< RX index max */
+    uint8_t rsv1;
+} EMAC_Handle_Type;
+
+/*@} end of group EMAC_Public_Types */
+
+/** @defgroup  EMAC_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  EMAC_DUPLEX_TYPE
+ *  @{
+ */
+#define IS_EMAC_DUPLEX_TYPE(type) (((type) == EMAC_MODE_HALFDUPLEX) || \
+                                   ((type) == EMAC_MODE_FULLDUPLEX))
+
+/** @defgroup  EMAC_SPEED_TYPE
+ *  @{
+ */
+#define IS_EMAC_SPEED_TYPE(type) (((type) == EMAC_SPEED_10M) || \
+                                  ((type) == EMAC_SPEED_100M))
+
+/** @defgroup  EMAC_INT_TYPE
+ *  @{
+ */
+#define IS_EMAC_INT_TYPE(type) (((type) == EMAC_INT_TX_DONE) ||  \
+                                ((type) == EMAC_INT_TX_ERROR) || \
+                                ((type) == EMAC_INT_RX_DONE) ||  \
+                                ((type) == EMAC_INT_RX_ERROR) || \
+                                ((type) == EMAC_INT_RX_BUSY) ||  \
+                                ((type) == EMAC_INT_TX_CTRL) ||  \
+                                ((type) == EMAC_INT_RX_CTRL) ||  \
+                                ((type) == EMAC_INT_ALL))
+
+/** @defgroup  EMAC_INT_INDEX
+ *  @{
+ */
+#define IS_EMAC_INT_INDEX(type) (((type) == EMAC_INT_TX_DONE_IDX) ||  \
+                                 ((type) == EMAC_INT_TX_ERROR_IDX) || \
+                                 ((type) == EMAC_INT_RX_DONE_IDX) ||  \
+                                 ((type) == EMAC_INT_RX_ERROR_IDX) || \
+                                 ((type) == EMAC_INT_RX_BUSY_IDX) ||  \
+                                 ((type) == EMAC_INT_TX_CTRL_IDX) ||  \
+                                 ((type) == EMAC_INT_RX_CTRL_IDX) ||  \
+                                 ((type) == EMAC_INT_CNT))
+
+/*@} end of group EMAC_Public_Constants */
+
+/** @defgroup  EMAC_Public_Macros
+ *  @{
+ */
+#define BD_TX_CS_POS   (0) /*!< Carrier Sense Lost */
+#define BD_TX_CS_LEN   (1)
+#define BD_TX_DF_POS   (1) /*!< Defer Indication */
+#define BD_TX_DF_LEN   (1)
+#define BD_TX_LC_POS   (2) /*!< Late Collision */
+#define BD_TX_LC_LEN   (1)
+#define BD_TX_RL_POS   (3) /*!< Retransmission Limit */
+#define BD_TX_RL_LEN   (1)
+#define BD_TX_RTRY_POS (4) /*!< Retry Count */
+#define BD_TX_RTRY_LEN (4)
+#define BD_TX_UR_POS   (8) /*!< Underrun */
+#define BD_TX_UR_LEN   (1)
+#define BD_TX_EOF_POS  (10) /*!< EOF */
+#define BD_TX_EOF_LEN  (1)
+#define BD_TX_CRC_POS  (11) /*!< CRC Enable */
+#define BD_TX_CRC_LEN  (1)
+#define BD_TX_PAD_POS  (12) /*!< PAD enable */
+#define BD_TX_PAD_LEN  (1)
+#define BD_TX_WR_POS   (13) /*!< Wrap */
+#define BD_TX_WR_LEN   (1)
+#define BD_TX_IRQ_POS  (14) /*!< Interrupt Request Enable */
+#define BD_TX_IRQ_LEN  (1)
+#define BD_TX_RD_POS   (15) /*!< The data buffer is ready for transmission or is currently being transmitted. You are not allowed to change it */
+#define BD_TX_RD_LEN   (1)
+#define BD_TX_LEN_POS  (16) /*!< TX Data buffer length */
+#define BD_TX_LEN_LEN  (16)
+
+#define BD_RX_LC_POS  (0) /*!< Late Collision */
+#define BD_RX_LC_LEN  (1)
+#define BD_RX_CRC_POS (1) /*!< RX CRC Error */
+#define BD_RX_CRC_LEN (1)
+#define BD_RX_SF_POS  (2) /*!< Short Frame */
+#define BD_RX_SF_LEN  (1)
+#define BD_RX_TL_POS  (3) /*!< Too Long */
+#define BD_RX_TL_LEN  (1)
+#define BD_RX_DN_POS  (4) /*!< Dribble Nibble */
+#define BD_RX_DN_LEN  (1)
+#define BD_RX_RE_POS  (5) /*!< Receive Error */
+#define BD_RX_RE_LEN  (1)
+#define BD_RX_OR_POS  (6) /*!< Overrun */
+#define BD_RX_OR_LEN  (1)
+#define BD_RX_M_POS   (7) /*!< Miss */
+#define BD_RX_M_LEN   (1)
+#define BD_RX_CF_POS  (8) /*!< Control Frame Received */
+#define BD_RX_CF_LEN  (1)
+#define BD_RX_WR_POS  (13) /*!< Wrap */
+#define BD_RX_WR_LEN  (1)
+#define BD_RX_IRQ_POS (14) /*!< Interrupt Request Enable */
+#define BD_RX_IRQ_LEN (1)
+#define BD_RX_E_POS   (15) /*!< The data buffer is empty (and ready for receiving data) or currently receiving data */
+#define BD_RX_E_LEN   (1)
+#define BD_RX_LEN_POS (16) /*!< RX Data buffer length */
+#define BD_RX_LEN_LEN (16)
+
+#define EMAC_BD_FIELD_MSK(field)  (((1U << BD_##field##_LEN) - 1) << BD_##field##_POS)
+#define EMAC_BD_FIELD_UMSK(field) (~(((1U << BD_##field##_LEN) - 1) << BD_##field##_POS))
+/* DMA Descriptor offset */
+#define EMAC_DMA_DESC_OFFSET 0x400
+
+/* ETH packet size */
+// ETH     | Header | Extra | VLAN tag | Payload   | CRC |
+// Size    | 14     | 2     | 4        | 46 ~ 1500 | 4   |
+#define ETH_MAX_PACKET_SIZE          ((uint32_t)1524U) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER_SZIE              ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define ETH_CRC_SIZE                 ((uint32_t)4U) /*!< Ethernet CRC */
+#define ETH_EXTRA_SIZE               ((uint32_t)2U) /*!< Extra bytes in some cases */
+#define ETH_VLAN_TAG_SIZE            ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */
+#define ETH_MIN_ETH_PAYLOAD_SIZE     ((uint32_t)46U) /*!< Minimum Ethernet payload size */
+#define ETH_MAX_ETH_PAYLOAD_SIZE     ((uint32_t)1500U) /*!< Maximum Ethernet payload size */
+#define ETH_JUMBO_FRAME_PAYLOAD_SIZE ((uint32_t)9000U) /*!< Jumbo frame payload size */
+
+/*@} end of group EMAC_Public_Macros */
+
+/** @defgroup  EMAC_Public_Functions
+ *  @{
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+void EMAC_IRQHandler(void);
+#endif
+BL_Err_Type EMAC_Init(EMAC_CFG_Type *cfg);
+BL_Err_Type EMAC_DeInit(void);
+BL_Err_Type EMAC_DMADescListInit(EMAC_Handle_Type *handle, uint8_t *txBuff, uint32_t txBuffCount,
+                                 uint8_t *rxBuff, uint32_t rxBuffCount);
+BL_Err_Type EMAC_DMATxDescGet(EMAC_Handle_Type *handle, EMAC_BD_Desc_Type **txDMADesc);
+BL_Err_Type EMAC_StartTx(EMAC_Handle_Type *handle, EMAC_BD_Desc_Type *txDMADesc, uint32_t len);
+BL_Err_Type EMAC_Enable(void);
+BL_Err_Type EMAC_Disable(void);
+BL_Err_Type EMAC_IntMask(EMAC_INT_Type intType, BL_Mask_Type intMask);
+BL_Sts_Type EMAC_GetIntStatus(EMAC_INT_Type intType);
+BL_Err_Type EMAC_ClrIntStatus(EMAC_INT_Type intType);
+BL_Err_Type EMAC_Int_Callback_Install(EMAC_INT_Index intIdx, intCallback_Type *cbFun);
+BL_Err_Type EMAC_TxPauseReq(uint16_t timeCount);
+BL_Err_Type EMAC_SetHash(uint32_t hash0, uint32_t hash1);
+BL_Err_Type EMAC_Phy_Read(uint16_t phyReg, uint16_t *regValue);
+BL_Err_Type EMAC_Phy_Write(uint16_t phyReg, uint16_t regValue);
+
+BL_Err_Type EMAC_Enable_TX(void);
+BL_Err_Type EMAC_Disable_TX(void);
+BL_Err_Type EMAC_Enable_RX(void);
+BL_Err_Type EMAC_Disable_RX(void);
+
+void EMAC_Phy_SetAddress(uint16_t phyAddress);
+void EMAC_Phy_Set_Full_Duplex(uint8_t fullDuplex);
+
+/*@} end of group EMAC_Public_Functions */
+
+/*@} end of group EMAC */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_EMAC_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_glb.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_glb.h
new file mode 100644
index 00000000..98bf43d7
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_glb.h
@@ -0,0 +1,822 @@
+/**
+  ******************************************************************************
+  * @file    bl702_glb.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_GLB_H__
+#define __BL702_GLB_H__
+
+#include "glb_reg.h"
+#include "pds_reg.h"
+#include "bl702_gpio.h"
+#include "bl702_l1c.h"
+#include "bl702_hbn.h"
+#include "bl702_sf_ctrl.h"
+#include "bl702_sf_cfg.h"
+#include "bl702_aon.h"
+#include "bl702_ef_ctrl.h"
+#include "bl702_pds.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  GLB
+ *  @{
+ */
+
+/** @defgroup  GLB_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief GLB root clock type definition
+ */
+typedef enum {
+    GLB_ROOT_CLK_RC32M, /*!< root clock select RC32M */
+    GLB_ROOT_CLK_XTAL,  /*!< root clock select XTAL */
+    GLB_ROOT_CLK_DLL,   /*!< root clock select DLL others, PLL120M not recommend */
+} GLB_ROOT_CLK_Type;
+
+/**
+ *  @brief GLB system clock type definition
+ */
+typedef enum {
+    GLB_SYS_CLK_RC32M,    /*!< use RC32M as system clock frequency */
+    GLB_SYS_CLK_XTAL,     /*!< use XTAL as system clock */
+    GLB_SYS_CLK_DLL57P6M, /*!< use DLL output 57.6M as system clock */
+    GLB_SYS_CLK_DLL96M,   /*!< use DLL output 96M as system clock */
+    GLB_SYS_CLK_DLL144M,  /*!< use DLL output 144M as system clock, PLL120M not recommend */
+} GLB_SYS_CLK_Type;
+
+/**
+ *  @brief GLB CAM clock type definition
+ */
+typedef enum {
+    GLB_CAM_CLK_XCLK,   /*!< Select XCLK as CAM clock */
+    GLB_CAM_CLK_DLL96M, /*!< Select DLL96M as CAM clock */
+} GLB_CAM_CLK_Type;
+
+/**
+ *  @brief GLB I2S output ref clock type definition
+ */
+typedef enum {
+    GLB_I2S_OUT_REF_CLK_NONE, /*!< no output reference clock on I2S_0 ref_clock port */
+    GLB_I2S_OUT_REF_CLK_SRC,  /*!< output reference clock on I2S_0 ref_clock port */
+} GLB_I2S_OUT_REF_CLK_Type;
+
+/**
+ *  @brief GLB qdec clock type definition
+ */
+typedef enum {
+    GLB_QDEC_CLK_XCLK, /*!< Select XCLK as QDEC clock */
+    GLB_QDEC_CLK_F32K, /*!< Select f32k as QDEC clock (PDS mode) */
+} GLB_QDEC_CLK_Type;
+
+/**
+ *  @brief GLB DMA clock ID type definition
+ */
+typedef enum {
+    GLB_DMA_CLK_DMA0_CH0, /*!< DMA clock ID:channel 0 */
+    GLB_DMA_CLK_DMA0_CH1, /*!< DMA clock ID:channel 1 */
+    GLB_DMA_CLK_DMA0_CH2, /*!< DMA clock ID:channel 2 */
+    GLB_DMA_CLK_DMA0_CH3, /*!< DMA clock ID:channel 3 */
+    GLB_DMA_CLK_DMA0_CH4, /*!< DMA clock ID:channel 4 */
+    GLB_DMA_CLK_DMA0_CH5, /*!< DMA clock ID:channel 5 */
+    GLB_DMA_CLK_DMA0_CH6, /*!< DMA clock ID:channel 6 */
+    GLB_DMA_CLK_DMA0_CH7, /*!< DMA clock ID:channel 7 */
+} GLB_DMA_CLK_ID_Type;
+
+/**
+ *  @brief GLB clock source type definition
+ */
+typedef enum {
+    GLB_IR_CLK_SRC_XCLK, /*!< IR clock source select XCLK */
+} GLB_IR_CLK_SRC_Type;
+
+/**
+ *  @brief GLB flash clock type definition
+ */
+typedef enum {
+    GLB_SFLASH_CLK_144M,  /*!< Select 144M as flash clock */
+    GLB_SFLASH_CLK_XCLK,  /*!< Select XCLK as flash clock */
+    GLB_SFLASH_CLK_57P6M, /*!< Select 57.6M as flash clock */
+    GLB_SFLASH_CLK_72M,   /*!< Select 72M as flash clock */
+    GLB_SFLASH_CLK_BCLK,  /*!< Select BCLK as flash clock */
+    GLB_SFLASH_CLK_96M,   /*!< Select 96M as flash clock */
+} GLB_SFLASH_CLK_Type;
+
+/**
+ *  @brief GLB chip clock out type definition
+ */
+typedef enum {
+    GLB_CHIP_CLK_OUT_NONE,          /*!< no chip clock out */
+    GLB_CHIP_CLK_OUT_I2S_REF_CLK,   /*!< i2s_ref_clk out */
+    GLB_CHIP_CLK_OUT_AUDIO_PLL_CLK, /*!< audio_pll_clk out */
+    GLB_CHIP_CLK_OUT_XTAL_SOC_32M,  /*!< clk_xtal_soc_32M */
+} GLB_CHIP_CLK_OUT_Type;
+
+/**
+ *  @brief GLB eth ref clock out type definition
+ */
+typedef enum {
+    GLB_ETH_REF_CLK_OUT_OUTSIDE_50M, /*!< select outside 50MHz RMII ref clock */
+    GLB_ETH_REF_CLK_OUT_INSIDE_50M,  /*!< select inside 50MHz RMII ref clock */
+} GLB_ETH_REF_CLK_OUT_Type;
+
+/**
+ *  @brief GLB SPI pad action type definition
+ */
+typedef enum {
+    GLB_SPI_PAD_ACT_AS_SLAVE,  /*!< SPI pad act as slave */
+    GLB_SPI_PAD_ACT_AS_MASTER, /*!< SPI pad act as master */
+} GLB_SPI_PAD_ACT_AS_Type;
+
+/**
+ *  @brief GLB PKA clock type definition
+ */
+typedef enum {
+    GLB_PKA_CLK_HCLK,   /*!< Select HCLK as PKA clock */
+    GLB_PKA_CLK_DLL96M, /*!< Select DLL 96M as PKA clock */
+} GLB_PKA_CLK_Type;
+
+/**
+ *  @brief BMX arb mode type definition
+ */
+typedef enum {
+    BMX_ARB_FIX,         /*!< 0->fix */
+    BMX_ARB_ROUND_ROBIN, /*!< 2->round-robin */
+    BMX_ARB_RANDOM,      /*!< 3->random */
+} BMX_ARB_Type;
+
+/**
+ *  @brief BMX configuration structure type definition
+ */
+typedef struct {
+    uint8_t timeoutEn;   /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */
+    BL_Fun_Type errEn;   /*!< Bus error response enable */
+    BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */
+} BMX_Cfg_Type;
+
+/**
+ *  @brief BMX bus err type definition
+ */
+typedef enum {
+    BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */
+    BMX_BUS_ERR_ADDR_DECODE,      /*!< Bus addr decode error */
+} BMX_BUS_ERR_Type;
+
+/**
+ *  @brief BMX bus err interrupt type definition
+ */
+typedef enum {
+    BMX_ERR_INT_ERR, /*!< BMX bus err interrupt */
+    BMX_ERR_INT_ALL, /*!< BMX bus err interrupt max num */
+} BMX_ERR_INT_Type;
+
+/**
+ *  @brief BMX time out interrupt type definition
+ */
+typedef enum {
+    BMX_TO_INT_TIMEOUT, /*!< BMX timeout interrupt */
+    BMX_TO_INT_ALL,     /*!< BMX timeout interrupt max num */
+} BMX_TO_INT_Type;
+
+/**
+ *  @brief GLB EM type definition
+ */
+typedef enum {
+    GLB_EM_0KB = 0x0,  /*!< 0x0 --> 0KB */
+    GLB_EM_8KB = 0x3,  /*!< 0x3 --> 8KB */
+    GLB_EM_16KB = 0xF, /*!< 0xF --> 16KB */
+} GLB_EM_Type;
+
+/**
+ *  @brief GLB EMAC and CAM pin type definition
+ */
+typedef enum {
+    GLB_EMAC_CAM_PIN_EMAC, /*!< select pin as emac */
+    GLB_EMAC_CAM_PIN_CAM,  /*!< select pin as cam */
+} GLB_EMAC_CAM_PIN_Type;
+
+/**
+ *  @brief GLB RTC clock type definition
+ */
+typedef enum {
+    GLB_MTIMER_CLK_BCLK, /*!< BUS clock */
+    GLB_MTIMER_CLK_32K,  /*!< 32KHz */
+} GLB_MTIMER_CLK_Type;
+
+/**
+ *  @brief GLB ADC clock type definition
+ */
+typedef enum {
+    GLB_ADC_CLK_AUDIO_PLL, /*!< use Audio PLL as ADC clock */
+    GLB_ADC_CLK_XCLK,      /*!< use XCLK as ADC clock */
+} GLB_ADC_CLK_Type;
+
+/**
+ *  @brief GLB DAC clock type definition
+ */
+typedef enum {
+    GLB_DAC_CLK_PLL_32M,   /*!< select PLL 32M as DAC clock source */
+    GLB_DAC_CLK_XCLK,      /*!< select XCLK as DAC clock source */
+    GLB_DAC_CLK_AUDIO_PLL, /*!< select Audio PLL as DAC clock source */
+} GLB_DAC_CLK_Type;
+
+/**
+ *  @brief GLB DIG clock source select type definition
+ */
+typedef enum {
+    GLB_DIG_CLK_PLL_32M,   /*!< select PLL 32M as DIG clock source */
+    GLB_DIG_CLK_XCLK,      /*!< select XCLK as DIG clock source */
+    GLB_DIG_CLK_AUDIO_PLL, /*!< select Audio PLL as DIG clock source */
+} GLB_DIG_CLK_Type;
+
+/**
+ *  @brief GLB BT bandwidth type definition
+ */
+typedef enum {
+    GLB_BT_BANDWIDTH_1M, /*!< BT bandwidth 1MHz */
+    GLB_BT_BANDWIDTH_2M, /*!< BT bandwidth 2MHz */
+} GLB_BT_BANDWIDTH_Type;
+
+/**
+ *  @brief GLB UART signal type definition
+ */
+typedef enum {
+    GLB_UART_SIG_0, /*!< UART signal 0 */
+    GLB_UART_SIG_1, /*!< UART signal 1 */
+    GLB_UART_SIG_2, /*!< UART signal 2 */
+    GLB_UART_SIG_3, /*!< UART signal 3 */
+    GLB_UART_SIG_4, /*!< UART signal 4 */
+    GLB_UART_SIG_5, /*!< UART signal 5 */
+    GLB_UART_SIG_6, /*!< UART signal 6 */
+    GLB_UART_SIG_7, /*!< UART signal 7 */
+} GLB_UART_SIG_Type;
+
+/**
+ *  @brief GLB UART signal  function type definition
+ */
+typedef enum {
+    GLB_UART_SIG_FUN_UART0_RTS, /*!< UART funtion: UART 0 RTS */
+    GLB_UART_SIG_FUN_UART0_CTS, /*!< UART funtion: UART 0 CTS */
+    GLB_UART_SIG_FUN_UART0_TXD, /*!< UART funtion: UART 0 TXD */
+    GLB_UART_SIG_FUN_UART0_RXD, /*!< UART funtion: UART 0 RXD */
+    GLB_UART_SIG_FUN_UART1_RTS, /*!< UART funtion: UART 1 RTS */
+    GLB_UART_SIG_FUN_UART1_CTS, /*!< UART funtion: UART 1 CTS */
+    GLB_UART_SIG_FUN_UART1_TXD, /*!< UART funtion: UART 1 TXD */
+    GLB_UART_SIG_FUN_UART1_RXD, /*!< UART funtion: UART 1 RXD */
+} GLB_UART_SIG_FUN_Type;
+
+/**
+ *  @brief GLB DLL output clock type definition
+ */
+typedef enum {
+    GLB_DLL_CLK_57P6M, /*!< DLL output 57P6M clock */
+    GLB_DLL_CLK_96M,   /*!< DLL output 96M clock */
+    GLB_DLL_CLK_144M,  /*!< DLL output 144M clock */
+    GLB_DLL_CLK_288M,  /*!< DLL output 288M clock */
+    GLB_DLL_CLK_MMDIV, /*!< DLL output mmdiv clock */
+} GLB_DLL_CLK_Type;
+
+/**
+ *  @brief GLB GPIO interrupt trigger mode type definition
+ */
+typedef enum {
+    GLB_GPIO_INT_TRIG_NEG_PULSE, /*!< GPIO negedge pulse trigger interrupt */
+    GLB_GPIO_INT_TRIG_POS_PULSE, /*!< GPIO posedge pulse trigger interrupt */
+    GLB_GPIO_INT_TRIG_NEG_LEVEL, /*!< GPIO negedge level trigger interrupt (32k 3T) */
+    GLB_GPIO_INT_TRIG_POS_LEVEL, /*!< GPIO posedge level trigger interrupt (32k 3T) */
+} GLB_GPIO_INT_TRIG_Type;
+
+/**
+ *  @brief GLB GPIO interrupt control mode type definition
+ */
+typedef enum {
+    GLB_GPIO_INT_CONTROL_SYNC,  /*!< GPIO interrupt sync mode */
+    GLB_GPIO_INT_CONTROL_ASYNC, /*!< GPIO interrupt async mode */
+} GLB_GPIO_INT_CONTROL_Type;
+
+/**
+ *  @brief PLL XTAL type definition
+ */
+typedef enum {
+    GLB_DLL_XTAL_NONE,  /*!< XTAL is none */
+    GLB_DLL_XTAL_32M,   /*!< XTAL is 32M */
+    GLB_DLL_XTAL_RC32M, /*!< XTAL is RC32M */
+} GLB_DLL_XTAL_Type;
+
+typedef enum {
+    GLB_AHB_CLOCK_IP_CPU,
+    GLB_AHB_CLOCK_IP_SDU,
+    GLB_AHB_CLOCK_IP_SEC,
+    GLB_AHB_CLOCK_IP_DMA_0,
+    GLB_AHB_CLOCK_IP_DMA_1,
+    GLB_AHB_CLOCK_IP_DMA_2,
+    GLB_AHB_CLOCK_IP_CCI,
+    GLB_AHB_CLOCK_IP_RF_TOP,
+    GLB_AHB_CLOCK_IP_GPIP,
+    GLB_AHB_CLOCK_IP_TZC,
+    GLB_AHB_CLOCK_IP_EF_CTRL,
+    GLB_AHB_CLOCK_IP_SF_CTRL,
+    GLB_AHB_CLOCK_IP_EMAC,
+    GLB_AHB_CLOCK_IP_UART0,
+    GLB_AHB_CLOCK_IP_UART1,
+    GLB_AHB_CLOCK_IP_UART2,
+    GLB_AHB_CLOCK_IP_UART3,
+    GLB_AHB_CLOCK_IP_UART4,
+    GLB_AHB_CLOCK_IP_SPI,
+    GLB_AHB_CLOCK_IP_I2C,
+    GLB_AHB_CLOCK_IP_PWM,
+    GLB_AHB_CLOCK_IP_TIMER,
+    GLB_AHB_CLOCK_IP_IR,
+    GLB_AHB_CLOCK_IP_CHECKSUM,
+    GLB_AHB_CLOCK_IP_QDEC,
+    GLB_AHB_CLOCK_IP_KYS,
+    GLB_AHB_CLOCK_IP_I2S,
+    GLB_AHB_CLOCK_IP_USB11,
+    GLB_AHB_CLOCK_IP_CAM,
+    GLB_AHB_CLOCK_IP_MJPEG,
+    GLB_AHB_CLOCK_IP_BT_BLE_NORMAL,
+    GLB_AHB_CLOCK_IP_BT_BLE_LP,
+    GLB_AHB_CLOCK_IP_ZB_NORMAL,
+    GLB_AHB_CLOCK_IP_ZB_LP,
+    GLB_AHB_CLOCK_IP_WIFI_NORMAL,
+    GLB_AHB_CLOCK_IP_WIFI_LP,
+    GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL,
+    GLB_AHB_CLOCK_IP_BT_BLE_2_LP,
+    GLB_AHB_CLOCK_IP_EMI_MISC,
+    GLB_AHB_CLOCK_IP_PSRAM0_CTRL,
+    GLB_AHB_CLOCK_IP_PSRAM1_CTRL,
+    GLB_AHB_CLOCK_IP_USB20,
+    GLB_AHB_CLOCK_IP_MIX2,
+    GLB_AHB_CLOCK_IP_AUDIO,
+    GLB_AHB_CLOCK_IP_SDH,
+} GLB_AHB_CLOCK_IP_Type;
+
+/*@} end of group GLB_Public_Types */
+
+/** @defgroup  GLB_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  GLB_ROOT_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_ROOT_CLK_TYPE(type) (((type) == GLB_ROOT_CLK_RC32M) || \
+                                    ((type) == GLB_ROOT_CLK_XTAL) ||  \
+                                    ((type) == GLB_ROOT_CLK_DLL))
+
+/** @defgroup  GLB_SYS_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_SYS_CLK_TYPE(type) (((type) == GLB_SYS_CLK_RC32M) ||    \
+                                   ((type) == GLB_SYS_CLK_XTAL) ||     \
+                                   ((type) == GLB_SYS_CLK_DLL57P6M) || \
+                                   ((type) == GLB_SYS_CLK_DLL96M) ||   \
+                                   ((type) == GLB_SYS_CLK_DLL144M))
+
+/** @defgroup  GLB_CAM_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_CAM_CLK_TYPE(type) (((type) == GLB_CAM_CLK_XCLK) || \
+                                   ((type) == GLB_CAM_CLK_DLL96M))
+
+/** @defgroup  GLB_I2S_OUT_REF_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_I2S_OUT_REF_CLK_TYPE(type) (((type) == GLB_I2S_OUT_REF_CLK_NONE) || \
+                                           ((type) == GLB_I2S_OUT_REF_CLK_SRC))
+
+/** @defgroup  GLB_QDEC_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_QDEC_CLK_TYPE(type) (((type) == GLB_QDEC_CLK_XCLK) || \
+                                    ((type) == GLB_QDEC_CLK_F32K))
+
+/** @defgroup  GLB_DMA_CLK_ID_TYPE
+ *  @{
+ */
+#define IS_GLB_DMA_CLK_ID_TYPE(type) (((type) == GLB_DMA_CLK_DMA0_CH0) || \
+                                      ((type) == GLB_DMA_CLK_DMA0_CH1) || \
+                                      ((type) == GLB_DMA_CLK_DMA0_CH2) || \
+                                      ((type) == GLB_DMA_CLK_DMA0_CH3) || \
+                                      ((type) == GLB_DMA_CLK_DMA0_CH4) || \
+                                      ((type) == GLB_DMA_CLK_DMA0_CH5) || \
+                                      ((type) == GLB_DMA_CLK_DMA0_CH6) || \
+                                      ((type) == GLB_DMA_CLK_DMA0_CH7))
+
+/** @defgroup  GLB_IR_CLK_SRC_TYPE
+ *  @{
+ */
+#define IS_GLB_IR_CLK_SRC_TYPE(type) (((type) == GLB_IR_CLK_SRC_XCLK))
+
+/** @defgroup  GLB_SFLASH_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_SFLASH_CLK_TYPE(type) (((type) == GLB_SFLASH_CLK_144M) ||  \
+                                      ((type) == GLB_SFLASH_CLK_XCLK) ||  \
+                                      ((type) == GLB_SFLASH_CLK_57P6M) || \
+                                      ((type) == GLB_SFLASH_CLK_72M) ||   \
+                                      ((type) == GLB_SFLASH_CLK_BCLK) ||  \
+                                      ((type) == GLB_SFLASH_CLK_96M))
+
+/** @defgroup  GLB_CHIP_CLK_OUT_TYPE
+ *  @{
+ */
+#define IS_GLB_CHIP_CLK_OUT_TYPE(type) (((type) == GLB_CHIP_CLK_OUT_NONE) ||          \
+                                        ((type) == GLB_CHIP_CLK_OUT_I2S_REF_CLK) ||   \
+                                        ((type) == GLB_CHIP_CLK_OUT_AUDIO_PLL_CLK) || \
+                                        ((type) == GLB_CHIP_CLK_OUT_XTAL_SOC_32M))
+
+/** @defgroup  GLB_ETH_REF_CLK_OUT_TYPE
+ *  @{
+ */
+#define IS_GLB_ETH_REF_CLK_OUT_TYPE(type) (((type) == GLB_ETH_REF_CLK_OUT_OUTSIDE_50M) || \
+                                           ((type) == GLB_ETH_REF_CLK_OUT_INSIDE_50M))
+
+/** @defgroup  GLB_SPI_PAD_ACT_AS_TYPE
+ *  @{
+ */
+#define IS_GLB_SPI_PAD_ACT_AS_TYPE(type) (((type) == GLB_SPI_PAD_ACT_AS_SLAVE) || \
+                                          ((type) == GLB_SPI_PAD_ACT_AS_MASTER))
+
+/** @defgroup  GLB_PKA_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_PKA_CLK_TYPE(type) (((type) == GLB_PKA_CLK_HCLK) || \
+                                   ((type) == GLB_PKA_CLK_DLL96M))
+
+/** @defgroup  BMX_ARB_TYPE
+ *  @{
+ */
+#define IS_BMX_ARB_TYPE(type) (((type) == BMX_ARB_FIX) ||         \
+                               ((type) == BMX_ARB_ROUND_ROBIN) || \
+                               ((type) == BMX_ARB_RANDOM))
+
+/** @defgroup  BMX_BUS_ERR_TYPE
+ *  @{
+ */
+#define IS_BMX_BUS_ERR_TYPE(type) (((type) == BMX_BUS_ERR_TRUSTZONE_DECODE) || \
+                                   ((type) == BMX_BUS_ERR_ADDR_DECODE))
+
+/** @defgroup  BMX_ERR_INT_TYPE
+ *  @{
+ */
+#define IS_BMX_ERR_INT_TYPE(type) (((type) == BMX_ERR_INT_ERR) || \
+                                   ((type) == BMX_ERR_INT_ALL))
+
+/** @defgroup  BMX_TO_INT_TYPE
+ *  @{
+ */
+#define IS_BMX_TO_INT_TYPE(type) (((type) == BMX_TO_INT_TIMEOUT) || \
+                                  ((type) == BMX_TO_INT_ALL))
+
+/** @defgroup  GLB_EM_TYPE
+ *  @{
+ */
+#define IS_GLB_EM_TYPE(type) (((type) == GLB_EM_0KB) || \
+                              ((type) == GLB_EM_8KB) || \
+                              ((type) == GLB_EM_16KB))
+
+/** @defgroup  GLB_EMAC_CAM_PIN_TYPE
+ *  @{
+ */
+#define IS_GLB_EMAC_CAM_PIN_TYPE(type) (((type) == GLB_EMAC_CAM_PIN_EMAC) || \
+                                        ((type) == GLB_EMAC_CAM_PIN_CAM))
+
+/** @defgroup  GLB_MTIMER_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_MTIMER_CLK_TYPE(type) (((type) == GLB_MTIMER_CLK_BCLK) || \
+                                      ((type) == GLB_MTIMER_CLK_32K))
+
+/** @defgroup  GLB_ADC_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_ADC_CLK_TYPE(type) (((type) == GLB_ADC_CLK_AUDIO_PLL) || \
+                                   ((type) == GLB_ADC_CLK_XCLK))
+
+/** @defgroup  GLB_DAC_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_DAC_CLK_TYPE(type) (((type) == GLB_DAC_CLK_PLL_32M) || \
+                                   ((type) == GLB_DAC_CLK_XCLK) ||    \
+                                   ((type) == GLB_DAC_CLK_AUDIO_PLL))
+
+/** @defgroup  GLB_DIG_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_DIG_CLK_TYPE(type) (((type) == GLB_DIG_CLK_PLL_32M) || \
+                                   ((type) == GLB_DIG_CLK_XCLK) ||    \
+                                   ((type) == GLB_DIG_CLK_AUDIO_PLL))
+
+/** @defgroup  GLB_BT_BANDWIDTH_TYPE
+ *  @{
+ */
+#define IS_GLB_BT_BANDWIDTH_TYPE(type) (((type) == GLB_BT_BANDWIDTH_1M) || \
+                                        ((type) == GLB_BT_BANDWIDTH_2M))
+
+/** @defgroup  GLB_UART_SIG_TYPE
+ *  @{
+ */
+#define IS_GLB_UART_SIG_TYPE(type) (((type) == GLB_UART_SIG_0) || \
+                                    ((type) == GLB_UART_SIG_1) || \
+                                    ((type) == GLB_UART_SIG_2) || \
+                                    ((type) == GLB_UART_SIG_3) || \
+                                    ((type) == GLB_UART_SIG_4) || \
+                                    ((type) == GLB_UART_SIG_5) || \
+                                    ((type) == GLB_UART_SIG_6) || \
+                                    ((type) == GLB_UART_SIG_7))
+
+/** @defgroup  GLB_UART_SIG_FUN_TYPE
+ *  @{
+ */
+#define IS_GLB_UART_SIG_FUN_TYPE(type) (((type) == GLB_UART_SIG_FUN_UART0_RTS) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART0_CTS) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART0_TXD) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART0_RXD) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART1_RTS) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART1_CTS) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART1_TXD) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART1_RXD))
+
+/** @defgroup  GLB_DLL_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_DLL_CLK_TYPE(type) (((type) == GLB_DLL_CLK_57P6M) || \
+                                   ((type) == GLB_DLL_CLK_96M) ||   \
+                                   ((type) == GLB_DLL_CLK_144M) ||  \
+                                   ((type) == GLB_DLL_CLK_288M) ||  \
+                                   ((type) == GLB_DLL_CLK_MMDIV))
+
+/** @defgroup  GLB_GPIO_INT_TRIG_TYPE
+ *  @{
+ */
+#define IS_GLB_GPIO_INT_TRIG_TYPE(type) (((type) == GLB_GPIO_INT_TRIG_NEG_PULSE) || \
+                                         ((type) == GLB_GPIO_INT_TRIG_POS_PULSE) || \
+                                         ((type) == GLB_GPIO_INT_TRIG_NEG_LEVEL) || \
+                                         ((type) == GLB_GPIO_INT_TRIG_POS_LEVEL))
+
+/** @defgroup  GLB_GPIO_INT_CONTROL_TYPE
+ *  @{
+ */
+#define IS_GLB_GPIO_INT_CONTROL_TYPE(type) (((type) == GLB_GPIO_INT_CONTROL_SYNC) || \
+                                            ((type) == GLB_GPIO_INT_CONTROL_ASYNC))
+
+/** @defgroup  GLB_DLL_XTAL_TYPE
+ *  @{
+ */
+#define IS_GLB_DLL_XTAL_TYPE(type) (((type) == GLB_DLL_XTAL_NONE) || \
+                                    ((type) == GLB_DLL_XTAL_32M) ||  \
+                                    ((type) == GLB_DLL_XTAL_RC32M))
+
+/*@} end of group GLB_Public_Constants */
+
+/** @defgroup  GLB_Public_Macros
+ *  @{
+ */
+#define UART_SIG_SWAP_GPIO0_GPIO7   0x01 /* GPIO0-7   uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */
+#define UART_SIG_SWAP_GPIO8_GPIO15  0x02 /* GPIO8-15  uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */
+#define UART_SIG_SWAP_GPIO16_GPIO22 0x04 /* GPIO16-22 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */
+#define UART_SIG_SWAP_NONE          0x00 /* GPIO0-22  uart_sig[0:7] <- uart_sig[4:7], uart_sig[0:3] */
+#define JTAG_SIG_SWAP_GPIO0_GPIO3   0x01 /* GPIO0-3   E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
+#define JTAG_SIG_SWAP_GPIO4_GPIO7   0x02 /* GPIO4-7   E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
+#define JTAG_SIG_SWAP_GPIO8_GPIO11  0x04 /* GPIO8-11  E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
+#define JTAG_SIG_SWAP_GPIO12_GPIO15 0x08 /* GPIO12-15 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
+#define JTAG_SIG_SWAP_GPIO16_GPIO19 0x10 /* GPIO16-19 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
+#define JTAG_SIG_SWAP_GPIO20_GPIO22 0x20 /* GPIO20-22 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
+#define JTAG_SIG_SWAP_NONE          0x00 /* GPIO0-22  E21_TMS/E21_TDI/E21_TCK/E21_TDO <- E21_TCK/E21_TDO/E21_TMS/E21_TDI */
+
+#define GLB_AHB_CLOCK_CPU             (0x0000000000000001UL)
+#define GLB_AHB_CLOCK_SDU             (0x0000000000000002UL)
+#define GLB_AHB_CLOCK_SEC             (0x0000000000000004UL)
+#define GLB_AHB_CLOCK_DMA_0           (0x0000000000000008UL)
+#define GLB_AHB_CLOCK_DMA_1           (0x0000000000000010UL)
+#define GLB_AHB_CLOCK_DMA_2           (0x0000000000000020UL)
+#define GLB_AHB_CLOCK_CCI             (0x0000000000000040UL)
+#define GLB_AHB_CLOCK_RF_TOP          (0x0000000000000080UL)
+#define GLB_AHB_CLOCK_GPIP            (0x0000000000000100UL)
+#define GLB_AHB_CLOCK_TZC             (0x0000000000000200UL)
+#define GLB_AHB_CLOCK_EF_CTRL         (0x0000000000000400UL)
+#define GLB_AHB_CLOCK_SF_CTRL         (0x0000000000000800UL)
+#define GLB_AHB_CLOCK_EMAC            (0x0000000000001000UL)
+#define GLB_AHB_CLOCK_UART0           (0x0000000000002000UL)
+#define GLB_AHB_CLOCK_UART1           (0x0000000000004000UL)
+#define GLB_AHB_CLOCK_UART2           (0x0000000000008000UL)
+#define GLB_AHB_CLOCK_UART3           (0x0000000000010000UL)
+#define GLB_AHB_CLOCK_UART4           (0x0000000000020000UL)
+#define GLB_AHB_CLOCK_SPI             (0x0000000000040000UL)
+#define GLB_AHB_CLOCK_I2C             (0x0000000000080000UL)
+#define GLB_AHB_CLOCK_PWM             (0x0000000000100000UL)
+#define GLB_AHB_CLOCK_TIMER           (0x0000000000200000UL)
+#define GLB_AHB_CLOCK_IR              (0x0000000000400000UL)
+#define GLB_AHB_CLOCK_CHECKSUM        (0x0000000000800000UL)
+#define GLB_AHB_CLOCK_QDEC            (0x0000000001000000UL)
+#define GLB_AHB_CLOCK_KYS             (0x0000000002000000UL)
+#define GLB_AHB_CLOCK_I2S             (0x0000000004000000UL)
+#define GLB_AHB_CLOCK_USB11           (0x0000000008000000UL)
+#define GLB_AHB_CLOCK_CAM             (0x0000000010000000UL)
+#define GLB_AHB_CLOCK_MJPEG           (0x0000000020000000UL)
+#define GLB_AHB_CLOCK_BT_BLE_NORMAL   (0x0000000040000000UL)
+#define GLB_AHB_CLOCK_BT_BLE_LP       (0x0000000080000000UL)
+#define GLB_AHB_CLOCK_ZB_NORMAL       (0x0000000100000000UL)
+#define GLB_AHB_CLOCK_ZB_LP           (0x0000000200000000UL)
+#define GLB_AHB_CLOCK_WIFI_NORMAL     (0x0000000400000000UL)
+#define GLB_AHB_CLOCK_WIFI_LP         (0x0000000800000000UL)
+#define GLB_AHB_CLOCK_BT_BLE_2_NORMAL (0x0000001000000000UL)
+#define GLB_AHB_CLOCK_BT_BLE_2_LP     (0x0000002000000000UL)
+#define GLB_AHB_CLOCK_EMI_MISC        (0x0000004000000000UL)
+#define GLB_AHB_CLOCK_PSRAM0_CTRL     (0x0000008000000000UL)
+#define GLB_AHB_CLOCK_PSRAM1_CTRL     (0x0000010000000000UL)
+#define GLB_AHB_CLOCK_USB20           (0x0000020000000000UL)
+#define GLB_AHB_CLOCK_MIX2            (0x0000040000000000UL)
+#define GLB_AHB_CLOCK_AUDIO           (0x0000080000000000UL)
+#define GLB_AHB_CLOCK_SDH             (0x0000100000000000UL)
+
+/*@} end of group GLB_Public_Macros */
+
+/** @defgroup  GLB_Public_Functions
+ *  @{
+ */
+/*----------*/
+#ifndef BFLB_USE_HAL_DRIVER
+void BMX_ERR_IRQHandler(void);
+void BMX_TO_IRQHandler(void);
+void GPIO_INT0_IRQHandler(void);
+#endif
+/*----------*/
+GLB_ROOT_CLK_Type GLB_Get_Root_CLK_Sel(void);
+BL_Err_Type GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv);
+uint8_t GLB_Get_BCLK_Div(void);
+uint8_t GLB_Get_HCLK_Div(void);
+BL_Err_Type Update_SystemCoreClockWith_XTAL(GLB_DLL_XTAL_Type xtalType);
+BL_Err_Type GLB_Set_System_CLK(GLB_DLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq);
+BL_Err_Type System_Core_Clock_Update_From_RC32M(void);
+/*----------*/
+BL_Err_Type GLB_Set_CAM_CLK(uint8_t enable, GLB_CAM_CLK_Type clkSel, uint8_t div);
+BL_Err_Type GLB_Set_MAC154_ZIGBEE_CLK(uint8_t enable);
+BL_Err_Type GLB_Set_BLE_CLK(uint8_t enable);
+BL_Err_Type GLB_Set_I2S_CLK(uint8_t enable, GLB_I2S_OUT_REF_CLK_Type outRef);
+BL_Err_Type GLB_Set_USB_CLK(uint8_t enable);
+BL_Err_Type GLB_Set_QDEC_CLK(GLB_QDEC_CLK_Type clkSel, uint8_t div);
+/*----------*/
+BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk);
+BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div);
+BL_Err_Type GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div);
+BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div);
+/*----------*/
+BL_Err_Type GLB_Set_Chip_Out_0_CLK_Sel(GLB_CHIP_CLK_OUT_Type clkSel);
+BL_Err_Type GLB_Set_Chip_Out_1_CLK_Sel(GLB_CHIP_CLK_OUT_Type clkSel);
+BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, uint8_t div);
+BL_Err_Type GLB_Invert_ETH_RX_CLK(uint8_t enable);
+BL_Err_Type GLB_Invert_RF_TEST_O_CLK(uint8_t enable);
+BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, uint8_t div);
+BL_Err_Type GLB_Invert_ETH_TX_CLK(uint8_t enable);
+BL_Err_Type GLB_Invert_ETH_REF_O_CLK(uint8_t enable);
+BL_Err_Type GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_Type clkSel);
+/*----------*/
+BL_Err_Type GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel);
+BL_Err_Type GLB_SW_System_Reset(void);
+BL_Err_Type GLB_SW_CPU_Reset(void);
+BL_Err_Type GLB_SW_POR_Reset(void);
+BL_Err_Type GLB_AHB_Slave1_Reset(BL_AHB_Slave1_Type slave1);
+BL_Err_Type GLB_AHB_Slave1_Clock_Gate(uint8_t enable, BL_AHB_Slave1_Type slave1);
+uint64_t GLB_PER_Clock_Gate_Status_Get(void);
+BL_Err_Type GLB_PER_Clock_Gate(uint64_t ips);
+BL_Err_Type GLB_PER_Clock_UnGate(uint64_t ips);
+/*----------*/
+BL_Err_Type GLB_BMX_Init(BMX_Cfg_Type *BmxCfg);
+BL_Err_Type GLB_BMX_Addr_Monitor_Enable(void);
+BL_Err_Type GLB_BMX_Addr_Monitor_Disable(void);
+BL_Err_Type GLB_BMX_BusErrResponse_Enable(void);
+BL_Err_Type GLB_BMX_BusErrResponse_Disable(void);
+BL_Sts_Type GLB_BMX_Get_Status(BMX_BUS_ERR_Type errType);
+uint32_t GLB_BMX_Get_Err_Addr(void);
+BL_Err_Type BMX_ERR_INT_Callback_Install(BMX_ERR_INT_Type intType, intCallback_Type *cbFun);
+BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun);
+/*----------*/
+BL_Err_Type GLB_Set_SRAM_RET(uint32_t value);
+uint32_t GLB_Get_SRAM_RET(void);
+BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value);
+uint32_t GLB_Get_SRAM_SLP(void);
+BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value);
+uint32_t GLB_Get_SRAM_PARM(void);
+/*----------*/
+BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType);
+/*----------*/
+BL_Err_Type GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_Type pinType);
+BL_Err_Type GLB_Set_Ext_Rst_Smt(uint8_t enable);
+BL_Err_Type GLB_Set_Kys_Drv_Col(uint8_t enable);
+BL_Err_Type GLB_UART_Sig_Swap_Set(uint8_t swapSel);
+BL_Err_Type GLB_JTAG_Sig_Swap_Set(uint8_t swapSel);
+BL_Err_Type GLB_CCI_Use_IO_0_1_2_7(uint8_t enable);
+BL_Err_Type GLB_CCI_Use_Jtag_Pin(uint8_t enable);
+BL_Err_Type GLB_Swap_SPI_0_MOSI_With_MISO(BL_Fun_Type newState);
+BL_Err_Type GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod);
+BL_Err_Type GLB_Select_Internal_Flash(void);
+BL_Err_Type GLB_Select_External_Flash(void);
+BL_Err_Type GLB_Deswap_Flash_Pin(void);
+BL_Err_Type GLB_Swap_Flash_CS_IO2_Pin();
+BL_Err_Type GLB_Swap_Flash_IO0_IO3_Pin();
+BL_Err_Type GLB_Swap_Flash_Pin(void);
+BL_Err_Type GLB_Select_Internal_PSram(void);
+/*----------*/
+BL_Err_Type GLB_Set_PDM_CLK(uint8_t enable, uint8_t div);
+/*----------*/
+BL_Err_Type GLB_Set_MTimer_CLK(uint8_t enable, GLB_MTIMER_CLK_Type clkSel, uint32_t div);
+/*----------*/
+BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div);
+BL_Err_Type GLB_Set_DAC_CLK(uint8_t enable, GLB_DAC_CLK_Type clkSel, uint8_t div);
+/*----------*/
+BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel);
+BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable, uint8_t compensation, uint8_t div);
+BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensation, uint8_t div);
+/*----------*/
+BL_Err_Type GLB_Set_BT_Coex_Signal(uint8_t enable, GLB_BT_BANDWIDTH_Type bandWidth,
+                                   uint8_t pti, uint8_t channel);
+/*----------*/
+BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun);
+/*----------*/
+BL_Err_Type GLB_Power_Off_DLL(void);
+BL_Err_Type GLB_Power_On_DLL(GLB_DLL_XTAL_Type xtalType);
+BL_Err_Type GLB_Enable_DLL_All_Clks(void);
+BL_Err_Type GLB_Enable_DLL_Clk(GLB_DLL_CLK_Type dllClk);
+BL_Err_Type GLB_Disable_DLL_All_Clks(void);
+BL_Err_Type GLB_Disable_DLL_Clk(GLB_DLL_CLK_Type dllClk);
+/*----------*/
+BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio);
+BL_Err_Type GLB_IR_LED_Driver_Enable(void);
+BL_Err_Type GLB_IR_LED_Driver_Disable(void);
+BL_Err_Type GLB_IR_LED_Driver_Output_Enable(GLB_GPIO_Type gpio);
+BL_Err_Type GLB_IR_LED_Driver_Output_Disable(GLB_GPIO_Type gpio);
+BL_Err_Type GLB_IR_LED_Driver_Ibias(uint8_t ibias);
+/*----------*/
+BL_Err_Type GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg);
+BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt);
+BL_Err_Type GLB_GPIO_INPUT_Enable(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_Set_Flash_Pad_HZ(void);
+BL_Err_Type GLB_Set_Psram_Pad_HZ(void);
+uint8_t GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val);
+uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask);
+BL_Err_Type GLB_GPIO_IntClear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear);
+BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_Set_GPIO_IntMod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod,
+                                GLB_GPIO_INT_TRIG_Type intTrgMod);
+GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_IntCtlMod(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_Int2Mask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask);
+BL_Err_Type GLB_GPIO_Int2Clear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear);
+BL_Sts_Type GLB_Get_GPIO_Int2Status(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_Set_GPIO_Int2Mod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod,
+                                 GLB_GPIO_INT_TRIG_Type intTrgMod);
+GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_Int2CtlMod(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void);
+BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun);
+BL_Err_Type GLB_GPIO_INT0_Callback_Install2(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun);
+/*----------*/;
+
+/*@} end of group GLB_Public_Functions */
+
+/*@} end of group GLB */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_GLB_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_gpio.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_gpio.h
new file mode 100644
index 00000000..294d1d80
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_gpio.h
@@ -0,0 +1,950 @@
+/**
+
+  ******************************************************************************
+
+  * @file    bl702_gpio.h
+
+  * @version V1.2
+
+  * @date    2020-09-04
+
+  * @brief   This file is the description of.IP register
+
+  ******************************************************************************
+
+  * @attention
+
+  *
+
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+
+  *
+
+  * Redistribution and use in source and binary forms, with or without modification,
+
+  * are permitted provided that the following conditions are met:
+
+  *   1. Redistributions of source code must retain the above copyright notice,
+
+  *      this list of conditions and the following disclaimer.
+
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+
+  *      this list of conditions and the following disclaimer in the documentation
+
+  *      and/or other materials provided with the distribution.
+
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+
+  *      may be used to endorse or promote products derived from this software
+
+  *      without specific prior written permission.
+
+  *
+
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+  *
+
+  ******************************************************************************
+
+  */
+
+#ifndef __BL702_GPIO_H__
+#define __BL702_GPIO_H__
+
+typedef enum {
+  GLB_GPIO_PIN_0 = 0,
+  GLB_GPIO_PIN_1,
+  GLB_GPIO_PIN_2,
+  GLB_GPIO_PIN_3,
+  GLB_GPIO_PIN_4,
+  GLB_GPIO_PIN_5,
+  GLB_GPIO_PIN_6,
+  GLB_GPIO_PIN_7,
+  GLB_GPIO_PIN_8,
+  GLB_GPIO_PIN_9,
+  GLB_GPIO_PIN_10,
+  GLB_GPIO_PIN_11,
+  GLB_GPIO_PIN_12,
+  GLB_GPIO_PIN_13,
+  GLB_GPIO_PIN_14,
+  GLB_GPIO_PIN_15,
+  GLB_GPIO_PIN_16,
+  GLB_GPIO_PIN_17,
+  GLB_GPIO_PIN_18,
+  GLB_GPIO_PIN_19,
+  GLB_GPIO_PIN_20,
+  GLB_GPIO_PIN_21,
+  GLB_GPIO_PIN_22,
+  GLB_GPIO_PIN_23,
+  GLB_GPIO_PIN_24,
+  GLB_GPIO_PIN_25,
+  GLB_GPIO_PIN_26,
+  GLB_GPIO_PIN_27,
+  GLB_GPIO_PIN_28,
+  GLB_GPIO_PIN_29,
+  GLB_GPIO_PIN_30,
+  GLB_GPIO_PIN_31,
+  GLB_GPIO_PIN_MAX,
+} GLB_GPIO_Type;
+
+#define GPIO_MODE_INPUT  ((uint32_t)0x00000000U) /*!< Input Floating Mode                   */
+#define GPIO_MODE_OUTPUT ((uint32_t)0x00000001U) /*!< Output Push Pull Mode                 */
+#define GPIO_MODE_AF     ((uint32_t)0x00000002U) /*!< Alternate function                    */
+#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog function                       */
+#define GPIO_PULL_UP     ((uint32_t)0x00000000U) /*!< GPIO pull up                          */
+#define GPIO_PULL_DOWN   ((uint32_t)0x00000001U) /*!< GPIO pull down                        */
+#define GPIO_PULL_NONE   ((uint32_t)0x00000002U) /*!< GPIO no pull up or down               */
+
+typedef enum {
+  GPIO_FUN_CLK_OUT                = 0,
+  GPIO_FUN_BT_COEXIST             = 1,
+  GPIO_FUN_FLASH_PSRAM            = 2,
+  GPIO_FUN_QSPI                   = 2,
+  GPIO_FUN_I2S                    = 3,
+  GPIO_FUN_SPI                    = 4,
+  GPIO_FUN_I2C                    = 6,
+  GPIO_FUN_UART                   = 7,
+  GPIO_FUN_PWM                    = 8,
+  GPIO_FUN_CAM                    = 9,
+  GPIO_FUN_ANALOG                 = 10,
+  GPIO_FUN_GPIO                   = 11,
+  GPIO_FUN_RF_TEST                = 12,
+  GPIO_FUN_SCAN                   = 13,
+  GPIO_FUN_E21_JTAG               = 14,
+  GPIO_FUN_DEBUG                  = 15,
+  GPIO_FUN_EXTERNAL_PA            = 16,
+  GPIO_FUN_USB_TRANCEIVER         = 17,
+  GPIO_FUN_USB_CONTROLLER         = 18,
+  GPIO_FUN_ETHER_MAC              = 19,
+  GPIO_FUN_EMAC                   = 19,
+  GPIO_FUN_QDEC                   = 20,
+  GPIO_FUN_KEY_SCAN_IN            = 21,
+  GPIO_FUN_KEY_SCAN_ROW           = 21,
+  GPIO_FUN_KEY_SCAN_DRIVE         = 22,
+  GPIO_FUN_KEY_SCAN_COL           = 22,
+  GPIO_FUN_CAM_MISC               = 23,
+  GPIO_FUN_USB                    = 0xD0,
+  GPIO_FUN_DAC                    = 0xD1,
+  GPIO_FUN_ADC                    = 0xD2,
+  GPIO_FUN_QDEC_LED               = 0xD3,
+  GPIO_FUN_GPIO_OUTPUT_UP         = 0xE0,
+  GPIO_FUN_GPIO_OUTPUT_DOWN       = 0xE1,
+  GPIO_FUN_GPIO_OUTPUT_NONE       = 0xE2,
+  GPIO_FUN_GPIO_INPUT_UP          = 0xE3,
+  GPIO_FUN_GPIO_INPUT_DOWN        = 0xE4,
+  GPIO_FUN_GPIO_INPUT_NONE        = 0xE5,
+  GPIO_FUN_GPIO_EXTI_RISING_EDGE  = 0xE6,
+  GPIO_FUN_GPIO_EXTI_FALLING_EDGE = 0xE7,
+  GPIO_FUN_GPIO_EXTI_HIGH_LEVEL   = 0xE8,
+  GPIO_FUN_GPIO_EXTI_LOW_LEVEL    = 0xE9,
+  GPIO_FUN_UART0_RTS              = 0xF0,
+  GPIO_FUN_UART0_CTS              = 0xF1,
+  GPIO_FUN_UART0_TX               = 0xF2,
+  GPIO_FUN_UART0_RX               = 0xF3,
+  GPIO_FUN_UART1_RTS              = 0xF4,
+  GPIO_FUN_UART1_CTS              = 0xF5,
+  GPIO_FUN_UART1_TX               = 0xF6,
+  GPIO_FUN_UART1_RX               = 0xF7,
+  GPIO_FUN_WAKEUP                 = 0xFE,
+  GPIO_FUN_UNUSED                 = 0xFF
+} GLB_GPIO_FUNC_Type;
+
+typedef struct {
+  uint8_t gpioPin;
+  uint8_t gpioFun;
+  uint8_t gpioMode;
+  uint8_t pullType;
+  uint8_t drive;
+  uint8_t smtCtrl; // Schmitt trigger
+} GLB_GPIO_Cfg_Type;
+
+/* GPIO0 function definition */
+#define GPIO0_FUN_CLK_OUT_0             0
+#define GPIO0_FUN_BT_ABORT              1
+#define GPIO0_FUN_UNUSED2               2
+#define GPIO0_FUN_I2S0_BCLK             3
+#define GPIO0_FUN_SPI_0_MOSI_SPI_0_MISO 4
+#define GPIO0_FUN_I2C0_SCL              6
+#define GPIO0_FUN_UART_SIG0_UART_SIG4   7
+#define GPIO0_FUN_PWM_CH0               8
+#define GPIO0_FUN_PIX_CLK               9
+#define GPIO0_FUN_UNUSED10              10
+#define GPIO0_FUN_REG_GPIO_0            11
+#define GPIO0_FUN_UNUSED12              12
+#define GPIO0_FUN_SCAN_IN_0             13
+#define GPIO0_FUN_E21_TMS_E21_TCK       14
+#define GPIO0_FUN_S_CCI_CLK             15
+#define GPIO0_FUN_FEM_GPIO_0            16
+#define GPIO0_FUN_USB_TX_DN_USB_RX_DN   17
+#define GPIO0_FUN_USB_SUS               18
+#define GPIO0_FUN_MII_REF_CLK           19
+#define GPIO0_FUN_QDEC0_A               20
+#define GPIO0_FUN_ROW_I_0               21
+#define GPIO0_FUN_COL_O_0               22
+#define GPIO0_FUN_CAM_PWRDN             23
+/* GPIO1 function definition */
+#define GPIO1_FUN_CLK_OUT_1             0
+#define GPIO1_FUN_BT_ACTIVE             1
+#define GPIO1_FUN_UNUSED2               2
+#define GPIO1_FUN_I2S0_FS               3
+#define GPIO1_FUN_SPI_0_MISO_SPI_0_MOSI 4
+#define GPIO1_FUN_I2C0_SDA              6
+#define GPIO1_FUN_UART_SIG1_UART_SIG5   7
+#define GPIO1_FUN_PWM_CH1               8
+#define GPIO1_FUN_FRAME_VLD             9
+#define GPIO1_FUN_UNUSED10              10
+#define GPIO1_FUN_REG_GPIO_1            11
+#define GPIO1_FUN_UNUSED12              12
+#define GPIO1_FUN_SCAN_IN_1             13
+#define GPIO1_FUN_E21_TDI_E21_TDO       14
+#define GPIO1_FUN_S_CCI_CS              15
+#define GPIO1_FUN_FEM_GPIO_1            16
+#define GPIO1_FUN_USB_TX_OE             17
+#define GPIO1_FUN_USB_ENUM              18
+#define GPIO1_FUN_MII_TXD_0             19
+#define GPIO1_FUN_QDEC0_B               20
+#define GPIO1_FUN_ROW_I_1               21
+#define GPIO1_FUN_COL_O_1               22
+#define GPIO1_FUN_CAM_REF_CLK           23
+/* GPIO2 function definition */
+#define GPIO2_FUN_CLK_OUT_0           0
+#define GPIO2_FUN_BT_PRI              1
+#define GPIO2_FUN_UNUSED2             2
+#define GPIO2_FUN_I2S0_DIO_I2S0_DO    3
+#define GPIO2_FUN_SPI_0_SS            4
+#define GPIO2_FUN_I2C0_SCL            6
+#define GPIO2_FUN_UART_SIG2_UART_SIG6 7
+#define GPIO2_FUN_PWM_CH2             8
+#define GPIO2_FUN_LINE_VLD            9
+#define GPIO2_FUN_UNUSED10            10
+#define GPIO2_FUN_REG_GPIO_2          11
+#define GPIO2_FUN_UNUSED12            12
+#define GPIO2_FUN_SCAN_IN_2           13
+#define GPIO2_FUN_E21_TCK_E21_TMS     14
+#define GPIO2_FUN_S_CCI_DATA_0        15
+#define GPIO2_FUN_FEM_GPIO_2          16
+#define GPIO2_FUN_USB_TX_DP_USB_RX_DP 17
+#define GPIO2_FUN_USB_OEB             18
+#define GPIO2_FUN_MII_TXD_1           19
+#define GPIO2_FUN_QDEC0_LED           20
+#define GPIO2_FUN_ROW_I_2             21
+#define GPIO2_FUN_COL_O_2             22
+#define GPIO2_FUN_CAM_RESET           23
+/* GPIO3 function definition */
+#define GPIO3_FUN_CLK_OUT_1           0
+#define GPIO3_FUN_BT_ABORT            1
+#define GPIO3_FUN_UNUSED2             2
+#define GPIO3_FUN_I2S0_RCLK_O_I2S0_DI 3
+#define GPIO3_FUN_SPI_0_SCLK          4
+#define GPIO3_FUN_I2C0_SDA            6
+#define GPIO3_FUN_UART_SIG3_UART_SIG7 7
+#define GPIO3_FUN_PWM_CH3             8
+#define GPIO3_FUN_PIX_DAT0            9
+#define GPIO3_FUN_UNUSED10            10
+#define GPIO3_FUN_REG_GPIO_3          11
+#define GPIO3_FUN_RF_TEST_0           12
+#define GPIO3_FUN_UNUSED13            13
+#define GPIO3_FUN_E21_TDO_E21_TDI     14
+#define GPIO3_FUN_DEBUG_0             15
+#define GPIO3_FUN_FEM_GPIO_3          16
+#define GPIO3_FUN_USB_SUS_EXT         17
+#define GPIO3_FUN_VOP                 18
+#define GPIO3_FUN_UNUSED19            19
+#define GPIO3_FUN_QDEC1_A             20
+#define GPIO3_FUN_ROW_I_3             21
+#define GPIO3_FUN_COL_O_3             22
+#define GPIO3_FUN_CAM_PWRDN           23
+/* GPIO4 function definition */
+#define GPIO4_FUN_CLK_OUT_0             0
+#define GPIO4_FUN_BT_ACTIVE             1
+#define GPIO4_FUN_UNUSED2               2
+#define GPIO4_FUN_I2S0_BCLK             3
+#define GPIO4_FUN_SPI_0_MOSI_SPI_0_MISO 4
+#define GPIO4_FUN_I2C0_SCL              6
+#define GPIO4_FUN_UART_SIG4_UART_SIG0   7
+#define GPIO4_FUN_PWM_CH4               8
+#define GPIO4_FUN_PIX_DAT1              9
+#define GPIO4_FUN_UNUSED10              10
+#define GPIO4_FUN_REG_GPIO_4            11
+#define GPIO4_FUN_RF_TEST_1             12
+#define GPIO4_FUN_UNUSED13              13
+#define GPIO4_FUN_E21_TMS_E21_TCK       14
+#define GPIO4_FUN_DEBUG_1               15
+#define GPIO4_FUN_FEM_GPIO_4            16
+#define GPIO4_FUN_USB_ENUM_EXT          17
+#define GPIO4_FUN_VOM                   18
+#define GPIO4_FUN_UNUSED19              19
+#define GPIO4_FUN_QDEC1_B               20
+#define GPIO4_FUN_ROW_I_4               21
+#define GPIO4_FUN_COL_O_4               22
+#define GPIO4_FUN_CAM_REF_CLK           23
+/* GPIO5 function definition */
+#define GPIO5_FUN_CLK_OUT_1             0
+#define GPIO5_FUN_BT_PRI                1
+#define GPIO5_FUN_UNUSED2               2
+#define GPIO5_FUN_I2S0_FS               3
+#define GPIO5_FUN_SPI_0_MISO_SPI_0_MOSI 4
+#define GPIO5_FUN_I2C0_SDA              6
+#define GPIO5_FUN_UART_SIG5_UART_SIG1   7
+#define GPIO5_FUN_PWM_CH0               8
+#define GPIO5_FUN_PIX_DAT2              9
+#define GPIO5_FUN_UNUSED10              10
+#define GPIO5_FUN_REG_GPIO_5            11
+#define GPIO5_FUN_RF_TEST_2             12
+#define GPIO5_FUN_UNUSED13              13
+#define GPIO5_FUN_E21_TDI_E21_TDO       14
+#define GPIO5_FUN_DEBUG_2               15
+#define GPIO5_FUN_FEM_GPIO_0            16
+#define GPIO5_FUN_USB_TX_DN_USB_RX_DN   17
+#define GPIO5_FUN_BD                    18
+#define GPIO5_FUN_UNUSED19              19
+#define GPIO5_FUN_QDEC1_LED             20
+#define GPIO5_FUN_ROW_I_5               21
+#define GPIO5_FUN_COL_O_5               22
+#define GPIO5_FUN_CAM_RESET             23
+/* GPIO6 function definition */
+#define GPIO6_FUN_CLK_OUT_0           0
+#define GPIO6_FUN_BT_ABORT            1
+#define GPIO6_FUN_UNUSED2             2
+#define GPIO6_FUN_I2S0_DIO_I2S0_DO    3
+#define GPIO6_FUN_SPI_0_SS            4
+#define GPIO6_FUN_I2C0_SCL            6
+#define GPIO6_FUN_UART_SIG6_UART_SIG2 7
+#define GPIO6_FUN_PWM_CH1             8
+#define GPIO6_FUN_PIX_DAT3            9
+#define GPIO6_FUN_UNUSED10            10
+#define GPIO6_FUN_REG_GPIO_6          11
+#define GPIO6_FUN_RF_TEST_3           12
+#define GPIO6_FUN_UNUSED13            13
+#define GPIO6_FUN_E21_TCK_E21_TMS     14
+#define GPIO6_FUN_DEBUG_3             15
+#define GPIO6_FUN_FEM_GPIO_1          16
+#define GPIO6_FUN_USB_TX_OE           17
+#define GPIO6_FUN_VIP                 18
+#define GPIO6_FUN_UNUSED19            19
+#define GPIO6_FUN_QDEC2_A             20
+#define GPIO6_FUN_ROW_I_6             21
+#define GPIO6_FUN_COL_O_6             22
+#define GPIO6_FUN_CAM_PWRDN           23
+/* GPIO7 function definition */
+#define GPIO7_FUN_CLK_OUT_1                       0
+#define GPIO7_FUN_BT_ACTIVE                       1
+#define GPIO7_FUN_UNUSED2                         2
+#define GPIO7_FUN_I2S0_RCLK_O_I2S0_DI             3
+#define GPIO7_FUN_SPI_0_SCLK                      4
+#define GPIO7_FUN_I2C0_SDA                        6
+#define GPIO7_FUN_UART_SIG7_UART_SIG3             7
+#define GPIO7_FUN_PWM_CH2                         8
+#define GPIO7_FUN_UNUSED9                         9
+#define GPIO7_FUN_USB_DP_GPIP_CH_6_GPDAC_VREF_EXT 10
+#define GPIO7_FUN_REG_GPIO_7                      11
+#define GPIO7_FUN_UNUSED12                        12
+#define GPIO7_FUN_SCAN_RSTB                       13
+#define GPIO7_FUN_E21_TDO_E21_TDI                 14
+#define GPIO7_FUN_S_CCI_DATA_1                    15
+#define GPIO7_FUN_FEM_GPIO_2                      16
+#define GPIO7_FUN_USB_TX_DP_USB_RX_DP             17
+#define GPIO7_FUN_VIM                             18
+#define GPIO7_FUN_MII_RXD_0                       19
+#define GPIO7_FUN_QDEC2_B                         20
+#define GPIO7_FUN_ROW_I_7                         21
+#define GPIO7_FUN_COL_O_7                         22
+#define GPIO7_FUN_CAM_REF_CLK                     23
+/* GPIO8 function definition */
+#define GPIO8_FUN_CLK_OUT_0             0
+#define GPIO8_FUN_BT_PRI                1
+#define GPIO8_FUN_UNUSED2               2
+#define GPIO8_FUN_I2S0_BCLK             3
+#define GPIO8_FUN_SPI_0_MOSI_SPI_0_MISO 4
+#define GPIO8_FUN_I2C0_SCL              6
+#define GPIO8_FUN_UART_SIG0_UART_SIG4   7
+#define GPIO8_FUN_PWM_CH3               8
+#define GPIO8_FUN_UNUSED9               9
+#define GPIO8_FUN_USB_DM_GPIP_CH_0      10
+#define GPIO8_FUN_REG_GPIO_8            11
+#define GPIO8_FUN_RF_TEST_4             12
+#define GPIO8_FUN_SCAN_CLK              13
+#define GPIO8_FUN_E21_TMS_E21_TCK       14
+#define GPIO8_FUN_DEBUG_4               15
+#define GPIO8_FUN_FEM_GPIO_3            16
+#define GPIO8_FUN_USB_SUS_EXT           17
+#define GPIO8_FUN_RCV                   18
+#define GPIO8_FUN_MII_RXD_1             19
+#define GPIO8_FUN_QDEC2_LED             20
+#define GPIO8_FUN_ROW_I_0               21
+#define GPIO8_FUN_COL_O_8               22
+#define GPIO8_FUN_CAM_RESET             23
+/* GPIO9 function definition */
+#define GPIO9_FUN_CLK_OUT_1                         0
+#define GPIO9_FUN_BT_ABORT                          1
+#define GPIO9_FUN_UNUSED2                           2
+#define GPIO9_FUN_I2S0_FS                           3
+#define GPIO9_FUN_SPI_0_MISO_SPI_0_MOSI             4
+#define GPIO9_FUN_I2C0_SDA                          6
+#define GPIO9_FUN_UART_SIG1_UART_SIG5               7
+#define GPIO9_FUN_PWM_CH4                           8
+#define GPIO9_FUN_UNUSED9                           9
+#define GPIO9_FUN_PMIP_DC_TP_CLKPLL_DC_TP_GPIP_CH_7 10
+#define GPIO9_FUN_REG_GPIO_9                        11
+#define GPIO9_FUN_RF_TEST_5                         12
+#define GPIO9_FUN_SCAN_EN                           13
+#define GPIO9_FUN_E21_TDI_E21_TDO                   14
+#define GPIO9_FUN_DEBUG_5                           15
+#define GPIO9_FUN_FEM_GPIO_4                        16
+#define GPIO9_FUN_USB_ENUM_EXT                      17
+#define GPIO9_FUN_USB_SUS                           18
+#define GPIO9_FUN_UNUSED19                          19
+#define GPIO9_FUN_QDEC0_A                           20
+#define GPIO9_FUN_ROW_I_1                           21
+#define GPIO9_FUN_COL_O_9                           22
+#define GPIO9_FUN_CAM_PWRDN                         23
+/* GPIO10 function definition */
+#define GPIO10_FUN_CLK_OUT_0           0
+#define GPIO10_FUN_BT_ACTIVE           1
+#define GPIO10_FUN_UNUSED2             2
+#define GPIO10_FUN_I2S0_DIO_I2S0_DO    3
+#define GPIO10_FUN_SPI_0_SS            4
+#define GPIO10_FUN_I2C0_SCL            6
+#define GPIO10_FUN_UART_SIG2_UART_SIG6 7
+#define GPIO10_FUN_PWM_CH0             8
+#define GPIO10_FUN_UNUSED9             9
+#define GPIO10_FUN_MICBIAS             10
+#define GPIO10_FUN_REG_GPIO_10         11
+#define GPIO10_FUN_RF_TEST_6           12
+#define GPIO10_FUN_UNUSED13            13
+#define GPIO10_FUN_E21_TCK_E21_TMS     14
+#define GPIO10_FUN_DEBUG_6             15
+#define GPIO10_FUN_FEM_GPIO_0          16
+#define GPIO10_FUN_USB_TX_DN_USB_RX_DN 17
+#define GPIO10_FUN_USB_ENUM            18
+#define GPIO10_FUN_UNUSED19            19
+#define GPIO10_FUN_QDEC0_B             20
+#define GPIO10_FUN_ROW_I_2             21
+#define GPIO10_FUN_COL_O_10            22
+#define GPIO10_FUN_CAM_REF_CLK         23
+/* GPIO11 function definition */
+#define GPIO11_FUN_CLK_OUT_1           0
+#define GPIO11_FUN_BT_PRI              1
+#define GPIO11_FUN_UNUSED2             2
+#define GPIO11_FUN_I2S0_RCLK_O_I2S0_DI 3
+#define GPIO11_FUN_SPI_0_SCLK          4
+#define GPIO11_FUN_I2C0_SDA            6
+#define GPIO11_FUN_UART_SIG3_UART_SIG7 7
+#define GPIO11_FUN_PWM_CH1             8
+#define GPIO11_FUN_UNUSED9             9
+#define GPIO11_FUN_GPIP_CH_3           10
+#define GPIO11_FUN_REG_GPIO_11         11
+#define GPIO11_FUN_RF_TEST_7           12
+#define GPIO11_FUN_UNUSED13            13
+#define GPIO11_FUN_E21_TDO_E21_TDI     14
+#define GPIO11_FUN_DEBUG_7             15
+#define GPIO11_FUN_FEM_GPIO_1          16
+#define GPIO11_FUN_USB_TX_OE           17
+#define GPIO11_FUN_USB_OEB             18
+#define GPIO11_FUN_UNUSED19            19
+#define GPIO11_FUN_QDEC0_LED           20
+#define GPIO11_FUN_ROW_I_3             21
+#define GPIO11_FUN_COL_O_11            22
+#define GPIO11_FUN_CAM_RESET           23
+/* GPIO12 function definition */
+#define GPIO12_FUN_CLK_OUT_0             0
+#define GPIO12_FUN_BT_ABORT              1
+#define GPIO12_FUN_UNUSED2               2
+#define GPIO12_FUN_I2S0_BCLK             3
+#define GPIO12_FUN_SPI_0_MOSI_SPI_0_MISO 4
+#define GPIO12_FUN_I2C0_SCL              6
+#define GPIO12_FUN_UART_SIG4_UART_SIG0   7
+#define GPIO12_FUN_PWM_CH2               8
+#define GPIO12_FUN_PIX_DAT4              9
+#define GPIO12_FUN_GPIP_CH_4             10
+#define GPIO12_FUN_REG_GPIO_12           11
+#define GPIO12_FUN_RF_TEST_8             12
+#define GPIO12_FUN_UNUSED13              13
+#define GPIO12_FUN_E21_TMS_E21_TCK       14
+#define GPIO12_FUN_DEBUG_8               15
+#define GPIO12_FUN_FEM_GPIO_2            16
+#define GPIO12_FUN_USB_TX_DP_USB_RX_DP   17
+#define GPIO12_FUN_VOP                   18
+#define GPIO12_FUN_UNUSED19              19
+#define GPIO12_FUN_QDEC1_A               20
+#define GPIO12_FUN_ROW_I_4               21
+#define GPIO12_FUN_COL_O_12              22
+#define GPIO12_FUN_CAM_PWRDN             23
+/* GPIO13 function definition */
+#define GPIO13_FUN_CLK_OUT_1             0
+#define GPIO13_FUN_BT_ACTIVE             1
+#define GPIO13_FUN_UNUSED2               2
+#define GPIO13_FUN_I2S0_FS               3
+#define GPIO13_FUN_SPI_0_MISO_SPI_0_MOSI 4
+#define GPIO13_FUN_I2C0_SDA              6
+#define GPIO13_FUN_UART_SIG5_UART_SIG1   7
+#define GPIO13_FUN_PWM_CH3               8
+#define GPIO13_FUN_UNUSED9               9
+#define GPIO13_FUN_UNUSED10              10
+#define GPIO13_FUN_REG_GPIO_13           11
+#define GPIO13_FUN_UNUSED12              12
+#define GPIO13_FUN_UNUSED13              13
+#define GPIO13_FUN_E21_TDI_E21_TDO       14
+#define GPIO13_FUN_DEBUG_9               15
+#define GPIO13_FUN_FEM_GPIO_3            16
+#define GPIO13_FUN_USB_SUS_EXT           17
+#define GPIO13_FUN_VOM                   18
+#define GPIO13_FUN_UNUSED19              19
+#define GPIO13_FUN_QDEC1_B               20
+#define GPIO13_FUN_ROW_I_5               21
+#define GPIO13_FUN_COL_O_13              22
+#define GPIO13_FUN_CAM_REF_CLK           23
+/* GPIO14 function definition */
+#define GPIO14_FUN_CLK_OUT_0             0
+#define GPIO14_FUN_BT_PRI                1
+#define GPIO14_FUN_UNUSED2               2
+#define GPIO14_FUN_I2S0_DIO_I2S0_DO      3
+#define GPIO14_FUN_SPI_0_SS              4
+#define GPIO14_FUN_I2C0_SCL              6
+#define GPIO14_FUN_UART_SIG6_UART_SIG2   7
+#define GPIO14_FUN_PWM_CH4               8
+#define GPIO14_FUN_UNUSED9               9
+#define GPIO14_FUN_GPIP_CH_5_ATEST_OUT_0 10
+#define GPIO14_FUN_REG_GPIO_14           11
+#define GPIO14_FUN_RF_TEST_9             12
+#define GPIO14_FUN_SCAN_OUT_0            13
+#define GPIO14_FUN_E21_TCK_E21_TMS       14
+#define GPIO14_FUN_DEBUG_10              15
+#define GPIO14_FUN_FEM_GPIO_4            16
+#define GPIO14_FUN_USB_ENUM_EXT          17
+#define GPIO14_FUN_BD                    18
+#define GPIO14_FUN_UNUSED19              19
+#define GPIO14_FUN_QDEC1_LED             20
+#define GPIO14_FUN_ROW_I_6               21
+#define GPIO14_FUN_COL_O_14              22
+#define GPIO14_FUN_CAM_RESET             23
+/* GPIO15 function definition */
+#define GPIO15_FUN_CLK_OUT_1             0
+#define GPIO15_FUN_BT_ABORT              1
+#define GPIO15_FUN_UNUSED2               2
+#define GPIO15_FUN_I2S0_RCLK_O_I2S0_DI   3
+#define GPIO15_FUN_SPI_0_SCLK            4
+#define GPIO15_FUN_I2C0_SDA              6
+#define GPIO15_FUN_UART_SIG7_UART_SIG3   7
+#define GPIO15_FUN_PWM_CH0               8
+#define GPIO15_FUN_UNUSED9               9
+#define GPIO15_FUN_GPIP_CH_1_ATEST_OUT_1 10
+#define GPIO15_FUN_REG_GPIO_15           11
+#define GPIO15_FUN_RF_TEST_10            12
+#define GPIO15_FUN_SCAN_OUT_1            13
+#define GPIO15_FUN_E21_TDO_E21_TDI       14
+#define GPIO15_FUN_DEBUG_11              15
+#define GPIO15_FUN_FEM_GPIO_0            16
+#define GPIO15_FUN_USB_TX_DN_USB_RX_DN   17
+#define GPIO15_FUN_VIP                   18
+#define GPIO15_FUN_UNUSED19              19
+#define GPIO15_FUN_QDEC2_A               20
+#define GPIO15_FUN_ROW_I_7               21
+#define GPIO15_FUN_COL_O_15              22
+#define GPIO15_FUN_CAM_PWRDN             23
+/* GPIO16 function definition */
+#define GPIO16_FUN_CLK_OUT_0             0
+#define GPIO16_FUN_BT_ACTIVE             1
+#define GPIO16_FUN_UNUSED2               2
+#define GPIO16_FUN_I2S0_BCLK             3
+#define GPIO16_FUN_SPI_0_MOSI_SPI_0_MISO 4
+#define GPIO16_FUN_I2C0_SCL              6
+#define GPIO16_FUN_UART_SIG0_UART_SIG4   7
+#define GPIO16_FUN_PWM_CH1               8
+#define GPIO16_FUN_UNUSED9               9
+#define GPIO16_FUN_UNUSED10              10
+#define GPIO16_FUN_REG_GPIO_16           11
+#define GPIO16_FUN_RF_TEST_11            12
+#define GPIO16_FUN_UNUSED13              13
+#define GPIO16_FUN_E21_TMS_E21_TCK       14
+#define GPIO16_FUN_DEBUG_12              15
+#define GPIO16_FUN_FEM_GPIO_1            16
+#define GPIO16_FUN_USB_TX_OE             17
+#define GPIO16_FUN_VIM                   18
+#define GPIO16_FUN_UNUSED19              19
+#define GPIO16_FUN_QDEC2_B               20
+#define GPIO16_FUN_ROW_I_0               21
+#define GPIO16_FUN_COL_O_16              22
+#define GPIO16_FUN_CAM_REF_CLK           23
+/* GPIO17 function definition */
+#define GPIO17_FUN_CLK_OUT_1             0
+#define GPIO17_FUN_BT_PRI                1
+#define GPIO17_FUN_SF_IO_0_SF2_CS2       2
+#define GPIO17_FUN_I2S0_FS               3
+#define GPIO17_FUN_SPI_0_MISO_SPI_0_MOSI 4
+#define GPIO17_FUN_I2C0_SDA              6
+#define GPIO17_FUN_UART_SIG1_UART_SIG5   7
+#define GPIO17_FUN_PWM_CH2               8
+#define GPIO17_FUN_PIX_DAT4              9
+#define GPIO17_FUN_GPIP_CH_2_PSW_IRRCV   10
+#define GPIO17_FUN_REG_GPIO_17           11
+#define GPIO17_FUN_RF_TEST_12            12
+#define GPIO17_FUN_SCAN_OUT_2            13
+#define GPIO17_FUN_E21_TDI_E21_TDO       14
+#define GPIO17_FUN_DEBUG_13              15
+#define GPIO17_FUN_FEM_GPIO_2            16
+#define GPIO17_FUN_USB_TX_DP_USB_RX_DP   17
+#define GPIO17_FUN_RCV                   18
+#define GPIO17_FUN_UNUSED19              19
+#define GPIO17_FUN_QDEC2_LED             20
+#define GPIO17_FUN_ROW_I_1               21
+#define GPIO17_FUN_COL_O_17              22
+#define GPIO17_FUN_CAM_RESET             23
+/* GPIO18 function definition */
+#define GPIO18_FUN_CLK_OUT_0           0
+#define GPIO18_FUN_BT_ABORT            1
+#define GPIO18_FUN_SF_IO_1             2
+#define GPIO18_FUN_I2S0_DIO_I2S0_DO    3
+#define GPIO18_FUN_SPI_0_SS            4
+#define GPIO18_FUN_I2C0_SCL            6
+#define GPIO18_FUN_UART_SIG2_UART_SIG6 7
+#define GPIO18_FUN_PWM_CH3             8
+#define GPIO18_FUN_PIX_DAT5            9
+#define GPIO18_FUN_GPIP_CH_8           10
+#define GPIO18_FUN_REG_GPIO_18         11
+#define GPIO18_FUN_RF_TEST_13          12
+#define GPIO18_FUN_UNUSED13            13
+#define GPIO18_FUN_E21_TCK_E21_TMS     14
+#define GPIO18_FUN_M_CCI_CLK_DEBUG_14  15
+#define GPIO18_FUN_FEM_GPIO_3          16
+#define GPIO18_FUN_USB_SUS_EXT         17
+#define GPIO18_FUN_USB_SUS             18
+#define GPIO18_FUN_RMII_MDC            19
+#define GPIO18_FUN_QDEC0_A             20
+#define GPIO18_FUN_ROW_I_2             21
+#define GPIO18_FUN_COL_O_18            22
+#define GPIO18_FUN_CAM_PWRDN           23
+/* GPIO19 function definition */
+#define GPIO19_FUN_CLK_OUT_1           0
+#define GPIO19_FUN_BT_ACTIVE           1
+#define GPIO19_FUN_SF_CS               2
+#define GPIO19_FUN_I2S0_RCLK_O_I2S0_DI 3
+#define GPIO19_FUN_SPI_0_SCLK          4
+#define GPIO19_FUN_I2C0_SDA            6
+#define GPIO19_FUN_UART_SIG3_UART_SIG7 7
+#define GPIO19_FUN_PWM_CH4             8
+#define GPIO19_FUN_PIX_DAT6            9
+#define GPIO19_FUN_GPIP_CH_9           10
+#define GPIO19_FUN_REG_GPIO_19         11
+#define GPIO19_FUN_RF_TEST_14          12
+#define GPIO19_FUN_UNUSED13            13
+#define GPIO19_FUN_E21_TDO_E21_TDI     14
+#define GPIO19_FUN_M_CCI_CS_DEBUG_15   15
+#define GPIO19_FUN_FEM_GPIO_4          16
+#define GPIO19_FUN_USB_ENUM_EXT        17
+#define GPIO19_FUN_USB_ENUM            18
+#define GPIO19_FUN_RMII_MDIO           19
+#define GPIO19_FUN_QDEC0_B             20
+#define GPIO19_FUN_ROW_I_3             21
+#define GPIO19_FUN_COL_O_19            22
+#define GPIO19_FUN_CAM_REF_CLK         23
+/* GPIO20 function definition */
+#define GPIO20_FUN_CLK_OUT_0             0
+#define GPIO20_FUN_BT_PRI                1
+#define GPIO20_FUN_SF_IO_3               2
+#define GPIO20_FUN_I2S0_BCLK             3
+#define GPIO20_FUN_SPI_0_MOSI_SPI_0_MISO 4
+#define GPIO20_FUN_I2C0_SCL              6
+#define GPIO20_FUN_UART_SIG4_UART_SIG0   7
+#define GPIO20_FUN_PWM_CH0               8
+#define GPIO20_FUN_PIX_DAT7              9
+#define GPIO20_FUN_GPIP_CH_10            10
+#define GPIO20_FUN_REG_GPIO_20           11
+#define GPIO20_FUN_RF_TEST_15            12
+#define GPIO20_FUN_UNUSED13              13
+#define GPIO20_FUN_E21_TMS_E21_TCK       14
+#define GPIO20_FUN_M_CCI_DI_DEBUG_16     15
+#define GPIO20_FUN_FEM_GPIO_0            16
+#define GPIO20_FUN_USB_TX_DN_USB_RX_DN   17
+#define GPIO20_FUN_USB_OEB               18
+#define GPIO20_FUN_RMII_RXERR            19
+#define GPIO20_FUN_QDEC0_LED             20
+#define GPIO20_FUN_ROW_I_4               21
+#define GPIO20_FUN_COL_O_0               22
+#define GPIO20_FUN_CAM_RESET             23
+/* GPIO21 function definition */
+#define GPIO21_FUN_CLK_OUT_1             0
+#define GPIO21_FUN_BT_ABORT              1
+#define GPIO21_FUN_SF_CLK                2
+#define GPIO21_FUN_I2S0_FS               3
+#define GPIO21_FUN_SPI_0_MISO_SPI_0_MOSI 4
+#define GPIO21_FUN_I2C0_SDA              6
+#define GPIO21_FUN_UART_SIG5_UART_SIG1   7
+#define GPIO21_FUN_PWM_CH1               8
+#define GPIO21_FUN_UNUSED9               9
+#define GPIO21_FUN_GPIP_CH_11            10
+#define GPIO21_FUN_REG_GPIO_21           11
+#define GPIO21_FUN_RF_TEST_16            12
+#define GPIO21_FUN_UNUSED13              13
+#define GPIO21_FUN_E21_TDI_E21_TDO       14
+#define GPIO21_FUN_M_CCI_DO_DEBUG_17     15
+#define GPIO21_FUN_FEM_GPIO_1            16
+#define GPIO21_FUN_USB_TX_OE             17
+#define GPIO21_FUN_VOP                   18
+#define GPIO21_FUN_RMII_TX_EN            19
+#define GPIO21_FUN_QDEC1_A               20
+#define GPIO21_FUN_ROW_I_5               21
+#define GPIO21_FUN_COL_O_1               22
+#define GPIO21_FUN_CAM_PWRDN             23
+/* GPIO22 function definition */
+#define GPIO22_FUN_CLK_OUT_0           0
+#define GPIO22_FUN_BT_ACTIVE           1
+#define GPIO22_FUN_SF_IO_2             2
+#define GPIO22_FUN_I2S0_DIO_I2S0_DO    3
+#define GPIO22_FUN_SPI_0_SS            4
+#define GPIO22_FUN_I2C0_SCL            6
+#define GPIO22_FUN_UART_SIG6_UART_SIG2 7
+#define GPIO22_FUN_PWM_CH2             8
+#define GPIO22_FUN_UNUSED9             9
+#define GPIO22_FUN_LEDDRV_0            10
+#define GPIO22_FUN_REG_GPIO_22         11
+#define GPIO22_FUN_RF_TEST_17          12
+#define GPIO22_FUN_UNUSED13            13
+#define GPIO22_FUN_E21_TCK_E21_TMS     14
+#define GPIO22_FUN_DEBUG_18            15
+#define GPIO22_FUN_FEM_GPIO_2          16
+#define GPIO22_FUN_USB_TX_DP_USB_RX_DP 17
+#define GPIO22_FUN_VOM                 18
+#define GPIO22_FUN_RMII_RX_DV          19
+#define GPIO22_FUN_QDEC1_B             20
+#define GPIO22_FUN_ROW_I_6             21
+#define GPIO22_FUN_COL_O_2             22
+#define GPIO22_FUN_CAM_REF_CLK         23
+/* GPIO23 function definition */
+#define GPIO23_FUN_CLK_OUT_1                 0
+#define GPIO23_FUN_BT_PRI                    1
+#define GPIO23_FUN_SF2_IO_2_SF3_CS2          2
+#define GPIO23_FUN_I2S0_RCLK_O_I2S0_DI       3
+#define GPIO23_FUN_SPI_0_SCLK                4
+#define GPIO23_FUN_I2C0_SDA                  6
+#define GPIO23_FUN_UART_SIG7_UART_SIG3       7
+#define GPIO23_FUN_PWM_CH3                   8
+#define GPIO23_FUN_PIX_DAT4                  9
+#define GPIO23_FUN_LEDDRV_1_FLASH_PULL_OUT_0 10
+#define GPIO23_FUN_REG_GPIO_23               11
+#define GPIO23_FUN_RF_TEST_18                12
+#define GPIO23_FUN_UNUSED13                  13
+#define GPIO23_FUN_E21_TDO_E21_TDI           14
+#define GPIO23_FUN_DEBUG_19                  15
+#define GPIO23_FUN_FEM_GPIO_3                16
+#define GPIO23_FUN_USB_SUS_EXT               17
+#define GPIO23_FUN_BD                        18
+#define GPIO23_FUN_UNUSED19                  19
+#define GPIO23_FUN_QDEC1_LED                 20
+#define GPIO23_FUN_ROW_I_7                   21
+#define GPIO23_FUN_COL_O_3                   22
+#define GPIO23_FUN_CAM_RESET                 23
+/* GPIO24 function definition */
+#define GPIO24_FUN_CLK_OUT_0             0
+#define GPIO24_FUN_BT_ABORT              1
+#define GPIO24_FUN_SF2_IO_1              2
+#define GPIO24_FUN_I2S0_BCLK             3
+#define GPIO24_FUN_SPI_0_MOSI_SPI_0_MISO 4
+#define GPIO24_FUN_I2C0_SCL              6
+#define GPIO24_FUN_UART_SIG0_UART_SIG4   7
+#define GPIO24_FUN_PWM_CH4               8
+#define GPIO24_FUN_PIX_DAT5              9
+#define GPIO24_FUN_FLASH_PULL_OUT_1      10
+#define GPIO24_FUN_REG_GPIO_24           11
+#define GPIO24_FUN_RF_TEST_19            12
+#define GPIO24_FUN_UNUSED13              13
+#define GPIO24_FUN_E21_TMS_E21_TCK       14
+#define GPIO24_FUN_DEBUG_20              15
+#define GPIO24_FUN_FEM_GPIO_4            16
+#define GPIO24_FUN_USB_ENUM_EXT          17
+#define GPIO24_FUN_VIP                   18
+#define GPIO24_FUN_RMII_MDC              19
+#define GPIO24_FUN_QDEC2_A               20
+#define GPIO24_FUN_ROW_I_0               21
+#define GPIO24_FUN_COL_O_4               22
+#define GPIO24_FUN_CAM_PWRDN             23
+/* GPIO25 function definition */
+#define GPIO25_FUN_CLK_OUT_1             0
+#define GPIO25_FUN_BT_ACTIVE             1
+#define GPIO25_FUN_SF2_CS                2
+#define GPIO25_FUN_I2S0_FS               3
+#define GPIO25_FUN_SPI_0_MISO_SPI_0_MOSI 4
+#define GPIO25_FUN_I2C0_SDA              6
+#define GPIO25_FUN_UART_SIG1_UART_SIG5   7
+#define GPIO25_FUN_PWM_CH0               8
+#define GPIO25_FUN_PIX_DAT6              9
+#define GPIO25_FUN_FLASH_PULL_OUT_2      10
+#define GPIO25_FUN_REG_GPIO_25           11
+#define GPIO25_FUN_RF_TEST_20            12
+#define GPIO25_FUN_UNUSED13              13
+#define GPIO25_FUN_E21_TDI_E21_TDO       14
+#define GPIO25_FUN_DEBUG_21              15
+#define GPIO25_FUN_FEM_GPIO_0            16
+#define GPIO25_FUN_USB_TX_DN_USB_RX_DN   17
+#define GPIO25_FUN_VIM                   18
+#define GPIO25_FUN_RMII_MDIO             19
+#define GPIO25_FUN_QDEC2_B               20
+#define GPIO25_FUN_ROW_I_1               21
+#define GPIO25_FUN_COL_O_5               22
+#define GPIO25_FUN_CAM_REF_CLK           23
+/* GPIO26 function definition */
+#define GPIO26_FUN_CLK_OUT_0           0
+#define GPIO26_FUN_BT_PRI              1
+#define GPIO26_FUN_SF2_IO_3            2
+#define GPIO26_FUN_I2S0_DIO_I2S0_DO    3
+#define GPIO26_FUN_SPI_0_SS            4
+#define GPIO26_FUN_I2C0_SCL            6
+#define GPIO26_FUN_UART_SIG2_UART_SIG6 7
+#define GPIO26_FUN_PWM_CH1             8
+#define GPIO26_FUN_PIX_DAT7            9
+#define GPIO26_FUN_FLASH_PULL_OUT_3    10
+#define GPIO26_FUN_REG_GPIO_26         11
+#define GPIO26_FUN_RF_TEST_21          12
+#define GPIO26_FUN_UNUSED13            13
+#define GPIO26_FUN_E21_TCK_E21_TMS     14
+#define GPIO26_FUN_DEBUG_22            15
+#define GPIO26_FUN_FEM_GPIO_1          16
+#define GPIO26_FUN_USB_TX_OE           17
+#define GPIO26_FUN_RCV                 18
+#define GPIO26_FUN_RMII_RXERR          19
+#define GPIO26_FUN_QDEC2_LED           20
+#define GPIO26_FUN_ROW_I_2             21
+#define GPIO26_FUN_COL_O_6             22
+#define GPIO26_FUN_CAM_RESET           23
+/* GPIO27 function definition */
+#define GPIO27_FUN_CLK_OUT_1           0
+#define GPIO27_FUN_BT_ABORT            1
+#define GPIO27_FUN_SF2_CLK             2
+#define GPIO27_FUN_I2S0_RCLK_O_I2S0_DI 3
+#define GPIO27_FUN_SPI_0_SCLK          4
+#define GPIO27_FUN_I2C0_SDA            6
+#define GPIO27_FUN_UART_SIG3_UART_SIG7 7
+#define GPIO27_FUN_PWM_CH2             8
+#define GPIO27_FUN_UNUSED9             9
+#define GPIO27_FUN_FLASH_PULL_OUT_4    10
+#define GPIO27_FUN_REG_GPIO_27         11
+#define GPIO27_FUN_RF_TEST_22          12
+#define GPIO27_FUN_UNUSED13            13
+#define GPIO27_FUN_E21_TDO_E21_TDI     14
+#define GPIO27_FUN_DEBUG_23            15
+#define GPIO27_FUN_FEM_GPIO_2          16
+#define GPIO27_FUN_USB_TX_DP_USB_RX_DP 17
+#define GPIO27_FUN_USB_SUS             18
+#define GPIO27_FUN_RMII_TX_EN          19
+#define GPIO27_FUN_QDEC0_A             20
+#define GPIO27_FUN_ROW_I_3             21
+#define GPIO27_FUN_COL_O_7             22
+#define GPIO27_FUN_CAM_PWRDN           23
+/* GPIO28 function definition */
+#define GPIO28_FUN_CLK_OUT_0             0
+#define GPIO28_FUN_BT_ACTIVE             1
+#define GPIO28_FUN_SF2_IO_0              2
+#define GPIO28_FUN_I2S0_BCLK             3
+#define GPIO28_FUN_SPI_0_MOSI_SPI_0_MISO 4
+#define GPIO28_FUN_I2C0_SCL              6
+#define GPIO28_FUN_UART_SIG4_UART_SIG0   7
+#define GPIO28_FUN_PWM_CH3               8
+#define GPIO28_FUN_PIX_DAT4              9
+#define GPIO28_FUN_FLASH_PULL_OUT_5      10
+#define GPIO28_FUN_REG_GPIO_28           11
+#define GPIO28_FUN_RF_TEST_23            12
+#define GPIO28_FUN_UNUSED13              13
+#define GPIO28_FUN_E21_TMS_E21_TCK       14
+#define GPIO28_FUN_DEBUG_24              15
+#define GPIO28_FUN_FEM_GPIO_3            16
+#define GPIO28_FUN_USB_SUS_EXT           17
+#define GPIO28_FUN_USB_ENUM              18
+#define GPIO28_FUN_RMII_RX_DV            19
+#define GPIO28_FUN_QDEC0_B               20
+#define GPIO28_FUN_ROW_I_4               21
+#define GPIO28_FUN_COL_O_8               22
+#define GPIO28_FUN_CAM_REF_CLK           23
+/* GPIO29 function definition */
+#define GPIO29_FUN_CLK_OUT_1             0
+#define GPIO29_FUN_BT_PRI                1
+#define GPIO29_FUN_UNUSED2               2
+#define GPIO29_FUN_I2S0_FS               3
+#define GPIO29_FUN_SPI_0_MISO_SPI_0_MOSI 4
+#define GPIO29_FUN_I2C0_SDA              6
+#define GPIO29_FUN_UART_SIG5_UART_SIG1   7
+#define GPIO29_FUN_PWM_CH4               8
+#define GPIO29_FUN_PIX_DAT5              9
+#define GPIO29_FUN_UNUSED10              10
+#define GPIO29_FUN_REG_GPIO_29           11
+#define GPIO29_FUN_RF_TEST_24            12
+#define GPIO29_FUN_UNUSED13              13
+#define GPIO29_FUN_E21_TDI_E21_TDO       14
+#define GPIO29_FUN_DEBUG_25              15
+#define GPIO29_FUN_FEM_GPIO_4            16
+#define GPIO29_FUN_USB_ENUM_EXT          17
+#define GPIO29_FUN_USB_OEB               18
+#define GPIO29_FUN_UNUSED19              19
+#define GPIO29_FUN_QDEC0_LED             20
+#define GPIO29_FUN_ROW_I_5               21
+#define GPIO29_FUN_COL_O_9               22
+#define GPIO29_FUN_CAM_RESET             23
+/* GPIO30 function definition */
+#define GPIO30_FUN_CLK_OUT_0           0
+#define GPIO30_FUN_BT_ABORT            1
+#define GPIO30_FUN_UNUSED2             2
+#define GPIO30_FUN_I2S0_DIO_I2S0_DO    3
+#define GPIO30_FUN_SPI_0_SS            4
+#define GPIO30_FUN_I2C0_SCL            6
+#define GPIO30_FUN_UART_SIG6_UART_SIG2 7
+#define GPIO30_FUN_PWM_CH0             8
+#define GPIO30_FUN_PIX_DAT6            9
+#define GPIO30_FUN_UNUSED10            10
+#define GPIO30_FUN_REG_GPIO_30         11
+#define GPIO30_FUN_RF_TEST_25          12
+#define GPIO30_FUN_UNUSED13            13
+#define GPIO30_FUN_E21_TCK_E21_TMS     14
+#define GPIO30_FUN_DEBUG_26            15
+#define GPIO30_FUN_FEM_GPIO_0          16
+#define GPIO30_FUN_USB_TX_DN_USB_RX_DN 17
+#define GPIO30_FUN_VOP                 18
+#define GPIO30_FUN_UNUSED19            19
+#define GPIO30_FUN_QDEC1_A             20
+#define GPIO30_FUN_ROW_I_6             21
+#define GPIO30_FUN_COL_O_10            22
+#define GPIO30_FUN_CAM_PWRDN           23
+/* GPIO31 function definition */
+#define GPIO31_FUN_CLK_OUT_1           0
+#define GPIO31_FUN_BT_ACTIVE           1
+#define GPIO31_FUN_UNUSED2             2
+#define GPIO31_FUN_I2S0_RCLK_O_I2S0_DI 3
+#define GPIO31_FUN_SPI_0_SCLK          4
+#define GPIO31_FUN_I2C0_SDA            6
+#define GPIO31_FUN_UART_SIG7_UART_SIG3 7
+#define GPIO31_FUN_PWM_CH1             8
+#define GPIO31_FUN_PIX_DAT7            9
+#define GPIO31_FUN_UNUSED10            10
+#define GPIO31_FUN_REG_GPIO_31         11
+#define GPIO31_FUN_RF_TEST_26          12
+#define GPIO31_FUN_UNUSED13            13
+#define GPIO31_FUN_E21_TDO_E21_TDI     14
+#define GPIO31_FUN_DEBUG_27            15
+#define GPIO31_FUN_FEM_GPIO_1          16
+#define GPIO31_FUN_USB_TX_OE           17
+#define GPIO31_FUN_VOM                 18
+#define GPIO31_FUN_UNUSED19            19
+#define GPIO31_FUN_QDEC1_B             20
+#define GPIO31_FUN_ROW_I_7             21
+#define GPIO31_FUN_COL_O_11            22
+#define GPIO31_FUN_CAM_REF_CLK         23
+
+#endif /*__BL702_GPIO_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_hbn.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_hbn.h
new file mode 100644
index 00000000..0eddd7d0
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_hbn.h
@@ -0,0 +1,564 @@
+/**
+  ******************************************************************************
+  * @file    bl702_hbn.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_HBN_H__
+#define __BL702_HBN_H__
+
+#include "hbn_reg.h"
+#include "bl702_aon.h"
+#include "bl702_sflash.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  HBN
+ *  @{
+ */
+
+/** @defgroup  HBN_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief HBN PIR interrupt configuration type definition
+ */
+typedef struct
+{
+    BL_Fun_Type lowIntEn;  /*!< Low will trigger interrupt */
+    BL_Fun_Type highIntEn; /*!< High will trigger interrupt */
+} HBN_PIR_INT_CFG_Type;
+
+/**
+ *  @brief HBN PIR low pass filter type definition
+ */
+typedef enum {
+    HBN_PIR_LPF_DIV1, /*!< HBN PIR lpf div 1 */
+    HBN_PIR_LPF_DIV2, /*!< HBN PIR lpf div 2 */
+} HBN_PIR_LPF_Type;
+
+/**
+ *  @brief HBN PIR high pass filter type definition
+ */
+typedef enum {
+    HBN_PIR_HPF_METHOD0, /*!< HBN PIR hpf calc method 0, 1-z^-1 */
+    HBN_PIR_HPF_METHOD1, /*!< HBN PIR hpf calc method 1, 1-z^-2 */
+    HBN_PIR_HPF_METHOD2, /*!< HBN PIR hpf calc method 2, 1-z^-3 */
+} HBN_PIR_HPF_Type;
+
+/**
+ *  @brief HBN BOR threshold type definition
+ */
+typedef enum {
+    HBN_BOR_THRES_2P0V, /*!< BOR threshold 2.0V */
+    HBN_BOR_THRES_2P4V, /*!< BOR threshold 2.4V */
+} HBN_BOR_THRES_Type;
+
+/**
+ *  @brief HBN BOR mode type definition
+ */
+typedef enum {
+    HBN_BOR_MODE_POR_INDEPENDENT, /*!< POR is independent of BOR */
+    HBN_BOR_MODE_POR_RELEVANT,    /*!< POR is relevant to BOR */
+} HBN_BOR_MODE_Type;
+
+/**
+ *  @brief HBN 32K clock type definition
+ */
+typedef enum {
+    HBN_32K_RC = 0,  /*!< HBN use rc 32k */
+    HBN_32K_XTAL,    /*!< HBN use xtal 32k */
+    HBN_32K_DIG = 3, /*!< HBN use dig 32k */
+} HBN_32K_CLK_Type;
+
+/**
+ *  @brief HBN xclk clock type definition
+ */
+typedef enum {
+    HBN_XCLK_CLK_RC32M, /*!< use RC32M as xclk clock */
+    HBN_XCLK_CLK_XTAL,  /*!< use XTAL as xclk clock */
+} HBN_XCLK_CLK_Type;
+
+/**
+ *  @brief HBN root clock type definition
+ */
+typedef enum {
+    HBN_ROOT_CLK_RC32M, /*!< use RC32M as root clock */
+    HBN_ROOT_CLK_XTAL,  /*!< use XTAL as root clock */
+    HBN_ROOT_CLK_DLL,   /*!< use DLL as root clock */
+} HBN_ROOT_CLK_Type;
+
+/**
+ *  @brief HBN UART clock type definition
+ */
+typedef enum {
+    HBN_UART_CLK_FCLK = 0, /*!< Select FCLK as UART clock */
+    HBN_UART_CLK_96M,      /*!< Select 96M as UART clock */
+} HBN_UART_CLK_Type;
+
+/**
+ *  @brief HBN RTC interrupt delay type definition
+ */
+typedef enum {
+    HBN_RTC_INT_DELAY_32T = 0, /*!< HBN RTC interrupt delay 32T */
+    HBN_RTC_INT_DELAY_0T = 1,  /*!< HBN RTC interrupt delay 0T */
+} HBN_RTC_INT_Delay_Type;
+
+/**
+ *  @brief HBN interrupt type definition
+ */
+typedef enum {
+    HBN_INT_GPIO9 = 0,   /*!< HBN interrupt type: GPIO9 */
+    HBN_INT_GPIO10 = 1,  /*!< HBN interrupt type: GPIO10 */
+    HBN_INT_GPIO11 = 2,  /*!< HBN interrupt type: GPIO11 */
+    HBN_INT_GPIO12 = 3,  /*!< HBN interrupt type: GPIO12 */
+    HBN_INT_GPIO13 = 4,  /*!< HBN interrupt type: GPIO13 */
+    HBN_INT_RTC = 16,    /*!< HBN interrupt type: RTC */
+    HBN_INT_PIR,         /*!< HBN interrupt type: PIR */
+    HBN_INT_BOR,         /*!< HBN interrupt type: BOR */
+    HBN_INT_ACOMP0 = 20, /*!< HBN interrupt type: ACOMP0 */
+    HBN_INT_ACOMP1 = 22, /*!< HBN interrupt type: ACOMP1 */
+} HBN_INT_Type;
+
+/**
+ *  @brief HBN acomp interrupt type definition
+ */
+typedef enum {
+    HBN_ACOMP_INT_EDGE_POSEDGE = 0, /*!< HBN acomp interrupt edge posedge */
+    HBN_ACOMP_INT_EDGE_NEGEDGE = 1, /*!< HBN acomp interrupt edge negedge */
+} HBN_ACOMP_INT_EDGE_Type;
+
+/**
+ *  @brief HBN reset event type definition
+ */
+typedef enum {
+    HBN_RST_EVENT_POR_OUT,   /*!< por_out event */
+    HBN_RST_EVENT_EXT_RST_N, /*!< ext_rst_n event */
+    HBN_RST_EVENT_SW_RST,    /*!< sw_rst event */
+    HBN_RST_EVENT_PWR_RST_N, /*!< pwr_rst_n event */
+    HBN_RST_EVENT_BOR_OUT,   /*!< bor_out_ event */
+} HBN_RST_EVENT_Type;
+
+/**
+ *  @brief HBN GPIO interrupt trigger type definition
+ */
+typedef enum {
+    HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE,  /*!< HBN GPIO INT trigger type: sync falling edge trigger */
+    HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE,   /*!< HBN GPIO INT trigger type: sync rising edge trigger */
+    HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL,     /*!< HBN GPIO INT trigger type: sync low level trigger */
+    HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL,    /*!< HBN GPIO INT trigger type: sync high level trigger */
+    HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE, /*!< HBN GPIO INT trigger type: async falling edge trigger */
+    HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE,  /*!< HBN GPIO INT trigger type: async rising edge trigger */
+    HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL,    /*!< HBN GPIO INT trigger type: async low level trigger */
+    HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL,   /*!< HBN GPIO INT trigger type: async high level trigger */
+} HBN_GPIO_INT_Trigger_Type;
+
+/**
+ *  @brief HBN OUT0 interrupt type definition
+ */
+typedef enum {
+    HBN_OUT0_INT_GPIO9 = 0,  /*!< HBN out 0 interrupt type: GPIO9 */
+    HBN_OUT0_INT_GPIO10 = 1, /*!< HBN out 0 interrupt type: GPIO10 */
+    HBN_OUT0_INT_GPIO11 = 2, /*!< HBN out 0 interrupt type: GPIO11 */
+    HBN_OUT0_INT_GPIO12 = 3, /*!< HBN out 0 interrupt type: GPIO12 */
+    HBN_OUT0_INT_GPIO13 = 4, /*!< HBN out 0 interrupt type: GPIO13 */
+    HBN_OUT0_INT_RTC,        /*!< HBN out 0 interrupt type: RTC */
+    HBN_OUT0_MAX,            /*!< HBN out 0 max num */
+} HBN_OUT0_INT_Type;
+
+/**
+ *  @brief HBN OUT0 interrupt type definition
+ */
+typedef enum {
+    HBN_OUT1_INT_PIR,    /*!< HBN out 1 interrupt type: PIR */
+    HBN_OUT1_INT_BOR,    /*!< HBN out 1 interrupt type: BOR */
+    HBN_OUT1_INT_ACOMP0, /*!< HBN out 1 interrupt type: ACOMP0 */
+    HBN_OUT1_INT_ACOMP1, /*!< HBN out 1 interrupt type: ACOMP1 */
+    HBN_OUT1_MAX,        /*!< HBN out 1 max num */
+} HBN_OUT1_INT_Type;
+
+/**
+ *  @brief HBN LDO level type definition
+ */
+typedef enum {
+    HBN_LDO_LEVEL_0P60V = 0,  /*!< HBN LDO voltage 0.60V */
+    HBN_LDO_LEVEL_0P65V = 1,  /*!< HBN LDO voltage 0.65V */
+    HBN_LDO_LEVEL_0P70V = 2,  /*!< HBN LDO voltage 0.70V */
+    HBN_LDO_LEVEL_0P75V = 3,  /*!< HBN LDO voltage 0.75V */
+    HBN_LDO_LEVEL_0P80V = 4,  /*!< HBN LDO voltage 0.80V */
+    HBN_LDO_LEVEL_0P85V = 5,  /*!< HBN LDO voltage 0.85V */
+    HBN_LDO_LEVEL_0P90V = 6,  /*!< HBN LDO voltage 0.90V */
+    HBN_LDO_LEVEL_0P95V = 7,  /*!< HBN LDO voltage 0.95V */
+    HBN_LDO_LEVEL_1P00V = 8,  /*!< HBN LDO voltage 1.00V */
+    HBN_LDO_LEVEL_1P05V = 9,  /*!< HBN LDO voltage 1.05V */
+    HBN_LDO_LEVEL_1P10V = 10, /*!< HBN LDO voltage 1.10V */
+    HBN_LDO_LEVEL_1P15V = 11, /*!< HBN LDO voltage 1.15V */
+    HBN_LDO_LEVEL_1P20V = 12, /*!< HBN LDO voltage 1.20V */
+    HBN_LDO_LEVEL_1P25V = 13, /*!< HBN LDO voltage 1.25V */
+    HBN_LDO_LEVEL_1P30V = 14, /*!< HBN LDO voltage 1.30V */
+    HBN_LDO_LEVEL_1P35V = 15, /*!< HBN LDO voltage 1.35V */
+} HBN_LDO_LEVEL_Type;
+
+/**
+ *  @brief HBN LDO11RT drive strength type definition
+ */
+typedef enum {
+    HBN_LDO11RT_DRIVE_STRENGTH_5_50UA = 0,   /*!< HBN LDO11RT drive strength 0: 5uA to 50uA */
+    HBN_LDO11RT_DRIVE_STRENGTH_10_100UA = 1, /*!< HBN LDO11RT drive strength 1: 10uA to 100uA */
+    HBN_LDO11RT_DRIVE_STRENGTH_15_150UA = 2, /*!< HBN LDO11RT drive strength 2: 15uA to 150uA */
+    HBN_LDO11RT_DRIVE_STRENGTH_25_250UA = 3, /*!< HBN LDO11RT drive strength 3: 25uA to 250uA */
+} HBN_LDO11RT_DRIVE_STRENGTH_Type;
+
+/**
+ *  @brief HBN level type definition
+ */
+typedef enum {
+    HBN_LEVEL_0, /*!< HBN pd_core */
+    HBN_LEVEL_1, /*!< HBN pd_aon_hbncore + pd_core */
+    HBN_LEVEL_2, /*!< HBN pd_aon_hbncore + pd_core */
+    HBN_LEVEL_3, /*!< HBN pd_aon_hbnrtc + pd_aon_hbncore + pd_core */
+} HBN_LEVEL_Type;
+
+/**
+ *  @brief HBN BOR configuration type definition
+ */
+typedef struct
+{
+    uint8_t enableBor;      /*!< Enable BOR or not */
+    uint8_t enableBorInt;   /*!< Enable BOR interrupt or not */
+    uint8_t borThreshold;   /*!< BOR threshold */
+    uint8_t enablePorInBor; /*!< Enable POR when BOR occure or not */
+} HBN_BOR_CFG_Type;
+
+/**
+ *  @brief HBN APP configuration type definition
+ */
+typedef struct
+{
+    uint8_t useXtal32k;                     /*!< Whether use xtal 32K as 32K clock source,otherwise use rc32k */
+    uint32_t sleepTime;                     /*!< HBN sleep time */
+    uint8_t gpioWakeupSrc;                  /*!< GPIO Wakeup source */
+    HBN_GPIO_INT_Trigger_Type gpioTrigType; /*!< GPIO Triger type */
+    SPI_Flash_Cfg_Type *flashCfg;           /*!< Flash config pointer, used when power down flash */
+    uint8_t flashPinCfg;                    /*!< 0 ext flash 23-28, 1 internal flash 23-28, 2 internal flash 23-28, 3 ext flash 17-22 */
+    HBN_LEVEL_Type hbnLevel;                /*!< HBN level */
+    HBN_LDO_LEVEL_Type ldoLevel;            /*!< LDO level */
+} HBN_APP_CFG_Type;
+
+/*@} end of group HBN_Public_Types */
+
+/** @defgroup  HBN_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  HBN_PIR_LPF_TYPE
+ *  @{
+ */
+#define IS_HBN_PIR_LPF_TYPE(type) (((type) == HBN_PIR_LPF_DIV1) || \
+                                   ((type) == HBN_PIR_LPF_DIV2))
+
+/** @defgroup  HBN_PIR_HPF_TYPE
+ *  @{
+ */
+#define IS_HBN_PIR_HPF_TYPE(type) (((type) == HBN_PIR_HPF_METHOD0) || \
+                                   ((type) == HBN_PIR_HPF_METHOD1) || \
+                                   ((type) == HBN_PIR_HPF_METHOD2))
+
+/** @defgroup  HBN_BOR_THRES_TYPE
+ *  @{
+ */
+#define IS_HBN_BOR_THRES_TYPE(type) (((type) == HBN_BOR_THRES_2P0V) || \
+                                     ((type) == HBN_BOR_THRES_2P4V))
+
+/** @defgroup  HBN_BOR_MODE_TYPE
+ *  @{
+ */
+#define IS_HBN_BOR_MODE_TYPE(type) (((type) == HBN_BOR_MODE_POR_INDEPENDENT) || \
+                                    ((type) == HBN_BOR_MODE_POR_RELEVANT))
+
+/** @defgroup  HBN_32K_CLK_TYPE
+ *  @{
+ */
+#define IS_HBN_32K_CLK_TYPE(type) (((type) == HBN_32K_RC) ||   \
+                                   ((type) == HBN_32K_XTAL) || \
+                                   ((type) == HBN_32K_DIG))
+
+/** @defgroup  HBN_XCLK_CLK_TYPE
+ *  @{
+ */
+#define IS_HBN_XCLK_CLK_TYPE(type) (((type) == HBN_XCLK_CLK_RC32M) || \
+                                    ((type) == HBN_XCLK_CLK_XTAL))
+
+/** @defgroup  HBN_ROOT_CLK_TYPE
+ *  @{
+ */
+#define IS_HBN_ROOT_CLK_TYPE(type) (((type) == HBN_ROOT_CLK_RC32M) || \
+                                    ((type) == HBN_ROOT_CLK_XTAL) ||  \
+                                    ((type) == HBN_ROOT_CLK_DLL))
+
+/** @defgroup  HBN_UART_CLK_TYPE
+ *  @{
+ */
+#define IS_HBN_UART_CLK_TYPE(type) (((type) == HBN_UART_CLK_FCLK) || \
+                                    ((type) == HBN_UART_CLK_96M))
+
+/** @defgroup  HBN_RTC_INT_DELAY_TYPE
+ *  @{
+ */
+#define IS_HBN_RTC_INT_DELAY_TYPE(type) (((type) == HBN_RTC_INT_DELAY_32T) || \
+                                         ((type) == HBN_RTC_INT_DELAY_0T))
+
+/** @defgroup  HBN_INT_TYPE
+ *  @{
+ */
+#define IS_HBN_INT_TYPE(type) (((type) == HBN_INT_GPIO9) ||  \
+                               ((type) == HBN_INT_GPIO10) || \
+                               ((type) == HBN_INT_GPIO11) || \
+                               ((type) == HBN_INT_GPIO12) || \
+                               ((type) == HBN_INT_GPIO13) || \
+                               ((type) == HBN_INT_RTC) ||    \
+                               ((type) == HBN_INT_PIR) ||    \
+                               ((type) == HBN_INT_BOR) ||    \
+                               ((type) == HBN_INT_ACOMP0) || \
+                               ((type) == HBN_INT_ACOMP1))
+
+/** @defgroup  HBN_ACOMP_INT_EDGE_TYPE
+ *  @{
+ */
+#define IS_HBN_ACOMP_INT_EDGE_TYPE(type) (((type) == HBN_ACOMP_INT_EDGE_POSEDGE) || \
+                                          ((type) == HBN_ACOMP_INT_EDGE_NEGEDGE))
+
+/** @defgroup  HBN_RST_EVENT_TYPE
+ *  @{
+ */
+#define IS_HBN_RST_EVENT_TYPE(type) (((type) == HBN_RST_EVENT_POR_OUT) ||   \
+                                     ((type) == HBN_RST_EVENT_EXT_RST_N) || \
+                                     ((type) == HBN_RST_EVENT_SW_RST) ||    \
+                                     ((type) == HBN_RST_EVENT_PWR_RST_N) || \
+                                     ((type) == HBN_RST_EVENT_BOR_OUT))
+
+/** @defgroup  HBN_GPIO_INT_TRIGGER_TYPE
+ *  @{
+ */
+#define IS_HBN_GPIO_INT_TRIGGER_TYPE(type) (((type) == HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) ||  \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) ||   \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) ||     \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) ||    \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) || \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) ||  \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) ||    \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL))
+
+/** @defgroup  HBN_OUT0_INT_TYPE
+ *  @{
+ */
+#define IS_HBN_OUT0_INT_TYPE(type) (((type) == HBN_OUT0_INT_GPIO9) ||  \
+                                    ((type) == HBN_OUT0_INT_GPIO10) || \
+                                    ((type) == HBN_OUT0_INT_GPIO11) || \
+                                    ((type) == HBN_OUT0_INT_GPIO12) || \
+                                    ((type) == HBN_OUT0_INT_GPIO13) || \
+                                    ((type) == HBN_OUT0_INT_RTC) ||    \
+                                    ((type) == HBN_OUT0_MAX))
+
+/** @defgroup  HBN_OUT1_INT_TYPE
+ *  @{
+ */
+#define IS_HBN_OUT1_INT_TYPE(type) (((type) == HBN_OUT1_INT_PIR) ||    \
+                                    ((type) == HBN_OUT1_INT_BOR) ||    \
+                                    ((type) == HBN_OUT1_INT_ACOMP0) || \
+                                    ((type) == HBN_OUT1_INT_ACOMP1) || \
+                                    ((type) == HBN_OUT1_MAX))
+
+/** @defgroup  HBN_LDO_LEVEL_TYPE
+ *  @{
+ */
+#define IS_HBN_LDO_LEVEL_TYPE(type) (((type) == HBN_LDO_LEVEL_0P60V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P65V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P70V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P75V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P80V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P85V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P90V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P95V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P00V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P05V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P10V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P15V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P20V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P25V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P30V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P35V))
+
+/** @defgroup  HBN_LDO11RT_DRIVE_STRENGTH_TYPE
+ *  @{
+ */
+#define IS_HBN_LDO11RT_DRIVE_STRENGTH_TYPE(type) (((type) == HBN_LDO11RT_DRIVE_STRENGTH_5_50UA) ||   \
+                                                  ((type) == HBN_LDO11RT_DRIVE_STRENGTH_10_100UA) || \
+                                                  ((type) == HBN_LDO11RT_DRIVE_STRENGTH_15_150UA) || \
+                                                  ((type) == HBN_LDO11RT_DRIVE_STRENGTH_25_250UA))
+
+/** @defgroup  HBN_LEVEL_TYPE
+ *  @{
+ */
+#define IS_HBN_LEVEL_TYPE(type) (((type) == HBN_LEVEL_0) || \
+                                 ((type) == HBN_LEVEL_1) || \
+                                 ((type) == HBN_LEVEL_2) || \
+                                 ((type) == HBN_LEVEL_3))
+
+/*@} end of group HBN_Public_Constants */
+
+/** @defgroup  HBN_Public_Macros
+ *  @{
+ */
+#define HBN_RAM_SIZE           (4 * 1024)
+#define HBN_RTC_COMP_BIT0_39   0x01
+#define HBN_RTC_COMP_BIT0_23   0x02
+#define HBN_RTC_COMP_BIT13_39  0x04
+#define HBN_STATUS_ENTER_FLAG  0x4e424845
+#define HBN_STATUS_WAKEUP_FLAG 0x4e424857
+#define HBN_WAKEUP_GPIO_NONE   0x00
+#define HBN_WAKEUP_GPIO_9      0x01
+#define HBN_WAKEUP_GPIO_10     0x02
+#define HBN_WAKEUP_GPIO_11     0x04
+#define HBN_WAKEUP_GPIO_12     0x08
+#define HBN_WAKEUP_GPIO_13     0x10
+#define HBN_WAKEUP_GPIO_ALL    0x1E
+
+/*@} end of group HBN_Public_Macros */
+
+/** @defgroup  HBN_Public_Functions
+ *  @{
+ */
+/*----------*/
+#ifndef BFLB_USE_HAL_DRIVER
+void HBN_OUT0_IRQHandler(void);
+void HBN_OUT1_IRQHandler(void);
+#endif
+/*----------*/
+void HBN_Mode_Enter(HBN_APP_CFG_Type *cfg);
+void HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg);
+void HBN_Enable_Ext(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel);
+BL_Err_Type HBN_Reset(void);
+BL_Err_Type HBN_App_Reset(uint8_t npXtalType, uint8_t bclkDiv, uint8_t apXtalType, uint8_t fclkDiv);
+BL_Err_Type HBN_Disable(void);
+/*----------*/
+BL_Err_Type HBN_PIR_Enable(void);
+BL_Err_Type HBN_PIR_Disable(void);
+BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type *pirIntCfg);
+BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf);
+BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf);
+BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold);
+uint16_t HBN_Get_PIR_Threshold(void);
+BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval);
+uint16_t HBN_Get_PIR_Interval(void);
+/*----------*/
+BL_Sts_Type HBN_Get_BOR_OUT_State(void);
+BL_Err_Type HBN_Set_BOR_Config(uint8_t enable, HBN_BOR_THRES_Type threshold, HBN_BOR_MODE_Type mode);
+/*----------*/
+BL_Err_Type HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel);
+BL_Err_Type HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel);
+BL_Err_Type HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel);
+BL_Err_Type HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel);
+BL_Err_Type HBN_Set_Ldo11rt_Drive_Strength(HBN_LDO11RT_DRIVE_STRENGTH_Type strength);
+/*----------*/
+BL_Err_Type HBN_32K_Sel(HBN_32K_CLK_Type clkType);
+BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel);
+BL_Err_Type HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_Type xClk);
+BL_Err_Type HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk);
+/*----------*/
+BL_Err_Type HBN_Set_HRAM_slp(void);
+BL_Err_Type HBN_Set_HRAM_Ret(void);
+/*----------*/
+uint32_t HBN_Get_Status_Flag(void);
+BL_Err_Type HBN_Set_Status_Flag(uint32_t flag);
+uint32_t HBN_Get_Wakeup_Addr(void);
+BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr);
+/*----------*/
+BL_Err_Type HBN_Clear_RTC_Counter(void);
+BL_Err_Type HBN_Enable_RTC_Counter(void);
+BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode);
+BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh);
+BL_Err_Type HBN_Clear_RTC_INT(void);
+/*----------*/
+BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType);
+BL_Err_Type HBN_GPIO_INT_Disable(void);
+BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType);
+uint8_t HBN_Get_Pin_Wakeup_Mode(void);
+BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType);
+BL_Err_Type HBN_Hw_Pu_Pd_Cfg(uint8_t enable);
+BL_Err_Type HBN_Aon_Pad_IeSmt_Cfg(uint8_t padCfg);
+BL_Err_Type HBN_Pin_WakeUp_Mask(uint8_t maskVal);
+/*----------*/
+BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge);
+BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge);
+BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge);
+BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge);
+/*----------*/
+BL_Err_Type HBN_Enable_BOR_IRQ(void);
+BL_Err_Type HBN_Disable_BOR_IRQ(void);
+/*----------*/
+BL_Sts_Type HBN_Get_Reset_Event(HBN_RST_EVENT_Type event);
+BL_Err_Type HBN_Clear_Reset_Event(void);
+/*----------*/
+BL_Err_Type HBN_Out0_IRQHandler_Install(void);
+BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType, intCallback_Type *cbFun);
+BL_Err_Type HBN_Out1_IRQHandler_Install(void);
+BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType, intCallback_Type *cbFun);
+/*----------*/
+BL_Err_Type HBN_GPIO_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type dlyEn,
+                                  uint8_t dlySec, HBN_INT_Type gpioIrq, BL_Mask_Type gpioMask);
+/*----------*/
+BL_Err_Type HBN_Power_On_Xtal_32K(void);
+BL_Err_Type HBN_Power_Off_Xtal_32K(void);
+BL_Err_Type HBN_Power_On_RC32K(void);
+BL_Err_Type HBN_Power_Off_RC32K(void);
+BL_Err_Type HBN_Trim_RC32K(void);
+BL_Err_Type HBN_Set_Pad_23_28_Pullnone(void);
+BL_Err_Type HBN_Set_Pad_23_28_Pullup(void);
+BL_Err_Type HBN_Set_Pad_23_28_Pulldown(void);
+BL_Err_Type HBN_Set_Pad_23_28_ActiveIE(void);
+BL_Err_Type HBN_Set_BOR_Cfg(HBN_BOR_CFG_Type *cfg);
+/*----------*/
+void HBN_Enable(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel);
+/*----------*/;
+
+/*@} end of group HBN_Public_Functions */
+
+/*@} end of group HBN */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_HBN_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_i2c.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_i2c.h
new file mode 100644
index 00000000..4fbbc179
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_i2c.h
@@ -0,0 +1,199 @@
+/**
+  ******************************************************************************
+  * @file    bl702_i2c.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_I2C_H__
+#define __BL702_I2C_H__
+
+#include "i2c_reg.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  I2C
+ *  @{
+ */
+
+/** @defgroup  I2C_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief I2C No. type definition
+ */
+typedef enum {
+    I2C0_ID = 0, /*!< I2C0 define */
+    I2C_ID_MAX,  /*!< I2C max define */
+} I2C_ID_Type;
+
+/**
+ *  @brief I2C read/write type definition
+ */
+typedef enum {
+    I2C_WRITE = 0, /*!< I2C write direction */
+    I2C_READ,      /*!< I2C read direction */
+} I2C_Direction_Type;
+
+/**
+ *  @brief I2C interrupt type definition
+ */
+typedef enum {
+    I2C_TRANS_END_INT,     /*!< I2C transfer end interrupt */
+    I2C_TX_FIFO_READY_INT, /*!< I2C TX fifo ready interrupt */
+    I2C_RX_FIFO_READY_INT, /*!< I2C RX fifo ready interrupt */
+    I2C_NACK_RECV_INT,     /*!< I2C nack received interrupt */
+    I2C_ARB_LOST_INT,      /*!< I2C arbitration lost interrupt */
+    I2C_FIFO_ERR_INT,      /*!< I2C TX/RX FIFO error interrupt */
+    I2C_INT_ALL,           /*!< I2C interrupt all type */
+} I2C_INT_Type;
+
+/**
+ *  @brief I2S start condition phase structure type definition
+ */
+typedef struct
+{
+    uint8_t len0; /*!< Length of START condition phase 0 */
+    uint8_t len1; /*!< Length of START condition phase 1 */
+    uint8_t len2; /*!< Length of START condition phase 2 */
+    uint8_t len3; /*!< Length of START condition phase 3 */
+} I2C_Start_Condition_Phase_Type;
+
+/**
+ *  @brief I2S stop condition phase structure type definition
+ */
+typedef struct
+{
+    uint8_t len0; /*!< Length of STOP condition phase 0 */
+    uint8_t len1; /*!< Length of STOP condition phase 1 */
+    uint8_t len2; /*!< Length of STOP condition phase 2 */
+    uint8_t len3; /*!< Length of STOP condition phase 3 */
+} I2C_Stop_Condition_Phase_Type;
+
+/**
+ *  @brief I2S data phase structure type definition
+ */
+typedef struct
+{
+    uint8_t len0; /*!< Length of DATA phase 0 */
+    uint8_t len1; /*!< Length of DATA phase 1 */
+    uint8_t len2; /*!< Length of DATA phase 2 */
+    uint8_t len3; /*!< Length of DATA phase 3 */
+} I2C_Data_Phase_Type;
+
+/**
+ *  @brief I2S transfer structure type definition
+ */
+typedef struct
+{
+    uint8_t slaveAddr;         /*!< I2C slave address */
+    BL_Fun_Type stopEveryByte; /*!< I2C all data byte with stop bit */
+    uint8_t subAddrSize;       /*!< Specifies the size of I2C sub address section */
+    uint32_t subAddr;          /*!< I2C sub address */
+    uint16_t dataSize;         /*!< Specifies the size of I2C data section */
+    uint8_t *data;             /*!< Specifies the pointer of I2C R/W data */
+} I2C_Transfer_Cfg;
+
+/*@} end of group I2C_Public_Types */
+
+/** @defgroup  I2C_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  I2C_ID_TYPE
+ *  @{
+ */
+#define IS_I2C_ID_TYPE(type) (((type) == I2C0_ID) || \
+                              ((type) == I2C_ID_MAX))
+
+/** @defgroup  I2C_DIRECTION_TYPE
+ *  @{
+ */
+#define IS_I2C_DIRECTION_TYPE(type) (((type) == I2C_WRITE) || \
+                                     ((type) == I2C_READ))
+
+/** @defgroup  I2C_INT_TYPE
+ *  @{
+ */
+#define IS_I2C_INT_TYPE(type) (((type) == I2C_TRANS_END_INT) ||     \
+                               ((type) == I2C_TX_FIFO_READY_INT) || \
+                               ((type) == I2C_RX_FIFO_READY_INT) || \
+                               ((type) == I2C_NACK_RECV_INT) ||     \
+                               ((type) == I2C_ARB_LOST_INT) ||      \
+                               ((type) == I2C_FIFO_ERR_INT) ||      \
+                               ((type) == I2C_INT_ALL))
+
+/*@} end of group I2C_Public_Constants */
+
+/** @defgroup  I2C_Public_Macros
+ *  @{
+ */
+
+/*@} end of group I2C_Public_Macros */
+
+/** @defgroup  I2C_Public_Functions
+ *  @{
+ */
+
+/**
+ *  @brief I2C Functions
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+void I2C_IRQHandler(void);
+#endif
+void I2C_SendWord(I2C_ID_Type i2cNo, uint32_t data);
+uint32_t I2C_RecieveWord(I2C_ID_Type i2cNo);
+void I2C_Enable(I2C_ID_Type i2cNo);
+void I2C_Disable(I2C_ID_Type i2cNo);
+BL_Err_Type I2C_SetDeglitchCount(I2C_ID_Type i2cNo, uint8_t cnt);
+BL_Err_Type I2C_Reset(I2C_ID_Type i2cNo);
+void I2C_SetPrd(I2C_ID_Type i2cNo, uint8_t phase);
+void I2C_ClockSet(I2C_ID_Type i2cNo, uint32_t clk);
+void I2C_SetSclSync(I2C_ID_Type i2cNo, uint8_t enable);
+void I2C_Init(I2C_ID_Type i2cNo, I2C_Direction_Type direct, I2C_Transfer_Cfg *cfg);
+BL_Sts_Type I2C_IsBusy(I2C_ID_Type i2cNo);
+BL_Sts_Type I2C_TransferEndStatus(I2C_ID_Type i2cNo);
+BL_Err_Type I2C_MasterSendBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg);
+BL_Err_Type I2C_MasterReceiveBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg);
+void I2C_IntMask(I2C_ID_Type i2cNo, I2C_INT_Type intType, BL_Mask_Type intMask);
+void I2C_Int_Callback_Install(I2C_ID_Type i2cNo, I2C_INT_Type intType, intCallback_Type *cbFun);
+
+/*@} end of group I2C_Public_Functions */
+
+/*@} end of group I2C */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_I2C_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_i2c_gpio_sim.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_i2c_gpio_sim.h
new file mode 100644
index 00000000..18a5ffb4
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_i2c_gpio_sim.h
@@ -0,0 +1,79 @@
+/**
+  ******************************************************************************
+  * @file    bl702_i2c_gpio_sim.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_I2C_GPIO_SIM_H__
+#define __BL702_I2C_GPIO_SIM_H__
+
+#include "bl702_glb.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  I2C_GPIO_SIM
+ *  @{
+ */
+
+/** @defgroup  I2C_GPIO_SIM_Public_Types
+ *  @{
+ */
+
+/*@} end of group I2C_GPIO_SIM_Public_Types */
+
+/** @defgroup  I2C_GPIO_SIM_Public_Functions
+ *  @{
+ */
+
+/**
+ *  @brief I2C Functions
+ */
+void I2C_GPIO_Sim_Init(GLB_GPIO_Type sclGPIOPin, GLB_GPIO_Type sdaGPIOPin);
+int I2C_Start(void);
+void I2C_Stop(void);
+uint8_t I2C_GetAck(void);
+void I2C_SendByte(uint8_t Data);
+uint8_t I2C_ReadByte(uint8_t ack);
+int SCCB_Init(GLB_GPIO_Type sclGPIOPin, GLB_GPIO_Type sdaGPIOPin);
+int SCCB_Write(uint8_t slave_addr, uint8_t *data, uint32_t wrsize);
+int SCCB_Read(uint8_t slave_addr, uint8_t *data, uint32_t rdsize);
+
+/*@} end of group I2C_GPIO_SIM_Public_Functions */
+
+/*@} end of group I2C_GPIO_SIM */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_I2C_GPIO_SIM_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_i2s.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_i2s.h
new file mode 100644
index 00000000..b19e363f
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_i2s.h
@@ -0,0 +1,295 @@
+/**
+  ******************************************************************************
+  * @file    bl702_i2s.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_I2S_H__
+#define __BL702_I2S_H__
+
+#include "i2s_reg.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  I2S
+ *  @{
+ */
+
+/** @defgroup  I2S_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief I2S mode type definition
+ */
+typedef enum {
+    I2S_MODE_I2S_LEFT,  /*!< Left-Justified Mode */
+    I2S_MODE_I2S_RIGHT, /*!< Right-Justified Mode */
+    I2S_MODE_I2S_DSP,   /*!< DSP Mode */
+} I2S_Mode_Type;
+
+/**
+ *  @brief I2S role type definition
+ */
+typedef enum {
+    I2S_ROLE_MASTER = 0, /*!< I2S as master */
+    I2S_ROLE_SLAVE = 1,  /*!< I2S as slave */
+} I2S_Role_Type;
+
+/**
+ *  @brief I2S data size type definition
+ */
+typedef enum {
+    I2S_SIZE_DATA_8 = 0, /*!< I2S data size 8 bits */
+    I2S_SIZE_DATA_16,    /*!< I2S data size 16 bits */
+    I2S_SIZE_DATA_24,    /*!< I2S data size 24 bits */
+    I2S_SIZE_DATA_32,    /*!< I2S data size 32 bits */
+} I2S_Data_Size_Type;
+
+/**
+ *  @brief I2S frame size type definition
+ */
+typedef enum {
+    I2S_SIZE_FRAME_8 = 0, /*!< I2S frame size 8 bits */
+    I2S_SIZE_FRAME_16,    /*!< I2S frame size 16 bits */
+    I2S_SIZE_FRAME_24,    /*!< I2S frame size 24 bits */
+    I2S_SIZE_FRAME_32,    /*!< I2S frame size 32 bits */
+} I2S_Frame_Size_Type;
+
+/**
+ *  @brief I2S endian data type definition
+ */
+typedef enum {
+    I2S_DATA_ENDIAN_MSB = 0, /*!< I2S use MSB first */
+    I2S_DATA_ENDIAN_LSB,     /*!< I2S use LSB first */
+} I2S_Endian_Type;
+
+/**
+ *  @brief I2S frame select mode type definition
+ */
+typedef enum {
+    I2S_FS_MODE_EVEN = 0, /*!< I2S frame is even */
+    I2S_FS_MODE_1T,       /*!< I2S frame is only 1T high */
+} I2S_Fs_Mode_Type;
+
+/**
+ *  @brief I2S rx mono mode channel select type definition
+ */
+typedef enum {
+    I2S_RX_MONO_MODE_LEFT_CHANNEL,  /*!< I2S rx mono mode left channel */
+    I2S_RX_MONO_MODE_RIGHT_CHANNEL, /*!< I2S rx mono mode right channel */
+} I2S_Mono_Mode_Channel;
+
+/**
+ *  @brief I2S frame channel mode type definition
+ */
+typedef enum {
+    I2S_FS_CHANNELS_2 = 0, /*!< I2S frame is for 2 channels */
+    I2S_FS_CHANNELS_3,     /*!< I2S frame is for 3 channels */
+    I2S_FS_CHANNELS_4,     /*!< I2S frame is for 4 channels */
+} I2S_Fs_Channel_Type;
+
+/**
+ *  @brief I2S mono control definition
+ */
+typedef enum {
+    I2S_MONO_CONTROL_STEREO = 0, /*!< I2S output stereo */
+    I2S_MONO_CONTROL_MONO,       /*!< I2S output mono */
+} I2S_MonoControl_Type;
+
+/**
+ *  @brief I2S fifo 24-bit data align type definition
+ */
+typedef enum {
+    I2S_FIFO_24_RIGHT_JUSTIFIED = 0, /*!< I2S fifo:[31:24]0x00,[23:0]24bit_data */
+    I2S_FIFO_24_LEFT_JUSTIFIED,      /*!< I2S fifo:[31:8]24bit_data,[7:0]0x00 */
+} I2S_FIFO_24_Justified_Type;
+
+/**
+ *  @brief I2S configuration structure type definition
+ */
+typedef struct
+{
+    I2S_Endian_Type endianType;            /*!< I2S endian configuration */
+    I2S_Mode_Type modeType;                /*!< I2S mode configuration */
+    uint32_t audioFreqHz;                  /*!< I2S audio pll output frequency in Hz */
+    uint32_t sampleFreqHz;                 /*!< I2S sample data frequency in Hz */
+    BL_Fun_Type bclkInvert;                /*!< I2S bclk invert configuration */
+    I2S_Frame_Size_Type frameSize;         /*!< I2S frame size configuration */
+    BL_Fun_Type fsInvert;                  /*!< I2S frame select invert configuration */
+    I2S_Fs_Mode_Type fsMode;               /*!< I2S frame mode configuration */
+    I2S_Fs_Channel_Type fsChannel;         /*!< I2S frame channels configuration */
+    uint32_t dataOffset;                   /*!< I2S data output offset configuration */
+    I2S_Data_Size_Type dataSize;           /*!< I2S data size configuration */
+    BL_Fun_Type monoMode;                  /*!< I2S enable mono mode,when this mode enable,lRMerge must be disabled */
+    I2S_Mono_Mode_Channel monoModeChannel; /*!< I2S mono mode channel configuration */
+} I2S_CFG_Type;
+
+/**
+ *  @brief I2S FIFO configuration structure type definition
+ */
+typedef struct
+{
+    BL_Fun_Type lRMerge;           /*!< I2S FIFO contains both left and right channel data in one entry */
+    BL_Fun_Type frameDataExchange; /*!< I2S exchange left and right channel data in one entry */
+    BL_Fun_Type txfifoDmaEnable;   /*!< Enable or disable I2S tx fifo dma function. */
+    BL_Fun_Type rxfifoDmaEnable;   /*!< Enable or disable I2S rx fifo dma function. */
+    uint8_t rxFifoLevel;           /*!< I2S receive fifo interrupt trigger level. only valid when fifo mode enabled. */
+    uint8_t txFifoLevel;           /*!< I2S transmit fifo interrupt trigger level. only valid when fifo mode enabled. */
+} I2S_FifoCfg_Type;
+
+/**
+ *  @brief I2S IO configuration structure type definition
+ */
+typedef struct
+{
+    BL_Fun_Type deglitchEn;  /*!< Enable or disable deglitch(for all the input pins) */
+    uint8_t deglitchCnt;     /*!< Deglitch cycle count(unit:cycle of I2S kernel clock) */
+    BL_Fun_Type inverseBCLK; /*!< Enable or disable inverse BCLK signal */
+    BL_Fun_Type inverseFS;   /*!< Enable or disable inverse FS signal */
+    BL_Fun_Type inverseRX;   /*!< Enable or disable inverse RX signal */
+    BL_Fun_Type inverseTX;   /*!< Enable or disable inverse TX signal */
+} I2S_IOCfg_Type;
+
+/*@} end of group I2S_Public_Types */
+
+/** @defgroup  I2S_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  I2S_MODE_TYPE
+ *  @{
+ */
+#define IS_I2S_MODE_TYPE(type) (((type) == I2S_MODE_I2S_LEFT) ||  \
+                                ((type) == I2S_MODE_I2S_RIGHT) || \
+                                ((type) == I2S_MODE_I2S_DSP))
+
+/** @defgroup  I2S_ROLE_TYPE
+ *  @{
+ */
+#define IS_I2S_ROLE_TYPE(type) (((type) == I2S_ROLE_MASTER) || \
+                                ((type) == I2S_ROLE_SLAVE))
+
+/** @defgroup  I2S_DATA_SIZE_TYPE
+ *  @{
+ */
+#define IS_I2S_DATA_SIZE_TYPE(type) (((type) == I2S_SIZE_DATA_8) ||  \
+                                     ((type) == I2S_SIZE_DATA_16) || \
+                                     ((type) == I2S_SIZE_DATA_24) || \
+                                     ((type) == I2S_SIZE_DATA_32))
+
+/** @defgroup  I2S_FRAME_SIZE_TYPE
+ *  @{
+ */
+#define IS_I2S_FRAME_SIZE_TYPE(type) (((type) == I2S_SIZE_FRAME_8) ||  \
+                                      ((type) == I2S_SIZE_FRAME_16) || \
+                                      ((type) == I2S_SIZE_FRAME_24) || \
+                                      ((type) == I2S_SIZE_FRAME_32))
+
+/** @defgroup  I2S_ENDIAN_TYPE
+ *  @{
+ */
+#define IS_I2S_ENDIAN_TYPE(type) (((type) == I2S_DATA_ENDIAN_MSB) || \
+                                  ((type) == I2S_DATA_ENDIAN_LSB))
+
+/** @defgroup  I2S_FS_MODE_TYPE
+ *  @{
+ */
+#define IS_I2S_FS_MODE_TYPE(type) (((type) == I2S_FS_MODE_EVEN) || \
+                                   ((type) == I2S_FS_MODE_1T))
+
+/** @defgroup  I2S_MONO_MODE_CHANNEL
+ *  @{
+ */
+#define IS_I2S_MONO_MODE_CHANNEL(type) (((type) == I2S_RX_MONO_MODE_LEFT_CHANNEL) || \
+                                        ((type) == I2S_RX_MONO_MODE_RIGHT_CHANNEL))
+
+/** @defgroup  I2S_FS_CHANNEL_TYPE
+ *  @{
+ */
+#define IS_I2S_FS_CHANNEL_TYPE(type) (((type) == I2S_FS_CHANNELS_2) || \
+                                      ((type) == I2S_FS_CHANNELS_3) || \
+                                      ((type) == I2S_FS_CHANNELS_4))
+
+/** @defgroup  I2S_MONOCONTROL_TYPE
+ *  @{
+ */
+#define IS_I2S_MONOCONTROL_TYPE(type) (((type) == I2S_MONO_CONTROL_STEREO) || \
+                                       ((type) == I2S_MONO_CONTROL_MONO))
+
+/** @defgroup  I2S_FIFO_24_JUSTIFIED_TYPE
+ *  @{
+ */
+#define IS_I2S_FIFO_24_JUSTIFIED_TYPE(type) (((type) == I2S_FIFO_24_RIGHT_JUSTIFIED) || \
+                                             ((type) == I2S_FIFO_24_LEFT_JUSTIFIED))
+
+/*@} end of group I2S_Public_Constants */
+
+/** @defgroup  I2S_Public_Macros
+ *  @{
+ */
+#define I2S_TX_FIFO_SIZE 16
+#define I2S_RX_FIFO_SIZE 16
+
+/*@} end of group I2S_Public_Macros */
+
+/** @defgroup  I2S_Public_Functions
+ *  @{
+ */
+
+/**
+ *  @brief I2S Functions
+ */
+void I2S_SetBclkPeriod(I2S_CFG_Type *i2sCfg);
+void I2S_Init(I2S_CFG_Type *i2sCfg);
+void I2S_FifoConfig(I2S_FifoCfg_Type *fifoCfg);
+void I2S_IOConfig(I2S_IOCfg_Type *ioCfg);
+void I2S_Enable(I2S_Role_Type roleType);
+void I2S_Disable(void);
+uint32_t I2S_Read(void);
+void I2S_Write(uint32_t data);
+void I2S_Mute(BL_Fun_Type enabled);
+void I2S_SetFifoJustified(I2S_FIFO_24_Justified_Type justType);
+uint32_t I2S_GetTxFIFO_AvlCnt(void);
+uint32_t I2S_GetRxFIFO_AvlCnt(void);
+void I2S_Flush(void);
+
+/*@} end of group I2S_Public_Functions */
+
+/*@} end of group I2S */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_I2S_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_ir.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_ir.h
new file mode 100644
index 00000000..7345dbb2
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_ir.h
@@ -0,0 +1,257 @@
+/**
+  ******************************************************************************
+  * @file    bl702_ir.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_IR_H__
+#define __BL702_IR_H__
+
+#include "ir_reg.h"
+#include "bl702_common.h"
+#include "bl702_hbn.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  IR
+ *  @{
+ */
+
+/** @defgroup  IR_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief IR direction type definition
+ */
+typedef enum {
+    IR_TX,   /*!< IR TX direction */
+    IR_RX,   /*!< IR RX direction */
+    IR_TXRX, /*!< IR TX and RX direction */
+} IR_Direction_Type;
+
+/**
+ *  @brief IR word type definition
+ */
+typedef enum {
+    IR_WORD_0, /*!< IR data word 0 */
+    IR_WORD_1, /*!< IR data word 1 */
+} IR_Word_Type;
+
+/**
+ *  @brief IR RX mode type definition
+ */
+typedef enum {
+    IR_RX_NEC, /*!< IR RX NEC mode */
+    IR_RX_RC5, /*!< IR RX RC5 mode */
+    IR_RX_SWM, /*!< IR RX software pulse-width detection mode */
+} IR_RxMode_Type;
+
+/**
+ *  @brief IR interrupt type definition
+ */
+typedef enum {
+    IR_INT_TX,  /*!< IR TX transfer end interrupt */
+    IR_INT_RX,  /*!< IR RX transfer end interrupt */
+    IR_INT_ALL, /*!< IR all interrupt */
+} IR_INT_Type;
+
+/**
+ *  @brief IR fifo underflow or overflow type definition
+ */
+typedef enum {
+    IR_RX_FIFO_UNDERFLOW, /*!< Underflow flag of rx fifo */
+    IR_RX_FIFO_OVERFLOW,  /*!< Overflow flag of rx fifo */
+} IR_FifoStatus_Type;
+
+/**
+ *  @brief IR TX configuration structure type definition
+ */
+typedef struct
+{
+    uint8_t dataBits;               /*!< Bit count of data phase */
+    BL_Fun_Type tailPulseInverse;   /*!< Enable or disable signal of tail pulse inverse (don't care if SWM is enabled) */
+    BL_Fun_Type tailPulse;          /*!< Enable or disable signal of tail pulse (don't care if SWM is enabled) */
+    BL_Fun_Type headPulseInverse;   /*!< Enable or disable signal of head pulse inverse (don't care if SWM is enabled) */
+    BL_Fun_Type headPulse;          /*!< Enable or disable signal of head pulse (don't care if SWM is enabled) */
+    BL_Fun_Type logic1PulseInverse; /*!< Enable or disable signal of logic 1 pulse inverse (don't care if SWM is enabled) */
+    BL_Fun_Type logic0PulseInverse; /*!< Enable or disable signal of logic 0 pulse inverse (don't care if SWM is enabled) */
+    BL_Fun_Type dataPulse;          /*!< Enable or disable signal of data pulse (don't care if SWM is enabled) */
+    BL_Fun_Type outputModulation;   /*!< Enable or disable signal of output modulation */
+    BL_Fun_Type outputInverse;      /*!< Enable or disable signal of output inverse,0:output stays at low during idle state,1:stay at high */
+} IR_TxCfg_Type;
+
+/**
+ *  @brief IR TX pulse width configuration structure type definition
+ */
+typedef struct
+{
+    uint8_t logic0PulseWidth_1; /*!< Pulse width of logic 0 pulse phase 1 (don't care if SWM is enabled) */
+    uint8_t logic0PulseWidth_0; /*!< Pulse width of logic 0 pulse phase 0 (don't care if SWM is enabled) */
+    uint8_t logic1PulseWidth_1; /*!< Pulse width of logic 1 pulse phase 1 (don't care if SWM is enabled) */
+    uint8_t logic1PulseWidth_0; /*!< Pulse width of logic 1 pulse phase 0 (don't care if SWM is enabled) */
+    uint8_t headPulseWidth_1;   /*!< Pulse width of head pulse phase 1 (don't care if SWM is enabled) */
+    uint8_t headPulseWidth_0;   /*!< Pulse width of head pulse phase 0 (don't care if SWM is enabled) */
+    uint8_t tailPulseWidth_1;   /*!< Pulse width of tail pulse phase 1 (don't care if SWM is enabled) */
+    uint8_t tailPulseWidth_0;   /*!< Pulse width of tail pulse phase 0 (don't care if SWM is enabled) */
+    uint8_t moduWidth_1;        /*!< Modulation phase 1 width */
+    uint8_t moduWidth_0;        /*!< Modulation phase 0 width */
+    uint16_t pulseWidthUnit;    /*!< Pulse width unit */
+} IR_TxPulseWidthCfg_Type;
+
+/**
+ *  @brief IR TX software mode pulse width(multiples of pulse width unit) configuration structure type definition
+ */
+typedef struct
+{
+    uint32_t swmData0; /*!< SWM pulse width data   0~7,multiples of pulse width unit,each pulse is represented by 4-bit */
+    uint32_t swmData1; /*!< SWM pulse width data  8~15,multiples of pulse width unit,each pulse is represented by 4-bit */
+    uint32_t swmData2; /*!< SWM pulse width data 16~23,multiples of pulse width unit,each pulse is represented by 4-bit */
+    uint32_t swmData3; /*!< SWM pulse width data 24~31,multiples of pulse width unit,each pulse is represented by 4-bit */
+    uint32_t swmData4; /*!< SWM pulse width data 32~39,multiples of pulse width unit,each pulse is represented by 4-bit */
+    uint32_t swmData5; /*!< SWM pulse width data 40~47,multiples of pulse width unit,each pulse is represented by 4-bit */
+    uint32_t swmData6; /*!< SWM pulse width data 48~55,multiples of pulse width unit,each pulse is represented by 4-bit */
+    uint32_t swmData7; /*!< SWM pulse width data 56~63,multiples of pulse width unit,each pulse is represented by 4-bit */
+} IR_TxSWMPulseWidthCfg_Type;
+
+/**
+ *  @brief IR RX configuration structure type definition
+ */
+typedef struct
+{
+    IR_RxMode_Type rxMode;    /*!< Set ir rx mode */
+    BL_Fun_Type inputInverse; /*!< Enable or disable signal of input inverse */
+    uint16_t endThreshold;    /*!< Pulse width threshold to trigger end condition */
+    uint16_t dataThreshold;   /*!< Pulse width threshold for logic 0/1 detection (don't care if SWM is enabled) */
+    BL_Fun_Type rxDeglitch;   /*!< Enable or disable signal of rx input de-glitch function */
+    uint8_t DeglitchCnt;      /*!< De-glitch function cycle count */
+} IR_RxCfg_Type;
+
+/*@} end of group IR_Public_Types */
+
+/** @defgroup  IR_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  IR_DIRECTION_TYPE
+ *  @{
+ */
+#define IS_IR_DIRECTION_TYPE(type) (((type) == IR_TX) || \
+                                    ((type) == IR_RX) || \
+                                    ((type) == IR_TXRX))
+
+/** @defgroup  IR_WORD_TYPE
+ *  @{
+ */
+#define IS_IR_WORD_TYPE(type) (((type) == IR_WORD_0) || \
+                               ((type) == IR_WORD_1))
+
+/** @defgroup  IR_RXMODE_TYPE
+ *  @{
+ */
+#define IS_IR_RXMODE_TYPE(type) (((type) == IR_RX_NEC) || \
+                                 ((type) == IR_RX_RC5) || \
+                                 ((type) == IR_RX_SWM))
+
+/** @defgroup  IR_INT_TYPE
+ *  @{
+ */
+#define IS_IR_INT_TYPE(type) (((type) == IR_INT_TX) || \
+                              ((type) == IR_INT_RX) || \
+                              ((type) == IR_INT_ALL))
+
+/** @defgroup  IR_FIFOSTATUS_TYPE
+ *  @{
+ */
+#define IS_IR_FIFOSTATUS_TYPE(type) (((type) == IR_RX_FIFO_UNDERFLOW) || \
+                                     ((type) == IR_RX_FIFO_OVERFLOW))
+
+/*@} end of group IR_Public_Constants */
+
+/** @defgroup  IR_Public_Macros
+ *  @{
+ */
+#define IR_RX_FIFO_SIZE 64
+
+/*@} end of group IR_Public_Macros */
+
+/** @defgroup  IR_Public_Functions
+ *  @{
+ */
+
+/**
+ *  @brief IR Functions
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+void IRRX_IRQHandler(void);
+void IRTX_IRQHandler(void);
+#endif
+BL_Err_Type IR_TxInit(IR_TxCfg_Type *irTxCfg);
+BL_Err_Type IR_TxPulseWidthConfig(IR_TxPulseWidthCfg_Type *irTxPulseWidthCfg);
+BL_Err_Type IR_TxSWMPulseWidthConfig(IR_TxSWMPulseWidthCfg_Type *irTxSWMPulseWidthCfg);
+BL_Err_Type IR_RxInit(IR_RxCfg_Type *irRxCfg);
+BL_Err_Type IR_DeInit(void);
+BL_Err_Type IR_Enable(IR_Direction_Type direct);
+BL_Err_Type IR_Disable(IR_Direction_Type direct);
+BL_Err_Type IR_TxSWM(BL_Fun_Type txSWM);
+BL_Err_Type IR_RxFIFOClear(void);
+BL_Err_Type IR_SendData(IR_Word_Type irWord, uint32_t data);
+BL_Err_Type IR_SWMSendData(uint16_t *data, uint8_t length);
+BL_Err_Type IR_SendCommand(uint32_t word1, uint32_t word0);
+BL_Err_Type IR_SWMSendCommand(uint16_t *data, uint8_t length);
+BL_Err_Type IR_SendNEC(uint8_t address, uint8_t command);
+BL_Err_Type IR_IntMask(IR_INT_Type intType, BL_Mask_Type intMask);
+BL_Err_Type IR_ClrIntStatus(IR_INT_Type intType);
+BL_Err_Type IR_Int_Callback_Install(IR_INT_Type intType, intCallback_Type *cbFun);
+BL_Sts_Type IR_GetIntStatus(IR_INT_Type intType);
+BL_Sts_Type IR_GetRxFIFOStatus(IR_FifoStatus_Type fifoSts);
+uint32_t IR_ReceiveData(IR_Word_Type irWord);
+uint8_t IR_SWMReceiveData(uint16_t *data, uint8_t length);
+BL_Err_Type IR_ReceiveNEC(uint8_t *address, uint8_t *command);
+uint8_t IR_GetRxDataBitCount(void);
+uint8_t IR_GetRxFIFOCount(void);
+IR_RxMode_Type IR_LearnToInit(uint32_t *data, uint8_t *length);
+BL_Err_Type IR_LearnToSend(IR_RxMode_Type mode, uint32_t *data, uint8_t length);
+uint8_t IR_LearnToReceive(IR_RxMode_Type mode, uint32_t *data);
+BL_Err_Type IR_LEDInit(HBN_XCLK_CLK_Type clk, uint8_t div, uint8_t unit, uint8_t code0H, uint8_t code0L, uint8_t code1H,
+                       uint8_t code1L);
+BL_Err_Type IR_LEDSend(uint32_t data);
+
+/*@} end of group IR_Public_Functions */
+
+/*@} end of group IR */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_IR_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_kys.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_kys.h
new file mode 100644
index 00000000..191ece52
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_kys.h
@@ -0,0 +1,124 @@
+/**
+  ******************************************************************************
+  * @file    bl702_kys.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_KYS_H__
+#define __BL702_KYS_H__
+
+#include "kys_reg.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  KYS
+ *  @{
+ */
+
+/** @defgroup  KYS_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief KYS keycode type definition
+ */
+typedef enum {
+    KYS_KEYCODE_0, /*!< KYS keycode 0 */
+    KYS_KEYCODE_1, /*!< KYS keycode 1 */
+    KYS_KEYCODE_2, /*!< KYS keycode 2 */
+    KYS_KEYCODE_3, /*!< KYS keycode 3 */
+} KYS_Keycode_Type;
+
+/**
+ *  @brief KYS configuration structure type definition
+ */
+typedef struct
+{
+    uint8_t col;            /*!< Col of keyboard,max:20 */
+    uint8_t row;            /*!< Row of keyboard,max:8 */
+    uint8_t idleDuration;   /*!< Idle duration between column scans */
+    BL_Fun_Type ghostEn;    /*!< Enable or disable ghost key event detection */
+    BL_Fun_Type deglitchEn; /*!< Enable or disable deglitch function */
+    uint8_t deglitchCnt;    /*!< Deglitch count */
+} KYS_CFG_Type;
+
+/*@} end of group KYS_Public_Types */
+
+/** @defgroup  KYS_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  KYS_KEYCODE_TYPE
+ *  @{
+ */
+#define IS_KYS_KEYCODE_TYPE(type) (((type) == KYS_KEYCODE_0) || \
+                                   ((type) == KYS_KEYCODE_1) || \
+                                   ((type) == KYS_KEYCODE_2) || \
+                                   ((type) == KYS_KEYCODE_3))
+
+/*@} end of group KYS_Public_Constants */
+
+/** @defgroup  KYS_Public_Macros
+ *  @{
+ */
+
+/*@} end of group KYS_Public_Macros */
+
+/** @defgroup  KYS_Public_Functions
+ *  @{
+ */
+
+/**
+ *  @brief UART Functions
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+void KYS_IRQHandler(void);
+#endif
+BL_Err_Type KYS_Init(KYS_CFG_Type *kysCfg);
+BL_Err_Type KYS_Enable(void);
+BL_Err_Type KYS_Disable(void);
+BL_Err_Type KYS_IntMask(BL_Mask_Type intMask);
+BL_Err_Type KYS_IntClear(void);
+BL_Err_Type KYS_Int_Callback_Install(intCallback_Type *cbFun);
+uint8_t KYS_GetIntStatus(void);
+uint8_t KYS_GetKeycode(KYS_Keycode_Type keycode, uint8_t *col, uint8_t *row);
+
+/*@} end of group KYS_Public_Functions */
+
+/*@} end of group KYS */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_KYS_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_l1c.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_l1c.h
new file mode 100644
index 00000000..6c3a27d6
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_l1c.h
@@ -0,0 +1,203 @@
+/**
+  ******************************************************************************
+  * @file    bl702_l1c.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_L1C_H__
+#define __BL702_L1C_H__
+
+#include "l1c_reg.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  L1C
+ *  @{
+ */
+
+/** @defgroup  L1C_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief L1C configuration structure type definition
+ */
+typedef struct
+{
+    BL_Fun_Type wrapDis;  /*!< wrap disable */
+    BL_Fun_Type bypassEn; /*!< bypass cache enable */
+    uint8_t wayDis;       /*!< Disable part of cache ways & used as ITCM */
+    BL_Fun_Type cntEn;    /*!< l1c count enable */
+} L1C_CACHE_Cfg_Type;
+
+/**
+ *  @brief L1C BMX arb mode type definition
+ */
+typedef enum {
+    L1C_BMX_ARB_FIX,         /*!< 0->fix */
+    L1C_BMX_ARB_ROUND_ROBIN, /*!< 2->round-robin */
+    L1C_BMX_ARB_RANDOM,      /*!< 3->random */
+} L1C_BMX_ARB_Type;
+
+/**
+ *  @brief L1C BMX configuration structure type definition
+ */
+typedef struct
+{
+    uint8_t timeoutEn;       /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */
+    BL_Fun_Type errEn;       /*!< Bus error response enable */
+    L1C_BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */
+} L1C_BMX_Cfg_Type;
+
+/**
+ *  @brief L1C BMX bus err type definition
+ */
+typedef enum {
+    L1C_BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */
+    L1C_BMX_BUS_ERR_ADDR_DECODE,      /*!< Bus addr decode error */
+} L1C_BMX_BUS_ERR_Type;
+
+/**
+ *  @brief L1C BMX bus err interrupt type definition
+ */
+typedef enum {
+    L1C_BMX_ERR_INT_ERR, /*!< L1C BMX bus err interrupt */
+    L1C_BMX_ERR_INT_ALL, /*!< L1C BMX bus err interrupt max num */
+} L1C_BMX_ERR_INT_Type;
+
+/**
+ *  @brief L1C BMX time out interrupt type definition
+ */
+typedef enum {
+    L1C_BMX_TO_INT_TIMEOUT, /*!< L1C_BMX timeout interrupt */
+    L1C_BMX_TO_INT_ALL,     /*!< L1C_BMX timeout interrupt max num */
+} L1C_BMX_TO_INT_Type;
+
+/*@} end of group L1C_Public_Types */
+
+/** @defgroup  L1C_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  L1C_BMX_ARB_TYPE
+ *  @{
+ */
+#define IS_L1C_BMX_ARB_TYPE(type) (((type) == L1C_BMX_ARB_FIX) ||         \
+                                   ((type) == L1C_BMX_ARB_ROUND_ROBIN) || \
+                                   ((type) == L1C_BMX_ARB_RANDOM))
+
+/** @defgroup  L1C_BMX_BUS_ERR_TYPE
+ *  @{
+ */
+#define IS_L1C_BMX_BUS_ERR_TYPE(type) (((type) == L1C_BMX_BUS_ERR_TRUSTZONE_DECODE) || \
+                                       ((type) == L1C_BMX_BUS_ERR_ADDR_DECODE))
+
+/** @defgroup  L1C_BMX_ERR_INT_TYPE
+ *  @{
+ */
+#define IS_L1C_BMX_ERR_INT_TYPE(type) (((type) == L1C_BMX_ERR_INT_ERR) || \
+                                       ((type) == L1C_BMX_ERR_INT_ALL))
+
+/** @defgroup  L1C_BMX_TO_INT_TYPE
+ *  @{
+ */
+#define IS_L1C_BMX_TO_INT_TYPE(type) (((type) == L1C_BMX_TO_INT_TIMEOUT) || \
+                                      ((type) == L1C_BMX_TO_INT_ALL))
+
+/*@} end of group L1C_Public_Constants */
+
+/** @defgroup  L1C_Public_Macros
+ *  @{
+ */
+#define L1C_WAY_DISABLE_NONE  0x00
+#define L1C_WAY_DISABLE_ONE   0x01
+#define L1C_WAY_DISABLE_TWO   0x03
+#define L1C_WAY_DISABLE_THREE 0x07
+#define L1C_WAY_DISABLE_ALL   0x0F
+#define L1C_WAY_DISABLE_USER  0xFF
+#if 1
+/*NP config address */
+#define L1C_CONF_REG        (L1C_BASE + 0x00)
+#define L1C_HIT_CNT_LSB_REG (L1C_BASE + 0x04)
+#define L1C_HIT_CNT_MSB_REG (L1C_BASE + 0x08)
+#define L1C_MISS_CNT_REG    (L1C_BASE + 0x0C)
+/* Get miss and hit count */
+#define L1C_Get_Miss_Cnt()    BL702_REG_RD(L1C_MISS_CNT_REG)
+#define L1C_Get_Hit_Cnt_LSB() BL702_REG_RD(L1C_HIT_CNT_LSB_REG)
+#define L1C_Get_Hit_Cnt_MSB() BL702_REG_RD(L1C_HIT_CNT_MSB_REG)
+#endif
+
+/*@} end of group L1C_Public_Macros */
+
+/** @defgroup  L1C_Public_Functions
+ *  @{
+ */
+/*----------*/
+#ifndef BFLB_USE_HAL_DRIVER
+void L1C_BMX_ERR_IRQHandler(void);
+void L1C_BMX_TO_IRQHandler(void);
+#endif
+/*----------*/
+BL_Err_Type L1C_Cache_Enable_Set(uint8_t wayDisable);
+void L1C_Cache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn);
+BL_Err_Type L1C_Cache_Flush(uint8_t wayDisable);
+BL_Err_Type L1C_Cache_Flush_Ext(void);
+void L1C_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh);
+uint32_t L1C_Cache_Miss_Count_Get(void);
+void L1C_Cache_Read_Disable(void);
+/*----------*/
+BL_Err_Type L1C_Set_Wrap(BL_Fun_Type wrap);
+BL_Err_Type L1C_Set_Way_Disable(uint8_t disableVal);
+BL_Err_Type L1C_IROM_2T_Access_Set(uint8_t enable);
+/*----------*/
+BL_Err_Type L1C_BMX_Init(L1C_BMX_Cfg_Type *l1cBmxCfg);
+BL_Err_Type L1C_BMX_Addr_Monitor_Enable(void);
+BL_Err_Type L1C_BMX_Addr_Monitor_Disable(void);
+BL_Err_Type L1C_BMX_BusErrResponse_Enable(void);
+BL_Err_Type L1C_BMX_BusErrResponse_Disable(void);
+BL_Sts_Type L1C_BMX_Get_Status(L1C_BMX_BUS_ERR_Type errType);
+uint32_t L1C_BMX_Get_Err_Addr(void);
+BL_Err_Type L1C_BMX_ERR_INT_Callback_Install(L1C_BMX_ERR_INT_Type intType, intCallback_Type *cbFun);
+BL_Err_Type L1C_BMX_TIMEOUT_INT_Callback_Install(L1C_BMX_TO_INT_Type intType,
+                                                 intCallback_Type *cbFun);
+/*----------*/;
+
+/*@} end of group L1C_Public_Functions */
+
+/*@} end of group L1C */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_L1C_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_mjpeg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_mjpeg.h
new file mode 100644
index 00000000..9b99591a
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_mjpeg.h
@@ -0,0 +1,229 @@
+/**
+  ******************************************************************************
+  * @file    bl702_mjpeg.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_MJPEG_H__
+#define __BL702_MJPEG_H__
+
+#include "mjpeg_reg.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  MJPEG
+ *  @{
+ */
+
+/** @defgroup  MJPEG_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief MJPEG YUV format definition
+ */
+typedef enum {
+    MJPEG_YUV420,            /*!< MJPEG YUV420 planar mode */
+    MJPEG_YUV400,            /*!< MJPEG YUV400 grey scale mode */
+    MJPEG_YUV422_PLANAR,     /*!< MJPEG YUV422 planar mode */
+    MJPEG_YUV422_INTERLEAVE, /*!< MJPEG YUV422 interleave mode */
+} MJPEG_YUV_Mode_Type;
+
+/**
+ *  @brief MJPEG burst type definition
+ */
+typedef enum {
+    MJPEG_BURST_SINGLE, /*!< MJPEG burst single */
+    MJPEG_BURST_INCR4,  /*!< MJPEG burst incr4 */
+    MJPEG_BURST_INCR8,  /*!< MJPEG burst incr8 */
+    MJPEG_BURST_INCR16, /*!< MJPEG burst incr16 */
+} MJPEG_Burst_Type;
+
+/**
+ *  @brief MJPEG swap mode block definition
+ */
+typedef enum {
+    MJPEG_BLOCK_0, /*!< Memory block 0 */
+    MJPEG_BLOCK_1, /*!< Memory block 1 */
+} MJPEG_Swap_Block_Type;
+
+/**
+ *  @brief MJPEG interrupt type definition
+ */
+typedef enum {
+    MJPEG_INT_NORMAL,          /*!< MJPEG normal write interrupt */
+    MJPEG_INT_CAM_OVERWRITE,   /*!< MJPEG camera overwrite interrupt */
+    MJPEG_INT_MEM_OVERWRITE,   /*!< MJPEG memory overwrite interrupt */
+    MJPEG_INT_FRAME_OVERWRITE, /*!< MJPEG frame overwrite interrupt */
+    MJPEG_INT_BACK_IDLE,       /*!< MJPEG back idle interrupt */
+    MJPEG_INT_SWAP,            /*!< MJPEG swap memory block interrupt */
+    MJPEG_INT_ALL,             /*!< MJPEG all interrupt type */
+} MJPEG_INT_Type;
+
+/**
+ *  @brief MJPEG configuration strcut definition
+ */
+typedef struct
+{
+    MJPEG_Burst_Type burst;      /*!< MJPEG burst type */
+    uint8_t quality;             /*!< MJPEG quantization selection, 1-75:Q table selection, others:Q100(lossless) */
+    MJPEG_YUV_Mode_Type yuv;     /*!< MJPEG control YUV mode */
+    uint16_t waitCount;          /*!< Cycle count in wait state, default value:0x400 */
+    uint32_t bufferMjpeg;        /*!< MJPEG buffer addr */
+    uint32_t sizeMjpeg;          /*!< MJPEG buffer size */
+    uint32_t bufferCamYY;        /*!< CAM buffer address of Y frame */
+    uint32_t sizeCamYY;          /*!< CAM buffer size of Y frame */
+    uint32_t bufferCamUV;        /*!< CAM buffer address of UV frame */
+    uint32_t sizeCamUV;          /*!< CAM buffer size of UV frame */
+    uint16_t resolutionX;        /*!< CAM RESOLUTION X */
+    uint16_t resolutionY;        /*!< CAM RESOLUTION Y */
+    BL_Fun_Type bitOrderEnable;  /*!< MJPEG bitstream order adjustment */
+    BL_Fun_Type evenOrderEnable; /*!< Enable:U is even byte of UV frame and V is odd byte of UV frame */
+    BL_Fun_Type swapModeEnable;  /*!< Enable or disable write swap mode */
+    BL_Fun_Type overStopEnable;  /*!< Enable:if camera overwrite error occur,mjpeg will stop fetch data */
+    BL_Fun_Type reflectDmy;      /*!< UV dummy with relect */
+    BL_Fun_Type verticalDmy;     /*!< MJPEG last half vertical block with dummy data 0x80 */
+    BL_Fun_Type horizationalDmy; /*!< MJPEG last half horizational block with dummy data 0x80 */
+} MJPEG_CFG_Type;
+
+/**
+ *  @brief MJPEG packet configuration strcut definition
+ */
+typedef struct
+{
+    BL_Fun_Type packetEnable; /*!< Enable or disable packet mode */
+    BL_Fun_Type endToTail;    /*!< Enable or disable jpeg end jump to packet tail */
+    uint16_t frameHead;       /*!< Preserve head memory space for each frame */
+    BL_Fun_Type frameTail;    /*!< Enable:auto fill tail 0xFF and 0xD9 */
+    uint16_t packetHead;      /*!< Packet head byte count */
+    uint16_t packetBody;      /*!< Packet body byte count */
+    uint16_t packetTail;      /*!< Packet tail byte count */
+} MJPEG_Packet_Type;
+
+/**
+ *  @brief MJPEG frame information strcut definition
+ */
+typedef struct
+{
+    uint8_t validFrames;    /*!< Valid frames */
+    uint32_t curFrameAddr;  /*!< Current frame address */
+    uint32_t curFrameBytes; /*!< Current frame bytes */
+    uint8_t curFrameQ;      /*!< Current frame Q mode */
+    uint32_t status;        /*!< MJPEG module status */
+} MJPEG_Frame_Info;
+
+/*@} end of group MJPEG_Public_Types */
+
+/** @defgroup  MJPEG_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  MJPEG_YUV_MODE_TYPE
+ *  @{
+ */
+#define IS_MJPEG_YUV_MODE_TYPE(type) (((type) == MJPEG_YUV420) ||        \
+                                      ((type) == MJPEG_YUV400) ||        \
+                                      ((type) == MJPEG_YUV422_PLANAR) || \
+                                      ((type) == MJPEG_YUV422_INTERLEAVE))
+
+/** @defgroup  MJPEG_BURST_TYPE
+ *  @{
+ */
+#define IS_MJPEG_BURST_TYPE(type) (((type) == MJPEG_BURST_SINGLE) || \
+                                   ((type) == MJPEG_BURST_INCR4) ||  \
+                                   ((type) == MJPEG_BURST_INCR8) ||  \
+                                   ((type) == MJPEG_BURST_INCR16))
+
+/** @defgroup  MJPEG_SWAP_BLOCK_TYPE
+ *  @{
+ */
+#define IS_MJPEG_SWAP_BLOCK_TYPE(type) (((type) == MJPEG_BLOCK_0) || \
+                                        ((type) == MJPEG_BLOCK_1))
+
+/** @defgroup  MJPEG_INT_TYPE
+ *  @{
+ */
+#define IS_MJPEG_INT_TYPE(type) (((type) == MJPEG_INT_NORMAL) ||          \
+                                 ((type) == MJPEG_INT_CAM_OVERWRITE) ||   \
+                                 ((type) == MJPEG_INT_MEM_OVERWRITE) ||   \
+                                 ((type) == MJPEG_INT_FRAME_OVERWRITE) || \
+                                 ((type) == MJPEG_INT_BACK_IDLE) ||       \
+                                 ((type) == MJPEG_INT_SWAP) ||            \
+                                 ((type) == MJPEG_INT_ALL))
+
+/*@} end of group MJPEG_Public_Constants */
+
+/** @defgroup  MJPEG_Public_Macros
+ *  @{
+ */
+
+/*@} end of group MJPEG_Public_Macros */
+
+/** @defgroup  MJPEG_Public_Functions
+ *  @{
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+void MJPEG_IRQHandler(void);
+#endif
+void MJPEG_Init(MJPEG_CFG_Type *cfg);
+void MJPEG_Packet_Config(MJPEG_Packet_Type *cfg);
+void MJPEG_Set_YUYV_Order_Interleave(uint8_t y0, uint8_t u0, uint8_t y1, uint8_t v0);
+void MJPEG_Set_YUYV_Order_Planar(uint8_t yy, uint8_t uv);
+void MJPEG_Deinit(void);
+void MJPEG_Enable(void);
+void MJPEG_Disable(void);
+void MJPEG_SW_Enable(uint8_t count);
+void MJPEG_SW_Run(void);
+void MJPEG_Get_Frame_Info(MJPEG_Frame_Info *info);
+uint8_t MJPEG_Get_Frame_Count(void);
+void MJPEG_Pop_Frame(void);
+void MJPEG_Current_Block_Clear(void);
+MJPEG_Swap_Block_Type MJPEG_Get_Current_Block(void);
+BL_Sts_Type MJPEG_Block_Is_Full(MJPEG_Swap_Block_Type block);
+BL_Sts_Type MJPEG_Current_Block_Is_Start(void);
+BL_Sts_Type MJPEG_Current_Block_Is_End(void);
+uint32_t MJPEG_Get_Remain_Bit(void);
+void MJPEG_Set_Frame_Threshold(uint8_t count);
+void MJPEG_IntMask(MJPEG_INT_Type intType, BL_Mask_Type intMask);
+void MJPEG_IntClr(MJPEG_INT_Type intType);
+void MJPEG_Int_Callback_Install(MJPEG_INT_Type intType, intCallback_Type *cbFun);
+
+/*@} end of group MJPEG_Public_Functions */
+
+/*@} end of group MJPEG */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_MJPEG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_nf_cfg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_nf_cfg.h
new file mode 100644
index 00000000..cc5e9b12
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_nf_cfg.h
@@ -0,0 +1,48 @@
+/**
+  ******************************************************************************
+  * @file    bl702_nf_cfg.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_NF_CFG_H__
+#define __BL702_NF_CFG_H__
+
+#include "string.h"
+#include "bl702_nflash.h"
+#include "bl702_sf_ctrl.h"
+
+/** @defgroup  NF_CFG_Public_Functions
+ *  @{
+ */
+uint32_t NF_Cfg_Flash_Identify(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, Nand_Flash_Cfg_Type *pFlashCfg);
+
+#endif /* __BL702_NF_CFG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_nflash.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_nflash.h
new file mode 100644
index 00000000..0bb232fd
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_nflash.h
@@ -0,0 +1,196 @@
+/**
+  ******************************************************************************
+  * @file    bl702_nflah.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_NFLAH_H__
+#define __BL702_NFLAH_H__
+
+#include "bl702_common.h"
+#include "bl702_sf_ctrl.h"
+
+/** @addtogroup  BL602_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SFLAH
+ *  @{
+ */
+
+/** @defgroup  SFLAH_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief Serial flash configuration structure type definition
+ */
+/*@} end of group SFLAH_Public_Types */
+
+/** @defgroup  SFLAH_Public_Constants
+ *  @{
+ */
+
+/*@} end of group SFLAH_Public_Constants */
+
+/** @defgroup  SFLAH_Public_Macros
+ *  @{
+ */
+#define BFLB_NAND_FLASH_BLK_DATA_SIZE   (128 * 1024)
+#define BFLB_NAND_FLASH_BLK_TOTAL_SIZE  ((128 + 4) * 1024)
+#define BFLB_NAND_FLASH_PAGE_SIZE       (2048)
+#define BFLB_NAND_FLASH_PAGE_TOTAL_SIZE (2048 + 64)
+#define BFLB_NAND_FLASH_PAGES_PER_BLOCK (64)
+#define BFLB_NAND_FLASH_CMD_INVALID     (0xff)
+#define DISK_SECTOR_SIZE                (512)
+typedef unsigned char BYTE;
+typedef unsigned long DWORD;
+typedef unsigned int UINT;
+typedef BYTE DSTATUS;
+typedef enum {
+    RES_OK = 0, /* 0: Successful */
+    RES_ERROR,  /* 1: R/W Error */
+    RES_WRPRT,  /* 2: Write Protected */
+    RES_NOTRDY, /* 3: Not Ready */
+    RES_PARERR  /* 4: Invalid Parameter */
+} DRESULT;
+
+typedef enum {
+    READ_DATA_FROM_CACHE = 0,       //date:2048 bytes in each page
+    READ_SPARE_DATA_FROM_CACHE = 1, //spare date:64 bytes in each page
+} BL_Nand_Flash_READ_DATE_TYPE;
+
+typedef struct
+{
+    uint8_t ioMode;               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
+    uint8_t cReadSupport;         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+    uint8_t clkDelay;             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+    uint8_t clkInvert;            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+    uint8_t resetEnCmd;           /*!< Flash enable reset command */
+    uint8_t resetCmd;             /*!< Flash reset command */
+    uint8_t resetCreadCmd;        /*!< Flash reset continuous read command */
+    uint8_t resetCreadCmdSize;    /*!< Flash reset continuous read command size */
+    uint8_t jedecIdCmd;           /*!< JEDEC ID command */
+    uint8_t jedecIdCmdDmyClk;     /*!< JEDEC ID command dummy clock */
+    uint8_t qpiJedecIdCmd;        /*!< QPI JEDEC ID comamnd */
+    uint8_t qpiJedecIdCmdDmyClk;  /*!< QPI JEDEC ID command dummy clock */
+    uint8_t sectorSize;           /*!< *1024bytes */
+    uint8_t mid;                  /*!< Manufacturer ID */
+    uint16_t pageSize;            /*!< Page size */
+    uint8_t chipEraseCmd;         /*!< Chip erase cmd */
+    uint8_t sectorEraseCmd;       /*!< Sector erase command */
+    uint8_t blk128EraseCmd;       /*!< Block 128K erase command */
+    uint8_t writeEnableCmd;       /*!< Need before every erase or program */
+    uint8_t programLoadCmd;       /*!< Program Load cmd */
+    uint8_t qprogramLoadCmd;      /*!< Program Load cmd x4*/
+    uint8_t pageProgramCmd;       /*!< Page program cmd */
+    uint8_t qpageProgramCmd;      /*!< QIO page program cmd */
+    uint8_t qppAddrMode;          /*!< QIO page program address mode */
+    uint8_t pageReadToCacheCmd;   /*!< Page read comamnd */
+    uint8_t getFeaturesCmd;       /*!< GET FEATURES command to read the status */
+    uint8_t setFeaturesCmd;       /*!< SET FEATURES command to read the status */
+    uint8_t readFromCacheCmd;     /*!< Read from cache command */
+    uint8_t fastReadCmd;          /*!< Fast read command */
+    uint8_t frDmyClk;             /*!< Fast read command dummy clock */
+    uint8_t qpiFastReadCmd;       /*!< QPI fast read command */
+    uint8_t qpiFrDmyClk;          /*!< QPI fast read command dummy clock */
+    uint8_t fastReadDoCmd;        /*!< Fast read dual output command */
+    uint8_t frDoDmyClk;           /*!< Fast read dual output command dummy clock */
+    uint8_t fastReadDioCmd;       /*!< Fast read dual io comamnd */
+    uint8_t frDioDmyClk;          /*!< Fast read dual io command dummy clock */
+    uint8_t fastReadQoCmd;        /*!< Fast read quad output comamnd */
+    uint8_t frQoDmyClk;           /*!< Fast read quad output comamnd dummy clock */
+    uint8_t fastReadQioCmd;       /*!< Fast read quad io comamnd */
+    uint8_t frQioDmyClk;          /*!< Fast read quad io comamnd dummy clock */
+    uint8_t qpiFastReadQioCmd;    /*!< QPI fast read quad io comamnd */
+    uint8_t qpiFrQioDmyClk;       /*!< QPI fast read QIO dummy clock */
+    uint8_t qpiPageProgramCmd;    /*!< QPI program command */
+    uint8_t writeVregEnableCmd;   /*!< Enable write reg */
+    uint8_t wrEnableIndex;        /*!< Write enable register index */
+    uint8_t qeIndex;              /*!< Quad mode enable register index */
+    uint8_t busyIndex;            /*!< Busy status register index */
+    uint8_t wrEnableBit;          /*!< Write enable bit pos */
+    uint8_t qeBit;                /*!< Quad enable bit pos */
+    uint8_t busyBit;              /*!< Busy status bit pos */
+    uint8_t wrEnableWriteRegLen;  /*!< Register length of write enable */
+    uint8_t wrEnableReadRegLen;   /*!< Register length of write enable status */
+    uint8_t qeWriteRegLen;        /*!< Register length of contain quad enable */
+    uint8_t qeReadRegLen;         /*!< Register length of contain quad enable status */
+    uint8_t releasePowerDown;     /*!< Release power down command */
+    uint8_t busyReadRegLen;       /*!< Register length of contain busy status */
+    uint8_t readRegCmd[4];        /*!< Read register command buffer */
+    uint8_t writeRegCmd[4];       /*!< Write register command buffer */
+    uint8_t enterQpi;             /*!< Enter qpi command */
+    uint8_t exitQpi;              /*!< Exit qpi command */
+    uint8_t cReadMode;            /*!< Config data for continuous read mode */
+    uint8_t cRExit;               /*!< Config data for exit continuous read mode */
+    uint8_t burstWrapCmd;         /*!< Enable burst wrap command */
+    uint8_t burstWrapCmdDmyClk;   /*!< Enable burst wrap command dummy clock */
+    uint8_t burstWrapDataMode;    /*!< Data and address mode for this command */
+    uint8_t burstWrapData;        /*!< Data to enable burst wrap */
+    uint8_t deBurstWrapCmd;       /*!< Disable burst wrap command */
+    uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
+    uint8_t deBurstWrapDataMode;  /*!< Data and address mode for this command */
+    uint8_t deBurstWrapData;      /*!< Data to disable burst wrap */
+    uint16_t timeEsector;         /*!< 4K erase time */
+    uint16_t timeE132k;           /*!< 132K erase time */
+    uint16_t timePagePgm;         /*!< Page program time */
+    uint16_t timeCe;              /*!< Chip erase time in ms */
+    uint8_t pdDelay;              /*!< Release power down command delay time for wake up */
+    uint8_t qeData;               /*!< QE set data */
+} __attribute__((packed)) Nand_Flash_Cfg_Type;
+
+//BL_Nand_Flash_Program_Bit_Err_Type ATTR_TCM_SECTION NFlash_Pass(uint8_t errorCode, BL_Nand_Flash_OP_Type opType);
+BL_Err_Type NFlash_GetJedecId(Nand_Flash_Cfg_Type *flashCfg, uint8_t *data);
+BL_Err_Type ATTR_TCM_SECTION NFlash_Erase(Nand_Flash_Cfg_Type *flashCfg, uint32_t startAddr, uint32_t endAddr);
+BL_Err_Type ATTR_TCM_SECTION NFlash_Blk128_Erase(Nand_Flash_Cfg_Type *flashCfg, uint32_t blockNum);
+BL_Err_Type ATTR_TCM_SECTION NFlash_Write_Enable(Nand_Flash_Cfg_Type *flashCfg);
+BL_Err_Type ATTR_TCM_SECTION NFlash_Read(Nand_Flash_Cfg_Type *flashCfg, uint32_t addr, uint8_t *data, uint32_t len);
+BL_Err_Type ATTR_TCM_SECTION NFlash_Program(Nand_Flash_Cfg_Type *flashCfg, uint32_t addr, const uint8_t *data, uint32_t len);
+BL_Err_Type ATTR_TCM_SECTION NFlash_Page_Read_To_Cache(Nand_Flash_Cfg_Type *flashCfg, uint32_t absolutePageNum);
+BL_Err_Type ATTR_TCM_SECTION NFlash_Get_Feature(Nand_Flash_Cfg_Type *flashCfg, uint8_t *data, uint8_t cmdType);
+BL_Err_Type ATTR_TCM_SECTION NFlash_Read_From_Cache(Nand_Flash_Cfg_Type *flashCfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t readType);
+BL_Err_Type ATTR_TCM_SECTION NFlash_Program_Execute(Nand_Flash_Cfg_Type *flashCfg, uint32_t addr);
+BL_Err_Type ATTR_TCM_SECTION NFlash_Set_Feature(Nand_Flash_Cfg_Type *flashCfg);
+BL_Err_Type ATTR_TCM_SECTION NFlash_Program_Load(Nand_Flash_Cfg_Type *flashCfg, uint32_t addr, const uint8_t *data, uint32_t len);
+BL_Err_Type ATTR_TCM_SECTION NFlash_Check_Bad_Block(Nand_Flash_Cfg_Type *flashCfg, uint32_t blockNum, uint8_t *data, uint32_t len);
+DRESULT ff_disk_read(BYTE pdrv, BYTE *buff, DWORD sector, UINT count);
+DRESULT ff_disk_write(BYTE pdrv, const BYTE *buff, DWORD sector, UINT count);
+DSTATUS ff_disk_initialize(BYTE pdrv);
+
+/*@} end of group SFLAH_Public_Functions */
+
+/*@} end of group SFLAH */
+
+/*@} end of group BL602_Peripheral_Driver */
+
+#endif /* __BL602_SFLAH_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_pds.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_pds.h
new file mode 100644
index 00000000..5c486a23
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_pds.h
@@ -0,0 +1,798 @@
+/**
+  ******************************************************************************
+  * @file    bl702_pds.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_PDS_H__
+#define __BL702_PDS_H__
+
+#include "pds_reg.h"
+#include "bl702_ef_ctrl.h"
+#include "bl702_aon.h"
+#include "bl702_hbn.h"
+#include "bl702_sflash.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  PDS
+ *  @{
+ */
+
+/** @defgroup  PDS_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief PDS LDO level type definition
+ */
+typedef enum {
+    PDS_LDO_LEVEL_0P60V = 0,  /*!< PDS LDO voltage 0.60V */
+    PDS_LDO_LEVEL_0P65V = 1,  /*!< PDS LDO voltage 0.65V */
+    PDS_LDO_LEVEL_0P70V = 2,  /*!< PDS LDO voltage 0.70V */
+    PDS_LDO_LEVEL_0P75V = 3,  /*!< PDS LDO voltage 0.75V */
+    PDS_LDO_LEVEL_0P80V = 4,  /*!< PDS LDO voltage 0.80V */
+    PDS_LDO_LEVEL_0P85V = 5,  /*!< PDS LDO voltage 0.85V */
+    PDS_LDO_LEVEL_0P90V = 6,  /*!< PDS LDO voltage 0.90V */
+    PDS_LDO_LEVEL_0P95V = 7,  /*!< PDS LDO voltage 0.95V */
+    PDS_LDO_LEVEL_1P00V = 8,  /*!< PDS LDO voltage 1.00V */
+    PDS_LDO_LEVEL_1P05V = 9,  /*!< PDS LDO voltage 1.05V */
+    PDS_LDO_LEVEL_1P10V = 10, /*!< PDS LDO voltage 1.10V */
+    PDS_LDO_LEVEL_1P15V = 11, /*!< PDS LDO voltage 1.15V */
+    PDS_LDO_LEVEL_1P20V = 12, /*!< PDS LDO voltage 1.20V */
+    PDS_LDO_LEVEL_1P25V = 13, /*!< PDS LDO voltage 1.25V */
+    PDS_LDO_LEVEL_1P30V = 14, /*!< PDS LDO voltage 1.30V */
+    PDS_LDO_LEVEL_1P35V = 15, /*!< PDS LDO voltage 1.35V */
+} PDS_LDO_LEVEL_Type;
+
+/**
+ *  @brief PDS RAM configuration type definition
+ */
+typedef struct
+{
+    uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_RET1N  : 1;  /*!< [0] 0~16KB cpu_ram RET1N */
+    uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_RET1N : 1;  /*!< [1] 16~32KB cpu_ram RET1N */
+    uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_RET1N : 1;  /*!< [2] 32~48KB cpu_ram RET1N */
+    uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_RET1N : 1;  /*!< [3] 48~64KB cpu_ram RET1N */
+    uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_RET2N  : 1;  /*!< [4] 0~16KB cpu_ram RET2N */
+    uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_RET2N : 1;  /*!< [5] 16~32KB cpu_ram RET2N */
+    uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_RET2N : 1;  /*!< [6] 32~48KB cpu_ram RET2N */
+    uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_RET2N : 1;  /*!< [7] 48~64KB cpu_ram RET2N */
+    uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_PGEN   : 1;  /*!< [8] 0~16KB cpu_ram PGEN */
+    uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_PGEN  : 1;  /*!< [9] 16~32KB cpu_ram PGEN */
+    uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_PGEN  : 1;  /*!< [10] 32~48KB cpu_ram PGEN */
+    uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_PGEN  : 1;  /*!< [11] 48~64KB cpu_ram PGEN */
+    uint32_t PDS_RAM_CFG_RSV                     : 20; /*!< [31:12]reserve */
+} PDS_RAM_CFG_Type;
+
+/**
+ *  @brief PDS PAD pin configuration type definition
+ */
+typedef enum {
+    PDS_PAD_PIN_GPIO_17, /*!< PAD GPIO 17 */
+    PDS_PAD_PIN_GPIO_18, /*!< PAD GPIO 18 */
+    PDS_PAD_PIN_GPIO_19, /*!< PAD GPIO 19 */
+    PDS_PAD_PIN_GPIO_20, /*!< PAD GPIO 20 */
+    PDS_PAD_PIN_GPIO_21, /*!< PAD GPIO 21 */
+    PDS_PAD_PIN_GPIO_22, /*!< PAD GPIO 22 */
+    PDS_PAD_PIN_GPIO_23, /*!< PAD GPIO 23 */
+    PDS_PAD_PIN_GPIO_24, /*!< PAD GPIO 24 */
+    PDS_PAD_PIN_GPIO_25, /*!< PAD GPIO 25 */
+    PDS_PAD_PIN_GPIO_26, /*!< PAD GPIO 26 */
+    PDS_PAD_PIN_GPIO_27, /*!< PAD GPIO 27 */
+    PDS_PAD_PIN_GPIO_28, /*!< PAD GPIO 28 */
+} PDS_PAD_PIN_Type;
+
+/**
+ *  @brief PDS PAD configuration type definition
+ */
+typedef enum {
+    PDS_PAD_CFG_PULL_NONE, /*!< no PD/PU/IE on PAD */
+    PDS_PAD_CFG_PULL_DOWN, /*!< Pulldown PAD */
+    PDS_PAD_CFG_PULL_UP,   /*!< Pullup PAD */
+    PDS_PAD_CFG_ACTIVE_IE, /*!< Active IE */
+} PDS_PAD_CFG_Type;
+
+/**
+ *  @brief PDS configuration type definition
+ */
+typedef struct
+{
+    uint32_t pdsStart                : 1; /*!< [0]PDS Start */
+    uint32_t sleepForever            : 1; /*!< [1]PDS sleep forever */
+    uint32_t xtalForceOff            : 1; /*!< [2]Power off xtal force */
+    uint32_t saveWifiState           : 1; /*!< [3]Save WIFI State Before Enter PDS */
+    uint32_t dcdc18Off               : 1; /*!< [4]power down dcdc18 during PDS */
+    uint32_t bgSysOff                : 1; /*!< [5]power down bg_sys during PDS */
+    uint32_t gpioIePuPd              : 1; /*!< [6]allow PDS Control the GPIO IE/PU/PD at Sleep Mode */
+    uint32_t puFlash                 : 1; /*!< [7]turn off Flash Power During PDS */
+    uint32_t clkOff                  : 1; /*!< [8]gate clock during PDS (each pwr domain has its own control) */
+    uint32_t memStby                 : 1; /*!< [9]mem_stby during PDS (each power domain can has its own control) */
+    uint32_t swPuFlash               : 1; /*!< [10]SW Turn on Flash */
+    uint32_t isolation               : 1; /*!< [11]Isolation during PDS (each power domain can has its own control) */
+    uint32_t waitXtalRdy             : 1; /*!< [12]wait XTAL Ready during before PDS Interrupt */
+    uint32_t pdsPwrOff               : 1; /*!< [13]Power off during PDS (each power domain can has its own control) */
+    uint32_t xtalOff                 : 1; /*!< [14]xtal power down during PDS */
+    uint32_t socEnbForceOn           : 1; /*!< [15]pds_soc_enb always active */
+    uint32_t pdsRstSocEn             : 1; /*!< [16]pds_rst controlled by PDS */
+    uint32_t pdsRC32mOn              : 1; /*!< [17]RC32M always on or RC32M on/off controlled by PDS state */
+    uint32_t pdsLdoVselEn            : 1; /*!< [18]PDS "SLEEP" control LDO voltage enable */
+    uint32_t pdsRamLowPowerWithClkEn : 1; /*!< [19]Control SRAM Low Power with CLK (Sync) */
+    uint32_t reserved20              : 1; /*!< [20]Reserved */
+    uint32_t cpu0WfiMask             : 1; /*!< [21]pds start condition mask np_wfi */
+    uint32_t ldo11Off                : 1; /*!< [22]power down ldo11 during PDS */
+    uint32_t pdsForceRamClkEn        : 1; /*!< [23]Force SRAM CLK Enable */
+    uint32_t pdsLdoVol               : 4; /*!< [27:24]LDO voltage value in PDS mode */
+    uint32_t pdsCtlRfSel             : 2; /*!< [29:28]select the way RF controlled by PDS */
+    uint32_t pdsCtlPllSel            : 2; /*!< [31:30]select the way PLL controlled by PDS */
+} PDS_CFG_Type;
+
+/**
+ *  @brief PDS configuration type definition
+ */
+typedef struct
+{
+    uint32_t pdsStart                : 1; /*!< [0]PDS Start */
+    uint32_t sleepForever            : 1; /*!< [1]PDS sleep forever */
+    uint32_t xtalForceOff            : 1; /*!< [2]Power off xtal force */
+    uint32_t saveWifiState           : 1; /*!< [3]Save WIFI State Before Enter PDS */
+    uint32_t dcdc18Off               : 1; /*!< [4]power down dcdc18 during PDS */
+    uint32_t bgSysOff                : 1; /*!< [5]power down bg_sys during PDS */
+    uint32_t gpioIePuPd              : 1; /*!< [6]allow PDS Control the GPIO IE/PU/PD at Sleep Mode */
+    uint32_t puFlash                 : 1; /*!< [7]turn off Flash Power During PDS */
+    uint32_t clkOff                  : 1; /*!< [8]gate clock during PDS (each pwr domain has its own control) */
+    uint32_t memStby                 : 1; /*!< [9]mem_stby during PDS (each power domain can has its own control) */
+    uint32_t swPuFlash               : 1; /*!< [10]SW Turn on Flash */
+    uint32_t isolation               : 1; /*!< [11]Isolation during PDS (each power domain can has its own control) */
+    uint32_t waitXtalRdy             : 1; /*!< [12]wait XTAL Ready during before PDS Interrupt */
+    uint32_t pdsPwrOff               : 1; /*!< [13]Power off during PDS (each power domain can has its own control) */
+    uint32_t xtalOff                 : 1; /*!< [14]xtal power down during PDS */
+    uint32_t socEnbForceOn           : 1; /*!< [15]pds_soc_enb always active */
+    uint32_t pdsRstSocEn             : 1; /*!< [16]pds_rst controlled by PDS */
+    uint32_t pdsRC32mOn              : 1; /*!< [17]RC32M always on or RC32M on/off controlled by PDS state */
+    uint32_t pdsLdoVselEn            : 1; /*!< [18]PDS "SLEEP" control LDO voltage enable */
+    uint32_t pdsRamLowPowerWithClkEn : 1; /*!< [19]Control SRAM Low Power with CLK (Sync) */
+    uint32_t reserved20              : 1; /*!< [20]Reserved */
+    uint32_t cpu0WfiMask             : 1; /*!< [21]pds start condition mask np_wfi */
+    uint32_t ldo11Off                : 1; /*!< [22]power down ldo11 during PDS */
+    uint32_t pdsForceRamClkEn        : 1; /*!< [23]Force SRAM CLK Enable */
+    uint32_t pdsLdoVol               : 4; /*!< [27:24]LDO voltage value in PDS mode */
+    uint32_t pdsCtlRfSel             : 2; /*!< [29:28]select the way RF controlled by PDS */
+    uint32_t pdsCtlPllSel            : 2; /*!< [31:30]select the way PLL controlled by PDS */
+} PDS_CTL_Type;
+
+/**
+ *  @brief PDS force configuration type definition
+ */
+typedef struct
+{
+    uint32_t forceCpuPwrOff  : 1;  /*!< [0]manual force NP power off */
+    uint32_t rsv1            : 1;  /*!< [1]reserve */
+    uint32_t forceBzPwrOff   : 1;  /*!< [2]manual force BZ power off */
+    uint32_t forceUsbPwrOff  : 1;  /*!< [3]manual force USB power off */
+    uint32_t forceCpuIsoEn   : 1;  /*!< [4]manual force NP isolation */
+    uint32_t rsv5            : 1;  /*!< [5]reserve */
+    uint32_t forceBzIsoEn    : 1;  /*!< [6]manual force BZ isolation */
+    uint32_t forceUsbIsoEn   : 1;  /*!< [7]manual force USB isolation */
+    uint32_t forceCpuPdsRst  : 1;  /*!< [8]manual force NP pds reset */
+    uint32_t rsv9            : 1;  /*!< [9]reserve */
+    uint32_t forceBzPdsRst   : 1;  /*!< [10]manual force BZ pds reset */
+    uint32_t forceUsbPdsRst  : 1;  /*!< [11]manual force USB pds reset */
+    uint32_t forceCpuMemStby : 1;  /*!< [12]manual force NP memory sleep */
+    uint32_t rsv13           : 1;  /*!< [13]reserve */
+    uint32_t forceBzMemStby  : 1;  /*!< [14]manual force BZ memory sleep */
+    uint32_t forceUsbMemStby : 1;  /*!< [15]manual force USB memory sleep */
+    uint32_t forceCpuGateClk : 1;  /*!< [16]manual force NP clock gated */
+    uint32_t rsv17           : 1;  /*!< [17]reserve */
+    uint32_t forceBzGateClk  : 1;  /*!< [18]manual force BZ clock gated */
+    uint32_t forceUsbGateClk : 1;  /*!< [19]manual force USB clock gated */
+    uint32_t rsv20_31        : 12; /*!< [31:20]reserve */
+} PDS_CTL2_Type;
+
+/**
+ *  @brief PDS force configuration type definition
+ */
+typedef struct
+{
+    uint32_t rsv0             : 1; /*!< [0]reserve */
+    uint32_t forceMiscPwrOff  : 1; /*!< [1]manual force MISC pwr_off */
+    uint32_t forceBlePwrOff   : 1; /*!< [2]manual force BZ_BLE pwr_off */
+    uint32_t rsv3_4           : 2; /*!< [4:3]reserve */
+    uint32_t forceBleIsoEn    : 1; /*!< [5]manual force BZ_BLE iso_en */
+    uint32_t rsv6             : 1; /*!< [6]reserve */
+    uint32_t forceMiscPdsRst  : 1; /*!< [7]manual force MISC pds_rst */
+    uint32_t forceBlePdsRst   : 1; /*!< [8]manual force BZ_BLE pds_rst */
+    uint32_t rsv9             : 1; /*!< [9]reserve */
+    uint32_t forceMiscMemStby : 1; /*!< [10]manual force MISC mem_stby */
+    uint32_t forceBleMemStby  : 1; /*!< [11]manual force BZ_BLE mem_stby */
+    uint32_t rsv12            : 1; /*!< [12]reserve */
+    uint32_t forceMiscGateClk : 1; /*!< [13]manual force MISC gate_clk */
+    uint32_t forceBleGateClk  : 1; /*!< [14]manual force BZ_BLE gate_clk */
+    uint32_t rsv15_23         : 9; /*!< [23:15]reserve */
+    uint32_t CpuIsoEn         : 1; /*!< [24]make NP isolated at PDS Sleep state */
+    uint32_t rsv25_26         : 2; /*!< [26:25]reserve */
+    uint32_t BzIsoEn          : 1; /*!< [27]make BZ isolated at PDS Sleep state */
+    uint32_t BleIsoEn         : 1; /*!< [28]make Ble isolated at PDS Sleep state */
+    uint32_t UsbIsoEn         : 1; /*!< [29]make USB isolated at PDS Sleep state */
+    uint32_t MiscIsoEn        : 1; /*!< [30]make misc isolated at PDS Sleep state */
+    uint32_t rsv31            : 1; /*!< [31]reserve */
+} PDS_CTL3_Type;
+
+/**
+ *  @brief PDS force configuration type definition
+ */
+typedef struct
+{
+    uint32_t cpuPwrOff     : 1; /*!< [0] */
+    uint32_t cpuRst        : 1; /*!< [1] */
+    uint32_t cpuMemStby    : 1; /*!< [2] */
+    uint32_t cpuGateClk    : 1; /*!< [3] */
+    uint32_t rsv4_11       : 8; /*!< [11:4]reserve */
+    uint32_t BzPwrOff      : 1; /*!< [12] */
+    uint32_t BzRst         : 1; /*!< [13] */
+    uint32_t BzMemStby     : 1; /*!< [14] */
+    uint32_t BzGateClk     : 1; /*!< [15] */
+    uint32_t BlePwrOff     : 1; /*!< [16] */
+    uint32_t BleRst        : 1; /*!< [17] */
+    uint32_t BleMemStby    : 1; /*!< [18] */
+    uint32_t BleGateClk    : 1; /*!< [19] */
+    uint32_t UsbPwrOff     : 1; /*!< [20] */
+    uint32_t UsbRst        : 1; /*!< [21] */
+    uint32_t UsbMemStby    : 1; /*!< [22] */
+    uint32_t UsbGateClk    : 1; /*!< [23] */
+    uint32_t MiscPwrOff    : 1; /*!< [24] */
+    uint32_t MiscRst       : 1; /*!< [25] */
+    uint32_t MiscMemStby   : 1; /*!< [26] */
+    uint32_t MiscGateClk   : 1; /*!< [27] */
+    uint32_t rsv28_29      : 2; /*!< [29:28]reserve */
+    uint32_t MiscAnaPwrOff : 1; /*!< [30] */
+    uint32_t MiscDigPwrOff : 1; /*!< [31] */
+} PDS_CTL4_Type;
+
+/**
+ *  @brief PDS default level configuration type definition
+ */
+typedef struct
+{
+    PDS_CTL_Type pdsCtl;   /*!< PDS_CTL configuration */
+    PDS_CTL2_Type pdsCtl2; /*!< PDS_CTL2 configuration */
+    PDS_CTL3_Type pdsCtl3; /*!< PDS_CTL3 configuration */
+    PDS_CTL4_Type pdsCtl4; /*!< PDS_CTL4 configuration */
+} PDS_DEFAULT_LV_CFG_Type;
+
+/**
+ *  @brief PDS interrupt type definition
+ */
+typedef enum {
+    PDS_INT_WAKEUP = 0,    /*!< PDS wakeup interrupt(assert bit while wakeup, include PDS_Timer/...) */
+    PDS_INT_RF_DONE,       /*!< PDS RF done interrupt */
+    PDS_INT_PLL_DONE,      /*!< PDS PLL done interrupt */
+    PDS_INT_PDS_SLEEP_CNT, /*!< wakeup trigger by pds_sleep_cnt=0 */
+    PDS_INT_HBN_IRQ_OUT0,  /*!< wakeup trigger by hbn_irq_out[0] */
+    PDS_INT_HBN_IRQ_OUT1,  /*!< wakeup trigger by hbn_irq_out[1] */
+    PDS_INT_GPIO_IRQ,      /*!< wakeup trigger by gpio_irq */
+    PDS_INT_IRRX,          /*!< wakeup trigger by irrx_int */
+    PDS_INT_BLE_SLP_IRQ,   /*!< wakeup trigger by ble_slp_irq */
+    PDS_INT_USB_WKUP,      /*!< wakeup trigger by usb_wkup */
+    PDS_INT_KYS_QDEC,      /*!< wakeup trigger by kys_int or qdec */
+    PDS_INT_MAX,           /*!< PDS int max number */
+} PDS_INT_Type;
+
+/**
+ *  @brief PDS vddcore GPIO interrupt type definition
+ */
+typedef enum {
+    PDS_VDDCORE_GPIO_SRC_GPIO_0, /*!< PDS VDDCORE GPIO0 as PDS interrupt source */
+    PDS_VDDCORE_GPIO_SRC_GPIO_1, /*!< PDS VDDCORE GPIO1 as PDS interrupt source */
+    PDS_VDDCORE_GPIO_SRC_GPIO_2, /*!< PDS VDDCORE GPIO2 as PDS interrupt source */
+    PDS_VDDCORE_GPIO_SRC_GPIO_3, /*!< PDS VDDCORE GPIO3 as PDS interrupt source */
+    PDS_VDDCORE_GPIO_SRC_GPIO_4, /*!< PDS VDDCORE GPIO4 as PDS interrupt source */
+    PDS_VDDCORE_GPIO_SRC_GPIO_5, /*!< PDS VDDCORE GPIO5 as PDS interrupt source */
+    PDS_VDDCORE_GPIO_SRC_GPIO_6, /*!< PDS VDDCORE GPIO6 as PDS interrupt source */
+    PDS_VDDCORE_GPIO_SRC_GPIO_7, /*!< PDS VDDCORE GPIO7 as PDS interrupt source */
+} PDS_VDDCORE_GPIO_SRC_Type;
+
+/**
+ *  @brief PDS reset event type definition
+ */
+typedef enum {
+    PDS_RST_EVENT_BUS_RST,        /*!< hreset_n (Bus Reset) */
+    PDS_RST_EVENT_HBN_PWR_ON_RST, /*!< pwr_rst_n (hbn power on reset) */
+    PDS_RST_EVENT_PDS_RST,        /*!< pds_rst_n (pds reset) */
+    PDS_RST_EVENT_MAX,            /*!< PDS rst event max number */
+} PDS_RST_EVENT_Type;
+
+/**
+ *  @brief PDS PLL status type definition
+ */
+typedef enum {
+    PDS_PLL_STS_OFF = 0,   /*!< 2'b00 */
+    PDS_PLL_STS_SFREG = 1, /*!< 2'b01 */
+    PDS_PLL_STS_PU = 2,    /*!< 2'b10 */
+    PDS_PLL_STS_RDY = 3,   /*!< 2'b11 */
+} PDS_PLL_STS_Type;
+
+/**
+ *  @brief PDS RF status type definition
+ */
+typedef enum {
+    PDS_RF_STS_OFF = 0,        /*!< 4'b0000 */
+    PDS_RF_STS_PU_MBG = 1,     /*!< 4'b0001 */
+    PDS_RF_STS_PU_LDO15RF = 3, /*!< 4'b0011 */
+    PDS_RF_STS_PU_SFREG = 7,   /*!< 4'b0111 */
+    PDS_RF_STS_BZ_EN_AON = 15, /*!< 4'b1111 */
+} PDS_RF_STS_Type;
+
+/**
+ *  @brief PDS status type definition
+ */
+typedef enum {
+    PDS_STS_IDLE = 0,            /*!< 4'b0000 */
+    PDS_STS_ECG = 8,             /*!< 4'b1000 */
+    PDS_STS_ERST = 12,           /*!< 4'b1100 */
+    PDS_STS_EISO = 15,           /*!< 4'b1111 */
+    PDS_STS_POFF = 7,            /*!< 4'b0111 */
+    PDS_STS_PRE_BGON = 3,        /*!< 4'b0011 */
+    PDS_STS_PRE_BGON1 = 1,       /*!< 4'b0001 */
+    PDS_STS_BGON = 5,            /*!< 4'b0101 */
+    PDS_STS_CLK_SW_32M = 4,      /*!< 4'b0100 */
+    PDS_STS_PON_DCDC = 6,        /*!< 4'b0110 */
+    PDS_STS_PON_LDO11_MISC = 14, /*!< 4'b1110 */
+    PDS_STS_PON = 10,            /*!< 4'b1010 */
+    PDS_STS_DISO = 2,            /*!< 4'b0010 */
+    PDS_STS_DCG = 13,            /*!< 4'b1101 */
+    PDS_STS_DRST = 11,           /*!< 4'b1011 */
+    PDS_STS_WAIT_EFUSE = 9,      /*!< 4'b1001 */
+} PDS_STS_Type;
+
+/**
+ *  @brief PLL XTAL type definition
+ */
+typedef enum {
+    PDS_PLL_XTAL_NONE,  /*!< XTAL is none */
+    PDS_PLL_XTAL_32M,   /*!< XTAL is 32M */
+    PDS_PLL_XTAL_RC32M, /*!< XTAL is RC32M */
+} PDS_PLL_XTAL_Type;
+
+/**
+ *  @brief PLL output clock type definition
+ */
+typedef enum {
+    PDS_PLL_CLK_480M, /*!< PLL output clock:480M */
+    PDS_PLL_CLK_240M, /*!< PLL output clock:240M */
+    PDS_PLL_CLK_192M, /*!< PLL output clock:192M */
+    PDS_PLL_CLK_160M, /*!< PLL output clock:160M */
+    PDS_PLL_CLK_120M, /*!< PLL output clock:120M */
+    PDS_PLL_CLK_96M,  /*!< PLL output clock:96M */
+    PDS_PLL_CLK_80M,  /*!< PLL output clock:80M */
+    PDS_PLL_CLK_48M,  /*!< PLL output clock:48M */
+    PDS_PLL_CLK_32M,  /*!< PLL output clock:32M */
+} PDS_PLL_CLK_Type;
+
+/**
+ *  @brief PDS level 0-7 mode HBN GPIO interrupt trigger type definition
+ */
+typedef enum {
+    PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE,  /*!< PDS level 0-7 mode HBN GPIO INT trigger type: sync falling edge trigger */
+    PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_EDGE,   /*!< PDS level 0-7 mode HBN GPIO INT trigger type: sync rising edge trigger */
+    PDS_AON_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL,     /*!< PDS level 0-7 mode HBN GPIO INT trigger type: sync low level trigger */
+    PDS_AON_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL,    /*!< PDS level 0-7 mode HBN GPIO INT trigger type: sync high level trigger */
+    PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE, /*!< PDS level 0-7 mode HBN GPIO INT trigger type: async falling edge trigger */
+    PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE,  /*!< PDS level 0-7 mode HBN GPIO INT trigger type: async rising edge trigger */
+    PDS_AON_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL,    /*!< PDS level 0-7 mode HBN GPIO INT trigger type: async low level trigger */
+    PDS_AON_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL,   /*!< PDS level 0-7 mode HBN GPIO INT trigger type: async high level trigger */
+} PDS_AON_GPIO_INT_Trigger_Type;
+
+/**
+ *  @brief PDS APP configuration type definition
+ */
+typedef struct
+{
+    uint8_t pdsLevel;                                 /*!< PDS level */
+    uint8_t turnOffXtal32m;                           /*!< Wheather turn off XTAL32M */
+    uint8_t turnOffDll;                               /*!< Wheather turn off DLL */
+    uint8_t turnOffRF;                                /*!< Wheather turn off RF */
+    uint8_t useXtal32k;                               /*!< Wheather use xtal 32K as 32K clock source,otherwise use rc32k */
+    uint8_t pdsAonGpioWakeupSrc;                      /*!< PDS level 0-7,31 mode aon GPIO Wakeup source(HBN wakeup pin) */
+    PDS_AON_GPIO_INT_Trigger_Type pdsAonGpioTrigType; /*!< PDS level 0-7,31 mode aon GPIO Triger type(HBN wakeup pin) */
+    uint8_t powerDownFlash;                           /*!< Whether power down flash */
+    uint8_t pdsHoldGpio;                              /*!< Whether pds hold gpio level */
+    uint8_t turnOffFlashPad;                          /*!< Whether turn off flash pad(GPIO17-GPIO22, GPIO23-GPIO28) */
+    uint8_t flashPinCfg;                              /*!< 0 ext flash 23-28, 1 internal flash 23-28, 2 internal flash 23-28, 3 ext flash 17-22 */
+    uint8_t turnoffPLL;                               /*!< Whether trun off PLL */
+    uint8_t xtalType;                                 /*!< XTal type, used when user choose turn off PLL, PDS will turn on when exit PDS mode */
+    uint8_t flashContRead;                            /*!< Whether enable flash continue read */
+    uint32_t sleepTime;                               /*!< PDS sleep time */
+    SPI_Flash_Cfg_Type *flashCfg;                     /*!< Flash config pointer, used when power down flash */
+    HBN_LDO_LEVEL_Type ldoLevel;                      /*!< LDO level */
+    void (*preCbFun)(void);                           /*!< Pre callback function */
+    void (*postCbFun)(void);                          /*!< Post callback function */
+} PDS_APP_CFG_Type;
+
+/**
+ *  @brief PDS LDO voltage type definition
+ */
+typedef enum {
+    PDS_LDO_VOLTAGE_0P60V, /*!< PDS LDO voltage 0.60V */
+    PDS_LDO_VOLTAGE_0P65V, /*!< PDS LDO voltage 0.65V */
+    PDS_LDO_VOLTAGE_0P70V, /*!< PDS LDO voltage 0.70V */
+    PDS_LDO_VOLTAGE_0P75V, /*!< PDS LDO voltage 0.75V */
+    PDS_LDO_VOLTAGE_0P80V, /*!< PDS LDO voltage 0.80V */
+    PDS_LDO_VOLTAGE_0P85V, /*!< PDS LDO voltage 0.85V */
+    PDS_LDO_VOLTAGE_0P90V, /*!< PDS LDO voltage 0.9V */
+    PDS_LDO_VOLTAGE_0P95V, /*!< PDS LDO voltage 0.95V */
+    PDS_LDO_VOLTAGE_1P00V, /*!< PDS LDO voltage 1.0V */
+    PDS_LDO_VOLTAGE_1P05V, /*!< PDS LDO voltage 1.05V */
+    PDS_LDO_VOLTAGE_1P10V, /*!< PDS LDO voltage 1.1V */
+    PDS_LDO_VOLTAGE_1P15V, /*!< PDS LDO voltage 1.15V */
+    PDS_LDO_VOLTAGE_1P20V, /*!< PDS LDO voltage 1.2V */
+    PDS_LDO_VOLTAGE_1P25V, /*!< PDS LDO voltage 1.25V */
+    PDS_LDO_VOLTAGE_1P30V, /*!< PDS LDO voltage 1.3V */
+    PDS_LDO_VOLTAGE_1P35V, /*!< PDS LDO voltage 1.35V */
+} PDS_LDO_VOLTAGE_Type;
+
+/**
+ *  @brief PDS auto power down configuration type definition
+ */
+typedef struct
+{
+    BL_Fun_Type mbgPower;      /*!< PDS auto [31] MBG power */
+    BL_Fun_Type ldo18rfPower;  /*!< PDS auto [30] LDO18RF power */
+    BL_Fun_Type sfregPower;    /*!< PDS auto [29] SF_REG power */
+    BL_Fun_Type pllPower;      /*!< PDS auto [28] PLL power */
+    BL_Fun_Type cpu0Power;     /*!< PDS auto [19] NP power */
+    BL_Fun_Type rc32mPower;    /*!< PDS auto [17] RC32M power */
+    BL_Fun_Type xtalPower;     /*!< PDS auto [14] XTAL power */
+    BL_Fun_Type allPower;      /*!< PDS auto [13] all power */
+    BL_Fun_Type isoPower;      /*!< PDS auto [11] ISO power */
+    BL_Fun_Type bzPower;       /*!< PDS auto [10] BZ power */
+    BL_Fun_Type sramDisStanby; /*!< PDS auto [9] SRAM memory stanby disable */
+    BL_Fun_Type cgPower;       /*!< PDS auto [8] CG power */
+    BL_Fun_Type cpu1Power;     /*!< PDS auto [7] AP power */
+    BL_Fun_Type usbPower;      /*!< PDS auto [3] USB power */
+} PDS_AUTO_POWER_DOWN_CFG_Type;
+
+/**
+ *  @brief PDS auto configuration type definition
+ */
+typedef struct
+{
+    PDS_LDO_VOLTAGE_Type vddcoreVol; /*!< PDS auto [27:24] VDDCORE voltage, reference 0x4001F80C[27:24], recommended 0xA */
+    BL_Fun_Type vddcoreVolEn;        /*!< PDS auto [18] VDDCORE voltage enable bit */
+    BL_Fun_Type cpu0NotNeedWFI;      /*!< PDS auto [21] NP not need WFI to get in PDS mode */
+    BL_Fun_Type cpu1NotNeedWFI;      /*!< PDS auto [20] AP not need WFI to get in PDS mode */
+    BL_Fun_Type busReset;            /*!< PDS auto [16] bus reset bit, reset after wake up from PDS mode */
+    BL_Fun_Type disIrqWakeUp;        /*!< PDS auto [15] disable IRQ request to wake up from PDS mode, except PDS counter IRQ */
+    BL_Fun_Type powerOffXtalForever; /*!< PDS auto [2] power off xtal after get in PDS mode, and never power on xtal after wake up */
+    BL_Fun_Type sleepForever;        /*!< PDS auto [1] sleep forever after get in PDS mode, need reset system to restart */
+} PDS_AUTO_NORMAL_CFG_Type;
+
+/**
+ *  @brief PDS force type definition
+ */
+typedef enum {
+    PDS_FORCE_NP,  /*!< PDS force NP */
+    PDS_FORCE_RSV, /*!< rsv */
+    PDS_FORCE_BZ,  /*!< PDS force BZ */
+    PDS_FORCE_USB, /*!< PDS force USB */
+} PDS_FORCE_Type;
+
+/**
+ *  @brief PDS force type definition
+ */
+typedef enum {
+    AUDIO_PLL_12288000_HZ, /*!< PDS AUDIO PLL SET AS 12.288MHZ */
+    AUDIO_PLL_11289600_HZ, /*!< PDS AUDIO PLL SET AS 11.2896HZ */
+    AUDIO_PLL_5644800_HZ,  /*!< PDS AUDIO PLL SET AS 2.822400HZ */
+    AUDIO_PLL_24576000_HZ, /*!< PDS AUDIO PLL SET AS 24.576000MHZ */
+    AUDIO_PLL_24000000_HZ, /*!< PDS AUDIO PLL SET AS 24.000000MHZ */
+} PDS_AUDIO_PLL_Type;
+
+/*@} end of group PDS_Public_Types */
+
+/** @defgroup  PDS_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  PDS_LDO_LEVEL_TYPE
+ *  @{
+ */
+#define IS_PDS_LDO_LEVEL_TYPE(type) (((type) == PDS_LDO_LEVEL_0P60V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P65V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P70V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P75V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P80V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P85V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P90V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P95V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P00V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P05V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P10V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P15V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P20V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P25V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P30V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P35V))
+
+/** @defgroup  PDS_PAD_PIN_TYPE
+ *  @{
+ */
+#define IS_PDS_PAD_PIN_TYPE(type) (((type) == PDS_PAD_PIN_GPIO_17) || \
+                                   ((type) == PDS_PAD_PIN_GPIO_18) || \
+                                   ((type) == PDS_PAD_PIN_GPIO_19) || \
+                                   ((type) == PDS_PAD_PIN_GPIO_20) || \
+                                   ((type) == PDS_PAD_PIN_GPIO_21) || \
+                                   ((type) == PDS_PAD_PIN_GPIO_22) || \
+                                   ((type) == PDS_PAD_PIN_GPIO_23) || \
+                                   ((type) == PDS_PAD_PIN_GPIO_24) || \
+                                   ((type) == PDS_PAD_PIN_GPIO_25) || \
+                                   ((type) == PDS_PAD_PIN_GPIO_26) || \
+                                   ((type) == PDS_PAD_PIN_GPIO_27) || \
+                                   ((type) == PDS_PAD_PIN_GPIO_28))
+
+/** @defgroup  PDS_PAD_CFG_TYPE
+ *  @{
+ */
+#define IS_PDS_PAD_CFG_TYPE(type) (((type) == PDS_PAD_CFG_PULL_NONE) || \
+                                   ((type) == PDS_PAD_CFG_PULL_DOWN) || \
+                                   ((type) == PDS_PAD_CFG_PULL_UP) ||   \
+                                   ((type) == PDS_PAD_CFG_ACTIVE_IE))
+
+/** @defgroup  PDS_INT_TYPE
+ *  @{
+ */
+#define IS_PDS_INT_TYPE(type) (((type) == PDS_INT_WAKEUP) ||        \
+                               ((type) == PDS_INT_RF_DONE) ||       \
+                               ((type) == PDS_INT_PLL_DONE) ||      \
+                               ((type) == PDS_INT_PDS_SLEEP_CNT) || \
+                               ((type) == PDS_INT_HBN_IRQ_OUT0) ||  \
+                               ((type) == PDS_INT_HBN_IRQ_OUT1) ||  \
+                               ((type) == PDS_INT_GPIO_IRQ) ||      \
+                               ((type) == PDS_INT_IRRX) ||          \
+                               ((type) == PDS_INT_BLE_SLP_IRQ) ||   \
+                               ((type) == PDS_INT_USB_WKUP) ||      \
+                               ((type) == PDS_INT_KYS_QDEC) ||      \
+                               ((type) == PDS_INT_MAX))
+
+/** @defgroup  PDS_VDDCORE_GPIO_SRC_TYPE
+ *  @{
+ */
+#define IS_PDS_VDDCORE_GPIO_SRC_TYPE(type) (((type) == PDS_VDDCORE_GPIO_SRC_GPIO_0) || \
+                                            ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_1) || \
+                                            ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_2) || \
+                                            ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_3) || \
+                                            ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_4) || \
+                                            ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_5) || \
+                                            ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_6) || \
+                                            ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_7))
+
+/** @defgroup  PDS_RST_EVENT_TYPE
+ *  @{
+ */
+#define IS_PDS_RST_EVENT_TYPE(type) (((type) == PDS_RST_EVENT_BUS_RST) ||        \
+                                     ((type) == PDS_RST_EVENT_HBN_PWR_ON_RST) || \
+                                     ((type) == PDS_RST_EVENT_PDS_RST) ||        \
+                                     ((type) == PDS_RST_EVENT_MAX))
+
+/** @defgroup  PDS_PLL_STS_TYPE
+ *  @{
+ */
+#define IS_PDS_PLL_STS_TYPE(type) (((type) == PDS_PLL_STS_OFF) ||   \
+                                   ((type) == PDS_PLL_STS_SFREG) || \
+                                   ((type) == PDS_PLL_STS_PU) ||    \
+                                   ((type) == PDS_PLL_STS_RDY))
+
+/** @defgroup  PDS_RF_STS_TYPE
+ *  @{
+ */
+#define IS_PDS_RF_STS_TYPE(type) (((type) == PDS_RF_STS_OFF) ||        \
+                                  ((type) == PDS_RF_STS_PU_MBG) ||     \
+                                  ((type) == PDS_RF_STS_PU_LDO15RF) || \
+                                  ((type) == PDS_RF_STS_PU_SFREG) ||   \
+                                  ((type) == PDS_RF_STS_BZ_EN_AON))
+
+/** @defgroup  PDS_STS_TYPE
+ *  @{
+ */
+#define IS_PDS_STS_TYPE(type) (((type) == PDS_STS_IDLE) ||           \
+                               ((type) == PDS_STS_ECG) ||            \
+                               ((type) == PDS_STS_ERST) ||           \
+                               ((type) == PDS_STS_EISO) ||           \
+                               ((type) == PDS_STS_POFF) ||           \
+                               ((type) == PDS_STS_PRE_BGON) ||       \
+                               ((type) == PDS_STS_PRE_BGON1) ||      \
+                               ((type) == PDS_STS_BGON) ||           \
+                               ((type) == PDS_STS_CLK_SW_32M) ||     \
+                               ((type) == PDS_STS_PON_DCDC) ||       \
+                               ((type) == PDS_STS_PON_LDO11_MISC) || \
+                               ((type) == PDS_STS_PON) ||            \
+                               ((type) == PDS_STS_DISO) ||           \
+                               ((type) == PDS_STS_DCG) ||            \
+                               ((type) == PDS_STS_DRST) ||           \
+                               ((type) == PDS_STS_WAIT_EFUSE))
+
+/** @defgroup  PDS_PLL_XTAL_TYPE
+ *  @{
+ */
+#define IS_PDS_PLL_XTAL_TYPE(type) (((type) == PDS_PLL_XTAL_NONE) || \
+                                    ((type) == PDS_PLL_XTAL_32M) ||  \
+                                    ((type) == PDS_PLL_XTAL_RC32M))
+
+/** @defgroup  PDS_PLL_CLK_TYPE
+ *  @{
+ */
+#define IS_PDS_PLL_CLK_TYPE(type) (((type) == PDS_PLL_CLK_480M) || \
+                                   ((type) == PDS_PLL_CLK_240M) || \
+                                   ((type) == PDS_PLL_CLK_192M) || \
+                                   ((type) == PDS_PLL_CLK_160M) || \
+                                   ((type) == PDS_PLL_CLK_120M) || \
+                                   ((type) == PDS_PLL_CLK_96M) ||  \
+                                   ((type) == PDS_PLL_CLK_80M) ||  \
+                                   ((type) == PDS_PLL_CLK_48M) ||  \
+                                   ((type) == PDS_PLL_CLK_32M))
+
+/** @defgroup  PDS_AON_GPIO_INT_TRIGGER_TYPE
+ *  @{
+ */
+#define IS_PDS_AON_GPIO_INT_TRIGGER_TYPE(type) (((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) ||  \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) ||   \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) ||     \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) ||    \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) || \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) ||  \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) ||    \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL))
+
+/** @defgroup  PDS_LDO_VOLTAGE_TYPE
+ *  @{
+ */
+#define IS_PDS_LDO_VOLTAGE_TYPE(type) (((type) == PDS_LDO_VOLTAGE_0P60V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_0P65V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_0P70V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_0P75V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_0P80V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_0P85V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_0P90V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_0P95V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_1P00V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_1P05V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_1P10V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_1P15V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_1P20V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_1P25V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_1P30V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_1P35V))
+
+/** @defgroup  PDS_FORCE_TYPE
+ *  @{
+ */
+#define IS_PDS_FORCE_TYPE(type) (((type) == PDS_FORCE_NP) ||  \
+                                 ((type) == PDS_FORCE_RSV) || \
+                                 ((type) == PDS_FORCE_BZ) ||  \
+                                 ((type) == PDS_FORCE_USB))
+
+/** @defgroup  PDS_AUDIO_PLL_TYPE
+ *  @{
+ */
+#define IS_PDS_AUDIO_PLL_TYPE(type) (((type) == AUDIO_PLL_12288000_HZ) || \
+                                     ((type) == AUDIO_PLL_11289600_HZ) || \
+                                     ((type) == AUDIO_PLL_5644800_HZ))
+
+/*@} end of group PDS_Public_Constants */
+
+/** @defgroup  PDS_Public_Macros
+ *  @{
+ */
+#define PDS_LDO_MIN_PU_CNT        (25) /* LDO need 25 cycles to power up */
+#define PDS_WARMUP_CNT            (38) /* LDO hw warmup compensation latency cycles */
+#define PDS_WARMUP_LATENCY_CNT    (38) /* LDO hw warmup compensation latency cycles */
+#define PDS_FORCE_PWR_OFF_OFFSET  (0)
+#define PDS_FORCE_ISO_EN_OFFSET   (4)
+#define PDS_FORCE_PDS_RST_OFFSET  (8)
+#define PDS_FORCE_MEM_STBY_OFFSET (12)
+#define PDS_FORCE_GATE_CLK_OFFSET (16)
+#define PDS_INT_MASK_BIT_OFFSET   (8)
+#define PDS_AON_WAKEUP_GPIO_NONE  (0x00)
+#define PDS_AON_WAKEUP_GPIO_9     (0x01)
+#define PDS_AON_WAKEUP_GPIO_10    (0x02)
+#define PDS_AON_WAKEUP_GPIO_11    (0x04)
+#define PDS_AON_WAKEUP_GPIO_12    (0x08)
+#define PDS_AON_WAKEUP_GPIO_13    (0x10)
+#define PDS_AON_WAKEUP_GPIO_ALL   (0x1E)
+
+/*@} end of group PDS_Public_Macros */
+
+/** @defgroup  PDS_Public_Functions
+ *  @{
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+void PDS_WAKEUP_IRQHandler(void);
+#endif
+/*----------*/
+BL_Err_Type PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg);
+BL_Err_Type PDS_Set_Pad_Config(PDS_PAD_PIN_Type pin, PDS_PAD_CFG_Type cfg);
+/*----------*/
+BL_Err_Type PDS_App_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt);
+BL_Err_Type PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3);
+BL_Err_Type PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, uint32_t pdsSleepCnt);
+/*----------*/
+BL_Err_Type PDS_IntEn(PDS_INT_Type intType, BL_Fun_Type enable);
+BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask);
+BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType);
+BL_Err_Type PDS_IntClear(void);
+PDS_PLL_STS_Type PDS_Get_PdsPllStstus(void);
+PDS_RF_STS_Type PDS_Get_PdsRfStstus(void);
+PDS_STS_Type PDS_Get_PdsStstus(void);
+/*----------*/
+BL_Err_Type PDS_Clear_Reset_Event(void);
+BL_Sts_Type PDS_Get_Reset_Event(PDS_RST_EVENT_Type event);
+/*----------*/
+BL_Err_Type PDS_Set_Vddcore_GPIO_IntCfg(PDS_VDDCORE_GPIO_SRC_Type src,
+                                        PDS_AON_GPIO_INT_Trigger_Type mode);
+BL_Err_Type PDS_Set_Vddcore_GPIO_IntMask(BL_Mask_Type intMask);
+BL_Sts_Type PDS_Get_Vddcore_GPIO_IntStatus(void);
+BL_Err_Type PDS_Set_Vddcore_GPIO_IntClear(void);
+/*----------*/
+BL_Err_Type PDS_WAKEUP_IRQHandler_Install(void);
+BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType, intCallback_Type *cbFun);
+/*----------*/
+BL_Err_Type PDS_Trim_RC32M(void);
+BL_Err_Type PDS_Select_RC32M_As_PLL_Ref(void);
+BL_Err_Type PDS_Select_XTAL_As_PLL_Ref(void);
+BL_Err_Type PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType);
+BL_Err_Type PDS_Enable_PLL_All_Clks(void);
+BL_Err_Type PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk);
+BL_Err_Type PDS_Disable_PLL_All_Clks(void);
+BL_Err_Type PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk);
+BL_Err_Type PDS_Power_Off_PLL(void);
+BL_Err_Type PDS_Set_Audio_PLL_Freq(PDS_AUDIO_PLL_Type audioPLLFreq);
+/*----------*/
+void PDS_Reset(void);
+void PDS_Enable(PDS_CFG_Type *cfg, uint32_t pdsSleepCnt);
+void PDS_Auto_Time_Config(uint32_t sleepDuration);
+void PDS_Auto_Enable(PDS_AUTO_POWER_DOWN_CFG_Type *powerCfg, PDS_AUTO_NORMAL_CFG_Type *normalCfg, BL_Fun_Type enable);
+void PDS_Manual_Force_Turn_Off(PDS_FORCE_Type domain);
+void PDS_Manual_Force_Turn_On(PDS_FORCE_Type domain);
+/*----------*/
+BL_Err_Type PDS_Set_Clkpll_Top_Ctrl(uint8_t vg11Sel);
+/*----------*/
+
+/*@} end of group PDS_Public_Functions */
+
+/*@} end of group PDS */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_PDS_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_psram.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_psram.h
new file mode 100644
index 00000000..e64808eb
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_psram.h
@@ -0,0 +1,175 @@
+/**
+  ******************************************************************************
+  * @file    bl702_psram.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_PSRAM_H__
+#define __BL702_PSRAM_H__
+
+#include "sf_ctrl_reg.h"
+#include "bl702_common.h"
+#include "bl702_sf_ctrl.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  PSRAM
+ *  @{
+ */
+
+/** @defgroup  PSRAM_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief Psram drive strength type definition
+ */
+typedef enum {
+    PSRAM_DRIVE_STRENGTH_50_OHMS,  /*!< Drive strength 50 ohms(default) */
+    PSRAM_DRIVE_STRENGTH_100_OHMS, /*!< Drive strength 100 ohms */
+    PSRAM_DRIVE_STRENGTH_200_OHMS, /*!< Drive strength 200 ohms */
+} PSRAM_Drive_Strength;
+
+/**
+ *  @brief Psram burst length size type definition
+ */
+typedef enum {
+    PSRAM_BURST_LENGTH_16_BYTES,  /*!< Burst Length 16 bytes */
+    PSRAM_BURST_LENGTH_32_BYTES,  /*!< Burst Length 32 bytes */
+    PSRAM_BURST_LENGTH_64_BYTES,  /*!< Burst Length 64 bytes */
+    PSRAM_BURST_LENGTH_512_BYTES, /*!< Burst Length 512 bytes(default) */
+} PSRAM_Burst_Length;
+
+/**
+ *  @brief Psram ctrl mode type definition
+ */
+typedef enum {
+    PSRAM_SPI_CTRL_MODE, /*!< Psram SPI ctrl mode */
+    PSRAM_QPI_CTRL_MODE, /*!< Psram QPI ctrl mode */
+} PSRAM_Ctrl_Mode;
+
+/**
+ *  @brief Psram ctrl configuration structure type definition
+ */
+typedef struct
+{
+    uint8_t readIdCmd;                  /*!< Read ID command */
+    uint8_t readIdDmyClk;               /*!< Read ID command dummy clock */
+    uint8_t burstToggleCmd;             /*!< Burst toggle length command */
+    uint8_t resetEnableCmd;             /*!< Psram reset enable command */
+    uint8_t resetCmd;                   /*!< Psram reset command */
+    uint8_t enterQuadModeCmd;           /*!< Psram enter quad mode command */
+    uint8_t exitQuadModeCmd;            /*!< Psram exit quad mode command */
+    uint8_t readRegCmd;                 /*!< Read register command */
+    uint8_t readRegDmyClk;              /*!< Read register command dummy clock */
+    uint8_t writeRegCmd;                /*!< Write register command */
+    uint8_t readCmd;                    /*!< Psram read command */
+    uint8_t readDmyClk;                 /*!< Psram read command dummy clock */
+    uint8_t fReadCmd;                   /*!< Psram fast read command */
+    uint8_t fReadDmyClk;                /*!< Psram fast read command dummy clock */
+    uint8_t fReadQuadCmd;               /*!< Psram fast read quad command */
+    uint8_t fReadQuadDmyClk;            /*!< Psram fast read quad command dummy clock */
+    uint8_t writeCmd;                   /*!< Psram write command */
+    uint8_t quadWriteCmd;               /*!< Psram quad write command */
+    uint16_t pageSize;                  /*!< Psram page size */
+    PSRAM_Ctrl_Mode ctrlMode;           /*!< Psram ctrl mode */
+    PSRAM_Drive_Strength driveStrength; /*!< Psram drive strength */
+    PSRAM_Burst_Length burstLength;     /*!< Psram burst length size */
+} SPI_Psram_Cfg_Type;
+
+/*@} end of group PSRAM_Public_Types */
+
+/** @defgroup  PSRAM_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  PSRAM_DRIVE_STRENGTH
+ *  @{
+ */
+#define IS_PSRAM_DRIVE_STRENGTH(type) (((type) == PSRAM_DRIVE_STRENGTH_50_OHMS) ||  \
+                                       ((type) == PSRAM_DRIVE_STRENGTH_100_OHMS) || \
+                                       ((type) == PSRAM_DRIVE_STRENGTH_200_OHMS))
+
+/** @defgroup  PSRAM_BURST_LENGTH
+ *  @{
+ */
+#define IS_PSRAM_BURST_LENGTH(type) (((type) == PSRAM_BURST_LENGTH_16_BYTES) || \
+                                     ((type) == PSRAM_BURST_LENGTH_32_BYTES) || \
+                                     ((type) == PSRAM_BURST_LENGTH_64_BYTES) || \
+                                     ((type) == PSRAM_BURST_LENGTH_512_BYTES))
+
+/** @defgroup  PSRAM_CTRL_MODE
+ *  @{
+ */
+#define IS_PSRAM_CTRL_MODE(type) (((type) == PSRAM_SPI_CTRL_MODE) || \
+                                  ((type) == PSRAM_QPI_CTRL_MODE))
+
+/*@} end of group PSRAM_Public_Constants */
+
+/** @defgroup  PSRAM_Public_Macros
+ *  @{
+ */
+
+/*@} end of group PSRAM_Public_Macros */
+
+/** @defgroup  PSRAM_Public_Functions
+ *  @{
+ */
+
+/**
+ *  @brief PSRAM Functions
+ */
+void Psram_Init(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Psram_Cfg *sfCtrlPsramCfg);
+void Psram_ReadReg(SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue);
+void Psram_WriteReg(SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue);
+BL_Err_Type Psram_SetDriveStrength(SPI_Psram_Cfg_Type *psramCfg);
+BL_Err_Type Psram_SetBurstWrap(SPI_Psram_Cfg_Type *psramCfg);
+void Psram_ReadId(SPI_Psram_Cfg_Type *psramCfg, uint8_t *data);
+BL_Err_Type Psram_EnterQuadMode(SPI_Psram_Cfg_Type *psramCfg);
+BL_Err_Type Psram_ExitQuadMode(SPI_Psram_Cfg_Type *psramCfg);
+BL_Err_Type Psram_ToggleBurstLength(SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode);
+BL_Err_Type Psram_SoftwareReset(SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode);
+BL_Err_Type Psram_Set_IDbus_Cfg(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint32_t len);
+BL_Err_Type Psram_Cache_Write_Set(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, BL_Fun_Type wtEn,
+                                  BL_Fun_Type wbEn, BL_Fun_Type waEn);
+BL_Err_Type Psram_Write(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len);
+BL_Err_Type Psram_Read(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len);
+
+/*@} end of group PSRAM_Public_Functions */
+
+/*@} end of group PSRAM */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_PSRAM_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_pwm.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_pwm.h
new file mode 100644
index 00000000..a158885f
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_pwm.h
@@ -0,0 +1,197 @@
+/**
+  ******************************************************************************
+  * @file    bl702_pwm.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_PWM_H__
+#define __BL702_PWM_H__
+
+#include "pwm_reg.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  PWM
+ *  @{
+ */
+
+/** @defgroup  PWM_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief PWM No. type definition
+ */
+typedef enum {
+    PWM_CH0 = 0, /*!< PWM Channel 0 define */
+    PWM_CH1,     /*!< PWM Channel 1 define */
+    PWM_CH2,     /*!< PWM Channel 2 define */
+    PWM_CH3,     /*!< PWM Channel 3 define */
+    PWM_CH4,     /*!< PWM Channel 4 define */
+    PWM_CH_MAX,  /*!<  */
+} PWM_CH_ID_Type;
+
+/**
+ *  @brief PWM Clock definition
+ */
+typedef enum {
+    PWM_CLK_XCLK = 0, /*!< PWM Clock source :XTAL CLK */
+    PWM_CLK_BCLK,     /*!< PWM Clock source :Bus CLK */
+    PWM_CLK_32K,      /*!< PWM Clock source :32K CLK */
+} PWM_Clk_Type;
+
+/**
+ *  @brief PWM Stop Mode definition
+ */
+typedef enum {
+    PWM_STOP_ABRUPT = 0, /*!< PWM stop abrupt select define */
+    PWM_STOP_GRACEFUL,   /*!< PWM stop graceful select define */
+} PWM_Stop_Mode_Type;
+
+/**
+ *  @brief PWM mode type def
+ */
+typedef enum {
+    PWM_POL_NORMAL = 0, /*!< PWM normal polarity mode define */
+    PWM_POL_INVERT,     /*!< PWM invert polarity mode define */
+} PWM_Polarity_Type;
+
+/**
+ *  @brief PWM interrupt type def
+ */
+typedef enum {
+    PWM_INT_PULSE_CNT = 0, /*!< PWM Pulse count interrupt define */
+    PWM_INT_ALL,           /*!<  */
+} PWM_INT_Type;
+
+/**
+ *  @brief PWM configuration structure type definition
+ */
+typedef struct
+{
+    PWM_CH_ID_Type ch;           /*!< PWM channel */
+    PWM_Clk_Type clk;            /*!< PWM Clock */
+    PWM_Stop_Mode_Type stopMode; /*!< PWM Stop Mode */
+    PWM_Polarity_Type pol;       /*!< PWM mode type */
+    uint16_t clkDiv;             /*!< PWM clkDiv num */
+    uint16_t period;             /*!< PWM period set */
+    uint16_t threshold1;         /*!< PWM threshold1 num */
+    uint16_t threshold2;         /*!< PWM threshold2 num */
+    uint16_t intPulseCnt;        /*!< PWM interrupt pulse count */
+} PWM_CH_CFG_Type;
+
+/*@} end of group PWM_Public_Types */
+
+/** @defgroup  PWM_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  PWM_CH_ID_TYPE
+ *  @{
+ */
+#define IS_PWM_CH_ID_TYPE(type) (((type) == PWM_CH0) || \
+                                 ((type) == PWM_CH1) || \
+                                 ((type) == PWM_CH2) || \
+                                 ((type) == PWM_CH3) || \
+                                 ((type) == PWM_CH4) || \
+                                 ((type) == PWM_CH_MAX))
+
+/** @defgroup  PWM_CLK_TYPE
+ *  @{
+ */
+#define IS_PWM_CLK_TYPE(type) (((type) == PWM_CLK_XCLK) || \
+                               ((type) == PWM_CLK_BCLK) || \
+                               ((type) == PWM_CLK_32K))
+
+/** @defgroup  PWM_STOP_MODE_TYPE
+ *  @{
+ */
+#define IS_PWM_STOP_MODE_TYPE(type) (((type) == PWM_STOP_ABRUPT) || \
+                                     ((type) == PWM_STOP_GRACEFUL))
+
+/** @defgroup  PWM_POLARITY_TYPE
+ *  @{
+ */
+#define IS_PWM_POLARITY_TYPE(type) (((type) == PWM_POL_NORMAL) || \
+                                    ((type) == PWM_POL_INVERT))
+
+/** @defgroup  PWM_INT_TYPE
+ *  @{
+ */
+#define IS_PWM_INT_TYPE(type) (((type) == PWM_INT_PULSE_CNT) || \
+                               ((type) == PWM_INT_ALL))
+
+/*@} end of group PWM_Public_Constants */
+
+/** @defgroup  PWM_Public_Macros
+ *  @{
+ */
+#define IS_PWM_CH(CH) ((CH) < PWM_CH_MAX)
+
+/*@} end of group PWM_Public_Macros */
+
+/** @defgroup  PWM_Public_Functions
+ *  @{
+ */
+
+/**
+ *  @brief PWM Functions
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+void PWM_IRQHandler(void);
+#endif
+BL_Err_Type PWM_Channel_Init(PWM_CH_CFG_Type *chCfg);
+void PWM_Channel_Update(PWM_CH_ID_Type ch, uint16_t period, uint16_t threshold1, uint16_t threshold2);
+void PWM_Channel_Set_Div(PWM_CH_ID_Type ch, uint16_t div);
+void PWM_Channel_Set_Threshold1(PWM_CH_ID_Type ch, uint16_t threshold1);
+void PWM_Channel_Set_Threshold2(PWM_CH_ID_Type ch, uint16_t threshold2);
+void PWM_Channel_Set_Period(PWM_CH_ID_Type ch, uint16_t period);
+void PWM_Channel_Get(PWM_CH_ID_Type ch, uint16_t *period, uint16_t *threshold1, uint16_t *threshold2);
+void PWM_IntMask(PWM_CH_ID_Type ch, PWM_INT_Type intType, BL_Mask_Type intMask);
+void PWM_Channel_Enable(PWM_CH_ID_Type ch);
+void PWM_Channel_Disable(PWM_CH_ID_Type ch);
+void PWM_SW_Mode(PWM_CH_ID_Type ch, BL_Fun_Type enable);
+void PWM_SW_Force_Value(PWM_CH_ID_Type ch, uint8_t value);
+void PWM_Int_Callback_Install(PWM_CH_ID_Type ch, uint32_t intType, intCallback_Type *cbFun);
+BL_Err_Type PWM_Smart_Configure(PWM_CH_ID_Type ch, uint32_t frequency, uint8_t dutyCycle);
+
+
+/*@} end of group PWM_Public_Functions */
+
+/*@} end of group PWM */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_PWM_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_qdec.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_qdec.h
new file mode 100644
index 00000000..3365dff2
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_qdec.h
@@ -0,0 +1,283 @@
+/**
+  ******************************************************************************
+  * @file    bl702_qdec.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_QDEC_H__
+#define __BL702_QDEC_H__
+
+#include "qdec_reg.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  QDEC
+ *  @{
+ */
+
+/** @defgroup  QDEC_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief QDEC port type definition
+ */
+typedef enum {
+    QDEC0_ID,    /*!< QDEC0 port define */
+    QDEC1_ID,    /*!< QDEC1 port define */
+    QDEC2_ID,    /*!< QDEC2 port define */
+    QDEC_ID_MAX, /*!< QDEC MAX ID define */
+} QDEC_ID_Type;
+
+/**
+ *  @brief QDEC sample work mode type definition
+ */
+typedef enum {
+    QDEC_SAMPLE_SINGLE_MOD,   /*!< Stop sample if rpt_rdy */
+    QDEC_SAMPLE_CONTINUE_MOD, /*!< Continue sample */
+} QDEC_SAMPLE_MODE_Type;
+
+/**
+ *  @brief QDEC sample period type definition
+ */
+typedef enum {
+    QDEC_SAMPLE_PERIOD_32US,  /*!< 32  us at clock 1MHz */
+    QDEC_SAMPLE_PERIOD_64US,  /*!< 64  us at clock 1MHz */
+    QDEC_SAMPLE_PERIOD_128US, /*!< 128 us at clock 1MHz */
+    QDEC_SAMPLE_PERIOD_256US, /*!< 256 us at clock 1MHz */
+    QDEC_SAMPLE_PERIOD_512US, /*!< 512 us at clock 1MHz */
+    QDEC_SAMPLE_PERIOD_1MS,   /*!< 1   ms at clock 1MHz */
+    QDEC_SAMPLE_PERIOD_2MS,   /*!< 2   ms at clock 1MHz */
+    QDEC_SAMPLE_PERIOD_4MS,   /*!< 4   ms at clock 1MHz */
+    QDEC_SAMPLE_PERIOD_8MS,   /*!< 8   ms at clock 1MHz */
+    QDEC_SAMPLE_PERIOD_16MS,  /*!< 16  ms at clock 1MHz */
+    QDEC_SAMPLE_PERIOD_32MS,  /*!< 32  ms at clock 1MHz */
+    QDEC_SAMPLE_PERIOD_65MS,  /*!< 65  ms at clock 1MHz */
+    QDEC_SAMPLE_PERIOD_131MS, /*!< 131 ms at clock 1MHz */
+} QDEC_SAMPLE_PERIOD_Type;
+
+/**
+ *  @brief QDEC report work mode type definition
+ */
+typedef enum {
+    QDEC_REPORT_SAMPLE_CHANGE_MOD, /*!< Count time only if sample change */
+    QDEC_REPORT_TIME_MOD,          /*!< Continue time */
+} QDEC_REPORT_MODE_Type;
+
+/**
+ *  @brief QDEC sample config structure type definition
+ */
+typedef struct
+{
+    QDEC_SAMPLE_MODE_Type sampleMod;      /*!< Sample work mode */
+    QDEC_SAMPLE_PERIOD_Type samplePeriod; /*!< Sample period time */
+} QDEC_SAMPLE_Type;
+
+/**
+ *  @brief QDEC report config structure type definition
+ */
+typedef struct
+{
+    QDEC_REPORT_MODE_Type reportMod; /*!< Report work mode */
+    uint16_t reportPeriod;           /*!< RPT_US report period in [us/report] = SP * RP */
+} QDEC_REPORT_Type;
+
+/**
+ *  @brief QDEC acc work mode type definition
+ */
+typedef enum {
+    QDEC_ACC_STOP_SAMPLE_IF_OVERFLOW, /*!< Stop accumulate if overflow */
+    QDEC_ACC_CONTINUE_ACCUMULATE,     /*!< Continue accumulate */
+} QDEC_ACC_MODE_Type;
+
+/**
+ *  @brief QDEC led config structure type definition
+ */
+typedef struct
+{
+    BL_Fun_Type ledEn;   /*!< LED enable */
+    BL_Fun_Type ledSwap; /*!< LED on/off polarity swap */
+    uint16_t ledPeriod;  /*!< Period in us the LED is switched on prior to sampling */
+} QDEC_LED_Type;
+
+/**
+ *  @brief QDEC deglitch config structure type definition
+ */
+typedef struct
+{
+    BL_Fun_Type deglitchEn;   /*!< deglitch enable */
+    uint8_t deglitchStrength; /*!< deglitch strength */
+} QDEC_DEGLITCH_Type;
+
+/**
+ *  @brief QDEC config structure type definition
+ */
+typedef struct
+{
+    QDEC_SAMPLE_Type sampleCfg;     /*!< QDEC sample config structure */
+    QDEC_REPORT_Type reportCfg;     /*!< QDEC report config structure */
+    QDEC_ACC_MODE_Type accMod;      /*!< QDEC acc mode config */
+    QDEC_LED_Type ledCfg;           /*!< QDEC led config structure */
+    QDEC_DEGLITCH_Type deglitchCfg; /*!< QDEC deglitch config structure */
+} QDEC_CFG_Type;
+
+/**
+ *  @brief QDEC direction type definition
+ */
+typedef enum {
+    QDEC_DIRECTION_NO_CHANGE,         /*!< Direction of last change no change */
+    QDEC_DIRECTION_CLOCKWISE,         /*!< Direction of last change clockwise */
+    QDEC_DIRECTION_COUNTER_CLOCKWISE, /*!< Direction of last change counter-clockwise */
+    QDEC_DIRECTION_ERROR,             /*!< Direction of last change error */
+} QDEC_DIRECTION_Type;
+
+/**
+ *  @brief QDEC interrupt type definition
+ */
+typedef enum {
+    QDEC_INT_REPORT,   /*!< report interrupt */
+    QDEC_INT_SAMPLE,   /*!< sample interrupt */
+    QDEC_INT_ERROR,    /*!< error interrupt */
+    QDEC_INT_OVERFLOW, /*!< ACC1 and ACC2 overflow interrupt */
+    QDEC_INT_ALL,      /*!< interrupt max num */
+} QDEC_INT_Type;
+
+/*@} end of group QDEC_Public_Types */
+
+/** @defgroup  QDEC_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  QDEC_ID_TYPE
+ *  @{
+ */
+#define IS_QDEC_ID_TYPE(type) (((type) == QDEC0_ID) || \
+                               ((type) == QDEC1_ID) || \
+                               ((type) == QDEC2_ID) || \
+                               ((type) == QDEC_ID_MAX))
+
+/** @defgroup  QDEC_SAMPLE_MODE_TYPE
+ *  @{
+ */
+#define IS_QDEC_SAMPLE_MODE_TYPE(type) (((type) == QDEC_SAMPLE_SINGLE_MOD) || \
+                                        ((type) == QDEC_SAMPLE_CONTINUE_MOD))
+
+/** @defgroup  QDEC_SAMPLE_PERIOD_TYPE
+ *  @{
+ */
+#define IS_QDEC_SAMPLE_PERIOD_TYPE(type) (((type) == QDEC_SAMPLE_PERIOD_32US) ||  \
+                                          ((type) == QDEC_SAMPLE_PERIOD_64US) ||  \
+                                          ((type) == QDEC_SAMPLE_PERIOD_128US) || \
+                                          ((type) == QDEC_SAMPLE_PERIOD_256US) || \
+                                          ((type) == QDEC_SAMPLE_PERIOD_512US) || \
+                                          ((type) == QDEC_SAMPLE_PERIOD_1MS) ||   \
+                                          ((type) == QDEC_SAMPLE_PERIOD_2MS) ||   \
+                                          ((type) == QDEC_SAMPLE_PERIOD_4MS) ||   \
+                                          ((type) == QDEC_SAMPLE_PERIOD_8MS) ||   \
+                                          ((type) == QDEC_SAMPLE_PERIOD_16MS) ||  \
+                                          ((type) == QDEC_SAMPLE_PERIOD_32MS) ||  \
+                                          ((type) == QDEC_SAMPLE_PERIOD_65MS) ||  \
+                                          ((type) == QDEC_SAMPLE_PERIOD_131MS))
+
+/** @defgroup  QDEC_REPORT_MODE_TYPE
+ *  @{
+ */
+#define IS_QDEC_REPORT_MODE_TYPE(type) (((type) == QDEC_REPORT_SAMPLE_CHANGE_MOD) || \
+                                        ((type) == QDEC_REPORT_TIME_MOD))
+
+/** @defgroup  QDEC_ACC_MODE_TYPE
+ *  @{
+ */
+#define IS_QDEC_ACC_MODE_TYPE(type) (((type) == QDEC_ACC_STOP_SAMPLE_IF_OVERFLOW) || \
+                                     ((type) == QDEC_ACC_CONTINUE_ACCUMULATE))
+
+/** @defgroup  QDEC_DIRECTION_TYPE
+ *  @{
+ */
+#define IS_QDEC_DIRECTION_TYPE(type) (((type) == QDEC_DIRECTION_NO_CHANGE) ||         \
+                                      ((type) == QDEC_DIRECTION_CLOCKWISE) ||         \
+                                      ((type) == QDEC_DIRECTION_COUNTER_CLOCKWISE) || \
+                                      ((type) == QDEC_DIRECTION_ERROR))
+
+/** @defgroup  QDEC_INT_TYPE
+ *  @{
+ */
+#define IS_QDEC_INT_TYPE(type) (((type) == QDEC_INT_REPORT) ||   \
+                                ((type) == QDEC_INT_SAMPLE) ||   \
+                                ((type) == QDEC_INT_ERROR) ||    \
+                                ((type) == QDEC_INT_OVERFLOW) || \
+                                ((type) == QDEC_INT_ALL))
+
+/*@} end of group QDEC_Public_Constants */
+
+/** @defgroup  QDEC_Public_Macros
+ *  @{
+ */
+
+/*@} end of group QDEC_Public_Macros */
+
+/** @defgroup  QDEC_Public_Functions
+ *  @{
+ */
+
+/**
+ *  @brief QDEC Functions
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+void QDEC0_IRQHandler(void);
+void QDEC1_IRQHandler(void);
+void QDEC2_IRQHandler(void);
+#endif
+void QDEC_Init(QDEC_ID_Type qdecId, QDEC_CFG_Type *qdecCfg);
+void QDEC_DeInit(QDEC_ID_Type qdecId);
+void QDEC_Enable(QDEC_ID_Type qdecId);
+void QDEC_Disable(QDEC_ID_Type qdecId);
+void QDEC_SetIntMask(QDEC_ID_Type qdecId, QDEC_INT_Type intType, BL_Mask_Type intMask);
+BL_Mask_Type QDEC_GetIntMask(QDEC_ID_Type qdecId, QDEC_INT_Type intType);
+void QDEC_Int_Callback_Install(QDEC_ID_Type qdecId, QDEC_INT_Type intType, intCallback_Type *cbFun);
+BL_Sts_Type QDEC_Get_Int_Status(QDEC_ID_Type qdecId, QDEC_INT_Type intType);
+void QDEC_Clr_Int_Status(QDEC_ID_Type qdecId, QDEC_INT_Type intType);
+QDEC_DIRECTION_Type QDEC_Get_Sample_Direction(QDEC_ID_Type qdecId);
+uint8_t QDEC_Get_Err_Cnt(QDEC_ID_Type qdecId);
+uint16_t QDEC_Get_Sample_Val(QDEC_ID_Type qdecId);
+void QDEC_IntHandler(QDEC_ID_Type qdecId, QDEC_INT_Type intType);
+
+/*@} end of group QDEC_Public_Functions */
+
+/*@} end of group QDEC */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_QDEC_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_romdriver.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_romdriver.h
new file mode 100644
index 00000000..3d21f20c
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_romdriver.h
@@ -0,0 +1,632 @@
+/**
+  ******************************************************************************
+  * @file    bl702_romdriver.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_ROMDRIVER_H__
+#define __BL702_ROMDRIVER_H__
+
+#include "bl702_common.h"
+#include "bl702_aon.h"
+#include "bl702_glb.h"
+#include "bl702_hbn.h"
+#include "bl702_xip_sflash.h"
+#include "bl702_sflash.h"
+#include "bl702_sf_ctrl.h"
+#include "bl702_psram.h"
+#include "softcrc.h"
+
+#define ROMAPI_INDEX_SECT_SIZE (0x800)
+#define ROMAPI_INDEX_MAX       (ROMAPI_INDEX_SECT_SIZE / 4 - 1)
+
+typedef enum {
+    ROM_API_INDEX_REV = 0,
+
+    ROM_API_INDEX_FUNC_START = 4,
+
+    ROM_API_INDEX_AON_Power_On_MBG = ROM_API_INDEX_FUNC_START,
+    ROM_API_INDEX_AON_Power_Off_MBG,
+    ROM_API_INDEX_AON_Power_On_XTAL,
+    ROM_API_INDEX_AON_Set_Xtal_CapCode,
+    ROM_API_INDEX_AON_Power_Off_XTAL,
+
+    ROM_API_INDEX_ASM_Delay_Us,
+    ROM_API_INDEX_BL702_Delay_US,
+    ROM_API_INDEX_BL702_Delay_MS,
+    ROM_API_INDEX_BL702_MemCpy,
+    ROM_API_INDEX_BL702_MemCpy4,
+    ROM_API_INDEX_BL702_MemCpy_Fast,
+    ROM_API_INDEX_ARCH_MemCpy_Fast,
+    ROM_API_INDEX_BL702_MemSet,
+    ROM_API_INDEX_BL702_MemSet4,
+    ROM_API_INDEX_BL702_MemCmp,
+    ROM_API_INDEX_BFLB_Soft_CRC32,
+
+    ROM_API_INDEX_GLB_Get_Root_CLK_Sel,
+    ROM_API_INDEX_GLB_Set_System_CLK_Div,
+    ROM_API_INDEX_GLB_Get_BCLK_Div,
+    ROM_API_INDEX_GLB_Get_HCLK_Div,
+    ROM_API_INDEX_Update_SystemCoreClockWith_XTAL,
+    ROM_API_INDEX_GLB_Set_System_CLK,
+    ROM_API_INDEX_System_Core_Clock_Update_From_RC32M,
+    ROM_API_INDEX_GLB_Set_SF_CLK,
+    ROM_API_INDEX_GLB_Power_Off_DLL,
+    ROM_API_INDEX_GLB_Power_On_DLL,
+    ROM_API_INDEX_GLB_Enable_DLL_All_Clks,
+    ROM_API_INDEX_GLB_Enable_DLL_Clk,
+    ROM_API_INDEX_GLB_Disable_DLL_All_Clks,
+    ROM_API_INDEX_GLB_Disable_DLL_Clk,
+    ROM_API_INDEX_GLB_SW_System_Reset,
+    ROM_API_INDEX_GLB_SW_CPU_Reset,
+    ROM_API_INDEX_GLB_SW_POR_Reset,
+    ROM_API_INDEX_GLB_Select_Internal_Flash,
+    ROM_API_INDEX_GLB_Swap_Flash_Pin,
+    ROM_API_INDEX_GLB_Swap_Flash_CS_IO2_Pin,
+    ROM_API_INDEX_GLB_Swap_Flash_IO0_IO3_Pin,
+    ROM_API_INDEX_GLB_Select_Internal_PSram,
+    ROM_API_INDEX_GLB_GPIO_Init,
+    ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable,
+    ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable,
+    ROM_API_INDEX_GLB_GPIO_Set_HZ,
+    ROM_API_INDEX_GLB_Deswap_Flash_Pin,
+    ROM_API_INDEX_GLB_Select_External_Flash,
+    ROM_API_INDEX_GLB_GPIO_Get_Fun,
+
+    ROM_API_INDEX_EF_Ctrl_Busy,
+    ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0,
+    ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0,
+    ROM_API_INDEX_EF_Ctrl_Clear,
+    ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity,
+    ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim,
+    ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim,
+
+    ROM_API_INDEX_PDS_Trim_RC32M,
+    ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref,
+    ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref,
+    ROM_API_INDEX_PDS_Power_On_PLL,
+    ROM_API_INDEX_PDS_Enable_PLL_All_Clks,
+    ROM_API_INDEX_PDS_Disable_PLL_All_Clks,
+    ROM_API_INDEX_PDS_Enable_PLL_Clk,
+    ROM_API_INDEX_PDS_Disable_PLL_Clk,
+    ROM_API_INDEX_PDS_Power_Off_PLL,
+    ROM_API_INDEX_PDS_Reset,
+    ROM_API_INDEX_PDS_Enable,
+    ROM_API_INDEX_PDS_Auto_Time_Config,
+    ROM_API_INDEX_PDS_Auto_Enable,
+    ROM_API_INDEX_PDS_Manual_Force_Turn_Off,
+    ROM_API_INDEX_PDS_Manual_Force_Turn_On,
+
+    ROM_API_INDEX_HBN_Enable,
+    ROM_API_INDEX_HBN_Reset,
+    ROM_API_INDEX_HBN_GPIO_Dbg_Pull_Cfg,
+    ROM_API_INDEX_HBN_Trim_RC32K,
+    ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel,
+
+    ROM_API_INDEX_XIP_SFlash_State_Save,
+    ROM_API_INDEX_XIP_SFlash_State_Restore,
+    ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock,
+    ROM_API_INDEX_XIP_SFlash_Write_Need_Lock,
+    ROM_API_INDEX_XIP_SFlash_Read_Need_Lock,
+    ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock,
+    ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock,
+    ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock,
+    ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock,
+    ROM_API_INDEX_XIP_SFlash_Read_With_Lock,
+    ROM_API_INDEX_XIP_SFlash_Write_With_Lock,
+    ROM_API_INDEX_XIP_SFlash_Erase_With_Lock,
+
+    ROM_API_INDEX_SFlash_Init,
+    ROM_API_INDEX_SFlash_SetSPIMode,
+    ROM_API_INDEX_SFlash_Read_Reg,
+    ROM_API_INDEX_SFlash_Write_Reg,
+    ROM_API_INDEX_SFlash_Read_Reg_With_Cmd,
+    ROM_API_INDEX_SFlash_Write_Reg_With_Cmd,
+    ROM_API_INDEX_SFlash_Busy,
+    ROM_API_INDEX_SFlash_Write_Enable,
+    ROM_API_INDEX_SFlash_Qspi_Enable,
+    ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable,
+    ROM_API_INDEX_SFlash_Chip_Erase,
+    ROM_API_INDEX_SFlash_Sector_Erase,
+    ROM_API_INDEX_SFlash_Blk32_Erase,
+    ROM_API_INDEX_SFlash_Blk64_Erase,
+    ROM_API_INDEX_SFlash_Erase,
+    ROM_API_INDEX_SFlash_Program,
+    ROM_API_INDEX_SFlash_GetUniqueId,
+    ROM_API_INDEX_SFlash_GetJedecId,
+    ROM_API_INDEX_SFlash_GetDeviceId,
+    ROM_API_INDEX_SFlash_Powerdown,
+    ROM_API_INDEX_SFlash_Releae_Powerdown,
+    ROM_API_INDEX_SFlash_Restore_From_Powerdown,
+    ROM_API_INDEX_SFlash_SetBurstWrap,
+    ROM_API_INDEX_SFlash_DisableBurstWrap,
+    ROM_API_INDEX_SFlash_Software_Reset,
+    ROM_API_INDEX_SFlash_Reset_Continue_Read,
+    ROM_API_INDEX_SFlash_Set_IDbus_Cfg,
+    ROM_API_INDEX_SFlash_IDbus_Read_Enable,
+    ROM_API_INDEX_SFlash_Cache_Read_Enable,
+    ROM_API_INDEX_SFlash_Cache_Read_Disable,
+    ROM_API_INDEX_SFlash_Read,
+
+    ROM_API_INDEX_L1C_Cache_Enable_Set,
+    ROM_API_INDEX_L1C_Cache_Write_Set,
+    ROM_API_INDEX_L1C_Cache_Flush,
+    ROM_API_INDEX_L1C_Cache_Hit_Count_Get,
+    ROM_API_INDEX_L1C_Cache_Miss_Count_Get,
+    ROM_API_INDEX_L1C_Cache_Read_Disable,
+    ROM_API_INDEX_L1C_Set_Wrap,
+    ROM_API_INDEX_L1C_Set_Way_Disable,
+    ROM_API_INDEX_L1C_IROM_2T_Access_Set,
+
+    ROM_API_INDEX_SF_Ctrl_Enable,
+    ROM_API_INDEX_SF_Ctrl_Psram_Init,
+    ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay,
+    ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay,
+    ROM_API_INDEX_SF_Ctrl_Cmds_Set,
+    ROM_API_INDEX_SF_Ctrl_Set_Owner,
+    ROM_API_INDEX_SF_Ctrl_Disable,
+    ROM_API_INDEX_SF_Ctrl_Select_Pad,
+    ROM_API_INDEX_SF_Ctrl_Select_Bank,
+    ROM_API_INDEX_SF_Ctrl_AES_Enable_BE,
+    ROM_API_INDEX_SF_Ctrl_AES_Enable_LE,
+    ROM_API_INDEX_SF_Ctrl_AES_Set_Region,
+    ROM_API_INDEX_SF_Ctrl_AES_Set_Key,
+    ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE,
+    ROM_API_INDEX_SF_Ctrl_AES_Set_IV,
+    ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE,
+    ROM_API_INDEX_SF_Ctrl_AES_Enable,
+    ROM_API_INDEX_SF_Ctrl_AES_Disable,
+    ROM_API_INDEX_SF_Ctrl_Is_AES_Enable,
+    ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset,
+    ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset,
+    ROM_API_INDEX_SF_Ctrl_Select_Clock,
+    ROM_API_INDEX_SF_Ctrl_SendCmd,
+    ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set,
+    ROM_API_INDEX_SF_Ctrl_Psram_Write_Icache_Set,
+    ROM_API_INDEX_SF_Ctrl_Psram_Read_Icache_Set,
+    ROM_API_INDEX_SF_Ctrl_GetBusyState,
+    ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio,
+    ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio,
+    ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock,
+    ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio,
+    ROM_API_INDEX_SF_Cfg_Flash_Identify,
+
+    ROM_API_INDEX_Psram_Init,
+    ROM_API_INDEX_Psram_ReadReg,
+    ROM_API_INDEX_Psram_WriteReg,
+    ROM_API_INDEX_Psram_SetDriveStrength,
+    ROM_API_INDEX_Psram_SetBurstWrap,
+    ROM_API_INDEX_Psram_ReadId,
+    ROM_API_INDEX_Psram_EnterQuadMode,
+    ROM_API_INDEX_Psram_ExitQuadMode,
+    ROM_API_INDEX_Psram_ToggleBurstLength,
+    ROM_API_INDEX_Psram_SoftwareReset,
+    ROM_API_INDEX_Psram_Set_IDbus_Cfg,
+    ROM_API_INDEX_Psram_Cache_Write_Set,
+    ROM_API_INDEX_Psram_Write,
+    ROM_API_INDEX_Psram_Read,
+
+    ROM_API_INDEX_FUNC_LAST = ROM_API_INDEX_Psram_Read,
+
+    ROM_API_INDEX_FUNC_INVALID_START,
+
+    ROM_API_INDEX_FUNC_LAST_ENTRY = ROMAPI_INDEX_MAX
+} ROM_API_INDEX_e;
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  ROMDRIVER
+ *  @{
+ */
+
+/** @defgroup  ROMDRIVER_Public_Types
+ *  @{
+ */
+#define ROM_APITABLE ((uint32_t *)0x21018800)
+
+#define RomDriver_AON_Power_On_MBG \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_MBG])
+#define RomDriver_AON_Power_Off_MBG \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_MBG])
+#define RomDriver_AON_Power_On_XTAL \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_XTAL])
+#define RomDriver_AON_Set_Xtal_CapCode \
+    ((BL_Err_Type(*)(uint8_t capIn, uint8_t capOut))ROM_APITABLE[ROM_API_INDEX_AON_Set_Xtal_CapCode])
+#define RomDriver_AON_Power_Off_XTAL \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_XTAL])
+
+#define RomDriver_ASM_Delay_Us \
+    ((void (*)(uint32_t core, uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_ASM_Delay_Us])
+#define RomDriver_BL702_Delay_US \
+    ((void (*)(uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_BL702_Delay_US])
+#define RomDriver_BL702_Delay_MS \
+    ((void (*)(uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_BL702_Delay_MS])
+#define RomDriver_BL702_MemCpy \
+    ((void *(*)(void *dst, const void *src, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL702_MemCpy])
+#define RomDriver_BL702_MemCpy4 \
+    ((uint32_t * (*)(uint32_t * dst, const uint32_t *src, uint32_t n)) ROM_APITABLE[ROM_API_INDEX_BL702_MemCpy4])
+#define RomDriver_BL702_MemCpy_Fast \
+    ((void *(*)(void *pdst, const void *psrc, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL702_MemCpy_Fast])
+#define RomDriver_ARCH_MemCpy_Fast \
+    ((void *(*)(void *pdst, const void *psrc, uint32_t n))ROM_APITABLE[ROM_API_INDEX_ARCH_MemCpy_Fast])
+#define RomDriver_BL702_MemSet \
+    ((void *(*)(void *s, uint8_t c, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL702_MemSet])
+#define RomDriver_BL702_MemSet4 \
+    ((uint32_t * (*)(uint32_t * dst, const uint32_t val, uint32_t n)) ROM_APITABLE[ROM_API_INDEX_BL702_MemSet4])
+#define RomDriver_BL702_MemCmp \
+    ((int (*)(const void *s1, const void *s2, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL702_MemCmp])
+#define RomDriver_BFLB_Soft_CRC32 \
+    ((uint32_t(*)(void *dataIn, uint32_t len))ROM_APITABLE[ROM_API_INDEX_BFLB_Soft_CRC32])
+
+#define RomDriver_GLB_Get_Root_CLK_Sel \
+    ((GLB_ROOT_CLK_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_Root_CLK_Sel])
+#define RomDriver_GLB_Set_System_CLK_Div \
+    ((BL_Err_Type(*)(uint8_t hclkDiv, uint8_t bclkDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Set_System_CLK_Div])
+#define RomDriver_GLB_Get_BCLK_Div \
+    ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_BCLK_Div])
+#define RomDriver_GLB_Get_HCLK_Div \
+    ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_HCLK_Div])
+#define RomDriver_Update_SystemCoreClockWith_XTAL \
+    ((BL_Err_Type(*)(GLB_DLL_XTAL_Type xtalType))ROM_APITABLE[ROM_API_INDEX_Update_SystemCoreClockWith_XTAL])
+#define RomDriver_GLB_Set_System_CLK \
+    ((BL_Err_Type(*)(GLB_DLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq))ROM_APITABLE[ROM_API_INDEX_GLB_Set_System_CLK])
+#define RomDriver_System_Core_Clock_Update_From_RC32M \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_System_Core_Clock_Update_From_RC32M])
+#define RomDriver_GLB_Set_SF_CLK \
+    ((BL_Err_Type(*)(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SF_CLK])
+#define RomDriver_GLB_Power_Off_DLL \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Power_Off_DLL])
+#define RomDriver_GLB_Power_On_DLL \
+    ((BL_Err_Type(*)(GLB_DLL_XTAL_Type xtalType))ROM_APITABLE[ROM_API_INDEX_GLB_Power_On_DLL])
+#define RomDriver_GLB_Enable_DLL_All_Clks \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Enable_DLL_All_Clks])
+#define RomDriver_GLB_Enable_DLL_Clk \
+    ((BL_Err_Type(*)(GLB_DLL_CLK_Type dllClk))ROM_APITABLE[ROM_API_INDEX_GLB_Enable_DLL_Clk])
+#define RomDriver_GLB_Disable_DLL_All_Clks \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Disable_DLL_All_Clks])
+#define RomDriver_GLB_Disable_DLL_Clk \
+    ((BL_Err_Type(*)(GLB_DLL_CLK_Type dllClk))ROM_APITABLE[ROM_API_INDEX_GLB_Disable_DLL_Clk])
+#define RomDriver_GLB_SW_System_Reset \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_System_Reset])
+#define RomDriver_GLB_SW_CPU_Reset \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_CPU_Reset])
+#define RomDriver_GLB_SW_POR_Reset \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_POR_Reset])
+#define RomDriver_GLB_Select_Internal_Flash \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Select_Internal_Flash])
+#define RomDriver_GLB_Swap_Flash_Pin \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Swap_Flash_Pin])
+#define RomDriver_GLB_Swap_Flash_CS_IO2_Pin \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Swap_Flash_CS_IO2_Pin])
+#define RomDriver_GLB_Swap_Flash_IO0_IO3_Pin \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Swap_Flash_IO0_IO3_Pin])
+#define RomDriver_GLB_Select_Internal_PSram \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Select_Internal_PSram])
+#define RomDriver_GLB_GPIO_Init \
+    ((BL_Err_Type(*)(GLB_GPIO_Cfg_Type * cfg)) ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Init])
+#define RomDriver_GLB_GPIO_OUTPUT_Enable \
+    ((BL_Err_Type(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable])
+#define RomDriver_GLB_GPIO_OUTPUT_Disable \
+    ((BL_Err_Type(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable])
+#define RomDriver_GLB_GPIO_Set_HZ \
+    ((BL_Err_Type(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Set_HZ])
+#define RomDriver_GLB_Deswap_Flash_Pin \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Deswap_Flash_Pin])
+#define RomDriver_GLB_Select_External_Flash \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Select_External_Flash])
+#define RomDriver_GLB_GPIO_Get_Fun \
+    ((uint8_t(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Get_Fun])
+
+#define RomDriver_EF_Ctrl_Busy \
+    ((BL_Sts_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Busy])
+#define RomDriver_EF_Ctrl_Sw_AHB_Clk_0 \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0])
+#define RomDriver_EF_Ctrl_Load_Efuse_R0 \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0])
+#define RomDriver_EF_Ctrl_Clear \
+    ((void (*)(uint32_t index, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Clear])
+#define RomDriver_EF_Ctrl_Get_Trim_Parity \
+    ((uint8_t(*)(uint32_t val, uint8_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity])
+#define RomDriver_EF_Ctrl_Read_RC32K_Trim \
+    ((void (*)(Efuse_Ana_RC32K_Trim_Type * trim)) ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim])
+#define RomDriver_EF_Ctrl_Read_RC32M_Trim \
+    ((void (*)(Efuse_Ana_RC32M_Trim_Type * trim)) ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim])
+
+#define RomDriver_PDS_Trim_RC32M \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Trim_RC32M])
+#define RomDriver_PDS_Select_RC32M_As_PLL_Ref \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref])
+#define RomDriver_PDS_Select_XTAL_As_PLL_Ref \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref])
+#define RomDriver_PDS_Power_On_PLL \
+    ((BL_Err_Type(*)(PDS_PLL_XTAL_Type xtalType))ROM_APITABLE[ROM_API_INDEX_PDS_Power_On_PLL])
+#define RomDriver_PDS_Enable_PLL_All_Clks \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Enable_PLL_All_Clks])
+#define RomDriver_PDS_Disable_PLL_All_Clks \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Disable_PLL_All_Clks])
+#define RomDriver_PDS_Enable_PLL_Clk \
+    ((BL_Err_Type(*)(PDS_PLL_CLK_Type pllClk))ROM_APITABLE[ROM_API_INDEX_PDS_Enable_PLL_Clk])
+#define RomDriver_PDS_Disable_PLL_Clk \
+    ((BL_Err_Type(*)(PDS_PLL_CLK_Type pllClk))ROM_APITABLE[ROM_API_INDEX_PDS_Disable_PLL_Clk])
+#define RomDriver_PDS_Power_Off_PLL \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Power_Off_PLL])
+#define RomDriver_PDS_Reset \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Reset])
+#define RomDriver_PDS_Enable \
+    ((void (*)(PDS_CFG_Type * cfg, uint32_t pdsSleepCnt)) ROM_APITABLE[ROM_API_INDEX_PDS_Enable])
+#define RomDriver_PDS_Auto_Time_Config \
+    ((void (*)(uint32_t sleepDuration))ROM_APITABLE[ROM_API_INDEX_PDS_Auto_Time_Config])
+#define RomDriver_PDS_Auto_Enable \
+    ((void (*)(PDS_AUTO_POWER_DOWN_CFG_Type * powerCfg, PDS_AUTO_NORMAL_CFG_Type * normalCfg, BL_Fun_Type enable)) ROM_APITABLE[ROM_API_INDEX_PDS_Auto_Enable])
+#define RomDriver_PDS_Manual_Force_Turn_Off \
+    ((void (*)(PDS_FORCE_Type domain))ROM_APITABLE[ROM_API_INDEX_PDS_Manual_Force_Turn_Off])
+#define RomDriver_PDS_Manual_Force_Turn_On \
+    ((void (*)(PDS_FORCE_Type domain))ROM_APITABLE[ROM_API_INDEX_PDS_Manual_Force_Turn_On])
+
+#define RomDriver_HBN_Enable \
+    ((void (*)(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Enable])
+#define RomDriver_HBN_Reset \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Reset])
+#define RomDriver_HBN_GPIO_Dbg_Pull_Cfg \
+    ((BL_Err_Type(*)(BL_Fun_Type pupdEn, BL_Fun_Type dlyEn, uint8_t dlySec, HBN_INT_Type gpioIrq, BL_Mask_Type gpioMask))ROM_APITABLE[ROM_API_INDEX_HBN_GPIO_Dbg_Pull_Cfg])
+#define RomDriver_HBN_Trim_RC32K \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Trim_RC32K])
+#define RomDriver_HBN_Set_ROOT_CLK_Sel \
+    ((BL_Err_Type(*)(HBN_ROOT_CLK_Type rootClk))ROM_APITABLE[ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel])
+
+#define RomDriver_XIP_SFlash_State_Save \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t * offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Save])
+#define RomDriver_XIP_SFlash_State_Restore \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Restore])
+#define RomDriver_XIP_SFlash_Erase_Need_Lock \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock])
+#define RomDriver_XIP_SFlash_Write_Need_Lock \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_Need_Lock])
+#define RomDriver_XIP_SFlash_Read_Need_Lock \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Need_Lock])
+#define RomDriver_XIP_SFlash_GetJedecId_Need_Lock \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock])
+#define RomDriver_XIP_SFlash_GetDeviceId_Need_Lock \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock])
+#define RomDriver_XIP_SFlash_GetUniqueId_Need_Lock \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t * data, uint8_t idLen)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock])
+#define RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock \
+    ((BL_Err_Type(*)(uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock])
+#define RomDriver_XIP_SFlash_Read_With_Lock \
+    ((int (*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * dst, int len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_With_Lock])
+#define RomDriver_XIP_SFlash_Write_With_Lock \
+    ((int (*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * src, int len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_With_Lock])
+#define RomDriver_XIP_SFlash_Erase_With_Lock \
+    ((int (*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, int len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_With_Lock])
+
+#define RomDriver_SFlash_Init \
+    ((void (*)(const SF_Ctrl_Cfg_Type *pSfCtrlCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Init])
+#define RomDriver_SFlash_SetSPIMode \
+    ((BL_Err_Type(*)(SF_Ctrl_Mode_Type mode))ROM_APITABLE[ROM_API_INDEX_SFlash_SetSPIMode])
+#define RomDriver_SFlash_Read_Reg \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg])
+#define RomDriver_SFlash_Write_Reg \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg])
+#define RomDriver_SFlash_Read_Reg_With_Cmd \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t readRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg_With_Cmd])
+#define RomDriver_SFlash_Write_Reg_With_Cmd \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t writeRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg_With_Cmd])
+#define RomDriver_SFlash_Busy \
+    ((BL_Sts_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Busy])
+#define RomDriver_SFlash_Write_Enable \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Enable])
+#define RomDriver_SFlash_Qspi_Enable \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Enable])
+#define RomDriver_SFlash_Volatile_Reg_Write_Enable \
+    ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable])
+#define RomDriver_SFlash_Chip_Erase \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Chip_Erase])
+#define RomDriver_SFlash_Sector_Erase \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t secNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Sector_Erase])
+#define RomDriver_SFlash_Blk32_Erase \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk32_Erase])
+#define RomDriver_SFlash_Blk64_Erase \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk64_Erase])
+#define RomDriver_SFlash_Erase \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_SFlash_Erase])
+#define RomDriver_SFlash_Program \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Program])
+#define RomDriver_SFlash_GetUniqueId \
+    ((void (*)(uint8_t * data, uint8_t idLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetUniqueId])
+#define RomDriver_SFlash_GetJedecId \
+    ((void (*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetJedecId])
+#define RomDriver_SFlash_GetDeviceId \
+    ((void (*)(uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetDeviceId])
+#define RomDriver_SFlash_Powerdown \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Powerdown])
+#define RomDriver_SFlash_Releae_Powerdown \
+    ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Releae_Powerdown])
+#define RomDriver_SFlash_Restore_From_Powerdown \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint8_t flashContRead)) ROM_APITABLE[ROM_API_INDEX_SFlash_Restore_From_Powerdown])
+#define RomDriver_SFlash_SetBurstWrap \
+    ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_SetBurstWrap])
+#define RomDriver_SFlash_DisableBurstWrap \
+    ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_DisableBurstWrap])
+#define RomDriver_SFlash_Software_Reset \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Software_Reset])
+#define RomDriver_SFlash_Reset_Continue_Read \
+    ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Reset_Continue_Read])
+#define RomDriver_SFlash_Set_IDbus_Cfg \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Set_IDbus_Cfg])
+#define RomDriver_SFlash_IDbus_Read_Enable \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead)) ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Enable])
+#define RomDriver_SFlash_Cache_Read_Enable \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint8_t wayDisable)) ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Enable])
+#define RomDriver_SFlash_Cache_Read_Disable \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Disable])
+#define RomDriver_SFlash_Read \
+    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read])
+
+#define RomDriver_L1C_Cache_Enable_Set \
+    ((BL_Err_Type(*)(uint8_t wayDisable))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Enable_Set])
+#define RomDriver_L1C_Cache_Write_Set \
+    ((void (*)(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Write_Set])
+#define RomDriver_L1C_Cache_Flush \
+    ((BL_Err_Type(*)(uint8_t wayDisable))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Flush])
+#define RomDriver_L1C_Cache_Hit_Count_Get \
+    ((void (*)(uint32_t * hitCountLow, uint32_t * hitCountHigh)) ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Hit_Count_Get])
+#define RomDriver_L1C_Cache_Miss_Count_Get \
+    ((uint32_t(*)(void))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Miss_Count_Get])
+#define RomDriver_L1C_Cache_Read_Disable \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Read_Disable])
+#define RomDriver_L1C_Set_Wrap \
+    ((BL_Err_Type(*)(BL_Fun_Type wrap))ROM_APITABLE[ROM_API_INDEX_L1C_Set_Wrap])
+#define RomDriver_L1C_Set_Way_Disable \
+    ((BL_Err_Type(*)(uint8_t disableVal))ROM_APITABLE[ROM_API_INDEX_L1C_Set_Way_Disable])
+#define RomDriver_L1C_IROM_2T_Access_Set \
+    ((BL_Err_Type(*)(uint8_t enable))ROM_APITABLE[ROM_API_INDEX_L1C_IROM_2T_Access_Set])
+
+#define RomDriver_SF_Ctrl_Enable \
+    ((void (*)(const SF_Ctrl_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Enable])
+#define RomDriver_SF_Ctrl_Psram_Init \
+    ((void (*)(SF_Ctrl_Psram_Cfg * sfCtrlPsramCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Psram_Init])
+#define RomDriver_SF_Ctrl_Get_Clock_Delay \
+    ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay])
+#define RomDriver_SF_Ctrl_Set_Clock_Delay \
+    ((void (*)(uint8_t delay))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay])
+#define RomDriver_SF_Ctrl_Cmds_Set \
+    ((void (*)(SF_Ctrl_Cmds_Cfg * cmdsCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Cmds_Set])
+#define RomDriver_SF_Ctrl_Set_Owner \
+    ((void (*)(SF_Ctrl_Owner_Type owner))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Owner])
+#define RomDriver_SF_Ctrl_Disable \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Disable])
+#define RomDriver_SF_Ctrl_Select_Pad \
+    ((void (*)(SF_Ctrl_Pad_Select sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Pad])
+#define RomDriver_SF_Ctrl_Select_Bank \
+    ((void (*)(SF_Ctrl_Select sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Bank])
+#define RomDriver_SF_Ctrl_AES_Enable_BE \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable_BE])
+#define RomDriver_SF_Ctrl_AES_Enable_LE \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable_LE])
+#define RomDriver_SF_Ctrl_AES_Set_Region \
+    ((void (*)(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Region])
+#define RomDriver_SF_Ctrl_AES_Set_Key \
+    ((void (*)(uint8_t region, uint8_t * key, SF_Ctrl_AES_Key_Type keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key])
+#define RomDriver_SF_Ctrl_AES_Set_Key_BE \
+    ((void (*)(uint8_t region, uint8_t * key, SF_Ctrl_AES_Key_Type keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE])
+#define RomDriver_SF_Ctrl_AES_Set_IV \
+    ((void (*)(uint8_t region, uint8_t * iv, uint32_t addrOffset)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV])
+#define RomDriver_SF_Ctrl_AES_Set_IV_BE \
+    ((void (*)(uint8_t region, uint8_t * iv, uint32_t addrOffset)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE])
+#define RomDriver_SF_Ctrl_AES_Enable \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable])
+#define RomDriver_SF_Ctrl_AES_Disable \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Disable])
+#define RomDriver_SF_Ctrl_Is_AES_Enable \
+    ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_AES_Enable])
+#define RomDriver_SF_Ctrl_Set_Flash_Image_Offset \
+    ((void (*)(uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset])
+#define RomDriver_SF_Ctrl_Get_Flash_Image_Offset \
+    ((uint32_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset])
+#define RomDriver_SF_Ctrl_Select_Clock \
+    ((void (*)(SF_Ctrl_Sahb_Type sahbType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Clock])
+#define RomDriver_SF_Ctrl_SendCmd \
+    ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_SendCmd])
+#define RomDriver_SF_Ctrl_Flash_Read_Icache_Set \
+    ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set])
+#define RomDriver_SF_Ctrl_Psram_Write_Icache_Set \
+    ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Psram_Write_Icache_Set])
+#define RomDriver_SF_Ctrl_Psram_Read_Icache_Set \
+    ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Psram_Read_Icache_Set])
+#define RomDriver_SF_Ctrl_GetBusyState \
+    ((BL_Sts_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_GetBusyState])
+#define RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio \
+    ((void (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio])
+#define RomDriver_SF_Cfg_Init_Ext_Flash_Gpio \
+    ((void (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio])
+#define RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock \
+    ((BL_Err_Type(*)(uint32_t flashID, SPI_Flash_Cfg_Type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock])
+#define RomDriver_SF_Cfg_Init_Flash_Gpio \
+    ((void (*)(uint8_t flashPinCfg, uint8_t restoreDefault))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio])
+#define RomDriver_SF_Cfg_Flash_Identify \
+    ((uint32_t(*)(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify])
+
+#define RomDriver_Psram_Init \
+    ((void (*)(SPI_Psram_Cfg_Type * psramCfg, SF_Ctrl_Cmds_Cfg * cmdsCfg, SF_Ctrl_Psram_Cfg * sfCtrlPsramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_Init])
+#define RomDriver_Psram_ReadReg \
+    ((void (*)(SPI_Psram_Cfg_Type * psramCfg, uint8_t * regValue)) ROM_APITABLE[ROM_API_INDEX_Psram_ReadReg])
+#define RomDriver_Psram_WriteReg \
+    ((void (*)(SPI_Psram_Cfg_Type * psramCfg, uint8_t * regValue)) ROM_APITABLE[ROM_API_INDEX_Psram_WriteReg])
+#define RomDriver_Psram_SetDriveStrength \
+    ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_SetDriveStrength])
+#define RomDriver_Psram_SetBurstWrap \
+    ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_SetBurstWrap])
+#define RomDriver_Psram_ReadId \
+    ((void (*)(SPI_Psram_Cfg_Type * psramCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_Psram_ReadId])
+#define RomDriver_Psram_EnterQuadMode \
+    ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_EnterQuadMode])
+#define RomDriver_Psram_ExitQuadMode \
+    ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_ExitQuadMode])
+#define RomDriver_Psram_ToggleBurstLength \
+    ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg, PSRAM_Ctrl_Mode ctrlMode)) ROM_APITABLE[ROM_API_INDEX_Psram_ToggleBurstLength])
+#define RomDriver_Psram_SoftwareReset \
+    ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg, PSRAM_Ctrl_Mode ctrlMode)) ROM_APITABLE[ROM_API_INDEX_Psram_SoftwareReset])
+#define RomDriver_Psram_Set_IDbus_Cfg \
+    ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_Psram_Set_IDbus_Cfg])
+#define RomDriver_Psram_Cache_Write_Set \
+    ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg, SF_Ctrl_IO_Type ioMode, BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn)) ROM_APITABLE[ROM_API_INDEX_Psram_Cache_Write_Set])
+#define RomDriver_Psram_Write \
+    ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_Psram_Write])
+#define RomDriver_Psram_Read \
+    ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_Psram_Read])
+/*@} end of group ROMDRIVER_Public_Types */
+
+/** @defgroup  ROMDRIVER_Public_Constants
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Public_Constants */
+
+/** @defgroup  ROMDRIVER_Public_Macros
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Public_Macros */
+
+/** @defgroup  ROMDRIVER_Public_Functions
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Public_Functions */
+
+/*@} end of group ROMDRIVER */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_ROMDRIVER_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sec_dbg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sec_dbg.h
new file mode 100644
index 00000000..05c35e36
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sec_dbg.h
@@ -0,0 +1,82 @@
+/**
+  ******************************************************************************
+  * @file    bl702_sec_dbg.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_SEC_DBG_H__
+#define __BL702_SEC_DBG_H__
+
+#include "sec_dbg_reg.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SEC_DBG
+ *  @{
+ */
+
+/** @defgroup  SEC_DBG_Public_Types
+ *  @{
+ */
+
+/*@} end of group SEC_DBG_Public_Types */
+
+/** @defgroup  SEC_DBG_Public_Constants
+ *  @{
+ */
+
+/*@} end of group SEC_DBG_Public_Constants */
+
+/** @defgroup  SEC_DBG_Public_Macros
+ *  @{
+ */
+
+/*@} end of group SEC_DBG_Public_Macros */
+
+/** @defgroup  SEC_DBG_Public_Functions
+ *  @{
+ */
+void Sec_Dbg_Read_Chip_ID(uint8_t id[8]);
+void Sec_Dbg_Read_WiFi_MAC(uint8_t macAddr[6]);
+uint32_t Sec_Dbg_Read_Dbg_Mode(void);
+uint32_t Sec_Dbg_Read_Dbg_Enable(void);
+
+/*@} end of group SEC_DBG_Public_Functions */
+
+/*@} end of group SEC_DBG */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_SEC_DBG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sec_eng.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sec_eng.h
new file mode 100644
index 00000000..7bb7eaf6
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sec_eng.h
@@ -0,0 +1,580 @@
+/**
+  ******************************************************************************
+  * @file    bl702_sec_eng.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_SEC_ENG_H__
+#define __BL702_SEC_ENG_H__
+
+#include "sec_eng_reg.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SEC_ENG
+ *  @{
+ */
+
+/** @defgroup  SEC_ENG_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief AES port type definition
+ */
+typedef enum {
+    SEC_ENG_AES_ID0, /*!< AES0 port define */
+} SEC_ENG_AES_ID_Type;
+
+/**
+ *  @brief SHA port type definition
+ */
+typedef enum {
+    SEC_ENG_SHA_ID0, /*!< SHA0 port define */
+} SEC_ENG_SHA_ID_Type;
+
+/**
+ *  @brief SHA type definition
+ */
+typedef enum {
+    SEC_ENG_SHA256,    /*!< SHA type:SHA256 */
+    SEC_ENG_SHA224,    /*!< SHA type:SHA224 */
+    SEC_ENG_SHA1,      /*!< SHA type:SHA1 */
+    SEC_ENG_SHA1_RSVD, /*!< SHA type:SHA1 */
+} SEC_ENG_SHA_Type;
+
+/**
+ *  @brief AES type definition
+ */
+typedef enum {
+    SEC_ENG_AES_ECB, /*!< AES mode type:ECB */
+    SEC_ENG_AES_CTR, /*!< AES mode type:CTR */
+    SEC_ENG_AES_CBC, /*!< AES mode type:CBC */
+} SEC_ENG_AES_Type;
+
+/**
+ *  @brief AES KEY type definition
+ */
+typedef enum {
+    SEC_ENG_AES_KEY_128BITS,        /*!< AES KEY type:128 bits */
+    SEC_ENG_AES_KEY_256BITS,        /*!< AES KEY type:256 bits */
+    SEC_ENG_AES_KEY_192BITS,        /*!< AES KEY type:192 bits */
+    SEC_ENG_AES_DOUBLE_KEY_128BITS, /*!< AES double KEY type:128 bits */
+} SEC_ENG_AES_Key_Type;
+
+/**
+ *  @brief AES CTR mode counter type definition
+ */
+typedef enum {
+    SEC_ENG_AES_COUNTER_BYTE_4, /*!< AES CTR mode counter type:4 bytes */
+    SEC_ENG_AES_COUNTER_BYTE_1, /*!< AES CTR mode counter type:1 byte */
+    SEC_ENG_AES_COUNTER_BYTE_2, /*!< AES CTR mode counter type:2 bytes */
+    SEC_ENG_AES_COUNTER_BYTE_3, /*!< AES CTR mode counter type:3 bytes */
+} SEC_ENG_AES_Counter_Type;
+
+/**
+ *  @brief AES use new or old value type definition
+ */
+typedef enum {
+    SEC_ENG_AES_USE_NEW, /*!< Use new value */
+    SEC_ENG_AES_USE_OLD, /*!< Use old value same as last one */
+} SEC_ENG_AES_ValueUsed_Type;
+
+/**
+ *  @brief AES KEY source type definition
+ */
+typedef enum {
+    SEC_ENG_AES_KEY_SW, /*!< AES KEY from software */
+    SEC_ENG_AES_KEY_HW, /*!< AES KEY from hardware */
+} SEC_ENG_AES_Key_Src_Type;
+
+/**
+ *  @brief AES KEY source type definition
+ */
+typedef enum {
+    SEC_ENG_AES_ENCRYPTION, /*!< AES encryption */
+    SEC_ENG_AES_DECRYPTION, /*!< AES decryption */
+} SEC_ENG_AES_EnDec_Type;
+
+/**
+ *  @brief AES PKA register size type definition
+ */
+typedef enum {
+    SEC_ENG_PKA_REG_SIZE_8 = 1, /*!< Register size is  8 Bytes */
+    SEC_ENG_PKA_REG_SIZE_16,    /*!< Register size is  16 Bytes */
+    SEC_ENG_PKA_REG_SIZE_32,    /*!< Register size is  32 Bytes */
+    SEC_ENG_PKA_REG_SIZE_64,    /*!< Register size is  64 Bytes */
+    SEC_ENG_PKA_REG_SIZE_96,    /*!< Register size is  96 Bytes */
+    SEC_ENG_PKA_REG_SIZE_128,   /*!< Register size is  128 Bytes */
+    SEC_ENG_PKA_REG_SIZE_192,   /*!< Register size is  192 Bytes */
+    SEC_ENG_PKA_REG_SIZE_256,   /*!< Register size is  256 Bytes */
+    SEC_ENG_PKA_REG_SIZE_384,   /*!< Register size is  384 Bytes */
+    SEC_ENG_PKA_REG_SIZE_512,   /*!< Register size is  512 Bytes */
+} SEC_ENG_PKA_REG_SIZE_Type;
+
+/**
+ *  @brief AES PKA register size type definition
+ */
+typedef enum {
+    SEC_ENG_PKA_OP_PPSEL,                /*!< PKA operation type */
+    SEC_ENG_PKA_OP_MOD2N = 0x11,         /*!< PKA operation type */
+    SEC_ENG_PKA_OP_LDIV2N = 0x12,        /*!< PKA operation type */
+    SEC_ENG_PKA_OP_LMUL2N = 0x13,        /*!< PKA operation type */
+    SEC_ENG_PKA_OP_LDIV = 0x14,          /*!< PKA operation type */
+    SEC_ENG_PKA_OP_LSQR = 0x15,          /*!< PKA operation type */
+    SEC_ENG_PKA_OP_LMUL = 0x16,          /*!< PKA operation type */
+    SEC_ENG_PKA_OP_LSUB = 0x17,          /*!< PKA operation type */
+    SEC_ENG_PKA_OP_LADD = 0x18,          /*!< PKA operation type */
+    SEC_ENG_PKA_OP_LCMP = 0x19,          /*!< PKA operation type */
+    SEC_ENG_PKA_OP_MDIV2 = 0x21,         /*!< PKA operation type */
+    SEC_ENG_PKA_OP_MINV = 0x22,          /*!< PKA operation type */
+    SEC_ENG_PKA_OP_MEXP = 0x23,          /*!< PKA operation type */
+    SEC_ENG_PKA_OP_MSQR = 0x24,          /*!< PKA operation type */
+    SEC_ENG_PKA_OP_MMUL = 0x25,          /*!< PKA operation type */
+    SEC_ENG_PKA_OP_MREM = 0x26,          /*!< PKA operation type */
+    SEC_ENG_PKA_OP_MSUB = 0x27,          /*!< PKA operation type */
+    SEC_ENG_PKA_OP_MADD = 0x28,          /*!< PKA operation type */
+    SEC_ENG_PKA_OP_RESIZE = 0x31,        /*!< PKA operation type */
+    SEC_ENG_PKA_OP_MOVDAT = 0x32,        /*!< PKA operation type */
+    SEC_ENG_PKA_OP_NLIR = 0x33,          /*!< PKA operation type */
+    SEC_ENG_PKA_OP_SLIR = 0x34,          /*!< PKA operation type */
+    SEC_ENG_PKA_OP_CLIR = 0x35,          /*!< PKA operation type */
+    SEC_ENG_PKA_OP_CFLIRI_BUFFER = 0x36, /*!< PKA operation type */
+    SEC_ENG_PKA_OP_CTLIRI_PLD = 0x37,    /*!< PKA operation type */
+    SEC_ENG_PKA_OP_CFLIR_BUFFER = 0x38,  /*!< PKA operation type */
+    SEC_ENG_PKA_OP_CTLIR_PLD = 0x39,     /*!< PKA operation type */
+} SEC_ENG_PKA_OP_Type;
+
+/**
+ *  @brief Sec Eng Interrupt Type Def
+ */
+typedef enum {
+    SEC_ENG_INT_TRNG, /*!< Sec Eng Trng Interrupt Type */
+    SEC_ENG_INT_AES,  /*!< Sec Eng Aes Interrupt Type */
+    SEC_ENG_INT_SHA,  /*!< Sec Eng Sha Interrupt Type */
+    SEC_ENG_INT_PKA,  /*!< Sec Eng Pka Interrupt Type */
+    SEC_ENG_INT_CDET, /*!< Sec Eng Cdet Interrupt Type */
+    SEC_ENG_INT_GMAC, /*!< Sec Eng Gmac Interrupt Type */
+    SEC_ENG_INT_ALL,  /*!< Sec Eng All Interrupt Types */
+} SEC_ENG_INT_Type;
+
+/**
+ *  @brief SEC_ENG SHA context
+ */
+typedef struct
+{
+    uint32_t total[2];    /*!< Number of bytes processed */
+    uint32_t *shaBuf;     /*!< Data not processed but in this temp buffer */
+    uint32_t *shaPadding; /*!< Padding data */
+    uint8_t shaFeed;      /*!< Sha has feed data */
+} SEC_Eng_SHA256_Ctx;
+
+/**
+ *  @brief SEC_ENG SHA link mode context
+ */
+typedef struct
+{
+    uint32_t total[2];    /*!< Number of bytes processed */
+    uint32_t *shaBuf;     /*!< Data not processed but in this temp buffer */
+    uint32_t *shaPadding; /*!< Padding data */
+    uint32_t linkAddr;    /*!< Link configure address */
+} SEC_Eng_SHA256_Link_Ctx;
+
+/**
+ *  @brief SEC_ENG AES context
+ */
+typedef struct
+{
+    uint8_t aesFeed;       /*!< AES has feed data */
+    SEC_ENG_AES_Type mode; /*!< AES mode */
+} SEC_Eng_AES_Ctx;
+
+/**
+ *  @brief SEC_ENG SHA link config structure type definition
+ */
+typedef struct
+{
+    uint32_t            : 2;  /*!< [1:0]reserved */
+    uint32_t shaMode    : 3;  /*!< [4:2]Sha-256/sha-224/sha-1/sha-1 */
+    uint32_t            : 1;  /*!< [5]reserved */
+    uint32_t shaHashSel : 1;  /*!< [6]New hash or accumulate last hash */
+    uint32_t            : 2;  /*!< [8:7]reserved */
+    uint32_t shaIntClr  : 1;  /*!< [9]Clear interrupt */
+    uint32_t shaIntSet  : 1;  /*!< [10]Set interrupt */
+    uint32_t            : 5;  /*!< [15:11]reserved */
+    uint32_t shaMsgLen  : 16; /*!< [31:16]Number of 512-bit block */
+    uint32_t shaSrcAddr;      /*!< Message source address */
+    uint32_t result[8];       /*!< Result of SHA */
+} __attribute__((aligned(4))) SEC_Eng_SHA_Link_Config_Type;
+
+/**
+ *  @brief SEC_ENG AES link config structure type definition
+ */
+typedef struct
+{
+    uint32_t              : 3;  /*!< [2:0]Reserved */
+    uint32_t aesMode      : 2;  /*!< [4:3]128-bit/256-bit/192-bit/128-bit-double key mode select */
+    uint32_t aesDecEn     : 1;  /*!< [5]Encode or decode */
+    uint32_t aesDecKeySel : 1;  /*!< [6]Use new key or use same key as last one */
+    uint32_t aesHwKeyEn   : 1;  /*!< [7]Enable or disable using hardware hey */
+    uint32_t              : 1;  /*!< [8]Reserved */
+    uint32_t aesIntClr    : 1;  /*!< [9]Clear interrupt */
+    uint32_t aesIntSet    : 1;  /*!< [10]Set interrupt */
+    uint32_t              : 1;  /*!< [11]Reserved */
+    uint32_t aesBlockMode : 2;  /*!< [13:12]ECB/CTR/CBC mode select */
+    uint32_t aesIVSel     : 1;  /*!< [14]Use new iv or use same iv as last one */
+    uint32_t              : 1;  /*!< [15]Reserved */
+    uint32_t aesMsgLen    : 16; /*!< [31:16]Number of 128-bit block */
+    uint32_t aesSrcAddr;        /*!< Message source address */
+    uint32_t aesDstAddr;        /*!< Message destination address */
+    uint32_t aesIV0;            /*!< Big endian initial vector(MSB) */
+    uint32_t aesIV1;            /*!< Big endian initial vector */
+    uint32_t aesIV2;            /*!< Big endian initial vector */
+    uint32_t aesIV3;            /*!< Big endian initial vector(LSB)(CTR mode:counter initial value) */
+    uint32_t aesKey0;           /*!< Big endian aes key(aes-128/256 key MSB) */
+    uint32_t aesKey1;           /*!< Big endian aes key */
+    uint32_t aesKey2;           /*!< Big endian aes key */
+    uint32_t aesKey3;           /*!< Big endian aes key(aes-128 key LSB) */
+    uint32_t aesKey4;           /*!< Big endian aes key */
+    uint32_t aesKey5;           /*!< Big endian aes key */
+    uint32_t aesKey6;           /*!< Big endian aes key */
+    uint32_t aesKey7;           /*!< Big endian aes key(aes-256 key LSB) */
+} __attribute__((aligned(4))) SEC_Eng_AES_Link_Config_Type;
+
+/**
+ *  @brief SEC_ENG GMAC link config structure type definition
+ */
+typedef struct
+{
+    uint32_t            : 9;  /*!< [8:0]reserved */
+    uint32_t gmacIntClr : 1;  /*!< [9]Clear interrupt */
+    uint32_t gmacIntSet : 1;  /*!< [10]Set interrupt */
+    uint32_t            : 5;  /*!< [15:11]reserved */
+    uint32_t gmacMsgLen : 16; /*!< [31:16]Number of 128-bit block */
+    uint32_t gmacSrcAddr;     /*!< Message source address */
+    uint32_t gmacKey0;        /*!< GMAC key */
+    uint32_t gmacKey1;        /*!< GMAC key */
+    uint32_t gmacKey2;        /*!< GMAC key */
+    uint32_t gmacKey3;        /*!< GMAC key */
+    uint32_t result[4];       /*!< Result of GMAC */
+    uint32_t dummy;           /*!< Not use,trigger GMAC will clear this value */
+} __attribute__((aligned(4))) SEC_Eng_GMAC_Link_Config_Type;
+
+/**
+ *  @brief SEC_ENG PKA status type definition
+ */
+typedef struct
+{
+    uint16_t primeFail   : 1; /*!< [0]Prime fail */
+    uint16_t errUnknown  : 1; /*!< [1]Err unknown opc */
+    uint16_t errOverflow : 1; /*!< [2]Err opq overflow */
+    uint16_t errSrc2     : 1; /*!< [3]Err invalid src2 */
+    uint16_t errSrc1     : 1; /*!< [4]Err invalid src1 */
+    uint16_t errSrc0     : 1; /*!< [5]Err invalid src0 */
+    uint16_t errDiv0     : 1; /*!< [6]Err div by 0 */
+    uint16_t errFull     : 1; /*!< [7]Err cam full */
+    uint16_t lastOpc     : 1; /*!< [8]Last opc */
+    uint16_t opqFull     : 1; /*!< [9]Opq full */
+    uint16_t cmdIndex    : 5; /*!< [14:10]Cmd err index */
+    uint16_t errCmd      : 1; /*!< [15]Err cmd */
+} SEC_Eng_PKA_Status_Type;
+
+/*@} end of group SEC_ENG_Public_Types */
+
+/** @defgroup  SEC_ENG_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  SEC_ENG_AES_ID_TYPE
+ *  @{
+ */
+#define IS_SEC_ENG_AES_ID_TYPE(type) (((type) == SEC_ENG_AES_ID0))
+
+/** @defgroup  SEC_ENG_SHA_ID_TYPE
+ *  @{
+ */
+#define IS_SEC_ENG_SHA_ID_TYPE(type) (((type) == SEC_ENG_SHA_ID0))
+
+/** @defgroup  SEC_ENG_SHA_TYPE
+ *  @{
+ */
+#define IS_SEC_ENG_SHA_TYPE(type) (((type) == SEC_ENG_SHA256) || \
+                                   ((type) == SEC_ENG_SHA224) || \
+                                   ((type) == SEC_ENG_SHA1) ||   \
+                                   ((type) == SEC_ENG_SHA1_RSVD))
+
+/** @defgroup  SEC_ENG_AES_TYPE
+ *  @{
+ */
+#define IS_SEC_ENG_AES_TYPE(type) (((type) == SEC_ENG_AES_ECB) || \
+                                   ((type) == SEC_ENG_AES_CTR) || \
+                                   ((type) == SEC_ENG_AES_CBC))
+
+/** @defgroup  SEC_ENG_AES_KEY_TYPE
+ *  @{
+ */
+#define IS_SEC_ENG_AES_KEY_TYPE(type) (((type) == SEC_ENG_AES_KEY_128BITS) || \
+                                       ((type) == SEC_ENG_AES_KEY_256BITS) || \
+                                       ((type) == SEC_ENG_AES_KEY_192BITS) || \
+                                       ((type) == SEC_ENG_AES_DOUBLE_KEY_128BITS))
+
+/** @defgroup  SEC_ENG_AES_COUNTER_TYPE
+ *  @{
+ */
+#define IS_SEC_ENG_AES_COUNTER_TYPE(type) (((type) == SEC_ENG_AES_COUNTER_BYTE_4) || \
+                                           ((type) == SEC_ENG_AES_COUNTER_BYTE_1) || \
+                                           ((type) == SEC_ENG_AES_COUNTER_BYTE_2) || \
+                                           ((type) == SEC_ENG_AES_COUNTER_BYTE_3))
+
+/** @defgroup  SEC_ENG_AES_VALUEUSED_TYPE
+ *  @{
+ */
+#define IS_SEC_ENG_AES_VALUEUSED_TYPE(type) (((type) == SEC_ENG_AES_USE_NEW) || \
+                                             ((type) == SEC_ENG_AES_USE_OLD))
+
+/** @defgroup  SEC_ENG_AES_KEY_SRC_TYPE
+ *  @{
+ */
+#define IS_SEC_ENG_AES_KEY_SRC_TYPE(type) (((type) == SEC_ENG_AES_KEY_SW) || \
+                                           ((type) == SEC_ENG_AES_KEY_HW))
+
+/** @defgroup  SEC_ENG_AES_ENDEC_TYPE
+ *  @{
+ */
+#define IS_SEC_ENG_AES_ENDEC_TYPE(type) (((type) == SEC_ENG_AES_ENCRYPTION) || \
+                                         ((type) == SEC_ENG_AES_DECRYPTION))
+
+/** @defgroup  SEC_ENG_PKA_REG_SIZE_TYPE
+ *  @{
+ */
+#define IS_SEC_ENG_PKA_REG_SIZE_TYPE(type) (((type) == SEC_ENG_PKA_REG_SIZE_8) ||   \
+                                            ((type) == SEC_ENG_PKA_REG_SIZE_16) ||  \
+                                            ((type) == SEC_ENG_PKA_REG_SIZE_32) ||  \
+                                            ((type) == SEC_ENG_PKA_REG_SIZE_64) ||  \
+                                            ((type) == SEC_ENG_PKA_REG_SIZE_96) ||  \
+                                            ((type) == SEC_ENG_PKA_REG_SIZE_128) || \
+                                            ((type) == SEC_ENG_PKA_REG_SIZE_192) || \
+                                            ((type) == SEC_ENG_PKA_REG_SIZE_256) || \
+                                            ((type) == SEC_ENG_PKA_REG_SIZE_384) || \
+                                            ((type) == SEC_ENG_PKA_REG_SIZE_512))
+
+/** @defgroup  SEC_ENG_PKA_OP_TYPE
+ *  @{
+ */
+#define IS_SEC_ENG_PKA_OP_TYPE(type) (((type) == SEC_ENG_PKA_OP_PPSEL) ||         \
+                                      ((type) == SEC_ENG_PKA_OP_MOD2N) ||         \
+                                      ((type) == SEC_ENG_PKA_OP_LDIV2N) ||        \
+                                      ((type) == SEC_ENG_PKA_OP_LMUL2N) ||        \
+                                      ((type) == SEC_ENG_PKA_OP_LDIV) ||          \
+                                      ((type) == SEC_ENG_PKA_OP_LSQR) ||          \
+                                      ((type) == SEC_ENG_PKA_OP_LMUL) ||          \
+                                      ((type) == SEC_ENG_PKA_OP_LSUB) ||          \
+                                      ((type) == SEC_ENG_PKA_OP_LADD) ||          \
+                                      ((type) == SEC_ENG_PKA_OP_LCMP) ||          \
+                                      ((type) == SEC_ENG_PKA_OP_MDIV2) ||         \
+                                      ((type) == SEC_ENG_PKA_OP_MINV) ||          \
+                                      ((type) == SEC_ENG_PKA_OP_MEXP) ||          \
+                                      ((type) == SEC_ENG_PKA_OP_MSQR) ||          \
+                                      ((type) == SEC_ENG_PKA_OP_MMUL) ||          \
+                                      ((type) == SEC_ENG_PKA_OP_MREM) ||          \
+                                      ((type) == SEC_ENG_PKA_OP_MSUB) ||          \
+                                      ((type) == SEC_ENG_PKA_OP_MADD) ||          \
+                                      ((type) == SEC_ENG_PKA_OP_RESIZE) ||        \
+                                      ((type) == SEC_ENG_PKA_OP_MOVDAT) ||        \
+                                      ((type) == SEC_ENG_PKA_OP_NLIR) ||          \
+                                      ((type) == SEC_ENG_PKA_OP_SLIR) ||          \
+                                      ((type) == SEC_ENG_PKA_OP_CLIR) ||          \
+                                      ((type) == SEC_ENG_PKA_OP_CFLIRI_BUFFER) || \
+                                      ((type) == SEC_ENG_PKA_OP_CTLIRI_PLD) ||    \
+                                      ((type) == SEC_ENG_PKA_OP_CFLIR_BUFFER) ||  \
+                                      ((type) == SEC_ENG_PKA_OP_CTLIR_PLD))
+
+/** @defgroup  SEC_ENG_INT_TYPE
+ *  @{
+ */
+#define IS_SEC_ENG_INT_TYPE(type) (((type) == SEC_ENG_INT_TRNG) || \
+                                   ((type) == SEC_ENG_INT_AES) ||  \
+                                   ((type) == SEC_ENG_INT_SHA) ||  \
+                                   ((type) == SEC_ENG_INT_PKA) ||  \
+                                   ((type) == SEC_ENG_INT_CDET) || \
+                                   ((type) == SEC_ENG_INT_GMAC) || \
+                                   ((type) == SEC_ENG_INT_ALL))
+
+/*@} end of group SEC_ENG_Public_Constants */
+
+/** @defgroup  SEC_ENG_Public_Macros
+ *  @{
+ */
+#define SEC_ENG_PKA_STATUS_LAST_OPC_OFFSET 24
+#define SEC_ENG_PKA_STATUS_LAST_OPC_MASK   0x01000000
+
+/*@} end of group SEC_ENG_Public_Macros */
+
+/** @defgroup  SEC_ENG_Public_Functions
+ *  @{
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+void SEC_GMAC_IRQHandler(void);
+void SEC_CDET_IRQHandler(void);
+void SEC_TRNG_IRQHandler(void);
+void SEC_PKA_IRQHandler(void);
+void SEC_AES_IRQHandler(void);
+void SEC_SHA_IRQHandler(void);
+#endif
+void Sec_Eng_SHA256_Init(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type type,
+                         uint32_t shaTmpBuf[16],
+                         uint32_t padding[16]);
+void Sec_Eng_SHA_Start(SEC_ENG_SHA_ID_Type shaNo);
+BL_Err_Type Sec_Eng_SHA256_Update(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input,
+                                  uint32_t len);
+BL_Err_Type Sec_Eng_SHA256_Finish(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash);
+void Sec_Eng_SHA_Enable_Link(SEC_ENG_SHA_ID_Type shaNo);
+void Sec_Eng_SHA_Disable_Link(SEC_ENG_SHA_ID_Type shaNo);
+void Sec_Eng_SHA256_Link_Init(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr,
+                              uint32_t shaTmpBuf[16], uint32_t padding[16]);
+BL_Err_Type Sec_Eng_SHA256_Link_Update(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo,
+                                       const uint8_t *input, uint32_t len);
+BL_Err_Type Sec_Eng_SHA256_Link_Finish(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo,
+                                       uint8_t *hash);
+BL_Err_Type Sec_Eng_AES_Init(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Type aesType,
+                             SEC_ENG_AES_Key_Type keyType, SEC_ENG_AES_EnDec_Type enDecType);
+void Sec_Eng_AES_Enable_LE(SEC_ENG_AES_ID_Type aesNo);
+void Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID_Type aesNo);
+void Sec_Eng_AES_Enable_Link(SEC_ENG_AES_ID_Type aesNo);
+void Sec_Eng_AES_Disable_Link(SEC_ENG_AES_ID_Type aesNo);
+BL_Err_Type Sec_Eng_AES_Link_Work(SEC_ENG_AES_ID_Type aesNo, uint32_t linkAddr, const uint8_t *in, uint32_t len,
+                                  uint8_t *out);
+void Sec_Eng_AES_Set_Hw_Key_Src(SEC_ENG_AES_ID_Type aesNo, uint8_t src);
+void Sec_Eng_AES_Set_Key_IV(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key,
+                            const uint8_t *iv);
+void Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key,
+                               const uint8_t *iv);
+void Sec_Eng_AES_Set_Counter_Byte(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Counter_Type counterType);
+BL_Err_Type Sec_Eng_AES_Crypt(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, const uint8_t *in, uint32_t len,
+                              uint8_t *out);
+BL_Err_Type Sec_Eng_AES_Finish(SEC_ENG_AES_ID_Type aesNo);
+BL_Err_Type Sec_Eng_Trng_Enable(void);
+void Sec_Eng_Trng_Int_Enable(void);
+void Sec_Eng_Trng_Int_Disable(void);
+BL_Err_Type Sec_Eng_Trng_Read(uint8_t data[32]);
+BL_Err_Type Sec_Eng_Trng_Get_Random(uint8_t *data, uint32_t len);
+void Sec_Eng_Trng_Int_Read_Trigger(void);
+void Sec_Eng_Trng_Int_Read(uint8_t data[32]);
+void Sec_Eng_Trng_Disable(void);
+void Sec_Eng_PKA_Reset(void);
+void Sec_Eng_PKA_BigEndian_Enable(void);
+void Sec_Eng_PKA_LittleEndian_Enable(void);
+void Sec_Eng_PKA_GetStatus(SEC_Eng_PKA_Status_Type *status);
+void Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, const uint32_t *data, uint16_t size,
+                            uint8_t lastOp);
+void Sec_Eng_PKA_Read_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIdx, uint32_t *result, uint8_t retSize);
+void Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_Type dRegType, uint8_t dRegIdx, uint8_t size, uint8_t lastOp);
+void Sec_Eng_PKA_Write_Immediate(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, uint32_t data, uint8_t lastOp);
+void Sec_Eng_PKA_NREG(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp);
+void Sec_Eng_PKA_Move_Data(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp);
+void Sec_Eng_PKA_RESIZE(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp);
+void Sec_Eng_PKA_MADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                      uint8_t s1RegType,
+                      uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp);
+void Sec_Eng_PKA_MSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                      uint8_t s1RegType,
+                      uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp);
+void Sec_Eng_PKA_MREM(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                      uint8_t s2RegType,
+                      uint8_t s2RegIdx, uint8_t lastOp);
+void Sec_Eng_PKA_MMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                      uint8_t s1RegType,
+                      uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp);
+void Sec_Eng_PKA_MSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                      uint8_t s2RegType,
+                      uint8_t s2RegIdx, uint8_t lastOp);
+void Sec_Eng_PKA_MEXP(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                      uint8_t s1RegType,
+                      uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp);
+void Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                      uint8_t s2RegType,
+                      uint8_t s2RegIdx, uint8_t lastOp);
+void Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                      uint8_t s2RegType,
+                      uint8_t s2RegIdx, uint8_t lastOp);
+void Sec_Eng_PKA_LCMP(uint8_t *cout, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx);
+void Sec_Eng_PKA_LADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                      uint8_t s1RegType,
+                      uint8_t s1RegIdx, uint8_t lastOp);
+void Sec_Eng_PKA_LSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                      uint8_t s1RegType,
+                      uint8_t s1RegIdx, uint8_t lastOp);
+void Sec_Eng_PKA_LMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                      uint8_t s1RegType,
+                      uint8_t s1RegIdx, uint8_t lastOp);
+void Sec_Eng_PKA_LSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp);
+void Sec_Eng_PKA_LDIV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                      uint8_t s2RegType,
+                      uint8_t s2RegIdx, uint8_t lastOp);
+void Sec_Eng_PKA_LMUL2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                        uint16_t bit_shift,
+                        uint8_t lastOp);
+void Sec_Eng_PKA_LDIV2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                        uint16_t bit_shift,
+                        uint8_t lastOp);
+void Sec_Eng_PKA_LMOD2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                        uint16_t bit_shift,
+                        uint8_t lastOp);
+void Sec_Eng_PKA_GF2Mont(uint8_t dRegType, uint8_t dRegIdx, uint8_t sRegType, uint8_t sRegIdx, uint32_t size,
+                         uint8_t tRegType, uint8_t tRegIdx, uint8_t pRegType, uint8_t pRegIdx);
+void Sec_Eng_PKA_Mont2GF(uint8_t dRegType, uint8_t dRegIdx, uint8_t aRegType, uint8_t aRegIdx, uint8_t invrRegType,
+                         uint8_t invrRegIdx,
+                         uint8_t tRegType, uint8_t tRegIdx, uint8_t pRegType, uint8_t pRegIdx);
+void Sec_Eng_GMAC_Enable_LE(void);
+void Sec_Eng_GMAC_Enable_BE(void);
+void Sec_Eng_GMAC_Enable_Link(void);
+void Sec_Eng_GMAC_Disable_Link(void);
+BL_Err_Type Sec_Eng_GMAC_Link_Work(uint32_t linkAddr, const uint8_t *in, uint32_t len, uint8_t *out);
+void SEC_Eng_IntMask(SEC_ENG_INT_Type intType, BL_Mask_Type intMask);
+void SEC_Eng_ClrIntStatus(SEC_ENG_INT_Type intType);
+void SEC_Eng_Int_Callback_Install(SEC_ENG_INT_Type intType, intCallback_Type *cbFun);
+BL_Sts_Type SEC_Eng_GetIntStatus(SEC_ENG_INT_Type intType);
+/*----------*/
+void SEC_Eng_Turn_On_Sec_Ring(void);
+void SEC_Eng_Turn_Off_Sec_Ring(void);
+/*----------*/;
+
+/*@} end of group SEC_ENG_Public_Functions */
+
+/*@} end of group SEC_ENG */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_SEC_ENG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sf_cfg.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sf_cfg.h
new file mode 100644
index 00000000..2ecc1228
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sf_cfg.h
@@ -0,0 +1,125 @@
+/**
+  ******************************************************************************
+  * @file    bl702_sf_cfg.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_SF_CFG_H__
+#define __BL702_SF_CFG_H__
+
+#include "string.h"
+#include "bl702_sflash.h"
+#include "bl702_sf_ctrl.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SF_CFG
+ *  @{
+ */
+
+/** @defgroup  SF_CFG_Public_Types
+ *  @{
+ */
+
+/*@} end of group SF_CFG_Public_Types */
+
+/** @defgroup  SF_CFG_Public_Constants
+ *  @{
+ */
+
+/*@} end of group SF_CFG_Public_Constants */
+
+/** @defgroup  SF_CFG_Public_Macros
+ *  @{
+ */
+/* Flash option 0 */
+/* Flash CLK */
+#define BFLB_EXTFLASH_CLK0_GPIO GLB_GPIO_PIN_21
+/* FLASH CS */
+#define BFLB_EXTFLASH_CS0_GPIO GLB_GPIO_PIN_19
+/* FLASH DATA */
+#define BFLB_EXTFLASH_DATA00_GPIO GLB_GPIO_PIN_17
+#define BFLB_EXTFLASH_DATA10_GPIO GLB_GPIO_PIN_18
+#define BFLB_EXTFLASH_DATA20_GPIO GLB_GPIO_PIN_22
+#define BFLB_EXTFLASH_DATA30_GPIO GLB_GPIO_PIN_20
+/* Flash option 1 */
+/* Flash CLK */
+#define BFLB_EXTFLASH_CLK1_GPIO GLB_GPIO_PIN_27
+/* FLASH CS */
+#define BFLB_EXTFLASH_CS1_GPIO GLB_GPIO_PIN_25
+/* FLASH DATA */
+#define BFLB_EXTFLASH_DATA01_GPIO GLB_GPIO_PIN_28
+#define BFLB_EXTFLASH_DATA11_GPIO GLB_GPIO_PIN_24
+#define BFLB_EXTFLASH_DATA21_GPIO GLB_GPIO_PIN_23
+#define BFLB_EXTFLASH_DATA31_GPIO GLB_GPIO_PIN_26
+/* Flash option 2 */
+/* Flash CLK */
+#define BFLB_EXTFLASH_CLK2_GPIO 38
+/* FLASH CS */
+#define BFLB_EXTFLASH_CS2_GPIO 38
+/* FLASH DATA */
+#define BFLB_EXTFLASH_DATA02_GPIO 38
+#define BFLB_EXTFLASH_DATA12_GPIO 38
+#define BFLB_EXTFLASH_DATA22_GPIO 38
+#define BFLB_EXTFLASH_DATA32_GPIO 38
+#define BFLB_FLASH_CFG_SF2_EXT_23_28 0
+#define BFLB_FLASH_CFG_SF2_INT_512K  1
+#define BFLB_FLASH_CFG_SF2_INT_1M    2
+#define BFLB_FLASH_CFG_SF1_EXT_17_22 3
+#define BFLB_SF2_SWAP_NONE           0
+#define BFLB_SF2_SWAP_CS_IO2         1
+#define BFLB_SF2_SWAP_IO0_IO3        2
+#define BFLB_SF2_SWAP_BOTH           3
+#define BFLB_FLASH_ID_VALID_FLAG     0x80000000
+#define BFLB_FLASH_ID_VALID_MASK     0x7FFFFFFF
+
+/*@} end of group SF_CFG_Public_Macros */
+
+/** @defgroup  SF_CFG_Public_Functions
+ *  @{
+ */
+BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg);
+void SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg, uint8_t restoreDefault);
+uint32_t SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault,
+                               SPI_Flash_Cfg_Type *pFlashCfg);
+void SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin);
+void SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin);
+
+/*@} end of group SF_CFG_Public_Functions */
+
+/*@} end of group SF_CFG */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_SF_CFG_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sf_cfg_ext.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sf_cfg_ext.h
new file mode 100644
index 00000000..91a614c5
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sf_cfg_ext.h
@@ -0,0 +1,83 @@
+/**
+  ******************************************************************************
+  * @file    bl702_sf_cfg_ext.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_SF_CFG_EXT_H__
+#define __BL702_SF_CFG_EXT_H__
+
+#include "string.h"
+#include "bl702_sflash.h"
+#include "bl702_sf_ctrl.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SF_CFG_EXT
+ *  @{
+ */
+
+/** @defgroup  SF_CFG_EXT_Public_Types
+ *  @{
+ */
+
+/*@} end of group SF_CFG_EXT_Public_Types */
+
+/** @defgroup  SF_CFG_EXT_Public_Constants
+ *  @{
+ */
+
+/*@} end of group SF_CFG_EXT_Public_Constants */
+
+/** @defgroup  SF_CFG_EXT_Public_Macros
+ *  @{
+ */
+
+/*@} end of group SF_CFG_EXT_Public_Macros */
+
+/** @defgroup  SF_CFG_EXT_Public_Functions
+ *  @{
+ */
+void SF_Cfg_Init_Internal_Flash_Gpio(void);
+BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg);
+uint32_t SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg,
+                                   uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg);
+
+/*@} end of group SF_CFG_EXT_Public_Functions */
+
+/*@} end of group SF_CFG_EXT */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_SF_CFG_EXT_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sf_ctrl.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sf_ctrl.h
new file mode 100644
index 00000000..c964ae07
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sf_ctrl.h
@@ -0,0 +1,410 @@
+/**
+  ******************************************************************************
+  * @file    bl702_sf_ctrl.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_SF_CTRL_H__
+#define __BL702_SF_CTRL_H__
+
+#include "sf_ctrl_reg.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SF_CTRL
+ *  @{
+ */
+
+/** @defgroup  SF_CTRL_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief Serial flash pad select type definition
+ */
+typedef enum {
+    SF_CTRL_PAD_SEL_SF1,               /*!< SF Ctrl pad select sf1, flash use GPIO 17-22, no psram */
+    SF_CTRL_PAD_SEL_SF2,               /*!< SF Ctrl pad select sf2, flash use GPIO 23-28, no psram, embedded flash */
+    SF_CTRL_PAD_SEL_SF3,               /*!< SF Ctrl pad select sf3, flash use GPIO 32-37, no psram */
+    SF_CTRL_PAD_SEL_DUAL_BANK_SF1_SF2, /*!< SF Ctrl pad select sf1 and sf2, flash use GPIO 17-22, psram use GPIO 23-28 */
+    SF_CTRL_PAD_SEL_DUAL_BANK_SF2_SF3, /*!< SF Ctrl pad select sf2 and sf3, flash use GPIO 23-28, psram use GPIO 32-37 */
+    SF_CTRL_PAD_SEL_DUAL_BANK_SF3_SF1, /*!< SF Ctrl pad select sf3 and sf1, flash use GPIO 32-37, psram use GPIO 17-22 */
+    SF_CTRL_PAD_SEL_DUAL_CS_SF2,       /*!< SF Ctrl pad select sf2, flash/psram use GPIO 23-28, psram use GPIO 17 as CS2 */
+    SF_CTRL_PAD_SEL_DUAL_CS_SF3,       /*!< SF Ctrl pad select sf3, flash/psram use GPIO 32-37, psram use GPIO 23 as CS2 */
+} SF_Ctrl_Pad_Select;
+
+/**
+ *  @brief Serial flash system bus control type definition
+ */
+typedef enum {
+    SF_CTRL_SEL_FLASH, /*!< SF Ctrl system bus control flash */
+    SF_CTRL_SEL_PSRAM, /*!< SF Ctrl system bus control psram */
+} SF_Ctrl_Select;
+
+/**
+ *  @brief Serail flash controller wrap mode len type definition
+ */
+typedef enum {
+    SF_CTRL_WRAP_LEN_8,    /*!< SF Ctrl wrap length: 8 */
+    SF_CTRL_WRAP_LEN_16,   /*!< SF Ctrl wrap length: 16 */
+    SF_CTRL_WRAP_LEN_32,   /*!< SF Ctrl wrap length: 32 */
+    SF_CTRL_WRAP_LEN_64,   /*!< SF Ctrl wrap length: 64 */
+    SF_CTRL_WRAP_LEN_128,  /*!< SF Ctrl wrap length: 128 */
+    SF_CTRL_WRAP_LEN_256,  /*!< SF Ctrl wrap length: 256 */
+    SF_CTRL_WRAP_LEN_512,  /*!< SF Ctrl wrap length: 512 */
+    SF_CTRL_WRAP_LEN_1024, /*!< SF Ctrl wrap length: 1024 */
+    SF_CTRL_WRAP_LEN_2048, /*!< SF Ctrl wrap length: 2048 */
+    SF_CTRL_WRAP_LEN_4096, /*!< SF Ctrl wrap length: 4096 */
+} SF_Ctrl_Wrap_Len_Type;
+
+/**
+ *  @brief Serial flash controller owner type definition
+ */
+typedef enum {
+    SF_CTRL_OWNER_SAHB, /*!< System AHB bus control serial flash controller */
+    SF_CTRL_OWNER_IAHB, /*!< I-Code AHB bus control serial flash controller */
+} SF_Ctrl_Owner_Type;
+
+/**
+ *  @brief Serial flash controller select clock type definition
+ */
+typedef enum {
+    SF_CTRL_SAHB_CLOCK,  /*!< Serial flash controller select default sahb clock */
+    SF_CTRL_FLASH_CLOCK, /*!< Serial flash controller select flash clock */
+} SF_Ctrl_Sahb_Type;
+
+/**
+ *  @brief Serial flash controller owner type definition
+ */
+typedef enum {
+    HIGH_SPEED_MODE_CLOCK,  /*!< Serial flash controller high speed mode clk_ahb>clk_sf */
+    REMOVE_CLOCK_CONSTRAIN, /*!< Serial flash controller remove clock constrain */
+} SF_Ctrl_Ahb2sif_Type;
+
+/**
+ *  @brief Read and write type definition
+ */
+typedef enum {
+    SF_CTRL_READ,  /*!< Serail flash read command flag */
+    SF_CTRL_WRITE, /*!< Serail flash write command flag */
+} SF_Ctrl_RW_Type;
+
+/**
+ *  @brief Serail flash interface IO type definition
+ */
+typedef enum {
+    SF_CTRL_NIO_MODE, /*!< Normal IO mode define */
+    SF_CTRL_DO_MODE,  /*!< Dual Output mode define */
+    SF_CTRL_QO_MODE,  /*!< Quad Output mode define */
+    SF_CTRL_DIO_MODE, /*!< Dual IO mode define */
+    SF_CTRL_QIO_MODE, /*!< Quad IO mode define */
+} SF_Ctrl_IO_Type;
+
+/**
+ *  @brief Serail flash controller interface mode type definition
+ */
+typedef enum {
+    SF_CTRL_SPI_MODE, /*!< SPI mode define */
+    SF_CTRL_QPI_MODE, /*!< QPI mode define */
+} SF_Ctrl_Mode_Type;
+
+/**
+ *  @brief Serail flash controller command mode type definition
+ */
+typedef enum {
+    SF_CTRL_CMD_1_LINE,  /*!< Command in one line mode */
+    SF_CTRL_CMD_4_LINES, /*!< Command in four lines mode */
+} SF_Ctrl_Cmd_Mode_Type;
+
+/**
+ *  @brief Serail flash controller address mode type definition
+ */
+typedef enum {
+    SF_CTRL_ADDR_1_LINE,  /*!< Address in one line mode */
+    SF_CTRL_ADDR_2_LINES, /*!< Address in two lines mode */
+    SF_CTRL_ADDR_4_LINES, /*!< Address in four lines mode */
+} SF_Ctrl_Addr_Mode_Type;
+
+/**
+ *  @brief Serail flash controller dummy mode type definition
+ */
+typedef enum {
+    SF_CTRL_DUMMY_1_LINE,  /*!< Dummy in one line mode */
+    SF_CTRL_DUMMY_2_LINES, /*!< Dummy in two lines mode */
+    SF_CTRL_DUMMY_4_LINES, /*!< Dummy in four lines mode */
+} SF_Ctrl_Dmy_Mode_Type;
+
+/**
+ *  @brief Serail flash controller data mode type definition
+ */
+typedef enum {
+    SF_CTRL_DATA_1_LINE,  /*!< Data in one line mode */
+    SF_CTRL_DATA_2_LINES, /*!< Data in two lines mode */
+    SF_CTRL_DATA_4_LINES, /*!< Data in four lines mode */
+} SF_Ctrl_Data_Mode_Type;
+
+/**
+ *  @brief Serail flash controller AES type definition
+ */
+typedef enum {
+    SF_CTRL_AES_128BITS,            /*!< Serail flash AES key 128 bits length */
+    SF_CTRL_AES_256BITS,            /*!< Serail flash AES key 256 bits length */
+    SF_CTRL_AES_192BITS,            /*!< Serail flash AES key 192 bits length */
+    SF_CTRL_AES_128BITS_DOUBLE_KEY, /*!< Serail flash AES key 128 bits length double key */
+} SF_Ctrl_AES_Key_Type;
+
+/**
+ *  @brief Serail flash controller configuration structure type definition
+ */
+typedef struct
+{
+    SF_Ctrl_Owner_Type owner;         /*!< Sflash interface bus owner */
+    SF_Ctrl_Sahb_Type sahbClock;      /*!< Sflash clock sahb sram select */
+    SF_Ctrl_Ahb2sif_Type ahb2sifMode; /*!< Sflash ahb2sif mode */
+    uint8_t clkDelay;                 /*!< Clock count for read due to pad delay */
+    uint8_t clkInvert;                /*!< Clock invert */
+    uint8_t rxClkInvert;              /*!< RX clock invert */
+    uint8_t doDelay;                  /*!< Data out delay */
+    uint8_t diDelay;                  /*!< Data in delay */
+    uint8_t oeDelay;                  /*!< Output enable delay */
+} SF_Ctrl_Cfg_Type;
+
+/**
+ *  @brief SF Ctrl psram controller configuration structure type definition
+ */
+typedef struct
+{
+    SF_Ctrl_Owner_Type owner;        /*!< Psram interface bus owner */
+    SF_Ctrl_Pad_Select padSel;       /*!< SF Ctrl pad select */
+    SF_Ctrl_Select bankSel;          /*!< SF Ctrl bank select */
+    BL_Fun_Type psramRxClkInvertSrc; /*!< Select psram rx clock invert source */
+    BL_Fun_Type psramRxClkInvertSel; /*!< Select inveted psram rx clock */
+    BL_Fun_Type psramDelaySrc;       /*!< Select psram read delay source */
+    uint8_t psramClkDelay;           /*!< Psram read delay cycle = n + 1 */
+} SF_Ctrl_Psram_Cfg;
+
+/**
+ *  @brief SF Ctrl cmds configuration structure type definition
+ */
+typedef struct
+{
+    BL_Fun_Type cmdsEn;            /*!< SF Ctrl cmds enable */
+    BL_Fun_Type burstToggleEn;     /*!< SF Ctrl burst toggle mode enable */
+    BL_Fun_Type wrapModeEn;        /*!< SF Ctrl wrap mode cmd enable */
+    SF_Ctrl_Wrap_Len_Type wrapLen; /*!< SF Ctrl wrap length */
+} SF_Ctrl_Cmds_Cfg;
+
+/**
+ *  @brief Serail flash command configuration structure type definition
+ */
+typedef struct
+{
+    uint8_t rwFlag;                  /*!< Read write flag */
+    SF_Ctrl_Cmd_Mode_Type cmdMode;   /*!< Command mode */
+    SF_Ctrl_Addr_Mode_Type addrMode; /*!< Address mode */
+    uint8_t addrSize;                /*!< Address size */
+    uint8_t dummyClks;               /*!< Dummy clocks */
+    SF_Ctrl_Dmy_Mode_Type dummyMode; /*!< Dummy mode */
+    SF_Ctrl_Data_Mode_Type dataMode; /*!< Data mode */
+    uint8_t rsv[1];                  /*!<  */
+    uint32_t nbData;                 /*!< Transfer number of bytes */
+    uint32_t cmdBuf[2];              /*!< Command buffer */
+} SF_Ctrl_Cmd_Cfg_Type;
+
+/*@} end of group SF_CTRL_Public_Types */
+
+/** @defgroup  SF_CTRL_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  SF_CTRL_PAD_SELECT
+ *  @{
+ */
+#define IS_SF_CTRL_PAD_SELECT(type) (((type) == SF_CTRL_PAD_SEL_SF1) ||               \
+                                     ((type) == SF_CTRL_PAD_SEL_SF2) ||               \
+                                     ((type) == SF_CTRL_PAD_SEL_SF3) ||               \
+                                     ((type) == SF_CTRL_PAD_SEL_DUAL_BANK_SF1_SF2) || \
+                                     ((type) == SF_CTRL_PAD_SEL_DUAL_BANK_SF2_SF3) || \
+                                     ((type) == SF_CTRL_PAD_SEL_DUAL_BANK_SF3_SF1) || \
+                                     ((type) == SF_CTRL_PAD_SEL_DUAL_CS_SF2) ||       \
+                                     ((type) == SF_CTRL_PAD_SEL_DUAL_CS_SF3))
+
+/** @defgroup  SF_CTRL_SELECT
+ *  @{
+ */
+#define IS_SF_CTRL_SELECT(type) (((type) == SF_CTRL_SEL_FLASH) || \
+                                 ((type) == SF_CTRL_SEL_PSRAM))
+
+/** @defgroup  SF_CTRL_WRAP_LEN_TYPE
+ *  @{
+ */
+#define IS_SF_CTRL_WRAP_LEN_TYPE(type) (((type) == SF_CTRL_WRAP_LEN_8) ||    \
+                                        ((type) == SF_CTRL_WRAP_LEN_16) ||   \
+                                        ((type) == SF_CTRL_WRAP_LEN_32) ||   \
+                                        ((type) == SF_CTRL_WRAP_LEN_64) ||   \
+                                        ((type) == SF_CTRL_WRAP_LEN_128) ||  \
+                                        ((type) == SF_CTRL_WRAP_LEN_256) ||  \
+                                        ((type) == SF_CTRL_WRAP_LEN_512) ||  \
+                                        ((type) == SF_CTRL_WRAP_LEN_1024) || \
+                                        ((type) == SF_CTRL_WRAP_LEN_2048) || \
+                                        ((type) == SF_CTRL_WRAP_LEN_4096))
+
+/** @defgroup  SF_CTRL_OWNER_TYPE
+ *  @{
+ */
+#define IS_SF_CTRL_OWNER_TYPE(type) (((type) == SF_CTRL_OWNER_SAHB) || \
+                                     ((type) == SF_CTRL_OWNER_IAHB))
+
+/** @defgroup  SF_CTRL_SAHB_TYPE
+ *  @{
+ */
+#define IS_SF_CTRL_SAHB_TYPE(type) (((type) == SF_CTRL_SAHB_CLOCK) || \
+                                    ((type) == SF_CTRL_FLASH_CLOCK))
+
+/** @defgroup  SF_CTRL_AHB2SIF_TYPE
+ *  @{
+ */
+#define IS_SF_CTRL_AHB2SIF_TYPE(type) (((type) == HIGH_SPEED_MODE_CLOCK) || \
+                                       ((type) == REMOVE_CLOCK_CONSTRAIN))
+
+/** @defgroup  SF_CTRL_RW_TYPE
+ *  @{
+ */
+#define IS_SF_CTRL_RW_TYPE(type) (((type) == SF_CTRL_READ) || \
+                                  ((type) == SF_CTRL_WRITE))
+
+/** @defgroup  SF_CTRL_IO_TYPE
+ *  @{
+ */
+#define IS_SF_CTRL_IO_TYPE(type) (((type) == SF_CTRL_NIO_MODE) || \
+                                  ((type) == SF_CTRL_DO_MODE) ||  \
+                                  ((type) == SF_CTRL_QO_MODE) ||  \
+                                  ((type) == SF_CTRL_DIO_MODE) || \
+                                  ((type) == SF_CTRL_QIO_MODE))
+
+/** @defgroup  SF_CTRL_MODE_TYPE
+ *  @{
+ */
+#define IS_SF_CTRL_MODE_TYPE(type) (((type) == SF_CTRL_SPI_MODE) || \
+                                    ((type) == SF_CTRL_QPI_MODE))
+
+/** @defgroup  SF_CTRL_CMD_MODE_TYPE
+ *  @{
+ */
+#define IS_SF_CTRL_CMD_MODE_TYPE(type) (((type) == SF_CTRL_CMD_1_LINE) || \
+                                        ((type) == SF_CTRL_CMD_4_LINES))
+
+/** @defgroup  SF_CTRL_ADDR_MODE_TYPE
+ *  @{
+ */
+#define IS_SF_CTRL_ADDR_MODE_TYPE(type) (((type) == SF_CTRL_ADDR_1_LINE) ||  \
+                                         ((type) == SF_CTRL_ADDR_2_LINES) || \
+                                         ((type) == SF_CTRL_ADDR_4_LINES))
+
+/** @defgroup  SF_CTRL_DMY_MODE_TYPE
+ *  @{
+ */
+#define IS_SF_CTRL_DMY_MODE_TYPE(type) (((type) == SF_CTRL_DUMMY_1_LINE) ||  \
+                                        ((type) == SF_CTRL_DUMMY_2_LINES) || \
+                                        ((type) == SF_CTRL_DUMMY_4_LINES))
+
+/** @defgroup  SF_CTRL_DATA_MODE_TYPE
+ *  @{
+ */
+#define IS_SF_CTRL_DATA_MODE_TYPE(type) (((type) == SF_CTRL_DATA_1_LINE) ||  \
+                                         ((type) == SF_CTRL_DATA_2_LINES) || \
+                                         ((type) == SF_CTRL_DATA_4_LINES))
+
+/** @defgroup  SF_CTRL_AES_KEY_TYPE
+ *  @{
+ */
+#define IS_SF_CTRL_AES_KEY_TYPE(type) (((type) == SF_CTRL_AES_128BITS) || \
+                                       ((type) == SF_CTRL_AES_256BITS) || \
+                                       ((type) == SF_CTRL_AES_192BITS) || \
+                                       ((type) == SF_CTRL_AES_128BITS_DOUBLE_KEY))
+
+/*@} end of group SF_CTRL_Public_Constants */
+
+/** @defgroup  SF_CTRL_Public_Macros
+ *  @{
+ */
+#define SF_CTRL_NO_ADDRESS  0xFFFFFFFF
+#define FLASH_CTRL_BUF_SIZE 256
+
+/*@} end of group SF_CTRL_Public_Macros */
+
+/** @defgroup  SF_CTRL_Public_Functions
+ *  @{
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+void SF_Ctrl_IRQHandler(void);
+#endif
+void SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg);
+void SF_Ctrl_Psram_Init(SF_Ctrl_Psram_Cfg *psramCfg);
+uint8_t SF_Ctrl_Get_Clock_Delay(void);
+void SF_Ctrl_Set_Clock_Delay(uint8_t delay);
+void SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg);
+void SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Select sel);
+void SF_Ctrl_Select_Bank(SF_Ctrl_Select sel);
+void SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner);
+void SF_Ctrl_Disable(void);
+void SF_Ctrl_AES_Enable_BE(void);
+void SF_Ctrl_AES_Enable_LE(void);
+void SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr,
+                            uint32_t endAddr,
+                            uint8_t locked);
+void SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType);
+void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType);
+void SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset);
+void SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset);
+void SF_Ctrl_AES_Enable(void);
+void SF_Ctrl_AES_Disable(void);
+uint8_t SF_Ctrl_Is_AES_Enable(void);
+void SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset);
+uint32_t SF_Ctrl_Get_Flash_Image_Offset(void);
+void SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType);
+void SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg);
+void SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid);
+void SF_Ctrl_Psram_Write_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid);
+void SF_Ctrl_Psram_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid);
+BL_Sts_Type SF_Ctrl_GetBusyState(void);
+
+/*@} end of group SF_CTRL_Public_Functions */
+
+/*@} end of group SF_CTRL */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_SF_CTRL_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sflash.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sflash.h
new file mode 100644
index 00000000..33fc6711
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sflash.h
@@ -0,0 +1,197 @@
+/**
+  ******************************************************************************
+  * @file    bl702_sflah.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_SFLAH_H__
+#define __BL702_SFLAH_H__
+
+#include "bl702_common.h"
+#include "bl702_sf_ctrl.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SFLAH
+ *  @{
+ */
+
+/** @defgroup  SFLAH_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief Serial flash configuration structure type definition
+ */
+typedef struct
+{
+    uint8_t ioMode;               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
+    uint8_t cReadSupport;         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+    uint8_t clkDelay;             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+    uint8_t clkInvert;            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+    uint8_t resetEnCmd;           /*!< Flash enable reset command */
+    uint8_t resetCmd;             /*!< Flash reset command */
+    uint8_t resetCreadCmd;        /*!< Flash reset continuous read command */
+    uint8_t resetCreadCmdSize;    /*!< Flash reset continuous read command size */
+    uint8_t jedecIdCmd;           /*!< JEDEC ID command */
+    uint8_t jedecIdCmdDmyClk;     /*!< JEDEC ID command dummy clock */
+    uint8_t qpiJedecIdCmd;        /*!< QPI JEDEC ID comamnd */
+    uint8_t qpiJedecIdCmdDmyClk;  /*!< QPI JEDEC ID command dummy clock */
+    uint8_t sectorSize;           /*!< *1024bytes */
+    uint8_t mid;                  /*!< Manufacturer ID */
+    uint16_t pageSize;            /*!< Page size */
+    uint8_t chipEraseCmd;         /*!< Chip erase cmd */
+    uint8_t sectorEraseCmd;       /*!< Sector erase command */
+    uint8_t blk32EraseCmd;        /*!< Block 32K erase command,some Micron not support */
+    uint8_t blk64EraseCmd;        /*!< Block 64K erase command */
+    uint8_t writeEnableCmd;       /*!< Need before every erase or program */
+    uint8_t pageProgramCmd;       /*!< Page program cmd */
+    uint8_t qpageProgramCmd;      /*!< QIO page program cmd */
+    uint8_t qppAddrMode;          /*!< QIO page program address mode */
+    uint8_t fastReadCmd;          /*!< Fast read command */
+    uint8_t frDmyClk;             /*!< Fast read command dummy clock */
+    uint8_t qpiFastReadCmd;       /*!< QPI fast read command */
+    uint8_t qpiFrDmyClk;          /*!< QPI fast read command dummy clock */
+    uint8_t fastReadDoCmd;        /*!< Fast read dual output command */
+    uint8_t frDoDmyClk;           /*!< Fast read dual output command dummy clock */
+    uint8_t fastReadDioCmd;       /*!< Fast read dual io comamnd */
+    uint8_t frDioDmyClk;          /*!< Fast read dual io command dummy clock */
+    uint8_t fastReadQoCmd;        /*!< Fast read quad output comamnd */
+    uint8_t frQoDmyClk;           /*!< Fast read quad output comamnd dummy clock */
+    uint8_t fastReadQioCmd;       /*!< Fast read quad io comamnd */
+    uint8_t frQioDmyClk;          /*!< Fast read quad io comamnd dummy clock */
+    uint8_t qpiFastReadQioCmd;    /*!< QPI fast read quad io comamnd */
+    uint8_t qpiFrQioDmyClk;       /*!< QPI fast read QIO dummy clock */
+    uint8_t qpiPageProgramCmd;    /*!< QPI program command */
+    uint8_t writeVregEnableCmd;   /*!< Enable write reg */
+    uint8_t wrEnableIndex;        /*!< Write enable register index */
+    uint8_t qeIndex;              /*!< Quad mode enable register index */
+    uint8_t busyIndex;            /*!< Busy status register index */
+    uint8_t wrEnableBit;          /*!< Write enable bit pos */
+    uint8_t qeBit;                /*!< Quad enable bit pos */
+    uint8_t busyBit;              /*!< Busy status bit pos */
+    uint8_t wrEnableWriteRegLen;  /*!< Register length of write enable */
+    uint8_t wrEnableReadRegLen;   /*!< Register length of write enable status */
+    uint8_t qeWriteRegLen;        /*!< Register length of contain quad enable */
+    uint8_t qeReadRegLen;         /*!< Register length of contain quad enable status */
+    uint8_t releasePowerDown;     /*!< Release power down command */
+    uint8_t busyReadRegLen;       /*!< Register length of contain busy status */
+    uint8_t readRegCmd[4];        /*!< Read register command buffer */
+    uint8_t writeRegCmd[4];       /*!< Write register command buffer */
+    uint8_t enterQpi;             /*!< Enter qpi command */
+    uint8_t exitQpi;              /*!< Exit qpi command */
+    uint8_t cReadMode;            /*!< Config data for continuous read mode */
+    uint8_t cRExit;               /*!< Config data for exit continuous read mode */
+    uint8_t burstWrapCmd;         /*!< Enable burst wrap command */
+    uint8_t burstWrapCmdDmyClk;   /*!< Enable burst wrap command dummy clock */
+    uint8_t burstWrapDataMode;    /*!< Data and address mode for this command */
+    uint8_t burstWrapData;        /*!< Data to enable burst wrap */
+    uint8_t deBurstWrapCmd;       /*!< Disable burst wrap command */
+    uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
+    uint8_t deBurstWrapDataMode;  /*!< Data and address mode for this command */
+    uint8_t deBurstWrapData;      /*!< Data to disable burst wrap */
+    uint16_t timeEsector;         /*!< 4K erase time */
+    uint16_t timeE32k;            /*!< 32K erase time */
+    uint16_t timeE64k;            /*!< 64K erase time */
+    uint16_t timePagePgm;         /*!< Page program time */
+    uint16_t timeCe;              /*!< Chip erase time in ms */
+    uint8_t pdDelay;              /*!< Release power down command delay time for wake up */
+    uint8_t qeData;               /*!< QE set data */
+} __attribute__((packed)) SPI_Flash_Cfg_Type;
+
+/*@} end of group SFLAH_Public_Types */
+
+/** @defgroup  SFLAH_Public_Constants
+ *  @{
+ */
+
+/*@} end of group SFLAH_Public_Constants */
+
+/** @defgroup  SFLAH_Public_Macros
+ *  @{
+ */
+#define BFLB_SPIFLASH_BLK32K_SIZE (32 * 1024)
+#define BFLB_SPIFLASH_BLK64K_SIZE (64 * 1024)
+#define BFLB_SPIFLASH_CMD_INVALID 0xff
+
+/*@} end of group SFLAH_Public_Macros */
+
+/** @defgroup  SFLAH_Public_Functions
+ *  @{
+ */
+void SFlash_Init(const SF_Ctrl_Cfg_Type *sfCtrlCfg);
+BL_Err_Type SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode);
+BL_Err_Type SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen);
+BL_Err_Type SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen);
+BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue,
+                                     uint8_t regLen);
+BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue,
+                                      uint8_t regLen);
+BL_Sts_Type SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg);
+BL_Err_Type SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg);
+BL_Err_Type SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg);
+void SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg);
+BL_Err_Type SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg);
+BL_Err_Type SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum);
+BL_Err_Type SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum);
+BL_Err_Type SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum);
+BL_Err_Type SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr);
+BL_Err_Type SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len);
+void SFlash_GetUniqueId(uint8_t *data, uint8_t idLen);
+void SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data);
+void SFlash_GetDeviceId(uint8_t *data);
+void SFlash_Powerdown(void);
+void SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg);
+BL_Err_Type SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead);
+void SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg);
+void SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg);
+BL_Err_Type SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg);
+void SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg);
+BL_Err_Type SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr,
+                                 uint32_t len);
+BL_Err_Type SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead);
+BL_Err_Type SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead,
+                                     uint8_t wayDisable);
+void SFlash_Cache_Read_Disable(void);
+BL_Err_Type SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead);
+BL_Err_Type SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data,
+                        uint32_t len);
+
+/*@} end of group SFLAH_Public_Functions */
+
+/*@} end of group SFLAH */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_SFLAH_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sflash_ext.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sflash_ext.h
new file mode 100644
index 00000000..41e65a39
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sflash_ext.h
@@ -0,0 +1,104 @@
+/**
+  ******************************************************************************
+  * @file    bl702_sflah_ext.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_SFLAH_EXT_H__
+#define __BL702_SFLAH_EXT_H__
+
+#include "bl702_sflash.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SFLAH_EXT
+ *  @{
+ */
+
+/** @defgroup  SFLAH_EXT_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief Serail flash protect KH25V40 type definition
+ */
+typedef enum {
+    SFLASH_KH25V40_PROTECT_NONE,          /*!< SFlash no protect KH25V40 */
+    SFLASH_KH25V40_PROTECT_448KTO512K,    /*!< SFlash protect KH25V40 448K to 512K */
+    SFLASH_KH25V40_PROTECT_384KTO512K,    /*!< SFlash protect KH25V40 384K to 512K */
+    SFLASH_KH25V40_PROTECT_256KTO512K,    /*!< SFlash protect KH25V40 256K to 512K */
+    SFLASH_KH25V40_PROTECT_ALL,           /*!< SFlash protect KH25V40 0K to 512K */
+} SFlash_Protect_Kh25v40_Type;
+
+/*@} end of group SFLAH_EXT_Public_Types */
+
+/** @defgroup  SFLAH_EXT_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  SFLASH_PROTECT_KH25V40_TYPE
+ *  @{
+ */
+#define IS_SFLASH_PROTECT_KH25V40_TYPE(type) (((type) == SFLASH_KH25V40_PROTECT_NONE) || \
+                                              ((type) == SFLASH_KH25V40_PROTECT_448KTO512K) ||  \
+                                              ((type) == SFLASH_KH25V40_PROTECT_384KTO512K) ||  \
+                                              ((type) == SFLASH_KH25V40_PROTECT_256KTO512K) || \
+                                              ((type) == SFLASH_KH25V40_PROTECT_ALL))
+
+/*@} end of group SFLAH_EXT_Public_Constants */
+
+/** @defgroup  SFLAH_EXT_Public_Macros
+ *  @{
+ */
+
+/*@} end of group SFLAH_EXT_Public_Macros */
+
+/** @defgroup  SFLAH_EXT_Public_Functions
+ *  @{
+ */
+BL_Err_Type SFlash_KH25V40_Write_Protect(SPI_Flash_Cfg_Type *flashCfg, SFlash_Protect_Kh25v40_Type protect);
+BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue,
+                                     uint8_t regLen);
+BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue,
+                                      uint8_t regLen);
+BL_Err_Type SFlash_Clear_Status_Register(SPI_Flash_Cfg_Type *pFlashCfg);
+
+/*@} end of group SFLAH_EXT_Public_Functions */
+
+/*@} end of group SFLAH_EXT */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_SFLAH_EXT_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_spi.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_spi.h
new file mode 100644
index 00000000..a8b9d1ab
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_spi.h
@@ -0,0 +1,317 @@
+/**
+  ******************************************************************************
+  * @file    bl702_spi.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_SPI_H__
+#define __BL702_SPI_H__
+
+#include "spi_reg.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SPI
+ *  @{
+ */
+
+/** @defgroup  SPI_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief SPI No. type definition
+ */
+typedef enum {
+    SPI_ID_0,   /*!< SPI0 port define */
+    SPI_ID_MAX, /*!< SPI MAX ID define */
+} SPI_ID_Type;
+
+/**
+ *  @brief SPI byte inverse type definition
+ */
+typedef enum {
+    SPI_BYTE_INVERSE_BYTE0_FIRST, /*!< SPI byte 0 is sent out first */
+    SPI_BYTE_INVERSE_BYTE3_FIRST, /*!< SPI byte 3 is sent out first */
+} SPI_BYTE_INVERSE_Type;
+
+/**
+ *  @brief SPI bit inverse type definition
+ */
+typedef enum {
+    SPI_BIT_INVERSE_MSB_FIRST, /*!< SPI each byte is sent out MSB first */
+    SPI_BIT_INVERSE_LSB_FIRST, /*!< SPI each byte is sent out LSB first */
+} SPI_BIT_INVERSE_Type;
+
+/**
+ *  @brief SPI clock phase inverse type definition
+ */
+typedef enum {
+    SPI_CLK_PHASE_INVERSE_0, /*!< SPI clock phase inverse 0 */
+    SPI_CLK_PHASE_INVERSE_1, /*!< SPI clock phase inverse 1 */
+} SPI_CLK_PHASE_INVERSE_Type;
+
+/**
+ *  @brief SPI clock polarity type definition
+ */
+typedef enum {
+    SPI_CLK_POLARITY_LOW,  /*!< SPI clock output low at IDLE state */
+    SPI_CLK_POLARITY_HIGH, /*!< SPI clock output high at IDLE state */
+} SPI_CLK_POLARITY_Type;
+
+/**
+ *  @brief SPI frame size(also the valid width for each fifo entry) type definition
+ */
+typedef enum {
+    SPI_FRAME_SIZE_8,  /*!< SPI frame size 8 bit */
+    SPI_FRAME_SIZE_16, /*!< SPI frame size 16 bit */
+    SPI_FRAME_SIZE_24, /*!< SPI frame size 24 bit */
+    SPI_FRAME_SIZE_32, /*!< SPI frame size 32 bit */
+} SPI_FrameSize_Type;
+
+/**
+ *  @brief SPI work mode select type definition
+ */
+typedef enum {
+    SPI_WORK_MODE_SLAVE,  /*!< SPI work at slave mode */
+    SPI_WORK_MODE_MASTER, /*!< SPI work at master mode */
+} SPI_WORK_MODE_Type;
+
+/**
+ *  @brief SPI enable or disable timeout judgment definition
+ */
+typedef enum {
+    SPI_TIMEOUT_DISABLE, /*!< SPI disable timeout judgment */
+    SPI_TIMEOUT_ENABLE,  /*!< SPI enable timeout judgment */
+} SPI_Timeout_Type;
+
+/**
+ *  @brief SPI fifo overflow/underflow flag type definition
+ */
+typedef enum {
+    SPI_FIFO_TX_OVERFLOW,  /*!< SPI tx fifo overflow flag */
+    SPI_FIFO_TX_UNDERFLOW, /*!< SPI tx fifo underflow flag */
+    SPI_FIFO_RX_OVERFLOW,  /*!< SPI rx fifo overflow flag */
+    SPI_FIFO_RX_UNDERFLOW, /*!< SPI rx fifo underflow flag */
+} SPI_FifoStatus_Type;
+
+/**
+ *  @brief SPI interrupt type definition
+ */
+typedef enum {
+    SPI_INT_END,            /*!< SPI transfer end interrupt,shared by both master and slave mode */
+    SPI_INT_TX_FIFO_REQ,    /*!< SPI tx fifo ready interrupt(tx fifo count > tx fifo threshold) */
+    SPI_INT_RX_FIFO_REQ,    /*!< SPI rx fifo ready interrupt(rx fifo count > rx fifo threshold) */
+    SPI_INT_SLAVE_TIMEOUT,  /*!< SPI slave mode transfer time-out interrupt,triggered when spi bus is idle for the given value */
+    SPI_INT_SLAVE_UNDERRUN, /*!< SPI slave mode tx underrun error interrupt,triggered when tx is not ready during transfer */
+    SPI_INT_FIFO_ERROR,     /*!< SPI tx/rx fifo error interrupt(overflow/underflow) */
+    SPI_INT_ALL,            /*!< All the interrupt */
+} SPI_INT_Type;
+
+/**
+ *  @brief SPI configuration type definition
+ */
+typedef struct
+{
+    BL_Fun_Type deglitchEnable;             /*!< Enable or disable de-glitch function */
+    BL_Fun_Type continuousEnable;           /*!< Enable or disable master continuous transfer mode,enable:SS will stay asserted if next data is valid */
+    SPI_BYTE_INVERSE_Type byteSequence;     /*!< The byte is sent first in SPI transfer */
+    SPI_BIT_INVERSE_Type bitSequence;       /*!< The bit is sent first in SPI transfer */
+    SPI_CLK_PHASE_INVERSE_Type clkPhaseInv; /*!< Inverse SPI clock phase */
+    SPI_CLK_POLARITY_Type clkPolarity;      /*!< SPI clock plarity */
+    SPI_FrameSize_Type frameSize;           /*!< SPI frame size(also the valid width for each fifo entry) */
+} SPI_CFG_Type;
+
+/**
+ *  @brief SPI configuration type definition
+ */
+typedef struct
+{
+    uint8_t startLen;      /*!< Length of start condition */
+    uint8_t stopLen;       /*!< Length of stop condition */
+    uint8_t dataPhase0Len; /*!< Length of data phase 0,affecting clock */
+    uint8_t dataPhase1Len; /*!< Length of data phase 1,affecting clock */
+    uint8_t intervalLen;   /*!< Length of interval between frame */
+} SPI_ClockCfg_Type;
+
+/**
+ *  @brief SPI DMA configuration type definition
+ */
+typedef struct
+{
+    uint8_t txFifoThreshold;     /*!< SPI tx FIFO threshold */
+    uint8_t rxFifoThreshold;     /*!< SPI rx FIFO threshold */
+    BL_Fun_Type txFifoDmaEnable; /*!< Enable or disable tx dma req/ack interface */
+    BL_Fun_Type rxFifoDmaEnable; /*!< Enable or disable rx dma req/ack interface */
+} SPI_FifoCfg_Type;
+
+/*@} end of group SPI_Public_Types */
+
+/** @defgroup  SPI_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  SPI_ID_TYPE
+ *  @{
+ */
+#define IS_SPI_ID_TYPE(type) (((type) == SPI_ID_0) || \
+                              ((type) == SPI_ID_MAX))
+
+/** @defgroup  SPI_BYTE_INVERSE_TYPE
+ *  @{
+ */
+#define IS_SPI_BYTE_INVERSE_TYPE(type) (((type) == SPI_BYTE_INVERSE_BYTE0_FIRST) || \
+                                        ((type) == SPI_BYTE_INVERSE_BYTE3_FIRST))
+
+/** @defgroup  SPI_BIT_INVERSE_TYPE
+ *  @{
+ */
+#define IS_SPI_BIT_INVERSE_TYPE(type) (((type) == SPI_BIT_INVERSE_MSB_FIRST) || \
+                                       ((type) == SPI_BIT_INVERSE_LSB_FIRST))
+
+/** @defgroup  SPI_CLK_PHASE_INVERSE_TYPE
+ *  @{
+ */
+#define IS_SPI_CLK_PHASE_INVERSE_TYPE(type) (((type) == SPI_CLK_PHASE_INVERSE_0) || \
+                                             ((type) == SPI_CLK_PHASE_INVERSE_1))
+
+/** @defgroup  SPI_CLK_POLARITY_TYPE
+ *  @{
+ */
+#define IS_SPI_CLK_POLARITY_TYPE(type) (((type) == SPI_CLK_POLARITY_LOW) || \
+                                        ((type) == SPI_CLK_POLARITY_HIGH))
+
+/** @defgroup  SPI_FRAMESIZE_TYPE
+ *  @{
+ */
+#define IS_SPI_FRAMESIZE_TYPE(type) (((type) == SPI_FRAME_SIZE_8) ||  \
+                                     ((type) == SPI_FRAME_SIZE_16) || \
+                                     ((type) == SPI_FRAME_SIZE_24) || \
+                                     ((type) == SPI_FRAME_SIZE_32))
+
+/** @defgroup  SPI_WORK_MODE_TYPE
+ *  @{
+ */
+#define IS_SPI_WORK_MODE_TYPE(type) (((type) == SPI_WORK_MODE_SLAVE) || \
+                                     ((type) == SPI_WORK_MODE_MASTER))
+
+/** @defgroup  SPI_TIMEOUT_TYPE
+ *  @{
+ */
+#define IS_SPI_TIMEOUT_TYPE(type) (((type) == SPI_TIMEOUT_DISABLE) || \
+                                   ((type) == SPI_TIMEOUT_ENABLE))
+
+/** @defgroup  SPI_FIFOSTATUS_TYPE
+ *  @{
+ */
+#define IS_SPI_FIFOSTATUS_TYPE(type) (((type) == SPI_FIFO_TX_OVERFLOW) ||  \
+                                      ((type) == SPI_FIFO_TX_UNDERFLOW) || \
+                                      ((type) == SPI_FIFO_RX_OVERFLOW) ||  \
+                                      ((type) == SPI_FIFO_RX_UNDERFLOW))
+
+/** @defgroup  SPI_INT_TYPE
+ *  @{
+ */
+#define IS_SPI_INT_TYPE(type) (((type) == SPI_INT_END) ||            \
+                               ((type) == SPI_INT_TX_FIFO_REQ) ||    \
+                               ((type) == SPI_INT_RX_FIFO_REQ) ||    \
+                               ((type) == SPI_INT_SLAVE_TIMEOUT) ||  \
+                               ((type) == SPI_INT_SLAVE_UNDERRUN) || \
+                               ((type) == SPI_INT_FIFO_ERROR) ||     \
+                               ((type) == SPI_INT_ALL))
+
+/*@} end of group SPI_Public_Constants */
+
+/** @defgroup  SPI_Public_Macros
+ *  @{
+ */
+#define SPI_RX_FIFO_SIZE 4
+#define SPI_TX_FIFO_SIZE 4
+
+/*@} end of group SPI_Public_Macros */
+
+/** @defgroup  SPI_Public_Functions
+ *  @{
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+void SPI_IRQHandler(void);
+#endif
+BL_Err_Type SPI_Init(SPI_ID_Type spiNo, SPI_CFG_Type *spiCfg);
+BL_Err_Type SPI_DeInit(SPI_ID_Type spiNo);
+BL_Err_Type SPI_SetClock(SPI_ID_Type spiNo, uint32_t clk);
+BL_Err_Type SPI_ClockConfig(SPI_ID_Type spiNo, SPI_ClockCfg_Type *clockCfg);
+BL_Err_Type SPI_FifoConfig(SPI_ID_Type spiNo, SPI_FifoCfg_Type *fifoCfg);
+BL_Err_Type SPI_Enable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType);
+BL_Err_Type SPI_Disable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType);
+BL_Err_Type SPI_SetTimeOutValue(SPI_ID_Type spiNo, uint16_t value);
+BL_Err_Type SPI_SetDeglitchCount(SPI_ID_Type spiNo, uint8_t cnt);
+BL_Err_Type SPI_RxIgnoreEnable(SPI_ID_Type spiNo, uint8_t startPoint, uint8_t stopPoint);
+BL_Err_Type SPI_RxIgnoreDisable(SPI_ID_Type spiNo);
+BL_Err_Type SPI_ClrTxFifo(SPI_ID_Type spiNo);
+BL_Err_Type SPI_ClrRxFifo(SPI_ID_Type spiNo);
+BL_Err_Type SPI_ClrIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType);
+BL_Err_Type SPI_IntMask(SPI_ID_Type spiNo, SPI_INT_Type intType, BL_Mask_Type intMask);
+BL_Err_Type SPI_Int_Callback_Install(SPI_ID_Type spiNo, SPI_INT_Type intType, intCallback_Type *cbFun);
+BL_Err_Type SPI_SendData(SPI_ID_Type spiNo, uint32_t data);
+BL_Err_Type SPI_Send_8bits(SPI_ID_Type spiNo, uint8_t *buff, uint32_t length, SPI_Timeout_Type timeoutType);
+BL_Err_Type SPI_Send_16bits(SPI_ID_Type spiNo, uint16_t *buff, uint32_t length, SPI_Timeout_Type timeoutType);
+BL_Err_Type SPI_Send_24bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType);
+BL_Err_Type SPI_Send_32bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType);
+BL_Err_Type SPI_Recv_8bits(SPI_ID_Type spiNo, uint8_t *buff, uint32_t length, SPI_Timeout_Type timeoutType);
+BL_Err_Type SPI_Recv_16bits(SPI_ID_Type spiNo, uint16_t *buff, uint32_t length, SPI_Timeout_Type timeoutType);
+BL_Err_Type SPI_Recv_24bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType);
+BL_Err_Type SPI_Recv_32bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType);
+BL_Err_Type SPI_SendRecv_8bits(SPI_ID_Type spiNo, uint8_t *sendBuff, uint8_t *recvBuff, uint32_t length,
+                               SPI_Timeout_Type timeoutType);
+BL_Err_Type SPI_SendRecv_16bits(SPI_ID_Type spiNo, uint16_t *sendBuff, uint16_t *recvBuff, uint32_t length,
+                                SPI_Timeout_Type timeoutType);
+BL_Err_Type SPI_SendRecv_24bits(SPI_ID_Type spiNo, uint32_t *sendBuff, uint32_t *recvBuff, uint32_t length,
+                                SPI_Timeout_Type timeoutType);
+BL_Err_Type SPI_SendRecv_32bits(SPI_ID_Type spiNo, uint32_t *sendBuff, uint32_t *recvBuff, uint32_t length,
+                                SPI_Timeout_Type timeoutType);
+uint32_t SPI_ReceiveData(SPI_ID_Type spiNo);
+uint8_t SPI_GetTxFifoCount(SPI_ID_Type spiNo);
+uint8_t SPI_GetRxFifoCount(SPI_ID_Type spiNo);
+BL_Sts_Type SPI_GetIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType);
+BL_Sts_Type SPI_GetFifoStatus(SPI_ID_Type spiNo, SPI_FifoStatus_Type fifoSts);
+BL_Sts_Type SPI_GetBusyStatus(SPI_ID_Type spiNo);
+
+/*@} end of group SPI_Public_Functions */
+
+/*@} end of group SPI */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_SPI_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_timer.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_timer.h
new file mode 100644
index 00000000..4df9ffd9
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_timer.h
@@ -0,0 +1,247 @@
+/**
+  ******************************************************************************
+  * @file    bl702_timer.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_TIMER_H__
+#define __BL702_TIMER_H__
+
+#include "timer_reg.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  TIMER
+ *  @{
+ */
+
+/** @defgroup  TIMER_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief TIMER channel type definition
+ */
+typedef enum {
+    TIMER_CH0,    /*!< TIMER channel 0 port define */
+    TIMER_CH1,    /*!< TIMER channel 1 port define */
+    TIMER_CH_MAX, /*!<  */
+} TIMER_Chan_Type;
+
+/**
+ *  @brief TIMER clock source type definition
+ */
+typedef enum {
+    TIMER_CLKSRC_FCLK, /*!< TIMER clock source :System CLK */
+    TIMER_CLKSRC_32K,  /*!< TIMER clock source :32K CLK */
+    TIMER_CLKSRC_1K,   /*!< TIMER clock source :1K CLK,Only for Timer not for Watchdog */
+    TIMER_CLKSRC_XTAL, /*!< TIMER clock source :XTAL CLK */
+} TIMER_ClkSrc_Type;
+
+/**
+ *  @brief TIMER match compare ID type definition
+ */
+typedef enum {
+    TIMER_COMP_ID_0, /*!< TIMER match compare ID 0 define */
+    TIMER_COMP_ID_1, /*!< TIMER match compare ID 1 define */
+    TIMER_COMP_ID_2, /*!< TIMER match compare ID 2 define */
+} TIMER_Comp_ID_Type;
+
+/**
+ *  @brief TIMER preload source type definition
+ */
+typedef enum {
+    TIMER_PRELOAD_TRIG_NONE,  /*!< TIMER no preload source, just free run */
+    TIMER_PRELOAD_TRIG_COMP0, /*!< TIMER count register preload triggered by comparator 0 */
+    TIMER_PRELOAD_TRIG_COMP1, /*!< TIMER count register preload triggered by comparator 1 */
+    TIMER_PRELOAD_TRIG_COMP2, /*!< TIMER count register preload triggered by comparator 2 */
+} TIMER_PreLoad_Trig_Type;
+
+/**
+ *  @brief TIMER count register run mode type definition
+ */
+typedef enum {
+    TIMER_COUNT_PRELOAD, /*!< TIMER count register preload from comparator register */
+    TIMER_COUNT_FREERUN, /*!< TIMER count register free run */
+} TIMER_CountMode_Type;
+
+/**
+ *  @brief TIMER interrupt type definition
+ */
+typedef enum {
+    TIMER_INT_COMP_0, /*!< Comparator 0 match cause interrupt */
+    TIMER_INT_COMP_1, /*!< Comparator 1 match cause interrupt */
+    TIMER_INT_COMP_2, /*!< Comparator 2 match cause interrupt */
+    TIMER_INT_ALL,    /*!<  */
+} TIMER_INT_Type;
+
+/**
+ *  @brief Watchdog timer interrupt type definition
+ */
+typedef enum {
+    WDT_INT,     /*!< Comparator 0 match cause interrupt */
+    WDT_INT_ALL, /*!<  */
+} WDT_INT_Type;
+
+/**
+ *  @brief TIMER configuration structure type definition
+ */
+typedef struct
+{
+    TIMER_Chan_Type timerCh;           /*!< Timer channel */
+    TIMER_ClkSrc_Type clkSrc;          /*!< Timer clock source */
+    TIMER_PreLoad_Trig_Type plTrigSrc; /*!< Timer count register preload trigger source slelect */
+    TIMER_CountMode_Type countMode;    /*!< Timer count mode */
+    uint8_t clockDivision;             /*!< Timer clock divison value */
+    uint32_t matchVal0;                /*!< Timer match 0 value 0 */
+    uint32_t matchVal1;                /*!< Timer match 1 value 0 */
+    uint32_t matchVal2;                /*!< Timer match 2 value 0 */
+    uint32_t preLoadVal;               /*!< Timer preload value */
+} TIMER_CFG_Type;
+
+/*@} end of group TIMER_Public_Types */
+
+/** @defgroup  TIMER_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  TIMER_CHAN_TYPE
+ *  @{
+ */
+#define IS_TIMER_CHAN_TYPE(type) (((type) == TIMER_CH0) || \
+                                  ((type) == TIMER_CH1) || \
+                                  ((type) == TIMER_CH_MAX))
+
+/** @defgroup  TIMER_CLKSRC_TYPE
+ *  @{
+ */
+#define IS_TIMER_CLKSRC_TYPE(type) (((type) == TIMER_CLKSRC_FCLK) || \
+                                    ((type) == TIMER_CLKSRC_32K) ||  \
+                                    ((type) == TIMER_CLKSRC_1K) ||   \
+                                    ((type) == TIMER_CLKSRC_XTAL))
+
+/** @defgroup  TIMER_COMP_ID_TYPE
+ *  @{
+ */
+#define IS_TIMER_COMP_ID_TYPE(type) (((type) == TIMER_COMP_ID_0) || \
+                                     ((type) == TIMER_COMP_ID_1) || \
+                                     ((type) == TIMER_COMP_ID_2))
+
+/** @defgroup  TIMER_PRELOAD_TRIG_TYPE
+ *  @{
+ */
+#define IS_TIMER_PRELOAD_TRIG_TYPE(type) (((type) == TIMER_PRELOAD_TRIG_NONE) ||  \
+                                          ((type) == TIMER_PRELOAD_TRIG_COMP0) || \
+                                          ((type) == TIMER_PRELOAD_TRIG_COMP1) || \
+                                          ((type) == TIMER_PRELOAD_TRIG_COMP2))
+
+/** @defgroup  TIMER_COUNTMODE_TYPE
+ *  @{
+ */
+#define IS_TIMER_COUNTMODE_TYPE(type) (((type) == TIMER_COUNT_PRELOAD) || \
+                                       ((type) == TIMER_COUNT_FREERUN))
+
+/** @defgroup  TIMER_INT_TYPE
+ *  @{
+ */
+#define IS_TIMER_INT_TYPE(type) (((type) == TIMER_INT_COMP_0) || \
+                                 ((type) == TIMER_INT_COMP_1) || \
+                                 ((type) == TIMER_INT_COMP_2) || \
+                                 ((type) == TIMER_INT_ALL))
+
+/** @defgroup  WDT_INT_TYPE
+ *  @{
+ */
+#define IS_WDT_INT_TYPE(type) (((type) == WDT_INT) || \
+                               ((type) == WDT_INT_ALL))
+
+/*@} end of group TIMER_Public_Constants */
+
+/** @defgroup  TIMER_Public_Macros
+ *  @{
+ */
+#define WDT_ENABLE_ACCESS()                                                                                            \
+    {                                                                                                                  \
+        BL_WR_REG(TIMER_BASE, TIMER_WFAR, BL_SET_REG_BITS_VAL(BL_RD_REG(TIMER_BASE, TIMER_WFAR), TIMER_WFAR, 0xBABA)); \
+        BL_WR_REG(TIMER_BASE, TIMER_WSAR, BL_SET_REG_BITS_VAL(BL_RD_REG(TIMER_BASE, TIMER_WSAR), TIMER_WSAR, 0xEB10)); \
+    }
+
+/*@} end of group TIMER_Public_Macros */
+
+/** @defgroup  TIMER_Public_Functions
+ *  @{
+ */
+
+/**
+ *  @brief UART Functions
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+void TIMER_CH0_IRQHandler(void);
+void TIMER_CH1_IRQHandler(void);
+void TIMER_WDT_IRQHandler(void);
+#endif
+BL_Err_Type TIMER_Init(TIMER_CFG_Type *timerCfg);
+uint32_t TIMER_GetCompValue(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo);
+void TIMER_SetCompValue(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo, uint32_t val);
+uint32_t TIMER_GetCounterValue(TIMER_Chan_Type timerCh);
+BL_Sts_Type TIMER_GetMatchStatus(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo);
+uint32_t TIMER_GetPreloadValue(TIMER_Chan_Type timerCh);
+void TIMER_SetPreloadValue(TIMER_Chan_Type timerCh, uint32_t val);
+void TIMER_SetPreloadSrc(TIMER_Chan_Type timerCh, TIMER_PreLoad_Trig_Type plSrc);
+void TIMER_SetCountMode(TIMER_Chan_Type timerCh, TIMER_CountMode_Type countMode);
+void TIMER_ClearIntStatus(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo);
+void TIMER_Enable(TIMER_Chan_Type timerCh);
+void TIMER_Disable(TIMER_Chan_Type timerCh);
+void TIMER_IntMask(TIMER_Chan_Type timerCh, TIMER_INT_Type intType, BL_Mask_Type intMask);
+void WDT_Set_Clock(TIMER_ClkSrc_Type clkSrc, uint8_t div);
+uint16_t WDT_GetMatchValue(void);
+void WDT_SetCompValue(uint16_t val);
+uint16_t WDT_GetCounterValue(void);
+void WDT_ResetCounterValue(void);
+BL_Sts_Type WDT_GetResetStatus(void);
+void WDT_ClearResetStatus(void);
+void WDT_Enable(void);
+void WDT_Disable(void);
+void WDT_IntMask(WDT_INT_Type intType, BL_Mask_Type intMask);
+void Timer_Int_Callback_Install(TIMER_Chan_Type timerChan, TIMER_INT_Type intType, intCallback_Type *cbFun);
+void WDT_Int_Callback_Install(WDT_INT_Type wdtInt, intCallback_Type *cbFun);
+
+/*@} end of group TIMER_Public_Functions */
+
+/*@} end of group TIMER */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_TIMER_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_uart.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_uart.h
new file mode 100644
index 00000000..10f8e2ef
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_uart.h
@@ -0,0 +1,326 @@
+/**
+  ******************************************************************************
+  * @file    bl702_uart.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_UART_H__
+#define __BL702_UART_H__
+
+#include "uart_reg.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  UART
+ *  @{
+ */
+
+/** @defgroup  UART_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief UART port type definition
+ */
+typedef enum {
+    UART0_ID,    /*!< UART0 port define */
+    UART1_ID,    /*!< UART1 port define */
+    UART_ID_MAX, /*!< UART MAX ID define */
+} UART_ID_Type;
+
+/**
+ *  @brief UART direction type definition
+ */
+typedef enum {
+    UART_TX,   /*!< UART TX Direction */
+    UART_RX,   /*!< UART RX Direction */
+    UART_TXRX, /*!< UART TX and RX Direction */
+} UART_Direction_Type;
+
+/**
+ *  @brief UART parity type definition
+ */
+typedef enum {
+    UART_PARITY_NONE, /*!< UART parity none define */
+    UART_PARITY_ODD,  /*!< UART parity odd define */
+    UART_PARITY_EVEN, /*!< UART parity even define */
+} UART_Parity_Type;
+
+/**
+ *  @brief UART data bits type definiton
+ */
+typedef enum {
+    UART_DATABITS_5, /*!< UART data bits length:5 bits */
+    UART_DATABITS_6, /*!< UART data bits length:6 bits */
+    UART_DATABITS_7, /*!< UART data bits length:7 bits */
+    UART_DATABITS_8, /*!< UART data bits length:8 bits */
+} UART_DataBits_Type;
+
+/**
+ *  @brief UART stop bits type definiton
+ */
+typedef enum {
+    UART_STOPBITS_0_5, /*!< UART data stop bits length:0.5 bits */
+    UART_STOPBITS_1,   /*!< UART data stop bits length:1 bits */
+    UART_STOPBITS_1_5, /*!< UART data stop bits length:1.5 bits */
+    UART_STOPBITS_2,   /*!< UART data stop bits length:2 bits */
+} UART_StopBits_Type;
+
+/**
+ *  @brief UART each data byte is send out LSB-first or MSB-first type definiton
+ */
+typedef enum {
+    UART_LSB_FIRST, /*!< UART each byte is send out LSB-first */
+    UART_MSB_FIRST, /*!< UART each byte is send out MSB-first */
+} UART_ByteBitInverse_Type;
+
+/**
+ *  @brief UART auto baudrate detection using codeword 0x55 or start bit definiton
+ */
+typedef enum {
+    UART_AUTOBAUD_0X55,     /*!< UART auto baudrate detection using codeword 0x55 */
+    UART_AUTOBAUD_STARTBIT, /*!< UART auto baudrate detection using start bit */
+} UART_AutoBaudDetection_Type;
+
+/**
+ *  @brief UART interrupt type definition
+ */
+typedef enum {
+    UART_INT_TX_END,      /*!< UART tx transfer end interrupt */
+    UART_INT_RX_END,      /*!< UART rx transfer end interrupt */
+    UART_INT_TX_FIFO_REQ, /*!< UART tx fifo interrupt when tx fifo count reaches,auto clear */
+    UART_INT_RX_FIFO_REQ, /*!< UART rx fifo interrupt when rx fifo count reaches,auto clear */
+    UART_INT_RTO,         /*!< UART rx time-out interrupt */
+    UART_INT_PCE,         /*!< UART rx parity check error interrupt */
+    UART_INT_TX_FER,      /*!< UART tx fifo overflow/underflow error interrupt */
+    UART_INT_RX_FER,      /*!< UART rx fifo overflow/underflow error interrupt */
+    UART_INT_LSE,         /*!< UART rx lin mode sync field error interrupt */
+    UART_INT_ALL,         /*!< All the interrupt */
+} UART_INT_Type;
+
+/**
+ *  @brief UART overflow or underflow type definition
+ */
+typedef enum {
+    UART_TX_OVERFLOW,  /*!< UART tx fifo overflow */
+    UART_TX_UNDERFLOW, /*!< UART tx fifo underflow */
+    UART_RX_OVERFLOW,  /*!< UART rx fifo overflow */
+    UART_RX_UNDERFLOW, /*!< UART rx fifo underflow */
+} UART_Overflow_Type;
+
+/**
+ *  @brief UART configuration structure type definition
+ */
+typedef struct
+{
+    uint32_t uartClk;                        /*!< Uart module clock */
+    uint32_t baudRate;                       /*!< Uart baudrate */
+    UART_DataBits_Type dataBits;             /*!< Uart frame length of data bit */
+    UART_StopBits_Type stopBits;             /*!< Uart frame length of stop bit */
+    UART_Parity_Type parity;                 /*!< Uart parity check type */
+    BL_Fun_Type ctsFlowControl;              /*!< Enable or disable tx CTS flow control */
+    BL_Fun_Type rxDeglitch;                  /*!< Enable or disable rx input de-glitch function */
+    BL_Fun_Type rtsSoftwareControl;          /*!< Enable or disable rx RTS output SW control mode */
+    BL_Fun_Type txSoftwareControl;           /*!< Enable or disable tx output SW control mode */
+    BL_Fun_Type txLinMode;                   /*!< Enable or disable tx LIN mode,LIN header will be sent before sending data */
+    BL_Fun_Type rxLinMode;                   /*!< Enable or disable rx LIN mode,LIN header will be required and checked before receiving data */
+    uint8_t txBreakBitCnt;                   /*!< Uart tx break bit count,additional 8 bit times will be added since LIN break field requires at
+                                                 least 13 bit times */
+    UART_ByteBitInverse_Type byteBitInverse; /*!< Uart each data byte is send out LSB-first or MSB-first */
+} UART_CFG_Type;
+
+/**
+ *  @brief UART FIFO configuration structure type definition
+ */
+typedef struct
+{
+    uint8_t txFifoDmaThreshold;  /*!< TX FIFO threshold, dma tx request will not be asserted if tx fifo count is less than this value */
+    uint8_t rxFifoDmaThreshold;  /*!< RX FIFO threshold, dma rx request will not be asserted if rx fifo count is less than this value */
+    BL_Fun_Type txFifoDmaEnable; /*!< Enable or disable tx dma req/ack interface */
+    BL_Fun_Type rxFifoDmaEnable; /*!< Enable or disable rx dma req/ack interface */
+} UART_FifoCfg_Type;
+
+/**
+ *  @brief UART infrared configuration structure type definition
+ */
+typedef struct
+{
+    BL_Fun_Type txIrEnable;  /*!< Enable or disable uart tx ir mode */
+    BL_Fun_Type rxIrEnable;  /*!< Enable or disable uart rx ir mode */
+    BL_Fun_Type txIrInverse; /*!< Enable or disable inverse signal of uart tx output in ir mode */
+    BL_Fun_Type rxIrInverse; /*!< Enable or disable inverse signal of uart rx input in ir mode */
+    uint16_t txIrPulseStart; /*!< Set start position of uart tx ir pulse */
+    uint16_t txIrPulseStop;  /*!< Set stop position of uart tx ir pulse */
+    uint16_t rxIrPulseStart; /*!< Set start position of uart rx pulse recovered from ir signal */
+} UART_IrCfg_Type;
+
+/*@} end of group UART_Public_Types */
+
+/** @defgroup  UART_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  UART_ID_TYPE
+ *  @{
+ */
+#define IS_UART_ID_TYPE(type) (((type) == UART0_ID) || \
+                               ((type) == UART1_ID) || \
+                               ((type) == UART_ID_MAX))
+
+/** @defgroup  UART_DIRECTION_TYPE
+ *  @{
+ */
+#define IS_UART_DIRECTION_TYPE(type) (((type) == UART_TX) || \
+                                      ((type) == UART_RX) || \
+                                      ((type) == UART_TXRX))
+
+/** @defgroup  UART_PARITY_TYPE
+ *  @{
+ */
+#define IS_UART_PARITY_TYPE(type) (((type) == UART_PARITY_NONE) || \
+                                   ((type) == UART_PARITY_ODD) ||  \
+                                   ((type) == UART_PARITY_EVEN))
+
+/** @defgroup  UART_DATABITS_TYPE
+ *  @{
+ */
+#define IS_UART_DATABITS_TYPE(type) (((type) == UART_DATABITS_5) || \
+                                     ((type) == UART_DATABITS_6) || \
+                                     ((type) == UART_DATABITS_7) || \
+                                     ((type) == UART_DATABITS_8))
+
+/** @defgroup  UART_STOPBITS_TYPE
+ *  @{
+ */
+#define IS_UART_STOPBITS_TYPE(type) (((type) == UART_STOPBITS_1) ||   \
+                                     ((type) == UART_STOPBITS_1_5) || \
+                                     ((type) == UART_STOPBITS_2))
+
+/** @defgroup  UART_BYTEBITINVERSE_TYPE
+ *  @{
+ */
+#define IS_UART_BYTEBITINVERSE_TYPE(type) (((type) == UART_LSB_FIRST) || \
+                                           ((type) == UART_MSB_FIRST))
+
+/** @defgroup  UART_AUTOBAUDDETECTION_TYPE
+ *  @{
+ */
+#define IS_UART_AUTOBAUDDETECTION_TYPE(type) (((type) == UART_AUTOBAUD_0X55) || \
+                                              ((type) == UART_AUTOBAUD_STARTBIT))
+
+/** @defgroup  UART_INT_TYPE
+ *  @{
+ */
+#define IS_UART_INT_TYPE(type) (((type) == UART_INT_TX_END) ||      \
+                                ((type) == UART_INT_RX_END) ||      \
+                                ((type) == UART_INT_TX_FIFO_REQ) || \
+                                ((type) == UART_INT_RX_FIFO_REQ) || \
+                                ((type) == UART_INT_RTO) ||         \
+                                ((type) == UART_INT_PCE) ||         \
+                                ((type) == UART_INT_TX_FER) ||      \
+                                ((type) == UART_INT_RX_FER) ||      \
+                                ((type) == UART_INT_LSE) ||         \
+                                ((type) == UART_INT_ALL))
+
+/** @defgroup  UART_OVERFLOW_TYPE
+ *  @{
+ */
+#define IS_UART_OVERFLOW_TYPE(type) (((type) == UART_TX_OVERFLOW) ||  \
+                                     ((type) == UART_TX_UNDERFLOW) || \
+                                     ((type) == UART_RX_OVERFLOW) ||  \
+                                     ((type) == UART_RX_UNDERFLOW))
+
+/*@} end of group UART_Public_Constants */
+
+/** @defgroup  UART_Public_Macros
+ *  @{
+ */
+#define UART_RX_FIFO_SIZE         128
+#define UART_TX_FIFO_SIZE         128
+#define UART_DEFAULT_RECV_TIMEOUT 80
+
+/*@} end of group UART_Public_Macros */
+
+/** @defgroup  UART_Public_Functions
+ *  @{
+ */
+
+/**
+ *  @brief UART Functions
+ */
+#if (!defined BFLB_USE_HAL_DRIVER) || (defined BFLB_EFLASH_LOADER)
+void UART0_IRQHandler(void);
+void UART1_IRQHandler(void);
+#endif
+BL_Err_Type UART_Init(UART_ID_Type uartId, UART_CFG_Type *uartCfg);
+BL_Err_Type UART_DeInit(UART_ID_Type uartId);
+BL_Err_Type UART_FifoConfig(UART_ID_Type uartId, UART_FifoCfg_Type *fifoCfg);
+BL_Err_Type UART_IrConfig(UART_ID_Type uartId, UART_IrCfg_Type *irCfg);
+BL_Err_Type UART_Enable(UART_ID_Type uartId, UART_Direction_Type direct);
+BL_Err_Type UART_Disable(UART_ID_Type uartId, UART_Direction_Type direct);
+BL_Err_Type UART_SetTxDataLength(UART_ID_Type uartId, uint16_t length);
+BL_Err_Type UART_SetRxDataLength(UART_ID_Type uartId, uint16_t length);
+BL_Err_Type UART_SetRxTimeoutValue(UART_ID_Type uartId, uint8_t time);
+BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId, uint8_t deglitchCnt);
+BL_Err_Type UART_ApplyAbrResult(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet);
+BL_Err_Type UART_SetRtsValue(UART_ID_Type uartId);
+BL_Err_Type UART_ClrRtsValue(UART_ID_Type uartId);
+BL_Err_Type UART_SetTxValue(UART_ID_Type uartId);
+BL_Err_Type UART_ClrTxValue(UART_ID_Type uartId);
+BL_Err_Type UART_TxFreeRun(UART_ID_Type uartId, BL_Fun_Type txFreeRun);
+BL_Err_Type UART_AutoBaudDetection(UART_ID_Type uartId, BL_Fun_Type autoBaud);
+BL_Err_Type UART_TxFifoClear(UART_ID_Type uartId);
+BL_Err_Type UART_RxFifoClear(UART_ID_Type uartId);
+BL_Err_Type UART_IntMask(UART_ID_Type uartId, UART_INT_Type intType, BL_Mask_Type intMask);
+BL_Err_Type UART_IntClear(UART_ID_Type uartId, UART_INT_Type intType);
+BL_Err_Type UART_Int_Callback_Install(UART_ID_Type uartId, UART_INT_Type intType, intCallback_Type *cbFun);
+BL_Err_Type UART_SendData(UART_ID_Type uartId, uint8_t *data, uint32_t len);
+BL_Err_Type UART_SendDataBlock(UART_ID_Type uartId, uint8_t *data, uint32_t len);
+uint32_t UART_ReceiveData(UART_ID_Type uartId, uint8_t *data, uint32_t maxLen);
+uint16_t UART_GetAutoBaudCount(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet);
+uint8_t UART_GetTxFifoCount(UART_ID_Type uartId);
+uint8_t UART_GetRxFifoCount(UART_ID_Type uartId);
+BL_Sts_Type UART_GetIntStatus(UART_ID_Type uartId, UART_INT_Type intType);
+BL_Sts_Type UART_GetTxBusBusyStatus(UART_ID_Type uartId);
+BL_Sts_Type UART_GetRxBusBusyStatus(UART_ID_Type uartId);
+BL_Sts_Type UART_GetOverflowStatus(UART_ID_Type uartId, UART_Overflow_Type overflow);
+
+/*@} end of group UART_Public_Functions */
+
+/*@} end of group UART */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_UART_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_usb.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_usb.h
new file mode 100644
index 00000000..c7c55d49
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_usb.h
@@ -0,0 +1,423 @@
+/**
+  ******************************************************************************
+  * @file    bl702_usb.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_USB_H__
+#define __BL702_USB_H__
+
+#include "usb_reg.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  USB
+ *  @{
+ */
+
+/** @defgroup  USB_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief USB end point ID
+ */
+typedef enum {
+    EP_ID0 = 0, /*!< USB end point 0 */
+    EP_ID1,     /*!< USB end point 1 */
+    EP_ID2,     /*!< USB end point 2 */
+    EP_ID3,     /*!< USB end point 3 */
+    EP_ID4,     /*!< USB end point 4 */
+    EP_ID5,     /*!< USB end point 5 */
+    EP_ID6,     /*!< USB end point 6 */
+    EP_ID7,     /*!< USB end point 7 */
+} USB_EP_ID;
+
+/**
+ *  @brief USB end point type
+ */
+typedef enum {
+    EP_INT = 0,  /*!< interrupt transfer ep */
+    EP_ISO = 2,  /*!< isochronous transfer ep */
+    EP_BULK = 4, /*!< bulk transfer ep */
+    EP_CTRL = 5, /*!< control transfer ep */
+} EP_XFER_Type;
+
+/**
+ *  @brief USB end point transfer directions
+ */
+typedef enum {
+    EP_DISABLED = 0, /*!< end point disabled */
+    EP_IN = 1,       /*!< IN end point,device to host */
+    EP_OUT = 2,      /*!< OUT end point ,host to device */
+} EP_XFER_DIR;
+
+typedef enum {
+    USB_INT_SOF = 0,
+    USB_INT_RESET,
+    USB_INT_VBUS_TGL,
+    USB_INT_GET_DCT_CMD,
+    USB_INT_EP0_SETUP_CMD,
+    USB_INT_EP0_SETUP_DONE,
+    USB_INT_EP0_IN_CMD,
+    USB_INT_EP0_IN_DONE,
+    USB_INT_EP0_OUT_CMD,
+    USB_INT_EP0_OUT_DONE,
+    USB_INT_EP1_CMD,
+    USB_INT_EP1_DONE,
+    USB_INT_EP2_CMD,
+    USB_INT_EP2_DONE,
+    USB_INT_EP3_CMD,
+    USB_INT_EP3_DONE,
+    USB_INT_EP4_CMD,
+    USB_INT_EP4_DONE,
+    USB_INT_EP5_CMD,
+    USB_INT_EP5_DONE,
+    USB_INT_EP6_CMD,
+    USB_INT_EP6_DONE,
+    USB_INT_EP7_CMD,
+    USB_INT_EP7_DONE,
+    USB_INT_RESET_END = 27,
+    USB_INT_LPM_WAKEUP = 28,
+    USB_INT_LPM_PACKET = 29,
+    USB_INT_LOST_SOF_3_TIMES = 30,
+    USB_INT_ERROR = 31,
+    USB_INT_ALL = 32, /* special */
+} USB_INT_Type;
+
+typedef enum {
+    USB_FIFO_EMPTY = 0,
+    USB_FIFO_FULL,
+} USB_FIFO_STATUS_Type;
+
+typedef enum {
+    USB_FIFO_ERROR_OVERFLOW = 0,
+    USB_FIFO_ERROR_UNDERFLOW,
+} USB_FIFO_ERROR_FLAG_Type;
+
+typedef enum {
+    USB_EP_STATUS_ACK = 0,
+    USB_EP_STATUS_NACK,
+    USB_EP_STATUS_STALL,
+    USB_EP_STATUS_NSTALL,
+} USB_EP_STATUS_Type;
+
+typedef enum {
+    USB_LPM_DEFAULT_RESP_ACK = 0,
+    USB_LPM_DEFAULT_RESP_NACK,
+    USB_LPM_DEFAULT_RESP_STALL,
+    USB_LPM_DEFAULT_RESP_NYET,
+} USB_LPM_DEFAULT_RESP_Type;
+
+typedef enum {
+    USB_ERROR_UTMI_RX = 0,
+    USB_ERROR_XFER_TO,
+    USB_ERROR_IVLD_EP,
+    USB_ERROR_PID_SEQ,
+    USB_ERROR_PID_CKS,
+    USB_ERROR_CRC5,
+    USB_ERROR_CRC16,
+} USB_ERROR_Type;
+
+/**
+ *  @brief USB configuration structure type definition
+ */
+typedef struct
+{
+    BL_Fun_Type EnumOutEn;             /*!< EP0 IN direction enable or disable */
+    BL_Fun_Type EnumInEn;              /*!< EP0 OUT direction enable or disable */
+    uint8_t EnumMaxPacketSize;         /*!< EP0 max packet size, only valid when SoftwareCtrl is set */
+    uint8_t DeviceAddress;             /*!< Device(EP0) address, only valid when SoftwareCtrl is set */
+    BL_Fun_Type SoftwareCtrl;          /*!< EP0 software control enable */
+    BL_Fun_Type RomBaseDescriptorUsed; /*!< Enable signal of ROM-based descriptors (don't care if SoftwareCtrl is set) */
+} USB_Config_Type;
+
+/**
+ *  @brief end point configuration structure type definition
+ */
+typedef struct
+{
+    uint16_t EPMaxPacketSize; /*!< Endpoint max packet size */
+    EP_XFER_DIR dir;          /*!< Endpoint direction */
+    EP_XFER_Type type;        /*!< Endpoint type */
+} EP_Config_Type;
+
+typedef struct
+{
+    uint32_t cr_ep_size     : 9;
+    uint32_t cr_ep_dir      : 2;
+    uint32_t cr_ep_type     : 3;
+    uint32_t cr_ep_stall    : 1;
+    uint32_t cr_ep_nack     : 1;
+    uint32_t cr_ep_rdy      : 1;
+    uint32_t reserved_17_31 : 15;
+} usb_reg_epx_config_t;
+
+typedef struct
+{
+    uint32_t ep_dma_tx_en         : 1;
+    uint32_t ep_dma_rx_en         : 1;
+    uint32_t ep_tx_fifo_clr       : 1;
+    uint32_t ep_rx_fifo_clr       : 1;
+    uint32_t ep_tx_fifo_overflow  : 1;
+    uint32_t ep_tx_fifo_underflow : 1;
+    uint32_t ep_rx_fifo_overflow  : 1;
+    uint32_t ep_rx_fifo_underflow : 1;
+    uint32_t reserved_8_31        : 24;
+} usb_reg_epx_fifo_config_t;
+
+typedef struct
+{
+    uint32_t ep_tx_fifo_cnt   : 7;
+    uint32_t reserved_7_13    : 7;
+    uint32_t ep_tx_fifo_empty : 1;
+    uint32_t ep_tx_fifo_full  : 1;
+    uint32_t ep_rx_fifo_cnt   : 7;
+    uint32_t reserved_23_29   : 7;
+    uint32_t ep_rx_fifo_empty : 1;
+    uint32_t ep_rx_fifo_full  : 1;
+} usb_reg_epx_fifo_status_t;
+
+typedef struct
+{
+    uint32_t fifo          : 8;
+    uint32_t reserved_8_31 : 24;
+} usb_reg_epx_fifo_t;
+
+/*@} end of group USB_Public_Types */
+
+/** @defgroup  USB_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  USB_EP_ID
+ *  @{
+ */
+#define IS_USB_EP_ID(type) (((type) == EP_ID0) || \
+                            ((type) == EP_ID1) || \
+                            ((type) == EP_ID2) || \
+                            ((type) == EP_ID3) || \
+                            ((type) == EP_ID4) || \
+                            ((type) == EP_ID5) || \
+                            ((type) == EP_ID6) || \
+                            ((type) == EP_ID7))
+
+/** @defgroup  EP_XFER_TYPE
+ *  @{
+ */
+#define IS_EP_XFER_TYPE(type) (((type) == EP_INT) ||  \
+                               ((type) == EP_ISO) ||  \
+                               ((type) == EP_CTRL) || \
+                               ((type) == EP_BULK))
+
+/** @defgroup  EP_XFER_DIR
+ *  @{
+ */
+#define IS_EP_XFER_DIR(type) (((type) == EP_DISABLED) || \
+                              ((type) == EP_IN) ||       \
+                              ((type) == EP_OUT))
+
+/*@} end of group USB_Public_Constants */
+
+/** @defgroup  USB_Public_Macros
+ *  @{
+ */
+#define USB_INT_TYPE_SOF              0x00000001
+#define USB_INT_TYPE_RESET            0x00000002
+#define USB_INT_TYPE_GET_DCT_CMD      0x00000008
+#define USB_INT_TYPE_EP0_SETUP_CMD    0x00000010
+#define USB_INT_TYPE_EP0_SETUP_DONE   0x00000020
+#define USB_INT_TYPE_EP0_IN_CMD       0x00000040
+#define USB_INT_TYPE_EP0_IN_DONE      0x00000080
+#define USB_INT_TYPE_EP0_OUT_CMD      0x00000100
+#define USB_INT_TYPE_EP0_OUT_DONE     0x00000200
+#define USB_INT_TYPE_EP1_CMD          0x00000400
+#define USB_INT_TYPE_EP1_DONE         0x00000800
+#define USB_INT_TYPE_EP2_CMD          0x00001000
+#define USB_INT_TYPE_EP2_DONE         0x00002000
+#define USB_INT_TYPE_EP3_CMD          0x00004000
+#define USB_INT_TYPE_EP3_DONE         0x00008000
+#define USB_INT_TYPE_EP4_CMD          0x00010000
+#define USB_INT_TYPE_EP4_DONE         0x00020000
+#define USB_INT_TYPE_EP5_CMD          0x00040000
+#define USB_INT_TYPE_EP5_DONE         0x00080000
+#define USB_INT_TYPE_EP6_CMD          0x00100000
+#define USB_INT_TYPE_EP6_DONE         0x00200000
+#define USB_INT_TYPE_EP7_CMD          0x00400000
+#define USB_INT_TYPE_EP7_DONE         0x00800000
+#define USB_INT_TYPE_RESET_END        0x08000000
+#define USB_INT_TYPE_LPM_WAKEUP       0x10000000
+#define USB_INT_TYPE_LPM_PACKET       0x20000000
+#define USB_INT_TYPE_LOST_SOF_3_TIMES 0x40000000
+#define USB_INT_TYPE_ERROR            0x80000000
+#define USB_INT_TYPE_ALL              (USB_INT_TYPE_SOF | \
+                          USB_INT_TYPE_RESET |            \
+                          USB_INT_TYPE_GET_DCT_CMD |      \
+                          USB_INT_TYPE_EP0_SETUP_CMD |    \
+                          USB_INT_TYPE_EP0_SETUP_DONE |   \
+                          USB_INT_TYPE_EP0_IN_CMD |       \
+                          USB_INT_TYPE_EP0_IN_DONE |      \
+                          USB_INT_TYPE_EP0_OUT_CMD |      \
+                          USB_INT_TYPE_EP0_OUT_DONE |     \
+                          USB_INT_TYPE_EP1_CMD |          \
+                          USB_INT_TYPE_EP1_DONE |         \
+                          USB_INT_TYPE_EP2_CMD |          \
+                          USB_INT_TYPE_EP2_DONE |         \
+                          USB_INT_TYPE_EP3_CMD |          \
+                          USB_INT_TYPE_EP3_DONE |         \
+                          USB_INT_TYPE_EP4_CMD |          \
+                          USB_INT_TYPE_EP4_DONE |         \
+                          USB_INT_TYPE_EP5_CMD |          \
+                          USB_INT_TYPE_EP5_DONE |         \
+                          USB_INT_TYPE_EP6_CMD |          \
+                          USB_INT_TYPE_EP6_DONE |         \
+                          USB_INT_TYPE_EP7_CMD |          \
+                          USB_INT_TYPE_EP7_DONE |         \
+                          USB_INT_TYPE_RESET_END |        \
+                          USB_INT_TYPE_LPM_WAKEUP |       \
+                          USB_INT_TYPE_LPM_PACKET |       \
+                          USB_INT_TYPE_LOST_SOF_3_TIMES | \
+                          USB_INT_TYPE_ERROR)
+
+#define USB_EP_TX_FIFO_EMPTY    0x00004000
+#define USB_EP_TX_FIFO_FULL     0x00008000
+#define USB_EP_RX_FIFO_EMPTY    0x40000000
+#define USB_EP_RX_FIFO_FULL     0x80000000
+#define USB_EP_FIFO_STATUS_MASK (USB_EP_TX_FIFO_EMPTY | \
+                                 USB_EP_TX_FIFO_FULL |  \
+                                 USB_EP_RX_FIFO_EMPTY | \
+                                 USB_EP_RX_FIFO_FULL)
+#define USB_EP_TX_FIFO_OVERFLOW  0x00000010
+#define USB_EP_TX_FIFO_UNDERFLOW 0x00000020
+#define USB_EP_RX_FIFO_OVERFLOW  0x00000040
+#define USB_EP_RX_FIFO_UNDERLOW  0x00000080
+#define USB_EP_FIFO_ERROR_MASK   (USB_EP_TX_FIFO_OVERFLOW | \
+                                USB_EP_TX_FIFO_UNDERFLOW |  \
+                                USB_EP_RX_FIFO_OVERFLOW |   \
+                                USB_EP_RX_FIFO_UNDERLOW)
+
+#define EP_ID_MAX 8
+
+/*@} end of group USB_Public_Macros */
+
+/** @defgroup  USB_Public_Functions
+ *  @{
+ */
+
+/**
+ *  @brief USB Functions
+ */
+
+/*----------*/
+#ifndef BFLB_USE_HAL_DRIVER
+void USB_IRQHandler(void);
+#endif
+/*----------*/
+BL_Err_Type USB_Enable(void);
+BL_Err_Type USB_Disable(void);
+BL_Err_Type USB_Set_Config(BL_Fun_Type enable, USB_Config_Type *usbCfg);
+BL_Err_Type USB_Set_Device_Addr(uint8_t addr);
+uint8_t USB_Get_Device_Addr(void);
+/*----------*/
+BL_Err_Type USB_Set_EPx_Xfer_Size(USB_EP_ID epId, uint8_t size);
+BL_Err_Type USB_Set_EPx_IN_Busy(USB_EP_ID epId);
+BL_Err_Type USB_Set_EPx_IN_Stall(USB_EP_ID epId);
+BL_Err_Type USB_Set_EPx_OUT_Busy(USB_EP_ID epId);
+BL_Err_Type USB_Set_EPx_OUT_Stall(USB_EP_ID epId);
+BL_Err_Type USB_Set_EPx_Rdy(USB_EP_ID epId);
+BL_Sts_Type USB_Is_EPx_RDY_Free(USB_EP_ID epId);
+BL_Err_Type USB_Set_EPx_STALL(USB_EP_ID epId);
+BL_Err_Type USB_Clr_EPx_STALL(USB_EP_ID epId);
+BL_Err_Type USB_Set_EPx_Busy(USB_EP_ID epId);
+BL_Err_Type USB_Set_EPx_Status(USB_EP_ID epId, USB_EP_STATUS_Type sts);
+USB_EP_STATUS_Type USB_Get_EPx_Status(USB_EP_ID epId);
+/*----------*/
+BL_Err_Type USB_IntEn(USB_INT_Type intType, uint8_t enable);
+BL_Err_Type USB_IntMask(USB_INT_Type intType, BL_Mask_Type intMask);
+BL_Sts_Type USB_Get_IntStatus(USB_INT_Type intType);
+BL_Err_Type USB_Clr_IntStatus(USB_INT_Type intType);
+BL_Err_Type USB_Clr_EPx_IntStatus(USB_EP_ID epId);
+/*----------*/
+uint16_t USB_Get_Frame_Num(void);
+/*----------*/
+BL_Err_Type USB_Set_EPx_Config(USB_EP_ID epId, EP_Config_Type *epCfg);
+BL_Err_Type USB_Set_EPx_Type(USB_EP_ID epId, EP_XFER_Type type);
+EP_XFER_Type USB_Get_EPx_Type(USB_EP_ID epId);
+BL_Err_Type USB_Set_EPx_Dir(USB_EP_ID epId, EP_XFER_DIR dir);
+EP_XFER_DIR USB_Get_EPx_Dir(USB_EP_ID epId);
+BL_Err_Type USB_Set_EPx_Size(USB_EP_ID epId, uint32_t size);
+/*----------*/
+BL_Sts_Type USB_Get_EPx_TX_FIFO_Errors(USB_EP_ID epId, USB_FIFO_ERROR_FLAG_Type errFlag);
+BL_Sts_Type USB_Get_EPx_RX_FIFO_Errors(USB_EP_ID epId, USB_FIFO_ERROR_FLAG_Type errFlag);
+BL_Err_Type USB_Clr_EPx_TX_FIFO_Errors(USB_EP_ID epId);
+BL_Err_Type USB_Clr_EPx_RX_FIFO_Errors(USB_EP_ID epId);
+/*----------*/
+BL_Err_Type USB_EPx_Write_Data_To_FIFO(USB_EP_ID epId, uint8_t *pData, uint16_t len);
+BL_Err_Type USB_EPx_Read_Data_From_FIFO(USB_EP_ID epId, uint8_t *pBuff, uint16_t len);
+/*----------*/
+BL_Err_Type USB_Set_EPx_TX_DMA_Interface_Config(USB_EP_ID epId, BL_Fun_Type newState);
+BL_Err_Type USB_Set_EPx_RX_DMA_Interface_Config(USB_EP_ID epId, BL_Fun_Type newState);
+BL_Err_Type USB_EPx_Write_Data_To_FIFO_DMA(USB_EP_ID epId, uint8_t *pData, uint16_t len);
+BL_Err_Type USB_EPx_Read_Data_From_FIFO_DMA(USB_EP_ID epId, uint8_t *pBuff, uint16_t len);
+/*----------*/
+uint16_t USB_Get_EPx_TX_FIFO_CNT(USB_EP_ID epId);
+uint16_t USB_Get_EPx_RX_FIFO_CNT(USB_EP_ID epId);
+BL_Sts_Type USB_Get_EPx_TX_FIFO_Status(USB_EP_ID epId, USB_FIFO_STATUS_Type sts);
+BL_Sts_Type USB_Get_EPx_RX_FIFO_Status(USB_EP_ID epId, USB_FIFO_STATUS_Type sts);
+/*----------*/
+BL_Err_Type USB_Set_Internal_PullUp_Config(BL_Fun_Type newState);
+/*----------*/
+BL_Sts_Type USB_Get_LPM_Status(void);
+uint16_t USB_Get_LPM_Packet_Attr(void);
+BL_Err_Type USB_Set_LPM_Default_Response(USB_LPM_DEFAULT_RESP_Type defaultResp);
+BL_Err_Type USB_LPM_Enable(void);
+BL_Err_Type USB_LPM_Disable(void);
+/*----------*/
+BL_Err_Type USB_Device_Output_K_State(uint16_t stateWidth);
+/*----------*/
+uint8_t USB_Get_Current_Packet_PID(void);
+uint8_t USB_Get_Current_Packet_EP(void);
+/*----------*/
+BL_Sts_Type USB_Get_Error_Status(USB_ERROR_Type err);
+BL_Err_Type USB_Clr_Error_Status(USB_ERROR_Type err);
+/*----------*/
+
+/*@} end of group USB_Public_Functions */
+
+/*@} end of group USB */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_USB_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_xip_sflash.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_xip_sflash.h
new file mode 100644
index 00000000..b418ff6f
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_xip_sflash.h
@@ -0,0 +1,95 @@
+/**
+  ******************************************************************************
+  * @file    bl702_xip_sflash.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_XIP_SFLASH_H__
+#define __BL702_XIP_SFLASH_H__
+
+#include "bl702_common.h"
+#include "bl702_sflash.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  XIP_SFLASH
+ *  @{
+ */
+
+/** @defgroup  XIP_SFLASH_Public_Types
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_Public_Types */
+
+/** @defgroup  XIP_SFLASH_Public_Constants
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_Public_Constants */
+
+/** @defgroup  XIP_SFLASH_Public_Macros
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_Public_Macros */
+
+/** @defgroup  XIP_SFLASH_Public_Functions
+ *  @{
+ */
+void XIP_SFlash_Opt_Enter(void);
+void XIP_SFlash_Opt_Exit(void);
+BL_Err_Type XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset);
+BL_Err_Type XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t offset);
+BL_Err_Type XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode,
+                                       uint32_t startaddr, uint32_t endaddr);
+BL_Err_Type XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr,
+                                       uint8_t *data, uint32_t len);
+BL_Err_Type XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr,
+                                      uint8_t *data, uint32_t len);
+BL_Err_Type XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode,
+                                            uint8_t *data);
+BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode,
+                                             uint8_t *data);
+BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode,
+                                             uint8_t *data, uint8_t idLen);
+BL_Err_Type XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len);
+
+/*@} end of group XIP_SFLASH_Public_Functions */
+
+/*@} end of group XIP_SFLASH */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_XIP_SFLASH_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_xip_sflash_ext.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_xip_sflash_ext.h
new file mode 100644
index 00000000..52545e77
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_xip_sflash_ext.h
@@ -0,0 +1,86 @@
+/**
+  ******************************************************************************
+  * @file    bl702_xip_sflash_ext.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_XIP_SFLASH_EXT_H__
+#define __BL702_XIP_SFLASH_EXT_H__
+
+#include "bl702_common.h"
+#include "bl702_sflash.h"
+#include "bl702_xip_sflash.h"
+#include "bl702_sflash.h"
+#include "bl702_sflash_ext.h"
+#include "bl702_sf_cfg.h"
+#include "bl702_sf_cfg_ext.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  XIP_SFLASH
+ *  @{
+ */
+
+/** @defgroup  XIP_SFLASH_EXT_Public_Types
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_EXT_Public_Types */
+
+/** @defgroup  XIP_SFLASH_EXT_Public_Constants
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_EXT_Public_Constants */
+
+/** @defgroup  XIP_SFLASH_EXT_Public_Macros
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_EXT_Public_Macros */
+
+/** @defgroup  XIP_SFLASH_EXT_Public_Functions
+ *  @{
+ */
+
+BL_Err_Type XIP_SFlash_KH25V40_Write_Protect_Need_Lock(SPI_Flash_Cfg_Type *flashCfg, SFlash_Protect_Kh25v40_Type protect);
+BL_Err_Type XIP_SFlash_Clear_Status_Register_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg);
+
+/*@} end of group XIP_SFLASH_EXT_Public_Functions */
+
+/*@} end of group XIP_SFLASH */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_XIP_SFLASH_EXT_H__ */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_acomp.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_acomp.c
new file mode 100644
index 00000000..666aa189
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_acomp.c
@@ -0,0 +1,202 @@
+/**
+  ******************************************************************************
+  * @file    bl702_acomp.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_acomp.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  ACOMP
+ *  @{
+ */
+
+/** @defgroup  ACOMP_Private_Macros
+ *  @{
+ */
+
+/*@} end of group ACOMP_Private_Macros */
+
+/** @defgroup  ACOMP_Private_Types
+ *  @{
+ */
+
+/*@} end of group ACOMP_Private_Types */
+
+/** @defgroup  ACOMP_Private_Variables
+ *  @{
+ */
+
+/*@} end of group ACOMP_Private_Variables */
+
+/** @defgroup  ACOMP_Global_Variables
+ *  @{
+ */
+
+/*@} end of group ACOMP_Global_Variables */
+
+/** @defgroup  ACOMP_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group ACOMP_Private_Fun_Declaration */
+
+/** @defgroup  ACOMP_Private_Functions
+ *  @{
+ */
+
+/*@} end of group ACOMP_Private_Functions */
+
+/** @defgroup  ACOMP_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Analog compare init
+ *
+ * @param  acompNo: Compare ID
+ * @param  cfg: Compare consideration pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void AON_ACOMP_Init(AON_ACOMP_ID_Type acompNo, AON_ACOMP_CFG_Type *cfg)
+{
+    uint32_t tmpVal = 0;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo));
+
+    if (acompNo == AON_ACOMP0_ID) {
+        /* Disable ACOMP first */
+        tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP0_CTRL);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, AON_ACOMP0_EN);
+        tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal);
+
+        /* Set ACOMP config */
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_MUXEN, cfg->muxEn);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_POS_SEL, cfg->posChanSel);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_NEG_SEL, cfg->negChanSel);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_LEVEL_SEL, cfg->levelFactor);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_BIAS_PROG, cfg->biasProg);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_HYST_SELP, cfg->hysteresisPosVolt);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_HYST_SELN, cfg->hysteresisNegVolt);
+
+        tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal);
+
+    } else {
+        /* Disable ACOMP first */
+        tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP1_CTRL);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, AON_ACOMP1_EN);
+        tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal);
+
+        /* Set ACOMP config */
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_MUXEN, cfg->muxEn);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_POS_SEL, cfg->posChanSel);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_NEG_SEL, cfg->negChanSel);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_LEVEL_SEL, cfg->levelFactor);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_BIAS_PROG, cfg->biasProg);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_HYST_SELP, cfg->hysteresisPosVolt);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_HYST_SELN, cfg->hysteresisNegVolt);
+
+        tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal);
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Analog compare enable
+ *
+ * @param  acompNo: Compare ID
+ *
+ * @return None
+ *
+*******************************************************************************/
+void AON_ACOMP_Enable(AON_ACOMP_ID_Type acompNo)
+{
+    uint32_t tmpVal = 0;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo));
+
+    if (acompNo == AON_ACOMP0_ID) {
+        tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP0_CTRL);
+        tmpVal = BL_SET_REG_BIT(tmpVal, AON_ACOMP0_EN);
+        tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal);
+    } else {
+        tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP1_CTRL);
+        tmpVal = BL_SET_REG_BIT(tmpVal, AON_ACOMP1_EN);
+        tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal);
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Analog compare enable
+ *
+ * @param  acompNo: Compare ID
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type AON_ACOMP_Get_Result(AON_ACOMP_ID_Type acompNo)
+{
+    uint32_t tmpVal = 0;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo));
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP_CTRL);
+
+    /* Disable ACOMP first */
+    if (acompNo == AON_ACOMP0_ID) {
+        if (BL_IS_REG_BIT_SET(tmpVal, AON_ACOMP0_OUT_RAW)) {
+            return SET;
+        } else {
+            return RESET;
+        }
+    } else {
+        if (BL_IS_REG_BIT_SET(tmpVal, AON_ACOMP1_OUT_RAW)) {
+            return SET;
+        } else {
+            return RESET;
+        }
+    }
+}
+
+/*@} end of group ACOMP_Public_Functions */
+
+/*@} end of group ACOMP */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_adc.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_adc.c
new file mode 100644
index 00000000..e4bd8213
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_adc.c
@@ -0,0 +1,1520 @@
+/**
+ ******************************************************************************
+ * @file    bl702_adc.c
+ * @version V1.0
+ * @date
+ * @brief   This file is the standard driver c file
+ ******************************************************************************
+ * @attention
+ *
+ * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#include "bl702_adc.h"
+#include "bl702_ef_ctrl.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  ADC
+ *  @{
+ */
+
+/** @defgroup  ADC_Private_Macros
+ *  @{
+ */
+#undef MSG
+#define MSG(...)
+#define AON_CLK_SET_DUMMY_WAIT \
+  {                            \
+    __NOP();                   \
+    __NOP();                   \
+    __NOP();                   \
+    __NOP();                   \
+    __NOP();                   \
+    __NOP();                   \
+    __NOP();                   \
+    __NOP();                   \
+  }
+#define ADC_RESTART_DUMMY_WAIT BL702_Delay_US(100)
+
+/*@} end of group ADC_Private_Macros */
+
+/** @defgroup  ADC_Private_Types
+ *  @{
+ */
+
+/*@} end of group ADC_Private_Types */
+
+/** @defgroup  ADC_Private_Variables
+ *  @{
+ */
+static intCallback_Type   *adcIntCbfArra[ADC_INT_ALL] = {NULL};
+static ADC_Gain_Coeff_Type adcGainCoeffCal            = {
+               .adcGainCoeffEnable = DISABLE,
+               .adcgainCoeffVal    = 0,
+               .coe                = 1,
+};
+
+/*@} end of group ADC_Private_Variables */
+
+/** @defgroup  ADC_Global_Variables
+ *  @{
+ */
+
+/*@} end of group ADC_Global_Variables */
+
+/** @defgroup  ADC_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group ADC_Private_Fun_Declaration */
+
+/** @defgroup  ADC_Private_Functions
+ *  @{
+ */
+
+/*@} end of group ADC_Private_Functions */
+
+/** @defgroup  ADC_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/
+/**
+ * @brief  Software reset the whole ADC
+ *
+ * @param  None
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ADC_Reset(void) {
+  uint32_t regCmd;
+
+  /* reset ADC */
+  regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, BL_SET_REG_BIT(regCmd, AON_GPADC_SOFT_RST));
+  AON_CLK_SET_DUMMY_WAIT;
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, BL_CLR_REG_BIT(regCmd, AON_GPADC_SOFT_RST));
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC glable enable
+ *
+ * @param  None
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ADC_Enable(void) {
+  uint32_t tmpVal;
+
+  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
+  tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_GLOBAL_EN);
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC glable disable
+ *
+ * @param  None
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ADC_Disable(void) {
+  uint32_t tmpVal;
+
+  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
+  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_GLOBAL_EN);
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC normal mode init
+ *
+ * @param  cfg: ADC normal mode configuration
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ADC_Init(ADC_CFG_Type *cfg) {
+  uint32_t regCfg1;
+  uint32_t regCfg2;
+  uint32_t regCalib;
+
+  CHECK_PARAM(IS_ADC_V18_SEL_TYPE(cfg->v18Sel));
+  CHECK_PARAM(IS_ADC_V11_SEL_TYPE(cfg->v11Sel));
+  CHECK_PARAM(IS_ADC_CLK_TYPE(cfg->clkDiv));
+  CHECK_PARAM(IS_ADC_PGA_GAIN_TYPE(cfg->gain1));
+  CHECK_PARAM(IS_ADC_PGA_GAIN_TYPE(cfg->gain2));
+  CHECK_PARAM(IS_ADC_CHOP_MOD_TYPE(cfg->chopMode));
+  CHECK_PARAM(IS_ADC_BIAS_SEL_TYPE(cfg->biasSel));
+  CHECK_PARAM(IS_ADC_PGA_VCM_TYPE(cfg->vcm));
+  CHECK_PARAM(IS_ADC_VREF_TYPE(cfg->vref));
+  CHECK_PARAM(IS_ADC_SIG_INPUT_TYPE(cfg->inputMode));
+  CHECK_PARAM(IS_ADC_DATA_WIDTH_TYPE(cfg->resWidth));
+
+  /* config 1 */
+  regCfg1 = 0; // BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1);
+  regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_V18_SEL, cfg->v18Sel);
+  regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_V11_SEL, cfg->v11Sel);
+  regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_DITHER_EN);
+  regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_SCAN_EN);
+  regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_SCAN_LENGTH, 0);
+  regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CLK_DIV_RATIO, cfg->clkDiv);
+  regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_CLK_ANA_INV);
+  regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CAL_OS_EN, cfg->offsetCalibEn);
+  regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_RES_SEL, cfg->resWidth);
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, regCfg1);
+  AON_CLK_SET_DUMMY_WAIT;
+
+  /* config 2 */
+  regCfg2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
+  regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_DLY_SEL, 0x00);
+  regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA1_GAIN, cfg->gain1);
+  regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA2_GAIN, cfg->gain2);
+  regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_BIAS_SEL, cfg->biasSel);
+  regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_CHOP_MODE, cfg->chopMode);
+  regCfg2 = BL_CLR_REG_BIT(regCfg2, AON_GPADC_VBAT_EN);   // vbat enabled (off)
+  regCfg2 = BL_CLR_REG_BIT(regCfg2, AON_GPADC_TSVBE_LOW); // tsen didoe current
+  /* pga_vcmi_en is for mic */
+  regCfg2 = BL_CLR_REG_BIT(regCfg2, AON_GPADC_PGA_VCMI_EN);
+
+  if ((cfg->gain1 != ADC_PGA_GAIN_NONE) || (cfg->gain2 != ADC_PGA_GAIN_NONE)) {
+    regCfg2 = BL_SET_REG_BIT(regCfg2, AON_GPADC_PGA_EN);
+  } else {
+    regCfg2 = BL_CLR_REG_BIT(regCfg2, AON_GPADC_PGA_EN);
+  }
+
+  /* pga_os_cal is for mic */
+  regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA_OS_CAL, 8);
+  regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA_VCM, cfg->vcm);
+  regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_VREF_SEL, cfg->vref);
+  regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_DIFF_MODE, cfg->inputMode);
+
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, regCfg2);
+
+  /* calibration offset */
+  regCalib = BL_RD_REG(AON_BASE, AON_GPADC_REG_DEFINE);
+  regCalib = BL_SET_REG_BITS_VAL(regCalib, AON_GPADC_OS_CAL_DATA, cfg->offsetCalibVal);
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_DEFINE, regCalib);
+
+#ifndef BFLB_USE_HAL_DRIVER
+  Interrupt_Handler_Register(GPADC_DMA_IRQn, GPADC_DMA_IRQHandler);
+#endif
+
+  // ADC_Gain_Trim();
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC normal mode channel config
+ *
+ * @param  posCh: ADC pos channel type
+ * @param  negCh: ADC neg channel type
+ * @param  contEn: ENABLE or DISABLE continuous mode
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ADC_Channel_Config(ADC_Chan_Type posCh, ADC_Chan_Type negCh, BL_Fun_Type contEn) {
+  uint32_t regCmd;
+  uint32_t regCfg1;
+
+  CHECK_PARAM(IS_AON_ADC_CHAN_TYPE(posCh));
+  CHECK_PARAM(IS_AON_ADC_CHAN_TYPE(negCh));
+
+  /* set channel */
+  regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
+  regCmd = BL_SET_REG_BITS_VAL(regCmd, AON_GPADC_POS_SEL, posCh);
+  regCmd = BL_SET_REG_BITS_VAL(regCmd, AON_GPADC_NEG_SEL, negCh);
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd);
+
+  /* set continuous mode */
+  regCfg1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1);
+  regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CONT_CONV_EN, contEn);
+  regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_SCAN_EN);
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, regCfg1);
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC scan mode channel config
+ *
+ * @param  posChList[]: ADC pos channel list type
+ * @param  negChList[]: ADC neg channel list type
+ * @param  scanLength: ADC scan length
+ * @param  contEn: ENABLE or DISABLE continuous mode
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ADC_Scan_Channel_Config(const ADC_Chan_Type posChList[], const ADC_Chan_Type negChList[], uint8_t scanLength, BL_Fun_Type contEn) {
+  uint32_t tmpVal, i;
+  uint32_t dealLen;
+
+  CHECK_PARAM((scanLength < 13));
+
+  /* Deal with the first 6 */
+  dealLen = 6;
+
+  if (scanLength < dealLen) {
+    dealLen = scanLength;
+  }
+
+  /* Set first 6 scan channels */
+  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_POS1);
+
+  for (i = 0; i < dealLen; i++) {
+    tmpVal = tmpVal & (~(0x1F << (i * 5)));
+    tmpVal |= (posChList[i] << (i * 5));
+  }
+
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_POS1, tmpVal);
+
+  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_NEG1);
+
+  for (i = 0; i < dealLen; i++) {
+    tmpVal = tmpVal & (~(0x1F << (i * 5)));
+    tmpVal |= (negChList[i] << (i * 5));
+  }
+
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_NEG1, tmpVal);
+
+  /* Set the left channels */
+  if (scanLength > dealLen) {
+    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_POS2);
+
+    for (i = 0; i < scanLength - dealLen; i++) {
+      tmpVal = tmpVal & (~(0x1F << (i * 5)));
+      tmpVal |= (posChList[i + dealLen] << (i * 5));
+    }
+
+    BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_POS2, tmpVal);
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_NEG2);
+
+    for (i = 0; i < scanLength - dealLen; i++) {
+      tmpVal = tmpVal & (~(0x1F << (i * 5)));
+      tmpVal |= (negChList[i + dealLen] << (i * 5));
+    }
+
+    BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_NEG2, tmpVal);
+  }
+
+  /* Scan mode */
+  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_SCAN_LENGTH, scanLength - 1);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_CONT_CONV_EN, contEn);
+  tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_CLK_ANA_INV);
+  tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_SCAN_EN);
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, tmpVal);
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC normal mode convert start
+ *
+ * @param  None
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ADC_Start(void) {
+  uint32_t regCmd;
+
+  /* disable convert start */
+  regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
+  regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_CONV_START);
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd);
+
+  ADC_RESTART_DUMMY_WAIT;
+
+  /* enable convert start */
+  regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
+  regCmd = BL_SET_REG_BIT(regCmd, AON_GPADC_CONV_START);
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd);
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC normal mode convert stop
+ *
+ * @param  None
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ADC_Stop(void) {
+  uint32_t regCmd;
+
+  /* disable convert start */
+  regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
+  regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_CONV_START);
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd);
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC FIFO configuration
+ *
+ * @param  fifoCfg: ADC FIFO confifuration pointer
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ADC_FIFO_Cfg(ADC_FIFO_Cfg_Type *fifoCfg) {
+  uint32_t tmpVal;
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_GPIP_ADC_FIFO_THRESHOLD_TYPE(fifoCfg->fifoThreshold));
+
+  /*
+   *  DMA enable : ,When the fifo data is exceeded to fifoThreshold DMA request will occur
+   *  DMA disable : fifoThreshold determine how many data will raise FIFO ready interrupt
+   */
+
+  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPADC_FIFO_THL, fifoCfg->fifoThreshold);
+
+  /* Enable DMA */
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPADC_DMA_EN, fifoCfg->dmaEn);
+
+  BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+
+  /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/
+  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+  tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR);
+  BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC get DMA FIFO data count
+ *
+ * @param  None
+ *
+ * @return data count in FIFO
+ *
+ *******************************************************************************/
+uint8_t ADC_Get_FIFO_Count(void) {
+  uint32_t tmpVal;
+
+  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+
+  return BL_GET_REG_BITS_VAL(tmpVal, GPIP_GPADC_FIFO_DATA_COUNT);
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC get DMA FIFO full status
+ *
+ * @param  None
+ *
+ * @return SET or RESET
+ *
+ *******************************************************************************/
+BL_Sts_Type ADC_FIFO_Is_Full(void) {
+  uint32_t tmpVal;
+
+  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+
+  if (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_FULL)) {
+    return SET;
+  } else {
+    return RESET;
+  }
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC get DMA FIFO empty status
+ *
+ * @param  None
+ *
+ * @return SET or RESET
+ *
+ *******************************************************************************/
+BL_Sts_Type ADC_FIFO_Is_Empty(void) {
+  uint32_t tmpVal;
+
+  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+
+  if (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_NE)) {
+    return RESET;
+  } else {
+    return SET;
+  }
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC read DMA FIFO data
+ *
+ * @param  None
+ *
+ * @return ADC result if return 0 that means this is error data,user should ignore this data.
+ *
+ *******************************************************************************/
+uint32_t ADC_Read_FIFO(void) {
+  uint32_t tmpVal;
+
+  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_DMA_RDATA);
+
+  return (tmpVal);
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC parse result
+ *
+ * @param  orgVal: Original A to D value
+ * @param  len: Original AD vaule count
+ * @param  result: Final Result array pointer
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ADC_Parse_Result(uint32_t *orgVal, uint32_t len, ADC_Result_Type *result) {
+  uint8_t             neg     = 0;
+  uint32_t            tmpVal1 = 0, tmpVal2 = 0;
+  ADC_Data_Width_Type dataType;
+  ADC_SIG_INPUT_Type  sigType;
+  float               ref = 2.0;
+  uint32_t            i   = 0;
+
+  float coe = 1.0;
+
+  if (adcGainCoeffCal.adcGainCoeffEnable) {
+    coe = adcGainCoeffCal.coe;
+  }
+
+  tmpVal1  = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1);
+  tmpVal2  = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
+  dataType = BL_GET_REG_BITS_VAL(tmpVal1, AON_GPADC_RES_SEL);
+  sigType  = BL_GET_REG_BITS_VAL(tmpVal2, AON_GPADC_DIFF_MODE);
+
+  if (BL_GET_REG_BITS_VAL(tmpVal2, AON_GPADC_VREF_SEL) == ADC_VREF_3P2V) {
+    ref = 3.2;
+  }
+
+  if (sigType == ADC_INPUT_SINGLE_END) {
+    for (i = 0; i < len; i++) {
+      result[i].posChan = orgVal[i] >> 21;
+      result[i].negChan = -1;
+
+      if (dataType == ADC_DATA_WIDTH_12) {
+        result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 4) / coe);
+        result[i].volt  = result[i].value / 4096.0 * ref;
+      } else if ((dataType == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) || (dataType == ADC_DATA_WIDTH_14_WITH_64_AVERAGE)) {
+        result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 2) / coe);
+        result[i].volt  = result[i].value / 16384.0 * ref;
+      } else if ((dataType == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) || (dataType == ADC_DATA_WIDTH_16_WITH_256_AVERAGE)) {
+        result[i].value = (unsigned int)((orgVal[i] & 0xffff) / coe);
+        result[i].volt  = result[i].value / 65536.0 * ref;
+      }
+    }
+  } else {
+    for (i = 0; i < len; i++) {
+      neg               = 0;
+      result[i].posChan = orgVal[i] >> 21;
+      result[i].negChan = (orgVal[i] >> 16) & 0x1F;
+
+      if (orgVal[i] & 0x8000) {
+        orgVal[i] = ~orgVal[i];
+        orgVal[i] += 1;
+        neg = 1;
+      }
+
+      if (dataType == ADC_DATA_WIDTH_12) {
+        result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 4) / coe);
+        result[i].volt  = result[i].value / 2048.0 * ref;
+      } else if ((dataType == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) || (dataType == ADC_DATA_WIDTH_14_WITH_64_AVERAGE)) {
+        result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 2) / coe);
+        result[i].volt  = result[i].value / 8192.0 * ref;
+      } else if ((dataType == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) || (dataType == ADC_DATA_WIDTH_16_WITH_256_AVERAGE)) {
+        result[i].value = (unsigned int)((orgVal[i] & 0xffff) / coe);
+        result[i].volt  = result[i].value / 32768.0 * ref;
+      }
+
+      if (neg) {
+        result[i].volt = -result[i].volt;
+      }
+    }
+  }
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC mask or unmask certain or all interrupt
+ *
+ * @param  intType: interrupt type
+ * @param  intMask: mask or unmask
+ *
+ * @return None
+ *
+ *******************************************************************************/
+BL_Mask_Type ADC_IntGetMask(ADC_INT_Type intType) {
+  uint32_t tmpVal;
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType));
+  CHECK_PARAM(IS_BL_MASK_TYPE(intMask));
+
+  switch (intType) {
+  case ADC_INT_POS_SATURATION:
+    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);
+    return BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_POS_SATUR_MASK);
+    break;
+
+  case ADC_INT_NEG_SATURATION:
+    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);
+    return BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_NEG_SATUR_MASK);
+    break;
+
+  case ADC_INT_FIFO_UNDERRUN:
+    tmpVal = BL_RD_REG(AON_BASE, GPIP_GPADC_CONFIG);
+    return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK);
+    break;
+
+  case ADC_INT_FIFO_OVERRUN:
+    tmpVal = BL_RD_REG(AON_BASE, GPIP_GPADC_CONFIG);
+    return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK);
+    break;
+
+  case ADC_INT_ADC_READY:
+    tmpVal = BL_RD_REG(AON_BASE, GPIP_GPADC_CONFIG);
+    return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_RDY_MASK);
+    break;
+
+  case ADC_INT_FIFO_READY:
+    tmpVal = BL_RD_REG(AON_BASE, GPIP_GPADC_CONFIG);
+    return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_RDY_MASK);
+    break;
+  default:
+    break;
+  }
+  return 0;
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC mask or unmask certain or all interrupt
+ *
+ * @param  intType: interrupt type
+ * @param  intMask: mask or unmask
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask) {
+  uint32_t tmpVal;
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType));
+  CHECK_PARAM(IS_BL_MASK_TYPE(intMask));
+
+  switch (intType) {
+  case ADC_INT_POS_SATURATION:
+    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);
+
+    if (intMask == UNMASK) {
+      /* Enable this interrupt */
+      tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK);
+    } else {
+      /* Disable this interrupt */
+      tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK);
+    }
+
+    BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);
+    break;
+
+  case ADC_INT_NEG_SATURATION:
+    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);
+
+    if (intMask == UNMASK) {
+      /* Enable this interrupt */
+      tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK);
+    } else {
+      /* Disable this interrupt */
+      tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK);
+    }
+
+    BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);
+    break;
+
+  case ADC_INT_FIFO_UNDERRUN:
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+
+    if (intMask == UNMASK) {
+      /* Enable this interrupt */
+      tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK);
+    } else {
+      /* Disable this interrupt */
+      tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK);
+    }
+
+    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+    break;
+
+  case ADC_INT_FIFO_OVERRUN:
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+
+    if (intMask == UNMASK) {
+      /* Enable this interrupt */
+      tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK);
+    } else {
+      /* Disable this interrupt */
+      tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK);
+    }
+
+    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+    break;
+
+  case ADC_INT_ADC_READY:
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+
+    if (intMask == UNMASK) {
+      /* Enable this interrupt */
+      tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK);
+    } else {
+      /* Disable this interrupt */
+      tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK);
+    }
+
+    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+    break;
+
+  case ADC_INT_FIFO_READY:
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+
+    if (intMask == UNMASK) {
+      /* Enable this interrupt */
+      tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY_MASK);
+    } else {
+      /* Disable this interrupt */
+      tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY_MASK);
+    }
+
+    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+    break;
+
+  case ADC_INT_ALL:
+    if (intMask == UNMASK) {
+      /* Enable this interrupt */
+      tmpVal = BL_RD_REG(GPIP_BASE, AON_GPADC_REG_ISR);
+      tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK);
+      tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK);
+      BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);
+
+      tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+      tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK);
+      tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK);
+      tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK);
+      BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+    } else {
+      /* Disable this interrupt */
+      tmpVal = BL_RD_REG(GPIP_BASE, AON_GPADC_REG_ISR);
+      tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK);
+      tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK);
+      BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);
+
+      tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+      tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK);
+      tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK);
+      tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK);
+      BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+    }
+
+    break;
+
+  default:
+    break;
+  }
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC clear certain or all interrupt
+ *
+ * @param  intType: interrupt type
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ADC_IntClr(ADC_INT_Type intType) {
+  uint32_t tmpVal;
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType));
+
+  switch (intType) {
+  case ADC_INT_POS_SATURATION:
+    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR);
+    BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR);
+    BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);
+
+    /*Manual reset*/
+    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR);
+    BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);
+
+    break;
+
+  case ADC_INT_NEG_SATURATION:
+    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR);
+    BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR);
+    BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);
+
+    /*Manual reset*/
+    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR);
+    BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);
+
+    break;
+
+  case ADC_INT_FIFO_UNDERRUN:
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR);
+    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR);
+    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+
+    /*Manual reset*/
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR);
+    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+
+    break;
+
+  case ADC_INT_FIFO_OVERRUN:
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR);
+    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR);
+    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+
+    /*Manual reset*/
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR);
+    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+
+    break;
+
+  case ADC_INT_ADC_READY:
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR);
+    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR);
+    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+
+    /*Manual reset*/
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR);
+    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+
+    break;
+
+  case ADC_INT_FIFO_READY:
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY);
+    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY);
+    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+
+    /*Manual reset*/
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY);
+    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+
+    break;
+
+  case ADC_INT_ALL:
+    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR);
+    BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR);
+    BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);
+
+    /*Manual reset*/
+    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR);
+    BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);
+
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR);
+    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR);
+    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+
+    /*Manual reset*/
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR);
+    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+
+    break;
+
+  default:
+    break;
+  }
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC get interrupt status
+ *
+ * @param  intType: interrupt type
+ *
+ * @return SET or RESET
+ *
+ *******************************************************************************/
+BL_Sts_Type ADC_GetIntStatus(ADC_INT_Type intType) {
+  uint32_t    tmpVal;
+  BL_Sts_Type bitStatus = RESET;
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType));
+
+  switch (intType) {
+  case ADC_INT_POS_SATURATION:
+    tmpVal    = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);
+    bitStatus = (BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_POS_SATUR)) ? SET : RESET;
+    break;
+
+  case ADC_INT_NEG_SATURATION:
+    tmpVal    = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);
+    bitStatus = (BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_NEG_SATUR)) ? SET : RESET;
+    break;
+
+  case ADC_INT_FIFO_UNDERRUN:
+    tmpVal    = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+    bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_UNDERRUN)) ? SET : RESET;
+    break;
+
+  case ADC_INT_FIFO_OVERRUN:
+    tmpVal    = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+    bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_OVERRUN)) ? SET : RESET;
+    break;
+
+  case ADC_INT_ADC_READY:
+    tmpVal    = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+    bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_RDY)) ? SET : RESET;
+    break;
+
+  case ADC_INT_FIFO_READY:
+    tmpVal    = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+    bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_RDY)) ? SET : RESET;
+    break;
+
+  case ADC_INT_ALL:
+    break;
+
+  default:
+    break;
+  }
+
+  return bitStatus;
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC install interrupt callback
+ *
+ * @param  intType: ADC interrupt type
+ * @param  cbFun: ADC interrupt callback
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ADC_Int_Callback_Install(ADC_INT_Type intType, intCallback_Type *cbFun) {
+  /* Check the parameters */
+  CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType));
+
+  adcIntCbfArra[intType] = cbFun;
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC DMA interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+ *******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void GPADC_DMA_IRQHandler(void) {
+  if (ADC_GetIntStatus(ADC_INT_POS_SATURATION) == SET) {
+    ADC_IntClr(ADC_INT_POS_SATURATION);
+
+    if (adcIntCbfArra[ADC_INT_POS_SATURATION] != NULL) {
+      adcIntCbfArra[ADC_INT_POS_SATURATION]();
+    }
+  }
+
+  if (ADC_GetIntStatus(ADC_INT_NEG_SATURATION) == SET) {
+    ADC_IntClr(ADC_INT_NEG_SATURATION);
+
+    if (adcIntCbfArra[ADC_INT_NEG_SATURATION] != NULL) {
+      adcIntCbfArra[ADC_INT_NEG_SATURATION]();
+    }
+  }
+
+  if (ADC_GetIntStatus(ADC_INT_FIFO_UNDERRUN) == SET) {
+    ADC_IntClr(ADC_INT_FIFO_UNDERRUN);
+
+    if (adcIntCbfArra[ADC_INT_FIFO_UNDERRUN] != NULL) {
+      adcIntCbfArra[ADC_INT_FIFO_UNDERRUN]();
+    }
+  }
+
+  if (ADC_GetIntStatus(ADC_INT_FIFO_OVERRUN) == SET) {
+    ADC_IntClr(ADC_INT_FIFO_OVERRUN);
+
+    if (adcIntCbfArra[ADC_INT_FIFO_OVERRUN] != NULL) {
+      adcIntCbfArra[ADC_INT_FIFO_OVERRUN]();
+    }
+  }
+
+  if (ADC_GetIntStatus(ADC_INT_FIFO_READY) == SET) {
+    ADC_IntClr(ADC_INT_FIFO_READY);
+
+    if (adcIntCbfArra[ADC_INT_FIFO_READY] != NULL) {
+      adcIntCbfArra[ADC_INT_FIFO_READY]();
+    }
+  }
+
+  if (ADC_GetIntStatus(ADC_INT_FIFO_READY) == SET) {
+    ADC_IntClr(ADC_INT_FIFO_READY);
+
+    if (adcIntCbfArra[ADC_INT_FIFO_READY] != NULL) {
+      adcIntCbfArra[ADC_INT_FIFO_READY]();
+    }
+  }
+}
+#endif
+
+/****************************************************************************/
+/**
+ * @brief  ADC VBAT enable
+ *
+ * @param  None
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ADC_Vbat_Enable(void) {
+  uint32_t tmpVal;
+
+  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
+  tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_VBAT_EN);
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC VBAT disable
+ *
+ * @param  None
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ADC_Vbat_Disable(void) {
+  uint32_t tmpVal;
+
+  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
+  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_VBAT_EN);
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC TSEN Config
+ *
+ * @param  tsenMod: None
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ADC_Tsen_Init(ADC_TSEN_MOD_Type tsenMod) {
+  uint32_t tmpVal;
+
+  CHECK_PARAM(IS_AON_ADC_TSEN_MOD_TYPE(type));
+
+  /* config gpadc_reg_cmd */
+  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
+  /* enable sensor dc test mux*/
+  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_SEN_TEST_EN);
+  /*selected sen output current channel*/
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_SEN_SEL, 0);
+  /* enable chip sensor*/
+  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_CHIP_SEN_PU);
+  /*dwa_en */
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_DWA_EN, 1);
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
+
+  /* config 2 */
+  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
+  /*tsvbe low=0*/
+  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW);
+  /*dly_sel=2*/
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_DLY_SEL, 2);
+  /*test_sel=0*/
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_TEST_SEL, 0);
+  /*test_en=0*/
+  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TEST_EN);
+  /*ts_en*/
+  tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TS_EN);
+  /*select tsen ext or inner*/
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_TSEXT_SEL, tsenMod);
+
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_VCM, 2);
+  /*pga vcmi enable*/
+  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_PGA_VCMI_EN);
+  /*0:512uS;1:16mS;2:32mS;3:64mS*/
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_OS_CAL, 0);
+
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);
+
+  /* config 3 */
+  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1);
+  /* set gpadc_dither_en */
+  tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_DITHER_EN);
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, tmpVal);
+
+  /* set 4000F90C[19](gpadc_mic2_diff) = 1
+   * debug advise form Ran
+   * 2020.08.26
+   */
+  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_MIC2_DIFF, 1);
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC TSEN Enable
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ADC_Tsen_Enable(void) {
+  uint32_t tmpVal;
+
+  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
+  tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TS_EN);
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC TSEN Disable
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ADC_Tsen_Disable(void) {
+  uint32_t tmpVal;
+
+  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
+  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TS_EN);
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC Clear fifo
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ADC_FIFO_Clear(void) {
+  uint32_t tmpVal;
+
+  /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/
+  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+  tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR);
+  BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+}
+
+/****************************************************************************/
+/**
+ * @brief  config pga
+ *
+ * @param  pga_vcmi_enable: enable or not vcmi
+ * @param  pga_os_cal: pga os cal value
+ * @return None
+ *
+ *******************************************************************************/
+void ADC_PGA_Config(uint8_t pga_vcmi_enable, uint8_t pga_os_cal) {
+  uint32_t tmpVal;
+
+  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
+
+  if (pga_vcmi_enable) {
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_PGA_VCMI_EN);
+  } else {
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_PGA_VCMI_EN);
+  }
+
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_OS_CAL, pga_os_cal);
+
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);
+}
+/****************************************************************************/
+/**
+ * @brief  TSEN_Get_V_Error
+ *
+ * @param  None
+ *
+ * @return None
+ *
+ *******************************************************************************/
+uint32_t TSEN_Get_V_Error(void) {
+  uint32_t        v0 = 0, v1 = 0;
+  uint32_t        v_error = 0;
+  uint32_t        regVal  = 0;
+  ADC_Result_Type result;
+  uint32_t        tmpVal;
+  uint8_t         gainCalEnabled = 0;
+
+  /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/
+  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+  tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR);
+  BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+
+  ADC_SET_TSVBE_LOW();
+
+  ADC_Start();
+
+  while (ADC_Get_FIFO_Count() == 0)
+    ;
+
+  regVal                             = ADC_Read_FIFO();
+  gainCalEnabled                     = adcGainCoeffCal.adcGainCoeffEnable;
+  adcGainCoeffCal.adcGainCoeffEnable = 0;
+  ADC_Parse_Result(®Val, 1, &result);
+  adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled;
+  v0                                 = result.value;
+
+  /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/
+  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+  tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR);
+  BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+
+  ADC_SET_TSVBE_HIGH();
+
+  ADC_Start();
+
+  while (ADC_Get_FIFO_Count() == 0)
+    ;
+
+  regVal                             = ADC_Read_FIFO();
+  gainCalEnabled                     = adcGainCoeffCal.adcGainCoeffEnable;
+  adcGainCoeffCal.adcGainCoeffEnable = 0;
+  ADC_Parse_Result(®Val, 1, &result);
+  adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled;
+  v1                                 = result.value;
+
+  v_error = v0 - v1;
+
+  return v_error;
+}
+
+/****************************************************************************/
+/**
+ * @brief  Trim TSEN
+ *
+ * @param  tsen_offset: None
+ *
+ * @return SUCCESS or ERROR
+ *
+ *******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION ADC_Trim_TSEN(uint16_t *tsen_offset) {
+  Efuse_TSEN_Refcode_Corner_Type trim;
+
+  EF_Ctrl_Read_TSEN_Trim(&trim);
+  if (trim.tsenRefcodeCornerEn) {
+    if (trim.tsenRefcodeCornerParity == EF_Ctrl_Get_Trim_Parity(trim.tsenRefcodeCorner, 12)) {
+      *tsen_offset = trim.tsenRefcodeCorner;
+
+      return SUCCESS;
+    }
+  }
+
+  return ERROR;
+}
+
+/****************************************************************************/
+/**
+ * @brief  SET ADC TSEN TSVBE LOW/HIGH
+ *
+ * @param  None
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ADC_SET_TSVBE_LOW(void) {
+  uint32_t tmpVal;
+  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
+  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW);
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);
+}
+
+/****************************************************************************/
+/**
+ * @brief  SET ADC TSEN TSVBE LOW/HIGH
+ *
+ * @param  None
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ADC_SET_TSVBE_HIGH(void) {
+  uint32_t tmpVal;
+  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
+  tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW);
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);
+}
+
+/****************************************************************************/
+/**
+ * @brief  SET ADC TSEN TSVBE LOW/HIGH
+ *
+ * @param  tsen_offset: tsen_offset form efuse trim data
+ *
+ * @return tempture
+ *
+ *******************************************************************************/
+float TSEN_Get_Temp(uint32_t tsen_offset) {
+  uint32_t        v0 = 0, v1 = 0;
+  float           temp   = 0;
+  uint32_t        regVal = 0;
+  ADC_Result_Type result;
+  uint32_t        tmpVal;
+  uint8_t         gainCalEnabled = 0;
+
+  /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/
+  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+  tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR);
+  BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+
+  ADC_SET_TSVBE_LOW();
+
+  ADC_Start();
+
+  while (ADC_Get_FIFO_Count() == 0)
+    ;
+
+  regVal = ADC_Read_FIFO();
+
+  gainCalEnabled                     = adcGainCoeffCal.adcGainCoeffEnable;
+  adcGainCoeffCal.adcGainCoeffEnable = 0;
+  ADC_Parse_Result(®Val, 1, &result);
+  adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled;
+  v0                                 = result.value;
+
+  /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/
+  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
+  tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR);
+  BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
+
+  ADC_SET_TSVBE_HIGH();
+
+  ADC_Start();
+
+  while (ADC_Get_FIFO_Count() == 0)
+    ;
+
+  regVal                             = ADC_Read_FIFO();
+  gainCalEnabled                     = adcGainCoeffCal.adcGainCoeffEnable;
+  adcGainCoeffCal.adcGainCoeffEnable = 0;
+  ADC_Parse_Result(®Val, 1, &result);
+  adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled;
+  v1                                 = result.value;
+
+  if (v0 > v1) {
+    temp = (((float)v0 - (float)v1) - (float)tsen_offset) / 7.753;
+  } else {
+    temp = (((float)v1 - (float)v0) - (float)tsen_offset) / 7.753;
+  }
+
+  return temp;
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC MIC Config
+ *
+ * @param  adc_mic_config: adc_mic_config
+ *
+ * @return success or not
+ *
+ *******************************************************************************/
+BL_Err_Type ADC_Mic_Init(ADC_MIC_Type *adc_mic_config) {
+  uint32_t tmpVal1 = 0, tmpVal2 = 0;
+
+  CHECK_PARAM(IS_ADC_MICBOOST_DB_Type(adc_mic_config->micboostDb));
+  CHECK_PARAM(IS_PGA2_GAIN_Type(adc_mic_config->micPga2Gain));
+  CHECK_PARAM(IS_ADC_MIC_MODE_Type(adc_mic_config->mic1Mode));
+  CHECK_PARAM(IS_ADC_MIC_MODE_Type(adc_mic_config->mic2Mode));
+  CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->dwaEn));
+  CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micboostBypassEn));
+  CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micPgaEn));
+  CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micBiasEn));
+
+  tmpVal2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
+
+  tmpVal1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
+  tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICBOOST_32DB_EN, adc_mic_config->micboostDb);
+  tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC_PGA2_GAIN, adc_mic_config->micPga2Gain);
+  tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC1_DIFF, adc_mic_config->mic1Mode);
+  tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC2_DIFF, adc_mic_config->mic2Mode);
+  tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_DWA_EN, adc_mic_config->dwaEn);
+  tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_BYP_MICBOOST, adc_mic_config->micboostBypassEn);
+
+  if (BL_IS_REG_BIT_SET(tmpVal2, AON_GPADC_PGA_EN) && adc_mic_config->micPgaEn == ENABLE) {
+    /* 0x4000F914[13] and 0x4000F90c[15] Cannot be both Enable*/
+    return ERROR;
+  } else {
+    tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICPGA_EN, adc_mic_config->micPgaEn);
+  }
+
+  tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICBIAS_EN, adc_mic_config->micBiasEn);
+
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal1);
+
+  return SUCCESS;
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC MIC bias control
+ *
+ * @param  None
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ADC_MIC_Bias_Enable(void) {
+  uint32_t tmpVal;
+
+  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
+  tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_MICBIAS_EN);
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
+}
+
+/****************************************************************************/
+/**
+ * @brief  ADC MIC bias control
+ *
+ * @param  None
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ADC_MIC_Bias_Disable(void) {
+  uint32_t tmpVal;
+
+  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
+  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_MICBIAS_EN);
+  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
+}
+
+/****************************************************************************/
+/**
+ * @brief  Trim ADC Gain
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+ *******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION ADC_Gain_Trim(void) {
+  Efuse_ADC_Gain_Coeff_Type trim;
+  uint32_t                  tmp;
+
+  EF_Ctrl_Read_ADC_Gain_Trim(&trim);
+
+  if (trim.adcGainCoeffEn) {
+    if (trim.adcGainCoeffParity == EF_Ctrl_Get_Trim_Parity(trim.adcGainCoeff, 12)) {
+      adcGainCoeffCal.adcGainCoeffEnable = ENABLE;
+      adcGainCoeffCal.adcgainCoeffVal    = trim.adcGainCoeff;
+      tmp                                = adcGainCoeffCal.adcgainCoeffVal;
+
+      if (tmp & 0x800) {
+        tmp = ~tmp;
+        tmp += 1;
+        tmp = tmp & 0xfff;
+        // printf("val==%08x\r\n",(unsigned int)tmp);
+        adcGainCoeffCal.coe = (1.0 + ((float)tmp / 2048.0));
+        // printf("coe==%0f\r\n",adcGainCoeffCal.coe);
+      } else {
+        adcGainCoeffCal.coe = (1.0 - ((float)tmp / 2048.0));
+        // printf("coe==%0f\r\n",adcGainCoeffCal.coe);
+      }
+
+      return SUCCESS;
+    }
+  }
+
+  return ERROR;
+}
+
+/*@} end of group ADC_Public_Functions */
+
+/*@} end of group ADC */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_aon.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_aon.c
new file mode 100644
index 00000000..d1664558
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_aon.c
@@ -0,0 +1,582 @@
+/**
+  ******************************************************************************
+  * @file    bl702_aon.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_aon.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  AON
+ *  @{
+ */
+
+/** @defgroup  AON_Private_Macros
+ *  @{
+ */
+#define AON_CLK_SET_DUMMY_WAIT \
+    {                          \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+    }
+
+/*@} end of group AON_Private_Macros */
+
+/** @defgroup  AON_Private_Types
+ *  @{
+ */
+
+/*@} end of group AON_Private_Types */
+
+/** @defgroup  AON_Private_Variables
+ *  @{
+ */
+
+/*@} end of group AON_Private_Variables */
+
+/** @defgroup  AON_Global_Variables
+ *  @{
+ */
+
+/*@} end of group AON_Global_Variables */
+
+/** @defgroup  AON_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group AON_Private_Fun_Declaration */
+
+/** @defgroup  AON_Private_Functions
+ *  @{
+ */
+
+/*@} end of group AON_Private_Functions */
+
+/** @defgroup  AON_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Power on MXX band gap
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* Power up RF for PLL to work */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    BL702_Delay_US(55);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power off MXX band gap
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* Power OFF */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power on XTAL
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_XTAL(void)
+{
+    uint32_t tmpVal = 0;
+    uint32_t timeOut = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_AON);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    /* Polling for ready */
+    do {
+        BL702_Delay_US(10);
+        timeOut++;
+        tmpVal = BL_RD_REG(AON_BASE, AON_TSEN);
+    } while (!BL_IS_REG_BIT_SET(tmpVal, AON_XTAL_RDY) && timeOut < 120);
+
+    if (timeOut >= 120) {
+        return TIMEOUT;
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set XTAL cap code
+ *
+ * @param  capIn: Cap code in
+ * @param  capOut: Cap code out
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON, capIn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_OUT_AON, capOut);
+    BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
+
+    BL702_Delay_US(100);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Get XTAL cap code
+ *
+ * @param  None
+ *
+ * @return Cap code
+ *
+*******************************************************************************/
+uint8_t ATTR_CLOCK_SECTION AON_Get_Xtal_CapCode(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON);
+}
+
+/****************************************************************************/ /**
+ * @brief  Set XTAL cap code
+ *
+ * @param  extra: cap cpde extra aon
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode_Extra(uint8_t extra)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
+    if (extra) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, AON_XTAL_CAPCODE_EXTRA_AON);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, AON_XTAL_CAPCODE_EXTRA_AON);
+    }
+    BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power off XTAL
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power on bandgap system
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* power up RF for PLL to work */
+    tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_BG_SYS_AON);
+    BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal);
+
+    BL702_Delay_US(55);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power off bandgap system
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* power up RF for PLL to work */
+    tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_BG_SYS_AON);
+    BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal);
+
+    BL702_Delay_US(55);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power on LDO11
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO11_SOC(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO11SOC_AON);
+    BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal);
+
+    BL702_Delay_US(55);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power off LDO11
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO11_SOC(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO11SOC_AON);
+    BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal);
+
+    BL702_Delay_US(55);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power on LDO15_RF
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO15_RF(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* ldo15rf power on */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    BL702_Delay_US(90);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power off LDO15_RF
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO15_RF(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* ldo15rf power off */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  power on source follow regular
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* power on sfreg */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    BL702_Delay_US(10);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  power off source follow regular
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_SFReg(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* power off sfreg */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power off the power can be shut down in PDS0
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Enter_PDS0(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* power off bz */
+    tmpVal = BL_RD_REG(AON_BASE, AON_MISC);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_SW_BZ_EN_AON);
+    BL_WR_REG(AON_BASE, AON_MISC, tmpVal);
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    /* gating Clock, no more use */
+    //tmpVal=BL_RD_REG(GLB_BASE,GLB_CGEN_CFG0);
+    //tmpVal=tmpVal&(~(1<<6));
+    //tmpVal=tmpVal&(~(1<<7));
+    //BL_WR_REG(GLB_BASE,GLB_CGEN_CFG0,tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power on the power powered down in PDS0
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Exit_PDS0(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    BL702_Delay_US(20);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    BL702_Delay_US(60);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    BL702_Delay_US(20);
+
+    /* power on bz */
+    tmpVal = BL_RD_REG(AON_BASE, AON_MISC);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_SW_BZ_EN_AON);
+    BL_WR_REG(AON_BASE, AON_MISC, tmpVal);
+
+    /* ungating Clock, no more use */
+    //tmpVal=BL_RD_REG(GLB_BASE,GLB_CGEN_CFG0);
+    //tmpVal=tmpVal|((1<<6));
+    //tmpVal=tmpVal|((1<<7));
+    //BL_WR_REG(GLB_BASE,GLB_CGEN_CFG0,tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power on the power powered down in PDS0
+ *
+ * @param  delay: None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((delay <= 0x3));
+
+    /* config ldo11soc_sstart_delay_aon */
+    tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_LDO11SOC_SSTART_DELAY_AON, delay);
+    BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief
+ *
+ * @param
+ *
+ * @return
+ *
+*******************************************************************************/
+BL_Err_Type AON_Set_DCDC18_Top_0(uint8_t voutSel, uint8_t vpfm)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_DCDC18_TOP_0);
+    //dcdc18_vout_sel_aon, 1.425V*1.05=1.5V
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC18_VOUT_SEL_AON, voutSel);
+    //dcdc18_vpfm_aon
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC18_VPFM_AON, vpfm);
+    BL_WR_REG(AON_BASE, AON_DCDC18_TOP_0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief
+ *
+ * @param
+ *
+ * @return
+ *
+*******************************************************************************/
+BL_Err_Type AON_Set_Xtal_Cfg(uint8_t gmBoost, uint8_t ampCtrl, uint8_t fastStartup)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
+    //xtal_gm_boost
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_GM_BOOST_AON, gmBoost);
+    //xtal_amp_ctrl
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_AMP_CTRL_AON, ampCtrl);
+    //xtal_fast_startup
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_FAST_STARTUP_AON, fastStartup);
+    BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/*@} end of group AON_Public_Functions */
+
+/*@} end of group AON */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_cam.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_cam.c
new file mode 100644
index 00000000..21123086
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_cam.c
@@ -0,0 +1,762 @@
+/**
+  ******************************************************************************
+  * @file    bl702_cam.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702.h"
+#include "bl702_cam.h"
+#include "bl702_glb.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  CAM
+ *  @{
+ */
+
+/** @defgroup  CAM_Private_Macros
+ *  @{
+ */
+
+/*@} end of group CAM_Private_Macros */
+
+/** @defgroup  CAM_Private_Types
+ *  @{
+ */
+
+/*@} end of group CAM_Private_Types */
+
+/** @defgroup  CAM_Private_Variables
+ *  @{
+ */
+static intCallback_Type *camIntCbfArra[CAM_INT_ALL] = { NULL };
+
+/*@} end of group CAM_Private_Variables */
+
+/** @defgroup  CAM_Global_Variables
+ *  @{
+ */
+
+/*@} end of group CAM_Global_Variables */
+
+/** @defgroup  CAM_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group CAM_Private_Fun_Declaration */
+
+/** @defgroup  CAM_Private_Functions
+ *  @{
+ */
+
+/*@} end of group CAM_Private_Functions */
+
+/** @defgroup  CAM_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Camera module init
+ *
+ * @param  cfg: Camera configuration structure pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void CAM_Init(CAM_CFG_Type *cfg)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_CAM_SW_MODE_TYPE(cfg->swMode));
+    CHECK_PARAM(IS_CAM_FRAME_MODE_TYPE(cfg->frameMode));
+    CHECK_PARAM(IS_CAM_YUV_MODE_TYPE(cfg->yuvMode));
+    CHECK_PARAM(IS_CAM_FRAME_ACTIVE_POL(cfg->framePol));
+    CHECK_PARAM(IS_CAM_LINE_ACTIVE_POL(cfg->linePol));
+    CHECK_PARAM(IS_CAM_BURST_TYPE(cfg->burstType));
+    CHECK_PARAM(IS_CAM_SENSOR_MODE_TYPE(cfg->camSensorMode));
+
+    /* Disable clock gate */
+    GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_CAM);
+
+    /* Set camera configuration */
+    tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DVP_ENABLE);
+    BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_SW_MODE, cfg->swMode);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_INTERLV_MODE, cfg->frameMode);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_FRAM_VLD_POL, cfg->framePol);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_LINE_VLD_POL, cfg->linePol);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_HBURST, cfg->burstType);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_DVP_MODE, cfg->camSensorMode);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_DVP_WAIT_CYCLE, cfg->waitCount);
+
+    switch (cfg->yuvMode) {
+        case CAM_YUV422:
+            tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DROP_EN);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_SUBSAMPLE_EN);
+            break;
+
+        case CAM_YUV420_EVEN:
+            tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DROP_EN);
+            tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_SUBSAMPLE_EN);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_SUBSAMPLE_EVEN);
+            break;
+
+        case CAM_YUV420_ODD:
+            tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DROP_EN);
+            tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_SUBSAMPLE_EN);
+            tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_SUBSAMPLE_EVEN);
+            break;
+
+        case CAM_YUV400_EVEN:
+            tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DROP_EN);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DROP_EVEN);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_SUBSAMPLE_EN);
+            break;
+
+        case CAM_YUV400_ODD:
+            tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DROP_EN);
+            tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DROP_EVEN);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_SUBSAMPLE_EN);
+            break;
+
+        default:
+            break;
+    }
+
+    BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal);
+
+    /* Set frame count to issue interrupt at sw mode */
+    tmpVal = BL_RD_REG(CAM_BASE, CAM_INT_CONTROL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_FRAME_CNT_TRGR_INT, cfg->swIntCnt);
+    BL_WR_REG(CAM_BASE, CAM_INT_CONTROL, tmpVal);
+
+    /* Set camera memory start address, memory size and frame size in burst */
+    BL_WR_REG(CAM_BASE, CAM_DVP2AHB_ADDR_START_0, cfg->memStart0 & 0xFFFFFFF0);
+
+    if (cfg->burstType == CAM_BURST_TYPE_SINGLE) {
+        BL_WR_REG(CAM_BASE, CAM_DVP2AHB_MEM_BCNT_0, cfg->memSize0 / 4);
+        BL_WR_REG(CAM_BASE, CAM_DVP2AHB_FRAME_BCNT_0, cfg->frameSize0 / 4);
+    } else if (cfg->burstType == CAM_BURST_TYPE_INCR4) {
+        BL_WR_REG(CAM_BASE, CAM_DVP2AHB_MEM_BCNT_0, cfg->memSize0 / 16);
+        BL_WR_REG(CAM_BASE, CAM_DVP2AHB_FRAME_BCNT_0, cfg->frameSize0 / 16);
+    } else if (cfg->burstType == CAM_BURST_TYPE_INCR8) {
+        BL_WR_REG(CAM_BASE, CAM_DVP2AHB_MEM_BCNT_0, cfg->memSize0 / 32);
+        BL_WR_REG(CAM_BASE, CAM_DVP2AHB_FRAME_BCNT_0, cfg->frameSize0 / 32);
+    } else if (cfg->burstType == CAM_BURST_TYPE_INCR16) {
+        BL_WR_REG(CAM_BASE, CAM_DVP2AHB_MEM_BCNT_0, cfg->memSize0 / 64);
+        BL_WR_REG(CAM_BASE, CAM_DVP2AHB_FRAME_BCNT_0, cfg->frameSize0 / 64);
+    }
+
+    if (!cfg->frameMode) {
+        BL_WR_REG(CAM_BASE, CAM_DVP2AHB_ADDR_START_1, cfg->memStart1 & 0xFFFFFFF0);
+
+        if (cfg->burstType == CAM_BURST_TYPE_SINGLE) {
+            BL_WR_REG(CAM_BASE, CAM_DVP2AHB_MEM_BCNT_1, cfg->memSize1 / 4);
+            BL_WR_REG(CAM_BASE, CAM_DVP2AHB_FRAME_BCNT_1, cfg->frameSize1 / 4);
+        } else if (cfg->burstType == CAM_BURST_TYPE_INCR4) {
+            BL_WR_REG(CAM_BASE, CAM_DVP2AHB_MEM_BCNT_1, cfg->memSize1 / 16);
+            BL_WR_REG(CAM_BASE, CAM_DVP2AHB_FRAME_BCNT_1, cfg->frameSize1 / 16);
+        } else if (cfg->burstType == CAM_BURST_TYPE_INCR8) {
+            BL_WR_REG(CAM_BASE, CAM_DVP2AHB_MEM_BCNT_1, cfg->memSize1 / 32);
+            BL_WR_REG(CAM_BASE, CAM_DVP2AHB_FRAME_BCNT_1, cfg->frameSize1 / 32);
+        } else if (cfg->burstType == CAM_BURST_TYPE_INCR16) {
+            BL_WR_REG(CAM_BASE, CAM_DVP2AHB_MEM_BCNT_1, cfg->memSize1 / 64);
+            BL_WR_REG(CAM_BASE, CAM_DVP2AHB_FRAME_BCNT_1, cfg->frameSize1 / 64);
+        }
+    }
+
+    /* Clear interrupt */
+    BL_WR_REG(CAM_BASE, CAM_DVP_FRAME_FIFO_POP, 0xFFFF0);
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(CAM_IRQn, CAM_IRQHandler);
+#endif
+}
+
+/****************************************************************************/ /**
+ * @brief  Deinit camera module
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void CAM_Deinit(void)
+{
+    //GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_CAM);
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable camera module
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void CAM_Enable(void)
+{
+    uint32_t tmpVal;
+
+    /* Enable camera module */
+    tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE);
+    tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DVP_ENABLE);
+    BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable camera module
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void CAM_Disable(void)
+{
+    uint32_t tmpVal;
+
+    /* Disable camera module */
+    tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DVP_ENABLE);
+    BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Camera clock gate function
+ *
+ * @param  enable: Enable or disable
+ *
+ * @return None
+ *
+*******************************************************************************/
+void CAM_Clock_Gate(BL_Fun_Type enable)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_DVP_PIX_CLK_CG, enable);
+    BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Camera hsync crop function
+ *
+ * @param  start: Valid hsync start count
+ * @param  end: Valid hsync end count
+ *
+ * @return None
+ *
+*******************************************************************************/
+void CAM_Hsync_Crop(uint16_t start, uint16_t end)
+{
+    BL_WR_REG(CAM_BASE, CAM_HSYNC_CONTROL, (start << 16) + end);
+}
+
+/****************************************************************************/ /**
+ * @brief  Camera vsync crop function
+ *
+ * @param  start: Valid vsync start count
+ * @param  end: Valid vsync end count
+ *
+ * @return None
+ *
+*******************************************************************************/
+void CAM_Vsync_Crop(uint16_t start, uint16_t end)
+{
+    BL_WR_REG(CAM_BASE, CAM_VSYNC_CONTROL, (start << 16) + end);
+}
+
+/****************************************************************************/ /**
+ * @brief  Camera set total valid pix count in a line function
+ *
+ * @param  count: Count value
+ *
+ * @return None
+ *
+*******************************************************************************/
+void CAM_Set_Hsync_Total_Count(uint16_t count)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(CAM_BASE, CAM_FRAME_SIZE_CONTROL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_TOTAL_HCNT, count);
+    BL_WR_REG(CAM_BASE, CAM_FRAME_SIZE_CONTROL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Camera set total valid line count in a frame function
+ *
+ * @param  count: Count value
+ *
+ * @return None
+ *
+*******************************************************************************/
+void CAM_Set_Vsync_Total_Count(uint16_t count)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(CAM_BASE, CAM_FRAME_SIZE_CONTROL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_TOTAL_VCNT, count);
+    BL_WR_REG(CAM_BASE, CAM_FRAME_SIZE_CONTROL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Get one camera frame in interleave mode
+ *
+ * @param  info: Interleave mode camera frame infomation pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void CAM_Interleave_Get_Frame_Info(CAM_Interleave_Frame_Info *info)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP_STATUS_AND_ERROR);
+
+    info->validFrames = BL_GET_REG_BITS_VAL(tmpVal, CAM_FRAME_VALID_CNT_0);
+    info->curFrameAddr = BL_RD_REG(CAM_BASE, CAM_FRAME_START_ADDR0_0);
+    info->curFrameBytes = BL_RD_REG(CAM_BASE, CAM_FRAME_BYTE_CNT0_0);
+    info->status = tmpVal;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get one camera frame in planar mode
+ *
+ * @param  info: Planar mode camera frame infomation pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void CAM_Planar_Get_Frame_Info(CAM_Planar_Frame_Info *info)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP_STATUS_AND_ERROR);
+
+    info->validFrames0 = BL_GET_REG_BITS_VAL(tmpVal, CAM_FRAME_VALID_CNT_0);
+    info->validFrames1 = BL_GET_REG_BITS_VAL(tmpVal, CAM_FRAME_VALID_CNT_1);
+    info->curFrameAddr0 = BL_RD_REG(CAM_BASE, CAM_FRAME_START_ADDR0_0);
+    info->curFrameAddr1 = BL_RD_REG(CAM_BASE, CAM_FRAME_START_ADDR1_0);
+    info->curFrameBytes0 = BL_RD_REG(CAM_BASE, CAM_FRAME_BYTE_CNT0_0);
+    info->curFrameBytes1 = BL_RD_REG(CAM_BASE, CAM_FRAME_BYTE_CNT1_0);
+    info->status = tmpVal;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get available count 0 of frames
+ *
+ * @param  None
+ *
+ * @return Frames count
+ *
+*******************************************************************************/
+uint8_t CAM_Get_Frame_Count_0(void)
+{
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(CAM_BASE, CAM_DVP_STATUS_AND_ERROR), CAM_FRAME_VALID_CNT_0);
+}
+
+/****************************************************************************/ /**
+ * @brief  Get available count 1 of frames
+ *
+ * @param  None
+ *
+ * @return Frames count
+ *
+*******************************************************************************/
+uint8_t CAM_Get_Frame_Count_1(void)
+{
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(CAM_BASE, CAM_DVP_STATUS_AND_ERROR), CAM_FRAME_VALID_CNT_1);
+}
+
+/****************************************************************************/ /**
+ * @brief  Pop one camera frame in interleave mode
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void CAM_Interleave_Pop_Frame(void)
+{
+    /* Pop one frame */
+    BL_WR_REG(CAM_BASE, CAM_DVP_FRAME_FIFO_POP, 1);
+}
+
+/****************************************************************************/ /**
+ * @brief  Pop one camera frame in planar mode
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void CAM_Planar_Pop_Frame(void)
+{
+    /* Pop one frame */
+    BL_WR_REG(CAM_BASE, CAM_DVP_FRAME_FIFO_POP, 3);
+}
+
+/****************************************************************************/ /**
+ * @brief  CAMERA Enable Disable Interrupt
+ *
+ * @param  intType: CAMERA Interrupt Type
+ * @param  intMask: Enable or Disable
+ *
+ * @return None
+ *
+*******************************************************************************/
+void CAM_IntMask(CAM_INT_Type intType, BL_Mask_Type intMask)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_CAM_INT_TYPE(intType));
+    CHECK_PARAM(IS_BL_MASK_TYPE(intMask));
+
+    tmpVal = BL_RD_REG(CAM_BASE, CAM_INT_CONTROL);
+
+    switch (intType) {
+        case CAM_INT_NORMAL_0:
+            if (intMask == UNMASK) {
+                /* Enable this interrupt */
+                tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_0_EN);
+            } else {
+                /* Disable this interrupt */
+                tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_0_EN);
+            }
+
+            break;
+
+        case CAM_INT_NORMAL_1:
+            if (intMask == UNMASK) {
+                /* Enable this interrupt */
+                tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_1_EN);
+            } else {
+                /* Disable this interrupt */
+                tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_1_EN);
+            }
+
+            break;
+
+        case CAM_INT_MEMORY_OVERWRITE_0:
+        case CAM_INT_MEMORY_OVERWRITE_1:
+            if (intMask == UNMASK) {
+                /* Enable this interrupt */
+                tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_MEM_EN);
+            } else {
+                /* Disable this interrupt */
+                tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_MEM_EN);
+            }
+
+            break;
+
+        case CAM_INT_FRAME_OVERWRITE_0:
+        case CAM_INT_FRAME_OVERWRITE_1:
+            if (intMask == UNMASK) {
+                /* Enable this interrupt */
+                tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FRAME_EN);
+            } else {
+                /* Disable this interrupt */
+                tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_FRAME_EN);
+            }
+
+            break;
+
+        case CAM_INT_FIFO_OVERWRITE_0:
+        case CAM_INT_FIFO_OVERWRITE_1:
+            if (intMask == UNMASK) {
+                /* Enable this interrupt */
+                tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FIFO_EN);
+            } else {
+                /* Disable this interrupt */
+                tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_FIFO_EN);
+            }
+
+            break;
+
+        case CAM_INT_VSYNC_CNT_ERROR:
+            if (intMask == UNMASK) {
+                /* Enable this interrupt */
+                tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_VCNT_EN);
+            } else {
+                /* Disable this interrupt */
+                tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_VCNT_EN);
+            }
+
+            break;
+
+        case CAM_INT_HSYNC_CNT_ERROR:
+            if (intMask == UNMASK) {
+                /* Enable this interrupt */
+                tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_HCNT_EN);
+            } else {
+                /* Disable this interrupt */
+                tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_HCNT_EN);
+            }
+
+            break;
+
+        case CAM_INT_ALL:
+            if (intMask == UNMASK) {
+                /* Enable all interrupt */
+                tmpVal |= 0x7F;
+            } else {
+                /* Disable all interrupt */
+                tmpVal &= 0xFFFFFF80;
+            }
+
+            break;
+
+        default:
+            break;
+    }
+
+    BL_WR_REG(CAM_BASE, CAM_INT_CONTROL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  CAMERA Interrupt Clear
+ *
+ * @param  intType: CAMERA Interrupt Type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void CAM_IntClr(CAM_INT_Type intType)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP_FRAME_FIFO_POP);
+
+    switch (intType) {
+        case CAM_INT_NORMAL_0:
+            tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_CLR_0);
+            break;
+
+        case CAM_INT_NORMAL_1:
+            tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_CLR_1);
+            break;
+
+        case CAM_INT_MEMORY_OVERWRITE_0:
+            tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_MEM_CLR_0);
+            break;
+
+        case CAM_INT_MEMORY_OVERWRITE_1:
+            tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_MEM_CLR_1);
+            break;
+
+        case CAM_INT_FRAME_OVERWRITE_0:
+            tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FRAME_CLR_0);
+            break;
+
+        case CAM_INT_FRAME_OVERWRITE_1:
+            tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FRAME_CLR_1);
+            break;
+
+        case CAM_INT_FIFO_OVERWRITE_0:
+            tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FIFO_CLR_0);
+            break;
+
+        case CAM_INT_FIFO_OVERWRITE_1:
+            tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FIFO_CLR_1);
+            break;
+
+        case CAM_INT_VSYNC_CNT_ERROR:
+            tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_VCNT_CLR_0);
+            break;
+
+        case CAM_INT_HSYNC_CNT_ERROR:
+            tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_HCNT_CLR_0);
+            break;
+
+        case CAM_INT_ALL:
+            tmpVal = 0xFFFF0;
+
+        default:
+            break;
+    }
+
+    BL_WR_REG(CAM_BASE, CAM_DVP_FRAME_FIFO_POP, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Install camera interrupt callback function
+ *
+ * @param  intType: CAMERA interrupt type
+ * @param  cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
+ *
+ * @return None
+ *
+*******************************************************************************/
+void CAM_Int_Callback_Install(CAM_INT_Type intType, intCallback_Type *cbFun)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_CAM_INT_TYPE(intType));
+
+    camIntCbfArra[intType] = cbFun;
+}
+
+/****************************************************************************/ /**
+ * @brief  CAM hardware mode with frame start address wrap to memory address start function enable or disable
+ *
+ * @param  enable: Enable or disable
+ * @return None
+ *
+*******************************************************************************/
+void CAM_HW_Mode_Wrap(BL_Fun_Type enable)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_HW_MODE_FWRAP, enable);
+    BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Camera interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void CAM_IRQHandler(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP_STATUS_AND_ERROR);
+
+    if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_NORMAL_INT_0)) {
+        CAM_IntClr(CAM_INT_NORMAL_0);
+
+        if (camIntCbfArra[CAM_INT_NORMAL_0] != NULL) {
+            /* call the callback function */
+            camIntCbfArra[CAM_INT_NORMAL_0]();
+        }
+    }
+
+    if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_NORMAL_INT_1)) {
+        CAM_IntClr(CAM_INT_NORMAL_1);
+
+        if (camIntCbfArra[CAM_INT_NORMAL_1] != NULL) {
+            /* call the callback function */
+            camIntCbfArra[CAM_INT_NORMAL_1]();
+        }
+    }
+
+    if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_MEM_INT_0)) {
+        CAM_IntClr(CAM_INT_MEMORY_OVERWRITE_0);
+
+        if (camIntCbfArra[CAM_INT_MEMORY_OVERWRITE_0] != NULL) {
+            /* call the callback function */
+            camIntCbfArra[CAM_INT_MEMORY_OVERWRITE_0]();
+        }
+    }
+
+    if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_MEM_INT_1)) {
+        CAM_IntClr(CAM_INT_MEMORY_OVERWRITE_1);
+
+        if (camIntCbfArra[CAM_INT_MEMORY_OVERWRITE_1] != NULL) {
+            /* call the callback function */
+            camIntCbfArra[CAM_INT_MEMORY_OVERWRITE_1]();
+        }
+    }
+
+    if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FRAME_INT_0)) {
+        CAM_IntClr(CAM_INT_FRAME_OVERWRITE_0);
+
+        if (camIntCbfArra[CAM_INT_FRAME_OVERWRITE_0] != NULL) {
+            /* call the callback function */
+            camIntCbfArra[CAM_INT_FRAME_OVERWRITE_0]();
+        }
+    }
+
+    if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FRAME_INT_1)) {
+        CAM_IntClr(CAM_INT_FRAME_OVERWRITE_1);
+
+        if (camIntCbfArra[CAM_INT_FRAME_OVERWRITE_1] != NULL) {
+            /* call the callback function */
+            camIntCbfArra[CAM_INT_FRAME_OVERWRITE_1]();
+        }
+    }
+
+    if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FIFO_INT_0)) {
+        CAM_IntClr(CAM_INT_FIFO_OVERWRITE_0);
+
+        if (camIntCbfArra[CAM_INT_FIFO_OVERWRITE_0] != NULL) {
+            /* call the callback function */
+            camIntCbfArra[CAM_INT_FIFO_OVERWRITE_0]();
+        }
+    }
+
+    if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FIFO_INT_1)) {
+        CAM_IntClr(CAM_INT_FIFO_OVERWRITE_1);
+
+        if (camIntCbfArra[CAM_INT_FIFO_OVERWRITE_1] != NULL) {
+            /* call the callback function */
+            camIntCbfArra[CAM_INT_FIFO_OVERWRITE_1]();
+        }
+    }
+
+    if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_HCNT_INT)) {
+        CAM_IntClr(CAM_INT_HSYNC_CNT_ERROR);
+
+        if (camIntCbfArra[CAM_INT_HSYNC_CNT_ERROR] != NULL) {
+            /* call the callback function */
+            camIntCbfArra[CAM_INT_HSYNC_CNT_ERROR]();
+        }
+    }
+
+    if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_VCNT_INT)) {
+        CAM_IntClr(CAM_INT_VSYNC_CNT_ERROR);
+
+        if (camIntCbfArra[CAM_INT_VSYNC_CNT_ERROR] != NULL) {
+            /* call the callback function */
+            camIntCbfArra[CAM_INT_VSYNC_CNT_ERROR]();
+        }
+    }
+}
+#endif
+
+/*@} end of group CAM_Public_Functions */
+
+/*@} end of group CAM */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_clock.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_clock.c
new file mode 100644
index 00000000..ce869738
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_clock.c
@@ -0,0 +1,166 @@
+/**
+  ******************************************************************************
+  * @file    bl702_clock.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_clock.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  CLOCK
+ *  @{
+ */
+
+/** @defgroup  CLOCK_Private_Macros
+ *  @{
+ */
+
+/*@} end of group CLOCK_Private_Macros */
+
+/** @defgroup  CLOCK_Private_Types
+ *  @{
+ */
+
+/*@} end of group CLOCK_Private_Types */
+
+/** @defgroup  CLOCK_Private_Variables
+ *  @{
+ */
+static Clock_Cfg_Type clkCfg;
+
+/*@} end of group CLOCK_Private_Variables */
+
+/** @defgroup  CLOCK_Global_Variables
+ *  @{
+ */
+
+/*@} end of group CLOCK_Global_Variables */
+
+/** @defgroup  CLOCK_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group CLOCK_Private_Fun_Declaration */
+
+/** @defgroup  CLOCK_Private_Functions
+ *  @{
+ */
+
+/*@} end of group CLOCK_Private_Functions */
+
+/** @defgroup  CLOCK_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Set System Clock
+ *
+ * @param  type: System clock type
+ * @param  clock: System clock value
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Clock_System_Clock_Set(BL_System_Clock_Type type, uint32_t clock)
+{
+    if (type < BL_SYSTEM_CLOCK_MAX) {
+        clkCfg.systemClock[type] = clock / 1000000;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Set Peripheral Clock
+ *
+ * @param  type: Peripheral clock type
+ * @param  clock: Peripheral clock value
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Clock_Peripheral_Clock_Set(BL_AHB_Slave1_Type type, uint32_t clock)
+{
+    if (type < BL_AHB_SLAVE1_MAX) {
+        if (type == BL_AHB_SLAVE1_I2S) {
+            clkCfg.i2sClock = clock;
+        } else {
+            clkCfg.peripheralClock[type] = clock / 1000000;
+        }
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Get System Clock
+ *
+ * @param  type: System clock type
+ *
+ * @return System clock value
+ *
+*******************************************************************************/
+uint32_t Clock_System_Clock_Get(BL_System_Clock_Type type)
+{
+    if (type < BL_SYSTEM_CLOCK_MAX) {
+        return clkCfg.systemClock[type] * 1000000;
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get Peripheral Clock
+ *
+ * @param  type: Peripheral clock type
+ *
+ * @return Peripheral clock value
+ *
+*******************************************************************************/
+uint32_t Clock_Peripheral_Clock_Get(BL_AHB_Slave1_Type type)
+{
+    if (type < BL_AHB_SLAVE1_MAX) {
+        if (type == BL_AHB_SLAVE1_I2S) {
+            return clkCfg.i2sClock;
+        } else {
+            return clkCfg.peripheralClock[type] * 1000000;
+        }
+    }
+
+    return 0;
+}
+
+/*@} end of group CLOCK_Public_Functions */
+
+/*@} end of group CLOCK */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_common.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_common.c
new file mode 100644
index 00000000..a9fafc03
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_common.c
@@ -0,0 +1,204 @@
+/**
+  ******************************************************************************
+  * @file    bl702_common.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#include "l1c_reg.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Periph_Driver
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief      delay us
+ *
+ * @param[in]  core:  systemcoreclock
+ *
+ * @param[in]  cnt:  delay cnt us
+ *
+ * @return none
+ *
+ *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+#ifdef ARCH_ARM
+#ifndef __GNUC__
+__WEAK
+__ASM void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt)
+{
+    lsrs r0, #0x10 muls r0, r1, r0 mov r2, r0 lsrs r2, #0x04 lsrs r2, #0x03 cmp r2, #0x01 beq end cmp r2, #0x00 beq end loop mov r0, r0 mov r0, r0 mov r0, r0 mov r0, r0 mov r0, r0 subs r2, r2, #0x01 cmp r2, #0x00 bne loop end bx lr
+}
+#else
+__WEAK
+void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt)
+{
+    __asm__ __volatile__(
+        "lsr r0,#0x10\n\t"
+        "mul r0,r1,r0\n\t"
+        "mov r2,r0\n\t"
+        "lsr r2,#0x04\n\t"
+        "lsr r2,#0x03\n\t"
+        "cmp r2,#0x01\n\t"
+        "beq end\n\t"
+        "cmp r2,#0x00\n\t"
+        "beq end\n"
+        "loop :"
+        "mov r0,r0\n\t"
+        "mov r0,r0\n\t"
+        "mov r0,r0\n\t"
+        "mov r0,r0\n\t"
+        "mov r0,r0\n\t"
+        "sub r2,r2,#0x01\n\t"
+        "cmp r2,#0x00\n\t"
+        "bne loop\n"
+        "end :"
+        "mov r0,r0\n\t");
+}
+#endif
+#endif
+#ifdef ARCH_RISCV
+__WEAK
+void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt)
+{
+    uint32_t codeAddress = 0;
+    uint32_t divVal = 40;
+
+    codeAddress = (uint32_t)&ASM_Delay_Us;
+
+    /* 1M=100K*10, so multiple is 10 */
+    /* loop function take 4 instructions, so instructionNum is 4 */
+    /* if codeAddress locate at IROM space and irom_2t_access is 1, then irom2TAccess=2, else irom2TAccess=1 */
+    /* divVal = multiple*instructionNum*irom2TAccess */
+    if (((codeAddress & (0xF << 24)) >> 24) == 0x01) {
+        /* IROM space */
+        if (BL_GET_REG_BITS_VAL(BL_RD_REG(L1C_BASE, L1C_CONFIG), L1C_IROM_2T_ACCESS)) {
+            /* instruction 2T */
+            divVal = 80;
+        }
+    }
+
+    __asm__ __volatile__(
+        ".align 4\n\t"
+        "lw       a4,%1\n\t"
+        "lui   a5,0x18\n\t"
+        "addi  a5,a5,1696\n\t"
+        "divu  a5,a4,a5\n\t"
+        "sw       a5,%1\n\t"
+        "lw       a4,%1\n\t"
+        "lw       a5,%0\n\t"
+        "mul   a5,a4,a5\n\t"
+        "sw       a5,%1\n\t"
+        "lw       a4,%1\n\t"
+        "lw       a5,%2\n\t"
+        "divu  a5,a4,a5\n\t"
+        "sw    a5,%1\n\t"
+        "lw    a5,%1\n\t"
+        "li    a4,0x1\n\t"
+        "beq   a5,zero,end\n\t"
+        "beq   a5,a4,end\n\t"
+        "nop\n\t"
+        "nop\n\t"
+        ".align 4\n\t"
+        "loop  :\n"
+        "addi  a4,a5,-1\n\t"
+        "mv    a5,a4\n\t"
+        "bnez  a5,loop\n\t"
+        "nop\n\t"
+        "end   :\n\t"
+        "nop\n"
+        :                                  /* output */
+        : "m"(cnt), "m"(core), "m"(divVal) /* input */
+        : "t1", "a4", "a5"                 /* destruct description */
+    );
+}
+#endif
+#endif
+
+/****************************************************************************/ /**
+ * @brief      delay us
+ *
+ * @param[in]  cnt:  delay cnt us
+ *
+ * @return none
+ *
+ *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION BL702_Delay_US(uint32_t cnt)
+{
+    ASM_Delay_Us(SystemCoreClockGet(), cnt);
+}
+#endif
+/****************************************************************************/ /**
+ * @brief      delay ms
+ *
+ * @param[in]  cnt:  delay cnt ms
+ *
+ * @return none
+ *
+ *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION BL702_Delay_MS(uint32_t cnt)
+{
+    uint32_t i = 0;
+    uint32_t count = 0;
+
+    if (cnt >= 1024) {
+        /* delay (n*1024) ms */
+        count = 1024;
+
+        for (i = 0; i < (cnt / 1024); i++) {
+            BL702_Delay_US(1024 * 1000);
+        }
+    }
+
+    if (cnt & 0x3FF) {
+        /* delay (1-1023)ms */
+        count = cnt & 0x3FF;
+        BL702_Delay_US(count * 1000);
+    }
+
+    //BL702_Delay_US(((cnt<<10)-(cnt<<4)-(cnt<<3)));
+}
+#endif
+
+/*
+char *_sbrk(int incr)
+{}
+*/
+/*@} end of group DRIVER_Public_Functions */
+
+/*@} end of group DRIVER_COMMON */
+
+/*@} end of group BL702_Periph_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_dac.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_dac.c
new file mode 100644
index 00000000..943b135f
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_dac.c
@@ -0,0 +1,518 @@
+/**
+  ******************************************************************************
+  * @file    bl702_dac.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_dac.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  DAC
+ *  @{
+ */
+
+/** @defgroup  DAC_Private_Macros
+ *  @{
+ */
+#define GPIP_CLK_SET_DUMMY_WAIT \
+    {                           \
+        __NOP();                \
+        __NOP();                \
+        __NOP();                \
+        __NOP();                \
+        __NOP();                \
+        __NOP();                \
+        __NOP();                \
+        __NOP();                \
+    }
+
+/*@} end of group DAC_Private_Macros */
+
+/** @defgroup  DAC_Private_Types
+ *  @{
+ */
+
+/*@} end of group DAC_Private_Types */
+
+/** @defgroup  DAC_Private_Variables
+ *  @{
+ */
+
+/*@} end of group DAC_Private_Variables */
+
+/** @defgroup  DAC_Global_Variables
+ *  @{
+ */
+
+/*@} end of group DAC_Global_Variables */
+
+/** @defgroup  DAC_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group DAC_Private_Fun_Declaration */
+
+/** @defgroup  DAC_Private_Functions
+ *  @{
+ */
+
+/*@} end of group DAC_Private_Functions */
+
+/** @defgroup  DAC_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  DAC initialization
+ *
+ * @param  cfg: DAC configuration pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void GLB_DAC_Init(GLB_DAC_Cfg_Type *cfg)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_GLB_DAC_REF_SEL_TYPE(cfg->refSel));
+
+    /* Set DAC config */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_REF_SEL, cfg->refSel);
+
+    if (ENABLE == cfg->resetChanA) {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA);
+        tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal);
+        __NOP();
+        __NOP();
+        __NOP();
+        __NOP();
+    }
+
+    if (ENABLE == cfg->resetChanB) {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA);
+        tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal);
+        __NOP();
+        __NOP();
+        __NOP();
+        __NOP();
+    }
+
+    /* Clear reset */
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA);
+    tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  DAC channel A initialization
+ *
+ * @param  cfg: DAC channel configuration pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void GLB_DAC_Set_ChanA_Config(GLB_DAC_Chan_Cfg_Type *cfg)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_GLB_DAC_CHAN_TYPE(cfg->outMux));
+
+    /* Set channel A config */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_ACTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_OUTMUX, cfg->outMux);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOA_EN, cfg->outputEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_EN, cfg->chanEn);
+
+    tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_ACTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  DAC channel B initialization
+ *
+ * @param  cfg: DAC channel configuration pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void GLB_DAC_Set_ChanB_Config(GLB_DAC_Chan_Cfg_Type *cfg)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_GLB_DAC_CHAN_TYPE(cfg->outMux));
+
+    /* Set channel A config */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_BCTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_OUTMUX, cfg->outMux);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOB_EN, cfg->outputEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_EN, cfg->chanEn);
+
+    tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_BCTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Select DAC channel B source
+ *
+ * @param  src: DAC channel B source selection type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void GPIP_Set_DAC_ChanB_SRC_SEL(GPIP_DAC_ChanB_SRC_Type src)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GPIP_DAC_CHANB_SRC_TYPE(src));
+
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_B_SEL, src);
+    BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Select DAC channel A source
+ *
+ * @param  src: DAC channel A source selection type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void GPIP_Set_DAC_ChanA_SRC_SEL(GPIP_DAC_ChanA_SRC_Type src)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GPIP_DAC_CHANA_SRC_TYPE(src));
+
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_A_SEL, src);
+    BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable DAC channel B
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void GPIP_DAC_ChanB_Enable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_EN2);
+    BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable DAC channel B
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void GPIP_DAC_ChanB_Disable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_EN2);
+    BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable DAC channel A
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void GPIP_DAC_ChanA_Enable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_EN);
+    BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable DAC channel A
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void GPIP_DAC_ChanA_Disable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_EN);
+    BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Select DAC DMA TX format
+ *
+ * @param  fmt: DAC DMA TX format selection type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void GPIP_Set_DAC_DMA_TX_FORMAT_SEL(GPIP_DAC_DMA_TX_FORMAT_Type fmt)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(fmt));
+
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_FORMAT, fmt);
+    BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable DAC DMA TX
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void GPIP_Set_DAC_DMA_TX_Enable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_DMA_TX_EN);
+    BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable DAC DMA TX
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void GPIP_Set_DAC_DMA_TX_Disable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_DMA_TX_EN);
+    BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable DAC DMA TX
+ *
+ * @param  data: The data to be send
+ *
+ * @return None
+ *
+*******************************************************************************/
+void GPIP_DAC_DMA_WriteData(uint32_t data)
+{
+    BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_WDATA, data);
+}
+
+/****************************************************************************/ /**
+ * @brief  AON and GPIP DAC config
+ *
+ * @param  cfg: AON and GPIP DAC configuration
+ *
+ * @return config success or not
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIP_DAC_Init(GLB_GPIP_DAC_Cfg_Type *cfg)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GLB_DAC_REF_SEL_TYPE(cfg->refSel));
+    CHECK_PARAM(IS_GPIP_DAC_MOD_TYPE(cfg->div));
+    CHECK_PARAM(IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(cfg->dmaFmt));
+
+    /* AON Set DAC config */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_REF_SEL, cfg->refSel);
+
+    if (ENABLE == cfg->resetChanA) {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA);
+        tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal);
+        __NOP();
+        __NOP();
+        __NOP();
+        __NOP();
+    }
+
+    if (ENABLE == cfg->resetChanB) {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA);
+        tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal);
+        __NOP();
+        __NOP();
+        __NOP();
+        __NOP();
+    }
+
+    /* AON Clear reset */
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA);
+    tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal);
+
+    /* GPIP Set DAC config */
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_MODE, cfg->div);
+    BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
+
+    /* GPIP Set DMA config */
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_TX_EN, cfg->dmaEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_FORMAT, cfg->dmaFmt);
+    BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  AON and GPIP DAC channel A config
+ *
+ * @param  cfg: AON and GPIP DAC channel A configuration
+ *
+ * @return None
+ *
+*******************************************************************************/
+void GLB_GPIP_DAC_Set_ChanA_Config(GLB_GPIP_DAC_ChanA_Cfg_Type *cfg)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GPIP_DAC_CHANA_SRC_TYPE(cfg->src));
+
+    /* GPIP select source */
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_A_SEL, cfg->src);
+    BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
+
+    /* GPIP enable or disable channel */
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_EN, cfg->chanEn);
+    BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
+
+    /* AON enable or disable channel */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_ACTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOA_EN, cfg->outputEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_EN, cfg->chanCovtEn);
+    tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_ACTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  AON and GPIP DAC channel B config
+ *
+ * @param  cfg: AON and GPIP DAC channel B configuration
+ *
+ * @return None
+ *
+*******************************************************************************/
+void GLB_GPIP_DAC_Set_ChanB_Config(GLB_GPIP_DAC_ChanB_Cfg_Type *cfg)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GPIP_DAC_CHANB_SRC_TYPE(cfg->src));
+
+    /* GPIP select source */
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_B_SEL, cfg->src);
+    BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
+
+    /* GPIP enable or disable channel */
+    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_EN2, cfg->chanEn);
+    BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
+
+    /* AON enable or disable channel */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_BCTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOB_EN, cfg->outputEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_EN, cfg->chanCovtEn);
+    tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_BCTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  DAC channel A set value
+ *
+ * @param  val: DAC value
+ *
+ * @return None
+ *
+*******************************************************************************/
+void GLB_DAC_Set_ChanA_Value(uint16_t val)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_DATA);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_DATA, val);
+    tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_DATA, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  DAC channel B set value
+ *
+ * @param  val: DAC value
+ *
+ * @return None
+ *
+*******************************************************************************/
+void GLB_DAC_Set_ChanB_Value(uint16_t val)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_DATA);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_DATA, val);
+    tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_DATA, tmpVal);
+}
+
+/*@} end of group DAC_Public_Functions */
+
+/*@} end of group DAC */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_dma.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_dma.c
new file mode 100644
index 00000000..d985ccc1
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_dma.c
@@ -0,0 +1,750 @@
+/**
+  ******************************************************************************
+  * @file    bl702_dma.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702.h"
+#include "bl702_dma.h"
+#include "string.h"
+#include "bl702_glb.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  DMA
+ *  @{
+ */
+
+/** @defgroup  DMA_Private_Macros
+ *  @{
+ */
+#define DMA_CHANNEL_OFFSET  0x100
+#define DMA_Get_Channel(ch) (DMA_BASE + DMA_CHANNEL_OFFSET + (ch)*0x100)
+static intCallback_Type *dmaIntCbfArra[DMA_CH_MAX][DMA_INT_ALL] = {
+    { NULL, NULL },
+    { NULL, NULL },
+    { NULL, NULL },
+    { NULL, NULL }
+};
+static DMA_LLI_Ctrl_Type PingPongListArra[DMA_CH_MAX][2];
+
+/*@} end of group DMA_Private_Macros */
+
+/** @defgroup  DMA_Private_Types
+ *  @{
+ */
+
+/*@} end of group DMA_Private_Types */
+
+/** @defgroup  DMA_Private_Variables
+ *  @{
+ */
+
+/*@} end of group DMA_Private_Variables */
+
+/** @defgroup  DMA_Global_Variables
+ *  @{
+ */
+
+/*@} end of group DMA_Global_Variables */
+
+/** @defgroup  DMA_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group DMA_Private_Fun_Declaration */
+
+/** @defgroup  DMA_Private_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  DMA interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void DMA_ALL_IRQHandler(void)
+{
+    uint32_t tmpVal;
+    uint32_t intClr;
+    uint8_t ch;
+    /* Get DMA register */
+    uint32_t DMAChs = DMA_BASE;
+
+    for (ch = 0; ch < DMA_CH_MAX; ch++) {
+        tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS);
+
+        if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << ch)) != 0) {
+            /* Clear interrupt */
+            tmpVal = BL_RD_REG(DMAChs, DMA_INTTCCLEAR);
+            intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR);
+            intClr |= (1 << ch);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR, intClr);
+            BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpVal);
+
+            if (dmaIntCbfArra[ch][DMA_INT_TCOMPLETED] != NULL) {
+                /* Call the callback function */
+                dmaIntCbfArra[ch][DMA_INT_TCOMPLETED]();
+            }
+        }
+    }
+
+    for (ch = 0; ch < DMA_CH_MAX; ch++) {
+        tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS);
+
+        if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << ch)) != 0) {
+            /*Clear interrupt */
+            tmpVal = BL_RD_REG(DMAChs, DMA_INTERRCLR);
+            intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR);
+            intClr |= (1 << ch);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR, intClr);
+            BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpVal);
+
+            if (dmaIntCbfArra[ch][DMA_INT_ERR] != NULL) {
+                /* Call the callback function */
+                dmaIntCbfArra[ch][DMA_INT_ERR]();
+            }
+        }
+    }
+}
+#endif
+
+/*@} end of group DMA_Private_Functions */
+
+/** @defgroup  DMA_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  DMA enable
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void DMA_Enable(void)
+{
+    uint32_t tmpVal;
+    /* Get DMA register */
+    uint32_t DMAChs = DMA_BASE;
+
+    tmpVal = BL_RD_REG(DMAChs, DMA_TOP_CONFIG);
+    tmpVal = BL_SET_REG_BIT(tmpVal, DMA_E);
+    BL_WR_REG(DMAChs, DMA_TOP_CONFIG, tmpVal);
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(DMA_ALL_IRQn, DMA_ALL_IRQHandler);
+#endif
+}
+
+/****************************************************************************/ /**
+ * @brief  DMA disable
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void DMA_Disable(void)
+{
+    uint32_t tmpVal;
+    /* Get DMA register */
+    uint32_t DMAChs = DMA_BASE;
+
+    tmpVal = BL_RD_REG(DMAChs, DMA_TOP_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_E);
+    BL_WR_REG(DMAChs, DMA_TOP_CONFIG, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  DMA channel init
+ *
+ * @param  chCfg: DMA configuration
+ *
+ * @return None
+ *
+*******************************************************************************/
+void DMA_Channel_Init(DMA_Channel_Cfg_Type *chCfg)
+{
+    uint32_t tmpVal;
+    /* Get channel register */
+    uint32_t DMAChs = DMA_Get_Channel(chCfg->ch);
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_DMA_CHAN_TYPE(chCfg->ch));
+    CHECK_PARAM(IS_DMA_TRANS_WIDTH_TYPE(chCfg->srcTransfWidth));
+    CHECK_PARAM(IS_DMA_TRANS_WIDTH_TYPE(chCfg->dstTransfWidth));
+    CHECK_PARAM(IS_DMA_BURST_SIZE_TYPE(chCfg->srcBurstSzie));
+    CHECK_PARAM(IS_DMA_BURST_SIZE_TYPE(chCfg->dstBurstSzie));
+    CHECK_PARAM(IS_DMA_TRANS_DIR_TYPE(chCfg->dir));
+    CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(chCfg->dstPeriph));
+    CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(chCfg->srcPeriph));
+
+    /* Disable clock gate */
+    GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_DMA);
+
+    /* Config channel config */
+    BL_WR_REG(DMAChs, DMA_SRCADDR, chCfg->srcDmaAddr);
+    BL_WR_REG(DMAChs, DMA_DSTADDR, chCfg->destDmaAddr);
+
+    tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, chCfg->transfLength);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SWIDTH, chCfg->srcTransfWidth);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DWIDTH, chCfg->dstTransfWidth);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SBSIZE, chCfg->srcBurstSzie);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DBSIZE, chCfg->dstBurstSzie);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DST_ADD_MODE, chCfg->dstAddMode);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DST_MIN_MODE, chCfg->dstMinMode);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_FIX_CNT, chCfg->fixCnt);
+
+    /* FIXME: how to deal with SLargerD */
+    tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_SLARGERD);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SI, chCfg->srcAddrInc);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DI, chCfg->destAddrInc);
+    BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);
+
+    tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_FLOWCNTRL, chCfg->dir);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DSTPERIPHERAL, chCfg->dstPeriph);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SRCPERIPHERAL, chCfg->srcPeriph);
+    BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  DMA channel update source memory address and len
+ *
+ * @param  ch: DMA channel
+ * @param  memAddr: source memoty address
+ * @param  len: source memory data length
+ *
+ * @return None
+ *
+*******************************************************************************/
+void DMA_Channel_Update_SrcMemcfg(uint8_t ch, uint32_t memAddr, uint32_t len)
+{
+    uint32_t tmpVal;
+    /* Get channel register */
+    uint32_t DMAChs = DMA_Get_Channel(ch);
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));
+
+    /* config channel config*/
+    BL_WR_REG(DMAChs, DMA_SRCADDR, memAddr);
+    tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, len);
+    BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  DMA channel update destination memory address and len
+ *
+ * @param  ch: DMA channel
+ * @param  memAddr: destination memoty address
+ * @param  len: destination memory data length
+ *
+ * @return None
+ *
+*******************************************************************************/
+void DMA_Channel_Update_DstMemcfg(uint8_t ch, uint32_t memAddr, uint32_t len)
+{
+    uint32_t tmpVal;
+    /* Get channel register */
+    uint32_t DMAChs = DMA_Get_Channel(ch);
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));
+
+    /* config channel config*/
+    BL_WR_REG(DMAChs, DMA_DSTADDR, memAddr);
+    tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, len);
+    BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Get DMA channel tranfersize
+ *
+ * @param  ch: DMA channel
+ *
+ * @return tranfersize size
+ *
+*******************************************************************************/
+uint32_t DMA_Channel_TranferSize(uint8_t ch)
+{
+    /* Get channel register */
+    uint32_t DMAChs = DMA_Get_Channel(ch);
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));
+
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_TRANSFERSIZE);
+}
+
+/****************************************************************************/ /**
+ * @brief  Get DMA channel busy status
+ *
+ * @param  ch: DMA channel
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type DMA_Channel_Is_Busy(uint8_t ch)
+{
+    /* Get channel register */
+    uint32_t DMAChs = DMA_Get_Channel(ch);
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));
+
+    return BL_IS_REG_BIT_SET(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_E) == 1 ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  DMA enable
+ *
+ * @param  ch: DMA channel number
+ *
+ * @return None
+ *
+*******************************************************************************/
+void DMA_Channel_Enable(uint8_t ch)
+{
+    uint32_t tmpVal;
+    /* Get channel register */
+    uint32_t DMAChs = DMA_Get_Channel(ch);
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));
+
+    tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG);
+    tmpVal = BL_SET_REG_BIT(tmpVal, DMA_E);
+    BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  DMA disable
+ *
+ * @param  ch: DMA channel number
+ *
+ * @return None
+ *
+*******************************************************************************/
+void DMA_Channel_Disable(uint8_t ch)
+{
+    uint32_t tmpVal;
+    /* Get channel register */
+    uint32_t DMAChs = DMA_Get_Channel(ch);
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));
+
+    tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_E);
+    BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  DMA init LLI transfer
+ *
+ * @param  ch: DMA channel number
+ * @param  lliCfg: LLI configuration
+ *
+ * @return None
+ *
+*******************************************************************************/
+void DMA_LLI_Init(uint8_t ch, DMA_LLI_Cfg_Type *lliCfg)
+{
+    uint32_t tmpVal;
+    /* Get channel register */
+    uint32_t DMAChs = DMA_Get_Channel(ch);
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));
+    CHECK_PARAM(IS_DMA_TRANS_DIR_TYPE(lliCfg->dir));
+    CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(lliCfg->dstPeriph));
+    CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(lliCfg->srcPeriph));
+
+    /* Disable clock gate */
+    GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_DMA);
+
+    tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_FLOWCNTRL, lliCfg->dir);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DSTPERIPHERAL, lliCfg->dstPeriph);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SRCPERIPHERAL, lliCfg->srcPeriph);
+    BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  DMA channel update LLI
+ *
+ * @param  ch: DMA channel number
+ * @param  LLI: LLI addr
+ *
+ * @return None
+ *
+*******************************************************************************/
+void DMA_LLI_Update(uint8_t ch, uint32_t LLI)
+{
+    /* Get channel register */
+    uint32_t DMAChs = DMA_Get_Channel(ch);
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));
+
+    /* Config channel config */
+    //BL_WR_REG(DMAChs, DMA_LLI, LLI);
+    BL702_MemCpy4((uint32_t *)DMAChs, (uint32_t *)LLI, 4);
+}
+
+/****************************************************************************/ /**
+ * @brief  DMA LLI PingPong Structure Start
+ *
+ * @param  dmaPpStruct: dma pp struct pointer
+ * @param  Ping_Transfer_len: ping len
+ * @param  Pong_Transfer_len: pong len
+ *
+ * @return Succrss or not
+ *
+*******************************************************************************/
+BL_Err_Type DMA_LLI_PpStruct_Set_Transfer_Len(DMA_LLI_PP_Struct *dmaPpStruct, uint16_t Ping_Transfer_len, uint16_t Pong_Transfer_len)
+{
+    struct DMA_Control_Reg dmaCtrlRegVal_temp;
+
+    if (Ping_Transfer_len > 4096 || Pong_Transfer_len > 4096) {
+        return ERROR;
+    }
+
+    dmaCtrlRegVal_temp = PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl;
+    dmaCtrlRegVal_temp.TransferSize = Ping_Transfer_len;
+    PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl = dmaCtrlRegVal_temp;
+
+    dmaCtrlRegVal_temp = PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl;
+    dmaCtrlRegVal_temp.TransferSize = Pong_Transfer_len;
+    PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl = dmaCtrlRegVal_temp;
+
+    DMA_LLI_Init(dmaPpStruct->dmaChan, dmaPpStruct->DMA_LLI_Cfg);
+    DMA_LLI_Update(dmaPpStruct->dmaChan, (uint32_t)&PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX]);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  DMA LLI Start New Transmit for Ping-Pong Buf
+ *
+ * @param  dmaPpBuf: DMA LLI Ping-Pong Buf
+ *
+ * @return None
+ *
+*******************************************************************************/
+void DMA_LLI_PpBuf_Start_New_Transmit(DMA_LLI_PP_Buf *dmaPpBuf)
+{
+    CPU_Interrupt_Disable(DMA_ALL_IRQn);
+
+    if (dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex] != NULL) {
+        DMA_LLI_Update(dmaPpBuf->dmaChan, (uint32_t)dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex]);
+        DMA_Channel_Enable(dmaPpBuf->dmaChan);
+        dmaPpBuf->idleIndex = (dmaPpBuf->idleIndex == 0) ? 1 : 0;
+    }
+
+    CPU_Interrupt_Enable(DMA_ALL_IRQn);
+}
+
+/****************************************************************************/ /**
+ * @brief  DMA LLI Remove Completed Ping-Pong Buf List
+ *
+ * @param  dmaPpBuf: DMA LLI Ping-Pong Buf
+ *
+ * @return Next Ping-Pong Buf List Header
+ *
+*******************************************************************************/
+DMA_LLI_Ctrl_Type *DMA_LLI_PpBuf_Remove_Completed_List(DMA_LLI_PP_Buf *dmaPpBuf)
+{
+    CPU_Interrupt_Disable(DMA_ALL_IRQn);
+
+    dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex] = NULL;
+    CPU_Interrupt_Enable(DMA_ALL_IRQn);
+    return dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex];
+}
+
+/****************************************************************************/ /**
+ * @brief  DMA LLI Append Buf to List
+ *
+ * @param  dmaPpBuf: DMA LLI Ping-Pong Buf
+ * @param  dmaLliList: New LLI Buf to Append
+ *
+ * @return None
+ *
+*******************************************************************************/
+void DMA_LLI_PpBuf_Append(DMA_LLI_PP_Buf *dmaPpBuf, DMA_LLI_Ctrl_Type *dmaLliList)
+{
+    DMA_LLI_Ctrl_Type *pLliList = NULL;
+    CPU_Interrupt_Disable(DMA_ALL_IRQn);
+
+    pLliList = dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex];
+
+    if (pLliList == NULL) {
+        dmaLliList->nextLLI = 0;
+        dmaLliList->dmaCtrl.I = 1;
+        dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex] = dmaLliList;
+    } else {
+        /*Append to last */
+        while (pLliList->nextLLI != 0) {
+            pLliList = (DMA_LLI_Ctrl_Type *)pLliList->nextLLI;
+        }
+
+        pLliList->nextLLI = (uint32_t)dmaLliList;
+        pLliList->dmaCtrl.I = 0;
+        dmaLliList->nextLLI = 0;
+        dmaLliList->dmaCtrl.I = 1;
+    }
+
+    if (DMA_Channel_Is_Busy(dmaPpBuf->dmaChan) == RESET) {
+        /* DMA stopped: maybe stop just a few minutes ago(not enter INT due to CPU_Interrupt_Disable)
+           or has already stopped before this function is called */
+        if (dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex] == NULL) {
+            /* DMA has already stopped before this function is called */
+            DMA_LLI_PpBuf_Start_New_Transmit(dmaPpBuf);
+        }
+    }
+
+    CPU_Interrupt_Enable(DMA_ALL_IRQn);
+}
+
+/****************************************************************************/ /**
+ * @brief  DMA LLi Destroy Ping-Pong Buf
+ *
+ * @param  dmaPpBuf: DMA LLI Ping-Pong Buf
+ *
+ * @return None
+ *
+*******************************************************************************/
+void DMA_LLI_PpBuf_Destroy(DMA_LLI_PP_Buf *dmaPpBuf)
+{
+    /* DMA LLI Disable */
+    DMA_Channel_Disable(dmaPpBuf->dmaChan);
+
+    if (dmaPpBuf->lliListHeader[0] != NULL && dmaPpBuf->onTransCompleted != NULL) {
+        dmaPpBuf->onTransCompleted(dmaPpBuf->lliListHeader[0]);
+    }
+
+    dmaPpBuf->lliListHeader[0] = NULL;
+
+    if (dmaPpBuf->lliListHeader[1] != NULL && dmaPpBuf->onTransCompleted != NULL) {
+        dmaPpBuf->onTransCompleted(dmaPpBuf->lliListHeader[1]);
+    }
+
+    dmaPpBuf->lliListHeader[1] = NULL;
+    dmaPpBuf->idleIndex = 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Mask/Unmask the DMA interrupt
+ *
+ * @param  ch: DMA channel number
+ * @param  intType: Specifies the interrupt type
+ * @param  intMask: Enable/Disable Specified interrupt type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void DMA_IntMask(uint8_t ch, DMA_INT_Type intType, BL_Mask_Type intMask)
+{
+    uint32_t tmpVal;
+    /* Get channel register */
+    uint32_t DMAChs = DMA_Get_Channel(ch);
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));
+    CHECK_PARAM(IS_DMA_INT_TYPE(intType));
+
+    switch (intType) {
+        case DMA_INT_TCOMPLETED:
+            if (intMask == UNMASK) {
+                /* UNMASK(Enable) this interrupt */
+                tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_ITC);
+                BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
+                tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_I);
+                BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);
+            } else {
+                /* MASK(Disable) this interrupt */
+                tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_ITC);
+                BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
+                tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_I);
+                BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);
+            }
+
+            break;
+
+        case DMA_INT_ERR:
+            if (intMask == UNMASK) {
+                /* UNMASK(Enable) this interrupt */
+                tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_IE);
+                BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
+            } else {
+                /* MASK(Disable) this interrupt */
+                tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_IE);
+                BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
+            }
+
+            break;
+
+        case DMA_INT_ALL:
+            if (intMask == UNMASK) {
+                /* UNMASK(Enable) this interrupt */
+                tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_ITC);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_IE);
+                BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
+                tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL);
+                tmpVal = BL_SET_REG_BIT(tmpVal, DMA_I);
+                BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);
+            } else {
+                /* MASK(Disable) this interrupt */
+                tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, DMA_ITC);
+                tmpVal = BL_SET_REG_BIT(tmpVal, DMA_IE);
+                BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
+                tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_I);
+                BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);
+            }
+
+            break;
+
+        default:
+            break;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Install DMA interrupt callback function
+ *
+ * @param  dmaChan: DMA Channel type
+ * @param  intType: DMA interrupt type
+ * @param  cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
+ *
+ * @return None
+ *
+*******************************************************************************/
+void DMA_Int_Callback_Install(DMA_Chan_Type dmaChan, DMA_INT_Type intType, intCallback_Type *cbFun)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_DMA_CHAN_TYPE(dmaChan));
+    CHECK_PARAM(IS_DMA_INT_TYPE(intType));
+
+    dmaIntCbfArra[dmaChan][intType] = cbFun;
+}
+
+/****************************************************************************/ /**
+ * @brief  DMA LLI PingPong Structure Initial
+ *
+ * @param  dmaPpStruct: DMA LLI PingPong Config Parameter
+ *
+ * @return start success or not
+ *
+*******************************************************************************/
+BL_Err_Type DMA_LLI_PpStruct_Init(DMA_LLI_PP_Struct *dmaPpStruct)
+{
+    //setup lliList
+    dmaPpStruct->dmaCtrlRegVal.I = 1;
+    dmaPpStruct->trans_index = 0;
+
+    if (dmaPpStruct->DMA_LLI_Cfg->dir == DMA_TRNS_M2P) {
+        PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].srcDmaAddr = dmaPpStruct->chache_buf_addr[0];
+        PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].destDmaAddr = dmaPpStruct->operatePeriphAddr;
+
+        PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].srcDmaAddr = dmaPpStruct->chache_buf_addr[1];
+        PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].destDmaAddr = dmaPpStruct->operatePeriphAddr;
+    } else if (dmaPpStruct->DMA_LLI_Cfg->dir == DMA_TRNS_P2M) {
+        PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].srcDmaAddr = dmaPpStruct->operatePeriphAddr;
+        PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].destDmaAddr = dmaPpStruct->chache_buf_addr[0];
+
+        PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].srcDmaAddr = dmaPpStruct->operatePeriphAddr;
+        PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].destDmaAddr = dmaPpStruct->chache_buf_addr[1];
+    } else {
+        return ERROR;
+        /*V1.0 version DMA LLI Ping-Pong structure not support P2P & M2M MODE*/
+    }
+
+    PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].nextLLI = (uint32_t)&PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX];
+    PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl = dmaPpStruct->dmaCtrlRegVal;
+
+    PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].nextLLI = (uint32_t)&PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX];
+    PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl = dmaPpStruct->dmaCtrlRegVal;
+
+    DMA_LLI_Init(dmaPpStruct->dmaChan, dmaPpStruct->DMA_LLI_Cfg);
+
+    DMA_LLI_Update(dmaPpStruct->dmaChan, (uint32_t)&PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX]);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  DMA LLI PingPong Structure Start
+ *
+ * @param  dmaPpStruct: None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void DMA_LLI_PpStruct_Start(DMA_LLI_PP_Struct *dmaPpStruct)
+{
+    DMA_Channel_Enable(dmaPpStruct->dmaChan);
+}
+
+/****************************************************************************/ /**
+ * @brief  DMA LLI PingPong Structure Stop
+ *
+ * @param  dmaPpStruct: None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void DMA_LLI_PpStruct_Stop(DMA_LLI_PP_Struct *dmaPpStruct)
+{
+    DMA_Channel_Disable(dmaPpStruct->dmaChan);
+}
+
+/*@} end of group DMA_Public_Functions */
+
+/*@} end of group DMA */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_ef_ctrl.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_ef_ctrl.c
new file mode 100644
index 00000000..01d99173
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_ef_ctrl.c
@@ -0,0 +1,1638 @@
+/**
+ ******************************************************************************
+ * @file    bl702_sec_ef_ctrl.c
+ * @version V1.0
+ * @date
+ * @brief   This file is the standard driver c file
+ ******************************************************************************
+ * @attention
+ *
+ * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#include "bl702_ef_ctrl.h"
+#include "ef_data_0_reg.h"
+#include "string.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SEC_EF_CTRL
+ *  @{
+ */
+
+/** @defgroup  SEC_EF_CTRL_Private_Macros
+ *  @{
+ */
+#define EF_CTRL_EFUSE_CYCLE_PROTECT (0xbf << 24)
+#define EF_CTRL_EFUSE_CTRL_PROTECT  (0xbf << 8)
+#define EF_CTRL_DFT_TIMEOUT_VAL     (160 * 1000)
+#ifndef BOOTROM
+#define EF_CTRL_LOAD_BEFORE_READ_R0 EF_Ctrl_Load_Efuse_R0()
+#else
+#define EF_CTRL_LOAD_BEFORE_READ_R0
+#endif
+#define EF_CTRL_DATA0_CLEAR EF_Ctrl_Clear(0, EF_CTRL_EFUSE_R0_SIZE / 4)
+
+/*@} end of group SEC_EF_CTRL_Private_Macros */
+
+/** @defgroup  SEC_EF_CTRL_Private_Types
+ *  @{
+ */
+
+/*@} end of group SEC_EF_CTRL_Private_Types */
+
+/** @defgroup  SEC_EF_CTRL_Private_Variables
+ *  @{
+ */
+
+/*@} end of group SEC_EF_CTRL_Private_Variables */
+
+/** @defgroup  SEC_EF_CTRL_Global_Variables
+ *  @{
+ */
+
+/*@} end of group SEC_EF_CTRL_Global_Variables */
+
+/** @defgroup  SEC_EF_CTRL_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group SEC_EF_CTRL_Private_Fun_Declaration */
+
+/** @defgroup  SEC_EF_CTRL_Private_Functions
+ *  @{
+ */
+
+/****************************************************************************
+ * @brief  Switch efuse region 0 control to AHB clock
+ *
+ * @param  None
+ *
+ * @return None
+ *
+ *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+/* static */ void ATTR_TCM_SECTION EF_Ctrl_Sw_AHB_Clk_0(void) {
+  uint32_t tmpVal;
+  uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL;
+
+  while (EF_Ctrl_Busy() == SET) {
+    timeout--;
+
+    if (timeout == 0) {
+      break;
+    }
+  }
+
+  tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS)
+           | (EF_CTRL_SAHB_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | (0 << EF_CTRL_EF_IF_POR_DIG_POS) | (1 << EF_CTRL_EF_IF_0_INT_CLR_POS)
+           | (0 << EF_CTRL_EF_IF_0_RW_POS) | (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+  BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);
+}
+#endif
+
+/****************************************************************************
+ * @brief  Program efuse region 0
+ *
+ * @param  None
+ *
+ * @return None
+ *
+ *******************************************************************************/
+static void EF_Ctrl_Program_Efuse_0(void) {
+  uint32_t tmpVal;
+
+  /* Select auto mode and select ef clock */
+  tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS)
+           | (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | (0 << EF_CTRL_EF_IF_POR_DIG_POS) | (1 << EF_CTRL_EF_IF_0_INT_CLR_POS)
+           | (0 << EF_CTRL_EF_IF_0_RW_POS) | (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+  BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);
+
+  /* Program */
+  tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS)
+           | (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | (1 << EF_CTRL_EF_IF_POR_DIG_POS) | (1 << EF_CTRL_EF_IF_0_INT_CLR_POS)
+           | (1 << EF_CTRL_EF_IF_0_RW_POS) | (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+  BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);
+
+  /* Add delay for POR to be stable */
+  BL702_Delay_US(4);
+
+  /* Trigger */
+  tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS)
+           | (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | (1 << EF_CTRL_EF_IF_POR_DIG_POS) | (1 << EF_CTRL_EF_IF_0_INT_CLR_POS)
+           | (1 << EF_CTRL_EF_IF_0_RW_POS) | (1 << EF_CTRL_EF_IF_0_TRIG_POS);
+  BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);
+}
+
+/*@} end of group SEC_EF_CTRL_Private_Functions */
+
+/** @defgroup  SEC_EF_CTRL_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************
+ * @brief  Load efuse region 0
+ *
+ * @param  None
+ *
+ * @return None
+ *
+ *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION EF_Ctrl_Load_Efuse_R0(void) {
+  uint32_t tmpVal;
+  uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL;
+
+  EF_CTRL_DATA0_CLEAR;
+
+  /* Trigger read */
+  tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS)
+           | (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | (0 << EF_CTRL_EF_IF_POR_DIG_POS) | (1 << EF_CTRL_EF_IF_0_INT_CLR_POS)
+           | (0 << EF_CTRL_EF_IF_0_RW_POS) | (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+  BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);
+
+  tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS)
+           | (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | (0 << EF_CTRL_EF_IF_POR_DIG_POS) | (1 << EF_CTRL_EF_IF_0_INT_CLR_POS)
+           | (0 << EF_CTRL_EF_IF_0_RW_POS) | (1 << EF_CTRL_EF_IF_0_TRIG_POS);
+  BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);
+
+  BL702_Delay_US(10);
+
+  /* Wait for efuse control idle*/
+  do {
+    tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0);
+    timeout--;
+
+    if (timeout == 0) {
+      break;
+    }
+  } while (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_BUSY) ||
+
+           (!BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE)));
+
+  /* Switch to AHB clock */
+  tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS)
+           | (EF_CTRL_SAHB_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | (0 << EF_CTRL_EF_IF_POR_DIG_POS) | (1 << EF_CTRL_EF_IF_0_INT_CLR_POS)
+           | (0 << EF_CTRL_EF_IF_0_RW_POS) | (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+  BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);
+}
+#endif
+
+/****************************************************************************
+ * @brief  Check efuse busy status
+ *
+ * @param  None
+ *
+ * @return SET or RESET
+ *
+ *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_Busy(void) {
+  uint32_t tmpVal;
+
+  tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0);
+
+  if (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_BUSY)) {
+    return SET;
+  }
+
+  return RESET;
+}
+#endif
+
+/****************************************************************************
+ * @brief  Check efuse whether finish loading
+ *
+ * @param  None
+ *
+ * @return SET or RESET
+ *
+ *******************************************************************************/
+BL_Sts_Type EF_Ctrl_AutoLoad_Done(void) {
+  uint32_t tmpVal;
+
+  tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0);
+
+  if (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE)) {
+    return SET;
+  } else {
+    return RESET;
+  }
+}
+
+/****************************************************************************
+ * @brief  Efuse write debug password
+ *
+ * @param  passWdLow: password low 32 bits
+ * @param  passWdHigh: password high 32 bits
+ * @param  program: program to efuse entity or not
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void EF_Ctrl_Write_Dbg_Pwd(uint32_t passWdLow, uint32_t passWdHigh, uint8_t program) {
+  /* Switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+
+  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW, passWdLow);
+  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH, passWdHigh);
+
+  if (program) {
+    EF_Ctrl_Program_Efuse_0();
+  }
+}
+
+/****************************************************************************
+ * @brief  Efuse read debug password
+ *
+ * @param  passWdLow: password low 32 bits pointer to store value
+ * @param  passWdHigh: password high 32 bits pointer to store value
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void EF_Ctrl_Read_Dbg_Pwd(uint32_t *passWdLow, uint32_t *passWdHigh) {
+  /* Trigger read data from efuse */
+  EF_CTRL_LOAD_BEFORE_READ_R0;
+
+  *passWdLow  = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW);
+  *passWdHigh = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH);
+}
+
+/****************************************************************************
+ * @brief  Efuse lock reading for passwd
+ *
+ * @param  program: program to efuse entity or not
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program) {
+  uint32_t tmpVal;
+
+  /* Switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+
+  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK);
+  tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_RD_LOCK_DBG_PWD);
+  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal);
+
+  if (program) {
+    EF_Ctrl_Program_Efuse_0();
+  }
+}
+
+/****************************************************************************
+ * @brief  Efuse lock writing for passwd
+ *
+ * @param  program: program to efuse entity or not
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program) {
+  uint32_t tmpVal;
+
+  /* Switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+
+  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK);
+  tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_DBG_PWD);
+  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal);
+
+  if (program) {
+    EF_Ctrl_Program_Efuse_0();
+  }
+}
+
+/****************************************************************************
+ * @brief  Efuse read security configuration
+ *
+ * @param  cfg: security configuration pointer
+ * @param  program: program to efuse entity or not
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg, uint8_t program) {
+  uint32_t tmpVal;
+
+  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_MODE, cfg->ef_dbg_mode);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_0_DIS, cfg->ef_dbg_jtag_0_dis);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_EN, cfg->ef_sboot_en);
+  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0, tmpVal);
+
+  if (program) {
+    EF_Ctrl_Program_Efuse_0();
+  }
+}
+
+/****************************************************************************
+ * @brief  Efuse read security configuration
+ *
+ * @param  cfg: security configuration pointer
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg) {
+  uint32_t tmpVal;
+
+  /* Trigger read data from efuse */
+  EF_CTRL_LOAD_BEFORE_READ_R0;
+
+  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0);
+
+  cfg->ef_dbg_mode       = (EF_Ctrl_Dbg_Mode_Type)BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_MODE);
+  cfg->ef_dbg_jtag_0_dis = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_0_DIS);
+  cfg->ef_sboot_en       = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_EN);
+}
+
+/****************************************************************************
+ * @brief  Efuse write security boot configuration
+ *
+ * @param  sign[1]: Sign configuration pointer
+ * @param  aes[1]: AES configuration pointer
+ * @param  program: program to efuse entity or not
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void EF_Ctrl_Write_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1], uint8_t program) {
+  uint32_t tmpVal;
+
+  /* Switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+
+  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0);
+
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_SIGN_MODE, sign[0]);
+
+  if (aes[0] != EF_CTRL_SF_AES_NONE) {
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SF_AES_MODE, aes[0]);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_CPU0_ENC_EN, 1);
+  }
+
+  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0, tmpVal);
+
+  if (program) {
+    EF_Ctrl_Program_Efuse_0();
+  }
+}
+
+/****************************************************************************
+ * @brief  Efuse write security boot configuration
+ *
+ * @param  sign[1]: Sign configuration pointer
+ * @param  aes[1]: AES configuration pointer
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void EF_Ctrl_Read_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1]) {
+  uint32_t tmpVal;
+  uint32_t tmpVal2;
+
+  /* Trigger read data from efuse */
+  EF_CTRL_LOAD_BEFORE_READ_R0;
+
+  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0);
+
+  tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_SIGN_MODE);
+  sign[0] = (EF_Ctrl_Sign_Type)(tmpVal2 & 0x01);
+
+  tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_CPU0_ENC_EN);
+
+  if (tmpVal2) {
+    aes[0] = (EF_Ctrl_SF_AES_Type)BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SF_AES_MODE);
+  } else {
+    aes[0] = EF_CTRL_SF_AES_NONE;
+  }
+}
+
+/****************************************************************************
+ * @brief  Analog Trim parity calculate
+ *
+ * @param  val: Value of efuse trim data
+ * @param  len: Length of bit to calculate
+ *
+ * @return Parity bit value
+ *
+ *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+uint8_t ATTR_CLOCK_SECTION EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len) {
+  uint8_t cnt = 0;
+  uint8_t i   = 0;
+
+  for (i = 0; i < len; i++) {
+    if (val & (1 << i)) {
+      cnt++;
+    }
+  }
+
+  return cnt & 0x01;
+}
+#endif
+
+/****************************************************************************
+ * @brief  Efuse write analog trim
+ *
+ * @param  index: index of analog trim
+ * @param  trim: trim value
+ * @param  program: program to efuse entity or not
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void EF_Ctrl_Write_Ana_Trim(uint32_t index, uint32_t trim, uint8_t program) {
+  /* Switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+
+  if (index == 0) {
+    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0, trim);
+  }
+
+  if (program) {
+    EF_Ctrl_Program_Efuse_0();
+  }
+}
+
+/****************************************************************************
+ * @brief  Efuse read analog trim
+ *
+ * @param  index: index of analog trim
+ * @param  trim: trim value
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void EF_Ctrl_Read_Ana_Trim(uint32_t index, uint32_t *trim) {
+  /* Switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+
+  EF_CTRL_LOAD_BEFORE_READ_R0;
+
+  if (index == 0) {
+    *trim = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0);
+  }
+}
+
+/****************************************************************************
+ * @brief  Efuse read RC32M trim
+ *
+ * @param  trim: Trim data pointer
+ *
+ * @return None
+ *
+ *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim) {
+  uint32_t tmpVal = 0;
+  /* Switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+
+  EF_CTRL_LOAD_BEFORE_READ_R0;
+
+  tmpVal                         = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0);
+  trim->trimRc32mCodeFrExt       = (tmpVal >> 10) & 0xff;
+  trim->trimRc32mCodeFrExtParity = (tmpVal >> 18) & 0x01;
+  trim->trimRc32mExtCodeEn       = (tmpVal >> 19) & 0x01;
+}
+#endif
+
+/****************************************************************************
+ * @brief  Efuse read RC32K trim
+ *
+ * @param  trim: Trim data pointer
+ *
+ * @return None
+ *
+ *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim) {
+  uint32_t tmpVal = 0;
+  /* Switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+
+  EF_CTRL_LOAD_BEFORE_READ_R0;
+
+  tmpVal                         = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0);
+  trim->trimRc32kCodeFrExt       = (tmpVal >> 20) & 0x3ff;
+  trim->trimRc32kCodeFrExtParity = (tmpVal >> 30) & 0x01;
+  trim->trimRc32kExtCodeEn       = (tmpVal >> 31) & 0x01;
+}
+#endif
+
+/****************************************************************************
+ * @brief  Efuse read TSEN trim
+ *
+ * @param  trim: Trim data pointer
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ATTR_CLOCK_SECTION EF_Ctrl_Read_TSEN_Trim(Efuse_TSEN_Refcode_Corner_Type *trim) {
+  uint32_t tmpVal = 0;
+  /* Switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+
+  EF_CTRL_LOAD_BEFORE_READ_R0;
+
+  tmpVal                    = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3);
+  trim->tsenRefcodeCornerEn = tmpVal & 0x01;
+
+  tmpVal                        = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK);
+  trim->tsenRefcodeCorner       = tmpVal & 0xfff;
+  trim->tsenRefcodeCornerParity = (tmpVal >> 12) & 0x01;
+
+  trim->tsenRefcodeCornerVersion = 0;
+}
+
+/****************************************************************************
+ * @brief  Efuse read ADC Gain trim
+ *
+ * @param  trim: Trim data pointer
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void ATTR_CLOCK_SECTION EF_Ctrl_Read_ADC_Gain_Trim(Efuse_ADC_Gain_Coeff_Type *trim) {
+  uint32_t tmpVal = 0;
+  /* Switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+
+  EF_CTRL_LOAD_BEFORE_READ_R0;
+
+  tmpVal                   = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3);
+  trim->adcGainCoeff       = (tmpVal >> 1) & 0xfff;
+  trim->adcGainCoeffParity = (tmpVal >> 13) & 0x01;
+  trim->adcGainCoeffEn     = (tmpVal >> 14) & 0x01;
+}
+
+/****************************************************************************
+ * @brief  Efuse write software usage
+ *
+ * @param  index: index of software usage
+ * @param  usage: usage value
+ * @param  program: program to efuse entity or not
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage, uint8_t program) {
+  /* switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+
+  if (index == 0) {
+    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0, usage);
+  }
+
+  if (program) {
+    EF_Ctrl_Program_Efuse_0();
+  }
+}
+
+/****************************************************************************
+ * @brief  Efuse read software usage
+ *
+ * @param  index: index of software usage
+ * @param  usage: usage value
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void EF_Ctrl_Read_Sw_Usage(uint32_t index, uint32_t *usage) {
+  /* Switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+
+  EF_CTRL_LOAD_BEFORE_READ_R0;
+
+  if (index == 0) {
+    *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0);
+  }
+}
+
+/****************************************************************************
+ * @brief  Efuse read software usage
+ *
+ * @param  index: index of software usage
+ * @param  program: usage value
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program) {
+  uint32_t tmpVal;
+
+  /* Switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+
+  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK);
+
+  if (index == 0) {
+    tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_SW_USAGE_0);
+  }
+
+  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal);
+
+  if (program) {
+    EF_Ctrl_Program_Efuse_0();
+  }
+}
+
+/****************************************************************************
+ * @brief  Efuse write MAC address
+ *
+ * @param  mac[6]: MAC address buffer
+ * @param  program: program to efuse entity or not
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void EF_Ctrl_Write_MAC_Address(uint8_t mac[6], uint8_t program) {
+  uint8_t *maclow  = (uint8_t *)mac;
+  uint8_t *machigh = (uint8_t *)(mac + 4);
+  uint32_t tmpVal;
+
+  /* Switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+
+  /* The low 32 bits */
+  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW, BL_RDWD_FRM_BYTEP(maclow));
+  /* The high 16 bits */
+  tmpVal = machigh[0] + (machigh[1] << 8);
+  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH, tmpVal);
+
+  if (program) {
+    EF_Ctrl_Program_Efuse_0();
+  }
+}
+
+/****************************************************************************
+ * @brief  Efuse Ctrl get zero bit count
+ *
+ * @param  val: Value to count
+ *
+ * @return Zero bit count
+ *
+ *******************************************************************************/
+static uint32_t EF_Ctrl_Get_Byte_Zero_Cnt(uint8_t val) {
+  uint32_t cnt = 0;
+  uint32_t i   = 0;
+
+  for (i = 0; i < 8; i++) {
+    if ((val & (1 << i)) == 0) {
+      cnt += 1;
+    }
+  }
+
+  return cnt;
+}
+
+/****************************************************************************
+ * @brief  Efuse read MAC address
+ *
+ * @param  mac[8]: MAC address buffer
+ *
+ * @return SUCCESS or ERROR
+ *
+ *******************************************************************************/
+BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[8]) {
+  uint8_t *maclow  = (uint8_t *)mac;
+  uint8_t *machigh = (uint8_t *)(mac + 4);
+  uint32_t tmpVal;
+  uint32_t i   = 0;
+  uint32_t cnt = 0;
+
+  /* Trigger read data from efuse */
+  EF_CTRL_LOAD_BEFORE_READ_R0;
+
+  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW);
+  BL_WRWD_TO_BYTEP(maclow, tmpVal);
+
+  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH);
+  BL_WRWD_TO_BYTEP(machigh, tmpVal);
+
+  /* Get original parity */
+  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2);
+
+  /* Check parity */
+  for (i = 0; i < 8; i++) {
+    cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]);
+  }
+
+  if ((cnt & 0x3f) == (tmpVal & 0x3f)) {
+    return SUCCESS;
+  } else {
+    return ERROR;
+  }
+}
+
+/****************************************************************************
+ * @brief  Efuse read MAC address
+ *
+ * @param  mac[7]: MAC address buffer
+ *
+ * @return SUCCESS or ERROR
+ *
+ *******************************************************************************/
+BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7]) {
+  uint8_t *maclow  = (uint8_t *)mac;
+  uint8_t *machigh = (uint8_t *)(mac + 4);
+  uint32_t tmpVal;
+
+  /* Trigger read data from efuse */
+  EF_CTRL_LOAD_BEFORE_READ_R0;
+
+  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW);
+  BL_WRWD_TO_BYTEP(maclow, tmpVal);
+
+  tmpVal     = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH);
+  machigh[0] = tmpVal & 0xff;
+  machigh[1] = (tmpVal >> 8) & 0xff;
+  machigh[2] = (tmpVal >> 16) & 0xff;
+
+  return SUCCESS;
+}
+
+/****************************************************************************
+ * @brief  Efuse lock writing for MAC address
+ *
+ * @param  program: program to efuse entity or not
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void EF_Ctrl_Writelock_MAC_Address(uint8_t program) {
+  uint32_t tmpVal;
+
+  /* Switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+
+  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK);
+  tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_WIFI_MAC);
+  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal);
+
+  if (program) {
+    EF_Ctrl_Program_Efuse_0();
+  }
+}
+
+/****************************************************************************
+ * @brief  Whether a value bits is all zero
+ *
+ * @param  val: value to check
+ * @param  start: start bit
+ * @param  len: total length of bits to check
+ *
+ * @return 1 for all bits zero 0 for others
+ *
+ *******************************************************************************/
+uint8_t EF_Ctrl_Is_All_Bits_Zero(uint32_t val, uint8_t start, uint8_t len) {
+  uint32_t mask = 0;
+
+  val = (val >> start);
+
+  if (len >= 32) {
+    mask = 0xffffffff;
+  } else {
+    mask = (1 << len) - 1;
+  }
+
+  if ((val & mask) == 0) {
+    return 1;
+  } else {
+    return 0;
+  }
+}
+
+/****************************************************************************
+ * @brief  Whether MAC address slot is empty
+ *
+ * @param  slot: MAC address slot
+ * @param  reload: whether  reload to check
+ *
+ * @return 0 for all slots full,1 for others
+ *
+ *******************************************************************************/
+uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload) {
+  uint32_t tmp1 = 0xffffffff, tmp2 = 0xffffffff;
+  uint32_t part1Empty = 0, part2Empty = 0;
+
+  if (slot == 0) {
+    /* Switch to AHB clock */
+    EF_Ctrl_Sw_AHB_Clk_0();
+
+    if (reload) {
+      EF_CTRL_LOAD_BEFORE_READ_R0;
+    }
+
+    tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW);
+    tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH);
+  } else if (slot == 1) {
+    /* Switch to AHB clock */
+    EF_Ctrl_Sw_AHB_Clk_0();
+
+    if (reload) {
+      EF_CTRL_LOAD_BEFORE_READ_R0;
+    }
+
+    tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W0);
+    tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1);
+  } else if (slot == 2) {
+    /* Switch to AHB clock */
+    EF_Ctrl_Sw_AHB_Clk_0();
+
+    if (reload) {
+      EF_CTRL_LOAD_BEFORE_READ_R0;
+    }
+
+    tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW);
+    tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH);
+  }
+
+  part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 0, 32));
+  part2Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp2, 0, 22));
+
+  return (part1Empty && part2Empty);
+}
+
+/****************************************************************************
+ * @brief  Efuse write optional MAC address
+ *
+ * @param  slot: MAC address slot
+ * @param  mac[8]: MAC address buffer
+ * @param  program: Whether program
+ *
+ * @return SUCCESS or ERROR
+ *
+ *******************************************************************************/
+BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[8], uint8_t program) {
+  uint8_t *maclow  = (uint8_t *)mac;
+  uint8_t *machigh = (uint8_t *)(mac + 4);
+  uint32_t tmpVal  = 0;
+  uint32_t i       = 0;
+  uint32_t cnt     = 0;
+
+  if (slot >= 3) {
+    return ERROR;
+  }
+
+  if (slot == 2) {
+    /* Switch to AHB clock */
+    EF_Ctrl_Sw_AHB_Clk_0();
+  } else {
+    /* Switch to AHB clock */
+    EF_Ctrl_Sw_AHB_Clk_0();
+  }
+
+  /* The low 32 bits */
+  if (slot == 0) {
+    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW, BL_RDWD_FRM_BYTEP(maclow));
+  } else if (slot == 1) {
+    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W0, BL_RDWD_FRM_BYTEP(maclow));
+  } else if (slot == 2) {
+    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW, BL_RDWD_FRM_BYTEP(maclow));
+  }
+
+  /* The high 32 bits */
+  if (slot == 0) {
+    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH, BL_RDWD_FRM_BYTEP(machigh));
+  } else if (slot == 1) {
+    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1, BL_RDWD_FRM_BYTEP(machigh));
+  } else if (slot == 2) {
+    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH, BL_RDWD_FRM_BYTEP(machigh));
+  }
+
+  cnt = 0;
+  for (i = 0; i < 8; i++) {
+    cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]);
+  }
+  cnt &= 0x3f;
+  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2);
+  if (slot == 0) {
+    tmpVal |= (cnt << 0);
+  } else if (slot == 1) {
+    tmpVal |= (cnt << 6);
+  } else if (slot == 2) {
+    tmpVal |= (cnt << 12);
+  }
+  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2, tmpVal);
+
+  if (program) {
+    if (slot == 2) {
+      EF_Ctrl_Program_Efuse_0();
+    } else {
+      EF_Ctrl_Program_Efuse_0();
+    }
+  }
+  return SUCCESS;
+}
+
+/****************************************************************************
+ * @brief  Efuse read optional MAC address
+ *
+ * @param  slot: MAC address slot
+ * @param  mac[8]: MAC address buffer
+ * @param  reload: Whether reload
+ *
+ * @return SUCCESS or ERROR
+ *
+ *******************************************************************************/
+BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[8], uint8_t reload) {
+  uint8_t *maclow  = (uint8_t *)mac;
+  uint8_t *machigh = (uint8_t *)(mac + 4);
+  uint32_t tmpVal  = 0;
+  uint32_t i       = 0;
+  uint32_t cnt     = 0;
+  uint32_t crc     = 0;
+
+  if (slot >= 3) {
+    return ERROR;
+  }
+
+  /* Trigger read data from efuse */
+  if (reload) {
+    if (slot == 2) {
+      EF_CTRL_LOAD_BEFORE_READ_R0;
+    } else {
+      EF_CTRL_LOAD_BEFORE_READ_R0;
+    }
+  }
+
+  if (slot == 0) {
+    tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW);
+  } else if (slot == 1) {
+    tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W0);
+  } else if (slot == 2) {
+    tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW);
+  }
+  BL_WRWD_TO_BYTEP(maclow, tmpVal);
+
+  if (slot == 0) {
+    tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH);
+  } else if (slot == 1) {
+    tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1);
+  } else if (slot == 2) {
+    tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH);
+  }
+  BL_WRWD_TO_BYTEP(machigh, tmpVal);
+
+  /* Get original parity */
+  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2);
+  if (slot == 0) {
+    crc = ((tmpVal >> 0) & 0x3f);
+  } else if (slot == 1) {
+    crc = ((tmpVal >> 6) & 0x3f);
+  } else if (slot == 2) {
+    crc = ((tmpVal >> 12) & 0x3f);
+  }
+
+  /* Check parity */
+  for (i = 0; i < 8; i++) {
+    cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]);
+  }
+  if ((cnt & 0x3f) == crc) {
+    return SUCCESS;
+  } else {
+    return ERROR;
+  }
+}
+
+/****************************************************************************
+ * @brief  Efuse read chip ID
+ *
+ * @param  chipID[8]: Chip ID buffer
+ *
+ * @return SUCCESS or ERROR
+ *
+ *******************************************************************************/
+BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t chipID[8]) { return EF_Ctrl_Read_MAC_Address(chipID); }
+
+/****************************************************************************
+ * @brief  Efuse get chip PID&&VID
+ *
+ * @param  pid[1]: Chip PID
+ * @param  vid[1]: Chip VID
+ *
+ * @return SUCCESS or ERROR
+ *
+ *******************************************************************************/
+BL_Err_Type EF_Ctrl_Get_Chip_PIDVID(uint16_t pid[1], uint16_t vid[1]) {
+  uint32_t tmpVal;
+
+  /* Trigger read data from efuse */
+  EF_CTRL_LOAD_BEFORE_READ_R0;
+
+  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W3);
+  pid[0] = (uint16_t)(tmpVal & 0xFFFF);
+  vid[0] = (uint16_t)(tmpVal >> 16);
+
+  return SUCCESS;
+}
+
+uint32_t EF_Ctrl_Get_Key_Slot_w0() {
+
+  /* Trigger read data from efuse */
+  EF_CTRL_LOAD_BEFORE_READ_R0;
+
+  return BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W0);
+}
+uint32_t EF_Ctrl_Get_Key_Slot_w1() {
+
+  /* Trigger read data from efuse */
+  EF_CTRL_LOAD_BEFORE_READ_R0;
+
+  return BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W1);
+}
+
+/****************************************************************************
+ * @brief  Efuse get customer PID&&VID
+ *
+ * @param  pid[1]: Customer PID
+ * @param  vid[1]: Customer VID
+ *
+ * @return SUCCESS or ERROR
+ *
+ *******************************************************************************/
+BL_Err_Type EF_Ctrl_Get_Customer_PIDVID(uint16_t pid[1], uint16_t vid[1]) {
+  uint32_t tmpVal;
+
+  /* Trigger read data from efuse */
+  EF_CTRL_LOAD_BEFORE_READ_R0;
+
+  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W2);
+  pid[0] = (uint16_t)(tmpVal & 0xFFFF);
+  vid[0] = (uint16_t)(tmpVal >> 16);
+
+  return SUCCESS;
+}
+
+/****************************************************************************
+ * @brief  Efuse read device info
+ *
+ * @param  deviceInfo: Device info pointer
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void EF_Ctrl_Read_Device_Info(Efuse_Device_Info_Type *deviceInfo) {
+  uint32_t  tmpVal;
+  uint32_t *p = (uint32_t *)deviceInfo;
+
+  /* Trigger read data from efuse */
+  EF_CTRL_LOAD_BEFORE_READ_R0;
+
+  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2);
+  *p     = tmpVal;
+}
+
+/****************************************************************************
+ * @brief  Whether Capcode is empty
+ *
+ * @param  slot: Cap code slot
+ * @param  reload: Whether reload
+ *
+ * @return 0 for all slots full,1 for others
+ *
+ *******************************************************************************/
+uint8_t EF_Ctrl_Is_CapCode_Empty(uint8_t slot, uint8_t reload) {
+  uint32_t tmp = 0xffffffff;
+
+  /* Switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+
+  if (reload) {
+    EF_CTRL_LOAD_BEFORE_READ_R0;
+  }
+
+  if (slot == 0) {
+    tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3);
+    return (EF_Ctrl_Is_All_Bits_Zero(tmp, 25, 7));
+  } else if (slot == 1) {
+    tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
+    return (EF_Ctrl_Is_All_Bits_Zero(tmp, 9, 7));
+  } else if (slot == 2) {
+    tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
+    return (EF_Ctrl_Is_All_Bits_Zero(tmp, 25, 7));
+  } else {
+    return 0;
+  }
+}
+
+/****************************************************************************
+ * @brief  Efuse write Cap code
+ *
+ * @param  slot: Cap code slot
+ * @param  code: Cap code value
+ * @param  program: Whether program
+ *
+ * @return SUCCESS or ERROR
+ *
+ *******************************************************************************/
+BL_Err_Type EF_Ctrl_Write_CapCode_Opt(uint8_t slot, uint8_t code, uint8_t program) {
+  uint32_t tmp;
+  uint8_t  trim;
+
+  if (slot >= 3) {
+    return ERROR;
+  }
+
+  /* Switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+  EF_CTRL_LOAD_BEFORE_READ_R0;
+
+  trim = (code << 1);
+  trim |= (1 << 0);
+
+  if (slot == 0) {
+    tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3);
+    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3, tmp | (trim << 25));
+  } else if (slot == 1) {
+    tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
+    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3, tmp | (trim << 9));
+  } else if (slot == 2) {
+    tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
+    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3, tmp | (trim << 25));
+  }
+
+  if (program) {
+    EF_Ctrl_Program_Efuse_0();
+  }
+  while (SET == EF_Ctrl_Busy())
+    ;
+
+  return SUCCESS;
+}
+
+/****************************************************************************
+ * @brief  Efuse read Cap code
+ *
+ * @param  slot: Cap code slot
+ * @param  code: Cap code pointer
+ * @param  reload: Whether reload
+ *
+ * @return SUCCESS or ERROR
+ *
+ *******************************************************************************/
+BL_Err_Type EF_Ctrl_Read_CapCode_Opt(uint8_t slot, uint8_t *code, uint8_t reload) {
+  uint32_t tmp;
+  uint8_t  trim = 0;
+
+  /* Switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+
+  if (reload) {
+    EF_CTRL_LOAD_BEFORE_READ_R0;
+  }
+
+  if (slot == 0) {
+    tmp  = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3);
+    trim = (tmp >> 25) & 0x7f;
+  } else if (slot == 1) {
+    tmp  = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
+    trim = (tmp >> 9) & 0x7f;
+  } else if (slot == 2) {
+    tmp  = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
+    trim = (tmp >> 25) & 0x7f;
+  }
+
+  if (trim & 0x01) {
+    *code = trim >> 1;
+    return SUCCESS;
+  }
+  return ERROR;
+}
+
+/****************************************************************************
+ * @brief  Whether power offset slot is empty
+ *
+ * @param  slot: Power offset code slot
+ * @param  reload: Whether reload
+ *
+ * @return 0 for all slots full,1 for others
+ *
+ *******************************************************************************/
+uint8_t EF_Ctrl_Is_PowerOffset_Slot_Empty(uint8_t slot, uint8_t reload) {
+  uint32_t tmp1       = 0xffffffff;
+  uint32_t part1Empty = 0, part2Empty = 0;
+
+  /* Switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+
+  if (reload) {
+    EF_CTRL_LOAD_BEFORE_READ_R0;
+  }
+
+  if (slot == 0) {
+    tmp1       = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3);
+    part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 16, 9));
+    part2Empty = 1;
+  } else if (slot == 1) {
+    tmp1       = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
+    part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 0, 9));
+    part2Empty = 1;
+  } else if (slot == 2) {
+    tmp1       = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
+    part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 16, 9));
+    part2Empty = 1;
+  }
+
+  return (part1Empty && part2Empty);
+}
+
+/****************************************************************************
+ * @brief  Efuse write power offset
+ *
+ * @param  slot: Power offset slot
+ * @param  pwrOffset[2]: Power offset value array
+ * @param  program: Whether program
+ *
+ * @return SUCCESS or ERROR
+ *
+ *******************************************************************************/
+BL_Err_Type EF_Ctrl_Write_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[2], uint8_t program) {
+  uint32_t tmp   = 0;
+  uint32_t k     = 0;
+  uint32_t Value = 0;
+
+  if (slot >= 3) {
+    return ERROR;
+  }
+
+  for (k = 0; k < 2; k++) {
+    /* Use 4 bits as signed value */
+    if (pwrOffset[k] > 7) {
+      pwrOffset[k] = 7;
+    }
+    if (pwrOffset[k] < -8) {
+      pwrOffset[k] = -8;
+    }
+    Value += (uint32_t)(pwrOffset[k] & 0x0f) << (k * 4);
+  }
+
+  if (slot == 0) {
+    tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3);
+    tmp |= (Value << 17);
+    tmp |= (1 << 16);
+    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3, tmp);
+  } else if (slot == 1) {
+    tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
+    tmp |= (Value << 1);
+    tmp |= (1 << 0);
+    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3, tmp);
+  } else if (slot == 2) {
+    tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
+    tmp |= (Value << 17);
+    tmp |= (1 << 16);
+    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3, tmp);
+  }
+
+  if (program) {
+    EF_Ctrl_Program_Efuse_0();
+  }
+
+  while (SET == EF_Ctrl_Busy())
+    ;
+
+  return SUCCESS;
+}
+
+/****************************************************************************
+ * @brief  Efuse read poweroffset value
+ *
+ * @param  slot: Power offset slot
+ * @param  pwrOffset[2]: Power offset array
+ * @param  reload: Whether reload
+ *
+ * @return SUCCESS or ERROR
+ *
+ *******************************************************************************/
+BL_Err_Type EF_Ctrl_Read_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[2], uint8_t reload) {
+  uint32_t pwrOffsetValue = 0;
+  uint32_t tmp            = 0, k;
+  uint8_t  en             = 0;
+
+  /* Switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+
+  if (reload) {
+    EF_CTRL_LOAD_BEFORE_READ_R0;
+  }
+
+  if (slot == 0) {
+    tmp            = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3);
+    en             = (tmp >> 16) & 0x01;
+    pwrOffsetValue = (tmp >> 17) & 0xff;
+  } else if (slot == 1) {
+    tmp            = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
+    en             = (tmp >> 0) & 0x01;
+    pwrOffsetValue = (tmp >> 1) & 0xff;
+  } else if (slot == 2) {
+    tmp            = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
+    en             = (tmp >> 16) & 0x01;
+    pwrOffsetValue = (tmp >> 17) & 0xff;
+  }
+
+  if (en) {
+    for (k = 0; k < 2; k++) {
+      tmp = (pwrOffsetValue >> (k * 4)) & 0x0f;
+      if (tmp >= 8) {
+        pwrOffset[k] = tmp - 16;
+      } else {
+        pwrOffset[k] = tmp;
+      }
+    }
+    return SUCCESS;
+  }
+  return ERROR;
+}
+
+/****************************************************************************
+ * @brief  Efuse write AES key
+ *
+ * @param  index: index of key slot
+ * @param  keyData: key data buffer
+ * @param  len: key data length in words
+ * @param  program: program to efuse entity or not
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program) {
+  uint32_t *pAESKeyStart0 = (uint32_t *)(EF_DATA_BASE + 0x1C);
+
+  if (index > 5) {
+    return;
+  }
+
+  /* Switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+
+  /* Every key is 4 words len*/
+  BL702_MemCpy4(pAESKeyStart0 + index * 4, keyData, len);
+
+  if (program) {
+    EF_Ctrl_Program_Efuse_0();
+  }
+}
+
+/****************************************************************************
+ * @brief  Efuse read AES key from specified region and index
+ *
+ * @param  index: index of key slot
+ * @param  keyData: key data buffer
+ * @param  len: key data length in words
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len) {
+  uint32_t *pAESKeyStart0 = (uint32_t *)(EF_DATA_BASE + 0x1C);
+
+  if (index > 5) {
+    return;
+  }
+
+  /* Trigger read data from efuse*/
+  EF_CTRL_LOAD_BEFORE_READ_R0;
+
+  /* Every key is 4 words len*/
+  BL702_MemCpy4(keyData, pAESKeyStart0 + index * 4, len);
+}
+
+/****************************************************************************
+ * @brief  Efuse lock writing for aes key
+ *
+ * @param  index: index of key slot
+ * @param  program: program to efuse entity or not
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program) {
+  uint32_t tmpVal;
+
+  if (index > 5) {
+    return;
+  }
+
+  /* Switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+
+  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK);
+
+  if (index <= 3) {
+    tmpVal |= (1 << (index + 19));
+  } else {
+    tmpVal |= (1 << (index + 19));
+    tmpVal |= (1 << (index - 4 + 13));
+  }
+
+  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal);
+
+  if (program) {
+    EF_Ctrl_Program_Efuse_0();
+  }
+}
+
+/****************************************************************************
+ * @brief  Efuse lock reading for aes key
+ *
+ * @param  index: index of key slot
+ * @param  program: program to efuse entity or not
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void EF_Ctrl_Readlock_AES_Key(uint8_t index, uint8_t program) {
+  uint32_t tmpVal;
+
+  if (index > 5) {
+    return;
+  }
+
+  /* Switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+
+  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK);
+  tmpVal |= (1 << (index + 26));
+  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal);
+
+  if (program) {
+    EF_Ctrl_Program_Efuse_0();
+  }
+}
+
+/****************************************************************************
+ * @brief  Program data to efuse region 0
+ *
+ * @param  index: index of efuse in word
+ * @param  data: data buffer
+ * @param  len: data length
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len) {
+  uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00);
+
+  /* Switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+
+  /* Add delay for CLK to be stable */
+  BL702_Delay_US(4);
+
+  BL702_MemCpy4(pEfuseStart0 + index, data, len);
+
+  EF_Ctrl_Program_Efuse_0();
+}
+
+/****************************************************************************
+ * @brief  Read data from efuse region 0
+ *
+ * @param  index: index of efuse in word
+ * @param  data: data buffer
+ * @param  len: data length
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len) {
+  uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00);
+
+  EF_CTRL_LOAD_BEFORE_READ_R0;
+
+  BL702_MemCpy4(data, pEfuseStart0 + index, len);
+}
+
+/****************************************************************************
+ * @brief  Clear efuse data register
+ *
+ * @param  index: index of efuse in word
+ * @param  len: data length
+ *
+ * @return None
+ *
+ *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION EF_Ctrl_Clear(uint32_t index, uint32_t len) {
+  uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00);
+  uint32_t  i            = 0;
+
+  /* Switch to AHB clock */
+  EF_Ctrl_Sw_AHB_Clk_0();
+
+  /* Clear data */
+  for (i = 0; i < len; i++) {
+    pEfuseStart0[index + i] = 0;
+  }
+}
+#endif
+
+/****************************************************************************
+ * @brief  efuse ctrl crc enable
+ *
+ * @param  None
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void EF_Ctrl_Crc_Enable(void) {
+  uint32_t tmpVal;
+
+  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0);
+  tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_TRIG);
+  tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_MODE);
+  tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DOUT_INV_EN);
+  tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DOUT_ENDIAN);
+  tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DIN_ENDIAN);
+  tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_INT_CLR);
+  tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_INT_SET);
+  BL_WR_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0, tmpVal);
+
+  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0);
+  tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_EN);
+  BL_WR_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0, tmpVal);
+}
+
+/****************************************************************************
+ * @brief  efuse ctrl get crc busy status
+ *
+ * @param  None
+ *
+ * @return DISABLE or ENABLE
+ *
+ *******************************************************************************/
+BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void) {
+  uint32_t tmpVal;
+
+  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0);
+  return (BL_Sts_Type)BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_CRC_BUSY);
+}
+
+/****************************************************************************
+ * @brief  efuse ctrl set golden value
+ *
+ * @param  goldenValue: Crc golden value
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue) { BL_WR_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_4, goldenValue); }
+
+/****************************************************************************
+ * @brief  efuse ctrl get crc result
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+ *******************************************************************************/
+BL_Err_Type EF_Ctrl_Crc_Result(void) {
+  uint32_t tmpVal;
+
+  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0);
+  return (BL_Err_Type)BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_CRC_ERROR);
+}
+
+/*@} end of group SEC_EF_CTRL_Public_Functions */
+
+/*@} end of group SEC_EF_CTRL */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_emac.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_emac.c
new file mode 100644
index 00000000..662ac309
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_emac.c
@@ -0,0 +1,687 @@
+/**
+  ******************************************************************************
+  * @file    bl702_emac.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702.h"
+#include "bl702_emac.h"
+#include "bl702_glb.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  EMAC
+ *  @{
+ */
+
+/** @defgroup  EMAC_Private_Macros
+ *  @{
+ */
+#define PHY_MAX_RETRY (0x3F0)
+
+/*@} end of group EMAC_Private_Macros */
+
+/** @defgroup  EMAC_Private_Types
+ *  @{
+ */
+
+/*@} end of group EMAC_Private_Types */
+
+/** @defgroup  EMAC_Private_Variables
+ *  @{
+ */
+static intCallback_Type *emacIntCbfArra[EMAC_INT_CNT] = { NULL };
+
+/*@} end of group EMAC_Private_Variables */
+
+/** @defgroup  EMAC_Global_Variables
+ *  @{
+ */
+
+/*@} end of group EMAC_Global_Variables */
+
+/** @defgroup  EMAC_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group EMAC_Private_Fun_Declaration */
+
+/** @defgroup  EMAC_Private_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Set MAC Address
+ *
+ * @param  macAddr[6]: MAC address buffer array
+ *
+ * @return None
+ *
+*******************************************************************************/
+static void EMAC_SetMACAddress(uint8_t macAddr[6])
+{
+    BL_WR_REG(EMAC_BASE, EMAC_MAC_ADDR1, (macAddr[0] << 8) | macAddr[1]);
+    BL_WR_REG(EMAC_BASE, EMAC_MAC_ADDR0, (macAddr[2] << 24) | (macAddr[3] << 16) | (macAddr[4] << 8) | (macAddr[5] << 0));
+}
+
+/****************************************************************************/ /**
+ * @brief  Set PHY Address
+ *
+ * @param  phyAddress: Phy address
+ *
+ * @return None
+ *
+*******************************************************************************/
+void EMAC_Phy_SetAddress(uint16_t phyAddress)
+{
+    uint32_t tmpVal;
+
+    /* Set Phy Address */
+    tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MIIADDRESS);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_FIAD, phyAddress);
+    BL_WR_REG(EMAC_BASE, EMAC_MIIADDRESS, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Set PHY Address
+ *
+ * @param  phyAddress: Phy address
+ *
+ * @return None
+ *
+*******************************************************************************/
+void EMAC_Phy_Set_Full_Duplex(uint8_t fullDuplex)
+{
+    uint32_t tmpVal;
+
+    /* Set MAC duplex config */
+    tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_FULLD, fullDuplex);
+    BL_WR_REG(EMAC_BASE, EMAC_MODE, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Read PHY register
+ *
+ * @param  phyReg: PHY register
+ * @param  regValue: PHY register value pointer
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type EMAC_Phy_Read(uint16_t phyReg, uint16_t *regValue)
+{
+    uint32_t tmpVal;
+
+    /* Set Register Address */
+    tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MIIADDRESS);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_RGAD, phyReg);
+    BL_WR_REG(EMAC_BASE, EMAC_MIIADDRESS, tmpVal);
+
+    /* Trigger read */
+    tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MIICOMMAND);
+    tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_RSTAT);
+    BL_WR_REG(EMAC_BASE, EMAC_MIICOMMAND, tmpVal);
+
+    BL_DRV_DUMMY;
+
+    do {
+        tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MIISTATUS);
+        BL702_Delay_US(16);
+    } while (BL_IS_REG_BIT_SET(tmpVal, EMAC_MIIM_BUSY));
+
+    *regValue = BL_RD_REG(EMAC_BASE, EMAC_MIIRX_DATA);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Write PHY register
+ *
+ * @param  phyReg: PHY register
+ * @param  regValue: PHY register value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type EMAC_Phy_Write(uint16_t phyReg, uint16_t regValue)
+{
+    uint32_t tmpVal;
+
+    /* Set Register Address */
+    tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MIIADDRESS);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_RGAD, phyReg);
+    BL_WR_REG(EMAC_BASE, EMAC_MIIADDRESS, tmpVal);
+
+    /* Set Write data */
+    BL_WR_REG(EMAC_BASE, EMAC_MIITX_DATA, regValue);
+
+    /* Trigger write */
+    tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MIICOMMAND);
+    tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_WCTRLDATA);
+    BL_WR_REG(EMAC_BASE, EMAC_MIICOMMAND, tmpVal);
+
+    BL_DRV_DUMMY;
+
+    do {
+        tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MIISTATUS);
+    } while (BL_IS_REG_BIT_SET(tmpVal, EMAC_MIIM_BUSY));
+
+    return SUCCESS;
+}
+
+/*@} end of group EMAC_Private_Functions */
+
+/** @defgroup  EMAC_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Initialize EMAC module
+ *
+ * @param  cfg: EMAC configuration pointer
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type EMAC_Init(EMAC_CFG_Type *cfg)
+{
+    uint32_t tmpVal;
+
+    /* Disable clock gate */
+    GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_EMAC);
+
+    /* Set MAC config */
+    tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_RMII_EN, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_RECSMALL, cfg->recvSmallFrame);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_PAD, cfg->padEnable);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_HUGEN, cfg->recvHugeFrame);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_CRCEN, cfg->crcEnable);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_NOPRE, cfg->noPreamble);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_BRO, cfg->recvBroadCast);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_PRO, ENABLE);
+    //tmpVal |= (1 << 7); /* local loopback in emac */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_IFG, cfg->interFrameGapCheck);
+    BL_WR_REG(EMAC_BASE, EMAC_MODE, tmpVal);
+
+    /* Set inter frame gap value */
+    BL_WR_REG(EMAC_BASE, EMAC_IPGT, cfg->interFrameGapValue);
+
+    /* Set MII interface */
+    tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MIIMODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_MIINOPRE, cfg->miiNoPreamble);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_CLKDIV, cfg->miiClkDiv);
+    BL_WR_REG(EMAC_BASE, EMAC_MIIMODE, tmpVal);
+
+    /* Set collision */
+    tmpVal = BL_RD_REG(EMAC_BASE, EMAC_COLLCONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_MAXRET, cfg->maxTxRetry);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_COLLVALID, cfg->collisionValid);
+    BL_WR_REG(EMAC_BASE, EMAC_COLLCONFIG, tmpVal);
+
+    /* Set frame length */
+    tmpVal = BL_RD_REG(EMAC_BASE, EMAC_PACKETLEN);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_MINFL, cfg->minFrameLen);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_MAXFL, cfg->maxFrameLen);
+    BL_WR_REG(EMAC_BASE, EMAC_PACKETLEN, tmpVal);
+
+    EMAC_SetMACAddress(cfg->macAddr);
+
+    void EMAC_IRQHandler(void);
+    Interrupt_Handler_Register(EMAC_IRQn, EMAC_IRQHandler);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  DeInitialize EMAC module
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type EMAC_DeInit(void)
+{
+    EMAC_Disable();
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Initialize EMAC TX RX MDA buffer
+ *
+ * @param  handle: EMAC handle pointer
+ * @param  txBuff: TX buffer
+ * @param  txBuffCount: TX buffer count
+ * @param  rxBuff: RX buffer
+ * @param  rxBuffCount: RX buffer count
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type EMAC_DMADescListInit(EMAC_Handle_Type *handle, uint8_t *txBuff, uint32_t txBuffCount, uint8_t *rxBuff, uint32_t rxBuffCount)
+{
+    uint32_t i = 0;
+
+    /* Set the Ethernet handler env */
+    handle->bd = (EMAC_BD_Desc_Type *)(EMAC_BASE + EMAC_DMA_DESC_OFFSET);
+    handle->txIndexEMAC = 0;
+    handle->txIndexCPU = 0;
+    handle->txBuffLimit = txBuffCount - 1;
+    /* The receive descriptors' address starts right after the last transmit BD. */
+    handle->rxIndexEMAC = txBuffCount;
+    handle->rxIndexCPU = txBuffCount;
+    handle->rxBuffLimit = txBuffCount + rxBuffCount - 1;
+
+    /* Fill each DMARxDesc descriptor with the right values */
+    for (i = 0; i < txBuffCount; i++) {
+        /* Get the pointer on the ith member of the Tx Desc list */
+        handle->bd[i].Buffer = (NULL == txBuff) ? 0 : (uint32_t)(txBuff + (ETH_MAX_PACKET_SIZE * i));
+        handle->bd[i].C_S_L = 0;
+    }
+
+    /* For the last TX DMA Descriptor, it should be wrap back */
+    handle->bd[handle->txBuffLimit].C_S_L |= EMAC_BD_FIELD_MSK(TX_WR);
+
+    for (i = txBuffCount; i < (txBuffCount + rxBuffCount); i++) {
+        /* Get the pointer on the ith member of the Rx Desc list */
+        handle->bd[i].Buffer = (NULL == rxBuff) ? 0 : (uint32_t)(rxBuff + (ETH_MAX_PACKET_SIZE * (i - txBuffCount)));
+        handle->bd[i].C_S_L = (ETH_MAX_PACKET_SIZE << 16) |
+                              EMAC_BD_FIELD_MSK(RX_IRQ) |
+                              EMAC_BD_FIELD_MSK(RX_E);
+    }
+
+    /* For the last RX DMA Descriptor, it should be wrap back */
+    handle->bd[handle->rxBuffLimit].C_S_L |= EMAC_BD_FIELD_MSK(RX_WR);
+
+    /* For the TX DMA Descriptor, it will wrap to 0 according to EMAC_TX_BD_NUM*/
+    BL_WR_REG(EMAC_BASE, EMAC_TX_BD_NUM, txBuffCount);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get TX MDA buffer descripter for data to send
+ *
+ * @param  handle: EMAC handle pointer
+ * @param  txDMADesc: TX DMA descriptor pointer
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type EMAC_DMATxDescGet(EMAC_Handle_Type *handle, EMAC_BD_Desc_Type **txDMADesc)
+{
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Start TX
+ *
+ * @param  handle: EMAC handle pointer
+ * @param  txDMADesc: TX DMA descriptor pointer
+ * @param  len: len
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type EMAC_StartTx(EMAC_Handle_Type *handle, EMAC_BD_Desc_Type *txDMADesc, uint32_t len)
+{
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable EMAC module
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type EMAC_Enable(void)
+{
+    uint32_t tmpVal;
+
+    /* Enable EMAC */
+    tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MODE);
+    tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_TXEN);
+    tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_RXEN);
+    BL_WR_REG(EMAC_BASE, EMAC_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  EMAC_Enable_TX
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type EMAC_Enable_TX(void)
+{
+    uint32_t tmpVal;
+
+    /* Enable EMAC */
+    tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MODE);
+    tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_TXEN);
+    BL_WR_REG(EMAC_BASE, EMAC_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  EMAC_Disable_TX
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type EMAC_Disable_TX(void)
+{
+    uint32_t tmpVal;
+
+    /* Enable EMAC */
+    tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MODE);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, EMAC_TXEN);
+    BL_WR_REG(EMAC_BASE, EMAC_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  EMAC_Enable_RX
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type EMAC_Enable_RX(void)
+{
+    uint32_t tmpval;
+
+    /* Enable EMAC TX*/
+    tmpval = BL_RD_REG(EMAC_BASE, EMAC_MODE);
+    tmpval = BL_SET_REG_BIT(tmpval, EMAC_RXEN);
+    BL_WR_REG(EMAC_BASE, EMAC_MODE, tmpval);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  EMAC_Disable_RX
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type EMAC_Disable_RX(void)
+{
+    uint32_t tmpval;
+
+    /* Disable EMAC RX*/
+    tmpval = BL_RD_REG(EMAC_BASE, EMAC_MODE);
+    tmpval = BL_CLR_REG_BIT(tmpval, EMAC_RXEN);
+    BL_WR_REG(EMAC_BASE, EMAC_MODE, tmpval);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable EMAC module
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type EMAC_Disable(void)
+{
+    uint32_t tmpVal;
+
+    /* Enable EMAC */
+    tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MODE);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, EMAC_TXEN);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, EMAC_RXEN);
+    BL_WR_REG(EMAC_BASE, EMAC_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  EMAC mask or unmask certain or all interrupt
+ *
+ * @param  intType: EMAC interrupt type
+ * @param  intMask: EMAC interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt )
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type EMAC_IntMask(EMAC_INT_Type intType, BL_Mask_Type intMask)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_BL_MASK_TYPE(intMask));
+
+    tmpVal = BL_RD_REG(EMAC_BASE, EMAC_INT_MASK);
+
+    /* Mask or unmask certain or all interrupt */
+    if (MASK == intMask) {
+        tmpVal |= intType;
+    } else {
+        tmpVal &= (~intType);
+    }
+
+    /* Write back */
+    BL_WR_REG(EMAC_BASE, EMAC_INT_MASK, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get EMAC interrupt status
+ *
+ * @param  intType: EMAC interrupt type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Sts_Type EMAC_GetIntStatus(EMAC_INT_Type intType)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_EMAC_INT_TYPE(intType));
+
+    tmpVal = BL_RD_REG(EMAC_BASE, EMAC_INT_SOURCE);
+
+    return (tmpVal & intType) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  Clear EMAC interrupt
+ *
+ * @param  intType: EMAC interrupt type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type EMAC_ClrIntStatus(EMAC_INT_Type intType)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_EMAC_INT_TYPE(intType));
+
+    tmpVal = BL_RD_REG(EMAC_BASE, EMAC_INT_SOURCE);
+
+    BL_WR_REG(EMAC_BASE, EMAC_INT_SOURCE, tmpVal | intType);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  EMAC_Int_Callback_Install
+ *
+ * @param  intIdx: EMAC_INT_Index
+ * @param  cbFun: call back
+ *
+ * @return None
+ *
+*******************************************************************************/
+BL_Err_Type EMAC_Int_Callback_Install(EMAC_INT_Index intIdx, intCallback_Type *cbFun)
+{
+    /* Check the parameters */
+
+    emacIntCbfArra[intIdx] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  EMAC_IRQHandler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void EMAC_IRQHandler(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(EMAC_BASE, EMAC_INT_MASK);
+
+    if (SET == EMAC_GetIntStatus(EMAC_INT_TX_DONE) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_TXB_M)) {
+        EMAC_ClrIntStatus(EMAC_INT_TX_DONE);
+
+        if (emacIntCbfArra[EMAC_INT_TX_DONE_IDX]) {
+            emacIntCbfArra[EMAC_INT_TX_DONE_IDX]();
+        }
+    }
+
+    if (SET == EMAC_GetIntStatus(EMAC_INT_TX_ERROR) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_TXE_M)) {
+        EMAC_ClrIntStatus(EMAC_INT_TX_ERROR);
+
+        if (emacIntCbfArra[EMAC_INT_TX_ERROR_IDX]) {
+            emacIntCbfArra[EMAC_INT_TX_ERROR_IDX]();
+        }
+    }
+
+    if (SET == EMAC_GetIntStatus(EMAC_INT_RX_DONE) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_RXB_M)) {
+        EMAC_ClrIntStatus(EMAC_INT_RX_DONE);
+
+        if (emacIntCbfArra[EMAC_INT_RX_DONE_IDX]) {
+            emacIntCbfArra[EMAC_INT_RX_DONE_IDX]();
+        }
+    }
+
+    if (SET == EMAC_GetIntStatus(EMAC_INT_RX_ERROR) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_RXE_M)) {
+        EMAC_ClrIntStatus(EMAC_INT_RX_ERROR);
+
+        if (emacIntCbfArra[EMAC_INT_RX_ERROR_IDX]) {
+            emacIntCbfArra[EMAC_INT_RX_ERROR_IDX]();
+        }
+    }
+
+    if (SET == EMAC_GetIntStatus(EMAC_INT_RX_BUSY) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_BUSY_M)) {
+        EMAC_ClrIntStatus(EMAC_INT_RX_BUSY);
+
+        if (emacIntCbfArra[EMAC_INT_RX_BUSY_IDX]) {
+            emacIntCbfArra[EMAC_INT_RX_BUSY_IDX]();
+        }
+    }
+
+    if (SET == EMAC_GetIntStatus(EMAC_INT_TX_CTRL) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_TXC_M)) {
+        EMAC_ClrIntStatus(EMAC_INT_TX_CTRL);
+
+        if (emacIntCbfArra[EMAC_INT_TX_CTRL_IDX]) {
+            emacIntCbfArra[EMAC_INT_TX_CTRL_IDX]();
+        }
+    }
+
+    if (SET == EMAC_GetIntStatus(EMAC_INT_RX_CTRL) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_RXC_M)) {
+        EMAC_ClrIntStatus(EMAC_INT_RX_CTRL);
+
+        if (emacIntCbfArra[EMAC_INT_RX_CTRL_IDX]) {
+            emacIntCbfArra[EMAC_INT_RX_CTRL_IDX]();
+        }
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Request to pause TX
+ *
+ * @param  timeCount: Pause time count
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type EMAC_TxPauseReq(uint16_t timeCount)
+{
+    BL_WR_REG(EMAC_BASE, EMAC_TXCTRL, (1 << 16) | timeCount);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set hash value
+ *
+ * @param  hash0: Hash value one
+ * @param  hash1: Hash value two
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type EMAC_SetHash(uint32_t hash0, uint32_t hash1)
+{
+    BL_WR_REG(EMAC_BASE, EMAC_HASH0_ADDR, hash0);
+
+    BL_WR_REG(EMAC_BASE, EMAC_HASH1_ADDR, hash1);
+
+    return SUCCESS;
+}
+
+/*@} end of group EMAC_Public_Functions */
+
+/*@} end of group EMAC */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_glb.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_glb.c
new file mode 100644
index 00000000..97c6d769
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_glb.c
@@ -0,0 +1,4038 @@
+/**
+  ******************************************************************************
+  * @file    bl702_glb.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_glb.h"
+#include "bl702_hbn.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  GLB
+ *  @{
+ */
+
+/** @defgroup  GLB_Private_Macros
+ *  @{
+ */
+#define GLB_CLK_SET_DUMMY_WAIT \
+    {                          \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+    }
+#define GLB_GPIO_Get_Reg(pin)       (glb_gpio_reg_t *)(GLB_BASE + GLB_GPIO_OFFSET + (pin / 2) * 4)
+#define GLB_GPIO_INT0_NUM           (32)
+#define GLB_REG_BCLK_DIS_TRUE       (*(volatile uint32_t *)(0x40000FFC) = (0x00000001))
+#define GLB_REG_BCLK_DIS_FALSE      (*(volatile uint32_t *)(0x40000FFC) = (0x00000000))
+#define GLB_GPIO_INT0_CLEAR_TIMEOUT (32)
+
+/*@} end of group GLB_Private_Macros */
+
+/** @defgroup  GLB_Private_Types
+ *  @{
+ */
+
+/*@} end of group GLB_Private_Types */
+
+/** @defgroup  GLB_Private_Variables
+ *  @{
+ */
+static intCallback_Type *glbBmxErrIntCbfArra[BMX_ERR_INT_ALL] = { NULL };
+static intCallback_Type *glbBmxToIntCbfArra[BMX_TO_INT_ALL] = { NULL };
+static intCallback_Type *glbGpioInt0CbfArra[GLB_GPIO_INT0_NUM] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+                                                                   NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+                                                                   NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+                                                                   NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL };
+static intCallback_Type *glbGpioInt0CbfArra2[GLB_GPIO_INT0_NUM] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+                                                                    NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+                                                                    NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+                                                                    NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL };
+
+/*@} end of group GLB_Private_Variables */
+
+/** @defgroup  GLB_Global_Variables
+ *  @{
+ */
+
+/*@} end of group GLB_Global_Variables */
+
+/** @defgroup  GLB_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group GLB_Private_Fun_Declaration */
+
+/** @defgroup  GLB_Private_Functions
+ *  @{
+ */
+
+/*@} end of group GLB_Private_Functions */
+
+/** @defgroup  GLB_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  get root clock selection
+ *
+ * @param  None
+ *
+ * @return root clock selection
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+GLB_ROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_Root_CLK_Sel(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+
+    switch (BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_ROOT_CLK_SEL)) {
+        case 0:
+            return GLB_ROOT_CLK_RC32M;
+        case 1:
+            return GLB_ROOT_CLK_XTAL;
+        case 2:
+        case 3:
+            return GLB_ROOT_CLK_DLL;
+        default:
+            return GLB_ROOT_CLK_RC32M;
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set System clock divider
+ *
+ * @param  hclkDiv: HCLK divider
+ * @param  bclkDiv: BCLK divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv)
+{
+    /***********************************************************************************/
+    /*                                 NOTE                                            */
+    /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */
+    /* OCRAM use bclk as source clock. Pay attention to risks when using this API.     */
+    /***********************************************************************************/
+    uint32_t tmpVal;
+
+    /* recommend: fclk<=160MHz, bclk<=80MHz */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, hclkDiv);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, bclkDiv);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
+    GLB_REG_BCLK_DIS_TRUE;
+    GLB_REG_BCLK_DIS_FALSE;
+    //SystemCoreClockSet(SystemCoreClockGet() / ((uint16_t)hclkDiv + 1));
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_HCLK_EN);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BCLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get Bus clock divider
+ *
+ * @param  None
+ *
+ * @return Clock Divider
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+uint8_t ATTR_CLOCK_SECTION GLB_Get_BCLK_Div(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Get CPU clock divider
+ *
+ * @param  None
+ *
+ * @return Clock Divider
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+uint8_t ATTR_CLOCK_SECTION GLB_Get_HCLK_Div(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  update SystemCoreClock value
+ *
+ * @param  xtalType: XTAL frequency type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION Update_SystemCoreClockWith_XTAL(GLB_DLL_XTAL_Type xtalType)
+{
+    CHECK_PARAM(IS_GLB_DLL_XTAL_TYPE(xtalType));
+
+    switch (xtalType) {
+        case GLB_DLL_XTAL_NONE:
+            break;
+        case GLB_DLL_XTAL_32M:
+            SystemCoreClockSet(32000000);
+            break;
+        case GLB_DLL_XTAL_RC32M:
+            SystemCoreClockSet(32000000);
+            break;
+        default:
+            break;
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set System clock
+ *
+ * @param  xtalType: XTAL frequency type
+ * @param  clkFreq: clock frequency selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK(GLB_DLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GLB_DLL_XTAL_TYPE(xtalType));
+    CHECK_PARAM(IS_GLB_SYS_CLK_TYPE(clkFreq));
+
+    /* reg_bclk_en = reg_hclk_en = reg_fclk_en = 1, cannot be zero */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BCLK_EN);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_HCLK_EN);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_FCLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
+
+    /* Before config XTAL and DLL ,make sure root clk is from RC32M */
+    HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M);
+    GLB_Set_System_CLK_Div(0, 0);
+    SystemCoreClockSet(32 * 1000 * 1000);
+
+    if (xtalType == GLB_DLL_XTAL_NONE) {
+        if (clkFreq == GLB_SYS_CLK_RC32M) {
+            return SUCCESS;
+        } else {
+            return ERROR;
+        }
+    }
+
+    if (xtalType != GLB_DLL_XTAL_RC32M) {
+        /* power on xtal first */
+        AON_Power_On_XTAL();
+    }
+
+    /* Bl702 make PLL Setting out of RF, so following setting can be removed*/
+    //AON_Power_On_MBG();
+    //AON_Power_On_LDO15_RF();
+
+    /* always power up PLL and enable all PLL clock output */
+    //PDS_Power_On_PLL((PDS_PLL_XTAL_Type)xtalType);
+    //BL702_Delay_US(55);
+    //PDS_Enable_PLL_All_Clks();
+
+    /* always power up DLL and enable all DLL clock output */
+    GLB_Power_Off_DLL();
+    GLB_Power_On_DLL(xtalType);
+    GLB_Enable_DLL_All_Clks();
+
+    /* reg_pll_en = 1, cannot be zero */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PLL_EN);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
+
+    /* select pll output clock before select root clock */
+    if (clkFreq >= GLB_SYS_CLK_DLL57P6M) {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PLL_SEL, clkFreq - GLB_SYS_CLK_DLL57P6M);
+        BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
+    }
+    /* select root clock */
+    switch (clkFreq) {
+        case GLB_SYS_CLK_RC32M:
+            break;
+        case GLB_SYS_CLK_XTAL:
+            HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL);
+            Update_SystemCoreClockWith_XTAL(xtalType);
+            break;
+        case GLB_SYS_CLK_DLL57P6M:
+            HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_DLL);
+            SystemCoreClockSet(57 * 6000 * 1000);
+            break;
+        case GLB_SYS_CLK_DLL96M:
+            L1C_IROM_2T_Access_Set(ENABLE);
+            GLB_Set_System_CLK_Div(0, 1);
+            HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_DLL);
+            SystemCoreClockSet(96 * 1000 * 1000);
+            break;
+        case GLB_SYS_CLK_DLL144M:
+            L1C_IROM_2T_Access_Set(ENABLE);
+            GLB_Set_System_CLK_Div(0, 1);
+            HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_DLL);
+            SystemCoreClockSet(144 * 1000 * 1000);
+            break;
+        default:
+            break;
+    }
+
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  This is demo for user that use RC32M as default bootup clock instead of DLL,when APP is
+ *         started, this function can be called to set DLL to 160M
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION System_Core_Clock_Update_From_RC32M(void)
+{
+    SF_Ctrl_Cfg_Type sfCtrlCfg = {
+        .owner = SF_CTRL_OWNER_IAHB,
+        .clkDelay = 1,
+        .clkInvert = 1,
+        .rxClkInvert = 1,
+        .doDelay = 0,
+        .diDelay = 0,
+        .oeDelay = 0,
+    };
+    /* Use RC32M as DLL ref source to set up DLL to 144M */
+    GLB_Set_System_CLK(GLB_DLL_XTAL_RC32M, GLB_SYS_CLK_DLL144M);
+    /* Flash controller also need changes since system (bus) clock changed */
+    SF_Ctrl_Enable(&sfCtrlCfg);
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  set CAM clock
+ *
+ * @param  enable: Enable or disable CAM clock
+ * @param  clkSel: CAM clock type
+ * @param  div: clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_CAM_CLK(uint8_t enable, GLB_CAM_CLK_Type clkSel, uint8_t div)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_CAM_CLK_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_SRC_SEL, clkSel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set mac154 and zigbee clock
+ *
+ * @param  enable: Enable or disable mac154 and zigbee clock
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_MAC154_ZIGBEE_CLK(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_M154_ZBEN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_M154_ZBEN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set BLE clock
+ *
+ * @param  enable: Enable or disable BLE clock
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_BLE_CLK(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BLE_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BLE_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set I2S clock
+ *
+ * @param  enable: Enable or disable I2S clock
+ * @param  outRef: I2S output ref clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_I2S_CLK(uint8_t enable, GLB_I2S_OUT_REF_CLK_Type outRef)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_I2S_OUT_REF_CLK_TYPE(outRef));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_0_REF_CLK_OE, outRef);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_I2S0_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_I2S0_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set USB clock
+ *
+ * @param  enable: Enable or disable USB clock
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_USB_CLK(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_48M_DIV_EN, 1);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_USB_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_USB_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set QDEC clock
+ *
+ * @param  clkSel: QDEC clock type
+ * @param  div: clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_QDEC_CLK(GLB_QDEC_CLK_Type clkSel, uint8_t div)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_QDEC_CLK_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_QDEC_CLK_SEL, clkSel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_QDEC_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set DMA clock
+ *
+ * @param  enable: Enable or disable DMA clock
+ * @param  clk: DMA ID type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN);
+    if (enable) {
+        tmpVal2 |= (1 << clk);
+    } else {
+        tmpVal2 &= (~(1 << clk));
+    }
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN, tmpVal2);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set IR clock divider
+ *
+ * @param  enable: enable or disable IR clock
+ * @param  clkSel: IR clock type
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_IR_CLK_SRC_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x3F));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_IR_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set sflash clock
+ *
+ * @param  enable: Enable or disable sflash clock
+ * @param  clkSel: sflash clock type
+ * @param  div: clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div)
+{
+    uint32_t tmpVal = 0;
+    GLB_DLL_CLK_Type clk;
+
+    CHECK_PARAM(IS_GLB_SFLASH_CLK_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x7));
+
+    /* disable SFLASH clock first */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    /* Select flash clock, all Flash CLKs are divied by DLL_288M */
+    clk = GLB_DLL_CLK_288M;
+    GLB_Enable_DLL_Clk(clk);
+    /* clock divider */
+    /* Select flash clock, all Flash CLKs are divied by DLL_288M */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV, div);
+    switch (clkSel) {
+        case GLB_SFLASH_CLK_144M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x0);
+            break;
+        case GLB_SFLASH_CLK_XCLK:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x1);
+            break;
+        case GLB_SFLASH_CLK_57P6M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x3);
+            break;
+        case GLB_SFLASH_CLK_72M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x1);
+            break;
+        case GLB_SFLASH_CLK_BCLK:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x2);
+            break;
+        case GLB_SFLASH_CLK_96M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x3);
+            break;
+        default:
+            break;
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    /* enable or disable flash clock */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SF_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  set UART clock
+ *
+ * @param  enable: Enable or disable UART clock
+ * @param  clkSel: UART clock type
+ * @param  div: clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((div <= 0x7));
+    CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel));
+
+    /* disable UART clock first */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    /* Set div */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    /* Select clock source for uart */
+    HBN_Set_UART_CLK_Sel(clkSel);
+
+    /* Set enable or disable */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_UART_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  select chip clock out 0 type
+ *
+ * @param  clkSel: chip clock out type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Chip_Out_0_CLK_Sel(GLB_CHIP_CLK_OUT_Type clkSel)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_CHIP_CLK_OUT_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  select chip clock out 1 type
+ *
+ * @param  clkSel: chip clock out type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Chip_Out_1_CLK_Sel(GLB_CHIP_CLK_OUT_Type clkSel)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_CHIP_CLK_OUT_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set I2C clock
+ *
+ * @param  enable: Enable or disable I2C clock
+ * @param  div: clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, uint8_t div)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_I2C_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  invert eth rx clock
+ *
+ * @param  enable: invert or not invert
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Invert_ETH_RX_CLK(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_RX_CLK);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_RX_CLK);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  invert rf test clock out
+ *
+ * @param  enable: invert or not invert
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Invert_RF_TEST_O_CLK(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_RF_TEST_CLK_O);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_RF_TEST_CLK_O);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set SPI clock
+ *
+ * @param  enable: Enable or disable SPI clock
+ * @param  div: clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, uint8_t div)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((div <= 0x1F));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SPI_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  invert eth tx clock
+ *
+ * @param  enable: invert or not invert
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Invert_ETH_TX_CLK(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_TX_CLK);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_TX_CLK);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  invert eth ref clock out
+ *
+ * @param  enable: invert or not invert
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Invert_ETH_REF_O_CLK(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_REF_CLK_O);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_REF_CLK_O);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  select eth ref clock out
+ *
+ * @param  clkSel: eth ref clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_Type clkSel)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_SEL_ETH_REF_CLK_O, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  select PKA clock source
+ *
+ * @param  clkSel: PKA clock selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_PKA_CLK_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Software system reset
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_SW_System_Reset(void)
+{
+    /***********************************************************************************/
+    /*                                 NOTE                                            */
+    /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */
+    /* OCRAM use bclk as source clock. Pay attention to risks when using this API.     */
+    /***********************************************************************************/
+    uint32_t tmpVal;
+
+    /* Swicth clock to 32M as default */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    /* HCLK is RC32M , so BCLK/HCLK no need divider */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
+    GLB_REG_BCLK_DIS_TRUE;
+    GLB_REG_BCLK_DIS_FALSE;
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    /* Do reset */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_PWRON_RST);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    /* waiting for reset */
+    while (1) {
+        BL702_Delay_US(10);
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Software CPU reset
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_SW_CPU_Reset(void)
+{
+    /***********************************************************************************/
+    /*                                 NOTE                                            */
+    /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */
+    /* OCRAM use bclk as source clock. Pay attention to risks when using this API.     */
+    /***********************************************************************************/
+    uint32_t tmpVal;
+
+    /* Swicth clock to 32M as default */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    /* HCLK is RC32M , so BCLK/HCLK no need divider */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
+    GLB_REG_BCLK_DIS_TRUE;
+    GLB_REG_BCLK_DIS_FALSE;
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    /* Do reset */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_SYS_RESET);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_PWRON_RST);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    /* waiting for reset */
+    while (1) {
+        BL702_Delay_US(10);
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Software power on reset
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_SW_POR_Reset(void)
+{
+    /***********************************************************************************/
+    /*                                 NOTE                                            */
+    /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */
+    /* OCRAM use bclk as source clock. Pay attention to risks when using this API.     */
+    /***********************************************************************************/
+    uint32_t tmpVal;
+
+    /* Swicth clock to 32M as default */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    /* HCLK is RC32M , so BCLK/HCLK no need divider */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
+    GLB_REG_BCLK_DIS_TRUE;
+    GLB_REG_BCLK_DIS_FALSE;
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    /* Do reset */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    /* waiting for reset */
+    while (1) {
+        BL702_Delay_US(10);
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Reset slave 1
+ *
+ * @param  slave1: slave num
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_AHB_Slave1_Reset(BL_AHB_Slave1_Type slave1)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
+    tmpVal &= (~(1 << slave1));
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmpVal);
+    BL_DRV_DUMMY;
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
+    tmpVal |= (1 << slave1);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmpVal);
+    BL_DRV_DUMMY;
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
+    tmpVal &= (~(1 << slave1));
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  clock gate
+ *
+ * @param  enable: ENABLE or DISABLE
+ * @param  slave1: AHB slaveClk type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_AHB_Slave1_Clock_Gate(uint8_t enable, BL_AHB_Slave1_Type slave1)
+{
+    /* gate QDEC <=> gate QDEC0 + QDEC1 +QDEC2 + I2S */
+    /* gate I2S  <=> gate I2S + QDEC2                */
+
+    uint32_t tmpVal = 0;
+
+    if ((BL_AHB_SLAVE1_GLB == slave1) || (BL_AHB_SLAVE1_TZ2 == slave1) ||
+        (BL_AHB_SLAVE1_CCI == slave1) || (BL_AHB_SLAVE1_L1C == slave1) ||
+        (BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM == slave1)) {
+        /* not support */
+        return ERROR;
+    }
+
+    /* gate QDEC and I2S */
+    if (BL_AHB_SLAVE1_QDEC == slave1) {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
+        if (enable) {
+            /* clear bit means clock gate */
+            tmpVal &= (~(1 << 0x18));
+            tmpVal &= (~(1 << 0x19));
+            tmpVal &= (~(1 << 0x1A));
+        } else {
+            /* set bit means clock pass */
+            tmpVal |= (1 << 0x18);
+            tmpVal |= (1 << 0x19);
+            tmpVal |= (1 << 0x1A);
+        }
+        BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
+        return SUCCESS;
+    }
+
+    /* gate KYS */
+    if (BL_AHB_SLAVE1_KYS == slave1) {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
+        if (enable) {
+            /* clear bit means clock gate */
+            tmpVal &= (~(1 << 0x1B));
+        } else {
+            /* set bit means clock pass */
+            tmpVal |= (1 << 0x1B);
+        }
+        BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
+        return SUCCESS;
+    }
+
+    /* gate I2S and QDEC2 */
+    if (BL_AHB_SLAVE1_I2S == slave1) {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
+        if (enable) {
+            /* clear bit means clock gate */
+            tmpVal &= (~(1 << 0x1A));
+        } else {
+            /* set bit means clock pass */
+            tmpVal |= (1 << 0x1A);
+        }
+        BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
+        return SUCCESS;
+    }
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
+    if (enable) {
+        /* clear bit means clock gate */
+        tmpVal &= (~(1 << slave1));
+    } else {
+        /* set bit means clock pass */
+        tmpVal |= (1 << slave1);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get IPs clock gate value
+ *
+ * @param  None
+ *
+ * @return clock gate value
+ *
+*******************************************************************************/
+uint64_t GLB_PER_Clock_Gate_Status_Get(void)
+{
+    /* api request from cjy */
+
+    uint32_t tmpValCfg0 = 0;
+    uint32_t tmpValCfg1 = 0;
+    uint32_t tmpValCfg2 = 0;
+    uint32_t targetBit = 0;
+    uint64_t targetVal = 0;
+
+    tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
+    tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
+    tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);
+    for (uint8_t i = 0; i < 64; i++) {
+        targetBit = 0;
+        switch (i) {
+            case GLB_AHB_CLOCK_IP_CPU:
+                targetBit = tmpValCfg0 & (1 << 0);
+                break;
+            case GLB_AHB_CLOCK_IP_SDU:
+                targetBit = tmpValCfg0 & (1 << 1);
+                break;
+            case GLB_AHB_CLOCK_IP_SEC:
+                targetBit = (tmpValCfg0 & (1 << 2)) && (tmpValCfg1 & (1 << 3)) && (tmpValCfg1 & (1 << 4));
+                break;
+            case GLB_AHB_CLOCK_IP_DMA_0:
+                targetBit = (tmpValCfg0 & (1 << 3)) && (tmpValCfg1 & (1 << 12));
+                break;
+            case GLB_AHB_CLOCK_IP_DMA_1:
+                break;
+            case GLB_AHB_CLOCK_IP_DMA_2:
+                break;
+            case GLB_AHB_CLOCK_IP_CCI:
+                targetBit = tmpValCfg0 & (1 << 4);
+                break;
+            case GLB_AHB_CLOCK_IP_RF_TOP:
+                break;
+            case GLB_AHB_CLOCK_IP_GPIP:
+                targetBit = tmpValCfg1 & (1 << 2);
+                break;
+            case GLB_AHB_CLOCK_IP_TZC:
+                targetBit = tmpValCfg1 & (1 << 5);
+                break;
+            case GLB_AHB_CLOCK_IP_EF_CTRL:
+                targetBit = tmpValCfg1 & (1 << 7);
+                break;
+            case GLB_AHB_CLOCK_IP_SF_CTRL:
+                targetBit = tmpValCfg1 & (1 << 11);
+                break;
+            case GLB_AHB_CLOCK_IP_EMAC:
+                targetBit = tmpValCfg1 & (1 << 13);
+                break;
+            case GLB_AHB_CLOCK_IP_UART0:
+                targetBit = tmpValCfg1 & (1 << 16);
+                break;
+            case GLB_AHB_CLOCK_IP_UART1:
+                targetBit = tmpValCfg1 & (1 << 17);
+                break;
+            case GLB_AHB_CLOCK_IP_UART2:
+                break;
+            case GLB_AHB_CLOCK_IP_UART3:
+                break;
+            case GLB_AHB_CLOCK_IP_UART4:
+                break;
+            case GLB_AHB_CLOCK_IP_SPI:
+                targetBit = tmpValCfg1 & (1 << 18);
+                break;
+            case GLB_AHB_CLOCK_IP_I2C:
+                targetBit = tmpValCfg1 & (1 << 19);
+                break;
+            case GLB_AHB_CLOCK_IP_PWM:
+                targetBit = tmpValCfg1 & (1 << 20);
+                break;
+            case GLB_AHB_CLOCK_IP_TIMER:
+                targetBit = tmpValCfg1 & (1 << 21);
+                break;
+            case GLB_AHB_CLOCK_IP_IR:
+                targetBit = tmpValCfg1 & (1 << 22);
+                break;
+            case GLB_AHB_CLOCK_IP_CHECKSUM:
+                targetBit = tmpValCfg1 & (1 << 23);
+                break;
+            case GLB_AHB_CLOCK_IP_QDEC:
+                targetBit = (tmpValCfg1 & (1 << 24)) && (tmpValCfg1 & (1 << 25)) && (tmpValCfg1 & (1 << 26));
+                break;
+            case GLB_AHB_CLOCK_IP_KYS:
+                targetBit = tmpValCfg1 & (1 << 27);
+                break;
+            case GLB_AHB_CLOCK_IP_I2S:
+                targetBit = tmpValCfg1 & (1 << 26);
+                break;
+            case GLB_AHB_CLOCK_IP_USB11:
+                targetBit = tmpValCfg1 & (1 << 28);
+                break;
+            case GLB_AHB_CLOCK_IP_CAM:
+                targetBit = tmpValCfg1 & (1 << 29);
+                break;
+            case GLB_AHB_CLOCK_IP_MJPEG:
+                targetBit = tmpValCfg1 & (1 << 30);
+                break;
+            case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL:
+                targetBit = (tmpValCfg2 & (1 << 0)) && (tmpValCfg2 & (1 << 4));
+                break;
+            case GLB_AHB_CLOCK_IP_BT_BLE_LP:
+                break;
+            case GLB_AHB_CLOCK_IP_ZB_NORMAL:
+                targetBit = tmpValCfg2 & (1 << 0);
+                break;
+            case GLB_AHB_CLOCK_IP_ZB_LP:
+                break;
+            case GLB_AHB_CLOCK_IP_WIFI_NORMAL:
+                break;
+            case GLB_AHB_CLOCK_IP_WIFI_LP:
+                break;
+            case GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL:
+                break;
+            case GLB_AHB_CLOCK_IP_BT_BLE_2_LP:
+                break;
+            case GLB_AHB_CLOCK_IP_EMI_MISC:
+                break;
+            case GLB_AHB_CLOCK_IP_PSRAM0_CTRL:
+                break;
+            case GLB_AHB_CLOCK_IP_PSRAM1_CTRL:
+                break;
+            case GLB_AHB_CLOCK_IP_USB20:
+                break;
+            case GLB_AHB_CLOCK_IP_MIX2:
+                break;
+            case GLB_AHB_CLOCK_IP_AUDIO:
+                break;
+            case GLB_AHB_CLOCK_IP_SDH:
+                break;
+            default:
+                break;
+        }
+        if (!targetBit) {
+            targetVal |= ((uint64_t)1 << i);
+        }
+    }
+
+    return targetVal;
+}
+
+/****************************************************************************/ /**
+ * @brief  get first 1 from u64, then clear it
+ *
+ * @param  val: target value
+ * @param  bit: first 1 in bit
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+static BL_Err_Type GLB_Get_And_Clr_First_Set_From_U64(uint64_t *val, uint32_t *bit)
+{
+    if (!*val) {
+        return ERROR;
+    }
+
+    for (uint8_t i = 0; i < 64; i++) {
+        if ((*val) & ((uint64_t)1 << i)) {
+            *bit = i;
+            (*val) &= ~((uint64_t)1 << i);
+            break;
+        }
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  hold IPs clock
+ *
+ * @param  ips: GLB_AHB_CLOCK_IP_xxx | GLB_AHB_CLOCK_IP_xxx | ......
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_PER_Clock_Gate(uint64_t ips)
+{
+    /* api request from cjy */
+
+    uint32_t tmpValCfg0 = 0;
+    uint32_t tmpValCfg1 = 0;
+    uint32_t tmpValCfg2 = 0;
+    uint32_t bitfield = 0;
+
+    tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
+    tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
+    tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);
+    while (ips) {
+        if (SUCCESS == GLB_Get_And_Clr_First_Set_From_U64(&ips, &bitfield)) {
+            switch (bitfield) {
+                case GLB_AHB_CLOCK_IP_CPU:
+                    tmpValCfg0 &= ~(1 << 0);
+                    break;
+                case GLB_AHB_CLOCK_IP_SDU:
+                    tmpValCfg0 &= ~(1 << 1);
+                    break;
+                case GLB_AHB_CLOCK_IP_SEC:
+                    tmpValCfg0 &= ~(1 << 2);
+                    tmpValCfg1 &= ~(1 << 3);
+                    tmpValCfg1 &= ~(1 << 4);
+                    break;
+                case GLB_AHB_CLOCK_IP_DMA_0:
+                    tmpValCfg0 &= ~(1 << 3);
+                    tmpValCfg1 &= ~(1 << 12);
+                    break;
+                case GLB_AHB_CLOCK_IP_DMA_1:
+                    break;
+                case GLB_AHB_CLOCK_IP_DMA_2:
+                    break;
+                case GLB_AHB_CLOCK_IP_CCI:
+                    tmpValCfg0 &= ~(1 << 4);
+                    break;
+                case GLB_AHB_CLOCK_IP_RF_TOP:
+                    break;
+                case GLB_AHB_CLOCK_IP_GPIP:
+                    tmpValCfg1 &= ~(1 << 2);
+                    break;
+                case GLB_AHB_CLOCK_IP_TZC:
+                    tmpValCfg1 &= ~(1 << 5);
+                    break;
+                case GLB_AHB_CLOCK_IP_EF_CTRL:
+                    tmpValCfg1 &= ~(1 << 7);
+                    break;
+                case GLB_AHB_CLOCK_IP_SF_CTRL:
+                    tmpValCfg1 &= ~(1 << 11);
+                    break;
+                case GLB_AHB_CLOCK_IP_EMAC:
+                    tmpValCfg1 &= ~(1 << 13);
+                    break;
+                case GLB_AHB_CLOCK_IP_UART0:
+                    tmpValCfg1 &= ~(1 << 16);
+                    break;
+                case GLB_AHB_CLOCK_IP_UART1:
+                    tmpValCfg1 &= ~(1 << 17);
+                    break;
+                case GLB_AHB_CLOCK_IP_UART2:
+                    break;
+                case GLB_AHB_CLOCK_IP_UART3:
+                    break;
+                case GLB_AHB_CLOCK_IP_UART4:
+                    break;
+                case GLB_AHB_CLOCK_IP_SPI:
+                    tmpValCfg1 &= ~(1 << 18);
+                    break;
+                case GLB_AHB_CLOCK_IP_I2C:
+                    tmpValCfg1 &= ~(1 << 19);
+                    break;
+                case GLB_AHB_CLOCK_IP_PWM:
+                    tmpValCfg1 &= ~(1 << 20);
+                    break;
+                case GLB_AHB_CLOCK_IP_TIMER:
+                    tmpValCfg1 &= ~(1 << 21);
+                    break;
+                case GLB_AHB_CLOCK_IP_IR:
+                    tmpValCfg1 &= ~(1 << 22);
+                    break;
+                case GLB_AHB_CLOCK_IP_CHECKSUM:
+                    tmpValCfg1 &= ~(1 << 23);
+                    break;
+                case GLB_AHB_CLOCK_IP_QDEC:
+                    tmpValCfg1 &= ~(1 << 24);
+                    tmpValCfg1 &= ~(1 << 25);
+                    tmpValCfg1 &= ~(1 << 26);
+                    break;
+                case GLB_AHB_CLOCK_IP_KYS:
+                    tmpValCfg1 &= ~(1 << 27);
+                    break;
+                case GLB_AHB_CLOCK_IP_I2S:
+                    tmpValCfg1 &= ~(1 << 26);
+                    break;
+                case GLB_AHB_CLOCK_IP_USB11:
+                    tmpValCfg1 &= ~(1 << 28);
+                    break;
+                case GLB_AHB_CLOCK_IP_CAM:
+                    tmpValCfg1 &= ~(1 << 29);
+                    break;
+                case GLB_AHB_CLOCK_IP_MJPEG:
+                    tmpValCfg1 &= ~(1 << 30);
+                    break;
+                case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL:
+                    tmpValCfg2 &= ~(1 << 0);
+                    tmpValCfg2 &= ~(1 << 4);
+                    break;
+                case GLB_AHB_CLOCK_IP_BT_BLE_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_ZB_NORMAL:
+                    tmpValCfg2 &= ~(1 << 0);
+                    break;
+                case GLB_AHB_CLOCK_IP_ZB_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_WIFI_NORMAL:
+                    break;
+                case GLB_AHB_CLOCK_IP_WIFI_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL:
+                    break;
+                case GLB_AHB_CLOCK_IP_BT_BLE_2_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_EMI_MISC:
+                    break;
+                case GLB_AHB_CLOCK_IP_PSRAM0_CTRL:
+                    break;
+                case GLB_AHB_CLOCK_IP_PSRAM1_CTRL:
+                    break;
+                case GLB_AHB_CLOCK_IP_USB20:
+                    break;
+                case GLB_AHB_CLOCK_IP_MIX2:
+                    break;
+                case GLB_AHB_CLOCK_IP_AUDIO:
+                    break;
+                case GLB_AHB_CLOCK_IP_SDH:
+                    break;
+                default:
+                    break;
+            }
+        }
+    }
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpValCfg0);
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpValCfg1);
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  release IPs clock
+ *
+ * @param  ips: GLB_AHB_CLOCK_IP_xxx | GLB_AHB_CLOCK_IP_xxx | ......
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_PER_Clock_UnGate(uint64_t ips)
+{
+    /* api request from cjy */
+
+    uint32_t tmpValCfg0 = 0;
+    uint32_t tmpValCfg1 = 0;
+    uint32_t tmpValCfg2 = 0;
+    uint32_t bitfield = 0;
+
+    tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
+    tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
+    tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);
+    while (ips) {
+        if (SUCCESS == GLB_Get_And_Clr_First_Set_From_U64(&ips, &bitfield)) {
+            switch (bitfield) {
+                case GLB_AHB_CLOCK_IP_CPU:
+                    tmpValCfg0 |= (1 << 0);
+                    break;
+                case GLB_AHB_CLOCK_IP_SDU:
+                    tmpValCfg0 |= (1 << 1);
+                    break;
+                case GLB_AHB_CLOCK_IP_SEC:
+                    tmpValCfg0 |= (1 << 2);
+                    tmpValCfg1 |= (1 << 3);
+                    tmpValCfg1 |= (1 << 4);
+                    break;
+                case GLB_AHB_CLOCK_IP_DMA_0:
+                    tmpValCfg0 |= (1 << 3);
+                    tmpValCfg1 |= (1 << 12);
+                    break;
+                case GLB_AHB_CLOCK_IP_DMA_1:
+                    break;
+                case GLB_AHB_CLOCK_IP_DMA_2:
+                    break;
+                case GLB_AHB_CLOCK_IP_CCI:
+                    tmpValCfg0 |= (1 << 4);
+                    break;
+                case GLB_AHB_CLOCK_IP_RF_TOP:
+                    break;
+                case GLB_AHB_CLOCK_IP_GPIP:
+                    tmpValCfg1 |= (1 << 2);
+                    break;
+                case GLB_AHB_CLOCK_IP_TZC:
+                    tmpValCfg1 |= (1 << 5);
+                    break;
+                case GLB_AHB_CLOCK_IP_EF_CTRL:
+                    tmpValCfg1 |= (1 << 7);
+                    break;
+                case GLB_AHB_CLOCK_IP_SF_CTRL:
+                    tmpValCfg1 |= (1 << 11);
+                    break;
+                case GLB_AHB_CLOCK_IP_EMAC:
+                    tmpValCfg1 |= (1 << 13);
+                    break;
+                case GLB_AHB_CLOCK_IP_UART0:
+                    tmpValCfg1 |= (1 << 16);
+                    break;
+                case GLB_AHB_CLOCK_IP_UART1:
+                    tmpValCfg1 |= (1 << 17);
+                    break;
+                case GLB_AHB_CLOCK_IP_UART2:
+                    break;
+                case GLB_AHB_CLOCK_IP_UART3:
+                    break;
+                case GLB_AHB_CLOCK_IP_UART4:
+                    break;
+                case GLB_AHB_CLOCK_IP_SPI:
+                    tmpValCfg1 |= (1 << 18);
+                    break;
+                case GLB_AHB_CLOCK_IP_I2C:
+                    tmpValCfg1 |= (1 << 19);
+                    break;
+                case GLB_AHB_CLOCK_IP_PWM:
+                    tmpValCfg1 |= (1 << 20);
+                    break;
+                case GLB_AHB_CLOCK_IP_TIMER:
+                    tmpValCfg1 |= (1 << 21);
+                    break;
+                case GLB_AHB_CLOCK_IP_IR:
+                    tmpValCfg1 |= (1 << 22);
+                    break;
+                case GLB_AHB_CLOCK_IP_CHECKSUM:
+                    tmpValCfg1 |= (1 << 23);
+                    break;
+                case GLB_AHB_CLOCK_IP_QDEC:
+                    tmpValCfg1 |= (1 << 24);
+                    tmpValCfg1 |= (1 << 25);
+                    tmpValCfg1 |= (1 << 26);
+                    break;
+                case GLB_AHB_CLOCK_IP_KYS:
+                    tmpValCfg1 |= (1 << 27);
+                    break;
+                case GLB_AHB_CLOCK_IP_I2S:
+                    tmpValCfg1 |= (1 << 26);
+                    break;
+                case GLB_AHB_CLOCK_IP_USB11:
+                    tmpValCfg1 |= (1 << 28);
+                    break;
+                case GLB_AHB_CLOCK_IP_CAM:
+                    tmpValCfg1 |= (1 << 29);
+                    break;
+                case GLB_AHB_CLOCK_IP_MJPEG:
+                    tmpValCfg1 |= (1 << 30);
+                    break;
+                case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL:
+                    tmpValCfg2 |= (1 << 0);
+                    tmpValCfg2 |= (1 << 4);
+                    break;
+                case GLB_AHB_CLOCK_IP_BT_BLE_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_ZB_NORMAL:
+                    tmpValCfg2 |= (1 << 0);
+                    break;
+                case GLB_AHB_CLOCK_IP_ZB_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_WIFI_NORMAL:
+                    break;
+                case GLB_AHB_CLOCK_IP_WIFI_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL:
+                    break;
+                case GLB_AHB_CLOCK_IP_BT_BLE_2_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_EMI_MISC:
+                    break;
+                case GLB_AHB_CLOCK_IP_PSRAM0_CTRL:
+                    break;
+                case GLB_AHB_CLOCK_IP_PSRAM1_CTRL:
+                    break;
+                case GLB_AHB_CLOCK_IP_USB20:
+                    break;
+                case GLB_AHB_CLOCK_IP_MIX2:
+                    break;
+                case GLB_AHB_CLOCK_IP_AUDIO:
+                    break;
+                case GLB_AHB_CLOCK_IP_SDH:
+                    break;
+                default:
+                    break;
+            }
+        }
+    }
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpValCfg0);
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpValCfg1);
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX init
+ *
+ * @param  BmxCfg: BMX config
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_BMX_Init(BMX_Cfg_Type *BmxCfg)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((BmxCfg->timeoutEn) <= 0xF);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_TIMEOUT_EN, BmxCfg->timeoutEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_EN, BmxCfg->errEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_ARB_MODE, BmxCfg->arbMod);
+    BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal);
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(BMX_ERR_IRQn, BMX_ERR_IRQHandler);
+    Interrupt_Handler_Register(BMX_TO_IRQn, BMX_TO_IRQHandler);
+#endif
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX address monitor enable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_BMX_Addr_Monitor_Enable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BMX_ERR_ADDR_DIS);
+    BL_WR_REG(GLB_BASE, GLB_BMX_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX address monitor disable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_BMX_Addr_Monitor_Disable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BMX_ERR_ADDR_DIS);
+    BL_WR_REG(GLB_BASE, GLB_BMX_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX bus error response enable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_BMX_BusErrResponse_Enable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BMX_ERR_EN);
+    BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX bus error response disable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_BMX_BusErrResponse_Disable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BMX_ERR_EN);
+    BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get BMX error status
+ *
+ * @param  errType: BMX error status type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type GLB_BMX_Get_Status(BMX_BUS_ERR_Type errType)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_BMX_BUS_ERR_TYPE(errType));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2);
+    if (errType == BMX_BUS_ERR_TRUSTZONE_DECODE) {
+        return BL_GET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_TZ) ? SET : RESET;
+    } else {
+        return BL_GET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_DEC) ? SET : RESET;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Get BMX error address
+ *
+ * @param  None
+ *
+ * @return NP BMX error address
+ *
+*******************************************************************************/
+uint32_t GLB_BMX_Get_Err_Addr(void)
+{
+    return BL_RD_REG(GLB_BASE, GLB_BMX_ERR_ADDR);
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX error interrupt callback install
+ *
+ * @param  intType: BMX error interrupt type
+ * @param  cbFun: callback
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type BMX_ERR_INT_Callback_Install(BMX_ERR_INT_Type intType, intCallback_Type *cbFun)
+{
+    CHECK_PARAM(IS_BMX_ERR_INT_TYPE(intType));
+
+    glbBmxErrIntCbfArra[intType] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX ERR interrupt IRQ handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void BMX_ERR_IRQHandler(void)
+{
+    BMX_ERR_INT_Type intType;
+
+    for (intType = BMX_ERR_INT_ERR; intType < BMX_ERR_INT_ALL; intType++) {
+        if (glbBmxErrIntCbfArra[intType] != NULL) {
+            glbBmxErrIntCbfArra[intType]();
+        }
+    }
+
+    while (1) {
+        //MSG("BMX_ERR_IRQHandler\r\n");
+        BL702_Delay_MS(1000);
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  BMX timeout interrupt callback install
+ *
+ * @param  intType: BMX timeout interrupt type
+ * @param  cbFun: callback
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun)
+{
+    CHECK_PARAM(IS_BMX_TO_INT_TYPE(intType));
+
+    glbBmxToIntCbfArra[intType] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX Time Out interrupt IRQ handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void BMX_TO_IRQHandler(void)
+{
+    BMX_TO_INT_Type intType;
+
+    for (intType = BMX_TO_INT_TIMEOUT; intType < BMX_TO_INT_ALL; intType++) {
+        if (glbBmxToIntCbfArra[intType] != NULL) {
+            glbBmxToIntCbfArra[intType]();
+        }
+    }
+
+    while (1) {
+        //MSG("BMX_TO_IRQHandler\r\n");
+        BL702_Delay_MS(1000);
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  set sram_ret value
+ *
+ * @param  value: value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SRAM_RET(uint32_t value)
+{
+    BL_WR_REG(GLB_BASE, GLB_SRAM_RET, value);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get sram_ret value
+ *
+ * @param  None
+ *
+ * @return value
+ *
+*******************************************************************************/
+uint32_t GLB_Get_SRAM_RET(void)
+{
+    return BL_RD_REG(GLB_BASE, GLB_SRAM_RET);
+}
+
+/****************************************************************************/ /**
+ * @brief  set sram_slp value
+ *
+ * @param  value: value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value)
+{
+    BL_WR_REG(GLB_BASE, GLB_SRAM_SLP, value);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get sram_slp value
+ *
+ * @param  None
+ *
+ * @return value
+ *
+*******************************************************************************/
+uint32_t GLB_Get_SRAM_SLP(void)
+{
+    return BL_RD_REG(GLB_BASE, GLB_SRAM_SLP);
+}
+
+/****************************************************************************/ /**
+ * @brief  set sram_param value
+ *
+ * @param  value: value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value)
+{
+    BL_WR_REG(GLB_BASE, GLB_SRAM_PARM, value);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get sram_parm value
+ *
+ * @param  None
+ *
+ * @return value
+ *
+*******************************************************************************/
+uint32_t GLB_Get_SRAM_PARM(void)
+{
+    return BL_RD_REG(GLB_BASE, GLB_SRAM_PARM);
+}
+
+/****************************************************************************/ /**
+ * @brief  select EM type
+ *
+ * @param  emType: EM type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_EM_TYPE(emType));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, emType);
+    BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  select pin as EMAC or CAM
+ *
+ * @param  pinType: pin type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_Type pinType)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_EMAC_CAM_PIN_TYPE(pinType));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PIN_SEL_EMAC_CAM, pinType);
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  EXT_RST PAD SMT
+ *
+ * @param  enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Ext_Rst_Smt(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_EXT_RST_SMT);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EXT_RST_SMT);
+    }
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Key Scan Column Drive
+ *
+ * @param  enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Kys_Drv_Col(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_KYS_DRV_VAL);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_KYS_DRV_VAL);
+    }
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  swap UART gpio pins sig function
+ *
+ * @param  swapSel: UART swap set gpio pins selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_UART_Sig_Swap_Set(uint8_t swapSel)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((swapSel <= 0xF));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, swapSel);
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  swap JTAG gpio pins function
+ *
+ * @param  swapSel: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_JTAG_Sig_Swap_Set(uint8_t swapSel)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((swapSel <= 0xFF));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_JTAG_SWAP_SET, swapSel);
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  CCI use GPIO 0 1 2 7
+ *
+ * @param  enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_CCI_Use_IO_0_1_2_7(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_P3_CCI_USE_IO_0_2_7);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_P3_CCI_USE_IO_0_2_7);
+    }
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  CCI use JTAG pin
+ *
+ * @param  enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_CCI_Use_Jtag_Pin(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CCI_USE_JTAG_PIN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CCI_USE_JTAG_PIN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  swap SPI0 MOSI with MISO
+ *
+ * @param  newState: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Swap_SPI_0_MOSI_With_MISO(BL_Fun_Type newState)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_SWAP, newState);
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select SPI_0 act mode
+ *
+ * @param  mod: SPI work mode
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GLB_SPI_PAD_ACT_AS_TYPE(mod));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_MASTER_MODE, mod);
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  use internal flash
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_Select_Internal_Flash(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x3f);
+    BL_WR_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  use external flash
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_Select_External_Flash(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x00);
+    BL_WR_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Deswap internal flash pin
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_Deswap_Flash_Pin(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3);
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Swap internal flash CS and IO2 pin
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_Swap_Flash_CS_IO2_Pin(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2);
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Swap internal flash IO3 and IO0 pin
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_Swap_Flash_IO0_IO3_Pin(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3);
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Swap internal flash IO3 and IO0 pin
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_Swap_Flash_Pin(void)
+{
+    /*To be removed*/
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Select internal psram
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_Select_Internal_PSram(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x00);
+    BL_WR_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  set PDM clock
+ *
+ * @param  enable: Enable or disable PDM clock
+ * @param  div: clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_PDM_CLK(uint8_t enable, uint8_t div)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PDM_CLK_CTRL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_PDM0_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_PDM_CLK_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PDM_CLK_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PDM0_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_PDM_CLK_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PDM_CLK_CTRL);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PDM0_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_PDM0_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_PDM_CLK_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set MTimer clock
+ *
+ * @param  enable: enable or disable MTimer clock
+ * @param  clkSel: clock selection
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_MTimer_CLK(uint8_t enable, GLB_MTIMER_CLK_Type clkSel, uint32_t div)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GLB_MTIMER_CLK_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x1FFFF));
+
+    /* disable MTimer clock first */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CPU_RTC_EN);
+    BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CPU_RTC_SEL, clkSel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CPU_RTC_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CPU_RTC_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CPU_RTC_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set ADC clock
+ *
+ * @param  enable: enable or disable ADC clock
+ * @param  clkSel: ADC clock selection
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GLB_ADC_CLK_TYPE(clkSel));
+
+    /* disable ADC clock first */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);
+    BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV, div);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set DAC clock
+ *
+ * @param  enable: enable frequency divider or not
+ * @param  clkSel: ADC clock selection
+ * @param  div: src divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DAC_CLK(uint8_t enable, GLB_DAC_CLK_Type clkSel, uint8_t div)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GLB_DAC_CLK_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_COMP);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL, clkSel);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV, div);
+
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);
+    }
+
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  select DIG clock source
+ *
+ * @param  clkSel: DIG clock selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel)
+{
+    uint32_t tmpVal;
+    uint32_t dig512kEn;
+    uint32_t dig32kEn;
+
+    /* disable DIG512K and DIG32K clock first */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    dig512kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN);
+    dig32kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN);
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    /* repristinate DIG512K and DIG32K clock */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN, dig512kEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN, dig32kEn);
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set DIG 512K clock
+ *
+ * @param  enable: enable or disable DIG 512K clock
+ * @param  compensation: enable or disable DIG 512K clock compensation
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable, uint8_t compensation, uint8_t div)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    if (compensation) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_COMP);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_COMP);
+    }
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set DIG 32K clock
+ *
+ * @param  enable: enable or disable DIG 32K clock
+ * @param  compensation: enable or disable DIG 32K clock compensation
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensation, uint8_t div)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    if (compensation) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_COMP);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_COMP);
+    }
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set BT coex signal
+ *
+ * @param  enable: ENABLE or DISABLE, if enable, the AP JTAG will be replaced by BT Coex Signal
+ * @param  bandWidth: BT Bandwidth
+ * @param  pti: BT Packet Traffic Information
+ * @param  channel: BT Channel
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_BT_Coex_Signal(uint8_t enable, GLB_BT_BANDWIDTH_Type bandWidth, uint8_t pti, uint8_t channel)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_BT_BANDWIDTH_TYPE(bandWidth));
+    CHECK_PARAM((pti <= 0xF));
+    CHECK_PARAM((channel <= 78));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_COEX_BT_BW, bandWidth);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_COEX_BT_PTI, pti);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_COEX_BT_CHANNEL, channel);
+    BL_WR_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL);
+    if (enable) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EN_GPIO_BT_COEX, 1);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EN_GPIO_BT_COEX, 0);
+    }
+    BL_WR_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select UART signal function
+ *
+ * @param  sig: UART signal
+ * @param  fun: UART function
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun)
+{
+    uint32_t sig_pos = 0;
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_UART_SIG_TYPE(sig));
+    CHECK_PARAM(IS_GLB_UART_SIG_FUN_TYPE(fun));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_SIG_SEL_0);
+    sig_pos = (sig * 4);
+    /* Clear original val */
+    tmpVal &= (~(0xf << sig_pos));
+    /* Set new value */
+    tmpVal |= (fun << sig_pos);
+    BL_WR_REG(GLB_BASE, GLB_UART_SIG_SEL_0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  power off DLL
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_Off_DLL(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* GLB->dll.BF.ppu_dll = 0;   */
+    /* GLB->dll.BF.pu_dll = 0;    */
+    /* GLB->dll.BF.dll_reset = 1; */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PPU_DLL, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_DLL, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_RESET, 1);
+    BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  power on DLL
+ *
+ * @param  xtalType: DLL xtal type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_DLL(GLB_DLL_XTAL_Type xtalType)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_DLL_XTAL_TYPE(xtalType));
+
+    /* GLB->dll.BF.dll_refclk_sel = XXX; */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
+    switch (xtalType) {
+        case GLB_DLL_XTAL_NONE:
+            return ERROR;
+        case GLB_DLL_XTAL_32M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_REFCLK_SEL, 0);
+            break;
+        case GLB_DLL_XTAL_RC32M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_REFCLK_SEL, 1);
+            break;
+        default:
+            break;
+    }
+    BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);
+
+    /* GLB->dll.BF.dll_prechg_sel = 1;   */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_PRECHG_SEL, 1);
+    BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);
+
+    /* GLB->dll.BF.ppu_dll = 1;   */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PPU_DLL, 1);
+    BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);
+
+    BL702_Delay_US(2);
+
+    /* GLB->dll.BF.pu_dll = 1; */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_DLL, 1);
+    BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);
+
+    BL702_Delay_US(2);
+
+    /* GLB->dll.BF.dll_reset = 0; */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_RESET, 0);
+    BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);
+
+    /* delay for settling */
+    BL702_Delay_US(5);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  enable all DLL output clock
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Enable_DLL_All_Clks(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* GLB->dll.WORD = GLB->dll.WORD | 0x000000f8; include 288m and mmdiv */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_57P6M_EN, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_96M_EN, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_144M_EN, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_288M_EN, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_MMDIV_EN, 1);
+    BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  enable one of DLL output clock
+ *
+ * @param  dllClk: None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Enable_DLL_Clk(GLB_DLL_CLK_Type dllClk)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_DLL_CLK_TYPE(dllClk));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
+    switch (dllClk) {
+        case GLB_DLL_CLK_57P6M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_57P6M_EN, 1);
+            break;
+        case GLB_DLL_CLK_96M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_96M_EN, 1);
+            break;
+        case GLB_DLL_CLK_144M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_144M_EN, 1);
+            break;
+        case GLB_DLL_CLK_288M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_288M_EN, 1);
+            break;
+        case GLB_DLL_CLK_MMDIV:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_MMDIV_EN, 1);
+            break;
+        default:
+            break;
+    }
+    BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  disable all DLL output clock
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Disable_DLL_All_Clks(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* GLB->dll.WORD = GLB->dll.WORD & ~0x000000f8; */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_57P6M_EN, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_96M_EN, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_144M_EN, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_288M_EN, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_MMDIV_EN, 0);
+    BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  disable one of DLL output clock
+ *
+ * @param  dllClk: None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Disable_DLL_Clk(GLB_DLL_CLK_Type dllClk)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_DLL_CLK_TYPE(dllClk));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
+    switch (dllClk) {
+        case GLB_DLL_CLK_57P6M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_57P6M_EN, 0);
+            break;
+        case GLB_DLL_CLK_96M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_96M_EN, 0);
+            break;
+        case GLB_DLL_CLK_144M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_144M_EN, 0);
+            break;
+        case GLB_DLL_CLK_288M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_288M_EN, 0);
+            break;
+        case GLB_DLL_CLK_MMDIV:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_MMDIV_EN, 0);
+            break;
+        default:
+            break;
+    }
+    BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Select ir rx gpio (gpio17~gpio31)
+ *
+ * @param  gpio: IR gpio selected
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio)
+{
+    uint32_t tmpVal = 0;
+
+    /* Select gpio between gpio17 and gpio31 */
+    if (gpio > 16 && gpio < 32) {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_RX_GPIO_SEL, gpio - 16);
+        BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable ir led driver
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_IR_LED_Driver_Enable(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* Enable led driver */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_LEDDRV);
+    BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable ir led driver
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_IR_LED_Driver_Disable(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* Disable led driver */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LEDDRV);
+    BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable ir led driver gpio output(gpio 22 or 23)
+ *
+ * @param  gpio: IR gpio selected
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_IR_LED_Driver_Output_Enable(GLB_GPIO_Type gpio)
+{
+    uint32_t tmpVal = 0;
+
+    if (gpio == GLB_GPIO_PIN_22) {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN, BL_GET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN) | 1);
+        BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
+    } else if (gpio == GLB_GPIO_PIN_23) {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN, BL_GET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN) | 2);
+        BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable ir led driver gpio output(gpio 22 or 23)
+ *
+ * @param  gpio: IR gpio selected
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_IR_LED_Driver_Output_Disable(GLB_GPIO_Type gpio)
+{
+    uint32_t tmpVal = 0;
+
+    if (gpio == GLB_GPIO_PIN_22) {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN, BL_GET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN) & ~1);
+        BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
+    } else if (gpio == GLB_GPIO_PIN_23) {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN, BL_GET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN) & ~2);
+        BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set ir led driver ibias
+ *
+ * @param  ibias: Ibias value,0x0:0mA~0xf:120mA,8mA/step
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_IR_LED_Driver_Ibias(uint8_t ibias)
+{
+    uint32_t tmpVal = 0;
+
+    /* Set driver ibias */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_IBIAS, ibias & 0xF);
+    BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO initialization
+ *
+ * @param  cfg: GPIO configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg)
+{
+    uint8_t gpioPin = cfg->gpioPin;
+    uint8_t realPin;
+    uint32_t *pOut;
+    uint32_t pos;
+    uint32_t tmpOut;
+    uint32_t tmpVal;
+
+    /* drive strength(drive) = 0  <=>  8.0mA  @ 3.3V */
+    /* drive strength(drive) = 1  <=>  9.6mA  @ 3.3V */
+    /* drive strength(drive) = 2  <=>  11.2mA @ 3.3V */
+    /* drive strength(drive) = 3  <=>  12.8mA @ 3.3V */
+
+    pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + ((gpioPin >> 5) << 2));
+    pos = gpioPin % 32;
+    tmpOut = *pOut;
+
+    /* Disable output anyway*/
+    tmpOut &= (~(1 << pos));
+    *pOut = tmpOut;
+
+    realPin = gpioPin;
+    /* sf pad use exclusive ie/pd/pu/drive/smtctrl */
+    if (gpioPin >= 23 && gpioPin <= 28) {
+        if ((BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (gpioPin - 23))) > 0) {
+            realPin += 9;
+        }
+    }
+    tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + realPin / 2 * 4);
+    if (realPin % 2 == 0) {
+        if (cfg->gpioMode != GPIO_MODE_ANALOG) {
+            /* not analog mode */
+
+            /* Set input or output */
+            if (cfg->gpioMode == GPIO_MODE_OUTPUT) {
+                tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+                tmpOut |= (1 << pos);
+            } else {
+                tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+            }
+
+            /* Set pull up or down */
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
+            if (cfg->pullType == GPIO_PULL_UP) {
+                tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
+            } else if (cfg->pullType == GPIO_PULL_DOWN) {
+                tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
+            }
+        } else {
+            /* analog mode */
+
+            /* clear ie && oe */
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+            tmpOut &= ~(1 << pos);
+
+            /* clear pu && pd */
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
+        }
+
+        /* set drive && smt && func */
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_DRV, cfg->drive);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_SMT, cfg->smtCtrl);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL, cfg->gpioFun);
+    } else {
+        if (cfg->gpioMode != GPIO_MODE_ANALOG) {
+            /* not analog mode */
+
+            /* Set input or output */
+            if (cfg->gpioMode == GPIO_MODE_OUTPUT) {
+                tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
+                tmpOut |= (1 << pos);
+            } else {
+                tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
+            }
+
+            /* Set pull up or down */
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD);
+            if (cfg->pullType == GPIO_PULL_UP) {
+                tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU);
+            } else if (cfg->pullType == GPIO_PULL_DOWN) {
+                tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD);
+            }
+        } else {
+            /* analog mode */
+
+            /* clear ie && oe */
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
+            tmpOut &= ~(1 << pos);
+
+            /* clear pu && pd */
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD);
+        }
+
+        /* set drive && smt && func */
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_DRV, cfg->drive);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_SMT, cfg->smtCtrl);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_FUNC_SEL, cfg->gpioFun);
+    }
+    BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + realPin / 2 * 4, tmpVal);
+
+    *pOut = tmpOut;
+
+    /* always on pads IE control (in HBN) */
+    if (gpioPin >= 9 && gpioPin <= 13) {
+        tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+        uint32_t aonPadIeSmt = BL_GET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT);
+
+        if (cfg->gpioMode != GPIO_MODE_ANALOG) {
+            /* not analog mode */
+
+            if (cfg->gpioMode == GPIO_MODE_OUTPUT) {
+                aonPadIeSmt &= ~(1 << (gpioPin - 9));
+            } else {
+                aonPadIeSmt |= (1 << (gpioPin - 9));
+            }
+        } else {
+            /* analog mode */
+
+            /* clear aon pad ie */
+            aonPadIeSmt &= ~(1 << (gpioPin - 9));
+        }
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aonPadIeSmt);
+        BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+    }
+
+    if (gpioPin >= 23 && gpioPin <= 28) {
+        if ((BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (gpioPin - 23))) > 0) {
+            tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4);
+            if (gpioPin % 2 == 0) {
+                tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL, cfg->gpioFun);
+            } else {
+                tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_FUNC_SEL, cfg->gpioFun);
+            }
+            BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal);
+
+            /* sf pad use GPIO23-GPIO28 pinmux&&outputEn */
+            pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + ((gpioPin >> 5) << 2));
+            pos = gpioPin % 32;
+            tmpOut = *pOut;
+            /* Disable output anyway*/
+            tmpOut &= (~(1 << pos));
+            *pOut = tmpOut;
+            if (cfg->gpioMode != GPIO_MODE_ANALOG) {
+                /* not analog mode */
+
+                if (cfg->gpioMode == GPIO_MODE_OUTPUT) {
+                    tmpOut |= (1 << pos);
+                }
+            }
+            *pOut = tmpOut;
+        }
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  init GPIO function in pin list
+ *
+ * @param  gpioFun: GPIO pin function
+ * @param  pinList: GPIO pin list
+ * @param  cnt: GPIO pin count
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt)
+{
+    GLB_GPIO_Cfg_Type gpioCfg = {
+        .gpioPin = GLB_GPIO_PIN_0,
+        .gpioFun = (uint8_t)gpioFun,
+        .gpioMode = GPIO_MODE_AF,
+        .pullType = GPIO_PULL_UP,
+        .drive = 3,
+        .smtCtrl = 1
+    };
+
+    if (gpioFun == GPIO_FUN_ANALOG) {
+        gpioCfg.gpioMode = GPIO_MODE_ANALOG;
+    }
+
+    for (uint8_t i = 0; i < cnt; i++) {
+        gpioCfg.gpioPin = pinList[i];
+        GLB_GPIO_Init(&gpioCfg);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO set input function enable
+ *
+ * @param  gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_INPUT_Enable(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+    uint32_t pinOffset;
+    uint32_t aonPadIeSmt;
+
+    pinOffset = (gpioPin >> 1) << 2;
+    tmpVal = *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset);
+    if (gpioPin % 2 == 0) {
+        /* [0] is ie */
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+    } else {
+        /* [16] is ie */
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
+    }
+    *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset) = tmpVal;
+
+    /* always on pads IE control (in HBN) */
+    if (gpioPin >= 9 && gpioPin <= 13) {
+        tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+        aonPadIeSmt = BL_GET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT);
+        aonPadIeSmt |= (1 << (gpioPin - 9));
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aonPadIeSmt);
+        BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO set input function disable
+ *
+ * @param  gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+    uint32_t pinOffset;
+    uint32_t aonPadIeSmt;
+
+    pinOffset = (gpioPin >> 1) << 2;
+    tmpVal = *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset);
+    if (gpioPin % 2 == 0) {
+        /* [0] is ie */
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+    } else {
+        /* [16] is ie */
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
+    }
+    *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset) = tmpVal;
+
+    /* always on pads IE control (in HBN) */
+    if (gpioPin >= 9 && gpioPin <= 13) {
+        tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+        aonPadIeSmt = BL_GET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT);
+        aonPadIeSmt &= ~(1 << (gpioPin - 9));
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aonPadIeSmt);
+        BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO set output function enable
+ *
+ * @param  gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFGCTL34);
+    tmpVal = tmpVal | (1 << gpioPin);
+    BL_WR_REG(GLB_BASE, GLB_GPIO_CFGCTL34, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO set output function disable
+ *
+ * @param  gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFGCTL34);
+    tmpVal = tmpVal & ~(1 << gpioPin);
+    BL_WR_REG(GLB_BASE, GLB_GPIO_CFGCTL34, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO set High-Z
+ *
+ * @param  gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin)
+{
+    uint32_t *pOut;
+    uint32_t pos;
+    uint32_t tmpOut;
+    uint32_t tmpVal;
+    uint32_t aonPadIeSmt;
+    uint8_t realPin;
+
+    /* always on pads IE control (in HBN) */
+    if (gpioPin >= 9 && gpioPin <= 13) {
+        tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+        aonPadIeSmt = BL_GET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT);
+        aonPadIeSmt &= ~(1 << (gpioPin - 9));
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aonPadIeSmt);
+        BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+    }
+
+    realPin = gpioPin;
+    /* sf pad use exclusive ie/pd/pu/drive/smtctrl */
+    if (gpioPin >= 23 && gpioPin <= 28) {
+        if ((BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (gpioPin - 23))) > 0) {
+            realPin += 9;
+        }
+    }
+    tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + realPin / 2 * 4);
+
+    /* pu=0, pd=0, ie=0 */
+    if (realPin % 2 == 0) {
+        tmpVal = (tmpVal & 0xffffff00);
+    } else {
+        tmpVal = (tmpVal & 0xff00ffff);
+    }
+
+    BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + realPin / 2 * 4, tmpVal);
+
+    pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + ((gpioPin >> 5) << 2));
+    pos = gpioPin % 32;
+    tmpOut = *pOut;
+
+    /* Disable output anyway*/
+    tmpOut &= (~(1 << pos));
+    *pOut = tmpOut;
+
+    tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4);
+
+    /* func_sel=swgpio */
+    if (gpioPin % 2 == 0) {
+        tmpVal = (tmpVal & 0xffff00ff);
+        tmpVal |= 0x0B00;
+    } else {
+        tmpVal = (tmpVal & 0x00ffffff);
+        tmpVal |= (0x0B00 << 16);
+    }
+
+    BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal);
+
+    /* Disable output anyway*/
+    *pOut = tmpOut;
+
+    return SUCCESS;
+}
+
+BL_Err_Type ATTR_TCM_SECTION GLB_Set_Flash_Pad_HZ(void)
+{
+    uint32_t tmpVal;
+    uint32_t offset;
+
+    if (BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) != 0x00) {
+        return ERROR;
+    }
+
+    for (offset = 23; offset <= 28; offset++) {
+        tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4);
+        /* pu=0, pd=0, ie=0 */
+        if (offset % 2 == 0) {
+            tmpVal = (tmpVal & 0xffffff00);
+        } else {
+            tmpVal = (tmpVal & 0xff00ffff);
+        }
+        BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4, tmpVal);
+
+        tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4);
+        /* func_sel=swgpio */
+        if (offset % 2 == 0) {
+            tmpVal = (tmpVal & 0xffff00ff);
+            tmpVal |= 0x0B00;
+        } else {
+            tmpVal = (tmpVal & 0x00ffffff);
+            tmpVal |= (0x0B00 << 16);
+        }
+        BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4, tmpVal);
+    }
+
+    tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET);
+    tmpVal &= 0xE07FFFFF;
+    BL_WR_WORD(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET, tmpVal);
+
+    return SUCCESS;
+}
+
+BL_Err_Type ATTR_TCM_SECTION GLB_Set_Psram_Pad_HZ(void)
+{
+    uint32_t tmpVal;
+    uint32_t offset;
+
+    if (BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) != 0x3F) {
+        return ERROR;
+    }
+
+    for (offset = 32; offset <= 37; offset++) {
+        tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4);
+        /* pu=0, pd=0, ie=0 */
+        if (offset % 2 == 0) {
+            tmpVal = (tmpVal & 0xffffff00);
+        } else {
+            tmpVal = (tmpVal & 0xff00ffff);
+        }
+        BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4, tmpVal);
+
+        tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + (offset - 9) / 2 * 4);
+        /* func_sel=swgpio */
+        if ((offset - 9) % 2 == 0) {
+            tmpVal = (tmpVal & 0xffff00ff);
+            tmpVal |= 0x0B00;
+        } else {
+            tmpVal = (tmpVal & 0x00ffffff);
+            tmpVal |= (0x0B00 << 16);
+        }
+        BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + (offset - 9) / 2 * 4, tmpVal);
+    }
+
+    tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET);
+    tmpVal &= 0xE07FFFFF;
+    BL_WR_WORD(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get GPIO function
+ *
+ * @param  gpioPin: GPIO type
+ *
+ * @return GPIO function
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+uint8_t ATTR_TCM_SECTION GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4);
+
+    if (gpioPin % 2 == 0) {
+        return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL);
+    } else {
+        return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_FUNC_SEL);
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Write GPIO
+ *
+ * @param  gpioPin: GPIO type
+ * @param  val: GPIO value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val)
+{
+    uint32_t *pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_OFFSET + ((gpioPin >> 5) << 2));
+    uint32_t pos = gpioPin % 32;
+    uint32_t tmpOut;
+
+    tmpOut = *pOut;
+    if (val > 0) {
+        tmpOut |= (1 << pos);
+    } else {
+        tmpOut &= (~(1 << pos));
+    }
+    *pOut = tmpOut;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Read GPIO
+ *
+ * @param  gpioPin: GPIO type
+ *
+ * @return GPIO value
+ *
+*******************************************************************************/
+uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin)
+{
+    uint32_t *p = (uint32_t *)(GLB_BASE + GLB_GPIO_INPUT_OFFSET + ((gpioPin >> 5) << 2));
+    uint32_t pos = gpioPin % 32;
+
+    if ((*p) & (1 << pos)) {
+        return 1;
+    } else {
+        return 0;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Set GLB GPIO interrupt mask
+ *
+ * @param  gpioPin: GPIO type
+ * @param  intMask: GPIO interrupt MASK or UNMASK
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask)
+{
+    uint32_t tmpVal;
+
+    if (gpioPin < 32) {
+        /* GPIO0 ~ GPIO31 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MASK1);
+        if (intMask == MASK) {
+            tmpVal = tmpVal | (1 << gpioPin);
+        } else {
+            tmpVal = tmpVal & ~(1 << gpioPin);
+        }
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MASK1, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set GLB GPIO interrupt mask
+ *
+ * @param  gpioPin: GPIO type
+ * @param  intClear: GPIO interrupt clear or unclear
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_IntClear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear)
+{
+    uint32_t tmpVal;
+
+    if (gpioPin < 32) {
+        /* GPIO0 ~ GPIO31 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_CLR1);
+        if (intClear == SET) {
+            tmpVal = tmpVal | (1 << gpioPin);
+        } else {
+            tmpVal = tmpVal & ~(1 << gpioPin);
+        }
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT_CLR1, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get GLB GPIO interrrupt status
+ *
+ * @param  gpioPin: GPIO type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal = 0;
+
+    if (gpioPin < 32) {
+        /* GPIO0 ~ GPIO31 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_STAT1);
+    }
+
+    return (tmpVal & (1 << gpioPin)) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set GLB GPIO interrupt mode
+ *
+ * @param  gpioPin: GPIO type
+ * @param  intCtlMod: GPIO interrupt control mode
+ * @param  intTrgMod: GPIO interrupt trigger mode
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_GPIO_IntMod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod, GLB_GPIO_INT_TRIG_Type intTrgMod)
+{
+    uint32_t tmpVal;
+    uint32_t tmpGpioPin;
+
+    CHECK_PARAM(IS_GLB_GPIO_INT_CONTROL_TYPE(intCtlMod));
+    CHECK_PARAM(IS_GLB_GPIO_INT_TRIG_TYPE(intTrgMod));
+
+    if (gpioPin < GLB_GPIO_PIN_10) {
+        /* GPIO0 ~ GPIO9 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1);
+        tmpGpioPin = gpioPin;
+        tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1, tmpVal);
+    } else if (gpioPin < GLB_GPIO_PIN_20) {
+        /* GPIO10 ~ GPIO19 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2);
+        tmpGpioPin = gpioPin - GLB_GPIO_PIN_10;
+        tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2, tmpVal);
+    } else if (gpioPin < GLB_GPIO_PIN_30) {
+        /* GPIO20 ~ GPIO29 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3);
+        tmpGpioPin = gpioPin - GLB_GPIO_PIN_20;
+        tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3, tmpVal);
+    } else {
+        /* GPIO30 ~ GPIO31 not recommend */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET4);
+        tmpGpioPin = gpioPin - GLB_GPIO_PIN_30;
+        tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET4, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get GPIO interrupt control mode
+ *
+ * @param  gpioPin: GPIO pin type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_IntCtlMod(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+    uint32_t bitVal;
+
+    if (gpioPin < GLB_GPIO_PIN_10) {
+        /* GPIO0 - GPIO9 */
+        bitVal = gpioPin - 0;
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1);
+        tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
+        return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
+    } else if ((gpioPin > GLB_GPIO_PIN_9) && (gpioPin < GLB_GPIO_PIN_20)) {
+        /* GPIO10 - GPIO19 */
+        bitVal = gpioPin - 10;
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2);
+        tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
+        return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
+    } else if ((gpioPin > GLB_GPIO_PIN_19) && (gpioPin < GLB_GPIO_PIN_30)) {
+        /* GPIO20 - GPIO29 */
+        bitVal = gpioPin - 20;
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3);
+        tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
+        return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
+    } else {
+        /* GPIO30 ~ GPIO31 not recommend */
+        bitVal = gpioPin - 30;
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET4);
+        tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
+        return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Set GLB GPIO interrupt mask 2
+ *
+ * @param  gpioPin: GPIO type
+ * @param  intMask: GPIO interrupt MASK or UNMASK
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Int2Mask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask)
+{
+    uint32_t tmpVal;
+
+    if (gpioPin < 32) {
+        /* GPIO0 ~ GPIO31 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MASK1);
+        if (intMask == MASK) {
+            tmpVal = tmpVal | (1 << gpioPin);
+        } else {
+            tmpVal = tmpVal & ~(1 << gpioPin);
+        }
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_MASK1, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set GLB GPIO interrupt mask 2
+ *
+ * @param  gpioPin: GPIO type
+ * @param  intClear: GPIO interrupt clear or unclear
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Int2Clear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear)
+{
+    uint32_t tmpVal;
+
+    if (gpioPin < 32) {
+        /* GPIO0 ~ GPIO31 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_CLR1);
+        if (intClear == SET) {
+            tmpVal = tmpVal | (1 << gpioPin);
+        } else {
+            tmpVal = tmpVal & ~(1 << gpioPin);
+        }
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_CLR1, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get GLB GPIO interrrupt status 2
+ *
+ * @param  gpioPin: GPIO type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type GLB_Get_GPIO_Int2Status(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal = 0;
+
+    if (gpioPin < 32) {
+        /* GPIO0 ~ GPIO31 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_STAT1);
+    }
+
+    return (tmpVal & (1 << gpioPin)) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set GLB GPIO interrupt mode 2
+ *
+ * @param  gpioPin: GPIO type
+ * @param  intCtlMod: GPIO interrupt control mode
+ * @param  intTrgMod: GPIO interrupt trigger mode
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_GPIO_Int2Mod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod, GLB_GPIO_INT_TRIG_Type intTrgMod)
+{
+    uint32_t tmpVal;
+    uint32_t tmpGpioPin;
+
+    CHECK_PARAM(IS_GLB_GPIO_INT_CONTROL_TYPE(intCtlMod));
+    CHECK_PARAM(IS_GLB_GPIO_INT_TRIG_TYPE(intTrgMod));
+
+    if (gpioPin < GLB_GPIO_PIN_10) {
+        /* GPIO0 ~ GPIO9 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET1);
+        tmpGpioPin = gpioPin;
+        tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET1, tmpVal);
+    } else if (gpioPin < GLB_GPIO_PIN_20) {
+        /* GPIO10 ~ GPIO19 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET2);
+        tmpGpioPin = gpioPin - GLB_GPIO_PIN_10;
+        tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET2, tmpVal);
+    } else if (gpioPin < GLB_GPIO_PIN_30) {
+        /* GPIO20 ~ GPIO29 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET3);
+        tmpGpioPin = gpioPin - GLB_GPIO_PIN_20;
+        tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET3, tmpVal);
+    } else {
+        /* GPIO30 ~ GPIO31 not recommend */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET4);
+        tmpGpioPin = gpioPin - GLB_GPIO_PIN_30;
+        tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET4, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get GPIO interrupt control mode 2
+ *
+ * @param  gpioPin: GPIO pin type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_Int2CtlMod(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+    uint32_t bitVal;
+
+    if (gpioPin < GLB_GPIO_PIN_10) {
+        /* GPIO0 - GPIO9 */
+        bitVal = gpioPin - 0;
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET1);
+        tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
+        return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
+    } else if ((gpioPin > GLB_GPIO_PIN_9) && (gpioPin < GLB_GPIO_PIN_20)) {
+        /* GPIO10 - GPIO19 */
+        bitVal = gpioPin - 10;
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET2);
+        tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
+        return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
+    } else if ((gpioPin > GLB_GPIO_PIN_19) && (gpioPin < GLB_GPIO_PIN_30)) {
+        /* GPIO20 - GPIO29 */
+        bitVal = gpioPin - 20;
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET3);
+        tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
+        return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
+    } else {
+        /* GPIO30 ~ GPIO31 not recommend */
+        bitVal = gpioPin - 30;
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET4);
+        tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
+        return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO INT0 IRQHandler install
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void)
+{
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO_INT0_IRQHandler);
+#endif
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO interrupt IRQ handler callback install
+ *
+ * @param  gpioPin: GPIO pin type
+ * @param  cbFun: callback function
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun)
+{
+    if (gpioPin < 32) {
+        glbGpioInt0CbfArra[gpioPin] = cbFun;
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO interrupt IRQ handler callback install2
+ *
+ * @param  gpioPin: GPIO pin type
+ * @param  cbFun: callback function
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_INT0_Callback_Install2(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun)
+{
+    if (gpioPin < 32) {
+        glbGpioInt0CbfArra2[gpioPin] = cbFun;
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO interrupt IRQ handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void GPIO_INT0_IRQHandler(void)
+{
+    GLB_GPIO_Type gpioPin;
+    uint32_t timeOut = 0;
+
+    for (gpioPin = GLB_GPIO_PIN_0; gpioPin <= GLB_GPIO_PIN_31; gpioPin++) {
+        if (SET == GLB_Get_GPIO_IntStatus(gpioPin)) {
+            GLB_GPIO_IntClear(gpioPin, SET);
+
+            /* timeout check */
+            timeOut = GLB_GPIO_INT0_CLEAR_TIMEOUT;
+            do {
+                timeOut--;
+            } while ((SET == GLB_Get_GPIO_IntStatus(gpioPin)) && timeOut);
+            if (!timeOut) {
+                //MSG("WARNING: Clear GPIO interrupt status fail.\r\n");
+            }
+
+            /* if timeOut==0, GPIO interrupt status not cleared */
+            GLB_GPIO_IntClear(gpioPin, RESET);
+
+            if (glbGpioInt0CbfArra[gpioPin] != NULL) {
+                /* Call the callback function */
+                glbGpioInt0CbfArra[gpioPin]();
+            }
+        }
+        if (SET == GLB_Get_GPIO_Int2Status(gpioPin)) {
+            GLB_GPIO_Int2Clear(gpioPin, SET);
+
+            /* timeout check */
+            timeOut = GLB_GPIO_INT0_CLEAR_TIMEOUT;
+            do {
+                timeOut--;
+            } while ((SET == GLB_Get_GPIO_Int2Status(gpioPin)) && timeOut);
+            if (!timeOut) {
+                //MSG("WARNING: Clear GPIO interrupt status fail.\r\n");
+            }
+
+            /* if timeOut==0, GPIO interrupt status not cleared */
+            GLB_GPIO_Int2Clear(gpioPin, RESET);
+
+            if (glbGpioInt0CbfArra2[gpioPin] != NULL) {
+                /* Call the callback function */
+                glbGpioInt0CbfArra2[gpioPin]();
+            }
+        }
+    }
+}
+#endif
+
+/*@} end of group GLB_Public_Functions */
+
+/*@} end of group GLB */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_hbn.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_hbn.c
new file mode 100644
index 00000000..9ddf2f9b
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_hbn.c
@@ -0,0 +1,2030 @@
+/**
+  ******************************************************************************
+  * @file    bl702_hbn.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_hbn.h"
+#include "bl702_glb.h"
+#include "bl702_xip_sflash.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  HBN
+ *  @{
+ */
+
+/** @defgroup  HBN_Private_Macros
+ *  @{
+ */
+#define HBN_CLK_SET_DUMMY_WAIT \
+    {                          \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+    }
+
+/*@} end of group HBN_Private_Macros */
+
+/** @defgroup  HBN_Private_Types
+ *  @{
+ */
+
+/*@} end of group HBN_Private_Types */
+
+/** @defgroup  HBN_Private_Variables
+ *  @{
+ */
+static intCallback_Type *hbnInt0CbfArra[HBN_OUT0_MAX] = { NULL, NULL, NULL, NULL, NULL, NULL };
+static intCallback_Type *hbnInt1CbfArra[HBN_OUT1_MAX] = { NULL, NULL, NULL, NULL };
+
+/*@} end of group HBN_Private_Variables */
+
+/** @defgroup  HBN_Global_Variables
+ *  @{
+ */
+
+/*@} end of group HBN_Global_Variables */
+
+/** @defgroup  HBN_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group HBN_Private_Fun_Declaration */
+
+/** @defgroup  HBN_Private_Functions
+ *  @{
+ */
+
+/*@} end of group HBN_Private_Functions */
+
+/** @defgroup  HBN_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Enter HBN
+ *
+ * @param  cfg: HBN APP Config
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION HBN_Mode_Enter(HBN_APP_CFG_Type *cfg)
+{
+    uint32_t valLow = 0, valHigh = 0;
+    uint64_t val;
+
+    /* work clock select */
+    if (cfg->useXtal32k) {
+        HBN_32K_Sel(HBN_32K_XTAL);
+    } else {
+        HBN_32K_Sel(HBN_32K_RC);
+        HBN_Power_Off_Xtal_32K();
+    }
+
+    /* turn off RC32K during HBN */
+    if ((cfg->hbnLevel) >= HBN_LEVEL_2) {
+        HBN_Power_Off_RC32K();
+    } else {
+        HBN_Power_On_RC32K();
+    }
+
+    /* clear aon pad interrupt before config them */
+    HBN_Clear_IRQ(HBN_INT_GPIO9);
+    HBN_Clear_IRQ(HBN_INT_GPIO10);
+    HBN_Clear_IRQ(HBN_INT_GPIO11);
+    HBN_Clear_IRQ(HBN_INT_GPIO12);
+    HBN_Clear_IRQ(HBN_INT_GPIO13);
+
+    /* always disable HBN pin pull up/down to reduce PDS/HBN current, 0x4000F014[16]=0 */
+    HBN_Hw_Pu_Pd_Cfg(DISABLE);
+
+    HBN_Pin_WakeUp_Mask(~(cfg->gpioWakeupSrc));
+
+    if (cfg->gpioWakeupSrc != 0) {
+        HBN_Aon_Pad_IeSmt_Cfg(cfg->gpioWakeupSrc);
+        HBN_GPIO_INT_Enable(cfg->gpioTrigType);
+    } else {
+        HBN_Aon_Pad_IeSmt_Cfg(0);
+    }
+
+    /* HBN RTC config and enable */
+    if (cfg->sleepTime != 0) {
+        // set rtc enable flag
+        BL_WR_WORD(0x40010FFC, 0x1);
+
+        HBN_Clear_RTC_Counter();
+        HBN_Get_RTC_Timer_Val(&valLow, &valHigh);
+        val = valLow + ((uint64_t)valHigh << 32);
+        val += cfg->sleepTime;
+        HBN_Set_RTC_Timer(HBN_RTC_INT_DELAY_0T, val & 0xffffffff, val >> 32, HBN_RTC_COMP_BIT0_39);
+        HBN_Enable_RTC_Counter();
+    }
+
+    HBN_Power_Down_Flash(cfg->flashCfg);
+
+    switch (cfg->flashPinCfg) {
+        case 0:
+            HBN_Set_Pad_23_28_Pullup();
+            break;
+
+        case 1:
+            /* need do nothing */
+            break;
+
+        case 2:
+            /* need do nothing */
+            break;
+
+        case 3:
+            /* can do nothing */
+            break;
+
+        default:
+            break;
+    }
+
+    GLB_Set_System_CLK(GLB_DLL_XTAL_NONE, GLB_SYS_CLK_RC32M);
+
+    /* power off xtal */
+    AON_Power_Off_XTAL();
+
+    HBN_Enable_Ext(cfg->gpioWakeupSrc, cfg->ldoLevel, cfg->hbnLevel);
+}
+
+/****************************************************************************/ /**
+ * @brief  power down and switch clock
+ *
+ * @param  flashCfg: None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg)
+{
+    SPI_Flash_Cfg_Type bhFlashCfg;
+
+    if (flashCfg == NULL) {
+        /* fix this some time */
+        /* SFlash_Cache_Flush(); */
+        XIP_SFlash_Read_Via_Cache_Need_Lock(BL702_FLASH_XIP_BASE + 8 + 4, (uint8_t *)(&bhFlashCfg), sizeof(SPI_Flash_Cfg_Type));
+        /* fix this some time */
+        /* SFlash_Cache_Flush(); */
+
+        SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
+        SFlash_Reset_Continue_Read(&bhFlashCfg);
+    } else {
+        SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
+        SFlash_Reset_Continue_Read(flashCfg);
+    }
+
+    SFlash_Powerdown();
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable HBN mode
+ *
+ * @param  aGPIOIeCfg: AON GPIO IE config,Bit0->GPIO18. Bit(s) of Wakeup GPIO(s) must not be set to
+ *                     0(s),say when use GPIO7 as wake up pin,aGPIOIeCfg should be 0x01.
+ * @param  ldoLevel: LDO volatge level
+ * @param  hbnLevel: HBN work level
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION HBN_Enable_Ext(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+    CHECK_PARAM(IS_HBN_LEVEL_TYPE(hbnLevel));
+
+    /* Setting from guide */
+    /* RAM Retion, no longer use */
+    /* BL_WR_REG(HBN_BASE,HBN_SRAM,0x24); */
+
+    /* AON GPIO IE */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aGPIOIeCfg);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    /* HBN mode LDO level */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_AON_VOUT_SEL, ldoLevel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_RT_VOUT_SEL, ldoLevel);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    /* Select RC32M */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+
+    /* Set HBN flag */
+    BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG);
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+
+    /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */
+    switch (hbnLevel) {
+        case HBN_LEVEL_0:
+            tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+            break;
+
+        case HBN_LEVEL_1:
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+            break;
+
+        case HBN_LEVEL_2:
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+            break;
+
+        case HBN_LEVEL_3:
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+            break;
+
+        default:
+            break;
+    }
+
+    /* Set power on option:0 for por reset twice for robust 1 for reset only once*/
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    /* Enable HBN mode */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    while (1) {
+        BL702_Delay_MS(1000);
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Reset HBN mode
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION HBN_Reset(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Reset HBN mode */
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_SW_RST);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  reset HBN by software
+ *
+ * @param  npXtalType: NP clock type
+ * @param  bclkDiv: NP clock div
+ * @param  apXtalType: AP clock type
+ * @param  fclkDiv: AP clock div
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_App_Reset(uint8_t npXtalType, uint8_t bclkDiv, uint8_t apXtalType, uint8_t fclkDiv)
+{
+    uint32_t tmp[12];
+
+    tmp[0] = BL_RD_REG(HBN_BASE, HBN_CTL);
+    tmp[1] = BL_RD_REG(HBN_BASE, HBN_TIME_L);
+    tmp[2] = BL_RD_REG(HBN_BASE, HBN_TIME_H);
+    tmp[3] = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmp[4] = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);
+    tmp[5] = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+    tmp[6] = BL_RD_REG(HBN_BASE, HBN_PIR_VTH);
+    tmp[7] = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL);
+    tmp[8] = BL_RD_REG(HBN_BASE, HBN_SRAM);
+    tmp[9] = BL_RD_REG(HBN_BASE, HBN_RSV0);
+    tmp[10] = BL_RD_REG(HBN_BASE, HBN_RSV1);
+    tmp[11] = BL_RD_REG(HBN_BASE, HBN_RSV2);
+    /* DO HBN reset */
+    HBN_Reset();
+    /* HBN need 3 32k cyclce to recovery */
+    BL702_Delay_US(100);
+    /* Recover HBN value */
+    BL_WR_REG(HBN_BASE, HBN_TIME_L, tmp[1]);
+    BL_WR_REG(HBN_BASE, HBN_TIME_H, tmp[2]);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmp[0]);
+
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmp[3]);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmp[4]);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmp[5]);
+    BL_WR_REG(HBN_BASE, HBN_PIR_VTH, tmp[6]);
+    BL_WR_REG(HBN_BASE, HBN_PIR_INTERVAL, tmp[7]);
+    BL_WR_REG(HBN_BASE, HBN_SRAM, tmp[8]);
+    BL_WR_REG(HBN_BASE, HBN_RSV0, tmp[9]);
+    BL_WR_REG(HBN_BASE, HBN_RSV1, tmp[10]);
+    BL_WR_REG(HBN_BASE, HBN_RSV2, tmp[11]);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable HBN mode
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Disable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Disable HBN mode */
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_MODE);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable HBN PIR
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_Enable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PIR_EN);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable HBN PIR
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_Disable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PIR_EN);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Config HBN PIR interrupt
+ *
+ * @param  pirIntCfg: HBN PIR interrupt configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type *pirIntCfg)
+{
+    uint32_t tmpVal;
+    uint32_t bit4 = 0;
+    uint32_t bit5 = 0;
+    uint32_t bitVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+
+    /* low trigger interrupt */
+    if (pirIntCfg->lowIntEn == ENABLE) {
+        bit5 = 0;
+    } else {
+        bit5 = 1;
+    }
+
+    /* high trigger interrupt */
+    if (pirIntCfg->highIntEn == ENABLE) {
+        bit4 = 0;
+    } else {
+        bit4 = 1;
+    }
+
+    bitVal = bit4 | (bit5 << 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_DIS, bitVal);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select HBN PIR low pass filter
+ *
+ * @param  lpf: HBN PIR low pass filter selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_PIR_LPF_TYPE(lpf));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_LPF_SEL, lpf);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select HBN PIR high pass filter
+ *
+ * @param  hpf: HBN PIR high pass filter selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_PIR_HPF_TYPE(hpf));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_HPF_SEL, hpf);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set HBN PIR threshold value
+ *
+ * @param  threshold: HBN PIR threshold value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM((threshold <= 0x3FFF));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_VTH);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH, threshold);
+    BL_WR_REG(HBN_BASE, HBN_PIR_VTH, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get HBN PIR threshold value
+ *
+ * @param  None
+ *
+ * @return HBN PIR threshold value
+ *
+*******************************************************************************/
+uint16_t HBN_Get_PIR_Threshold(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_VTH);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH);
+}
+
+/****************************************************************************/ /**
+ * @brief  Set HBN PIR interval value
+ *
+ * @param  interval: HBN PIR interval value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM((interval <= 0xFFF));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL, interval);
+    BL_WR_REG(HBN_BASE, HBN_PIR_INTERVAL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get HBN PIR interval value
+ *
+ * @param  None
+ *
+ * @return HBN PIR interval value
+ *
+*******************************************************************************/
+uint16_t HBN_Get_PIR_Interval(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL);
+}
+
+/****************************************************************************/ /**
+ * @brief  get HBN bor out state
+ *
+ * @param  None
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type HBN_Get_BOR_OUT_State(void)
+{
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_MISC), HBN_R_BOR_OUT) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  set HBN bor config
+ *
+ * @param  enable: ENABLE or DISABLE, if enable, Power up Brown Out Reset
+ * @param  threshold: bor threshold
+ * @param  mode: bor work mode with por
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_BOR_Config(uint8_t enable, HBN_BOR_THRES_Type threshold, HBN_BOR_MODE_Type mode)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_BOR_THRES_TYPE(threshold));
+    CHECK_PARAM(IS_HBN_BOR_MODE_TYPE(mode));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC);
+
+    if (enable) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PU_BOR, 1);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PU_BOR, 0);
+    }
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_VTH, threshold);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_SEL, mode);
+    BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN set ldo11aon voltage out
+ *
+ * @param  ldoLevel: LDO volatge level
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN set ldo11rt voltage out
+ *
+ * @param  ldoLevel: LDO volatge level
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_RT_VOUT_SEL, ldoLevel);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN set ldo11soc voltage out
+ *
+ * @param  ldoLevel: LDO volatge level
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11SOC_VOUT_SEL_AON, ldoLevel);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN set ldo11 all voltage out
+ *
+ * @param  ldoLevel: LDO volatge level
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_RT_VOUT_SEL, ldoLevel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11SOC_VOUT_SEL_AON, ldoLevel);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN set ldo11rt drive strength
+ *
+ * @param  strength: ldo11rt drive strength
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11rt_Drive_Strength(HBN_LDO11RT_DRIVE_STRENGTH_Type strength)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO11RT_DRIVE_STRENGTH_TYPE(strength));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_RT_ILOAD_SEL, strength);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN select 32K
+ *
+ * @param  clkType: HBN 32k clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_32K_Sel(HBN_32K_CLK_Type clkType)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_HBN_32K_CLK_TYPE(clkType));
+
+    HBN_Trim_RC32K();
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL, clkType);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select uart clock source
+ *
+ * @param  clkSel: uart clock type selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL, clkSel);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select xclk clock source
+ *
+ * @param  xClk: xclk clock type selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_Type xClk)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_HBN_XCLK_CLK_TYPE(xClk));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);
+
+    switch (xClk) {
+        case HBN_XCLK_CLK_RC32M:
+            tmpVal2 &= (~(1 << 0));
+            break;
+
+        case HBN_XCLK_CLK_XTAL:
+            tmpVal2 |= (1 << 0);
+            break;
+
+        default:
+            break;
+    }
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, tmpVal2);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+    HBN_CLK_SET_DUMMY_WAIT;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select root clk source
+ *
+ * @param  rootClk: root clock type selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_HBN_ROOT_CLK_TYPE(rootClk));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);
+
+    switch (rootClk) {
+        case HBN_ROOT_CLK_RC32M:
+            tmpVal2 = 0x0;
+            break;
+
+        case HBN_ROOT_CLK_XTAL:
+            tmpVal2 = 0x1;
+            break;
+
+        case HBN_ROOT_CLK_DLL:
+            tmpVal2 |= (1 << 1);
+            break;
+
+        default:
+            break;
+    }
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, tmpVal2);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+    HBN_CLK_SET_DUMMY_WAIT;
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  set HBN_RAM sleep mode
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_HRAM_slp(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_SLP);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_RET);
+    BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set HBN_RAM retension mode
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_HRAM_Ret(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_SLP);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_RET);
+    BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power on XTAL 32K
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_Xtal_32K(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF);
+    BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal);
+
+    /* Delay >1s */
+    BL702_Delay_US(1100);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power off XTAL 32K
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_Xtal_32K(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF);
+    BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power on RC32K
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_RC32K(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_RC32K);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    /* Delay >800us */
+    BL702_Delay_US(880);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power off RC3K
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_RC32K(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_RC32K);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Trim RC32K
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Trim_RC32K(void)
+{
+    Efuse_Ana_RC32K_Trim_Type trim;
+    int32_t tmpVal = 0;
+
+    EF_Ctrl_Read_RC32K_Trim(&trim);
+
+    if (trim.trimRc32kExtCodeEn) {
+        if (trim.trimRc32kCodeFrExtParity == EF_Ctrl_Get_Trim_Parity(trim.trimRc32kCodeFrExt, 10)) {
+            tmpVal = BL_RD_REG(HBN_BASE, HBN_RC32K_CTRL0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RC32K_CODE_FR_EXT, trim.trimRc32kCodeFrExt);
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RC32K_EXT_CODE_EN);
+            BL_WR_REG(HBN_BASE, HBN_RC32K_CTRL0, tmpVal);
+            BL702_Delay_US(2);
+            return SUCCESS;
+        }
+    }
+
+    return ERROR;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Get HBN status flag
+ *
+ * @param  None
+ *
+ * @return HBN status flag value
+ *
+*******************************************************************************/
+uint32_t HBN_Get_Status_Flag(void)
+{
+    return BL_RD_REG(HBN_BASE, HBN_RSV0);
+}
+
+/****************************************************************************/ /**
+ * @brief  Set HBN status flag
+ *
+ * @param  flag: Status Flag
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_Status_Flag(uint32_t flag)
+{
+    BL_WR_REG(HBN_BASE, HBN_RSV0, flag);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get HBN wakeup address
+ *
+ * @param  None
+ *
+ * @return HBN wakeup address
+ *
+*******************************************************************************/
+uint32_t HBN_Get_Wakeup_Addr(void)
+{
+    return BL_RD_REG(HBN_BASE, HBN_RSV1);
+}
+
+/****************************************************************************/ /**
+ * @brief  Set HBN wakeup address
+ *
+ * @param  addr: HBN wakeup address
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr)
+{
+    BL_WR_REG(HBN_BASE, HBN_RSV1, addr);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN clear RTC timer counter
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Clear_RTC_Counter(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Clear RTC control bit0 */
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffffe);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN clear RTC timer counter
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Enable_RTC_Counter(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Set RTC control bit0 */
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal | 0x01);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN set RTC timer configuration
+ *
+ * @param  delay: RTC interrupt delay 32 clocks
+ * @param  compValLow: RTC interrupt commpare value low 32 bits
+ * @param  compValHigh: RTC interrupt commpare value high 32 bits
+ * @param  compMode: RTC interrupt commpare
+ *                   mode:HBN_RTC_COMP_BIT0_39,HBN_RTC_COMP_BIT0_23,HBN_RTC_COMP_BIT13_39
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_HBN_RTC_INT_DELAY_TYPE(delay));
+
+    BL_WR_REG(HBN_BASE, HBN_TIME_L, compValLow);
+    BL_WR_REG(HBN_BASE, HBN_TIME_H, compValHigh & 0xff);
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Set interrupt delay option */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RTC_DLY_OPTION, delay);
+    /* Set RTC compare mode */
+    tmpVal |= (compMode << 1);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN get RTC async timer count value
+ *
+ * @param  valLow: RTC count value pointer for low 32 bits
+ * @param  valHigh: RTC count value pointer for high 8 bits
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+static BL_Err_Type HBN_Get_RTC_Timer_Async_Val(uint32_t *valLow, uint32_t *valHigh)
+{
+    uint32_t tmpVal;
+
+    /* Tigger RTC val read */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);
+    BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);
+    BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);
+
+    /* Read RTC val */
+    *valLow = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_L);
+    *valHigh = (BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H) & 0xff);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN get RTC timer count value
+ *
+ * @param  valLow: RTC count value pointer for low 32 bits
+ * @param  valHigh: RTC count value pointer for high 8 bits
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh)
+{
+    uint32_t tmpValLow, tmpValHigh, tmpValLow1, tmpValHigh1;
+    uint64_t val, val1;
+
+    do {
+        HBN_Get_RTC_Timer_Async_Val(&tmpValLow, &tmpValHigh);
+        val = ((uint64_t)tmpValHigh << 32) | ((uint64_t)tmpValLow);
+        HBN_Get_RTC_Timer_Async_Val(&tmpValLow1, &tmpValHigh1);
+        val1 = ((uint64_t)tmpValHigh1 << 32) | ((uint64_t)tmpValLow1);
+    } while (val1 < val);
+
+    *valLow = tmpValLow1;
+    *valHigh = tmpValHigh1;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN clear RTC timer interrupt,this function must be called to clear delayed rtc IRQ
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Clear_RTC_INT(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Clear RTC commpare:bit1-3 for clearing Delayed RTC IRQ */
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffff1);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN enable GPIO interrupt
+ *
+ * @param  gpioIntTrigType: HBN GPIO interrupt trigger type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_HBN_GPIO_INT_TRIGGER_TYPE(gpioIntTrigType));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MODE, gpioIntTrigType);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN disable GPIO interrupt
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_GPIO_INT_Disable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, 0);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN get interrupt status
+ *
+ * @param  irqType: HBN interrupt type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_STAT);
+
+    if (tmpVal & (1 << irqType)) {
+        return SET;
+    } else {
+        return RESET;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN get pin wakeup mode value
+ *
+ * @param  None
+ *
+ * @return HBN pin wakeup mode value
+ *
+*******************************************************************************/
+uint8_t HBN_Get_Pin_Wakeup_Mode(void)
+{
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_IRQ_MODE), HBN_PIN_WAKEUP_MODE);
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN clear interrupt status
+ *
+ * @param  irqType: HBN interrupt type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_INT_TYPE(irqType));
+
+    /* set clear bit */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);
+    tmpVal |= (1 << irqType);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal);
+
+    /* unset clear bit */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);
+    tmpVal &= (~(1 << irqType));
+    BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN hardware pullup or pulldown configuration
+ *
+ * @param  enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Hw_Pu_Pd_Cfg(uint8_t enable)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
+    }
+
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN Config AON pad input and SMT
+ *
+ * @param  padCfg: AON pad config
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Aon_Pad_IeSmt_Cfg(uint8_t padCfg)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, padCfg);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN wakeup pin mask configuration
+ *
+ * @param  maskVal: mask value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Pin_WakeUp_Mask(uint8_t maskVal)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, maskVal);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN enable ACOMP0 interrupt
+ *
+ * @param  edge: HBN acomp interrupt edge type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN);
+    tmpVal2 = tmpVal2 | (1 << edge);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN disable ACOMP0 interrupt
+ *
+ * @param  edge: HBN acomp interrupt edge type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN);
+    tmpVal2 = tmpVal2 & (~(1 << edge));
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN enable ACOMP1 interrupt
+ *
+ * @param  edge: HBN acomp interrupt edge type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN);
+    tmpVal2 = tmpVal2 | (1 << edge);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN disable ACOMP1 interrupt
+ *
+ * @param  edge: HBN acomp interrupt edge type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN);
+    tmpVal2 = tmpVal2 & (~(1 << edge));
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN enable BOR interrupt
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Enable_BOR_IRQ(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_IRQ_BOR_EN);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN disable BOR interrupt
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Disable_BOR_IRQ(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_IRQ_BOR_EN);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get HBN reset event status
+ *
+ * @param  event: HBN reset event type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type HBN_Get_Reset_Event(HBN_RST_EVENT_Type event)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_RESET_EVENT);
+
+    return (tmpVal & (1 << event)) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  clear HBN reset event status
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Clear_Reset_Event(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_CLEAR_RESET_EVENT);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_CLEAR_RESET_EVENT);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_CLEAR_RESET_EVENT);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN out0 install interrupt callback
+ *
+ * @param  intType: HBN out0 interrupt type
+ * @param  cbFun: HBN out0 interrupt callback
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType, intCallback_Type *cbFun)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_HBN_OUT0_INT_TYPE(intType));
+
+    hbnInt0CbfArra[intType] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN out1 install interrupt callback
+ *
+ * @param  intType: HBN out1 interrupt type
+ * @param  cbFun: HBN out1 interrupt callback
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType, intCallback_Type *cbFun)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_HBN_OUT1_INT_TYPE(intType));
+
+    hbnInt1CbfArra[intType] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN GPIO debug pull config
+ *
+ * @param  pupdEn: Enable or disable GPIO pull down and pull up
+ * @param  dlyEn: Enable or disable GPIO wakeup delay function
+ * @param  dlySec: GPIO wakeup delay sec 1 to 7
+ * @param  gpioIrq: HBN GPIO num
+ * @param  gpioMask: HBN GPIO MASK or UNMASK
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION HBN_GPIO_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type dlyEn, uint8_t dlySec, HBN_INT_Type gpioIrq, BL_Mask_Type gpioMask)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(((dlySec >= 1) && (dlySec <= 7)));
+    CHECK_PARAM((gpioIrq >= HBN_INT_GPIO9) && (gpioIrq <= HBN_INT_GPIO13));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_EN, dlyEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_SEL, dlySec);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_EN_HW_PU_PD, pupdEn);
+
+    if (gpioMask != UNMASK) {
+        tmpVal = tmpVal | (1 << (gpioIrq + 8));
+    } else {
+        tmpVal = tmpVal & ~(1 << (gpioIrq + 8));
+    }
+
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set pad 23-28 pull none
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Pad_23_28_Pullnone(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLDOWN_AON, 0x00);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLUP_AON, 0x00);
+    BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set pad 23-28 pull up
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Pad_23_28_Pullup(void)
+{
+    uint32_t tmpVal = 0;
+
+    /********************************************/
+    /* GPIO28 is bootpin, so leave it pull none */
+    /********************************************/
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLDOWN_AON, 0x00);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLUP_AON, 0x1F);
+    BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set pad 23-28 pull down
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Pad_23_28_Pulldown(void)
+{
+    uint32_t tmpVal = 0;
+
+    /********************************************/
+    /* GPIO28 is bootpin, so leave it pull none */
+    /********************************************/
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLDOWN_AON, 0x1F);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLUP_AON, 0x00);
+    BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set pad 23-28 active ie
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Pad_23_28_ActiveIE(void)
+{
+    uint32_t tmpVal = 0;
+
+    /********************************************/
+    /* GPIO28 is bootpin, so leave it pull none */
+    /********************************************/
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLDOWN_AON, 0x1F);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLUP_AON, 0x1F);
+    BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set BOR config
+ *
+ * @param  cfg: Enable or disable
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_BOR_Cfg(HBN_BOR_CFG_Type *cfg)
+{
+    uint32_t tmpVal = 0;
+
+    if (cfg->enableBorInt) {
+        HBN_Enable_BOR_IRQ();
+    } else {
+        HBN_Disable_BOR_IRQ();
+    }
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_VTH, cfg->borThreshold);
+
+    if (cfg->enablePorInBor) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, HBN_BOR_SEL);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_BOR_SEL);
+    }
+
+    if (cfg->enableBor) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_BOR);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_BOR);
+    }
+
+    BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN OUT0 interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void HBN_OUT0_IRQHandler(void)
+{
+    if (SET == HBN_Get_INT_State(HBN_INT_GPIO9)) {
+        HBN_Clear_IRQ(HBN_INT_GPIO9);
+
+        if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO9] != NULL) {
+            hbnInt0CbfArra[HBN_OUT0_INT_GPIO9]();
+        }
+    }
+
+    if (SET == HBN_Get_INT_State(HBN_INT_GPIO10)) {
+        HBN_Clear_IRQ(HBN_INT_GPIO10);
+
+        if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO10] != NULL) {
+            hbnInt0CbfArra[HBN_OUT0_INT_GPIO10]();
+        }
+    }
+
+    if (SET == HBN_Get_INT_State(HBN_INT_GPIO11)) {
+        HBN_Clear_IRQ(HBN_INT_GPIO11);
+
+        if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO11] != NULL) {
+            hbnInt0CbfArra[HBN_OUT0_INT_GPIO11]();
+        }
+    }
+
+    if (SET == HBN_Get_INT_State(HBN_INT_GPIO12)) {
+        HBN_Clear_IRQ(HBN_INT_GPIO12);
+
+        if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO12] != NULL) {
+            hbnInt0CbfArra[HBN_OUT0_INT_GPIO12]();
+        }
+    }
+
+    if (SET == HBN_Get_INT_State(HBN_INT_GPIO13)) {
+        HBN_Clear_IRQ(HBN_INT_GPIO13);
+
+        if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO13] != NULL) {
+            hbnInt0CbfArra[HBN_OUT0_INT_GPIO13]();
+        }
+    }
+
+    if (SET == HBN_Get_INT_State(HBN_INT_RTC)) {
+        HBN_Clear_IRQ(HBN_INT_RTC);
+        HBN_Clear_RTC_INT();
+
+        if (hbnInt0CbfArra[HBN_OUT0_INT_RTC] != NULL) {
+            hbnInt0CbfArra[HBN_OUT0_INT_RTC]();
+        }
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN OUT1 interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void HBN_OUT1_IRQHandler(void)
+{
+    /* PIR */
+    if (SET == HBN_Get_INT_State(HBN_INT_PIR)) {
+        HBN_Clear_IRQ(HBN_INT_PIR);
+
+        if (hbnInt1CbfArra[HBN_OUT1_INT_PIR] != NULL) {
+            hbnInt1CbfArra[HBN_OUT1_INT_PIR]();
+        }
+    }
+
+    /* BOR */
+    if (SET == HBN_Get_INT_State(HBN_INT_BOR)) {
+        HBN_Clear_IRQ(HBN_INT_BOR);
+
+        if (hbnInt1CbfArra[HBN_OUT1_INT_BOR] != NULL) {
+            hbnInt1CbfArra[HBN_OUT1_INT_BOR]();
+        }
+    }
+
+    /* ACOMP0 */
+    if (SET == HBN_Get_INT_State(HBN_INT_ACOMP0)) {
+        HBN_Clear_IRQ(HBN_INT_ACOMP0);
+
+        if (hbnInt1CbfArra[HBN_OUT1_INT_ACOMP0] != NULL) {
+            hbnInt1CbfArra[HBN_OUT1_INT_ACOMP0]();
+        }
+    }
+
+    /* ACOMP1 */
+    if (SET == HBN_Get_INT_State(HBN_INT_ACOMP1)) {
+        HBN_Clear_IRQ(HBN_INT_ACOMP1);
+
+        if (hbnInt1CbfArra[HBN_OUT1_INT_ACOMP1] != NULL) {
+            hbnInt1CbfArra[HBN_OUT1_INT_ACOMP1]();
+        }
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable HBN mode
+ *
+ * @param  aGPIOIeCfg: AON GPIO IE config,Bit0->GPIO18. Bit(s) of Wakeup GPIO(s) must not be set to
+ *                     0(s),say when use GPIO7 as wake up pin,aGPIOIeCfg should be 0x01.
+ * @param  ldoLevel: LDO volatge level
+ * @param  hbnLevel: HBN work level
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION HBN_Enable(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+    CHECK_PARAM(IS_HBN_LEVEL_TYPE(hbnLevel));
+
+    /* Setting from guide */
+    /* RAM Retion */
+    BL_WR_REG(HBN_BASE, HBN_SRAM, 0x24);
+    /* AON GPIO IE */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aGPIOIeCfg);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+    ///* Power off 1.8V */
+    //tmpVal=BL_RD_REG(AON_BASE,AON_PMIP);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_TOPLDO11_SOC);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_TOPLDO18_RF);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_TOPLDO18_IO);
+    ///* SOC11 enum is not the same as VDD11*/
+    //tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_TOPLDO11_SOC_VOUT_SEL,ldoLevel-1);
+    //BL_WR_REG(AON_BASE,AON_PMIP,tmpVal);
+    //
+    ///* Set RT voltage */
+    //tmpVal=BL_RD_REG(AON_BASE,AON);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_TOPLDO18_IO_SW3);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_TOPLDO18_IO_SW2);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_TOPLDO18_IO_SW1);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_TOPLDO18_IO_BYPASS);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_LDO18_AON);
+    ///* RT11 enum is not the same as VDD11*/
+    //tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_TOPLDO11_RT_VOUT_SEL,ldoLevel-1);
+    //tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_VDD11_SEL,ldoLevel);
+    //BL_WR_REG(AON_BASE,AON,tmpVal);
+
+    /* Select RC32M */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+
+    /* Set HBN flag */
+    BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG);
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+
+    /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */
+    switch (hbnLevel) {
+        case HBN_LEVEL_0:
+            tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+            break;
+
+        case HBN_LEVEL_1:
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+            break;
+
+        case HBN_LEVEL_2:
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+            break;
+
+        case HBN_LEVEL_3:
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+            break;
+
+        default:
+            break;
+    }
+
+    /* Set power on option:0 for por reset twice for robust 1 for reset only once*/
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    /* Enable HBN mode */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    while (1) {
+        BL702_Delay_MS(1000);
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN out0 IRQHandler install
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Out0_IRQHandler_Install(void)
+{
+    Interrupt_Handler_Register(HBN_OUT0_IRQn, HBN_OUT0_IRQHandler);
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN out1 IRQHandler install
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Out1_IRQHandler_Install(void)
+{
+    Interrupt_Handler_Register(HBN_OUT1_IRQn, HBN_OUT1_IRQHandler);
+    return SUCCESS;
+}
+
+/*@} end of group HBN_Public_Functions */
+
+/*@} end of group HBN */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_i2c.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_i2c.c
new file mode 100644
index 00000000..1398efed
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_i2c.c
@@ -0,0 +1,822 @@
+/**
+ ******************************************************************************
+ * @file    bl702_i2c.c
+ * @version V1.0
+ * @date
+ * @brief   This file is the standard driver c file
+ ******************************************************************************
+ * @attention
+ *
+ * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#include "bl702_i2c.h"
+#include "bflb_platform.h"
+#include "bl702_glb.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  I2C
+ *  @{
+ */
+
+/** @defgroup  I2C_Private_Macros
+ *  @{
+ */
+#define I2C_FIFO_STATUS_TIMEOUT (160 * 1000 * 2)
+#define PUT_UINT32_LE(n, b, i)           \
+  {                                      \
+    (b)[(i)]     = (uint8_t)((n));       \
+    (b)[(i) + 1] = (uint8_t)((n) >> 8);  \
+    (b)[(i) + 2] = (uint8_t)((n) >> 16); \
+    (b)[(i) + 3] = (uint8_t)((n) >> 24); \
+  }
+
+/*@} end of group I2C_Private_Macros */
+
+/** @defgroup  I2C_Private_Types
+ *  @{
+ */
+
+/*@} end of group I2C_Private_Types */
+
+/** @defgroup  I2C_Private_Variables
+ *  @{
+ */
+intCallback_Type *i2cIntCbfArra[I2C_ID_MAX][I2C_INT_ALL] = {{NULL}};
+
+/*@} end of group I2C_Private_Variables */
+
+/** @defgroup  I2C_Global_Variables
+ *  @{
+ */
+
+/*@} end of group I2C_Global_Variables */
+
+/** @defgroup  I2C_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group I2C_Private_Fun_Declaration */
+
+/** @defgroup  I2C_Private_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+                                                                                * @brief  I2C interrupt handler
+                                                                                *
+                                                                                * @param  i2cNo: I2C ID type
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+static void I2C_IntHandler(I2C_ID_Type i2cNo) {
+  uint32_t tmpVal;
+  uint32_t I2Cx = I2C_BASE;
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
+
+  tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS);
+
+  if (BL_IS_REG_BIT_SET(tmpVal, I2C_END_INT)) {
+    if (i2cIntCbfArra[i2cNo][I2C_TRANS_END_INT] != NULL) {
+      /* Call the callback function */
+      i2cIntCbfArra[i2cNo][I2C_TRANS_END_INT]();
+    }
+  }
+
+  if (BL_IS_REG_BIT_SET(tmpVal, I2C_TXF_INT)) {
+    if (i2cIntCbfArra[i2cNo][I2C_TX_FIFO_READY_INT] != NULL) {
+      /* Call the callback function */
+      i2cIntCbfArra[i2cNo][I2C_TX_FIFO_READY_INT]();
+    }
+  }
+
+  if (BL_IS_REG_BIT_SET(tmpVal, I2C_RXF_INT)) {
+    if (i2cIntCbfArra[i2cNo][I2C_RX_FIFO_READY_INT] != NULL) {
+      /* Call the callback function */
+      i2cIntCbfArra[i2cNo][I2C_RX_FIFO_READY_INT]();
+    }
+  }
+
+  if (BL_IS_REG_BIT_SET(tmpVal, I2C_NAK_INT)) {
+    if (i2cIntCbfArra[i2cNo][I2C_NACK_RECV_INT] != NULL) {
+      /* Call the callback function */
+      i2cIntCbfArra[i2cNo][I2C_NACK_RECV_INT]();
+    }
+  }
+
+  if (BL_IS_REG_BIT_SET(tmpVal, I2C_ARB_INT)) {
+    if (i2cIntCbfArra[i2cNo][I2C_ARB_LOST_INT] != NULL) {
+      /* Call the callback function */
+      i2cIntCbfArra[i2cNo][I2C_ARB_LOST_INT]();
+    }
+  }
+
+  if (BL_IS_REG_BIT_SET(tmpVal, I2C_FER_INT)) {
+    if (i2cIntCbfArra[i2cNo][I2C_FIFO_ERR_INT] != NULL) {
+      /* Call the callback function */
+      i2cIntCbfArra[i2cNo][I2C_FIFO_ERR_INT]();
+    }
+  }
+}
+#endif
+
+/*@} end of group I2C_Private_Functions */
+
+/** @defgroup  I2C_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+                                                                                * @brief  I2C write word data
+                                                                                *
+                                                                                * @param  i2cNo: I2C ID type
+                                                                                * @param  data: Data word
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+void I2C_SendWord(I2C_ID_Type i2cNo, uint32_t data) {
+  uint32_t I2Cx = I2C_BASE;
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
+  BL_WR_REG(I2Cx, I2C_FIFO_WDATA, data);
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  I2C read word data
+                                                                                *
+                                                                                * @param  i2cNo: I2C ID type
+                                                                                *
+                                                                                * @return word data
+                                                                                *
+                                                                                *******************************************************************************/
+uint32_t I2C_RecieveWord(I2C_ID_Type i2cNo) {
+  uint32_t I2Cx = I2C_BASE;
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
+  return BL_RD_REG(I2Cx, I2C_FIFO_RDATA);
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  I2C enable
+                                                                                *
+                                                                                * @param  i2cNo: I2C ID type
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+void I2C_Enable(I2C_ID_Type i2cNo) {
+  uint32_t tmpVal;
+  uint32_t I2Cx = I2C_BASE;
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
+
+  tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG);
+  tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_M_EN);
+  BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal);
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  I2C disable
+                                                                                *
+                                                                                * @param  i2cNo: I2C ID type
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+void I2C_Disable(I2C_ID_Type i2cNo) {
+  uint32_t tmpVal;
+  uint32_t I2Cx = I2C_BASE;
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
+
+  tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG);
+  tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_M_EN);
+  BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal);
+
+  /* Clear I2C fifo */
+  tmpVal = BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_0);
+  tmpVal = BL_SET_REG_BIT(tmpVal, I2C_TX_FIFO_CLR);
+  tmpVal = BL_SET_REG_BIT(tmpVal, I2C_RX_FIFO_CLR);
+  BL_WR_REG(I2Cx, I2C_FIFO_CONFIG_0, tmpVal);
+
+  /* Clear I2C interrupt status */
+  tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS);
+  tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_CLR);
+  tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_CLR);
+  tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_CLR);
+  BL_WR_REG(I2Cx, I2C_INT_STS, tmpVal);
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  I2C set global reset function
+                                                                                *
+                                                                                * @param  i2cNo: I2C ID type
+                                                                                *
+                                                                                * @return SUCCESS or ERROR
+                                                                                *
+                                                                                *******************************************************************************/
+BL_Err_Type I2C_Reset(I2C_ID_Type i2cNo) {
+  /* Check the parameters */
+  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
+
+  GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_I2C);
+  return SUCCESS;
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  I2C init function
+                                                                                *
+                                                                                * @param  i2cNo: I2C ID type
+                                                                                * @param  direct: I2C read or write direct
+                                                                                * @param  cfg: I2C transfer config struct
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+void I2C_Init(I2C_ID_Type i2cNo, I2C_Direction_Type direct, I2C_Transfer_Cfg *cfg) {
+  uint32_t tmpVal;
+  uint32_t I2Cx = I2C_BASE;
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
+
+  /* Disable clock gate */
+  GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_I2C);
+
+  /* I2C write config */
+  tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG);
+
+  if (direct == I2C_WRITE) {
+    tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_PKT_DIR);
+  } else {
+    tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_PKT_DIR);
+  }
+
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_SLV_ADDR, cfg->slaveAddr);
+
+  if (cfg->subAddrSize > 0) {
+    tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_SUB_ADDR_EN);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_SUB_ADDR_BC, cfg->subAddrSize - 1);
+  } else {
+    tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_SUB_ADDR_EN);
+  }
+
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PKT_LEN, cfg->dataSize - 1);
+  BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal);
+
+  /* Set sub address */
+  BL_WR_REG(I2Cx, I2C_SUB_ADDR, cfg->subAddr);
+
+#ifndef BFLB_USE_HAL_DRIVER
+  Interrupt_Handler_Register(I2C_IRQn, I2C_IRQHandler);
+#endif
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  Set de-glitch function cycle count value
+                                                                                *
+                                                                                * @param  i2cNo: I2C ID type
+                                                                                * @param  cnt: De-glitch function cycle count
+                                                                                *
+                                                                                * @return SUCCESS
+                                                                                *
+                                                                                *******************************************************************************/
+BL_Err_Type I2C_SetDeglitchCount(I2C_ID_Type i2cNo, uint8_t cnt) {
+  uint32_t tmpVal;
+  uint32_t I2Cx = I2C_BASE;
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
+
+  tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG);
+
+  if (cnt > 0) {
+    /* enable de-glitch function */
+    tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_DEG_EN);
+  } else if (cnt == 0) {
+    /* disable de-glitch function */
+    tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_DEG_EN);
+  } else {
+    return ERROR;
+  }
+
+  /* Set count value */
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_DEG_CNT, cnt);
+  BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal);
+
+  return SUCCESS;
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  Set i2c prd
+                                                                                *
+                                                                                * @param  i2cNo: I2C ID type
+                                                                                * @param  phase: I2C phase value
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+void I2C_SetPrd(I2C_ID_Type i2cNo, uint8_t phase) {
+  uint32_t tmpVal;
+  uint32_t I2Cx = I2C_BASE;
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
+
+  // phase_cycles = (32000000 / phase / 4) - 1;
+  tmpVal = BL_RD_REG(I2Cx, I2C_PRD_START);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_0, phase);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_1, phase);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_2, phase);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_3, phase);
+  BL_WR_REG(I2Cx, I2C_PRD_START, tmpVal);
+  tmpVal = BL_RD_REG(I2Cx, I2C_PRD_STOP);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_0, phase);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_1, phase);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_2, phase);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_3, phase);
+  BL_WR_REG(I2Cx, I2C_PRD_STOP, tmpVal);
+  tmpVal = BL_RD_REG(I2Cx, I2C_PRD_DATA);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_0, phase);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_1, phase);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_2, phase);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_3, phase);
+  BL_WR_REG(I2Cx, I2C_PRD_DATA, tmpVal);
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  I2C set scl output clock
+                                                                                *
+                                                                                * @param  i2cNo: I2C ID type
+                                                                                * @param  clk: Clock set
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+void I2C_ClockSet(I2C_ID_Type i2cNo, uint32_t clk) {
+  uint8_t bclkDiv = 0;
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
+
+  bclkDiv = GLB_Get_BCLK_Div();
+
+  if (clk >= 100000) {
+    GLB_Set_I2C_CLK(1, 0);
+    I2C_SetPrd(i2cNo, (SystemCoreClockGet() / (bclkDiv + 1)) / (clk * 4) - 1);
+  } else if (clk >= 8000) {
+    GLB_Set_I2C_CLK(1, 9);
+    I2C_SetPrd(i2cNo, ((SystemCoreClockGet() / (bclkDiv + 1)) / 10) / (clk * 4) - 1);
+  } else if (clk >= 800) {
+    GLB_Set_I2C_CLK(1, 99);
+    I2C_SetPrd(i2cNo, ((SystemCoreClockGet() / (bclkDiv + 1)) / 100) / (clk * 4) - 1);
+  } else {
+    GLB_Set_I2C_CLK(1, 255);
+    I2C_SetPrd(i2cNo, ((SystemCoreClockGet() / (bclkDiv + 1)) / 256) / (clk * 4) - 1);
+  }
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  I2C set scl sync
+                                                                                *
+                                                                                * @param  i2cNo: I2C ID type
+                                                                                * @param  enable: Enable or disable I2C scl sync
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+void I2C_SetSclSync(I2C_ID_Type i2cNo, uint8_t enable) {
+  uint32_t tmpVal;
+  uint32_t I2Cx = I2C_BASE;
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
+
+  tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG);
+
+  if (enable) {
+    tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_SCL_SYNC_EN);
+  } else {
+    tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_SCL_SYNC_EN);
+  }
+
+  BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal);
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  Get i2c busy state
+                                                                                *
+                                                                                * @param  i2cNo: I2C ID type
+                                                                                *
+                                                                                * @return RESET or SET
+                                                                                *
+                                                                                *******************************************************************************/
+BL_Sts_Type I2C_IsBusy(I2C_ID_Type i2cNo) {
+  uint32_t tmpVal;
+  uint32_t I2Cx = I2C_BASE;
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
+
+  tmpVal = BL_RD_REG(I2Cx, I2C_BUS_BUSY);
+  return ((BL_IS_REG_BIT_SET(tmpVal, I2C_STS_I2C_BUS_BUSY)) ? SET : RESET);
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  Get i2c transfer end state
+                                                                                *
+                                                                                * @param  i2cNo: I2C ID type
+                                                                                *
+                                                                                * @return RESET or SET
+                                                                                *
+                                                                                *******************************************************************************/
+BL_Sts_Type I2C_TransferEndStatus(I2C_ID_Type i2cNo) {
+  uint32_t tmpVal;
+  uint32_t I2Cx = I2C_BASE;
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
+
+  tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS);
+  return ((BL_IS_REG_BIT_SET(tmpVal, I2C_END_INT)) ? SET : RESET);
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  I2C master write block data
+                                                                                *
+                                                                                * @param  i2cNo: I2C ID type
+                                                                                * @param  cfg: I2C transfer config struct
+                                                                                *
+                                                                                * @return SUCCESS or ERROR
+                                                                                *
+                                                                                *******************************************************************************/
+BL_Err_Type I2C_MasterSendBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg) {
+  uint8_t  i;
+  uint32_t timeOut = 0;
+  uint32_t temp    = 0;
+  uint32_t I2Cx    = I2C_BASE;
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
+
+  I2C_Disable(i2cNo);
+  I2C_Init(i2cNo, I2C_WRITE, cfg);
+  I2C_Enable(i2cNo);
+
+  /* Set I2C write data */
+  for (i = 0; i < cfg->dataSize; i++) {
+    temp += (cfg->data[i] << ((i % 4) * 8));
+
+    if ((i + 1) % 4 == 0) {
+      timeOut = I2C_FIFO_STATUS_TIMEOUT;
+
+      while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_TX_FIFO_CNT) == 0) {
+        timeOut--;
+
+        if (timeOut == 0) {
+          I2C_Disable(i2cNo);
+          return TIMEOUT;
+        }
+      }
+
+      BL_WR_REG(I2Cx, I2C_FIFO_WDATA, temp);
+      temp = 0;
+    }
+  }
+
+  if ((cfg->dataSize % 4) != 0) {
+    timeOut = I2C_FIFO_STATUS_TIMEOUT;
+
+    while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_TX_FIFO_CNT) == 0) {
+      timeOut--;
+
+      if (timeOut == 0) {
+        I2C_Disable(i2cNo);
+        return TIMEOUT;
+      }
+    }
+
+    BL_WR_REG(I2Cx, I2C_FIFO_WDATA, temp);
+  }
+
+  timeOut = I2C_FIFO_STATUS_TIMEOUT;
+
+  while (I2C_IsBusy(i2cNo) || !I2C_TransferEndStatus(i2cNo)) {
+    timeOut--;
+
+    if (timeOut == 0) {
+      I2C_Disable(i2cNo);
+      return TIMEOUT;
+    }
+  }
+
+  I2C_Disable(i2cNo);
+  return SUCCESS;
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  I2C master read block data
+                                                                                *
+                                                                                * @param  i2cNo: I2C ID type
+                                                                                * @param  cfg: I2C transfer config struct
+                                                                                *
+                                                                                * @return SUCCESS or ERROR
+                                                                                *
+                                                                                *******************************************************************************/
+BL_Err_Type I2C_MasterReceiveBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg) {
+  uint8_t  i       = 0;
+  uint32_t timeOut = 0;
+  uint32_t temp    = 0;
+  uint32_t I2Cx    = I2C_BASE;
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
+
+  I2C_Disable(i2cNo);
+  I2C_Init(i2cNo, I2C_READ, cfg);
+  I2C_Enable(i2cNo);
+  timeOut = I2C_FIFO_STATUS_TIMEOUT;
+  if (cfg->dataSize == 0 && cfg->subAddrSize == 0) {
+    while (BL_RD_REG(I2C_BASE, I2C_BUS_BUSY)) {
+      timeOut--;
+
+      if (timeOut == 0) {
+        I2C_Disable(i2cNo);
+        return TIMEOUT;
+      }
+    }
+
+    temp = BL_RD_REG(I2C_BASE, I2C_INT_STS); // TODO this sucks as a workaround
+    if (BL_IS_REG_BIT_SET(temp, I2C_NAK_INT)) {
+      temp = BL_RD_REG(I2C_BASE, I2C_BUS_BUSY);
+      I2C_Disable(i2cNo);
+      return TIMEOUT;
+    }
+  }
+  /* Read I2C data */
+  while (cfg->dataSize - i >= 4) {
+    timeOut = I2C_FIFO_STATUS_TIMEOUT;
+
+    while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_RX_FIFO_CNT) == 0) {
+      timeOut--;
+
+      if (timeOut == 0) {
+        I2C_Disable(i2cNo);
+        return TIMEOUT;
+      }
+    }
+
+    temp = BL_RD_REG(I2Cx, I2C_FIFO_RDATA);
+    PUT_UINT32_LE(temp, cfg->data, i);
+    i += 4;
+  }
+
+  if (i < cfg->dataSize) {
+    timeOut = I2C_FIFO_STATUS_TIMEOUT;
+
+    while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_RX_FIFO_CNT) == 0) {
+      timeOut--;
+
+      if (timeOut == 0) {
+        I2C_Disable(i2cNo);
+        return TIMEOUT;
+      }
+    }
+
+    temp = BL_RD_REG(I2Cx, I2C_FIFO_RDATA);
+
+    while (i < cfg->dataSize) {
+      cfg->data[i] = (temp & 0xff);
+      temp         = (temp >> 8);
+      i++;
+    }
+  }
+
+  timeOut = I2C_FIFO_STATUS_TIMEOUT;
+
+  while (I2C_IsBusy(i2cNo) || !I2C_TransferEndStatus(i2cNo)) {
+    timeOut--;
+
+    if (timeOut == 0) {
+      I2C_Disable(i2cNo);
+      return TIMEOUT;
+    }
+  }
+
+  I2C_Disable(i2cNo);
+  return SUCCESS;
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  Mask/Unmask the I2C interrupt
+                                                                                *
+                                                                                * @param  i2cNo: I2C ID type
+                                                                                * @param  intType: Specifies the interrupt type
+                                                                                * @param  intMask: Enable/Disable Specified interrupt type
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+void I2C_IntMask(I2C_ID_Type i2cNo, I2C_INT_Type intType, BL_Mask_Type intMask) {
+  uint32_t tmpVal;
+  uint32_t I2Cx = I2C_BASE;
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
+  CHECK_PARAM(IS_I2C_INT_TYPE(intType));
+  CHECK_PARAM(IS_BL_MASK_TYPE(intMask));
+
+  tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS);
+
+  switch (intType) {
+  case I2C_TRANS_END_INT:
+    if (intMask == UNMASK) {
+      /* UNMASK(Enable) this interrupt */
+      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_EN);
+      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK);
+    } else {
+      /* MASK(Disable) this interrupt */
+      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_EN);
+      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK);
+    }
+
+    break;
+
+  case I2C_TX_FIFO_READY_INT:
+    if (intMask == UNMASK) {
+      /* UNMASK(Enable) this interrupt */
+      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN);
+      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK);
+    } else {
+      /* MASK(Disable) this interrupt */
+      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN);
+      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK);
+    }
+
+    break;
+
+  case I2C_RX_FIFO_READY_INT:
+    if (intMask == UNMASK) {
+      /* UNMASK(Enable) this interrupt */
+      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN);
+      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK);
+    } else {
+      /* MASK(Disable) this interrupt */
+      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN);
+      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK);
+    }
+
+    break;
+
+  case I2C_NACK_RECV_INT:
+    if (intMask == UNMASK) {
+      /* UNMASK(Enable) this interrupt */
+      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN);
+      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK);
+    } else {
+      /* MASK(Disable) this interrupt */
+      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN);
+      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK);
+    }
+
+    break;
+
+  case I2C_ARB_LOST_INT:
+    if (intMask == UNMASK) {
+      /* UNMASK(Enable) this interrupt */
+      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN);
+      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK);
+    } else {
+      /* MASK(Disable) this interrupt */
+      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN);
+      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK);
+    }
+
+    break;
+
+  case I2C_FIFO_ERR_INT:
+    if (intMask == UNMASK) {
+      /* UNMASK(Enable) this interrupt */
+      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN);
+      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK);
+    } else {
+      /* MASK(Disable) this interrupt */
+      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN);
+      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK);
+    }
+
+    break;
+
+  case I2C_INT_ALL:
+    if (intMask == UNMASK) {
+      /* UNMASK(Enable) this interrupt */
+      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_EN);
+      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN);
+      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN);
+      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN);
+      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN);
+      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN);
+      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK);
+      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK);
+      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK);
+      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK);
+      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK);
+      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK);
+    } else {
+      /* MASK(Disable) this interrupt */
+      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_EN);
+      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN);
+      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN);
+      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN);
+      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN);
+      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN);
+      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK);
+      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK);
+      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK);
+      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK);
+      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK);
+      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK);
+    }
+
+    break;
+
+  default:
+    break;
+  }
+
+  BL_WR_REG(I2Cx, I2C_INT_STS, tmpVal);
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  Install I2C interrupt callback function
+                                                                                *
+                                                                                * @param  i2cNo: I2C ID type
+                                                                                * @param  intType: Specifies the interrupt type
+                                                                                * @param  cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void I2C_Int_Callback_Install(I2C_ID_Type i2cNo, I2C_INT_Type intType, intCallback_Type *cbFun) {
+  /* Check the parameters */
+  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
+  CHECK_PARAM(IS_I2C_INT_TYPE(intType));
+
+  i2cIntCbfArra[i2cNo][intType] = cbFun;
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  I2C IRQ handler
+                                                                                *
+                                                                                * @param  None
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void I2C_IRQHandler(void) { I2C_IntHandler(I2C0_ID); }
+#endif
+
+/*@} end of group I2C_Public_Functions */
+
+/*@} end of group I2C */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_i2c_gpio_sim.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_i2c_gpio_sim.c
new file mode 100644
index 00000000..3a1d4e91
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_i2c_gpio_sim.c
@@ -0,0 +1,457 @@
+/**
+ ******************************************************************************
+ * @file    bl702_i2c_gpio_sim.c
+ * @version V1.0
+ * @date
+ * @brief   This file is the standard driver c file
+ ******************************************************************************
+ * @attention
+ *
+ * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#include "bl702_glb.h"
+#include "bl702_gpio.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  I2C_GPIO_SIM
+ *  @{
+ */
+
+/** @defgroup  I2C_GPIO_SIM_Private_Macros
+ *  @{
+ */
+#define SCL_H           GLB_GPIO_Write(sclPin, 1)
+#define SCL_L           GLB_GPIO_Write(sclPin, 0)
+#define SDA_H           GLB_GPIO_Write(sdaPin, 1)
+#define SDA_L           GLB_GPIO_Write(sdaPin, 0)
+#define SDA_read        GLB_GPIO_Read(sdaPin)
+#define I2C_Delay_US(a) BL702_Delay_US(a)
+#define I2C_Delay_Const I2C_Delay_US(2)
+
+/*@} end of group I2C_GPIO_SIM_Private_Macros */
+
+/** @defgroup  I2C_GPIO_SIM_Private_Types
+ *  @{
+ */
+
+/*@} end of group I2C_GPIO_SIM_Private_Types */
+
+/** @defgroup  I2C_GPIO_SIM_Private_Variables
+ *  @{
+ */
+static GLB_GPIO_Type sclPin;
+static GLB_GPIO_Type sdaPin;
+static uint8_t       sda_out = 0;
+
+/*@} end of group I2C_GPIO_SIM_Private_Variables */
+
+/** @defgroup  I2C_GPIO_SIM_Global_Variables
+ *  @{
+ */
+
+/*@} end of group I2C_GPIO_SIM_Global_Variables */
+
+/** @defgroup  I2C_GPIO_SIM_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group I2C_GPIO_SIM_Private_Fun_Declaration */
+
+/** @defgroup  I2C_GPIO_SIM_Private_Functions
+ *  @{
+ */
+
+/*@} end of group I2C_GPIO_SIM_Private_Functions */
+
+/** @defgroup  I2C_GPIO_SIM_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+                                                                                * @brief  I2C GPIO init function
+                                                                                *
+                                                                                * @param  sclGPIOPin: I2C SCL GPIO pin
+                                                                                * @param  sdaGPIOPin: I2C SDA GPIO pin
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+void I2C_GPIO_Sim_Init(GLB_GPIO_Type sclGPIOPin, GLB_GPIO_Type sdaGPIOPin) {
+  GLB_GPIO_Cfg_Type cfg;
+  uint8_t           gpiopins[2];
+  uint8_t           gpiofuns[2];
+  size_t            i;
+
+  sclPin = sclGPIOPin;
+  sdaPin = sdaGPIOPin;
+
+  cfg.pullType = GPIO_PULL_UP;
+  cfg.drive    = 1;
+  cfg.smtCtrl  = 1;
+  cfg.gpioMode = GPIO_MODE_OUTPUT;
+
+  gpiopins[0] = sclPin;
+  gpiopins[1] = sdaPin;
+  gpiofuns[0] = 11;
+  gpiofuns[1] = 11;
+
+  for (i = 0; i < sizeof(gpiopins) / sizeof(gpiopins[0]); i++) {
+    cfg.gpioPin = gpiopins[i];
+    cfg.gpioFun = gpiofuns[i];
+    GLB_GPIO_Init(&cfg);
+  }
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  I2C SDA out function
+                                                                                *
+                                                                                * @param  None
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+static void I2C_SDA_OUT(void) {
+  GLB_GPIO_Cfg_Type cfg;
+
+  if (sda_out == 1) {
+    return;
+  }
+
+  cfg.pullType = GPIO_PULL_UP;
+  cfg.drive    = 1;
+  cfg.smtCtrl  = 1;
+  cfg.gpioMode = GPIO_MODE_OUTPUT;
+  cfg.gpioPin  = sdaPin;
+  cfg.gpioFun  = 11;
+
+  GLB_GPIO_Init(&cfg);
+
+  sda_out = 1;
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  I2C SDA in function
+                                                                                *
+                                                                                * @param  None
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+static void I2C_SDA_IN(void) {
+  GLB_GPIO_Cfg_Type cfg;
+
+  if (sda_out == 0) {
+    return;
+  }
+
+  cfg.pullType = GPIO_PULL_UP;
+  cfg.drive    = 1;
+  cfg.smtCtrl  = 1;
+  cfg.gpioMode = GPIO_MODE_INPUT;
+  cfg.gpioPin  = sdaPin;
+  cfg.gpioFun  = 11;
+
+  GLB_GPIO_Init(&cfg);
+
+  sda_out = 0;
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  I2C start function
+                                                                                *
+                                                                                * @param  None
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+void I2C_Start(void) {
+  I2C_SDA_OUT();
+  SDA_H;
+  I2C_Delay_Const;
+  SCL_H;
+  I2C_Delay_Const;
+  SDA_L;
+  I2C_Delay_Const;
+  SCL_L;
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  I2C stop function
+                                                                                *
+                                                                                * @param  None
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+void I2C_Stop(void) {
+  I2C_SDA_OUT();
+  SCL_L;
+  I2C_Delay_Const;
+  SDA_L;
+  I2C_Delay_Const;
+  SCL_H;
+  I2C_Delay_Const;
+  SDA_H;
+  I2C_Delay_Const;
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  I2C ack function
+                                                                                *
+                                                                                * @param  None
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+static void I2C_Ack(void) {
+  SCL_L;
+  I2C_Delay_Const;
+  I2C_SDA_OUT();
+  SDA_L;
+  I2C_Delay_Const;
+  SCL_H;
+  I2C_Delay_Const;
+  SCL_L;
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  I2C no ack function
+                                                                                *
+                                                                                * @param  None
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+static void I2C_NoAck(void) {
+  SCL_L;
+  I2C_Delay_Const;
+  I2C_SDA_OUT();
+  SDA_H;
+  I2C_Delay_Const;
+  SCL_H;
+  I2C_Delay_Const;
+  SCL_L;
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  I2C get ack function
+                                                                                *
+                                                                                * @param  None
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+uint8_t I2C_GetAck(void) {
+  uint8_t time = 0;
+
+  I2C_Delay_Const;
+  I2C_SDA_IN();
+
+  I2C_Delay_Const;
+  SCL_H;
+  I2C_Delay_Const;
+
+  while (SDA_read) {
+    time++;
+
+    if (time > 25) {
+      SCL_L;
+      return 0;
+    }
+  }
+
+  SCL_L;
+
+  return 1;
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  I2C send byte function
+                                                                                *
+                                                                                * @param  Data: send data
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+void I2C_SendByte(uint8_t Data) {
+  uint8_t cnt;
+
+  I2C_SDA_OUT();
+
+  for (cnt = 0; cnt < 8; cnt++) {
+    SCL_L;
+    I2C_Delay_Const;
+
+    if (Data & 0x80) {
+      SDA_H;
+    } else {
+      SDA_L;
+    }
+
+    Data <<= 1;
+    I2C_Delay_Const;
+    SCL_H;
+    I2C_Delay_Const;
+  }
+
+  SCL_L;
+
+  I2C_Delay_Const;
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  I2C read byte function
+                                                                                *
+                                                                                * @param  ack: i2c ack byte
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+uint8_t I2C_ReadByte(uint8_t ack) {
+  uint8_t cnt;
+  uint8_t data = 0;
+
+  I2C_SDA_IN();
+
+  for (cnt = 0; cnt < 8; cnt++) {
+    SCL_L;
+    I2C_Delay_Const;
+
+    SCL_H;
+    I2C_Delay_Const;
+    data <<= 1;
+
+    if (SDA_read) {
+      data |= 0x01;
+    }
+  }
+
+  if (ack == 1) {
+    I2C_Ack();
+  } else {
+    I2C_NoAck();
+  }
+
+  return data;
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  SCCB init function
+                                                                                *
+                                                                                * @param  sclGPIOPin: I2C SCL GPIO pin
+                                                                                * @param  sdaGPIOPin: I2C SDA GPIO pin
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+int SCCB_Init(GLB_GPIO_Type sclGPIOPin, GLB_GPIO_Type sdaGPIOPin) {
+  I2C_GPIO_Sim_Init(sclGPIOPin, sdaGPIOPin);
+  return 0;
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  SCCB write function
+                                                                                *
+                                                                                * @param  slave_addr: salve addr
+                                                                                * @param  data: write data
+                                                                                * @param  wrsize: write data len
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+int SCCB_Write(uint8_t slave_addr, uint8_t *data, uint32_t wrsize) {
+  uint32_t i = 0;
+
+  I2C_Start();
+
+  I2C_SendByte((slave_addr << 1) | 0);
+
+  if (!I2C_GetAck()) {
+    I2C_Stop();
+    return -1;
+  }
+
+  for (i = 0; i < wrsize; i++) {
+    I2C_SendByte(data[i]);
+
+    if (!I2C_GetAck()) {
+      I2C_Stop();
+      return -1;
+    }
+  }
+
+  I2C_Stop();
+
+  return 0;
+}
+
+/****************************************************************************/ /**
+                                                                                * @brief  SCCB read function
+                                                                                *
+                                                                                * @param  slave_addr: salve addr
+                                                                                * @param  data: read data
+                                                                                * @param  rdsize: read data len
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+int SCCB_Read(uint8_t slave_addr, uint8_t *data, uint32_t rdsize) {
+  uint32_t i = 0;
+
+  if (0 == rdsize) {
+    return -1;
+  }
+
+  I2C_Start();
+
+  I2C_SendByte((slave_addr << 1) | 1);
+
+  if (!I2C_GetAck()) {
+    I2C_Stop();
+    return -1;
+  }
+
+  for (i = 0; i < rdsize - 1; i++) {
+    data[i] = I2C_ReadByte(1);
+  }
+
+  data[i] = I2C_ReadByte(0);
+
+  I2C_Stop();
+
+  return 0;
+}
+
+/*@} end of group I2C_GPIO_SIM_Public_Functions */
+
+/*@} end of group I2C_GPIO_SIM */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_i2s.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_i2s.c
new file mode 100644
index 00000000..b79a1872
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_i2s.c
@@ -0,0 +1,469 @@
+/**
+  ******************************************************************************
+  * @file    bl702_i2s.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_i2s.h"
+#include "bl702_glb.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  I2S
+ *  @{
+ */
+
+/** @defgroup  I2S_Private_Macros
+ *  @{
+ */
+
+/*@} end of group I2S_Private_Macros */
+
+/** @defgroup  I2S_Private_Types
+ *  @{
+ */
+
+/*@} end of group I2S_Private_Types */
+
+/** @defgroup  I2S_Private_Variables
+ *  @{
+ */
+
+/*@} end of group I2S_Private_Variables */
+
+/** @defgroup  I2S_Global_Variables
+ *  @{
+ */
+
+/*@} end of group I2S_Global_Variables */
+
+/** @defgroup  I2S_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group I2S_Private_Fun_Declaration */
+
+/** @defgroup  I2S_Private_Functions
+ *  @{
+ */
+
+/*@} end of group I2S_Private_Functions */
+
+/** @defgroup  I2S_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  I2S BCLK config
+ *
+ * @param  i2sCfg: I2S configuration pointer
+ *
+ * @return NONE
+ *
+*******************************************************************************/
+void I2S_SetBclkPeriod(I2S_CFG_Type *i2sCfg)
+{
+    uint32_t overSampleRate;
+    uint32_t bclkDivCnt;
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_I2S_FRAME_SIZE_TYPE(i2sCfg->frameSize));
+
+    overSampleRate = i2sCfg->audioFreqHz / i2sCfg->sampleFreqHz;
+
+    switch (i2sCfg->frameSize) {
+        case I2S_SIZE_FRAME_8:
+            bclkDivCnt = overSampleRate / 16;
+            break;
+
+        case I2S_SIZE_FRAME_16:
+            bclkDivCnt = overSampleRate / 32;
+            break;
+
+        case I2S_SIZE_FRAME_24:
+            bclkDivCnt = overSampleRate / 48;
+            break;
+
+        case I2S_SIZE_FRAME_32:
+            bclkDivCnt = overSampleRate / 64;
+            break;
+
+        default:
+            bclkDivCnt = overSampleRate / 16;
+            break;
+    }
+
+    bclkDivCnt = (bclkDivCnt / 2) - 1;
+
+    tmpVal = (bclkDivCnt << 16) | bclkDivCnt;
+    BL_WR_REG(I2S_BASE, I2S_BCLK_CONFIG, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  I2S configuration
+ *
+ * @param  i2sCfg: I2S configuration pointer
+ *
+ * @return NONE
+ *
+*******************************************************************************/
+void I2S_Init(I2S_CFG_Type *i2sCfg)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_I2S_ENDIAN_TYPE(i2sCfg->endianType));
+    CHECK_PARAM(IS_I2S_MODE_TYPE(i2sCfg->modeType));
+    CHECK_PARAM(IS_I2S_FRAME_SIZE_TYPE(i2sCfg->frameSize));
+    CHECK_PARAM(IS_I2S_FS_MODE_TYPE(i2sCfg->fsMode));
+    CHECK_PARAM(IS_I2S_FS_CHANNEL_TYPE(i2sCfg->fsChannel));
+    CHECK_PARAM(IS_I2S_DATA_SIZE_TYPE(i2sCfg->dataSize));
+    CHECK_PARAM(IS_I2S_MONO_MODE_CHANNEL(i2sCfg->monoModeChannel));
+
+    /* Disable clock gate */
+    GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_I2S);
+
+    tmpVal = BL_RD_REG(I2S_BASE, I2S_CONFIG);
+
+    /* Set data endian*/
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_ENDIAN, i2sCfg->endianType);
+
+    /* Set I2S mode */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_MODE, i2sCfg->modeType);
+
+    /* Set BCLK invert */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_BCLK_INV, i2sCfg->bclkInvert);
+
+    /* Set FS size */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FRAME_SIZE, i2sCfg->frameSize);
+
+    /* Set FS invert */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_FS_INV, i2sCfg->fsInvert);
+
+    /* Set FS mode */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FS_1T_MODE, i2sCfg->fsMode);
+
+    /* Set FS channel mode */
+
+    switch (i2sCfg->fsChannel) {
+        case I2S_FS_CHANNELS_2:
+            tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_FS_3CH_MODE);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_FS_4CH_MODE);
+            break;
+
+        case I2S_FS_CHANNELS_3:
+            tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_FS_3CH_MODE);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_FS_4CH_MODE);
+            break;
+
+        case I2S_FS_CHANNELS_4:
+            tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_FS_3CH_MODE);
+            tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_FS_4CH_MODE);
+            break;
+
+        default:
+            break;
+    }
+
+    /* Set Data size */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_DATA_SIZE, i2sCfg->dataSize);
+
+    /* Set Data offset */
+    if (i2sCfg->dataOffset != 0) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_OFS_EN);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_OFS_CNT, i2sCfg->dataOffset - 1);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_OFS_EN);
+    }
+
+    /* Set mono mode */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_MONO_MODE, i2sCfg->monoMode);
+
+    /* Set rx mono mode channel left or right */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_MONO_RX_CH, i2sCfg->monoModeChannel);
+
+    /* Clear mute mode */
+    tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_MUTE_MODE);
+
+    BL_WR_REG(I2S_BASE, I2S_CONFIG, tmpVal);
+
+    I2S_SetBclkPeriod(i2sCfg);
+}
+
+/****************************************************************************/ /**
+ * @brief  I2S configure FIFO function
+ *
+ * @param  fifoCfg: FIFO configuration structure pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void I2S_FifoConfig(I2S_FifoCfg_Type *fifoCfg)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(I2S_BASE, I2S_FIFO_CONFIG_0);
+    /* Set packed mode */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FIFO_LR_MERGE, fifoCfg->lRMerge);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FIFO_LR_EXCHG, fifoCfg->frameDataExchange);
+    /* Clear tx and rx FIFO signal */
+    tmpVal = BL_SET_REG_BIT(tmpVal, I2S_TX_FIFO_CLR);
+    tmpVal = BL_SET_REG_BIT(tmpVal, I2S_RX_FIFO_CLR);
+
+    /* Set DMA config */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_DMA_TX_EN, fifoCfg->txfifoDmaEnable);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_DMA_RX_EN, fifoCfg->rxfifoDmaEnable);
+
+    BL_WR_REG(I2S_BASE, I2S_FIFO_CONFIG_0, tmpVal);
+
+    /* Set CLR signal to 0*/
+    tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_TX_FIFO_CLR);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_RX_FIFO_CLR);
+    BL_WR_REG(I2S_BASE, I2S_FIFO_CONFIG_0, tmpVal);
+
+    tmpVal = BL_RD_REG(I2S_BASE, I2S_FIFO_CONFIG_1);
+    /* Set TX and RX FIFO threshold */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_TX_FIFO_TH, fifoCfg->txFifoLevel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_RX_FIFO_TH, fifoCfg->rxFifoLevel);
+
+    BL_WR_REG(I2S_BASE, I2S_FIFO_CONFIG_1, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  I2S configure IO function
+ *
+ * @param  ioCfg: IO configuration structure pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void I2S_IOConfig(I2S_IOCfg_Type *ioCfg)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(I2S_BASE, I2S_IO_CONFIG);
+    /* Enable or disable deglitch */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_DEG_EN, ioCfg->deglitchEn);
+
+    /* Set deglitch cycle count */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_DEG_CNT, ioCfg->deglitchCnt);
+
+    /* Enable or disable inverse BCLK signal */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_BCLK_INV, ioCfg->inverseBCLK);
+
+    /* Enable or disable inverse FS signal */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_FS_INV, ioCfg->inverseFS);
+
+    /* Enable or disable inverse RX signal */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_RXD_INV, ioCfg->inverseRX);
+
+    /* Enable or disable inverse TX signal */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_TXD_INV, ioCfg->inverseTX);
+
+    BL_WR_REG(I2S_BASE, I2S_IO_CONFIG, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable I2S
+ *
+ * @param  roleType: I2S master or slave
+ *
+ * @return None
+ *
+*******************************************************************************/
+void I2S_Enable(I2S_Role_Type roleType)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_I2S_ROLE_TYPE(roleType));
+
+    tmpVal = BL_RD_REG(I2S_BASE, I2S_CONFIG);
+    tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_I2S_TXD_EN);
+    tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_I2S_RXD_EN);
+
+    /* Set role type */
+    if (I2S_ROLE_MASTER == roleType) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_I2S_M_EN);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_S_EN);
+    } else if (I2S_ROLE_SLAVE == roleType) {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_M_EN);
+        tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_I2S_S_EN);
+    }
+
+    BL_WR_REG(I2S_BASE, I2S_CONFIG, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable I2S
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void I2S_Disable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(I2S_BASE, I2S_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_TXD_EN);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_RXD_EN);
+
+    tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_M_EN);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_S_EN);
+    BL_WR_REG(I2S_BASE, I2S_CONFIG, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  I2S read data
+ *
+ * @param  None
+ *
+ * @return Data read
+ *
+*******************************************************************************/
+uint32_t I2S_Read(void)
+{
+    while (0 == BL_GET_REG_BITS_VAL(BL_RD_REG(I2S_BASE, I2S_FIFO_CONFIG_1), I2S_RX_FIFO_CNT)) {
+    };
+
+    return BL_RD_REG(I2S_BASE, I2S_FIFO_RDATA);
+}
+
+/****************************************************************************/ /**
+ * @brief  I2S write data
+ *
+ * @param  data: write data
+ *
+ * @return None
+ *
+*******************************************************************************/
+void I2S_Write(uint32_t data)
+{
+    while (0 == BL_GET_REG_BITS_VAL(BL_RD_REG(I2S_BASE, I2S_FIFO_CONFIG_1), I2S_TX_FIFO_CNT)) {
+    };
+
+    BL_WR_REG(I2S_BASE, I2S_FIFO_WDATA, data);
+}
+
+/****************************************************************************/ /**
+ * @brief  I2S set mute
+ *
+ * @param  enabled: mute enabled or not
+ *
+ * @return None
+ *
+*******************************************************************************/
+void I2S_Mute(BL_Fun_Type enabled)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(I2S_BASE, I2S_CONFIG);
+
+    if (enabled ? 1 : 0) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_MUTE_MODE);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_MUTE_MODE);
+    }
+
+    BL_WR_REG(I2S_BASE, I2S_CONFIG, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  I2S set 24-bit data align mode in fifo
+ *
+ * @param  justType: Align mode
+ *
+ * @return None
+ *
+*******************************************************************************/
+void I2S_SetFifoJustified(I2S_FIFO_24_Justified_Type justType)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_I2S_FIFO_24_JUSTIFIED_TYPE(justType));
+
+    tmpVal = BL_RD_REG(I2S_BASE, I2S_FIFO_CONFIG_0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FIFO_24B_LJ, justType);
+    BL_WR_REG(I2S_BASE, I2S_FIFO_CONFIG_0, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  I2S flush
+ *
+ * @param  None
+ *
+ * @return data count in TX FIFO
+ *
+*******************************************************************************/
+uint32_t I2S_GetTxFIFO_AvlCnt(void)
+{
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(I2S_BASE, I2S_FIFO_CONFIG_1), I2S_TX_FIFO_CNT);
+}
+
+/****************************************************************************/ /**
+ * @brief  I2S flush
+ *
+ * @param  None
+ *
+ * @return data count in RX FIFO
+ *
+*******************************************************************************/
+uint32_t I2S_GetRxFIFO_AvlCnt(void)
+{
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(I2S_BASE, I2S_FIFO_CONFIG_1), I2S_RX_FIFO_CNT);
+}
+
+/****************************************************************************/ /**
+ * @brief  I2S flush
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void I2S_Flush(void)
+{
+    while (I2S_TX_FIFO_SIZE != I2S_GetTxFIFO_AvlCnt())
+        ;
+}
+
+/*@} end of group I2S_Public_Functions */
+
+/*@} end of group I2S */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_ir.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_ir.c
new file mode 100644
index 00000000..681f8a1c
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_ir.c
@@ -0,0 +1,1156 @@
+/**
+  ******************************************************************************
+  * @file    bl702_ir.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_ir.h"
+#include "bl702_glb.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  IR
+ *  @{
+ */
+
+/** @defgroup  IR_Private_Macros
+ *  @{
+ */
+#define NEC_HEAD_H_MIN          17000
+#define NEC_HEAD_H_MAX          19000
+#define NEC_HEAD_L_MIN          8400
+#define NEC_HEAD_L_MAX          9600
+#define NEC_BIT0_H_MIN          525
+#define NEC_BIT0_H_MAX          1725
+#define RC5_ONE_PLUSE_MIN       1175
+#define RC5_ONE_PLUSE_MAX       2375
+#define RC5_TWO_PLUSE_MIN       2955
+#define RC5_TWO_PLUSE_MAX       4155
+#define IR_TX_INT_TIMEOUT_COUNT (100 * 160 * 1000)
+#define IR_RX_INT_TIMEOUT_COUNT (100 * 160 * 1000)
+
+/*@} end of group IR_Private_Macros */
+
+/** @defgroup  IR_Private_Types
+ *  @{
+ */
+
+/*@} end of group IR_Private_Types */
+
+/** @defgroup  IR_Private_Variables
+ *  @{
+ */
+static intCallback_Type *irIntCbfArra[IR_INT_ALL] = { NULL, NULL };
+
+/*@} end of group IR_Private_Variables */
+
+/** @defgroup  IR_Global_Variables
+ *  @{
+ */
+
+/*@} end of group IR_Global_Variables */
+
+/** @defgroup  IR_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group IR_Private_Fun_Declaration */
+
+/** @defgroup  IR_Private_Functions
+ *  @{
+ */
+
+/*@} end of group IR_Private_Functions */
+
+/** @defgroup  IR_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  IR RX IRQ handler function
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void IRRX_IRQHandler(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS);
+
+    if (BL_IS_REG_BIT_SET(tmpVal, IRRX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRRX_END_MASK)) {
+        BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR));
+
+        if (irIntCbfArra[IR_INT_RX] != NULL) {
+            irIntCbfArra[IR_INT_RX]();
+        }
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  IR TX IRQ handler function
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void IRTX_IRQHandler(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS);
+
+    if (BL_IS_REG_BIT_SET(tmpVal, IRTX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRTX_END_MASK)) {
+        BL_WR_REG(IR_BASE, IRTX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_END_CLR));
+
+        if (irIntCbfArra[IR_INT_TX] != NULL) {
+            irIntCbfArra[IR_INT_TX]();
+        }
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  IR tx initialization function
+ *
+ * @param  irTxCfg: IR tx configuration structure pointer
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type IR_TxInit(IR_TxCfg_Type *irTxCfg)
+{
+    uint32_t tmpVal;
+
+    /* Disable clock gate */
+    GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_IRR);
+
+    tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG);
+    /* Set data bit */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_DATA_NUM, irTxCfg->dataBits - 1);
+    /* Set tail pulse */
+    ENABLE == irTxCfg->tailPulseInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_TAIL_HL_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_TAIL_HL_INV));
+    ENABLE == irTxCfg->tailPulse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_TAIL_EN)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_TAIL_EN));
+    /* Set head pulse */
+    ENABLE == irTxCfg->headPulseInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_HEAD_HL_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_HEAD_HL_INV));
+    ENABLE == irTxCfg->headPulse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_HEAD_EN)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_HEAD_EN));
+    /* Enable or disable logic 1 and 0 pulse inverse */
+    ENABLE == irTxCfg->logic1PulseInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_LOGIC1_HL_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_LOGIC1_HL_INV));
+    ENABLE == irTxCfg->logic0PulseInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_LOGIC0_HL_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_LOGIC0_HL_INV));
+    /* Enable or disable data pulse */
+    ENABLE == irTxCfg->dataPulse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_DATA_EN)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_DATA_EN));
+    /* Enable or disable output modulation */
+    ENABLE == irTxCfg->outputModulation ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_MOD_EN)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_MOD_EN));
+    /* Enable or disable output inverse */
+    ENABLE == irTxCfg->outputInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_OUT_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_OUT_INV));
+
+    /* Write back */
+    BL_WR_REG(IR_BASE, IRTX_CONFIG, tmpVal);
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(IRTX_IRQn, IRTX_IRQHandler);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  IR tx pulse width configure function
+ *
+ * @param  irTxPulseWidthCfg: IR tx pulse width configuration structure pointer
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type IR_TxPulseWidthConfig(IR_TxPulseWidthCfg_Type *irTxPulseWidthCfg)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(IR_BASE, IRTX_PW);
+    /* Set logic 0 pulse phase 0 width */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC0_PH0_W, irTxPulseWidthCfg->logic0PulseWidth_0 - 1);
+    /* Set logic 0 pulse phase 1 width */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC0_PH1_W, irTxPulseWidthCfg->logic0PulseWidth_1 - 1);
+    /* Set logic 1 pulse phase 0 width */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC1_PH0_W, irTxPulseWidthCfg->logic1PulseWidth_0 - 1);
+    /* Set logic 1 pulse phase 1 width */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC1_PH1_W, irTxPulseWidthCfg->logic1PulseWidth_1 - 1);
+    /* Set head pulse phase 0 width */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_HEAD_PH0_W, irTxPulseWidthCfg->headPulseWidth_0 - 1);
+    /* Set head pulse phase 1 width */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_HEAD_PH1_W, irTxPulseWidthCfg->headPulseWidth_1 - 1);
+    /* Set tail pulse phase 0 width */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_TAIL_PH0_W, irTxPulseWidthCfg->tailPulseWidth_0 - 1);
+    /* Set tail pulse phase 1 width */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_TAIL_PH1_W, irTxPulseWidthCfg->tailPulseWidth_1 - 1);
+    BL_WR_REG(IR_BASE, IRTX_PW, tmpVal);
+
+    tmpVal = BL_RD_REG(IR_BASE, IRTX_PULSE_WIDTH);
+    /* Set modulation phase 0 width */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_MOD_PH0_W, irTxPulseWidthCfg->moduWidth_0 - 1);
+    /* Set modulation phase 1 width */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_MOD_PH1_W, irTxPulseWidthCfg->moduWidth_1 - 1);
+    /* Set pulse width unit */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_PW_UNIT, irTxPulseWidthCfg->pulseWidthUnit - 1);
+    BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  IR tx software mode pulse width(multiples of pulse width unit) configure function
+ *
+ * @param  irTxSWMPulseWidthCfg: IR tx software mode pulse width configuration structure pointer
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type IR_TxSWMPulseWidthConfig(IR_TxSWMPulseWidthCfg_Type *irTxSWMPulseWidthCfg)
+{
+    /* Set swm pulse width,multiples of pulse width unit */
+    BL_WR_REG(IR_BASE, IRTX_SWM_PW_0, irTxSWMPulseWidthCfg->swmData0);
+    BL_WR_REG(IR_BASE, IRTX_SWM_PW_1, irTxSWMPulseWidthCfg->swmData1);
+    BL_WR_REG(IR_BASE, IRTX_SWM_PW_2, irTxSWMPulseWidthCfg->swmData2);
+    BL_WR_REG(IR_BASE, IRTX_SWM_PW_3, irTxSWMPulseWidthCfg->swmData3);
+    BL_WR_REG(IR_BASE, IRTX_SWM_PW_4, irTxSWMPulseWidthCfg->swmData4);
+    BL_WR_REG(IR_BASE, IRTX_SWM_PW_5, irTxSWMPulseWidthCfg->swmData5);
+    BL_WR_REG(IR_BASE, IRTX_SWM_PW_6, irTxSWMPulseWidthCfg->swmData6);
+    BL_WR_REG(IR_BASE, IRTX_SWM_PW_7, irTxSWMPulseWidthCfg->swmData7);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  IR rx initialization function
+ *
+ * @param  irRxCfg: IR rx configuration structure pointer
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type IR_RxInit(IR_RxCfg_Type *irRxCfg)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_IR_RXMODE_TYPE(irRxCfg->rxMode));
+
+    /* Disable clock gate */
+    GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_IRR);
+
+    tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);
+
+    /* Set rx mode */
+    switch (irRxCfg->rxMode) {
+        case IR_RX_NEC:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x0);
+            break;
+
+        case IR_RX_RC5:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x1);
+            break;
+
+        case IR_RX_SWM:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x2);
+            break;
+
+        default:
+            break;
+    }
+
+    /* Enable or disable input inverse */
+    ENABLE == irRxCfg->inputInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_IN_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_IN_INV));
+    /* Enable or disable rx input de-glitch function */
+    ENABLE == irRxCfg->rxDeglitch ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_DEG_EN)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_DEG_EN));
+    /* Set de-glitch function cycle count */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_DEG_CNT, irRxCfg->DeglitchCnt);
+    /* Write back */
+    BL_WR_REG(IR_BASE, IRRX_CONFIG, tmpVal);
+
+    tmpVal = BL_RD_REG(IR_BASE, IRRX_PW_CONFIG);
+    /* Set pulse width threshold to trigger end condition */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_END_TH, irRxCfg->endThreshold - 1);
+    /* Set pulse width threshold for logic0/1 detection */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_DATA_TH, irRxCfg->dataThreshold - 1);
+    /* Write back */
+    BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, tmpVal);
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(IRRX_IRQn, IRRX_IRQHandler);
+#endif
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  IR set default value of all registers function
+ *
+ * @param  None
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type IR_DeInit(void)
+{
+    GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_IRR);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  IR enable function
+ *
+ * @param  direct: IR direction type
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type IR_Enable(IR_Direction_Type direct)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_IR_DIRECTION_TYPE(direct));
+
+    if (direct == IR_TX || direct == IR_TXRX) {
+        /* Enable ir tx unit */
+        tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG);
+        BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_EN));
+    }
+
+    if (direct == IR_RX || direct == IR_TXRX) {
+        /* Enable ir rx unit */
+        tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);
+        BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_EN));
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  IR disable function
+ *
+ * @param  direct: IR direction type
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type IR_Disable(IR_Direction_Type direct)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_IR_DIRECTION_TYPE(direct));
+
+    if (direct == IR_TX || direct == IR_TXRX) {
+        /* Disable ir tx unit */
+        tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG);
+        BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_EN));
+    }
+
+    if (direct == IR_RX || direct == IR_TXRX) {
+        /* Disable ir rx unit */
+        tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);
+        BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_EN));
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  IR tx software mode enable or disable function
+ *
+ * @param  txSWM: Enable or disable
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type IR_TxSWM(BL_Fun_Type txSWM)
+{
+    uint32_t tmpVal;
+
+    /* Enable or disable tx swm */
+    tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG);
+
+    if (ENABLE == txSWM) {
+        BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_SWM_EN));
+    } else {
+        BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_SWM_EN));
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  IR clear rx fifo function
+ *
+ * @param  None
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type IR_RxFIFOClear(void)
+{
+    uint32_t tmpVal;
+
+    /* Clear rx fifo */
+    tmpVal = BL_RD_REG(IR_BASE, IRRX_SWM_FIFO_CONFIG_0);
+    BL_WR_REG(IR_BASE, IRRX_SWM_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, IR_RX_FIFO_CLR));
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  IR send data function
+ *
+ * @param  irWord: IR tx data word 0 or 1
+ * @param  data: data to send
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type IR_SendData(IR_Word_Type irWord, uint32_t data)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_IR_WORD_TYPE(irWord));
+
+    /* Write word 0 or word 1 */
+    if (IR_WORD_0 == irWord) {
+        BL_WR_REG(IR_BASE, IRTX_DATA_WORD0, data);
+    } else {
+        BL_WR_REG(IR_BASE, IRTX_DATA_WORD1, data);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  IR software mode send pulse width data function
+ *
+ * @param  data: data to send
+ * @param  length: Length of send buffer
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type IR_SWMSendData(uint16_t *data, uint8_t length)
+{
+    uint8_t i = 0, j = 0;
+    uint16_t minData = data[0];
+    uint32_t tmpVal;
+    uint32_t pwVal = 0;
+    uint32_t count = (length + 7) / 8;
+
+    /* Search for min value */
+    for (i = 1; i < length; i++) {
+        if (minData > data[i] && data[i] != 0) {
+            minData = data[i];
+        }
+    }
+
+    /* Set pulse width unit */
+    tmpVal = BL_RD_REG(IR_BASE, IRTX_PULSE_WIDTH);
+    BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_PW_UNIT, minData));
+
+    /* Set tx SWM pulse width data as multiples of pulse width unit */
+    for (i = 0; i < count; i++) {
+        pwVal = 0;
+
+        if (i < count - 1) {
+            for (j = 0; j < 8; j++) {
+                tmpVal = ((2 * data[j + i * 8] + minData) / (2 * minData) - 1) & 0xf;
+                pwVal |= tmpVal << (4 * j);
+            }
+
+            *(volatile uint32_t *)(IR_BASE + IRTX_SWM_PW_0_OFFSET + i * 4) = pwVal;
+        } else {
+            for (j = 0; j < length % 8; j++) {
+                tmpVal = ((2 * data[j + i * 8] + minData) / (2 * minData) - 1) & 0xf;
+                pwVal |= tmpVal << (4 * j);
+            }
+
+            *(volatile uint32_t *)(IR_BASE + IRTX_SWM_PW_0_OFFSET + i * 4) = pwVal;
+        }
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  IR send command function
+ *
+ * @param  word1: IR send data word 1
+ * @param  word0: IR send data word 0
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type IR_SendCommand(uint32_t word1, uint32_t word0)
+{
+    uint32_t timeoutCnt = IR_TX_INT_TIMEOUT_COUNT;
+
+    /* Write data */
+    IR_SendData(IR_WORD_1, word1);
+    IR_SendData(IR_WORD_0, word0);
+
+    /* Mask tx interrupt */
+    IR_IntMask(IR_INT_TX, MASK);
+
+    /* Clear tx interrupt */
+    IR_ClrIntStatus(IR_INT_TX);
+
+    /* Enable ir tx */
+    IR_Enable(IR_TX);
+
+    /* Wait for tx interrupt */
+    while (SET != IR_GetIntStatus(IR_INT_TX)) {
+        timeoutCnt--;
+
+        if (timeoutCnt == 0) {
+            IR_Disable(IR_TX);
+
+            return TIMEOUT;
+        }
+    }
+
+    /* Disable ir tx */
+    IR_Disable(IR_TX);
+
+    /* Clear tx interrupt */
+    IR_ClrIntStatus(IR_INT_TX);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  IR send command in software mode function
+ *
+ * @param  data: IR fifo data to send
+ * @param  length: Length of data
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type IR_SWMSendCommand(uint16_t *data, uint8_t length)
+{
+    uint32_t timeoutCnt = IR_TX_INT_TIMEOUT_COUNT;
+
+    /* Write fifo */
+    IR_SWMSendData(data, length);
+
+    /* Mask tx interrupt */
+    IR_IntMask(IR_INT_TX, MASK);
+
+    /* Clear tx interrupt */
+    IR_ClrIntStatus(IR_INT_TX);
+
+    /* Enable ir tx */
+    IR_Enable(IR_TX);
+
+    /* Wait for tx interrupt */
+    while (SET != IR_GetIntStatus(IR_INT_TX)) {
+        timeoutCnt--;
+
+        if (timeoutCnt == 0) {
+            IR_Disable(IR_TX);
+
+            return TIMEOUT;
+        }
+    }
+
+    /* Disable ir tx */
+    IR_Disable(IR_TX);
+
+    /* Clear tx interrupt */
+    IR_ClrIntStatus(IR_INT_TX);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  IR send in NEC protocol
+ *
+ * @param  address: Address
+ * @param  command: Command
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type IR_SendNEC(uint8_t address, uint8_t command)
+{
+    uint32_t tmpVal = ((~command & 0xff) << 24) + (command << 16) + ((~address & 0xff) << 8) + address;
+
+    IR_SendCommand(0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  IR interrupt mask or unmask function
+ *
+ * @param  intType: IR interrupt type
+ * @param  intMask: Mask or unmask
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type IR_IntMask(IR_INT_Type intType, BL_Mask_Type intMask)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_IR_INT_TYPE(intType));
+
+    if (intType == IR_INT_TX || intType == IR_INT_ALL) {
+        /* Mask or unmask tx interrupt */
+        tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS);
+        BL_WR_REG(IR_BASE, IRTX_INT_STS, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_END_MASK, intMask));
+    }
+
+    if (intType == IR_INT_RX || intType == IR_INT_ALL) {
+        /* Mask or unmask rx interrupt */
+        tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS);
+        BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_END_MASK, intMask));
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Clear ir interrupt function
+ *
+ * @param  intType: IR interrupt type
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type IR_ClrIntStatus(IR_INT_Type intType)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_IR_INT_TYPE(intType));
+
+    if (intType == IR_INT_TX || intType == IR_INT_ALL) {
+        /* Clear tx interrupt */
+        tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS);
+        BL_WR_REG(IR_BASE, IRTX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_END_CLR));
+    }
+
+    if (intType == IR_INT_RX || intType == IR_INT_ALL) {
+        /* Clear rx interrupt */
+        tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS);
+        BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR));
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  IR install interrupt callback function
+ *
+ * @param  intType: IR interrupt type
+ * @param  cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type IR_Int_Callback_Install(IR_INT_Type intType, intCallback_Type *cbFun)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_IR_INT_TYPE(intType));
+
+    irIntCbfArra[intType] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  IR get interrupt status function
+ *
+ * @param  intType: IR int type
+ *
+ * @return IR tx or rx interrupt status
+ *
+*******************************************************************************/
+BL_Sts_Type IR_GetIntStatus(IR_INT_Type intType)
+{
+    uint32_t tmpVal = 0;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_IR_INT_TYPE(intType));
+
+    /* Read tx or rx interrupt status */
+    if (IR_INT_TX == intType) {
+        tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS);
+        tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IRTX_END_INT);
+    } else if (IR_INT_RX == intType) {
+        tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS);
+        tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IRRX_END_INT);
+    }
+
+    if (tmpVal) {
+        return SET;
+    } else {
+        return RESET;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  IR get rx fifo underflow or overflow status function
+ *
+ * @param  fifoSts: IR fifo status type
+ *
+ * @return IR rx fifo status
+ *
+*******************************************************************************/
+BL_Sts_Type IR_GetRxFIFOStatus(IR_FifoStatus_Type fifoSts)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_IR_FIFOSTATUS_TYPE(fifoSts));
+
+    /* Read rx fifo status */
+    tmpVal = BL_RD_REG(IR_BASE, IRRX_SWM_FIFO_CONFIG_0);
+
+    if (fifoSts == IR_RX_FIFO_UNDERFLOW) {
+        tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_RX_FIFO_UNDERFLOW);
+    } else {
+        tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_RX_FIFO_OVERFLOW);
+    }
+
+    if (tmpVal) {
+        return SET;
+    } else {
+        return RESET;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  IR receive data function
+ *
+ * @param  irWord: IR rx data word 0 or 1
+ *
+ * @return Data received
+ *
+*******************************************************************************/
+uint32_t IR_ReceiveData(IR_Word_Type irWord)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_IR_WORD_TYPE(irWord));
+
+    /* Read word 0 or word 1 */
+    if (IR_WORD_0 == irWord) {
+        tmpVal = BL_RD_REG(IR_BASE, IRRX_DATA_WORD0);
+    } else {
+        tmpVal = BL_RD_REG(IR_BASE, IRRX_DATA_WORD1);
+    }
+
+    return tmpVal;
+}
+
+/****************************************************************************/ /**
+ * @brief  IR software mode receive pulse width data function
+ *
+ * @param  data: Data received
+ * @param  length: Max length of receive buffer
+ *
+ * @return Length of datas received
+ *
+*******************************************************************************/
+uint8_t IR_SWMReceiveData(uint16_t *data, uint8_t length)
+{
+    uint8_t rxLen = 0;
+
+    while (rxLen < length && IR_GetRxFIFOCount() > 0) {
+        /* Read data */
+        data[rxLen++] = BL_RD_REG(IR_BASE, IRRX_SWM_FIFO_RDATA) & 0xffff;
+    }
+
+    return rxLen;
+}
+
+/****************************************************************************/ /**
+ * @brief  IR receive in NEC protocol
+ *
+ * @param  address: Address
+ * @param  command: Command
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type IR_ReceiveNEC(uint8_t *address, uint8_t *command)
+{
+    uint32_t tmpVal = IR_ReceiveData(IR_WORD_0);
+
+    *address = tmpVal & 0xff;
+    *command = (tmpVal >> 16) & 0xff;
+
+    if ((~(*address) & 0xff) != ((tmpVal >> 8) & 0xff) || (~(*command) & 0xff) != ((tmpVal >> 24) & 0xff)) {
+        return ERROR;
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  IR get rx data bit count function
+ *
+ * @param  None
+ *
+ * @return IR rx data bit count
+ *
+*******************************************************************************/
+uint8_t IR_GetRxDataBitCount(void)
+{
+    uint32_t tmpVal;
+
+    /* Read rx data bit count */
+    tmpVal = BL_RD_REG(IR_BASE, IRRX_DATA_COUNT);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_STS_IRRX_DATA_CNT);
+
+    return tmpVal;
+}
+
+/****************************************************************************/ /**
+ * @brief  IR get rx fifo count function
+ *
+ * @param  None
+ *
+ * @return IR rx fifo available count
+ *
+*******************************************************************************/
+uint8_t IR_GetRxFIFOCount(void)
+{
+    uint32_t tmpVal;
+
+    /* Read rx fifo count */
+    tmpVal = BL_RD_REG(IR_BASE, IRRX_SWM_FIFO_CONFIG_0);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_RX_FIFO_CNT);
+
+    return tmpVal;
+}
+
+/****************************************************************************/ /**
+ * @brief  IR learning to set rx and tx mode function
+ *
+ * @param  data: Buffer to save data
+ * @param  length: Length of data
+ *
+ * @return Protocol type
+ *
+*******************************************************************************/
+IR_RxMode_Type IR_LearnToInit(uint32_t *data, uint8_t *length)
+{
+    uint32_t tmpVal;
+    uint32_t timeoutCnt = IR_RX_INT_TIMEOUT_COUNT;
+
+    /* Disable clock gate */
+    GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_IRR);
+
+    /* Disable rx,set rx in software mode and enable rx input inverse */
+    tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_EN);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x2);
+    tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_IN_INV);
+    BL_WR_REG(IR_BASE, IRRX_CONFIG, tmpVal);
+    /* Set pulse width threshold to trigger end condition */
+    tmpVal = BL_RD_REG(IR_BASE, IRRX_PW_CONFIG);
+    BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_END_TH, 19999));
+
+    /* Clear and mask rx interrupt */
+    tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS);
+    tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_MASK);
+    BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR));
+
+    /* Enable rx */
+    tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);
+    BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_EN));
+
+    /* Wait for rx interrupt */
+    while (SET != IR_GetIntStatus(IR_INT_RX)) {
+        timeoutCnt--;
+
+        if (timeoutCnt == 0) {
+            IR_Disable(IR_RX);
+
+            return IR_RX_SWM;
+        }
+    }
+
+    /* Disable rx */
+    tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);
+    BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_EN));
+
+    /* Clear rx interrupt */
+    tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS);
+    BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR));
+
+    /*Receive data */
+    *length = IR_GetRxFIFOCount();
+    *length = IR_SWMReceiveData((uint16_t *)data, *length);
+
+    /* Judge protocol type */
+    if (NEC_HEAD_H_MIN < (data[0] & 0xffff) && (data[0] & 0xffff) < NEC_HEAD_H_MAX && NEC_HEAD_L_MIN < (data[0] >> 16) && (data[0] >> 16) < NEC_HEAD_L_MAX && NEC_BIT0_H_MIN < (data[1] & 0xffff) && (data[1] & 0xffff) < NEC_BIT0_H_MAX) {
+        /* Set rx in NEC mode */
+        tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);
+        BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x0));
+        /* Set pulse width threshold to trigger end condition and pulse width threshold for logic0/1 detection */
+        BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, 0x23270d47);
+        /* Set tx in NEC mode */
+        /* Tx configure */
+        BL_WR_REG(IR_BASE, IRTX_CONFIG, 0x1f514);
+        /* Set logic 0,logic 1,head and tail pulse width */
+        BL_WR_REG(IR_BASE, IRTX_PW, 0x7f2000);
+        /* Set modulation phase width and pulse width unit */
+        BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, 0x22110464);
+
+        return IR_RX_NEC;
+    } else if (RC5_ONE_PLUSE_MIN < (data[0] & 0xffff) && (data[0] & 0xffff) < RC5_ONE_PLUSE_MAX && ((RC5_ONE_PLUSE_MIN < (data[0] >> 16) && (data[0] >> 16) < RC5_ONE_PLUSE_MAX) || (RC5_TWO_PLUSE_MIN < (data[0] >> 16) && (data[0] >> 16) < RC5_TWO_PLUSE_MAX)) &&
+               ((RC5_ONE_PLUSE_MIN < (data[1] & 0xffff) && (data[1] & 0xffff) < RC5_ONE_PLUSE_MAX) || (RC5_TWO_PLUSE_MIN < (data[1] & 0xffff) && (data[1] & 0xffff) < RC5_TWO_PLUSE_MAX))) {
+        /* Set rx in RC-5 mode */
+        tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);
+        BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x1));
+        /* Set pulse width threshold to trigger end condition and pulse width threshold for logic0/1 detection */
+        BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, 0x13870a6a);
+        /* Set tx in RC-5 mode */
+        /* Tx configure */
+        BL_WR_REG(IR_BASE, IRTX_CONFIG, 0xc134);
+        /* Set logic 0,logic 1,head and tail pulse width */
+        BL_WR_REG(IR_BASE, IRTX_PW, 0);
+        /* Set modulation phase width and pulse width unit */
+        BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, 0x221106f1);
+
+        return IR_RX_RC5;
+    } else if ((data[0] >> 16) != 0) {
+        /* Set tx in software mode */
+        /* Tx configure */
+        BL_WR_REG(IR_BASE, IRTX_CONFIG, *length << 12 | 0xc);
+        /* Set modulation phase width */
+        BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, 0x22110000);
+
+        return IR_RX_SWM;
+    } else {
+        tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);
+        tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE);
+
+        if (tmpVal == 0) {
+            return IR_RX_NEC;
+        } else if (tmpVal == 1) {
+            return IR_RX_RC5;
+        } else {
+            return IR_RX_SWM;
+        }
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  IR receive data according to mode which is learned function
+ *
+ * @param  mode: Protocol type
+ * @param  data: Buffer to save data
+ *
+ * @return Length of data
+ *
+*******************************************************************************/
+uint8_t IR_LearnToReceive(IR_RxMode_Type mode, uint32_t *data)
+{
+    uint8_t length = 0;
+    uint32_t timeoutCnt = IR_RX_INT_TIMEOUT_COUNT;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_IR_RXMODE_TYPE(mode));
+
+    /* Disable ir rx */
+    IR_Disable(IR_RX);
+
+    /* Clear and mask rx interrupt */
+    IR_ClrIntStatus(IR_INT_RX);
+    IR_IntMask(IR_INT_RX, MASK);
+
+    /* Enable ir rx */
+    IR_Enable(IR_RX);
+
+    /* Wait for rx interrupt */
+    while (SET != IR_GetIntStatus(IR_INT_RX)) {
+        timeoutCnt--;
+
+        if (timeoutCnt == 0) {
+            IR_Disable(IR_RX);
+
+            return TIMEOUT;
+        }
+    }
+
+    /* Disable ir rx */
+    IR_Disable(IR_RX);
+
+    /* Clear rx interrupt */
+    IR_ClrIntStatus(IR_INT_RX);
+
+    /* Receive data according to mode */
+    if (mode == IR_RX_NEC || mode == IR_RX_RC5) {
+        /* Get data bit count */
+        length = IR_GetRxDataBitCount();
+        data[0] = IR_ReceiveData(IR_WORD_0);
+    } else {
+        /* Get fifo count */
+        length = IR_GetRxFIFOCount();
+        length = IR_SWMReceiveData((uint16_t *)data, length);
+    }
+
+    return length;
+}
+
+/****************************************************************************/ /**
+ * @brief  IR send data according to mode which is learned function
+ *
+ * @param  mode: Protocol type
+ * @param  data: Buffer of data to send
+ * @param  length: Length of data
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type IR_LearnToSend(IR_RxMode_Type mode, uint32_t *data, uint8_t length)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_IR_RXMODE_TYPE(mode));
+
+    /* Set send length */
+    tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_DATA_NUM, length - 1);
+    BL_WR_REG(IR_BASE, IRTX_CONFIG, tmpVal);
+
+    if (mode == IR_RX_NEC || mode == IR_RX_RC5) {
+        IR_SendCommand(0, data[0]);
+    } else {
+        IR_SWMSendCommand((uint16_t *)data, length);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  IR init to control led function
+ *
+ * @param  clk: Clock source
+ * @param  div: Clock division(1~64)
+ * @param  unit: Pulse width unit(multiples of clock pulse width, 1~4096)
+ * @param  code0H: code 0 high level time(multiples of pulse width unit, 1~16)
+ * @param  code0L: code 0 low level time(multiples of pulse width unit, 1~16)
+ * @param  code1H: code 1 high level time(multiples of pulse width unit, 1~16)
+ * @param  code1L: code 1 low level time(multiples of pulse width unit, 1~16)
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type IR_LEDInit(HBN_XCLK_CLK_Type clk, uint8_t div, uint8_t unit, uint8_t code0H, uint8_t code0L, uint8_t code1H, uint8_t code1L)
+{
+    IR_TxCfg_Type txCfg = {
+        24,      /* 24-bit data */
+        DISABLE, /* Disable signal of tail pulse inverse */
+        DISABLE, /* Disable signal of tail pulse */
+        DISABLE, /* Disable signal of head pulse inverse */
+        DISABLE, /* Disable signal of head pulse */
+        DISABLE, /* Disable signal of logic 1 pulse inverse */
+        DISABLE, /* Disable signal of logic 0 pulse inverse */
+        ENABLE,  /* Enable signal of data pulse */
+        DISABLE, /* Disable signal of output modulation */
+        ENABLE   /* Enable signal of output inverse */
+    };
+
+    IR_TxPulseWidthCfg_Type txPWCfg = {
+        code0L, /* Pulse width of logic 0 pulse phase 1 */
+        code0H, /* Pulse width of logic 0 pulse phase 0 */
+        code1L, /* Pulse width of logic 1 pulse phase 1 */
+        code1H, /* Pulse width of logic 1 pulse phase 0 */
+        1,      /* Pulse width of head pulse phase 1 */
+        1,      /* Pulse width of head pulse phase 0 */
+        1,      /* Pulse width of tail pulse phase 1 */
+        1,      /* Pulse width of tail pulse phase 0 */
+        1,      /* Modulation phase 1 width */
+        1,      /* Modulation phase 0 width */
+        unit    /* Pulse width unit */
+    };
+
+    HBN_Set_XCLK_CLK_Sel(clk);
+    GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, div - 1);
+
+    /* Disable ir before config */
+    IR_Disable(IR_TXRX);
+
+    /* IR tx init */
+    IR_TxInit(&txCfg);
+    IR_TxPulseWidthConfig(&txPWCfg);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  IR send 24-bit data to control led function
+ *
+ * @param  data: Data to send(24-bit)
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type IR_LEDSend(uint32_t data)
+{
+    /* Change MSB_first to LSB_first */
+    data = ((data >> 1) & 0x55555555) | ((data << 1) & 0xaaaaaaaa);
+    data = ((data >> 2) & 0x33333333) | ((data << 2) & 0xcccccccc);
+    data = ((data >> 4) & 0x0f0f0f0f) | ((data << 4) & 0xf0f0f0f0);
+    data = ((data >> 16) & 0xff) | (data & 0xff00) | ((data << 16) & 0xff0000);
+    IR_SendCommand(0, data);
+
+    return SUCCESS;
+}
+
+/*@} end of group IR_Public_Functions */
+
+/*@} end of group IR */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_kys.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_kys.c
new file mode 100644
index 00000000..45ca6a29
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_kys.c
@@ -0,0 +1,274 @@
+/**
+  ******************************************************************************
+  * @file    bl702_kys.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_kys.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  KYS
+ *  @{
+ */
+
+/** @defgroup  KYS_Private_Macros
+ *  @{
+ */
+
+/*@} end of group KYS_Private_Macros */
+
+/** @defgroup  KYS_Private_Types
+ *  @{
+ */
+
+/*@} end of group KYS_Private_Types */
+
+/** @defgroup  KYS_Private_Variables
+ *  @{
+ */
+static intCallback_Type *KYSIntCbfArra[1] = { NULL };
+
+/*@} end of group KYS_Private_Variables */
+
+/** @defgroup  KYS_Global_Variables
+ *  @{
+ */
+
+/*@} end of group KYS_Global_Variables */
+
+/** @defgroup  KYS_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group KYS_Private_Fun_Declaration */
+
+/** @defgroup  KYS_Private_Functions
+ *  @{
+ */
+
+/*@} end of group KYS_Private_Functions */
+
+/** @defgroup  KYS_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  KYS interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void KYS_IRQHandler(void)
+{
+    if (KYSIntCbfArra[0] != NULL) {
+        KYSIntCbfArra[0]();
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  KYS initialization function
+ *
+ * @param  kysCfg: KYS configuration structure pointer
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type KYS_Init(KYS_CFG_Type *kysCfg)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_CTRL);
+    /* Set col and row */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_COL_NUM, kysCfg->col - 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_ROW_NUM, kysCfg->row - 1);
+
+    /* Set idle duration between column scans */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_RC_EXT, kysCfg->idleDuration);
+
+    /* Enable or disable ghost key event detection */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_GHOST_EN, kysCfg->ghostEn);
+
+    /* Enable or disable deglitch function */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_DEG_EN, kysCfg->deglitchEn);
+
+    /* Set deglitch count */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_DEG_CNT, kysCfg->deglitchCnt);
+
+    /* Write back */
+    BL_WR_REG(KYS_BASE, KYS_KS_CTRL, tmpVal);
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(KYS_IRQn, KYS_IRQHandler);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable KYS
+ *
+ * @param  None
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type KYS_Enable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_CTRL);
+    BL_WR_REG(KYS_BASE, KYS_KS_CTRL, BL_SET_REG_BIT(tmpVal, KYS_KS_EN));
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable KYS
+ *
+ * @param  None
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type KYS_Disable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_CTRL);
+    BL_WR_REG(KYS_BASE, KYS_KS_CTRL, BL_CLR_REG_BIT(tmpVal, KYS_KS_EN));
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  KYS mask or unmask interrupt
+ *
+ * @param  intMask: KYS interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt )
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type KYS_IntMask(BL_Mask_Type intMask)
+{
+    if (MASK == intMask) {
+        BL_WR_REG(KYS_BASE, KYS_KS_INT_EN, 0);
+    } else {
+        BL_WR_REG(KYS_BASE, KYS_KS_INT_EN, 1);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  KYS clear interrupt
+ *
+ * @param  None
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type KYS_IntClear(void)
+{
+    BL_WR_REG(KYS_BASE, KYS_KEYCODE_CLR, 0xf);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Install KYS interrupt callback function
+ *
+ * @param  cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type KYS_Int_Callback_Install(intCallback_Type *cbFun)
+{
+    KYSIntCbfArra[0] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  KYS get interrupt status
+ *
+ * @param  None
+ *
+ * @return Status of interrupt
+ *
+*******************************************************************************/
+uint8_t KYS_GetIntStatus(void)
+{
+    return BL_RD_REG(KYS_BASE, KYS_KS_INT_STS) & 0xf;
+}
+
+/****************************************************************************/ /**
+ * @brief  KYS get keycode value
+ *
+ * @param  keycode: KYS keycode type
+ * @param  col: Col of key
+ * @param  row: Row of key
+ *
+ * @return Keycode value
+ *
+*******************************************************************************/
+uint8_t KYS_GetKeycode(KYS_Keycode_Type keycode, uint8_t *col, uint8_t *row)
+{
+    uint32_t tmpVal;
+    uint8_t keyValue;
+
+    /* Get keycode value */
+    keyValue = BL_RD_REG(KYS_BASE, KYS_KEYCODE_VALUE) >> (8 * keycode) & 0xff;
+
+    /* Get total row number of keyboard */
+    tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_CTRL);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, KYS_ROW_NUM);
+
+    /* Calculate col and row of the key */
+    *col = keyValue / (tmpVal + 1);
+    *row = keyValue % (tmpVal + 1);
+
+    return keyValue;
+}
+
+/*@} end of group KYS_Public_Functions */
+
+/*@} end of group KYS */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_l1c.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_l1c.c
new file mode 100644
index 00000000..303ebd13
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_l1c.c
@@ -0,0 +1,665 @@
+/**
+  ******************************************************************************
+  * @file    bl702_l1c.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_l1c.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  L1C
+ *  @{
+ */
+
+/** @defgroup  L1C_Private_Macros
+ *  @{
+ */
+
+/*@} end of group L1C_Private_Macros */
+
+/** @defgroup  L1C_Private_Types
+ *  @{
+ */
+
+/*@} end of group L1C_Private_Types */
+
+/** @defgroup  L1C_Private_Variables
+ *  @{
+ */
+static intCallback_Type *l1cBmxErrIntCbfArra[L1C_BMX_ERR_INT_ALL] = { NULL };
+static intCallback_Type *l1cBmxToIntCbfArra[L1C_BMX_TO_INT_ALL] = { NULL };
+
+/*@} end of group L1C_Private_Variables */
+
+/** @defgroup  L1C_Global_Variables
+ *  @{
+ */
+
+/*@} end of group L1C_Global_Variables */
+
+/** @defgroup  L1C_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group L1C_Private_Fun_Declaration */
+
+/** @defgroup  L1C_Private_Functions
+ *  @{
+ */
+
+/*@} end of group L1C_Private_Functions */
+
+/** @defgroup  L1C_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Enable cache
+ *
+ * @param  wayDisable: cache way disable config
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_Cache_Enable_Set(uint8_t wayDisable)
+{
+    L1C_Cache_Flush(wayDisable);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  L1C cache write set
+ *
+ * @param  wtEn: L1C write through enable
+ * @param  wbEn: L1C write back enable
+ * @param  waEn: L1C write allocate enable
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION L1C_Cache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+
+    if (wtEn) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WT_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WT_EN);
+    }
+
+    if (wbEn) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WB_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WB_EN);
+    }
+
+    if (waEn) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WA_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WA_EN);
+    }
+
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Flush cache
+ *
+ * @param  wayDisable: cache way disable config
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_Cache_Flush(uint8_t wayDisable)
+{
+    uint32_t tmpVal;
+    uint32_t cnt = 0;
+    uint8_t finWayDisable = 0;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
+    tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BYPASS);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WAY_DIS);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CNT_EN);
+    finWayDisable = BL_GET_REG_BITS_VAL(tmpVal, L1C_WAY_DIS);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    /*Set Tag RAM to zero */
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_INVALID_EN);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+    /* Left space for hardware change status*/
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+    tmpVal = BL_SET_REG_BIT(tmpVal, L1C_INVALID_EN);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+    /* Left space for hardware change status*/
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+
+    /* Polling for invalid done */
+    do {
+        BL702_Delay_US(1);
+        cnt++;
+        tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    } while (!BL_IS_REG_BIT_SET(tmpVal, L1C_INVALID_DONE) && cnt < 100);
+
+    /* data flush */
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_FLUSH_EN);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+    /* Left space for hardware change status*/
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+    tmpVal = BL_SET_REG_BIT(tmpVal, L1C_FLUSH_EN);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+    /* Left space for hardware change status*/
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+
+    /* Polling for flush done */
+    do {
+        BL702_Delay_US(1);
+        cnt++;
+        tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    } while (!BL_IS_REG_BIT_SET(tmpVal, L1C_FLUSH_DONE) && cnt < 100);
+
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_FLUSH_EN);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BYPASS);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BYPASS);
+    tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CNT_EN);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    if (wayDisable != 0xff) {
+        finWayDisable = wayDisable;
+    }
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WAY_DIS);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    tmpVal |= (finWayDisable << L1C_WAY_DIS_POS);
+
+    /* If way disable is 0x0f, cacheable can't be set */
+    if (finWayDisable != 0x0f) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
+    }
+
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Flush cache external api
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION L1C_Cache_Flush_Ext(void)
+{
+    uint32_t tmpVal;
+
+    /* Disable early respone */
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    L1C_Cache_Flush((tmpVal >> L1C_WAY_DIS_POS) & 0xf);
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get cache hit count
+ *
+ * @param  hitCountLow: hit count low 32 bits pointer
+ * @param  hitCountHigh: hit count high 32 bits pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION L1C_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh)
+{
+    *hitCountLow = BL_RD_REG(L1C_BASE, L1C_HIT_CNT_LSB);
+    *hitCountHigh = BL_RD_REG(L1C_BASE, L1C_HIT_CNT_MSB);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Get cache miss count
+ *
+ * @param  None
+ *
+ * @return Cache miss count
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+uint32_t ATTR_TCM_SECTION L1C_Cache_Miss_Count_Get(void)
+{
+    return BL_RD_REG(L1C_BASE, L1C_MISS_CNT);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Disable read from flash or psram with cache
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION L1C_Cache_Read_Disable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  wrap set
+ *
+ * @param  wrap: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_Set_Wrap(BL_Fun_Type wrap)
+{
+    uint32_t tmpVal = 0;
+    uint8_t cacheEn = 0;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    cacheEn = BL_IS_REG_BIT_SET(L1C_BASE, L1C_CACHEABLE);
+
+    if (cacheEn != 0) {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
+        BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+    }
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+
+    if (wrap == ENABLE) {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WRAP_DIS);
+    } else {
+        tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WRAP_DIS);
+    }
+
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    if (cacheEn != 0) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE);
+        BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  cache way disable set
+ *
+ * @param  disableVal: cache way disable value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_Set_Way_Disable(uint8_t disableVal)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_WAY_DIS, disableVal);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    if (disableVal != 0x0f) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
+    }
+
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set for ROM 2T access if CPU freq >120MHz
+ *
+ * @param  enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_IROM_2T_Access_Set(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, L1C_IROM_2T_ACCESS);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_IROM_2T_ACCESS);
+    }
+
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX init
+ *
+ * @param  l1cBmxCfg: L1C BMX config
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type L1C_BMX_Init(L1C_BMX_Cfg_Type *l1cBmxCfg)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((l1cBmxCfg->timeoutEn) <= 0xF);
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_TIMEOUT_EN, l1cBmxCfg->timeoutEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_EN, l1cBmxCfg->errEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_ARB_MODE, l1cBmxCfg->arbMod);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(L1C_BMX_ERR_IRQn, L1C_BMX_ERR_IRQHandler);
+    Interrupt_Handler_Register(L1C_BMX_TO_IRQn, L1C_BMX_TO_IRQHandler);
+#endif
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX address monitor enable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type L1C_BMX_Addr_Monitor_Enable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BMX_ERR_ADDR_DIS);
+    BL_WR_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX address monitor disable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type L1C_BMX_Addr_Monitor_Disable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN);
+    tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BMX_ERR_ADDR_DIS);
+    BL_WR_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX bus error response enable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type L1C_BMX_BusErrResponse_Enable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BMX_ERR_EN);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX bus error response disable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type L1C_BMX_BusErrResponse_Disable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BMX_ERR_EN);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get L1C BMX error status
+ *
+ * @param  errType: L1C BMX error status type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type L1C_BMX_Get_Status(L1C_BMX_BUS_ERR_Type errType)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_L1C_BMX_BUS_ERR_TYPE(errType));
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN);
+
+    if (errType == L1C_BMX_BUS_ERR_TRUSTZONE_DECODE) {
+        return BL_GET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_TZ) ? SET : RESET;
+    } else {
+        return BL_GET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_DEC) ? SET : RESET;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Get L1C BMX error address
+ *
+ * @param  None
+ *
+ * @return NP L1C BMX error address
+ *
+*******************************************************************************/
+uint32_t L1C_BMX_Get_Err_Addr(void)
+{
+    return BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR);
+}
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX error interrupt callback install
+ *
+ * @param  intType: L1C BMX error interrupt type
+ * @param  cbFun: callback
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type L1C_BMX_ERR_INT_Callback_Install(L1C_BMX_ERR_INT_Type intType, intCallback_Type *cbFun)
+{
+    CHECK_PARAM(IS_L1C_BMX_ERR_INT_TYPE(intType));
+
+    l1cBmxErrIntCbfArra[intType] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX ERR interrupt IRQ handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void L1C_BMX_ERR_IRQHandler(void)
+{
+    L1C_BMX_ERR_INT_Type intType;
+
+    for (intType = L1C_BMX_ERR_INT_ERR; intType < L1C_BMX_ERR_INT_ALL; intType++) {
+        if (l1cBmxErrIntCbfArra[intType] != NULL) {
+            l1cBmxErrIntCbfArra[intType]();
+        }
+    }
+
+    while (1) {
+        //MSG("L1C_BMX_ERR_IRQHandler\r\n");
+        BL702_Delay_MS(1000);
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX timeout interrupt callback install
+ *
+ * @param  intType: L1C BMX timeout interrupt type
+ * @param  cbFun: callback
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type L1C_BMX_TIMEOUT_INT_Callback_Install(L1C_BMX_TO_INT_Type intType, intCallback_Type *cbFun)
+{
+    CHECK_PARAM(IS_L1C_BMX_TO_INT_TYPE(intType));
+
+    l1cBmxToIntCbfArra[intType] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX Time Out interrupt IRQ handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void L1C_BMX_TO_IRQHandler(void)
+{
+    L1C_BMX_TO_INT_Type intType;
+
+    for (intType = L1C_BMX_TO_INT_TIMEOUT; intType < L1C_BMX_TO_INT_ALL; intType++) {
+        if (l1cBmxToIntCbfArra[intType] != NULL) {
+            l1cBmxToIntCbfArra[intType]();
+        }
+    }
+
+    while (1) {
+        //MSG("L1C_BMX_TO_IRQHandler\r\n");
+        BL702_Delay_MS(1000);
+    }
+}
+#endif
+
+/*@} end of group L1C_Public_Functions */
+
+/*@} end of group L1C */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_mjpeg.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_mjpeg.c
new file mode 100644
index 00000000..06ff2f95
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_mjpeg.c
@@ -0,0 +1,740 @@
+/**
+  ******************************************************************************
+  * @file    bl702_mjpeg.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702.h"
+#include "bl702_mjpeg.h"
+#include "bl702_glb.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  MJPEG
+ *  @{
+ */
+
+/** @defgroup  MJPEG_Private_Macros
+ *  @{
+ */
+
+/*@} end of group MJPEG_Private_Macros */
+
+/** @defgroup  MJPEG_Private_Types
+ *  @{
+ */
+
+/*@} end of group MJPEG_Private_Types */
+
+/** @defgroup  MJPEG_Private_Variables
+ *  @{
+ */
+static intCallback_Type *mjpegIntCbfArra[MJPEG_INT_ALL] = { NULL };
+
+/*@} end of group MJPEG_Private_Variables */
+
+/** @defgroup  MJPEG_Global_Variables
+ *  @{
+ */
+
+/*@} end of group MJPEG_Global_Variables */
+
+/** @defgroup  MJPEG_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group MJPEG_Private_Fun_Declaration */
+
+/** @defgroup  MJPEG_Private_Functions
+ *  @{
+ */
+
+/*@} end of group MJPEG_Private_Functions */
+
+/** @defgroup  MJPEG_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Mjpeg module init
+ *
+ * @param  cfg: Mjpeg configuration structure pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void MJPEG_Init(MJPEG_CFG_Type *cfg)
+{
+    uint32_t tmpVal;
+
+    /* Disable clock gate */
+    GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_MJPEG);
+
+    /* disable mjpeg */
+    tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_ENABLE);
+    BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal);
+
+    /* basic stuff */
+    tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_YUV_MODE, cfg->yuv);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_Q_MODE, cfg->quality);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_H_BUST, cfg->burst);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_MJPEG_BIT_ORDER, cfg->bitOrderEnable);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_ORDER_U_EVEN, cfg->evenOrderEnable);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_WR_OVER_STOP, cfg->overStopEnable);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_REFLECT_DMY, cfg->reflectDmy);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_LAST_HF_HBLK_DMY, cfg->verticalDmy);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_LAST_HF_WBLK_DMY, cfg->horizationalDmy);
+    BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal);
+
+    tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_MJPEG_WAIT_CYCLE, cfg->waitCount);
+    BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal);
+
+    tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_FRAME_SIZE);
+
+    switch (cfg->yuv) {
+        case MJPEG_YUV422_INTERLEAVE:
+        case MJPEG_YUV422_PLANAR:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_WBLK, (cfg->resolutionX + 15) >> 4);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_HBLK, (cfg->resolutionY + 7) >> 3);
+            break;
+
+        case MJPEG_YUV420:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_WBLK, (cfg->resolutionX + 15) >> 4);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_HBLK, (cfg->resolutionY + 15) >> 4);
+            break;
+
+        case MJPEG_YUV400:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_WBLK, (cfg->resolutionX + 7) >> 3);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_HBLK, (cfg->resolutionY + 7) >> 3);
+            break;
+
+        default:
+            break;
+    }
+
+    BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_SIZE, tmpVal);
+
+    tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_W_SWAP_MODE, cfg->swapModeEnable);
+    BL_WR_REG(MJPEG_BASE, MJPEG_SWAP_MODE, tmpVal);
+
+    /*align buffer to 16 bytes boundary, should be kept the same as CAM module*/
+    BL_WR_REG(MJPEG_BASE, MJPEG_YY_FRAME_ADDR, (cfg->bufferCamYY & 0xFFFFFFF0));
+    BL_WR_REG(MJPEG_BASE, MJPEG_UV_FRAME_ADDR, (cfg->bufferCamUV & 0xFFFFFFF0));
+    BL_WR_REG(MJPEG_BASE, MJPEG_YUV_MEM, (cfg->sizeCamUV << 16) + cfg->sizeCamYY);
+
+    /*align buffer to 16 bytes boundary*/
+    BL_WR_REG(MJPEG_BASE, MJPEG_JPEG_FRAME_ADDR, (cfg->bufferMjpeg & 0xFFFFFFF0));
+    /*align buffer size in unit of 64 bytes */
+    BL_WR_REG(MJPEG_BASE, MJPEG_JPEG_STORE_MEMORY, cfg->sizeMjpeg >> 6);
+
+    /* Clear interrupt */
+    BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x3F00);
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(MJPEG_IRQn, MJPEG_IRQHandler);
+#endif
+}
+
+/****************************************************************************/ /**
+ * @brief  Mjpeg packet mode configure
+ *
+ * @param  cfg: Packet configuration
+ *
+ * @return None
+ *
+*******************************************************************************/
+void MJPEG_Packet_Config(MJPEG_Packet_Type *cfg)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_PAKET_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_PKET_EN, cfg->packetEnable);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_JEND_TO_PEND, cfg->endToTail);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_PKET_BODY_BYTE, cfg->packetBody);
+    BL_WR_REG(MJPEG_BASE, MJPEG_PAKET_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_HEADER_BYTE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_HEAD_BYTE, cfg->frameHead);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_TAIL_EXP, cfg->frameTail);
+    BL_WR_REG(MJPEG_BASE, MJPEG_HEADER_BYTE, tmpVal);
+
+    BL_WR_REG(MJPEG_BASE, MJPEG_PAKET_HEAD_TAIL, (cfg->packetTail << 16) + cfg->packetHead);
+}
+
+/****************************************************************************/ /**
+ * @brief  Mjpeg set YUYV order, only work in interleave mode
+ *
+ * @param  y0: Y0 order
+ * @param  u0: U0 order
+ * @param  y1: Y1 order
+ * @param  v0: V0 order
+ *
+ * @return None
+ *
+*******************************************************************************/
+void MJPEG_Set_YUYV_Order_Interleave(uint8_t y0, uint8_t u0, uint8_t y1, uint8_t v0)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_Y0_ORDER, y0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_U0_ORDER, u0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_Y1_ORDER, y1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_V0_ORDER, v0);
+    BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal);
+
+    MJPEG_Set_YUYV_Order_Planar(0, 1);
+}
+
+/****************************************************************************/ /**
+ * @brief  Mjpeg set YY/UV order, only work in planar mode
+ *
+ * @param  yy: YY order
+ * @param  uv: UV order
+ *
+ * @return None
+ *
+*******************************************************************************/
+void MJPEG_Set_YUYV_Order_Planar(uint8_t yy, uint8_t uv)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_YY_DVP2AHB_LSEL, yy);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_YY_DVP2AHB_FSEL, yy);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_UV_DVP2AHB_LSEL, uv);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_UV_DVP2AHB_FSEL, uv);
+    BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Deinit mjpeg module
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void MJPEG_Deinit(void)
+{
+    //GLB_AHB_Slave2_Reset(BL_AHB_SLAVE2_MJPEG);
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable mjpeg module
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void MJPEG_Enable(void)
+{
+    uint32_t tmpVal;
+
+    /* Enable mjpeg module */
+    tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1);
+    tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_MJPEG_ENABLE);
+    BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable mjpeg module
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void MJPEG_Disable(void)
+{
+    uint32_t tmpVal;
+
+    /* Disable mjpeg module */
+    tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_ENABLE);
+    BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable&disable mjpeg software mode and set frame count
+ *
+ * @param  count: Frame count
+ *
+ * @return None
+ *
+*******************************************************************************/
+void MJPEG_SW_Enable(uint8_t count)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_SW_FRAME, count);
+    tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_MJPEG_SW_MODE);
+    BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_SW_MODE);
+    BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  MJPEG software mode run, software mode enable first
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void MJPEG_SW_Run(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2);
+    tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_MJPEG_SW_RUN);
+    BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_SW_RUN);
+    BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Get one mjpeg frame
+ *
+ * @param  info: Mjpeg frame infomation pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void MJPEG_Get_Frame_Info(MJPEG_Frame_Info *info)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3);
+
+    info->validFrames = BL_GET_REG_BITS_VAL(tmpVal, MJPEG_FRAME_VALID_CNT);
+    info->curFrameAddr = BL_RD_REG(MJPEG_BASE, MJPEG_START_ADDR0);
+    info->curFrameBytes = (BL_RD_REG(MJPEG_BASE, MJPEG_BIT_CNT0) + 7) >> 3;
+    info->curFrameQ = BL_RD_REG(MJPEG_BASE, MJPEG_Q_MODE0) & 0x3f;
+    info->status = tmpVal;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get available count of frames
+ *
+ * @param  None
+ *
+ * @return Frames count
+ *
+*******************************************************************************/
+uint8_t MJPEG_Get_Frame_Count(void)
+{
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3), MJPEG_FRAME_VALID_CNT);
+}
+
+/****************************************************************************/ /**
+ * @brief  Pop one mjpeg frame
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void MJPEG_Pop_Frame(void)
+{
+    BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 1);
+}
+
+/****************************************************************************/ /**
+ * @brief  Free current read memory block
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void MJPEG_Current_Block_Clear(void)
+{
+    BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x2);
+}
+
+/****************************************************************************/ /**
+ * @brief  Current read memory block index
+ *
+ * @param  None
+ *
+ * @return Block number
+ *
+*******************************************************************************/
+MJPEG_Swap_Block_Type MJPEG_Get_Current_Block(void)
+{
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_READ_SWAP_IDX);
+}
+
+/****************************************************************************/ /**
+ * @brief  Get block status, full or not full
+ *
+ * @param  block: Block number
+ *
+ * @return Block status
+ *
+*******************************************************************************/
+BL_Sts_Type MJPEG_Block_Is_Full(MJPEG_Swap_Block_Type block)
+{
+    CHECK_PARAM(IS_MJPEG_SWAP_BLOCK_TYPE(block));
+
+    if (MJPEG_BLOCK_0 == block) {
+        return BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_SWAP0_FULL);
+    } else {
+        return BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_SWAP1_FULL);
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Current read memory block is frame start
+ *
+ * @param  None
+ *
+ * @return Set or reset
+ *
+*******************************************************************************/
+BL_Sts_Type MJPEG_Current_Block_Is_Start(void)
+{
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_SWAP_FSTART);
+}
+
+/****************************************************************************/ /**
+ * @brief  Current read memory block is frame end
+ *
+ * @param  None
+ *
+ * @return Set or reset
+ *
+*******************************************************************************/
+BL_Sts_Type MJPEG_Current_Block_Is_End(void)
+{
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_SWAP_FEND);
+}
+
+/****************************************************************************/ /**
+ * @brief  Get frame remain bit count in last block, only valid when current read memory block is
+ *         frame end
+ *
+ * @param  None
+ *
+ * @return Bit count
+ *
+*******************************************************************************/
+uint32_t MJPEG_Get_Remain_Bit(void)
+{
+    return BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_BIT_CNT);
+}
+
+/****************************************************************************/ /**
+ * @brief  Set frame threshold to issue normal interrupt
+ *
+ * @param  count: Frame threshold
+ *
+ * @return None
+ *
+*******************************************************************************/
+void MJPEG_Set_Frame_Threshold(uint8_t count)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_CNT_TRGR_INT, count);
+    BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_3, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  MJPEG Enable Disable Interrupt
+ *
+ * @param  intType: MJPEG Interrupt Type
+ * @param  intMask: Enable or Disable
+ *
+ * @return None
+ *
+*******************************************************************************/
+void MJPEG_IntMask(MJPEG_INT_Type intType, BL_Mask_Type intMask)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_MJPEG_INT_TYPE(intType));
+    CHECK_PARAM(IS_BL_MASK_TYPE(intMask));
+
+    tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3);
+
+    switch (intType) {
+        case MJPEG_INT_NORMAL:
+            if (intMask == UNMASK) {
+                /* Enable this interrupt */
+                tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_EN);
+            } else {
+                /* Disable this interrupt */
+                tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_EN);
+            }
+
+            break;
+
+        case MJPEG_INT_CAM_OVERWRITE:
+            if (intMask == UNMASK) {
+                /* Enable this interrupt */
+                tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_EN);
+            } else {
+                /* Disable this interrupt */
+                tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_EN);
+            }
+
+            break;
+
+        case MJPEG_INT_MEM_OVERWRITE:
+            if (intMask == UNMASK) {
+                /* Enable this interrupt */
+                tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_EN);
+            } else {
+                /* Disable this interrupt */
+                tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_EN);
+            }
+
+            break;
+
+        case MJPEG_INT_FRAME_OVERWRITE:
+            if (intMask == UNMASK) {
+                /* Enable this interrupt */
+                tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_EN);
+            } else {
+                /* Disable this interrupt */
+                tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_EN);
+            }
+
+            break;
+
+        case MJPEG_INT_BACK_IDLE:
+            if (intMask == UNMASK) {
+                /* Enable this interrupt */
+                tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_EN);
+            } else {
+                /* Disable this interrupt */
+                tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_EN);
+            }
+
+            break;
+
+        case MJPEG_INT_SWAP:
+            if (intMask == UNMASK) {
+                /* Enable this interrupt */
+                tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_EN);
+            } else {
+                /* Disable this interrupt */
+                tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_EN);
+            }
+
+            break;
+
+        case MJPEG_INT_ALL:
+            if (intMask == UNMASK) {
+                /* Enable all interrupt */
+                tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_EN);
+                tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_EN);
+                tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_EN);
+                tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_EN);
+                tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_EN);
+                tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_EN);
+            } else {
+                /* Disable all interrupt */
+                tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_EN);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_EN);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_EN);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_EN);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_EN);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_EN);
+            }
+
+            break;
+
+        default:
+            break;
+    }
+
+    BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_3, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  MJPEG Interrupt Clear
+ *
+ * @param  intType: MJPEG Interrupt Type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void MJPEG_IntClr(MJPEG_INT_Type intType)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_MJPEG_INT_TYPE(intType));
+
+    tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP);
+
+    switch (intType) {
+        case MJPEG_INT_NORMAL:
+            tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_CLR);
+            break;
+
+        case MJPEG_INT_CAM_OVERWRITE:
+            tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_CLR);
+            break;
+
+        case MJPEG_INT_MEM_OVERWRITE:
+            tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_CLR);
+            break;
+
+        case MJPEG_INT_FRAME_OVERWRITE:
+            tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_CLR);
+            break;
+
+        case MJPEG_INT_BACK_IDLE:
+            tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_CLR);
+            break;
+
+        case MJPEG_INT_SWAP:
+            tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_CLR);
+            break;
+
+        case MJPEG_INT_ALL:
+            tmpVal = 0x3F00;
+
+        default:
+            break;
+    }
+
+    BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Install mjpeg interrupt callback function
+ *
+ * @param  intType: MJPEG interrupt type
+ * @param  cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
+ *
+ * @return None
+ *
+*******************************************************************************/
+void MJPEG_Int_Callback_Install(MJPEG_INT_Type intType, intCallback_Type *cbFun)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_MJPEG_INT_TYPE(intType));
+
+    mjpegIntCbfArra[intType] = cbFun;
+}
+
+/****************************************************************************/ /**
+ * @brief  Mjpeg interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void MJPEG_IRQHandler(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3);
+
+    if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_NORMAL_INT)) {
+        BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x100);
+
+        if (mjpegIntCbfArra[MJPEG_INT_NORMAL] != NULL) {
+            /* call the callback function */
+            mjpegIntCbfArra[MJPEG_INT_NORMAL]();
+        }
+    }
+
+    if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_CAM_INT)) {
+        BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x200);
+
+        if (mjpegIntCbfArra[MJPEG_INT_CAM_OVERWRITE] != NULL) {
+            /* call the callback function */
+            mjpegIntCbfArra[MJPEG_INT_CAM_OVERWRITE]();
+        }
+    }
+
+    if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_MEM_INT)) {
+        BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x400);
+
+        if (mjpegIntCbfArra[MJPEG_INT_MEM_OVERWRITE] != NULL) {
+            /* call the callback function */
+            mjpegIntCbfArra[MJPEG_INT_MEM_OVERWRITE]();
+        }
+    }
+
+    if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_FRAME_INT)) {
+        BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x800);
+
+        if (mjpegIntCbfArra[MJPEG_INT_FRAME_OVERWRITE] != NULL) {
+            /* call the callback function */
+            mjpegIntCbfArra[MJPEG_INT_FRAME_OVERWRITE]();
+        }
+    }
+
+    if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_IDLE_INT)) {
+        BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x1000);
+
+        if (mjpegIntCbfArra[MJPEG_INT_BACK_IDLE] != NULL) {
+            /* call the callback function */
+            mjpegIntCbfArra[MJPEG_INT_BACK_IDLE]();
+        }
+    }
+
+    if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_SWAP_INT)) {
+        BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x2000);
+
+        if (mjpegIntCbfArra[MJPEG_INT_SWAP] != NULL) {
+            /* call the callback function */
+            mjpegIntCbfArra[MJPEG_INT_SWAP]();
+        }
+    }
+}
+#endif
+
+/*@} end of group MJPEG_Public_Functions */
+
+/*@} end of group MJPEG */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_pds.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_pds.c
new file mode 100644
index 00000000..28b6cbcf
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_pds.c
@@ -0,0 +1,1355 @@
+/**
+  ******************************************************************************
+  * @file    bl702_pds.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702.h"
+#include "bl702_pds.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  PDS
+ *  @{
+ */
+
+/** @defgroup  PDS_Private_Macros
+ *  @{
+ */
+
+/*@} end of group PDS_Private_Macros */
+
+/** @defgroup  PDS_Private_Types
+ *  @{
+ */
+
+/*@} end of group PDS_Private_Types */
+
+/** @defgroup  PDS_Private_Variables
+ *  @{
+ */
+static intCallback_Type *pdsIntCbfArra[PDS_INT_MAX][1] = { { NULL }, { NULL }, { NULL }, { NULL }, { NULL }, { NULL }, { NULL }, { NULL }, { NULL }, { NULL }, { NULL } };
+
+/*@} end of group PDS_Private_Variables */
+
+/** @defgroup  PDS_Global_Variables
+ *  @{
+ */
+
+/*@} end of group PDS_Global_Variables */
+
+/** @defgroup  PDS_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group PDS_Private_Fun_Declaration */
+
+/** @defgroup  PDS_Private_Functions
+ *  @{
+ */
+
+/*@} end of group PDS_Private_Functions */
+
+/** @defgroup  PDS_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  power down sleep ram configure
+ *
+ * @param  ramCfg: power down sleep force ram configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg)
+{
+    if (NULL == ramCfg) {
+        return ERROR;
+    }
+
+    /* PDS_RAM1 config */
+    BL_WR_REG(PDS_BASE, PDS_RAM1, *(uint32_t *)ramCfg);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  power down sleep set pad configure
+ *
+ * @param  pin: power down sleep pad num
+ * @param  cfg: power down sleep pad type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Set_Pad_Config(PDS_PAD_PIN_Type pin, PDS_PAD_CFG_Type cfg)
+{
+    uint32_t tmpVal = 0;
+    uint32_t tmpPu = 0;
+    uint32_t tmpPd = 0;
+
+    if (pin < PDS_PAD_PIN_GPIO_23) {
+        /* GPIO17 - GPIO22 */
+        tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_SET_PU_PD);
+
+        switch (cfg) {
+            case PDS_PAD_CFG_PULL_NONE:
+                tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD) & ~(1 << pin);
+                tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU) & ~(1 << pin);
+                break;
+
+            case PDS_PAD_CFG_PULL_DOWN:
+                tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD) | (1 << pin);
+                tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU) & ~(1 << pin);
+                break;
+
+            case PDS_PAD_CFG_PULL_UP:
+                tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD) & ~(1 << pin);
+                tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU) | (1 << pin);
+                break;
+
+            case PDS_PAD_CFG_ACTIVE_IE:
+                tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD) | (1 << pin);
+                tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU) | (1 << pin);
+                break;
+
+            default:
+                break;
+        }
+
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD, tmpPd);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU, tmpPu);
+        BL_WR_REG(PDS_BASE, PDS_GPIO_SET_PU_PD, tmpVal);
+    } else {
+        /* GPIO23 - GPIO28 */
+        tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_SET_PU_PD);
+
+        switch (cfg) {
+            case PDS_PAD_CFG_PULL_NONE:
+                tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD) & ~(1 << (pin - PDS_PAD_PIN_GPIO_23));
+                tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU) & ~(1 << (pin - PDS_PAD_PIN_GPIO_23));
+                break;
+
+            case PDS_PAD_CFG_PULL_DOWN:
+                tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD) | (1 << (pin - PDS_PAD_PIN_GPIO_23));
+                tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU) & ~(1 << (pin - PDS_PAD_PIN_GPIO_23));
+                break;
+
+            case PDS_PAD_CFG_PULL_UP:
+                tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD) & ~(1 << (pin - PDS_PAD_PIN_GPIO_23));
+                tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU) | (1 << (pin - PDS_PAD_PIN_GPIO_23));
+                break;
+
+            case PDS_PAD_CFG_ACTIVE_IE:
+                tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD) | (1 << (pin - PDS_PAD_PIN_GPIO_23));
+                tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU) | (1 << (pin - PDS_PAD_PIN_GPIO_23));
+                break;
+
+            default:
+                break;
+        }
+
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD, tmpPd);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU, tmpPu);
+        BL_WR_REG(PDS_BASE, PDS_GPIO_SET_PU_PD, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable power down sleep
+ *
+ * @param  cfg: power down sleep configuration 1
+ * @param  cfg4: power down sleep configuration 2
+ * @param  pdsSleepCnt: power down sleep count cycle
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_App_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt)
+{
+    /* PDS sleep time 0 <=> sleep forever */
+    /* PDS sleep time 1~PDS_WARMUP_LATENCY_CNT <=> error */
+    /* PDS sleep time >PDS_WARMUP_LATENCY_CNT <=> correct */
+    if (!pdsSleepCnt) {
+        cfg->sleepForever = 0;
+    } else if ((pdsSleepCnt) && (pdsSleepCnt <= PDS_WARMUP_LATENCY_CNT)) {
+        return ERROR;
+    } else {
+        BL_WR_REG(PDS_BASE, PDS_TIME1, pdsSleepCnt - PDS_WARMUP_LATENCY_CNT);
+    }
+
+    /* PDS_CTL4 config */
+    BL_WR_REG(PDS_BASE, PDS_CTL4, *(uint32_t *)cfg4);
+
+    /* PDS_CTL config */
+    if (cfg->pdsStart) {
+        BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg & ~(1 << 0)));
+        BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg | (1 << 0)));
+    } else {
+        BL_WR_REG(PDS_BASE, PDS_CTL, *(uint32_t *)cfg);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  power down sleep force configure
+ *
+ * @param  cfg2: power down sleep force configuration 1
+ * @param  cfg3: power down sleep force configuration 2
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3)
+{
+    /* PDS_CTL2 config */
+    BL_WR_REG(PDS_BASE, PDS_CTL2, *(uint32_t *)cfg2);
+
+    /* PDS_CTL3 config */
+    BL_WR_REG(PDS_BASE, PDS_CTL3, *(uint32_t *)cfg3);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  power down sleep force configure
+ *
+ * @param  defaultLvCfg: power down sleep default level configuration
+ * @param  pdsSleepCnt: power down sleep time count
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, uint32_t pdsSleepCnt)
+{
+    PDS_Force_Config((PDS_CTL2_Type *)&(defaultLvCfg->pdsCtl2), (PDS_CTL3_Type *)&(defaultLvCfg->pdsCtl3));
+    PDS_App_Enable((PDS_CTL_Type *)&(defaultLvCfg->pdsCtl), (PDS_CTL4_Type *)&(defaultLvCfg->pdsCtl4), pdsSleepCnt);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  power down sleep int enable
+ *
+ * @param  intType: PDS int type
+ * @param  enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_IntEn(PDS_INT_Type intType, BL_Fun_Type enable)
+{
+    uint32_t offset = 0;
+    uint32_t tmpVal = 0;
+
+    if ((intType < PDS_INT_PDS_SLEEP_CNT) || (intType > PDS_INT_KYS_QDEC)) {
+        return ERROR;
+    }
+
+    switch (intType) {
+        case PDS_INT_WAKEUP:
+        case PDS_INT_RF_DONE:
+        case PDS_INT_PLL_DONE:
+            return ERROR;
+
+        case PDS_INT_PDS_SLEEP_CNT:
+            offset = 16;
+            break;
+
+        case PDS_INT_HBN_IRQ_OUT0:
+            offset = 17;
+            break;
+
+        case PDS_INT_HBN_IRQ_OUT1:
+            offset = 18;
+            break;
+
+        case PDS_INT_GPIO_IRQ:
+            offset = 19;
+            break;
+
+        case PDS_INT_IRRX:
+            offset = 20;
+            break;
+
+        case PDS_INT_BLE_SLP_IRQ:
+            offset = 21;
+            break;
+
+        case PDS_INT_USB_WKUP:
+            offset = 22;
+            break;
+
+        case PDS_INT_KYS_QDEC:
+            offset = 23;
+            break;
+
+        case PDS_INT_MAX:
+            break;
+
+        default:
+            break;
+    }
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+
+    if (enable) {
+        tmpVal = tmpVal | (1 << offset);
+    } else {
+        tmpVal = tmpVal & ~(1 << offset);
+    }
+
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  power down sleep int mask
+ *
+ * @param  intType: PDS int type
+ * @param  intMask: MASK or UNMASK
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask)
+{
+    uint32_t offset = 0;
+    uint32_t tmpVal = 0;
+
+    if (intType > PDS_INT_PLL_DONE) {
+        return ERROR;
+    }
+
+    switch (intType) {
+        case PDS_INT_WAKEUP:
+            offset = 8;
+            break;
+
+        case PDS_INT_RF_DONE:
+            offset = 10;
+            break;
+
+        case PDS_INT_PLL_DONE:
+            offset = 11;
+            break;
+
+        case PDS_INT_PDS_SLEEP_CNT:
+        case PDS_INT_HBN_IRQ_OUT0:
+        case PDS_INT_HBN_IRQ_OUT1:
+        case PDS_INT_GPIO_IRQ:
+        case PDS_INT_IRRX:
+        case PDS_INT_BLE_SLP_IRQ:
+        case PDS_INT_USB_WKUP:
+        case PDS_INT_KYS_QDEC:
+        case PDS_INT_MAX:
+        default:
+            return ERROR;
+    }
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+
+    if (intMask != UNMASK) {
+        tmpVal = tmpVal | (1 << offset);
+    } else {
+        tmpVal = tmpVal & ~(1 << offset);
+    }
+
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get power down sleep int status
+ *
+ * @param  intType: PDS int type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType)
+{
+    uint32_t offset = 0;
+
+    switch (intType) {
+        case PDS_INT_WAKEUP:
+            offset = 0;
+            break;
+
+        case PDS_INT_RF_DONE:
+            offset = 2;
+            break;
+
+        case PDS_INT_PLL_DONE:
+            offset = 3;
+            break;
+
+        case PDS_INT_PDS_SLEEP_CNT:
+            offset = 24;
+            break;
+
+        case PDS_INT_HBN_IRQ_OUT0:
+            offset = 25;
+            break;
+
+        case PDS_INT_HBN_IRQ_OUT1:
+            offset = 26;
+            break;
+
+        case PDS_INT_GPIO_IRQ:
+            offset = 27;
+            break;
+
+        case PDS_INT_IRRX:
+            offset = 28;
+            break;
+
+        case PDS_INT_BLE_SLP_IRQ:
+            offset = 29;
+            break;
+
+        case PDS_INT_USB_WKUP:
+            offset = 30;
+            break;
+
+        case PDS_INT_KYS_QDEC:
+            offset = 31;
+            break;
+
+        case PDS_INT_MAX:
+            break;
+
+        default:
+            break;
+    }
+
+    return (BL_RD_REG(PDS_BASE, PDS_INT) & (1 << offset)) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  clear power down sleep int status
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_IntClear(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get power down sleep PLL status
+ *
+ * @param  None
+ *
+ * @return PDS PLL status
+ *
+*******************************************************************************/
+PDS_PLL_STS_Type PDS_Get_PdsPllStstus(void)
+{
+    return (PDS_PLL_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_PLL_STATE);
+}
+
+/****************************************************************************/ /**
+ * @brief  get power down sleep RF status
+ *
+ * @param  None
+ *
+ * @return PDS RF status
+ *
+*******************************************************************************/
+PDS_RF_STS_Type PDS_Get_PdsRfStstus(void)
+{
+    return (PDS_RF_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_RF_STATE);
+}
+
+/****************************************************************************/ /**
+ * @brief  get power down sleep status
+ *
+ * @param  None
+ *
+ * @return PDS status
+ *
+*******************************************************************************/
+PDS_STS_Type PDS_Get_PdsStstus(void)
+{
+    return (PDS_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_STATE);
+}
+
+/****************************************************************************/ /**
+ * @brief  power down sleep clear reset event
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_Clear_Reset_Event(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLR_RESET_EVENT);
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLR_RESET_EVENT);
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLR_RESET_EVENT);
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get power down sleep reset event
+ *
+ * @param  event: power down sleep reset event
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type PDS_Get_Reset_Event(PDS_RST_EVENT_Type event)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_RESET_EVENT);
+
+    return (tmpVal & (1 << event)) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  set power down sleep VDDCORE gpio interrupt config
+ *
+ * @param  src: PDS VDDCORE src pin num
+ * @param  mode: PDS VDDCORE src pin interrupt type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_Set_Vddcore_GPIO_IntCfg(PDS_VDDCORE_GPIO_SRC_Type src, PDS_AON_GPIO_INT_Trigger_Type mode)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_PDS_VDDCORE_GPIO_SRC_TYPE(src));
+    CHECK_PARAM(IS_PDS_AON_GPIO_INT_Trigger_TYPE(mode));
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_INT_SELECT, src);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_INT_MODE, mode);
+    BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set power down sleep VDDCORE gpio interrupt mask
+ *
+ * @param  intMask: None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_Set_Vddcore_GPIO_IntMask(BL_Mask_Type intMask)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
+
+    if (intMask != UNMASK) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, PDS_GPIO_INT_MASK);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_INT_MASK);
+    }
+
+    BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set power down sleep VDDCORE gpio interrupt mask
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Sts_Type PDS_Get_Vddcore_GPIO_IntStatus(void)
+{
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_GPIO_INT), PDS_GPIO_INT_STAT) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  set power down sleep VDDCORE gpio interrupt mask
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_Set_Vddcore_GPIO_IntClear(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_INT_CLR);
+    BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_GPIO_INT_CLR);
+    BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_INT_CLR);
+    BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Install PDS interrupt callback function
+ *
+ * @param  intType: PDS int type
+ * @param  cbFun: cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType, intCallback_Type *cbFun)
+{
+    pdsIntCbfArra[intType][0] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Trim RC32M
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Trim_RC32M(void)
+{
+    Efuse_Ana_RC32M_Trim_Type trim;
+    int32_t tmpVal = 0;
+
+    EF_Ctrl_Read_RC32M_Trim(&trim);
+
+    if (trim.trimRc32mExtCodeEn) {
+        if (trim.trimRc32mCodeFrExtParity == EF_Ctrl_Get_Trim_Parity(trim.trimRc32mCodeFrExt, 8)) {
+            tmpVal = BL_RD_REG(PDS_BASE, PDS_RC32M_CTRL0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_RC32M_CODE_FR_EXT, trim.trimRc32mCodeFrExt);
+            tmpVal = BL_SET_REG_BIT(tmpVal, PDS_RC32M_EXT_CODE_EN);
+            BL_WR_REG(PDS_BASE, PDS_RC32M_CTRL0, tmpVal);
+            BL702_Delay_US(2);
+            return SUCCESS;
+        }
+    }
+
+    return ERROR;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Select RC32M as PLL ref source
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_RC32M_As_PLL_Ref(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_XTAL_RC32M_SEL);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Select XTAL as PLL ref source
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_XTAL_As_PLL_Ref(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_XTAL_RC32M_SEL);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power on PLL
+ *
+ * @param  xtalType: xtal type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType)
+{
+    uint32_t tmpVal = 0;
+
+    /* Check parameter*/
+    CHECK_PARAM(IS_PDS_PLL_XTAL_TYPE(xtalType));
+
+    /**************************/
+    /* select PLL XTAL source */
+    /**************************/
+
+    if ((xtalType == PDS_PLL_XTAL_RC32M) || (xtalType == PDS_PLL_XTAL_NONE)) {
+        PDS_Trim_RC32M();
+        PDS_Select_RC32M_As_PLL_Ref();
+    } else {
+        PDS_Select_XTAL_As_PLL_Ref();
+    }
+
+    /*******************************************/
+    /* PLL power down first, not indispensable */
+    /*******************************************/
+    /* power off PLL first, this step is not indispensable */
+    PDS_Power_Off_PLL();
+
+    /********************/
+    /* PLL param config */
+    /********************/
+
+    /* clkpll_icp_1u */
+    /* clkpll_icp_5u */
+    /* clkpll_int_frac_sw */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_CP);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_ICP_1U, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_ICP_5U, 2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_INT_FRAC_SW, 0);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_CP, tmpVal);
+
+    /* clkpll_c3 */
+    /* clkpll_cz */
+    /* clkpll_rz */
+    /* clkpll_r4 */
+    /* clkpll_r4_short */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_RZ);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_C3, 3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_CZ, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_RZ, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_R4_SHORT, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_R4, 2);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_RZ, tmpVal);
+
+    /* clkpll_refdiv_ratio */
+    /* clkpll_postdiv */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_POSTDIV, 0x14);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_REFDIV_RATIO, 2);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
+
+    /* clkpll_sdmin */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x3C0000);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_SDM, tmpVal);
+
+    /* clkpll_sel_fb_clk */
+    /* clkpll_sel_sample_clk can be 0/1, default is 1 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_FBDV);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SEL_FB_CLK, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SEL_SAMPLE_CLK, 1);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_FBDV, tmpVal);
+
+    /*************************/
+    /* PLL power up sequence */
+    /*************************/
+
+    /* pu_clkpll_sfreg=1 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_PU_CLKPLL_SFREG);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    BL702_Delay_US(5);
+
+    /* pu_clkpll=1 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_PU_CLKPLL);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    /* clkpll_pu_cp=1 */
+    /* clkpll_pu_pfd=1 */
+    /* clkpll_pu_fbdv=1 */
+    /* clkpll_pu_postdiv=1 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_CP);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_PFD);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_FBDV);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_POSTDIV);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    BL702_Delay_US(5);
+
+    /* clkpll_sdm_reset=1 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_SDM_RESET);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+    BL702_Delay_US(1);
+    /* clkpll_reset_fbdv=1 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_RESET_FBDV);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+    BL702_Delay_US(2);
+    /* clkpll_reset_fbdv=0 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_RESET_FBDV);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+    BL702_Delay_US(1);
+    /* clkpll_sdm_reset=0 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_SDM_RESET);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+/** PLL output config **/
+/*
+[8]    1'h0    r/w    clkpll_en_32m
+[7]    1'h0    r/w    clkpll_en_48m
+[6]    1'h0    r/w    clkpll_en_80m
+[5]    1'h0    r/w    clkpll_en_96m
+[4]    1'h0    r/w    clkpll_en_120m
+[3]    1'h0    r/w    clkpll_en_160m
+[2]    1'h0    r/w    clkpll_en_192m
+[1]    1'h0    r/w    clkpll_en_240m
+[0]    1'h0    r/w    clkpll_en_480m
+*/
+
+/****************************************************************************/ /**
+ * @brief  Enable all PLL clock
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_All_Clks(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN);
+    tmpVal |= 0x1FF;
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Disable all PLL clock
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_All_Clks(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN);
+    tmpVal &= (~0x1FF);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Enable PLL clock
+ *
+ * @param  pllClk: PLL clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk)
+{
+    uint32_t tmpVal = 0;
+
+    /* Check parameter*/
+    CHECK_PARAM(IS_PDS_PLL_CLK_TYPE(pllClk));
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN);
+    tmpVal |= (1 << pllClk);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Disable PLL clock
+ *
+ * @param  pllClk: PLL clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk)
+{
+    uint32_t tmpVal = 0;
+
+    /* Check parameter*/
+    CHECK_PARAM(IS_PDS_PLL_CLK_TYPE(pllClk));
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN);
+    tmpVal &= (~(1 << pllClk));
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power off PLL
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_Off_PLL(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* pu_clkpll_sfreg=0 */
+    /* pu_clkpll=0 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_PU_CLKPLL_SFREG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_PU_CLKPLL);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    /* clkpll_pu_cp=0 */
+    /* clkpll_pu_pfd=0 */
+    /* clkpll_pu_fbdv=0 */
+    /* clkpll_pu_postdiv=0 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_CP);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_PFD);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_FBDV);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_POSTDIV);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set Audio PLL clock
+ *
+ * @param  audioPLLFreq: Audio PLL sel frequency , have two vaild input 12.288 or 11.289 MHZ
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Set_Audio_PLL_Freq(PDS_AUDIO_PLL_Type audioPLLFreq)
+{
+    uint32_t sdmin_table[] = { 0x374BC6, 0x32CCED, 0x32CCED, 0x6E978D, 0x6C0000 };
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_PDS_AUDIO_PLL_TYPE(audioPLLFreq));
+
+    /*set PDS_CLKPLL_REFDIV_RATIO as 0x2 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_REFDIV_RATIO, 0x2);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
+
+    /*set clkpll_sdmin as sdmin*/
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, (uint32_t)sdmin_table[audioPLLFreq % (sizeof(sdmin_table) / sizeof(sdmin_table[0]))]);
+
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_SDM, tmpVal);
+
+    /*reset pll */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_PU_CLKPLL_SFREG, 1);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    BL702_Delay_MS(10);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_PU_CLKPLL, 1);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_RESET_FBDV, 1);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    BL702_Delay_MS(10);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_RESET_FBDV, 0);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    /*set div for audio pll */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
+
+    if (audioPLLFreq != AUDIO_PLL_5644800_HZ) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_POSTDIV, 36);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_POSTDIV, 72);
+    }
+
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  PDS software reset
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION PDS_Reset(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = *(uint32_t *)0x40000010;
+    tmpVal = tmpVal | (1 << 14);
+    *(uint32_t *)0x40000010 = tmpVal;
+
+    tmpVal = *(uint32_t *)0x40000010;
+    tmpVal = tmpVal & ~(1 << 14);
+    *(uint32_t *)0x40000010 = tmpVal;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Enable power down sleep
+ *
+ * @param  cfg: power down sleep configuration 1
+ * @param  pdsSleepCnt: power down sleep count cycle
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION PDS_Enable(PDS_CFG_Type *cfg, uint32_t pdsSleepCnt)
+{
+    uint32_t *p = (uint32_t *)cfg;
+
+    if (pdsSleepCnt - PDS_WARMUP_CNT <= 0) {
+        return;
+    }
+
+    BL_WR_REG(PDS_BASE, PDS_TIME1, pdsSleepCnt - PDS_WARMUP_CNT);
+
+    /* Set PDS control register  */
+    BL_WR_REG(PDS_BASE, PDS_CTL, *p);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  PDS Auto mode wake up counter config
+ *
+ * @param  sleepDuration: sleep time, total pds = sleep_duration + max_warmup_cnt (32K clock cycles),
+ *                        recommend maxWarmCnt*N+2
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION PDS_Auto_Time_Config(uint32_t sleepDuration)
+{
+    /* PDS_TIME1 */
+    BL_WR_REG(PDS_BASE, PDS_TIME1, sleepDuration);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  PDS Auto mode config and enable
+ *
+ * @param  powerCfg: PDS Auto mode power domain config
+ * @param  normalCfg: PDS Auto mode power normal config
+ * @param  enable: PDS Auto mode Enable or Disable
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION PDS_Auto_Enable(PDS_AUTO_POWER_DOWN_CFG_Type *powerCfg, PDS_AUTO_NORMAL_CFG_Type *normalCfg, BL_Fun_Type enable)
+{
+    uint32_t pdsCtl = 0;
+
+    CHECK_PARAM(IS_PDS_LDO_VOLTAGE_TYPE(normalCfg->vddcoreVol));
+
+    /* power config */
+    pdsCtl |= (powerCfg->mbgPower << 31) |
+              (powerCfg->ldo18rfPower << 30) |
+              (powerCfg->sfregPower << 29) |
+              (powerCfg->pllPower << 28) |
+              (powerCfg->cpu0Power << 19) |
+              (powerCfg->rc32mPower << 17) |
+              (powerCfg->xtalPower << 14) |
+              (powerCfg->allPower << 13) |
+              (powerCfg->isoPower << 11) |
+              (powerCfg->bzPower << 10) |
+              (powerCfg->sramDisStanby << 9) |
+              (powerCfg->cgPower << 8) |
+              (powerCfg->cpu1Power << 7) |
+              (powerCfg->usbPower << 3);
+    pdsCtl = BL_SET_REG_BITS_VAL(pdsCtl, PDS_CR_PDS_LDO_VOL, normalCfg->vddcoreVol);
+    pdsCtl |= (normalCfg->vddcoreVolEn << 18) |
+              (normalCfg->cpu0NotNeedWFI << 21) |
+              (normalCfg->cpu1NotNeedWFI << 20) |
+              (normalCfg->busReset << 16) |
+              (normalCfg->disIrqWakeUp << 15) |
+              (normalCfg->powerOffXtalForever << 2) |
+              (normalCfg->sleepForever << 1);
+    BL_WR_REG(PDS_BASE, PDS_CTL, pdsCtl);
+
+    pdsCtl = BL_RD_REG(PDS_BASE, PDS_CTL);
+
+    if (enable) {
+        pdsCtl |= (1 << 0);
+    } else {
+        pdsCtl &= ~(1 << 0);
+    }
+
+    BL_WR_REG(PDS_BASE, PDS_CTL, pdsCtl);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  PDS force turn off XXX domain
+ *
+ * @param  domain: PDS domain
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION PDS_Manual_Force_Turn_Off(PDS_FORCE_Type domain)
+{
+    uint32_t tmpVal = 0;
+
+    /* memory sleep */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+    tmpVal |= 1 << (domain + PDS_FORCE_MEM_STBY_OFFSET);
+    BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+
+    /* gate clock */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+    tmpVal |= 1 << (domain + PDS_FORCE_GATE_CLK_OFFSET);
+    BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+
+    /* pds reset */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+    tmpVal |= 1 << (domain + PDS_FORCE_PDS_RST_OFFSET);
+    BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+
+    /* isolation on */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+    tmpVal |= 1 << (domain + PDS_FORCE_ISO_EN_OFFSET);
+    BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+
+    /* power off */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+    tmpVal |= 1 << (domain + PDS_FORCE_PWR_OFF_OFFSET);
+    BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  PDS force turn on XXX domain
+ *
+ * @param  domain: PDS domain
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION PDS_Manual_Force_Turn_On(PDS_FORCE_Type domain)
+{
+    uint32_t tmpVal = 0;
+
+    /* power on */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+    tmpVal &= ~(1 << (domain + PDS_FORCE_PWR_OFF_OFFSET));
+    BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+
+    /* isolation off */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+    tmpVal &= ~(1 << (domain + PDS_FORCE_ISO_EN_OFFSET));
+    BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+
+    /* pds de_reset */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+    tmpVal &= ~(1 << (domain + PDS_FORCE_PDS_RST_OFFSET));
+    BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+
+    /* memory active */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+    tmpVal &= ~(1 << (domain + PDS_FORCE_MEM_STBY_OFFSET));
+    BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+
+    /* clock on */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+    tmpVal &= ~(1 << (domain + PDS_FORCE_GATE_CLK_OFFSET));
+    BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power down sleep wake up interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void PDS_WAKEUP_IRQHandler(void)
+{
+    for (PDS_INT_Type intType = PDS_INT_WAKEUP; intType < PDS_INT_MAX; intType++) {
+        if (PDS_Get_IntStatus(intType) && (pdsIntCbfArra[intType][0] != NULL)) {
+            pdsIntCbfArra[intType][0]();
+        }
+    }
+    PDS_Set_Vddcore_GPIO_IntClear();
+    PDS_IntClear();
+}
+
+/****************************************************************************/ /**
+ * @brief  PDS wakeup IRQHandler install
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_WAKEUP_IRQHandler_Install(void)
+{
+    Interrupt_Handler_Register(PDS_WAKEUP_IRQn, PDS_WAKEUP_IRQHandler);
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief
+ *
+ * @param
+ *
+ * @return
+ *
+*******************************************************************************/
+BL_Err_Type PDS_Set_Clkpll_Top_Ctrl(uint8_t vg11Sel)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
+    //clkpll_vg11_sel
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_VG11_SEL, vg11Sel);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/*@} end of group PDS_Public_Functions */
+
+/*@} end of group PDS */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_psram.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_psram.c
new file mode 100644
index 00000000..a56c2d10
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_psram.c
@@ -0,0 +1,764 @@
+/**
+  ******************************************************************************
+  * @file    bl702_psram.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_psram.h"
+#include "bl702_l1c.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  PSRAM
+ *  @{
+ */
+
+/** @defgroup  PSRAM_Private_Macros
+ *  @{
+ */
+
+/*@} end of group PSRAM_Private_Macros */
+
+/** @defgroup  PSRAM_Private_Types
+ *  @{
+ */
+
+/*@} end of group PSRAM_Private_Types */
+
+/** @defgroup  PSRAM_Private_Variables
+ *  @{
+ */
+
+/*@} end of group PSRAM_Private_Variables */
+
+/** @defgroup  PSRAM_Global_Variables
+ *  @{
+ */
+
+/*@} end of group PSRAM_Global_Variables */
+
+/** @defgroup  PSRAM_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group PSRAM_Private_Fun_Declaration */
+
+/** @defgroup  PSRAM_Private_Functions
+ *  @{
+ */
+
+/*@} end of group PSRAM_Private_Functions */
+
+/** @defgroup  PSRAM_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Init serial psram control interface
+ *
+ * @param  psramCfg: Serial psram parameter configuration pointer
+ * @param  cmdsCfg: Serial Serial Flash controller configuration pointer
+ * @param  sfCtrlPsramCfg: Serial psram controller configuration pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+//#ifndef BFLB_USE_ROM_DRIVER
+//__WEAK
+void ATTR_TCM_SECTION Psram_Init(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Psram_Cfg *sfCtrlPsramCfg)
+{
+    SF_Ctrl_Psram_Init(sfCtrlPsramCfg);
+    SF_Ctrl_Cmds_Set(cmdsCfg);
+
+    Psram_SetDriveStrength(psramCfg);
+    Psram_SetBurstWrap(psramCfg);
+}
+//#endif
+
+/****************************************************************************/ /**
+ * @brief  Read psram register
+ *
+ * @param  psramCfg: Serial psram parameter configuration pointer
+ * @param  regValue: Register value pointer to store data
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION Psram_ReadReg(SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_PSRAM_CTRL_MODE(psramCfg->ctrlMode));
+
+    uint8_t *const psramCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
+    SF_Ctrl_Cmd_Cfg_Type psramCmd;
+
+    if (((uint32_t)&psramCmd) % 4 == 0) {
+        BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4);
+    } else {
+        BL702_MemSet(&psramCmd, 0, sizeof(psramCmd));
+    }
+
+    if (psramCfg->ctrlMode == PSRAM_QPI_CTRL_MODE) {
+        psramCmd.cmdMode = SF_CTRL_CMD_4_LINES;
+        psramCmd.addrMode = SF_CTRL_ADDR_4_LINES;
+        psramCmd.dataMode = SF_CTRL_DATA_4_LINES;
+    }
+
+    psramCmd.cmdBuf[0] = (psramCfg->readRegCmd) << 24;
+    psramCmd.rwFlag = SF_CTRL_READ;
+    psramCmd.addrSize = 3;
+    psramCmd.dummyClks = psramCfg->readRegDmyClk;
+    psramCmd.nbData = 1;
+
+    SF_Ctrl_SendCmd(&psramCmd);
+
+    while (SET == SF_Ctrl_GetBusyState()) {
+    }
+
+    BL702_MemCpy(regValue, psramCtrlBuf, 1);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Write psram register
+ *
+ * @param  psramCfg: Serial psram parameter configuration pointer
+ * @param  regValue: Register value pointer storing data
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION Psram_WriteReg(SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_PSRAM_CTRL_MODE(psramCfg->ctrlMode));
+
+    uint8_t *const psramCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
+    SF_Ctrl_Cmd_Cfg_Type psramCmd;
+
+    if (((uint32_t)&psramCmd) % 4 == 0) {
+        BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4);
+    } else {
+        BL702_MemSet(&psramCmd, 0, sizeof(psramCmd));
+    }
+
+    BL702_MemCpy(psramCtrlBuf, regValue, 1);
+
+    if (psramCfg->ctrlMode == PSRAM_QPI_CTRL_MODE) {
+        psramCmd.cmdMode = SF_CTRL_CMD_4_LINES;
+        psramCmd.addrMode = SF_CTRL_ADDR_4_LINES;
+        psramCmd.dataMode = SF_CTRL_DATA_4_LINES;
+    }
+
+    psramCmd.cmdBuf[0] = (psramCfg->writeRegCmd) << 24;
+    psramCmd.rwFlag = SF_CTRL_WRITE;
+    psramCmd.addrSize = 3;
+    psramCmd.nbData = 1;
+
+    SF_Ctrl_SendCmd(&psramCmd);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set psram driver strength
+ *
+ * @param  psramCfg: Serial psram parameter configuration pointer
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION Psram_SetDriveStrength(SPI_Psram_Cfg_Type *psramCfg)
+{
+    uint32_t stat = 0;
+    /* Check the parameters */
+    CHECK_PARAM(IS_PSRAM_DRIVE_STRENGTH(psramCfg->driveStrength));
+
+    Psram_ReadReg(psramCfg, (uint8_t *)&stat);
+
+    if ((stat & 0x3) == psramCfg->driveStrength) {
+        return SUCCESS;
+    }
+
+    stat &= (~0x3);
+    stat |= psramCfg->driveStrength;
+
+    Psram_WriteReg(psramCfg, (uint8_t *)&stat);
+    /* Wait for write done */
+
+    Psram_ReadReg(psramCfg, (uint8_t *)&stat);
+
+    if ((stat & 0x3) == psramCfg->driveStrength) {
+        return SUCCESS;
+    }
+
+    return ERROR;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set psram burst wrap size
+ *
+ * @param  psramCfg: Serial psram parameter configuration pointer
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION Psram_SetBurstWrap(SPI_Psram_Cfg_Type *psramCfg)
+{
+    uint32_t stat = 0;
+    /* Check the parameters */
+    CHECK_PARAM(IS_PSRAM_BURST_LENGTH(psramCfg->burstLength));
+
+    Psram_ReadReg(psramCfg, (uint8_t *)&stat);
+
+    if (((stat >> 5) & 0x3) == psramCfg->burstLength) {
+        return SUCCESS;
+    }
+
+    stat &= (~(0x3 << 5));
+    stat |= (psramCfg->burstLength << 5);
+
+    Psram_WriteReg(psramCfg, (uint8_t *)&stat);
+    /* Wait for write done */
+
+    Psram_ReadReg(psramCfg, (uint8_t *)&stat);
+
+    if (((stat >> 5) & 0x3) == psramCfg->burstLength) {
+        return SUCCESS;
+    }
+
+    return ERROR;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Get psram ID
+ *
+ * @param  psramCfg: Serial psram parameter configuration pointer
+ * @param  data: Data pointer to store read data
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION Psram_ReadId(SPI_Psram_Cfg_Type *psramCfg, uint8_t *data)
+{
+    uint8_t *const psramCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
+    SF_Ctrl_Cmd_Cfg_Type psramCmd;
+
+    if (((uint32_t)&psramCmd) % 4 == 0) {
+        BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4);
+    } else {
+        BL702_MemSet(&psramCmd, 0, sizeof(psramCmd));
+    }
+
+    psramCmd.cmdBuf[0] = (psramCfg->readIdCmd) << 24;
+    psramCmd.rwFlag = SF_CTRL_READ;
+    psramCmd.addrSize = 3;
+    psramCmd.dummyClks = psramCfg->readIdDmyClk;
+    psramCmd.nbData = 8;
+
+    SF_Ctrl_SendCmd(&psramCmd);
+
+    while (SET == SF_Ctrl_GetBusyState()) {
+    }
+
+    BL702_MemCpy(data, psramCtrlBuf, 8);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Psram enter quad mode
+ *
+ * @param  psramCfg: Serial psram parameter configuration pointer
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION Psram_EnterQuadMode(SPI_Psram_Cfg_Type *psramCfg)
+{
+    SF_Ctrl_Cmd_Cfg_Type psramCmd;
+
+    if (((uint32_t)&psramCmd) % 4 == 0) {
+        BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4);
+    } else {
+        BL702_MemSet(&psramCmd, 0, sizeof(psramCmd));
+    }
+
+    psramCmd.cmdBuf[0] = (psramCfg->enterQuadModeCmd) << 24;
+    psramCmd.rwFlag = SF_CTRL_READ;
+
+    SF_Ctrl_SendCmd(&psramCmd);
+
+    while (SET == SF_Ctrl_GetBusyState()) {
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Psram exit quad mode
+ *
+ * @param  psramCfg: Serial psram parameter configuration pointer
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION Psram_ExitQuadMode(SPI_Psram_Cfg_Type *psramCfg)
+{
+    SF_Ctrl_Cmd_Cfg_Type psramCmd;
+
+    if (((uint32_t)&psramCmd) % 4 == 0) {
+        BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4);
+    } else {
+        BL702_MemSet(&psramCmd, 0, sizeof(psramCmd));
+    }
+
+    psramCmd.cmdMode = SF_CTRL_CMD_4_LINES;
+    psramCmd.addrMode = SF_CTRL_ADDR_4_LINES;
+    psramCmd.dataMode = SF_CTRL_DATA_4_LINES;
+
+    psramCmd.cmdBuf[0] = (psramCfg->exitQuadModeCmd) << 24;
+    psramCmd.rwFlag = SF_CTRL_READ;
+
+    SF_Ctrl_SendCmd(&psramCmd);
+
+    while (SET == SF_Ctrl_GetBusyState()) {
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Psram toggle burst length
+ *
+ * @param  psramCfg: Serial psram parameter configuration pointer
+ * @param  ctrlMode: Psram ctrl mode type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION Psram_ToggleBurstLength(SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode)
+{
+    SF_Ctrl_Cmd_Cfg_Type psramCmd;
+    /* Check the parameters */
+    CHECK_PARAM(IS_PSRAM_CTRL_MODE(ctrlMode));
+
+    if (((uint32_t)&psramCmd) % 4 == 0) {
+        BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4);
+    } else {
+        BL702_MemSet(&psramCmd, 0, sizeof(psramCmd));
+    }
+
+    if (ctrlMode == PSRAM_QPI_CTRL_MODE) {
+        psramCmd.cmdMode = SF_CTRL_CMD_4_LINES;
+        psramCmd.addrMode = SF_CTRL_ADDR_4_LINES;
+        psramCmd.dataMode = SF_CTRL_DATA_4_LINES;
+    }
+
+    psramCmd.cmdBuf[0] = (psramCfg->burstToggleCmd) << 24;
+    psramCmd.rwFlag = SF_CTRL_READ;
+
+    SF_Ctrl_SendCmd(&psramCmd);
+
+    while (SET == SF_Ctrl_GetBusyState()) {
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Psram software reset
+ *
+ * @param  psramCfg: Serial psram parameter configuration pointer
+ * @param  ctrlMode: Psram ctrl mode type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION Psram_SoftwareReset(SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode)
+{
+    SF_Ctrl_Cmd_Cfg_Type psramCmd;
+    /* Check the parameters */
+    CHECK_PARAM(IS_PSRAM_CTRL_MODE(ctrlMode));
+
+    if (((uint32_t)&psramCmd) % 4 == 0) {
+        BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4);
+    } else {
+        BL702_MemSet(&psramCmd, 0, sizeof(psramCmd));
+    }
+
+    if (ctrlMode == PSRAM_QPI_CTRL_MODE) {
+        psramCmd.cmdMode = SF_CTRL_CMD_4_LINES;
+        psramCmd.addrMode = SF_CTRL_ADDR_4_LINES;
+        psramCmd.dataMode = SF_CTRL_DATA_4_LINES;
+    }
+
+    /* Reset enable */
+    psramCmd.cmdBuf[0] = (psramCfg->resetEnableCmd) << 24;
+    /* rwFlag don't care */
+    psramCmd.rwFlag = SF_CTRL_READ;
+    /* Wait for write done */
+
+    SF_Ctrl_SendCmd(&psramCmd);
+
+    while (SET == SF_Ctrl_GetBusyState()) {
+    }
+
+    /* Reset */
+    psramCmd.cmdBuf[0] = (psramCfg->resetCmd) << 24;
+    /* rwFlag don't care */
+    psramCmd.rwFlag = SF_CTRL_READ;
+    SF_Ctrl_SendCmd(&psramCmd);
+
+    while (SET == SF_Ctrl_GetBusyState()) {
+    }
+
+    BL702_Delay_US(50);
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Psram set IDbus config
+ *
+ * @param  psramCfg: Serial psram parameter configuration pointer
+ * @param  ioMode: Psram ctrl mode type
+ * @param  addr: Address to read/write
+ * @param  len: Data length to read/write
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION Psram_Set_IDbus_Cfg(SPI_Psram_Cfg_Type *psramCfg,
+                                                 SF_Ctrl_IO_Type ioMode, uint32_t addr, uint32_t len)
+{
+    uint8_t cmd, dummyClks;
+    SF_Ctrl_Cmd_Cfg_Type psramCmd;
+    uint8_t cmdValid = 1;
+    /* Check the parameters */
+    CHECK_PARAM(IS_SF_CTRL_IO_TYPE(ioMode));
+
+    SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB);
+
+    /* read mode cache set */
+    if (((uint32_t)&psramCmd) % 4 == 0) {
+        BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4);
+    } else {
+        BL702_MemSet(&psramCmd, 0, sizeof(psramCmd));
+    }
+
+    if (SF_CTRL_NIO_MODE == ioMode) {
+        cmd = psramCfg->fReadCmd;
+        dummyClks = psramCfg->fReadDmyClk;
+    } else if (SF_CTRL_QIO_MODE == ioMode) {
+        psramCmd.addrMode = SF_CTRL_ADDR_4_LINES;
+        psramCmd.dataMode = SF_CTRL_DATA_4_LINES;
+        cmd = psramCfg->fReadQuadCmd;
+        dummyClks = psramCfg->fReadQuadDmyClk;
+    } else {
+        return ERROR;
+    }
+
+    /* prepare command */
+    psramCmd.rwFlag = SF_CTRL_READ;
+    psramCmd.addrSize = 3;
+    psramCmd.cmdBuf[0] = (cmd << 24) | addr;
+    psramCmd.dummyClks = dummyClks;
+    psramCmd.nbData = len;
+    SF_Ctrl_Psram_Read_Icache_Set(&psramCmd, cmdValid);
+
+    /* write mode cache set */
+    if (((uint32_t)&psramCmd) % 4 == 0) {
+        BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4);
+    } else {
+        BL702_MemSet(&psramCmd, 0, sizeof(psramCmd));
+    }
+
+    if (SF_CTRL_NIO_MODE == ioMode) {
+        cmd = psramCfg->writeCmd;
+    } else if (SF_CTRL_QIO_MODE == ioMode) {
+        psramCmd.addrMode = SF_CTRL_ADDR_4_LINES;
+        psramCmd.dataMode = SF_CTRL_DATA_4_LINES;
+        cmd = psramCfg->quadWriteCmd;
+    } else {
+        return ERROR;
+    }
+
+    dummyClks = 0;
+
+    /* prepare command */
+    psramCmd.rwFlag = SF_CTRL_WRITE;
+    psramCmd.addrSize = 3;
+    psramCmd.cmdBuf[0] = (cmd << 24) | addr;
+    psramCmd.dummyClks = dummyClks;
+    psramCmd.nbData = len;
+    SF_Ctrl_Psram_Write_Icache_Set(&psramCmd, cmdValid);
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set cache write to psram with cache
+ *
+ * @param  psramCfg: Serial psram parameter configuration pointer
+ * @param  ioMode: Psram controller interface mode
+ * @param  wtEn: Psram cache write through enable
+ * @param  wbEn: Psram cache write back enable
+ * @param  waEn: Psram cache write allocate enable
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION Psram_Cache_Write_Set(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode,
+                                                   BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn)
+{
+    BL_Err_Type stat;
+
+    /* Cache now only support 32 bytes read */
+    stat = Psram_Set_IDbus_Cfg(psramCfg, ioMode, 0, 32);
+
+    if (SUCCESS != stat) {
+        return stat;
+    }
+
+    L1C_Cache_Write_Set(wtEn, wbEn, waEn);
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Write psram one region
+ *
+ * @param  psramCfg: Serial psram parameter configuration pointer
+ * @param  ioMode: Write mode: SPI mode or QPI mode
+ * @param  addr: Start address to be write
+ * @param  data: Data pointer to be write
+ * @param  len: Data length to be write
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION Psram_Write(SPI_Psram_Cfg_Type *psramCfg,
+                                         SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len)
+{
+    uint8_t *const psramCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
+    uint32_t i = 0, curLen = 0;
+    uint32_t burstLen = 512;
+    uint8_t cmd;
+    SF_Ctrl_Cmd_Cfg_Type psramCmd;
+    /* Check the parameters */
+    CHECK_PARAM(IS_SF_CTRL_IO_TYPE(ioMode));
+
+    if (((uint32_t)&psramCmd) % 4 == 0) {
+        BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4);
+    } else {
+        BL702_MemSet(&psramCmd, 0, sizeof(psramCmd));
+    }
+
+    if (SF_CTRL_NIO_MODE == ioMode) {
+        cmd = psramCfg->writeCmd;
+    } else if (SF_CTRL_QIO_MODE == ioMode) {
+        psramCmd.addrMode = SF_CTRL_ADDR_4_LINES;
+        psramCmd.dataMode = SF_CTRL_DATA_4_LINES;
+        cmd = psramCfg->quadWriteCmd;
+    } else {
+        return ERROR;
+    }
+
+    /* Prepare command */
+    psramCmd.rwFlag = SF_CTRL_WRITE;
+    psramCmd.addrSize = 3;
+
+    if (psramCfg->burstLength == PSRAM_BURST_LENGTH_16_BYTES) {
+        burstLen = 16;
+    } else if (psramCfg->burstLength == PSRAM_BURST_LENGTH_32_BYTES) {
+        burstLen = 32;
+    } else if (psramCfg->burstLength == PSRAM_BURST_LENGTH_64_BYTES) {
+        burstLen = 64;
+    } else if (psramCfg->burstLength == PSRAM_BURST_LENGTH_512_BYTES) {
+        burstLen = 512;
+    }
+
+    for (i = 0; i < len;) {
+        /* Get current programmed length within page size */
+        curLen = burstLen - addr % burstLen;
+
+        if (curLen > len - i) {
+            curLen = len - i;
+        }
+
+        /* Prepare command */
+        BL702_MemCpy_Fast(psramCtrlBuf, data, curLen);
+        psramCmd.cmdBuf[0] = (cmd << 24) | (addr);
+        psramCmd.nbData = curLen;
+
+        SF_Ctrl_SendCmd(&psramCmd);
+
+        /* Adjust address and programmed length */
+        addr += curLen;
+        i += curLen;
+        data += curLen;
+
+        /* Wait for write done */
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Read data from psram
+ *
+ * @param  psramCfg: Serial psram parameter configuration pointer
+ * @param  ioMode: IoMode: psram controller interface mode
+ * @param  addr: Psram read start address
+ * @param  data: Data pointer to store data read from psram
+ * @param  len: Data length to read
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION Psram_Read(SPI_Psram_Cfg_Type *psramCfg,
+                                        SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len)
+{
+    uint8_t *const psramCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
+    uint32_t curLen, i;
+    uint32_t burstLen = 512;
+    uint8_t cmd, dummyClks;
+    SF_Ctrl_Cmd_Cfg_Type psramCmd;
+    /* Check the parameters */
+    CHECK_PARAM(IS_SF_CTRL_IO_TYPE(ioMode));
+
+    if (((uint32_t)&psramCmd) % 4 == 0) {
+        BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4);
+    } else {
+        BL702_MemSet(&psramCmd, 0, sizeof(psramCmd));
+    }
+
+    if (SF_CTRL_NIO_MODE == ioMode) {
+        cmd = psramCfg->fReadCmd;
+        dummyClks = psramCfg->fReadDmyClk;
+    } else if (SF_CTRL_QIO_MODE == ioMode) {
+        psramCmd.addrMode = SF_CTRL_ADDR_4_LINES;
+        psramCmd.dataMode = SF_CTRL_DATA_4_LINES;
+        cmd = psramCfg->fReadQuadCmd;
+        dummyClks = psramCfg->fReadQuadDmyClk;
+    } else {
+        return ERROR;
+    }
+
+    /* Prepare command */
+    psramCmd.rwFlag = SF_CTRL_READ;
+    psramCmd.addrSize = 3;
+    psramCmd.dummyClks = dummyClks;
+
+    if (psramCfg->burstLength == PSRAM_BURST_LENGTH_16_BYTES) {
+        burstLen = 16;
+    } else if (psramCfg->burstLength == PSRAM_BURST_LENGTH_32_BYTES) {
+        burstLen = 32;
+    } else if (psramCfg->burstLength == PSRAM_BURST_LENGTH_64_BYTES) {
+        burstLen = 64;
+    } else if (psramCfg->burstLength == PSRAM_BURST_LENGTH_512_BYTES) {
+        burstLen = 512;
+    }
+
+    /* Read data */
+    for (i = 0; i < len;) {
+        /* Prepare command */
+        psramCmd.cmdBuf[0] = (cmd << 24) | (addr);
+        curLen = burstLen - addr % burstLen;
+
+        if (curLen > len - i) {
+            curLen = len - i;
+        }
+
+        if (curLen >= FLASH_CTRL_BUF_SIZE) {
+            curLen = FLASH_CTRL_BUF_SIZE;
+            psramCmd.nbData = curLen;
+        } else {
+            /* Make sf_ctrl word read */
+            psramCmd.nbData = ((curLen + 3) >> 2) << 2;
+        }
+
+        SF_Ctrl_SendCmd(&psramCmd);
+
+        while (SET == SF_Ctrl_GetBusyState()) {
+        }
+
+        BL702_MemCpy_Fast(data, psramCtrlBuf, curLen);
+
+        addr += curLen;
+        i += curLen;
+        data += curLen;
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/*@} end of group PSRAM_Public_Functions */
+
+/*@} end of group PSRAM */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_pwm.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_pwm.c
new file mode 100644
index 00000000..535ef94e
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_pwm.c
@@ -0,0 +1,588 @@
+/**
+ ******************************************************************************
+ * @file    bl702_pwm.c
+ * @version V1.0
+ * @date
+ * @brief   This file is the standard driver c file
+ ******************************************************************************
+ * @attention
+ *
+ * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#include "bl702_pwm.h"
+#include "bl702_glb.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  PWM
+ *  @{
+ */
+
+/** @defgroup  PWM_Private_Macros
+ *  @{
+ */
+#define PWM_Get_Channel_Reg(ch) (PWM_BASE + PWM_CHANNEL_OFFSET + (ch)*0x20)
+#define PWM_INT_TIMEOUT_COUNT   (160 * 1000)
+#define PWM_STOP_TIMEOUT_COUNT  (160 * 1000)
+
+/*@} end of group PWM_Private_Macros */
+
+/** @defgroup  PWM_Private_Types
+ *  @{
+ */
+
+/*@} end of group PWM_Private_Types */
+
+/** @defgroup  PWM_Private_Variables
+ *  @{
+ */
+
+/**
+ *  @brief PWM interrupt callback function address array
+ */
+static intCallback_Type *PWMIntCbfArra[PWM_CH_MAX][PWM_INT_ALL] = {{NULL}};
+
+/*@} end of group PWM_Private_Variables */
+
+/** @defgroup  PWM_Global_Variables
+ *  @{
+ */
+
+/*@} end of group PWM_Global_Variables */
+
+/** @defgroup  PWM_Private_Fun_Declaration
+ *  @{
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+static BL_Err_Type PWM_IntHandler(IRQn_Type intPeriph);
+#endif
+
+/*@} end of group PWM_Private_Fun_Declaration */
+
+/** @defgroup  PWM_Private_Functions
+ *  @{
+ */
+
+/****************************************************************************
+ * @brief  PWM interrupt handle
+ *
+ * @param  intPeriph: Select the peripheral, such as PWM0_IRQn
+ *
+ * @return SUCCESS
+ *
+ *******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+static BL_Err_Type PWM_IntHandler(IRQn_Type intPeriph) {
+  uint32_t i;
+  uint32_t tmpVal;
+  uint32_t timeoutCnt = PWM_INT_TIMEOUT_COUNT;
+  /* Get channel register */
+  uint32_t PWMx = PWM_BASE;
+
+  for (i = 0; i < PWM_CH_MAX; i++) {
+    tmpVal = BL_RD_REG(PWMx, PWM_INT_CONFIG);
+
+    if ((BL_GET_REG_BITS_VAL(tmpVal, PWM_INTERRUPT_STS) & (1 << i)) != 0) {
+      /* Clear interrupt */
+      tmpVal |= (1 << (i + PWM_INT_CLEAR_POS));
+      BL_WR_REG(PWMx, PWM_INT_CONFIG, tmpVal);
+
+      /* FIXME: we need set pwm_int_clear to 0 by software and
+         before this,we must make sure pwm_interrupt_sts is 0*/
+      do {
+        tmpVal = BL_RD_REG(PWMx, PWM_INT_CONFIG);
+        timeoutCnt--;
+
+        if (timeoutCnt == 0) {
+          break;
+        }
+      } while (BL_GET_REG_BITS_VAL(tmpVal, PWM_INTERRUPT_STS) & (1 << i));
+
+      tmpVal &= (~(1 << (i + PWM_INT_CLEAR_POS)));
+      BL_WR_REG(PWMx, PWM_INT_CONFIG, tmpVal);
+
+      if (PWMIntCbfArra[i][PWM_INT_PULSE_CNT] != NULL) {
+        /* Call the callback function */
+        PWMIntCbfArra[i][PWM_INT_PULSE_CNT]();
+      }
+    }
+  }
+
+  return SUCCESS;
+}
+#endif
+
+/*@} end of group PWM_Private_Functions */
+
+/** @defgroup  PWM_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************
+ * @brief  PWM channel init
+ *
+ * @param  chCfg: PWM configuration
+ *
+ * @return SUCCESS
+ *
+ *******************************************************************************/
+BL_Err_Type PWM_Channel_Init(PWM_CH_CFG_Type *chCfg) {
+  uint32_t tmpVal;
+  uint32_t timeoutCnt = PWM_STOP_TIMEOUT_COUNT;
+  /* Get channel register */
+  uint32_t PWMx = PWM_Get_Channel_Reg(chCfg->ch);
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_PWM_CH_ID_TYPE(chCfg->ch));
+  CHECK_PARAM(IS_PWM_CLK_TYPE(chCfg->clk));
+  CHECK_PARAM(IS_PWM_POLARITY_TYPE(chCfg->pol));
+  CHECK_PARAM(IS_PWM_STOP_MODE_TYPE(chCfg->stopMode));
+
+  /* Disable clock gate */
+  GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_PWM);
+
+  /* Config pwm clock and polarity */
+  tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
+  BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN));
+
+  while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)) {
+    timeoutCnt--;
+
+    if (timeoutCnt == 0) {
+      return TIMEOUT;
+    }
+  }
+
+  tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL, chCfg->clk);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_OUT_INV, chCfg->pol);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_STOP_MODE, chCfg->stopMode);
+  BL_WR_REG(PWMx, PWM_CONFIG, tmpVal);
+
+  /* Config pwm division */
+  BL_WR_REG(PWMx, PWM_CLKDIV, chCfg->clkDiv);
+
+  /* Config pwm period and duty */
+  BL_WR_REG(PWMx, PWM_THRE1, chCfg->threshold1);
+  BL_WR_REG(PWMx, PWM_THRE2, chCfg->threshold2);
+  BL_WR_REG(PWMx, PWM_PERIOD, chCfg->period);
+
+  /* Config interrupt pulse count */
+  tmpVal = BL_RD_REG(PWMx, PWM_INTERRUPT);
+  BL_WR_REG(PWMx, PWM_INTERRUPT, BL_SET_REG_BITS_VAL(tmpVal, PWM_INT_PERIOD_CNT, chCfg->intPulseCnt));
+  // PWM_IntMask(chCfg->ch, PWM_INT_PULSE_CNT, chCfg->intPulseCnt != 0 ? UNMASK : MASK);
+  CPU_Interrupt_Disable(PWM_IRQn);
+
+  return SUCCESS;
+}
+
+/****************************************************************************
+ * @brief  PWM channel update source memory address and len
+ *
+ * @param  ch: PWM channel
+ * @param  period: period
+ * @param  threshold1: threshold1
+ * @param  threshold2: threshold2
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void PWM_Channel_Update(PWM_CH_ID_Type ch, uint16_t period, uint16_t threshold1, uint16_t threshold2) {
+  /* Get channel register */
+  uint32_t PWMx = PWM_Get_Channel_Reg(ch);
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));
+
+  /* Config pwm period and duty */
+  BL_WR_REG(PWMx, PWM_THRE1, threshold1);
+  BL_WR_REG(PWMx, PWM_THRE2, threshold2);
+  BL_WR_REG(PWMx, PWM_PERIOD, period);
+}
+
+/****************************************************************************
+ * @brief  PWM channel update clock divider
+ *
+ * @param  ch: PWM channel
+ * @param  div: Clock divider
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void PWM_Channel_Set_Div(PWM_CH_ID_Type ch, uint16_t div) {
+  /* Get channel register */
+  uint32_t PWMx = PWM_Get_Channel_Reg(ch);
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));
+
+  BL_WR_REG(PWMx, PWM_CLKDIV, div);
+}
+
+/****************************************************************************
+ * @brief  PWM channel update threshold1
+ *
+ * @param  ch: PWM channel
+ * @param  threshold1: threshold1
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void PWM_Channel_Set_Threshold1(PWM_CH_ID_Type ch, uint16_t threshold1) {
+  /* Get channel register */
+  uint32_t PWMx = PWM_Get_Channel_Reg(ch);
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));
+
+  /* Config pwm period and duty */
+  BL_WR_REG(PWMx, PWM_THRE1, threshold1);
+}
+
+/****************************************************************************
+ * @brief  PWM channel update threshold2
+ *
+ * @param  ch: PWM channel
+ * @param  threshold2: threshold2
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void PWM_Channel_Set_Threshold2(PWM_CH_ID_Type ch, uint16_t threshold2) {
+  /* Get channel register */
+  uint32_t PWMx = PWM_Get_Channel_Reg(ch);
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));
+
+  /* Config pwm period and duty */
+  BL_WR_REG(PWMx, PWM_THRE2, threshold2);
+}
+
+/****************************************************************************
+ * @brief  PWM channel update period
+ *
+ * @param  ch: PWM channel
+ * @param  period: period
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void PWM_Channel_Set_Period(PWM_CH_ID_Type ch, uint16_t period) {
+  /* Get channel register */
+  uint32_t PWMx = PWM_Get_Channel_Reg(ch);
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));
+
+  /* Config pwm period and duty */
+  BL_WR_REG(PWMx, PWM_PERIOD, period);
+}
+
+/****************************************************************************
+ * @brief  PWM get configuration
+ *
+ * @param  ch: PWM channel
+ * @param  period: period pointer
+ * @param  threshold1: threshold1 pointer
+ * @param  threshold2: threshold2 pointer
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void PWM_Channel_Get(PWM_CH_ID_Type ch, uint16_t *period, uint16_t *threshold1, uint16_t *threshold2) {
+  uint32_t tmpVal;
+  /* Get channel register */
+  uint32_t PWMx = PWM_Get_Channel_Reg(ch);
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));
+
+  /* get pwm period and duty */
+  tmpVal      = BL_RD_REG(PWMx, PWM_THRE1);
+  *threshold1 = BL_GET_REG_BITS_VAL(tmpVal, PWM_THRE1);
+  tmpVal      = BL_RD_REG(PWMx, PWM_THRE2);
+  *threshold2 = BL_GET_REG_BITS_VAL(tmpVal, PWM_THRE2);
+  tmpVal      = BL_RD_REG(PWMx, PWM_PERIOD);
+  *period     = BL_GET_REG_BITS_VAL(tmpVal, PWM_PERIOD);
+}
+
+/****************************************************************************
+ * @brief  PWM enable
+ *
+ * @param  ch: PWM channel number
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void PWM_Channel_Enable(PWM_CH_ID_Type ch) {
+  uint32_t tmpVal;
+  /* Get channel register */
+  uint32_t PWMx = PWM_Get_Channel_Reg(ch);
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));
+
+  /* Config pwm clock to enable pwm */
+  tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
+  BL_WR_REG(PWMx, PWM_CONFIG, BL_CLR_REG_BIT(tmpVal, PWM_STOP_EN));
+}
+
+/****************************************************************************
+ * @brief  PWM disable
+ *
+ * @param  ch: PWM channel number
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void PWM_Channel_Disable(PWM_CH_ID_Type ch) {
+  uint32_t tmpVal;
+  /* Get channel register */
+  uint32_t PWMx = PWM_Get_Channel_Reg(ch);
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));
+
+  /* Config pwm clock to disable pwm */
+  tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
+  BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN));
+  PWM_IntMask(ch, PWM_INT_PULSE_CNT, MASK);
+}
+
+/****************************************************************************
+ * @brief  PWM channel software mode enable or disable
+ *
+ * @param  ch: PWM channel number
+ * @param  enable: Enable or disable
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void PWM_SW_Mode(PWM_CH_ID_Type ch, BL_Fun_Type enable) {
+  uint32_t tmpVal;
+  /* Get channel register */
+  uint32_t PWMx = PWM_Get_Channel_Reg(ch);
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));
+
+  tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
+  BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, PWM_SW_MODE, enable));
+}
+
+/****************************************************************************
+ * @brief  PWM channel force output high or low
+ *
+ * @param  ch: PWM channel number
+ * @param  value: Output value
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void PWM_SW_Force_Value(PWM_CH_ID_Type ch, uint8_t value) {
+  uint32_t tmpVal;
+  /* Get channel register */
+  uint32_t PWMx = PWM_Get_Channel_Reg(ch);
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));
+
+  tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
+  BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, PWM_SW_FORCE_VAL, value));
+}
+
+/****************************************************************************
+ * @brief  PWM channel force output high
+ *
+ * @param  ch: PWM channel number
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void PWM_Channel_Fource_Output(PWM_CH_ID_Type ch) {
+  uint32_t tmpVal;
+  /* Get channel register */
+  uint32_t PWMx = PWM_Get_Channel_Reg(ch);
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));
+
+  tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
+  BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_SW_MODE));
+}
+
+/****************************************************************************
+ * @brief  Mask/Unmask the PWM interrupt
+ *
+ * @param  ch: PWM channel number
+ * @param  intType: Specifies the interrupt type
+ * @param  intMask: Enable/Disable Specified interrupt type
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void PWM_IntMask(PWM_CH_ID_Type ch, PWM_INT_Type intType, BL_Mask_Type intMask) {
+  uint32_t tmpVal;
+  /* Get channel register */
+  uint32_t PWMx = PWM_Get_Channel_Reg(ch);
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));
+  CHECK_PARAM(IS_PWM_INT_TYPE(intType));
+
+  tmpVal = BL_RD_REG(PWMx, PWM_INTERRUPT);
+
+  switch (intType) {
+  case PWM_INT_PULSE_CNT:
+    if (intMask == UNMASK) {
+      /* UNMASK(Enable) this interrupt */
+      BL_WR_REG(PWMx, PWM_INTERRUPT, BL_SET_REG_BIT(tmpVal, PWM_INT_ENABLE));
+    } else {
+      /* MASK(Disable) this interrupt */
+      BL_WR_REG(PWMx, PWM_INTERRUPT, BL_CLR_REG_BIT(tmpVal, PWM_INT_ENABLE));
+    }
+
+    break;
+
+  case PWM_INT_ALL:
+    if (intMask == UNMASK) {
+      /* UNMASK(Enable) this interrupt */
+      BL_WR_REG(PWMx, PWM_INTERRUPT, BL_SET_REG_BIT(tmpVal, PWM_INT_ENABLE));
+    } else {
+      /* MASK(Disable) this interrupt */
+      BL_WR_REG(PWMx, PWM_INTERRUPT, BL_CLR_REG_BIT(tmpVal, PWM_INT_ENABLE));
+    }
+
+    break;
+
+  default:
+    break;
+  }
+}
+
+/****************************************************************************
+ * @brief  Install PWM interrupt callback function
+ *
+ * @param  ch: PWM channel number
+ * @param  intType: PWM interrupt type
+ * @param  cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
+ *
+ * @return None
+ *
+ *******************************************************************************/
+void PWM_Int_Callback_Install(PWM_CH_ID_Type ch, uint32_t intType, intCallback_Type *cbFun) { PWMIntCbfArra[ch][intType] = cbFun; }
+
+/****************************************************************************
+ * @brief  PWM smart configure according to frequency and duty cycle function
+ *
+ * @param  ch: PWM channel number
+ * @param  frequency: PWM frequency
+ * @param  dutyCycle: PWM duty cycle
+ *
+ * @return SUCCESS or TIMEOUT
+ *
+ *******************************************************************************/
+BL_Err_Type PWM_Smart_Configure(PWM_CH_ID_Type ch, uint32_t frequency, uint8_t dutyCycle) {
+  uint32_t tmpVal;
+  uint16_t clkDiv, period, threshold2;
+  uint32_t timeoutCnt = PWM_STOP_TIMEOUT_COUNT;
+  /* Get channel register */
+  uint32_t PWMx = PWM_Get_Channel_Reg(ch);
+
+  if (frequency <= 32) {
+    clkDiv     = 500;
+    period     = 64000 / frequency;
+    threshold2 = 640 * dutyCycle / frequency;
+  } else if (frequency <= 62) {
+    clkDiv     = 16;
+    period     = 2000000 / frequency;
+    threshold2 = 20000 * dutyCycle / frequency;
+  } else if (frequency <= 124) {
+    clkDiv     = 8;
+    period     = 4000000 / frequency;
+    threshold2 = 40000 * dutyCycle / frequency;
+  } else if (frequency <= 246) {
+    clkDiv     = 4;
+    period     = 8000000 / frequency;
+    threshold2 = 80000 * dutyCycle / frequency;
+  } else if (frequency <= 490) {
+    clkDiv     = 2;
+    period     = 16000000 / frequency;
+    threshold2 = 160000 * dutyCycle / frequency;
+  } else {
+    clkDiv     = 1;
+    period     = 32000000 / frequency;
+    threshold2 = 320000 * dutyCycle / frequency;
+  }
+
+  tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
+  if (BL_GET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL) != PWM_CLK_XCLK) {
+    BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN));
+    while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)) {
+      timeoutCnt--;
+      if (timeoutCnt == 0) {
+        return TIMEOUT;
+      }
+    }
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL, PWM_CLK_XCLK);
+  }
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_OUT_INV, PWM_POL_NORMAL);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_STOP_MODE, PWM_STOP_GRACEFUL);
+  BL_WR_REG(PWMx, PWM_CONFIG, tmpVal);
+
+  /* Config pwm division */
+  BL_WR_REG(PWMx, PWM_CLKDIV, clkDiv);
+
+  /* Config pwm period and duty */
+  BL_WR_REG(PWMx, PWM_PERIOD, period);
+  BL_WR_REG(PWMx, PWM_THRE1, 0);
+  BL_WR_REG(PWMx, PWM_THRE2, threshold2);
+
+  return SUCCESS;
+}
+
+/****************************************************************************
+ * @brief  PWM interrupt function
+ *
+ * @param  None
+ *
+ * @return None
+ *
+ *******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void PWM_IRQHandler(void) { PWM_IntHandler(PWM_IRQn); }
+#endif
+
+/*@} end of group PWM_Public_Functions */
+
+/*@} end of group PWM */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_qdec.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_qdec.c
new file mode 100644
index 00000000..c34af329
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_qdec.c
@@ -0,0 +1,548 @@
+/**
+  ******************************************************************************
+  * @file    bl702_qdec.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_qdec.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  QDEC
+ *  @{
+ */
+
+/** @defgroup  QDEC_Private_Macros
+ *  @{
+ */
+
+/*@} end of group QDEC_Private_Macros */
+
+/** @defgroup  QDEC_Private_Types
+ *  @{
+ */
+
+/*@} end of group QDEC_Private_Types */
+
+/** @defgroup  QDEC_Private_Variables
+ *  @{
+ */
+static const uint32_t qdecAddr[QDEC_ID_MAX] = { QDEC0_BASE, QDEC1_BASE, QDEC2_BASE };
+static intCallback_Type *qdecIntCbfArra[QDEC_ID_MAX][QDEC_INT_ALL] = { { NULL, NULL, NULL, NULL },
+                                                                       { NULL, NULL, NULL, NULL },
+                                                                       { NULL, NULL, NULL, NULL } };
+
+/*@} end of group QDEC_Private_Variables */
+
+/** @defgroup  QDEC_Global_Variables
+ *  @{
+ */
+
+/*@} end of group QDEC_Global_Variables */
+
+/** @defgroup  QDEC_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group QDEC_Private_Fun_Declaration */
+
+/** @defgroup  QDEC_Private_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  QDEC init
+ *
+ * @param  qdecId: QDEC ID
+ * @param  qdecCfg: QDEC config
+ *
+ * @return None
+ *
+*******************************************************************************/
+void QDEC_Init(QDEC_ID_Type qdecId, QDEC_CFG_Type *qdecCfg)
+{
+    uint32_t tmpVal = 0;
+    uint32_t QDECx = qdecAddr[qdecId];
+
+    CHECK_PARAM(IS_QDEC_SAMPLE_MODE_TYPE(qdecCfg->sampleCfg.sampleMod));
+    CHECK_PARAM(IS_QDEC_SAMPLE_PERIOD_TYPE(qdecCfg->sampleCfg.samplePeriod));
+    CHECK_PARAM(IS_QDEC_REPORT_MODE_TYPE(qdecCfg->reportCfg.reportMod));
+    CHECK_PARAM((qdecCfg->ledCfg.ledPeriod) <= 0x1FF);
+    CHECK_PARAM((qdecCfg->deglitchCfg.deglitchStrength) <= 0xF);
+
+    /* qdec_ctrl */
+    tmpVal = BL_RD_REG(QDECx, QDEC0_CTRL0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_SPL_PERIOD, qdecCfg->sampleCfg.samplePeriod);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_RPT_PERIOD, qdecCfg->reportCfg.reportPeriod);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_LED_EN, qdecCfg->ledCfg.ledEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_LED_POL, qdecCfg->ledCfg.ledSwap);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_DEG_EN, qdecCfg->deglitchCfg.deglitchEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_DEG_CNT, qdecCfg->deglitchCfg.deglitchStrength);
+    BL_WR_REG(QDECx, QDEC0_CTRL0, tmpVal);
+
+    /* qdec_ctrl1 */
+    tmpVal = BL_RD_REG(QDECx, QDEC0_CTRL1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_SPL_MODE, qdecCfg->sampleCfg.sampleMod);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_RPT_MODE, qdecCfg->reportCfg.reportMod);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_LED_PERIOD, qdecCfg->ledCfg.ledPeriod);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_ACC_MODE, qdecCfg->accMod);
+    BL_WR_REG(QDECx, QDEC0_CTRL1, tmpVal);
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(QDEC0_IRQn, QDEC0_IRQHandler);
+    Interrupt_Handler_Register(QDEC1_IRQn, QDEC1_IRQHandler);
+    Interrupt_Handler_Register(QDEC2_IRQn, QDEC2_IRQHandler);
+#endif
+}
+
+/****************************************************************************/ /**
+ * @brief  QDEC deinit
+ *
+ * @param  qdecId: QDEC ID
+ *
+ * @return None
+ *
+*******************************************************************************/
+void QDEC_DeInit(QDEC_ID_Type qdecId)
+{
+    uint32_t tmpVal = 0;
+    uint32_t QDECx = qdecAddr[qdecId];
+
+    /* deconfig qdec */
+    tmpVal = BL_RD_REG(QDECx, QDEC0_CTRL0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_RPT_PERIOD, 10);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_SPL_PERIOD, 2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_DEG_CNT, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_DEG_EN, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_LED_POL, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_LED_EN, 0);
+    BL_WR_REG(QDECx, QDEC0_CTRL0, tmpVal);
+    tmpVal = BL_RD_REG(QDECx, QDEC0_CTRL1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_LED_PERIOD, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_INPUT_SWAP, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_RPT_MODE, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_SPL_MODE, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_ACC_MODE, 1);
+    BL_WR_REG(QDECx, QDEC0_CTRL1, tmpVal);
+
+    /* enable qdec */
+    tmpVal = BL_RD_REG(QDECx, QDEC0_CTRL0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_EN, 1);
+    BL_WR_REG(QDECx, QDEC0_CTRL0, tmpVal);
+
+    /* deconfig interrupt */
+    tmpVal = BL_RD_REG(QDECx, QDEC0_INT_EN);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_OVERFLOW_EN, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_DBL_RDY_EN, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_SPL_RDY_EN, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_RPT_RDY_EN, 1);
+    BL_WR_REG(QDECx, QDEC0_INT_EN, tmpVal);
+
+    /* clear status */
+    tmpVal = BL_RD_REG(QDECx, QDEC0_INT_CLR);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_OVERFLOW_CLR, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_DBL_RDY_CLR, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_SPL_RDY_CLR, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_RPT_RDY_CLR, 1);
+    BL_WR_REG(QDECx, QDEC0_INT_STS, tmpVal);
+
+    /* clear value */
+    tmpVal = BL_RD_REG(QDECx, QDEC0_VALUE);
+
+    /* disable qdec */
+    tmpVal = BL_RD_REG(QDECx, QDEC0_CTRL0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_EN, 0);
+    BL_WR_REG(QDECx, QDEC0_CTRL0, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  QDEC enable
+ *
+ * @param  qdecId: QDEC ID
+ *
+ * @return None
+ *
+*******************************************************************************/
+void QDEC_Enable(QDEC_ID_Type qdecId)
+{
+    uint32_t tmpVal = 0;
+    uint32_t QDECx = qdecAddr[qdecId];
+
+    /* qdec_ctrl */
+    tmpVal = BL_RD_REG(QDECx, QDEC0_CTRL0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, QDEC_EN);
+    BL_WR_REG(QDECx, QDEC0_CTRL0, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  QDEC disable
+ *
+ * @param  qdecId: QDEC ID
+ *
+ * @return None
+ *
+*******************************************************************************/
+void QDEC_Disable(QDEC_ID_Type qdecId)
+{
+    uint32_t tmpVal = 0;
+    uint32_t QDECx = qdecAddr[qdecId];
+
+    /* qdec_ctrl */
+    tmpVal = BL_RD_REG(QDECx, QDEC0_CTRL0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, QDEC_EN);
+    BL_WR_REG(QDECx, QDEC0_CTRL0, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  set QDEC interrupt mask
+ *
+ * @param  qdecId: QDEC ID
+ * @param  intType: QDEC interrupt type
+ * @param  intMask: MASK or UNMASK
+ *
+ * @return None
+ *
+*******************************************************************************/
+void QDEC_SetIntMask(QDEC_ID_Type qdecId, QDEC_INT_Type intType, BL_Mask_Type intMask)
+{
+    uint32_t tmpVal = 0;
+    uint32_t QDECx = qdecAddr[qdecId];
+
+    CHECK_PARAM(IS_QDEC_INT_TYPE(intType));
+
+    /* qdec_int_en */
+    tmpVal = BL_RD_REG(QDECx, QDEC0_INT_EN);
+
+    switch (intType) {
+        case QDEC_INT_REPORT:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_RPT_RDY_EN, (intMask ? 0 : 1));
+            break;
+
+        case QDEC_INT_SAMPLE:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_SPL_RDY_EN, (intMask ? 0 : 1));
+            break;
+
+        case QDEC_INT_ERROR:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_DBL_RDY_EN, (intMask ? 0 : 1));
+            break;
+
+        case QDEC_INT_OVERFLOW:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_OVERFLOW_EN, (intMask ? 0 : 1));
+            break;
+
+        default:
+            break;
+    }
+
+    BL_WR_REG(QDECx, QDEC0_INT_EN, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  get QDEC interrupt mask
+ *
+ * @param  qdecId: QDEC ID
+ * @param  intType: QDEC interrupt type
+ *
+ * @return MASK or UNMASK
+ *
+*******************************************************************************/
+BL_Mask_Type QDEC_GetIntMask(QDEC_ID_Type qdecId, QDEC_INT_Type intType)
+{
+    uint32_t tmpVal = 0;
+    uint32_t QDECx = qdecAddr[qdecId];
+
+    CHECK_PARAM(IS_QDEC_INT_TYPE(intType));
+
+    /* qdec_int_en */
+    tmpVal = BL_RD_REG(QDECx, QDEC0_INT_EN);
+
+    switch (intType) {
+        case QDEC_INT_REPORT:
+            return BL_GET_REG_BITS_VAL(tmpVal, QDEC_RPT_RDY_EN) ? UNMASK : MASK;
+
+        case QDEC_INT_SAMPLE:
+            return BL_GET_REG_BITS_VAL(tmpVal, QDEC_SPL_RDY_EN) ? UNMASK : MASK;
+
+        case QDEC_INT_ERROR:
+            return BL_GET_REG_BITS_VAL(tmpVal, QDEC_DBL_RDY_EN) ? UNMASK : MASK;
+
+        case QDEC_INT_OVERFLOW:
+            return BL_GET_REG_BITS_VAL(tmpVal, QDEC_OVERFLOW_EN) ? UNMASK : MASK;
+
+        default:
+            return UNMASK;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  QDEC interrupt callback install
+ *
+ * @param  qdecId: QDEC ID
+ * @param  intType: QDEC interrupt type
+ * @param  cbFun: interrupt callback
+ *
+ * @return None
+ *
+*******************************************************************************/
+void QDEC_Int_Callback_Install(QDEC_ID_Type qdecId, QDEC_INT_Type intType, intCallback_Type *cbFun)
+{
+    qdecIntCbfArra[qdecId][intType] = cbFun;
+}
+
+/****************************************************************************/ /**
+ * @brief  QDEC get interrupt status
+ *
+ * @param  qdecId: QDEC ID
+ * @param  intType: QDEC interrupt type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type QDEC_Get_Int_Status(QDEC_ID_Type qdecId, QDEC_INT_Type intType)
+{
+    uint32_t tmpVal = 0;
+    uint32_t QDECx = qdecAddr[qdecId];
+
+    CHECK_PARAM(IS_QDEC_INT_TYPE(intType));
+
+    /* qdec_int_sts */
+    tmpVal = BL_RD_REG(QDECx, QDEC0_INT_STS);
+
+    switch (intType) {
+        case QDEC_INT_REPORT:
+            return BL_GET_REG_BITS_VAL(tmpVal, QDEC_RPT_RDY_STS) ? SET : RESET;
+
+        case QDEC_INT_SAMPLE:
+            return BL_GET_REG_BITS_VAL(tmpVal, QDEC_SPL_RDY_STS) ? SET : RESET;
+
+        case QDEC_INT_ERROR:
+            return BL_GET_REG_BITS_VAL(tmpVal, QDEC_DBL_RDY_STS) ? SET : RESET;
+
+        case QDEC_INT_OVERFLOW:
+            return BL_GET_REG_BITS_VAL(tmpVal, QDEC_OVERFLOW_STS) ? SET : RESET;
+
+        default:
+            return RESET;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  QDEC clear interrupt status
+ *
+ * @param  qdecId: QDEC ID
+ * @param  intType: QDEC interrupt type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void QDEC_Clr_Int_Status(QDEC_ID_Type qdecId, QDEC_INT_Type intType)
+{
+    uint32_t tmpVal = 0;
+    uint32_t QDECx = qdecAddr[qdecId];
+
+    CHECK_PARAM(IS_QDEC_INT_TYPE(intType));
+
+    /* qdec_int_clr */
+    tmpVal = BL_RD_REG(QDECx, QDEC0_INT_CLR);
+
+    switch (intType) {
+        case QDEC_INT_REPORT:
+            tmpVal = BL_SET_REG_BIT(tmpVal, QDEC_RPT_RDY_CLR);
+            break;
+
+        case QDEC_INT_SAMPLE:
+            tmpVal = BL_SET_REG_BIT(tmpVal, QDEC_SPL_RDY_CLR);
+            break;
+
+        case QDEC_INT_ERROR:
+            tmpVal = BL_SET_REG_BIT(tmpVal, QDEC_DBL_RDY_CLR);
+            break;
+
+        case QDEC_INT_OVERFLOW:
+            tmpVal = BL_SET_REG_BIT(tmpVal, QDEC_OVERFLOW_CLR);
+            break;
+
+        default:
+            break;
+    }
+
+    BL_WR_REG(QDECx, QDEC0_INT_CLR, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  QDEC get sample direction
+ *
+ * @param  qdecId: QDEC ID
+ *
+ * @return None
+ *
+*******************************************************************************/
+QDEC_DIRECTION_Type QDEC_Get_Sample_Direction(QDEC_ID_Type qdecId)
+{
+    uint32_t tmpVal = 0;
+    uint32_t QDECx = qdecAddr[qdecId];
+
+    /* qdec_value */
+    tmpVal = BL_RD_REG(QDECx, QDEC0_VALUE);
+
+    return (QDEC_DIRECTION_Type)BL_GET_REG_BITS_VAL(tmpVal, QDEC_SPL_VAL);
+}
+
+/****************************************************************************/ /**
+ * @brief  QDEC get error count
+ *
+ * @param  qdecId: QDEC ID
+ *
+ * @return None
+ *
+*******************************************************************************/
+uint8_t QDEC_Get_Err_Cnt(QDEC_ID_Type qdecId)
+{
+    uint32_t tmpVal = 0;
+    uint32_t QDECx = qdecAddr[qdecId];
+
+    /* qdec_value */
+    tmpVal = BL_RD_REG(QDECx, QDEC0_VALUE);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, QDEC_ACC2_VAL);
+}
+
+/****************************************************************************/ /**
+ * @brief  QDEC get sample value
+ *
+ * @param  qdecId: QDEC ID
+ *
+ * @return None
+ *
+*******************************************************************************/
+uint16_t QDEC_Get_Sample_Val(QDEC_ID_Type qdecId)
+{
+    uint32_t tmpVal = 0;
+    uint32_t QDECx = qdecAddr[qdecId];
+
+    /* qdec_value */
+    tmpVal = BL_RD_REG(QDECx, QDEC0_VALUE);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, QDEC_ACC1_VAL);
+}
+
+/****************************************************************************/ /**
+ * @brief  QDEC interrupt handler
+ *
+ * @param  qdecId: QDEC ID
+ * @param  intType: QDEC interrupt type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void QDEC_IntHandler(QDEC_ID_Type qdecId, QDEC_INT_Type intType)
+{
+    if (SET == QDEC_Get_Int_Status(qdecId, intType)) {
+        QDEC_Clr_Int_Status(qdecId, intType);
+
+        if (qdecIntCbfArra[qdecId][intType] != NULL) {
+            qdecIntCbfArra[qdecId][intType]();
+        }
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  QDEC0 interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void QDEC0_IRQHandler(void)
+{
+    QDEC_INT_Type intType;
+
+    for (intType = QDEC_INT_REPORT; intType < QDEC_INT_ALL; intType++) {
+        if (UNMASK == QDEC_GetIntMask(QDEC0_ID, intType)) {
+            QDEC_IntHandler(QDEC0_ID, intType);
+        }
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  QDEC1 interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void QDEC1_IRQHandler(void)
+{
+    QDEC_INT_Type intType;
+
+    for (intType = QDEC_INT_REPORT; intType < QDEC_INT_ALL; intType++) {
+        if (UNMASK == QDEC_GetIntMask(QDEC1_ID, intType)) {
+            QDEC_IntHandler(QDEC1_ID, intType);
+        }
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  QDEC2 interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void QDEC2_IRQHandler(void)
+{
+    QDEC_INT_Type intType;
+
+    for (intType = QDEC_INT_REPORT; intType < QDEC_INT_ALL; intType++) {
+        if (UNMASK == QDEC_GetIntMask(QDEC2_ID, intType)) {
+            QDEC_IntHandler(QDEC2_ID, intType);
+        }
+    }
+}
+#endif
+
+/*@} end of group QDEC_Private_Functions */
+
+/*@} end of group QDEC */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_romapi.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_romapi.c
new file mode 100644
index 00000000..73040c43
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_romapi.c
@@ -0,0 +1,1106 @@
+#include "bl702_romdriver.h"
+
+/******************************************************************************/
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    AON_Power_On_MBG(void)
+{
+    return RomDriver_AON_Power_On_MBG();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    AON_Power_Off_MBG(void)
+{
+    return RomDriver_AON_Power_Off_MBG();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    AON_Power_On_XTAL(void)
+{
+    return RomDriver_AON_Power_On_XTAL();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut)
+{
+    return RomDriver_AON_Set_Xtal_CapCode(capIn, capOut);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    AON_Power_Off_XTAL(void)
+{
+    return RomDriver_AON_Power_Off_XTAL();
+}
+/******************************************************************************/
+
+/******************************************************************************/
+__ALWAYS_INLINE ATTR_TCM_SECTION void ASM_Delay_Us(uint32_t core, uint32_t cnt)
+{
+    RomDriver_ASM_Delay_Us(core, cnt);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void BL702_Delay_US(uint32_t cnt)
+{
+    RomDriver_BL702_Delay_US(cnt);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void BL702_Delay_MS(uint32_t cnt)
+{
+    RomDriver_BL702_Delay_MS(cnt);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void *BL702_MemCpy(void *dst, const void *src, uint32_t n)
+{
+    return RomDriver_BL702_MemCpy(dst, src, n);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    uint32_t *
+    BL702_MemCpy4(uint32_t *dst, const uint32_t *src, uint32_t n)
+{
+    return RomDriver_BL702_MemCpy4(dst, src, n);
+}
+
+// __ALWAYS_INLINE ATTR_TCM_SECTION
+// void* BL702_MemCpy_Fast(void *pdst, const void *psrc, uint32_t n) {
+//     return RomDriver_BL702_MemCpy_Fast(pdst, psrc, n);
+// }
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void *ARCH_MemCpy_Fast(void *pdst, const void *psrc, uint32_t n)
+{
+    return RomDriver_ARCH_MemCpy_Fast(pdst, psrc, n);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void *BL702_MemSet(void *s, uint8_t c, uint32_t n)
+{
+    return RomDriver_BL702_MemSet(s, c, n);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    uint32_t *
+    BL702_MemSet4(uint32_t *dst, const uint32_t val, uint32_t n)
+{
+    return RomDriver_BL702_MemSet4(dst, val, n);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION int BL702_MemCmp(const void *s1, const void *s2, uint32_t n)
+{
+    return RomDriver_BL702_MemCmp(s1, s2, n);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    uint32_t
+    BFLB_Soft_CRC32(void *dataIn, uint32_t len)
+{
+    return RomDriver_BFLB_Soft_CRC32(dataIn, len);
+}
+/******************************************************************************/
+
+/******************************************************************************/
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    GLB_ROOT_CLK_Type
+    GLB_Get_Root_CLK_Sel(void)
+{
+    return RomDriver_GLB_Get_Root_CLK_Sel();
+}
+#if 0
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv)
+{
+    return RomDriver_GLB_Set_System_CLK_Div(hclkDiv, bclkDiv);
+}
+#endif
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    uint8_t
+    GLB_Get_BCLK_Div(void)
+{
+    return RomDriver_GLB_Get_BCLK_Div();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    uint8_t
+    GLB_Get_HCLK_Div(void)
+{
+    return RomDriver_GLB_Get_HCLK_Div();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    Update_SystemCoreClockWith_XTAL(GLB_DLL_XTAL_Type xtalType)
+{
+    return RomDriver_Update_SystemCoreClockWith_XTAL(xtalType);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    GLB_Set_System_CLK(GLB_DLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq)
+{
+    return RomDriver_GLB_Set_System_CLK(xtalType, clkFreq);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    System_Core_Clock_Update_From_RC32M(void)
+{
+    return RomDriver_System_Core_Clock_Update_From_RC32M();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div)
+{
+    return RomDriver_GLB_Set_SF_CLK(enable, clkSel, div);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    GLB_Power_Off_DLL(void)
+{
+    return RomDriver_GLB_Power_Off_DLL();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    GLB_Power_On_DLL(GLB_DLL_XTAL_Type xtalType)
+{
+    return RomDriver_GLB_Power_On_DLL(xtalType);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    GLB_Enable_DLL_All_Clks(void)
+{
+    return RomDriver_GLB_Enable_DLL_All_Clks();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    GLB_Enable_DLL_Clk(GLB_DLL_CLK_Type dllClk)
+{
+    return RomDriver_GLB_Enable_DLL_Clk(dllClk);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    GLB_Disable_DLL_All_Clks(void)
+{
+    return RomDriver_GLB_Disable_DLL_All_Clks();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    GLB_Disable_DLL_Clk(GLB_DLL_CLK_Type dllClk)
+{
+    return RomDriver_GLB_Disable_DLL_Clk(dllClk);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    GLB_SW_System_Reset(void)
+{
+    return RomDriver_GLB_SW_System_Reset();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    GLB_SW_CPU_Reset(void)
+{
+    return RomDriver_GLB_SW_CPU_Reset();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    GLB_SW_POR_Reset(void)
+{
+    return RomDriver_GLB_SW_POR_Reset();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    GLB_Select_Internal_Flash(void)
+{
+    return RomDriver_GLB_Select_Internal_Flash();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    GLB_Swap_Flash_Pin(void)
+{
+    return RomDriver_GLB_Swap_Flash_Pin();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    GLB_Swap_Flash_CS_IO2_Pin(void)
+{
+    return RomDriver_GLB_Swap_Flash_CS_IO2_Pin();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    GLB_Swap_Flash_IO0_IO3_Pin(void)
+{
+    return RomDriver_GLB_Swap_Flash_IO0_IO3_Pin();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    GLB_Select_Internal_PSram(void)
+{
+    return RomDriver_GLB_Select_Internal_PSram();
+}
+
+/* aon pads GPIO9~GPIO13 IE controlled by HBN reg_aon_pad_ie_smt, abandon romdriver for this reason */
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg)
+{
+    return RomDriver_GLB_GPIO_Init(cfg);
+}
+#endif
+
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin)
+{
+    return RomDriver_GLB_GPIO_OUTPUT_Enable(gpioPin);
+}
+#endif
+
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin)
+{
+    return RomDriver_GLB_GPIO_OUTPUT_Disable(gpioPin);
+}
+#endif
+
+/* aon pads GPIO9~GPIO13 IE controlled by HBN reg_aon_pad_ie_smt, abandon romdriver for this reason */
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin)
+{
+    return RomDriver_GLB_GPIO_Set_HZ(gpioPin);
+}
+#endif
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    GLB_Deswap_Flash_Pin(void)
+{
+    return RomDriver_GLB_Deswap_Flash_Pin();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    GLB_Select_External_Flash(void)
+{
+    return RomDriver_GLB_Select_External_Flash();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    uint8_t
+    GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin)
+{
+    return RomDriver_GLB_GPIO_Get_Fun(gpioPin);
+}
+/******************************************************************************/
+
+/******************************************************************************/
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Sts_Type
+    EF_Ctrl_Busy(void)
+{
+    return RomDriver_EF_Ctrl_Busy();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void EF_Ctrl_Sw_AHB_Clk_0(void)
+{
+    RomDriver_EF_Ctrl_Sw_AHB_Clk_0();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void EF_Ctrl_Load_Efuse_R0(void)
+{
+    RomDriver_EF_Ctrl_Load_Efuse_R0();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void EF_Ctrl_Clear(uint32_t index, uint32_t len)
+{
+    RomDriver_EF_Ctrl_Clear(index, len);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    uint8_t
+    EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len)
+{
+    return RomDriver_EF_Ctrl_Get_Trim_Parity(val, len);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION void EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim)
+{
+    RomDriver_EF_Ctrl_Read_RC32K_Trim(trim);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION void EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim)
+{
+    RomDriver_EF_Ctrl_Read_RC32M_Trim(trim);
+}
+/******************************************************************************/
+
+/******************************************************************************/
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    PDS_Trim_RC32M(void)
+{
+    return RomDriver_PDS_Trim_RC32M();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    PDS_Select_RC32M_As_PLL_Ref(void)
+{
+    return RomDriver_PDS_Select_RC32M_As_PLL_Ref();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    PDS_Select_XTAL_As_PLL_Ref(void)
+{
+    return RomDriver_PDS_Select_XTAL_As_PLL_Ref();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType)
+{
+    return RomDriver_PDS_Power_On_PLL(xtalType);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    PDS_Enable_PLL_All_Clks(void)
+{
+    return RomDriver_PDS_Enable_PLL_All_Clks();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    PDS_Disable_PLL_All_Clks(void)
+{
+    return RomDriver_PDS_Disable_PLL_All_Clks();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk)
+{
+    return RomDriver_PDS_Enable_PLL_Clk(pllClk);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk)
+{
+    return RomDriver_PDS_Disable_PLL_Clk(pllClk);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    PDS_Power_Off_PLL(void)
+{
+    return RomDriver_PDS_Power_Off_PLL();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void PDS_Reset(void)
+{
+    RomDriver_PDS_Reset();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void PDS_Enable(PDS_CFG_Type *cfg, uint32_t pdsSleepCnt)
+{
+    RomDriver_PDS_Enable(cfg, pdsSleepCnt);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void PDS_Auto_Time_Config(uint32_t sleepDuration)
+{
+    RomDriver_PDS_Auto_Time_Config(sleepDuration);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void PDS_Auto_Enable(PDS_AUTO_POWER_DOWN_CFG_Type *powerCfg, PDS_AUTO_NORMAL_CFG_Type *normalCfg, BL_Fun_Type enable)
+{
+    RomDriver_PDS_Auto_Enable(powerCfg, normalCfg, enable);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void PDS_Manual_Force_Turn_Off(PDS_FORCE_Type domain)
+{
+    RomDriver_PDS_Manual_Force_Turn_Off(domain);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void PDS_Manual_Force_Turn_On(PDS_FORCE_Type domain)
+{
+    RomDriver_PDS_Manual_Force_Turn_On(domain);
+}
+/******************************************************************************/
+
+/******************************************************************************/
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+void HBN_Enable(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel)
+{
+    RomDriver_HBN_Enable(aGPIOIeCfg, ldoLevel, hbnLevel);
+}
+#endif
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    HBN_Reset(void)
+{
+    return RomDriver_HBN_Reset();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    HBN_GPIO_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type dlyEn, uint8_t dlySec, HBN_INT_Type gpioIrq, BL_Mask_Type gpioMask)
+{
+    return RomDriver_HBN_GPIO_Dbg_Pull_Cfg(pupdEn, dlyEn, dlySec, gpioIrq, gpioMask);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    HBN_Trim_RC32K(void)
+{
+    return RomDriver_HBN_Trim_RC32K();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk)
+{
+    return RomDriver_HBN_Set_ROOT_CLK_Sel(rootClk);
+}
+/******************************************************************************/
+
+/******************************************************************************/
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset)
+{
+    return RomDriver_XIP_SFlash_State_Save(pFlashCfg, offset);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t offset)
+{
+    return RomDriver_XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t startaddr, uint32_t endaddr)
+{
+    return RomDriver_XIP_SFlash_Erase_Need_Lock(pFlashCfg, ioMode, startaddr, endaddr);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len)
+{
+    return RomDriver_XIP_SFlash_Write_Need_Lock(pFlashCfg, ioMode, addr, data, len);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len)
+{
+    return RomDriver_XIP_SFlash_Read_Need_Lock(pFlashCfg, ioMode, addr, data, len);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t *data)
+{
+    return RomDriver_XIP_SFlash_GetJedecId_Need_Lock(pFlashCfg, ioMode, data);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t *data)
+{
+    return RomDriver_XIP_SFlash_GetDeviceId_Need_Lock(pFlashCfg, ioMode, data);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t *data, uint8_t idLen)
+{
+    return RomDriver_XIP_SFlash_GetUniqueId_Need_Lock(pFlashCfg, ioMode, data, idLen);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len)
+{
+    return RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock(addr, data, len);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION int XIP_SFlash_Read_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *dst, int len)
+{
+    return RomDriver_XIP_SFlash_Read_With_Lock(pFlashCfg, ioMode, addr, dst, len);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION int XIP_SFlash_Write_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *src, int len)
+{
+    return RomDriver_XIP_SFlash_Write_With_Lock(pFlashCfg, ioMode, addr, src, len);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION int XIP_SFlash_Erase_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, int len)
+{
+    return RomDriver_XIP_SFlash_Erase_With_Lock(pFlashCfg, ioMode, addr, len);
+}
+/******************************************************************************/
+
+/******************************************************************************/
+__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg)
+{
+    RomDriver_SFlash_Init(pSfCtrlCfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode)
+{
+    return RomDriver_SFlash_SetSPIMode(mode);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen)
+{
+    return RomDriver_SFlash_Read_Reg(flashCfg, regIndex, regValue, regLen);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen)
+{
+    return RomDriver_SFlash_Write_Reg(flashCfg, regIndex, regValue, regLen);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen)
+{
+    return RomDriver_SFlash_Read_Reg_With_Cmd(flashCfg, readRegCmd, regValue, regLen);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen)
+{
+    return RomDriver_SFlash_Write_Reg_With_Cmd(flashCfg, writeRegCmd, regValue, regLen);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Sts_Type
+    SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg)
+{
+    return RomDriver_SFlash_Busy(flashCfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg)
+{
+    return RomDriver_SFlash_Write_Enable(flashCfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg)
+{
+    return RomDriver_SFlash_Qspi_Enable(flashCfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg)
+{
+    RomDriver_SFlash_Volatile_Reg_Write_Enable(flashCfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg)
+{
+    return RomDriver_SFlash_Chip_Erase(flashCfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum)
+{
+    return RomDriver_SFlash_Sector_Erase(flashCfg, secNum);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum)
+{
+    return RomDriver_SFlash_Blk32_Erase(flashCfg, blkNum);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum)
+{
+    return RomDriver_SFlash_Blk64_Erase(flashCfg, blkNum);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr)
+{
+    return RomDriver_SFlash_Erase(flashCfg, startaddr, endaddr);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len)
+{
+    return RomDriver_SFlash_Program(flashCfg, ioMode, addr, data, len);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_GetUniqueId(uint8_t *data, uint8_t idLen)
+{
+    RomDriver_SFlash_GetUniqueId(data, idLen);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data)
+{
+    RomDriver_SFlash_GetJedecId(flashCfg, data);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_GetDeviceId(uint8_t *data)
+{
+    RomDriver_SFlash_GetDeviceId(data);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_Powerdown(void)
+{
+    RomDriver_SFlash_Powerdown();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg)
+{
+    RomDriver_SFlash_Releae_Powerdown(flashCfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead)
+{
+    return RomDriver_SFlash_Restore_From_Powerdown(pFlashCfg, flashContRead);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg)
+{
+    RomDriver_SFlash_SetBurstWrap(flashCfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg)
+{
+    RomDriver_SFlash_DisableBurstWrap(flashCfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg)
+{
+    return RomDriver_SFlash_Software_Reset(flashCfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg)
+{
+    return RomDriver_SFlash_Reset_Continue_Read(flashCfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg,
+                         SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len)
+{
+    return RomDriver_SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, addr, len);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead)
+{
+    return RomDriver_SFlash_IDbus_Read_Enable(flashCfg, ioMode, contRead);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg,
+                             SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint8_t wayDisable)
+{
+    return RomDriver_SFlash_Cache_Read_Enable(flashCfg, ioMode, contRead, wayDisable);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_Cache_Read_Disable(void)
+{
+    RomDriver_SFlash_Cache_Read_Disable();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    SFlash_Read(SPI_Flash_Cfg_Type *flashCfg,
+                SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len)
+{
+    return RomDriver_SFlash_Read(flashCfg, ioMode, contRead, addr, data, len);
+}
+/******************************************************************************/
+
+/******************************************************************************/
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    L1C_Cache_Enable_Set(uint8_t wayDisable)
+{
+    return RomDriver_L1C_Cache_Enable_Set(wayDisable);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void L1C_Cache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn)
+{
+    RomDriver_L1C_Cache_Write_Set(wtEn, wbEn, waEn);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    L1C_Cache_Flush(uint8_t wayDisable)
+{
+    return RomDriver_L1C_Cache_Flush(wayDisable);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void L1C_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh)
+{
+    RomDriver_L1C_Cache_Hit_Count_Get(hitCountLow, hitCountHigh);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    uint32_t
+    L1C_Cache_Miss_Count_Get(void)
+{
+    return RomDriver_L1C_Cache_Miss_Count_Get();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void L1C_Cache_Read_Disable(void)
+{
+    RomDriver_L1C_Cache_Read_Disable();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    L1C_Set_Wrap(BL_Fun_Type wrap)
+{
+    return RomDriver_L1C_Set_Wrap(wrap);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    L1C_Set_Way_Disable(uint8_t disableVal)
+{
+    return RomDriver_L1C_Set_Way_Disable(disableVal);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    L1C_IROM_2T_Access_Set(uint8_t enable)
+{
+    return RomDriver_L1C_IROM_2T_Access_Set(enable);
+}
+/******************************************************************************/
+
+/******************************************************************************/
+__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg)
+{
+    RomDriver_SF_Ctrl_Enable(cfg);
+}
+
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+void SF_Ctrl_Psram_Init(SF_Ctrl_Psram_Cfg *sfCtrlPsramCfg)
+{
+    RomDriver_SF_Ctrl_Psram_Init(sfCtrlPsramCfg);
+}
+#endif
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    uint8_t
+    SF_Ctrl_Get_Clock_Delay(void)
+{
+    return RomDriver_SF_Ctrl_Get_Clock_Delay();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Set_Clock_Delay(uint8_t delay)
+{
+    RomDriver_SF_Ctrl_Set_Clock_Delay(delay);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg)
+{
+    RomDriver_SF_Ctrl_Cmds_Set(cmdsCfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner)
+{
+    RomDriver_SF_Ctrl_Set_Owner(owner);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Disable(void)
+{
+    RomDriver_SF_Ctrl_Disable();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Select sel)
+{
+    RomDriver_SF_Ctrl_Select_Pad(sel);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Select_Bank(SF_Ctrl_Select sel)
+{
+    RomDriver_SF_Ctrl_Select_Bank(sel);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Enable_BE(void)
+{
+    RomDriver_SF_Ctrl_AES_Enable_BE();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Enable_LE(void)
+{
+    RomDriver_SF_Ctrl_AES_Enable_LE();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable,
+                                                             uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked)
+{
+    RomDriver_SF_Ctrl_AES_Set_Region(region, enable, hwKey, startAddr, endAddr, locked);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType)
+{
+    RomDriver_SF_Ctrl_AES_Set_Key(region, key, keyType);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType)
+{
+    RomDriver_SF_Ctrl_AES_Set_Key_BE(region, key, keyType);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset)
+{
+    RomDriver_SF_Ctrl_AES_Set_IV(region, iv, addrOffset);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset)
+{
+    RomDriver_SF_Ctrl_AES_Set_IV_BE(region, iv, addrOffset);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Enable(void)
+{
+    RomDriver_SF_Ctrl_AES_Enable();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Disable(void)
+{
+    RomDriver_SF_Ctrl_AES_Disable();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    uint8_t
+    SF_Ctrl_Is_AES_Enable(void)
+{
+    return RomDriver_SF_Ctrl_Is_AES_Enable();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset)
+{
+    RomDriver_SF_Ctrl_Set_Flash_Image_Offset(addrOffset);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    uint32_t
+    SF_Ctrl_Get_Flash_Image_Offset(void)
+{
+    return RomDriver_SF_Ctrl_Get_Flash_Image_Offset();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType)
+{
+    RomDriver_SF_Ctrl_Select_Clock(sahbType);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg)
+{
+    RomDriver_SF_Ctrl_SendCmd(cfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid)
+{
+    RomDriver_SF_Ctrl_Flash_Read_Icache_Set(cfg, cmdValid);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Psram_Write_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid)
+{
+    RomDriver_SF_Ctrl_Psram_Write_Icache_Set(cfg, cmdValid);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Psram_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid)
+{
+    RomDriver_SF_Ctrl_Psram_Read_Icache_Set(cfg, cmdValid);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Sts_Type
+    SF_Ctrl_GetBusyState(void)
+{
+    return RomDriver_SF_Ctrl_GetBusyState();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin)
+{
+    RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio(extFlashPin);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin)
+{
+    RomDriver_SF_Cfg_Init_Ext_Flash_Gpio(extFlashPin);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg)
+{
+    return RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg);
+}
+
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+void SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg, uint8_t restoreDefault)
+{
+    RomDriver_SF_Cfg_Init_Flash_Gpio(flashPinCfg, restoreDefault);
+}
+#endif
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    uint32_t
+    SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault,
+                          SPI_Flash_Cfg_Type *pFlashCfg)
+{
+    return RomDriver_SF_Cfg_Flash_Identify(callFromFlash, autoScan, flashPinCfg, restoreDefault, pFlashCfg);
+}
+/******************************************************************************/
+
+/******************************************************************************/
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+void Psram_Init(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Psram_Cfg *sfCtrlPsramCfg)
+{
+    RomDriver_Psram_Init(psramCfg, cmdsCfg, sfCtrlPsramCfg);
+}
+#endif
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void Psram_ReadReg(SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue)
+{
+    RomDriver_Psram_ReadReg(psramCfg, regValue);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void Psram_WriteReg(SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue)
+{
+    RomDriver_Psram_WriteReg(psramCfg, regValue);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    Psram_SetDriveStrength(SPI_Psram_Cfg_Type *psramCfg)
+{
+    return RomDriver_Psram_SetDriveStrength(psramCfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    Psram_SetBurstWrap(SPI_Psram_Cfg_Type *psramCfg)
+{
+    return RomDriver_Psram_SetBurstWrap(psramCfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void Psram_ReadId(SPI_Psram_Cfg_Type *psramCfg, uint8_t *data)
+{
+    RomDriver_Psram_ReadId(psramCfg, data);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    Psram_EnterQuadMode(SPI_Psram_Cfg_Type *psramCfg)
+{
+    return RomDriver_Psram_EnterQuadMode(psramCfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    Psram_ExitQuadMode(SPI_Psram_Cfg_Type *psramCfg)
+{
+    return RomDriver_Psram_ExitQuadMode(psramCfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    Psram_ToggleBurstLength(SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode)
+{
+    return RomDriver_Psram_ToggleBurstLength(psramCfg, ctrlMode);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    Psram_SoftwareReset(SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode)
+{
+    return RomDriver_Psram_SoftwareReset(psramCfg, ctrlMode);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    Psram_Set_IDbus_Cfg(SPI_Psram_Cfg_Type *psramCfg,
+                        SF_Ctrl_IO_Type ioMode, uint32_t addr, uint32_t len)
+{
+    return RomDriver_Psram_Set_IDbus_Cfg(psramCfg, ioMode, addr, len);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    Psram_Cache_Write_Set(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode,
+                          BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn)
+{
+    return RomDriver_Psram_Cache_Write_Set(psramCfg, ioMode, wtEn, wbEn, waEn);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    Psram_Write(SPI_Psram_Cfg_Type *psramCfg,
+                SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len)
+{
+    return RomDriver_Psram_Write(psramCfg, ioMode, addr, data, len);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    Psram_Read(SPI_Psram_Cfg_Type *psramCfg,
+               SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len)
+{
+    return RomDriver_Psram_Read(psramCfg, ioMode, addr, data, len);
+}
+/******************************************************************************/
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_romdriver.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_romdriver.c
new file mode 100644
index 00000000..6910921b
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_romdriver.c
@@ -0,0 +1,246 @@
+#include "bl702_romdriver.h"
+#include 
+
+/** @addtogroup  BL702_Periph_Driver
+ *  @{
+ */
+
+/** @defgroup ROMDRIVER
+ *  @brief ROMDRIVER common functions
+ *  @{
+ */
+
+/** @defgroup ROMDRIVER_Private_Type
+ *  @{
+ */
+uint32_t const romDriverTable[] = {
+    0x07020001,
+    0x00000000,
+    0x00000000,
+    0x00000000,
+
+    [ROM_API_INDEX_AON_Power_On_MBG]     = (uint32_t)AON_Power_On_MBG,
+    [ROM_API_INDEX_AON_Power_Off_MBG]    = (uint32_t)AON_Power_Off_MBG,
+    [ROM_API_INDEX_AON_Power_On_XTAL]    = (uint32_t)AON_Power_On_XTAL,
+    [ROM_API_INDEX_AON_Set_Xtal_CapCode] = (uint32_t)AON_Set_Xtal_CapCode,
+    [ROM_API_INDEX_AON_Power_Off_XTAL]   = (uint32_t)AON_Power_Off_XTAL,
+
+    [ROM_API_INDEX_ASM_Delay_Us]      = (uint32_t)ASM_Delay_Us,
+    [ROM_API_INDEX_BL702_Delay_US]    = (uint32_t)BL702_Delay_US,
+    [ROM_API_INDEX_BL702_Delay_MS]    = (uint32_t)BL702_Delay_MS,
+    [ROM_API_INDEX_BL702_MemCpy]      = (uint32_t)BL702_MemCpy,
+    [ROM_API_INDEX_BL702_MemCpy4]     = (uint32_t)BL702_MemCpy4,
+    [ROM_API_INDEX_BL702_MemCpy_Fast] = (uint32_t)BL702_MemCpy_Fast,
+    [ROM_API_INDEX_ARCH_MemCpy_Fast]  = (uint32_t)ARCH_MemCpy_Fast,
+    [ROM_API_INDEX_BL702_MemSet]      = (uint32_t)BL702_MemSet,
+    [ROM_API_INDEX_BL702_MemSet4]     = (uint32_t)BL702_MemSet4,
+    [ROM_API_INDEX_BL702_MemCmp]      = (uint32_t)BL702_MemCmp,
+    [ROM_API_INDEX_BFLB_Soft_CRC32]   = (uint32_t)BFLB_Soft_CRC32,
+
+    [ROM_API_INDEX_GLB_Get_Root_CLK_Sel]                = (uint32_t)GLB_Get_Root_CLK_Sel,
+    [ROM_API_INDEX_GLB_Set_System_CLK_Div]              = (uint32_t)GLB_Set_System_CLK_Div,
+    [ROM_API_INDEX_GLB_Get_BCLK_Div]                    = (uint32_t)GLB_Get_BCLK_Div,
+    [ROM_API_INDEX_GLB_Get_HCLK_Div]                    = (uint32_t)GLB_Get_HCLK_Div,
+    [ROM_API_INDEX_Update_SystemCoreClockWith_XTAL]     = (uint32_t)Update_SystemCoreClockWith_XTAL,
+    [ROM_API_INDEX_GLB_Set_System_CLK]                  = (uint32_t)GLB_Set_System_CLK,
+    [ROM_API_INDEX_System_Core_Clock_Update_From_RC32M] = (uint32_t)System_Core_Clock_Update_From_RC32M,
+    [ROM_API_INDEX_GLB_Set_SF_CLK]                      = (uint32_t)GLB_Set_SF_CLK,
+    [ROM_API_INDEX_GLB_Power_Off_DLL]                   = (uint32_t)GLB_Power_Off_DLL,
+    [ROM_API_INDEX_GLB_Power_On_DLL]                    = (uint32_t)GLB_Power_On_DLL,
+    [ROM_API_INDEX_GLB_Enable_DLL_All_Clks]             = (uint32_t)GLB_Enable_DLL_All_Clks,
+    [ROM_API_INDEX_GLB_Enable_DLL_Clk]                  = (uint32_t)GLB_Enable_DLL_Clk,
+    [ROM_API_INDEX_GLB_Disable_DLL_All_Clks]            = (uint32_t)GLB_Disable_DLL_All_Clks,
+    [ROM_API_INDEX_GLB_Disable_DLL_Clk]                 = (uint32_t)GLB_Disable_DLL_Clk,
+    [ROM_API_INDEX_GLB_SW_System_Reset]                 = (uint32_t)GLB_SW_System_Reset,
+    [ROM_API_INDEX_GLB_SW_CPU_Reset]                    = (uint32_t)GLB_SW_CPU_Reset,
+    [ROM_API_INDEX_GLB_SW_POR_Reset]                    = (uint32_t)GLB_SW_POR_Reset,
+    [ROM_API_INDEX_GLB_Select_Internal_Flash]           = (uint32_t)GLB_Select_Internal_Flash,
+    [ROM_API_INDEX_GLB_Swap_Flash_Pin]                  = (uint32_t)GLB_Swap_Flash_Pin,
+    [ROM_API_INDEX_GLB_Swap_Flash_CS_IO2_Pin]           = (uint32_t)GLB_Swap_Flash_CS_IO2_Pin,
+    [ROM_API_INDEX_GLB_Swap_Flash_IO0_IO3_Pin]          = (uint32_t)GLB_Swap_Flash_IO0_IO3_Pin,
+    [ROM_API_INDEX_GLB_Select_Internal_PSram]           = (uint32_t)GLB_Select_Internal_PSram,
+    [ROM_API_INDEX_GLB_GPIO_Init]                       = (uint32_t)GLB_GPIO_Init,
+    [ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable]              = (uint32_t)GLB_GPIO_OUTPUT_Enable,
+    [ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable]             = (uint32_t)GLB_GPIO_OUTPUT_Disable,
+    [ROM_API_INDEX_GLB_GPIO_Set_HZ]                     = (uint32_t)GLB_GPIO_Set_HZ,
+    [ROM_API_INDEX_GLB_Deswap_Flash_Pin]                = (uint32_t)GLB_Deswap_Flash_Pin,
+    [ROM_API_INDEX_GLB_Select_External_Flash]           = (uint32_t)GLB_Select_External_Flash,
+    [ROM_API_INDEX_GLB_GPIO_Get_Fun]                    = (uint32_t)GLB_GPIO_Get_Fun,
+
+    [ROM_API_INDEX_EF_Ctrl_Busy]            = (uint32_t)EF_Ctrl_Busy,
+    [ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0]    = (uint32_t)EF_Ctrl_Sw_AHB_Clk_0,
+    [ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0]   = (uint32_t)EF_Ctrl_Load_Efuse_R0,
+    [ROM_API_INDEX_EF_Ctrl_Clear]           = (uint32_t)EF_Ctrl_Clear,
+    [ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity] = (uint32_t)EF_Ctrl_Get_Trim_Parity,
+    [ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim] = (uint32_t)EF_Ctrl_Read_RC32K_Trim,
+    [ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim] = (uint32_t)EF_Ctrl_Read_RC32M_Trim,
+
+    [ROM_API_INDEX_PDS_Trim_RC32M]              = (uint32_t)PDS_Trim_RC32M,
+    [ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref] = (uint32_t)PDS_Select_RC32M_As_PLL_Ref,
+    [ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref]  = (uint32_t)PDS_Select_XTAL_As_PLL_Ref,
+    [ROM_API_INDEX_PDS_Power_On_PLL]            = (uint32_t)PDS_Power_On_PLL,
+    [ROM_API_INDEX_PDS_Enable_PLL_All_Clks]     = (uint32_t)PDS_Enable_PLL_All_Clks,
+    [ROM_API_INDEX_PDS_Disable_PLL_All_Clks]    = (uint32_t)PDS_Disable_PLL_All_Clks,
+    [ROM_API_INDEX_PDS_Enable_PLL_Clk]          = (uint32_t)PDS_Enable_PLL_Clk,
+    [ROM_API_INDEX_PDS_Disable_PLL_Clk]         = (uint32_t)PDS_Disable_PLL_Clk,
+    [ROM_API_INDEX_PDS_Power_Off_PLL]           = (uint32_t)PDS_Power_Off_PLL,
+    [ROM_API_INDEX_PDS_Reset]                   = (uint32_t)PDS_Reset,
+    [ROM_API_INDEX_PDS_Enable]                  = (uint32_t)PDS_Enable,
+    [ROM_API_INDEX_PDS_Auto_Time_Config]        = (uint32_t)PDS_Auto_Time_Config,
+    [ROM_API_INDEX_PDS_Auto_Enable]             = (uint32_t)PDS_Auto_Enable,
+    [ROM_API_INDEX_PDS_Manual_Force_Turn_Off]   = (uint32_t)PDS_Manual_Force_Turn_Off,
+    [ROM_API_INDEX_PDS_Manual_Force_Turn_On]    = (uint32_t)PDS_Manual_Force_Turn_On,
+
+    [ROM_API_INDEX_HBN_Enable]            = (uint32_t)HBN_Enable,
+    [ROM_API_INDEX_HBN_Reset]             = (uint32_t)HBN_Reset,
+    [ROM_API_INDEX_HBN_GPIO_Dbg_Pull_Cfg] = (uint32_t)HBN_GPIO_Dbg_Pull_Cfg,
+    [ROM_API_INDEX_HBN_Trim_RC32K]        = (uint32_t)HBN_Trim_RC32K,
+    [ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel]  = (uint32_t)HBN_Set_ROOT_CLK_Sel,
+
+    [ROM_API_INDEX_XIP_SFlash_State_Save]               = (uint32_t)XIP_SFlash_State_Save,
+    [ROM_API_INDEX_XIP_SFlash_State_Restore]            = (uint32_t)XIP_SFlash_State_Restore,
+    [ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock]          = (uint32_t)XIP_SFlash_Erase_Need_Lock,
+    [ROM_API_INDEX_XIP_SFlash_Write_Need_Lock]          = (uint32_t)XIP_SFlash_Write_Need_Lock,
+    [ROM_API_INDEX_XIP_SFlash_Read_Need_Lock]           = (uint32_t)XIP_SFlash_Read_Need_Lock,
+    [ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock]     = (uint32_t)XIP_SFlash_GetJedecId_Need_Lock,
+    [ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock]    = (uint32_t)XIP_SFlash_GetDeviceId_Need_Lock,
+    [ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock]    = (uint32_t)XIP_SFlash_GetUniqueId_Need_Lock,
+    [ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock] = (uint32_t)XIP_SFlash_Read_Via_Cache_Need_Lock,
+    // [ROM_API_INDEX_XIP_SFlash_Read_With_Lock] = (uint32_t)XIP_SFlash_Read_With_Lock,
+    // [ROM_API_INDEX_XIP_SFlash_Write_With_Lock] = (uint32_t)XIP_SFlash_Write_With_Lock,
+    // [ROM_API_INDEX_XIP_SFlash_Erase_With_Lock] = (uint32_t)XIP_SFlash_Erase_With_Lock,
+
+    [ROM_API_INDEX_SFlash_Init]                      = (uint32_t)SFlash_Init,
+    [ROM_API_INDEX_SFlash_SetSPIMode]                = (uint32_t)SFlash_SetSPIMode,
+    [ROM_API_INDEX_SFlash_Read_Reg]                  = (uint32_t)SFlash_Read_Reg,
+    [ROM_API_INDEX_SFlash_Write_Reg]                 = (uint32_t)SFlash_Write_Reg,
+    [ROM_API_INDEX_SFlash_Read_Reg_With_Cmd]         = (uint32_t)SFlash_Read_Reg_With_Cmd,
+    [ROM_API_INDEX_SFlash_Write_Reg_With_Cmd]        = (uint32_t)SFlash_Write_Reg_With_Cmd,
+    [ROM_API_INDEX_SFlash_Busy]                      = (uint32_t)SFlash_Busy,
+    [ROM_API_INDEX_SFlash_Write_Enable]              = (uint32_t)SFlash_Write_Enable,
+    [ROM_API_INDEX_SFlash_Qspi_Enable]               = (uint32_t)SFlash_Qspi_Enable,
+    [ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable] = (uint32_t)SFlash_Volatile_Reg_Write_Enable,
+    [ROM_API_INDEX_SFlash_Chip_Erase]                = (uint32_t)SFlash_Chip_Erase,
+    [ROM_API_INDEX_SFlash_Sector_Erase]              = (uint32_t)SFlash_Sector_Erase,
+    [ROM_API_INDEX_SFlash_Blk32_Erase]               = (uint32_t)SFlash_Blk32_Erase,
+    [ROM_API_INDEX_SFlash_Blk64_Erase]               = (uint32_t)SFlash_Blk64_Erase,
+    [ROM_API_INDEX_SFlash_Erase]                     = (uint32_t)SFlash_Erase,
+    [ROM_API_INDEX_SFlash_Program]                   = (uint32_t)SFlash_Program,
+    [ROM_API_INDEX_SFlash_GetUniqueId]               = (uint32_t)SFlash_GetUniqueId,
+    [ROM_API_INDEX_SFlash_GetJedecId]                = (uint32_t)SFlash_GetJedecId,
+    [ROM_API_INDEX_SFlash_GetDeviceId]               = (uint32_t)SFlash_GetDeviceId,
+    [ROM_API_INDEX_SFlash_Powerdown]                 = (uint32_t)SFlash_Powerdown,
+    [ROM_API_INDEX_SFlash_Releae_Powerdown]          = (uint32_t)SFlash_Releae_Powerdown,
+    [ROM_API_INDEX_SFlash_Restore_From_Powerdown]    = (uint32_t)SFlash_Restore_From_Powerdown,
+    [ROM_API_INDEX_SFlash_SetBurstWrap]              = (uint32_t)SFlash_SetBurstWrap,
+    [ROM_API_INDEX_SFlash_DisableBurstWrap]          = (uint32_t)SFlash_DisableBurstWrap,
+    [ROM_API_INDEX_SFlash_Software_Reset]            = (uint32_t)SFlash_Software_Reset,
+    [ROM_API_INDEX_SFlash_Reset_Continue_Read]       = (uint32_t)SFlash_Reset_Continue_Read,
+    [ROM_API_INDEX_SFlash_Set_IDbus_Cfg]             = (uint32_t)SFlash_Set_IDbus_Cfg,
+    [ROM_API_INDEX_SFlash_IDbus_Read_Enable]         = (uint32_t)SFlash_IDbus_Read_Enable,
+    [ROM_API_INDEX_SFlash_Cache_Read_Enable]         = (uint32_t)SFlash_Cache_Read_Enable,
+    [ROM_API_INDEX_SFlash_Cache_Read_Disable]        = (uint32_t)SFlash_Cache_Read_Disable,
+    [ROM_API_INDEX_SFlash_Read]                      = (uint32_t)SFlash_Read,
+
+    [ROM_API_INDEX_L1C_Cache_Enable_Set]     = (uint32_t)L1C_Cache_Enable_Set,
+    [ROM_API_INDEX_L1C_Cache_Write_Set]      = (uint32_t)L1C_Cache_Write_Set,
+    [ROM_API_INDEX_L1C_Cache_Flush]          = (uint32_t)L1C_Cache_Flush,
+    [ROM_API_INDEX_L1C_Cache_Hit_Count_Get]  = (uint32_t)L1C_Cache_Hit_Count_Get,
+    [ROM_API_INDEX_L1C_Cache_Miss_Count_Get] = (uint32_t)L1C_Cache_Miss_Count_Get,
+    [ROM_API_INDEX_L1C_Cache_Read_Disable]   = (uint32_t)L1C_Cache_Read_Disable,
+    [ROM_API_INDEX_L1C_Set_Wrap]             = (uint32_t)L1C_Set_Wrap,
+    [ROM_API_INDEX_L1C_Set_Way_Disable]      = (uint32_t)L1C_Set_Way_Disable,
+    [ROM_API_INDEX_L1C_IROM_2T_Access_Set]   = (uint32_t)L1C_IROM_2T_Access_Set,
+
+    [ROM_API_INDEX_SF_Ctrl_Enable]                 = (uint32_t)SF_Ctrl_Enable,
+    [ROM_API_INDEX_SF_Ctrl_Psram_Init]             = (uint32_t)SF_Ctrl_Psram_Init,
+    [ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay]        = (uint32_t)SF_Ctrl_Get_Clock_Delay,
+    [ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay]        = (uint32_t)SF_Ctrl_Set_Clock_Delay,
+    [ROM_API_INDEX_SF_Ctrl_Cmds_Set]               = (uint32_t)SF_Ctrl_Cmds_Set,
+    [ROM_API_INDEX_SF_Ctrl_Set_Owner]              = (uint32_t)SF_Ctrl_Set_Owner,
+    [ROM_API_INDEX_SF_Ctrl_Disable]                = (uint32_t)SF_Ctrl_Disable,
+    [ROM_API_INDEX_SF_Ctrl_Select_Pad]             = (uint32_t)SF_Ctrl_Select_Pad,
+    [ROM_API_INDEX_SF_Ctrl_Select_Bank]            = (uint32_t)SF_Ctrl_Select_Bank,
+    [ROM_API_INDEX_SF_Ctrl_AES_Enable_BE]          = (uint32_t)SF_Ctrl_AES_Enable_BE,
+    [ROM_API_INDEX_SF_Ctrl_AES_Enable_LE]          = (uint32_t)SF_Ctrl_AES_Enable_LE,
+    [ROM_API_INDEX_SF_Ctrl_AES_Set_Region]         = (uint32_t)SF_Ctrl_AES_Set_Region,
+    [ROM_API_INDEX_SF_Ctrl_AES_Set_Key]            = (uint32_t)SF_Ctrl_AES_Set_Key,
+    [ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE]         = (uint32_t)SF_Ctrl_AES_Set_Key_BE,
+    [ROM_API_INDEX_SF_Ctrl_AES_Set_IV]             = (uint32_t)SF_Ctrl_AES_Set_IV,
+    [ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE]          = (uint32_t)SF_Ctrl_AES_Set_IV_BE,
+    [ROM_API_INDEX_SF_Ctrl_AES_Enable]             = (uint32_t)SF_Ctrl_AES_Enable,
+    [ROM_API_INDEX_SF_Ctrl_AES_Disable]            = (uint32_t)SF_Ctrl_AES_Disable,
+    [ROM_API_INDEX_SF_Ctrl_Is_AES_Enable]          = (uint32_t)SF_Ctrl_Is_AES_Enable,
+    [ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset] = (uint32_t)SF_Ctrl_Set_Flash_Image_Offset,
+    [ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset] = (uint32_t)SF_Ctrl_Get_Flash_Image_Offset,
+    [ROM_API_INDEX_SF_Ctrl_Select_Clock]           = (uint32_t)SF_Ctrl_Select_Clock,
+    [ROM_API_INDEX_SF_Ctrl_SendCmd]                = (uint32_t)SF_Ctrl_SendCmd,
+    [ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set]  = (uint32_t)SF_Ctrl_Flash_Read_Icache_Set,
+    [ROM_API_INDEX_SF_Ctrl_Psram_Write_Icache_Set] = (uint32_t)SF_Ctrl_Psram_Write_Icache_Set,
+    [ROM_API_INDEX_SF_Ctrl_Psram_Read_Icache_Set]  = (uint32_t)SF_Ctrl_Psram_Read_Icache_Set,
+    [ROM_API_INDEX_SF_Ctrl_GetBusyState]           = (uint32_t)SF_Ctrl_GetBusyState,
+    [ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio]   = (uint32_t)SF_Cfg_Deinit_Ext_Flash_Gpio,
+    [ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio]     = (uint32_t)SF_Cfg_Init_Ext_Flash_Gpio,
+    [ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock] = (uint32_t)SF_Cfg_Get_Flash_Cfg_Need_Lock,
+    [ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio]         = (uint32_t)SF_Cfg_Init_Flash_Gpio,
+    [ROM_API_INDEX_SF_Cfg_Flash_Identify]          = (uint32_t)SF_Cfg_Flash_Identify,
+
+    [ROM_API_INDEX_Psram_Init]              = (uint32_t)Psram_Init,
+    [ROM_API_INDEX_Psram_ReadReg]           = (uint32_t)Psram_ReadReg,
+    [ROM_API_INDEX_Psram_WriteReg]          = (uint32_t)Psram_WriteReg,
+    [ROM_API_INDEX_Psram_SetDriveStrength]  = (uint32_t)Psram_SetDriveStrength,
+    [ROM_API_INDEX_Psram_SetBurstWrap]      = (uint32_t)Psram_SetBurstWrap,
+    [ROM_API_INDEX_Psram_ReadId]            = (uint32_t)Psram_ReadId,
+    [ROM_API_INDEX_Psram_EnterQuadMode]     = (uint32_t)Psram_EnterQuadMode,
+    [ROM_API_INDEX_Psram_ExitQuadMode]      = (uint32_t)Psram_ExitQuadMode,
+    [ROM_API_INDEX_Psram_ToggleBurstLength] = (uint32_t)Psram_ToggleBurstLength,
+    [ROM_API_INDEX_Psram_SoftwareReset]     = (uint32_t)Psram_SoftwareReset,
+    [ROM_API_INDEX_Psram_Set_IDbus_Cfg]     = (uint32_t)Psram_Set_IDbus_Cfg,
+    [ROM_API_INDEX_Psram_Cache_Write_Set]   = (uint32_t)Psram_Cache_Write_Set,
+    [ROM_API_INDEX_Psram_Write]             = (uint32_t)Psram_Write,
+    [ROM_API_INDEX_Psram_Read]              = (uint32_t)Psram_Read,
+
+    [ROM_API_INDEX_FUNC_INVALID_START... ROM_API_INDEX_FUNC_LAST_ENTRY] = 0xdeedbeef,
+};
+
+/*@} end of group ROMDRIVER_Private_Type*/
+
+/** @defgroup ROMDRIVER_Private_Defines
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Private_Defines */
+
+/** @defgroup ROMDRIVER_Private_Variables
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Private_Variables */
+
+/** @defgroup ROMDRIVER_Global_Variables
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Global_Variables */
+
+/** @defgroup ROMDRIVER_Private_FunctionDeclaration
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Private_FunctionDeclaration */
+
+/** @defgroup ROMDRIVER_Private_Functions
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Private_Functions */
+
+/** @defgroup ROMDRIVER_Public_Functions
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Public_Functions */
+
+/*@} end of group ROMDRIVER_COMMON */
+
+/*@} end of group BL702_Periph_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sec_dbg.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sec_dbg.c
new file mode 100644
index 00000000..0db07bef
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sec_dbg.c
@@ -0,0 +1,151 @@
+/**
+  ******************************************************************************
+  * @file    bl702_sec_dbg.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "string.h"
+#include "bl702_sec_dbg.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SEC_DBG
+ *  @{
+ */
+
+/** @defgroup  SEC_DBG_Private_Macros
+ *  @{
+ */
+
+/*@} end of group SEC_DBG_Private_Macros */
+
+/** @defgroup  SEC_DBG_Private_Types
+ *  @{
+ */
+
+/*@} end of group SEC_DBG_Private_Types */
+
+/** @defgroup  SEC_DBG_Private_Variables
+ *  @{
+ */
+
+/*@} end of group SEC_DBG_Private_Variables */
+
+/** @defgroup  SEC_DBG_Global_Variables
+ *  @{
+ */
+
+/*@} end of group SEC_DBG_Global_Variables */
+
+/** @defgroup  SEC_DBG_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group SEC_DBG_Private_Fun_Declaration */
+
+/** @defgroup  SEC_DBG_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Sec Dbg read chip ID
+ *
+ * @param  id[8]: chip ID buffer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Dbg_Read_Chip_ID(uint8_t id[8])
+{
+    uint32_t idLow, idHigh;
+
+    idLow = BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_CHIP_ID_LOW);
+    BL_WRWD_TO_BYTEP(id, idLow);
+
+    idHigh = BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_CHIP_ID_HIGH);
+    BL_WRWD_TO_BYTEP((id + 4), idHigh);
+}
+
+/****************************************************************************/ /**
+ * @brief  Sec Dbg read MAC address
+ *
+ * @param  macAddr[6]: MAC address buffer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Dbg_Read_WiFi_MAC(uint8_t macAddr[6])
+{
+    uint32_t macLow, macHigh;
+
+    macLow = BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_WIFI_MAC_LOW);
+    BL_WRWD_TO_BYTEP(macAddr, macLow);
+
+    macHigh = BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_WIFI_MAC_HIGH);
+    macAddr[4] = (macHigh >> 0) & 0xff;
+    macAddr[5] = (macHigh >> 8) & 0xff;
+}
+
+/****************************************************************************/ /**
+ * @brief  Sec Dbg read debug mode
+ *
+ * @param  None
+ *
+ * @return debug mode status
+ *
+*******************************************************************************/
+uint32_t Sec_Dbg_Read_Dbg_Mode(void)
+{
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_STATUS), SEC_DBG_SD_DBG_MODE);
+}
+
+/****************************************************************************/ /**
+ * @brief  Sec Dbg read debug enable status
+ *
+ * @param  None
+ *
+ * @return enable status
+ *
+*******************************************************************************/
+uint32_t Sec_Dbg_Read_Dbg_Enable(void)
+{
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_STATUS), SEC_DBG_SD_DBG_ENA);
+}
+
+/*@} end of group SEC_DBG_Public_Functions */
+
+/*@} end of group SEC_DBG */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sec_eng.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sec_eng.c
new file mode 100644
index 00000000..8939276d
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sec_eng.c
@@ -0,0 +1,3387 @@
+/**
+  ******************************************************************************
+  * @file    bl702_sec_eng.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "string.h"
+#include "bl702_sec_eng.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SEC_ENG
+ *  @{
+ */
+
+/** @defgroup  SEC_ENG_Private_Macros
+ *  @{
+ */
+#define PUT_UINT32_BE(n, b, i)               \
+    {                                        \
+        (b)[(i)] = (uint8_t)((n) >> 24);     \
+        (b)[(i) + 1] = (uint8_t)((n) >> 16); \
+        (b)[(i) + 2] = (uint8_t)((n) >> 8);  \
+        (b)[(i) + 3] = (uint8_t)((n));       \
+    }
+#define PUT_UINT64_BE(n, b, i)               \
+    {                                        \
+        (b)[(i)] = (uint8_t)((n) >> 56);     \
+        (b)[(i) + 1] = (uint8_t)((n) >> 48); \
+        (b)[(i) + 2] = (uint8_t)((n) >> 40); \
+        (b)[(i) + 3] = (uint8_t)((n) >> 32); \
+        (b)[(i) + 4] = (uint8_t)((n) >> 24); \
+        (b)[(i) + 5] = (uint8_t)((n) >> 16); \
+        (b)[(i) + 6] = (uint8_t)((n) >> 8);  \
+        (b)[(i) + 7] = (uint8_t)((n));       \
+    }
+#define SEC_ENG_SHA_BUSY_TIMEOUT_COUNT  (100 * 160 * 1000)
+#define SEC_ENG_AES_BUSY_TIMEOUT_COUNT  (100 * 160 * 1000)
+#define SEC_ENG_TRNG_BUSY_TIMEOUT_COUNT (100 * 160 * 1000)
+#define SEC_ENG_PKA_INT_TIMEOUT_COUNT   (100 * 160 * 1000)
+#define SEC_ENG_GMAC_BUSY_TIMEOUT_COUNT (100 * 160 * 1000)
+
+/*@} end of group SEC_ENG_Private_Macros */
+
+/** @defgroup  SEC_ENG_Private_Types
+ *  @{
+ */
+struct pka0_pld_cfg {
+    union {
+        struct
+        {
+            uint32_t size        : 12; /*[11: 0],       r/w,        0x0 */
+            uint32_t d_reg_index : 8;  /*[19:12],        r/w,        0x0 */
+            uint32_t d_reg_type  : 4;  /*[23:20],        r/w,        0x0 */
+            uint32_t op          : 7;  /*[30:24],        r/w,        0x0 */
+            uint32_t last_op     : 1;  /*[31:31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } value;
+};
+
+struct pka0_pldi_cfg {
+    union {
+        struct
+        {
+            uint32_t rsvd        : 12; /*[11: 0],       r/w,        0x0 */
+            uint32_t d_reg_index : 8;  /*[19:12],        r/w,        0x0 */
+            uint32_t d_reg_type  : 4;  /*[23:20],        r/w,        0x0 */
+            uint32_t op          : 7;  /*[30:24],        r/w,        0x0 */
+            uint32_t last_op     : 1;  /*[31:31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } value;
+};
+
+struct pka0_common_op_first_cfg {
+    union {
+        struct
+        {
+            uint32_t s0_reg_idx  : 8; /*[7: 0],       r/w,        0x0 */
+            uint32_t s0_reg_type : 4; /*[11:8],       r/w,        0x0 */
+            uint32_t d_reg_idx   : 8; /*[19:12],      r/w,        0x0 */
+            uint32_t d_reg_type  : 4; /*[23:20],      r/w,        0x0 */
+            uint32_t op          : 7; /*[30:24],      r/w,        0x0 */
+            uint32_t last_op     : 1; /*[31:31],      r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } value;
+};
+
+struct pka0_common_op_snd_cfg_S1_only {
+    union {
+        struct
+        {
+            uint32_t reserved_0_11  : 12; /*[11: 0],       rsvd,       0x0 */
+            uint32_t s1_reg_idx     : 8;  /*[19:12],       r/w,        0x0 */
+            uint32_t s1_reg_type    : 4;  /*[23:20],       r/w,        0x0 */
+            uint32_t reserved_24_31 : 8;  /*[31:24],       rsvd,       0x0 */
+        } BF;
+        uint32_t WORD;
+    } value;
+};
+
+struct pka0_common_op_snd_cfg_S2_only {
+    union {
+        struct
+        {
+            uint32_t s2_reg_idx     : 8;  /*[7 : 0],       r/w,        0x0 */
+            uint32_t s2_reg_type    : 4;  /*[11: 8],       r/w,        0x0 */
+            uint32_t reserved_12_31 : 20; /*[31:12],       rsvd,       0x0 */
+        } BF;
+        uint32_t WORD;
+    } value;
+};
+
+struct pka0_common_op_snd_cfg_S1_S2 {
+    union {
+        struct
+        {
+            uint32_t s2_reg_idx     : 8; /*[7 : 0],       r/w,        0x0 */
+            uint32_t s2_reg_type    : 4; /*[11: 8],       r/w,        0x0 */
+            uint32_t s1_reg_idx     : 8; /*[19:12],       r/w,        0x0 */
+            uint32_t s1_reg_type    : 4; /*[23:20],       r/w,        0x0 */
+            uint32_t reserved_24_31 : 8; /*[31:24],       rsvd,       0x0 */
+        } BF;
+        uint32_t WORD;
+    } value;
+};
+
+struct pka0_bit_shift_op_cfg {
+    union {
+        struct
+        {
+            uint32_t bit_shift      : 15; /*[14: 0],       r/w,        0x0 */
+            uint32_t reserved_24_31 : 17; /*[31:15],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } value;
+};
+
+/*@} end of group SEC_ENG_Private_Types */
+
+/** @defgroup  SEC_ENG_Private_Variables
+ *  @{
+ */
+static intCallback_Type *secEngIntCbfArra[SEC_ENG_INT_ALL] = { NULL };
+
+/*@} end of group SEC_ENG_Private_Variables */
+
+/** @defgroup  SEC_ENG_Global_Variables
+ *  @{
+ */
+
+/*@} end of group SEC_ENG_Global_Variables */
+
+/** @defgroup  SEC_ENG_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group SEC_ENG_Private_Fun_Declaration */
+
+/** @defgroup  SEC_ENG_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  SHA256 initialization function
+ *
+ * @param  shaCtx: SHA256 context pointer
+ * @param  shaNo: SHA ID type
+ * @param  shaType: SHA type
+ * @param  shaTmpBuf[16]: SHA temp buffer for store data that is less than 64 bytes
+ * @param  padding[16]: SHA padding buffer for store padding data
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_SHA256_Init(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type shaType, uint32_t shaTmpBuf[16], uint32_t padding[16])
+{
+    uint32_t SHAx = SEC_ENG_BASE + SEC_ENG_SHA_OFFSET;
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));
+    CHECK_PARAM(IS_SEC_ENG_SHA_TYPE(shaType));
+
+    /* Deal SHA control register to set SHA mode */
+    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_MODE, shaType);
+    BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal);
+
+    /* Clear context */
+    memset(shaCtx, 0, sizeof(SEC_Eng_SHA256_Ctx));
+
+    /* Init temp buffer and padding buffer */
+    shaCtx->shaBuf = shaTmpBuf;
+    shaCtx->shaPadding = padding;
+    BL702_MemSet(shaCtx->shaPadding, 0, 64);
+    BL702_MemSet(shaCtx->shaPadding, 0x80, 1);
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(SEC_SHA_IRQn, SEC_SHA_IRQHandler);
+#endif
+}
+
+/****************************************************************************/ /**
+ * @brief  SHA start function
+ *
+ * @param  shaNo: SHA ID type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_SHA_Start(SEC_ENG_SHA_ID_Type shaNo)
+{
+    uint32_t SHAx = SEC_ENG_BASE + SEC_ENG_SHA_OFFSET;
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));
+
+    /* Set SHA enable */
+    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_EN);
+    /* Hash sel 0 for new start */
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_HASH_SEL);
+
+    BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  SHA256 update input data function
+ *
+ * @param  shaCtx: SHA256 context pointer
+ * @param  shaNo: SHA ID type
+ * @param  input: SHA input data pointer, and the address should be word align
+ * @param  len: SHA input data length
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type Sec_Eng_SHA256_Update(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint32_t len)
+{
+    uint32_t SHAx = SEC_ENG_BASE + SEC_ENG_SHA_OFFSET;
+    uint32_t tmpVal;
+    uint32_t fill;
+    uint32_t left;
+    uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;
+
+    if (len == 0) {
+        return SUCCESS;
+    }
+
+    do {
+        tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL);
+        timeoutCnt--;
+
+        if (timeoutCnt == 0) {
+            return TIMEOUT;
+        }
+    } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY));
+
+    /* SHA need set se_sha_sel to 1 to keep the last SHA state */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_HASH_SEL, shaCtx->shaFeed);
+
+    left = shaCtx->total[0] & 0x3F;
+    fill = 64 - left;
+
+    shaCtx->total[0] += (uint32_t)len;
+    shaCtx->total[0] &= 0xFFFFFFFF;
+
+    if (shaCtx->total[0] < (uint32_t)len) {
+        shaCtx->total[1]++;
+    }
+
+    if (left && len >= fill) {
+        BL702_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, fill);
+        /* Set data source address */
+        BL_WR_REG(SHAx, SEC_ENG_SE_SHA_MSA, (uint32_t)shaCtx->shaBuf);
+
+        /* Set data length */
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_MSG_LEN, 1);
+        BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal);
+        /* Trigger */
+        tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_TRIG_1T);
+        BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal);
+
+        shaCtx->shaFeed = 1;
+        input += fill;
+        len -= fill;
+        left = 0;
+    }
+
+    fill = len / 64;
+    len = len % 64;
+
+    if (fill > 0) {
+        /* Wait finished */
+        timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;
+
+        do {
+            tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL);
+            timeoutCnt--;
+
+            if (timeoutCnt == 0) {
+                return TIMEOUT;
+            }
+        } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY));
+
+        /* SHA need set se_sha_sel to 1 to keep the last sha state */
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_HASH_SEL, shaCtx->shaFeed);
+
+        /* Fill data */
+        BL_WR_REG(SHAx, SEC_ENG_SE_SHA_MSA, (uint32_t)input);
+
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_MSG_LEN, fill);
+        BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal);
+
+        tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_TRIG_1T);
+        BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal);
+
+        input += (fill * 64);
+        shaCtx->shaFeed = 1;
+    }
+
+    if (len > 0) {
+        /* Wait finished */
+        timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;
+
+        do {
+            tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL);
+            timeoutCnt--;
+
+            if (timeoutCnt == 0) {
+                return TIMEOUT;
+            }
+        } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY));
+
+        /* Copy left data into temp buffer */
+        BL702_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, len);
+    }
+
+    /* Wait finished */
+    timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;
+
+    do {
+        tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL);
+        timeoutCnt--;
+
+        if (timeoutCnt == 0) {
+            return TIMEOUT;
+        }
+    } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY));
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SHA256 finish to get output function
+ *
+ * @param  shaCtx: SHA256 context pointer
+ * @param  shaNo: SHA ID type
+ * @param  hash: SHA output data of SHA result
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type Sec_Eng_SHA256_Finish(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash)
+{
+    uint32_t last, padn;
+    uint32_t high, low;
+    uint8_t shaMode;
+    uint8_t msgLen[8];
+    uint8_t *p = (uint8_t *)hash;
+    uint32_t SHAx = SEC_ENG_BASE + SEC_ENG_SHA_OFFSET;
+    uint32_t tmpVal;
+    uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));
+
+    /* Wait finished */
+    do {
+        tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL);
+        timeoutCnt--;
+
+        if (timeoutCnt == 0) {
+            return TIMEOUT;
+        }
+    } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY));
+
+    high = (shaCtx->total[0] >> 29) | (shaCtx->total[1] << 3);
+    low = (shaCtx->total[0] << 3);
+
+    PUT_UINT32_BE(high, msgLen, 0);
+    PUT_UINT32_BE(low, msgLen, 4);
+
+    last = shaCtx->total[0] & 0x3F;
+    padn = (last < 56) ? (56 - last) : (120 - last);
+
+    Sec_Eng_SHA256_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, padn);
+
+    /* Wait for  shaPadding idle */
+    timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;
+
+    do {
+        tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL);
+        timeoutCnt--;
+
+        if (timeoutCnt == 0) {
+            return TIMEOUT;
+        }
+    } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY));
+
+    BL702_MemCpy_Fast(shaCtx->shaPadding, msgLen, 8);
+    Sec_Eng_SHA256_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, 8);
+
+    /* Wait finished */
+    timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;
+
+    do {
+        tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL);
+        timeoutCnt--;
+
+        if (timeoutCnt == 0) {
+            return TIMEOUT;
+        }
+    } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY));
+
+    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL);
+    shaMode = (SEC_ENG_SHA_Type)BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_MODE);
+    /* Copy SHA value */
+    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_0);
+    *p++ = (tmpVal & 0xff);
+    *p++ = ((tmpVal >> 8) & 0xff);
+    *p++ = ((tmpVal >> 16) & 0xff);
+    *p++ = ((tmpVal >> 24) & 0xff);
+    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_1);
+    *p++ = (tmpVal & 0xff);
+    *p++ = ((tmpVal >> 8) & 0xff);
+    *p++ = ((tmpVal >> 16) & 0xff);
+    *p++ = ((tmpVal >> 24) & 0xff);
+    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_2);
+    *p++ = (tmpVal & 0xff);
+    *p++ = ((tmpVal >> 8) & 0xff);
+    *p++ = ((tmpVal >> 16) & 0xff);
+    *p++ = ((tmpVal >> 24) & 0xff);
+    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_3);
+    *p++ = (tmpVal & 0xff);
+    *p++ = ((tmpVal >> 8) & 0xff);
+    *p++ = ((tmpVal >> 16) & 0xff);
+    *p++ = ((tmpVal >> 24) & 0xff);
+    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_4);
+    *p++ = (tmpVal & 0xff);
+    *p++ = ((tmpVal >> 8) & 0xff);
+    *p++ = ((tmpVal >> 16) & 0xff);
+    *p++ = ((tmpVal >> 24) & 0xff);
+
+    if (shaMode == SEC_ENG_SHA224 || shaMode == SEC_ENG_SHA256) {
+        tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_5);
+        *p++ = (tmpVal & 0xff);
+        *p++ = ((tmpVal >> 8) & 0xff);
+        *p++ = ((tmpVal >> 16) & 0xff);
+        *p++ = ((tmpVal >> 24) & 0xff);
+        tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_6);
+        *p++ = (tmpVal & 0xff);
+        *p++ = ((tmpVal >> 8) & 0xff);
+        *p++ = ((tmpVal >> 16) & 0xff);
+        *p++ = ((tmpVal >> 24) & 0xff);
+
+        if (shaMode == SEC_ENG_SHA256) {
+            tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_7);
+            *p++ = (tmpVal & 0xff);
+            *p++ = ((tmpVal >> 8) & 0xff);
+            *p++ = ((tmpVal >> 16) & 0xff);
+            *p++ = ((tmpVal >> 24) & 0xff);
+        }
+    }
+
+    /* Disable SHA engine*/
+    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_HASH_SEL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_EN);
+    BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SHA enable link mode and set link config address
+ *
+ * @param  shaNo: SHA ID type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_SHA_Enable_Link(SEC_ENG_SHA_ID_Type shaNo)
+{
+    uint32_t SHAx = SEC_ENG_BASE;
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));
+
+    /* Enable sha and enable link mode */
+    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_LINK_MODE);
+    BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  SHA disable link mode
+ *
+ * @param  shaNo: SHA ID type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_SHA_Disable_Link(SEC_ENG_SHA_ID_Type shaNo)
+{
+    uint32_t SHAx = SEC_ENG_BASE;
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));
+
+    /* Disable sha and disable link mode */
+    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_LINK_MODE);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN);
+    BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  SHA256 link mode initialization function
+ *
+ * @param  shaCtx: SHA256 link mode context pointer
+ * @param  shaNo: SHA ID type
+ * @param  linkAddr: SHA link configure address
+ * @param  shaTmpBuf[16]: SHA temp buffer for store data that is less than 64 bytes
+ * @param  padding[16]: SHA padding buffer for store padding data
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_SHA256_Link_Init(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, uint32_t shaTmpBuf[16], uint32_t padding[16])
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));
+
+    /* Clear context */
+    memset(shaCtx, 0, sizeof(SEC_Eng_SHA256_Link_Ctx));
+
+    /* Init temp buffer,padding buffer and link address */
+    shaCtx->shaBuf = shaTmpBuf;
+    shaCtx->shaPadding = padding;
+    BL702_MemSet(shaCtx->shaPadding, 0, 64);
+    BL702_MemSet(shaCtx->shaPadding, 0x80, 1);
+    shaCtx->linkAddr = linkAddr;
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(SEC_SHA_IRQn, SEC_SHA_IRQHandler);
+#endif
+}
+
+/****************************************************************************/ /**
+ * @brief  SHA256 link mode update input data function
+ *
+ * @param  shaCtx: SHA256 link mode context pointer
+ * @param  shaNo: SHA ID type
+ * @param  input: SHA input data pointer, and the address should be word align
+ * @param  len: SHA input data length
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type Sec_Eng_SHA256_Link_Update(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint32_t len)
+{
+    uint32_t SHAx = SEC_ENG_BASE;
+    uint32_t tmpVal;
+    uint32_t fill;
+    uint32_t left;
+    uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;
+
+    if (len == 0) {
+        return SUCCESS;
+    }
+
+    do {
+        tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);
+        timeoutCnt--;
+
+        if (timeoutCnt == 0) {
+            return TIMEOUT;
+        }
+    } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));
+
+    /* Set link address */
+    BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, shaCtx->linkAddr);
+
+    left = shaCtx->total[0] & 0x3F;
+    fill = 64 - left;
+
+    shaCtx->total[0] += (uint32_t)len;
+    shaCtx->total[0] &= 0xFFFFFFFF;
+
+    if (shaCtx->total[0] < (uint32_t)len) {
+        shaCtx->total[1]++;
+    }
+
+    if (left && len >= fill) {
+        BL702_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, fill);
+        /* Set data source address */
+        *(uint32_t *)(shaCtx->linkAddr + 4) = (uint32_t)shaCtx->shaBuf;
+
+        /* Set data length */
+        *((uint16_t *)shaCtx->linkAddr + 1) = 1;
+        /* Trigger */
+        tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);
+        BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T));
+
+        /* Choose accumulating last hash in the next time */
+        *((uint32_t *)shaCtx->linkAddr) |= 0x40;
+        input += fill;
+        len -= fill;
+        left = 0;
+    }
+
+    fill = len / 64;
+    len = len % 64;
+
+    if (fill > 0) {
+        /* Wait finished */
+        timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;
+
+        do {
+            tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);
+            timeoutCnt--;
+
+            if (timeoutCnt == 0) {
+                return TIMEOUT;
+            }
+        } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));
+
+        /* Fill data */
+        *(uint32_t *)(shaCtx->linkAddr + 4) = (uint32_t)input;
+        *((uint16_t *)shaCtx->linkAddr + 1) = fill;
+
+        /* Trigger */
+        tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);
+        BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T));
+
+        input += (fill * 64);
+        /* Choose accumulating last hash in the next time */
+        *((uint32_t *)shaCtx->linkAddr) |= 0x40;
+    }
+
+    if (len > 0) {
+        /* Wait finished */
+        timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;
+
+        do {
+            tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);
+            timeoutCnt--;
+
+            if (timeoutCnt == 0) {
+                return TIMEOUT;
+            }
+        } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));
+
+        /* Copy left data into temp buffer */
+        BL702_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, len);
+    }
+
+    /* Wait finished */
+    timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;
+
+    do {
+        tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);
+        timeoutCnt--;
+
+        if (timeoutCnt == 0) {
+            return TIMEOUT;
+        }
+    } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SHA256 link mode finish to get output function
+ *
+ * @param  shaCtx: SHA256 link mode context pointer
+ * @param  shaNo: SHA ID type
+ * @param  hash: SHA output data of SHA result
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type Sec_Eng_SHA256_Link_Finish(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash)
+{
+    uint32_t last, padn;
+    uint32_t high, low;
+    uint8_t msgLen[8];
+    uint32_t SHAx = SEC_ENG_BASE;
+    uint32_t tmpVal;
+    uint32_t shaMode = (*(uint32_t *)shaCtx->linkAddr) >> 2 & 0x7;
+    uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));
+
+    /* Wait finished */
+    do {
+        tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);
+        timeoutCnt--;
+
+        if (timeoutCnt == 0) {
+            return TIMEOUT;
+        }
+    } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));
+
+    /* Set link address */
+    BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, shaCtx->linkAddr);
+
+    high = (shaCtx->total[0] >> 29) | (shaCtx->total[1] << 3);
+    low = (shaCtx->total[0] << 3);
+
+    PUT_UINT32_BE(high, msgLen, 0);
+    PUT_UINT32_BE(low, msgLen, 4);
+
+    last = shaCtx->total[0] & 0x3F;
+    padn = (last < 56) ? (56 - last) : (120 - last);
+
+    Sec_Eng_SHA256_Link_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, padn);
+
+    /* Wait for shaPadding idle */
+    timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;
+
+    do {
+        tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);
+        timeoutCnt--;
+
+        if (timeoutCnt == 0) {
+            return TIMEOUT;
+        }
+    } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));
+
+    Sec_Eng_SHA256_Link_Update(shaCtx, shaNo, msgLen, 8);
+
+    /* Wait finished */
+    timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;
+
+    do {
+        tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);
+        timeoutCnt--;
+
+        if (timeoutCnt == 0) {
+            return TIMEOUT;
+        }
+    } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));
+
+    /* Get result according to SHA mode,result is placed in (link address + offset:8) */
+    switch (shaMode) {
+        case 0:
+            BL702_MemCpy_Fast(hash, (uint8_t *)(shaCtx->linkAddr + 8), 32);
+            break;
+
+        case 1:
+            BL702_MemCpy_Fast(hash, (uint8_t *)(shaCtx->linkAddr + 8), 28);
+            break;
+
+        case 2:
+            BL702_MemCpy_Fast(hash, (uint8_t *)(shaCtx->linkAddr + 8), 20);
+            break;
+
+        case 3:
+            BL702_MemCpy_Fast(hash, (uint8_t *)(shaCtx->linkAddr + 8), 20);
+            break;
+
+        default:
+            break;
+    }
+
+    /* Choose new hash in the next time */
+    *((uint32_t *)shaCtx->linkAddr) &= ~0x40;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  AES initialization function
+ *
+ * @param  aesCtx: AES context pointer
+ * @param  aesNo: AES ID type
+ * @param  aesType: AES type:ECB,CTR,CBC
+ * @param  keyType: AES key type:128,256,192
+ * @param  enDecType: AES encryption or decryption
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type Sec_Eng_AES_Init(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Type aesType, SEC_ENG_AES_Key_Type keyType, SEC_ENG_AES_EnDec_Type enDecType)
+{
+    uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET;
+    uint32_t tmpVal;
+    uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));
+    CHECK_PARAM(IS_SEC_ENG_AES_TYPE(aesType));
+    CHECK_PARAM(IS_SEC_ENG_AES_KEY_TYPE(keyType));
+    CHECK_PARAM(IS_SEC_ENG_AES_ENDEC_TYPE(enDecType));
+
+    /* Wait finished */
+    do {
+        tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL);
+        timeoutCnt--;
+
+        if (timeoutCnt == 0) {
+            return TIMEOUT;
+        }
+    } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_BUSY));
+
+    /* Set AES mode type*/
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_BLOCK_MODE, aesType);
+
+    /* Set AES key type */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_MODE, keyType);
+
+    /* Set AES encryption or decryption */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_DEC_EN, enDecType);
+
+    /* Clear dec_key_sel to select new key */
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_DEC_KEY_SEL);
+
+    /* Clear aes iv sel to select new iv */
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_IV_SEL);
+
+    /* Clear AES interrupt */
+    tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_INT_CLR_1T);
+
+    /* Enable AES */
+    tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_EN);
+
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal);
+
+    /* Clear AES context */
+    memset(aesCtx, 0, sizeof(SEC_Eng_AES_Ctx));
+
+    /* Enable ID0 Access for HW Key */
+    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL_PROT, 0x03);
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(SEC_AES_IRQn, SEC_AES_IRQHandler);
+#endif
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  AES enable function,set AES bigendian
+ *
+ * @param  aesNo: AES ID type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID_Type aesNo)
+{
+    uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));
+
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_ENDIAN, 0x0f);
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(SEC_AES_IRQn, SEC_AES_IRQHandler);
+#endif
+}
+
+/****************************************************************************/ /**
+ * @brief  AES enable function,set AES littleendian
+ *
+ * @param  aesNo: AES ID type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_AES_Enable_LE(SEC_ENG_AES_ID_Type aesNo)
+{
+    uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));
+
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_ENDIAN, 0x00);
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(SEC_AES_IRQn, SEC_AES_IRQHandler);
+#endif
+}
+
+/****************************************************************************/ /**
+ * @brief  AES enable link mode
+ *
+ * @param  aesNo: AES ID type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_AES_Enable_Link(SEC_ENG_AES_ID_Type aesNo)
+{
+    uint32_t AESx = SEC_ENG_BASE;
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));
+
+    /* Enable aes link mode */
+    tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_LINK_MODE));
+
+    /* Enable ID0 Access for HW Key */
+    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL_PROT, 0x03);
+}
+
+/****************************************************************************/ /**
+ * @brief  AES disable link mode
+ *
+ * @param  aesNo: AES ID type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_AES_Disable_Link(SEC_ENG_AES_ID_Type aesNo)
+{
+    uint32_t AESx = SEC_ENG_BASE;
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));
+
+    /* Disable aes link mode */
+    tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_LINK_MODE));
+}
+
+/****************************************************************************/ /**
+ * @brief  AES work in link mode
+ *
+ * @param  aesNo: AES ID type
+ * @param  linkAddr: Address of config structure in link mode
+ * @param  in: AES input data buffer to deal with
+ * @param  len: AES input data length
+ * @param  out: AES output data buffer
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type Sec_Eng_AES_Link_Work(SEC_ENG_AES_ID_Type aesNo, uint32_t linkAddr, const uint8_t *in, uint32_t len, uint8_t *out)
+{
+    uint32_t AESx = SEC_ENG_BASE;
+    uint32_t tmpVal;
+    uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));
+
+    /* Link address should word align */
+    if ((linkAddr & 0x03) != 0 || len % 16 != 0) {
+        return ERROR;
+    }
+
+    /* Wait finished */
+    do {
+        tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);
+        timeoutCnt--;
+
+        if (timeoutCnt == 0) {
+            return TIMEOUT;
+        }
+    } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY));
+
+    /* Set link address */
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_0_LINK, linkAddr);
+
+    /* Change source buffer address and destination buffer address */
+    *(uint32_t *)(linkAddr + 4) = (uint32_t)in;
+    *(uint32_t *)(linkAddr + 8) = (uint32_t)out;
+
+    /* Set data length */
+    *((uint16_t *)linkAddr + 1) = len / 16;
+
+    /* Enable aes */
+    tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_EN));
+
+    /* Start aes engine and wait finishing */
+    tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_TRIG_1T));
+    __NOP();
+    __NOP();
+    timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT;
+
+    do {
+        tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);
+        timeoutCnt--;
+
+        if (timeoutCnt == 0) {
+            return TIMEOUT;
+        }
+    } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY));
+
+    /* Disable aes */
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_EN));
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  AES set hardware key source:efuse region for CPU0  or region efuse for CPU1
+ *
+ * @param  aesNo: AES ID type
+ * @param  src: AES key source type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_AES_Set_Hw_Key_Src(SEC_ENG_AES_ID_Type aesNo, uint8_t src)
+{
+    uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET;
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));
+
+    tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_SBOOT);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_SBOOT_KEY_SEL, src);
+
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_SBOOT, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  AES set KEY and IV
+ *
+ * @param  aesNo: AES ID type
+ * @param  keySrc: AES KEY type:SEC_ENG_AES_KEY_HW or SEC_ENG_AES_KEY_SW
+ * @param  key: AES KEY pointer
+ * @param  iv: AES IV pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_AES_Set_Key_IV(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key, const uint8_t *iv)
+{
+    uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET;
+    uint32_t tmpVal;
+    uint32_t keyType;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));
+    CHECK_PARAM(IS_SEC_ENG_AES_KEY_SRC_TYPE(keySrc));
+
+    /* Set IV */
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_3, __REV(BL_RDWD_FRM_BYTEP(iv)));
+    iv += 4;
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_2, __REV(BL_RDWD_FRM_BYTEP(iv)));
+    iv += 4;
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_1, __REV(BL_RDWD_FRM_BYTEP(iv)));
+    iv += 4;
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_0, __REV(BL_RDWD_FRM_BYTEP(iv)));
+    iv += 4;
+
+    /* Select hardware key */
+    if (keySrc == SEC_ENG_AES_KEY_HW) {
+        tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_HW_KEY_EN, SEC_ENG_AES_KEY_HW);
+        BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal);
+
+        tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_KEY_SEL_0, *key);
+        BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_0, tmpVal);
+
+        tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_1);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_KEY_SEL_1, *key);
+        BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_1, tmpVal);
+
+        return;
+    }
+
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_7, __REV(BL_RDWD_FRM_BYTEP(key)));
+    key += 4;
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_6, __REV(BL_RDWD_FRM_BYTEP(key)));
+    key += 4;
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_5, __REV(BL_RDWD_FRM_BYTEP(key)));
+    key += 4;
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_4, __REV(BL_RDWD_FRM_BYTEP(key)));
+    key += 4;
+
+    tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL);
+    keyType = BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_MODE);
+
+    if (keyType == (uint32_t)SEC_ENG_AES_KEY_192BITS) {
+        BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_3, __REV(BL_RDWD_FRM_BYTEP(key)));
+        key += 4;
+        BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_2, __REV(BL_RDWD_FRM_BYTEP(key)));
+        key += 4;
+    } else if (keyType == (uint32_t)SEC_ENG_AES_KEY_256BITS || keyType == (uint32_t)SEC_ENG_AES_DOUBLE_KEY_128BITS) {
+        BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_3, __REV(BL_RDWD_FRM_BYTEP(key)));
+        key += 4;
+        BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_2, __REV(BL_RDWD_FRM_BYTEP(key)));
+        key += 4;
+        BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_1, __REV(BL_RDWD_FRM_BYTEP(key)));
+        key += 4;
+        BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_0, __REV(BL_RDWD_FRM_BYTEP(key)));
+        key += 4;
+    }
+
+    /* Select software key */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_HW_KEY_EN, SEC_ENG_AES_KEY_SW);
+
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  AES set KEY and IV with bigendian
+ *
+ * @param  aesNo: AES ID type
+ * @param  keySrc: AES KEY type:SEC_ENG_AES_KEY_HW or SEC_ENG_AES_KEY_SW
+ * @param  key: AES KEY pointer
+ * @param  iv: AES IV pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key, const uint8_t *iv)
+{
+    uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET;
+    uint32_t tmpVal;
+    uint32_t keyType;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));
+    CHECK_PARAM(IS_SEC_ENG_AES_KEY_SRC_TYPE(keySrc));
+
+    /* Set IV */
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_0, BL_RDWD_FRM_BYTEP(iv));
+    iv += 4;
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_1, BL_RDWD_FRM_BYTEP(iv));
+    iv += 4;
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_2, BL_RDWD_FRM_BYTEP(iv));
+    iv += 4;
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_3, BL_RDWD_FRM_BYTEP(iv));
+    iv += 4;
+
+    /* Select hardware key */
+    if (keySrc == SEC_ENG_AES_KEY_HW) {
+        tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_HW_KEY_EN, SEC_ENG_AES_KEY_HW);
+        BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal);
+
+        tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_KEY_SEL_0, *key);
+        BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_0, tmpVal);
+
+        tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_1);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_KEY_SEL_1, *key);
+        BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_1, tmpVal);
+
+        return;
+    }
+
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_0, BL_RDWD_FRM_BYTEP(key));
+    key += 4;
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_1, BL_RDWD_FRM_BYTEP(key));
+    key += 4;
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_2, BL_RDWD_FRM_BYTEP(key));
+    key += 4;
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_3, BL_RDWD_FRM_BYTEP(key));
+    key += 4;
+
+    tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL);
+    keyType = BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_MODE);
+
+    if (keyType == (uint32_t)SEC_ENG_AES_KEY_192BITS) {
+        BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_4, BL_RDWD_FRM_BYTEP(key));
+        key += 4;
+        BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_5, BL_RDWD_FRM_BYTEP(key));
+        key += 4;
+    } else if (keyType == (uint32_t)SEC_ENG_AES_KEY_256BITS || keyType == (uint32_t)SEC_ENG_AES_DOUBLE_KEY_128BITS) {
+        BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_4, BL_RDWD_FRM_BYTEP(key));
+        key += 4;
+        BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_5, BL_RDWD_FRM_BYTEP(key));
+        key += 4;
+        BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_6, BL_RDWD_FRM_BYTEP(key));
+        key += 4;
+        BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_7, BL_RDWD_FRM_BYTEP(key));
+        key += 4;
+    }
+
+    /* Select software key */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_HW_KEY_EN, SEC_ENG_AES_KEY_SW);
+
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  AES set counter byte type in CTR mode
+ *
+ * @param  aesNo: AES ID type
+ * @param  counterType: AES counter type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_AES_Set_Counter_Byte(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Counter_Type counterType)
+{
+    uint32_t AESx = SEC_ENG_BASE;
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));
+    CHECK_PARAM(IS_SEC_ENG_AES_COUNTER_TYPE(counterType));
+
+    /* Set counter type */
+    tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_ENDIAN);
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_0_ENDIAN, BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_CTR_LEN, counterType));
+}
+
+/****************************************************************************/ /**
+ * @brief  AES encrypt or decrypt input data
+ *
+ * @param  aesCtx: AES context pointer
+ * @param  aesNo: AES ID type
+ * @param  in: AES input data buffer to deal with
+ * @param  len: AES input data length
+ * @param  out: AES output data buffer
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type Sec_Eng_AES_Crypt(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, const uint8_t *in, uint32_t len, uint8_t *out)
+{
+    uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET;
+    uint32_t tmpVal;
+    uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT;
+
+    if (len % 16 != 0) {
+        return ERROR;
+    }
+
+    /* Wait finished */
+    do {
+        tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL);
+        timeoutCnt--;
+
+        if (timeoutCnt == 0) {
+            return TIMEOUT;
+        }
+    } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_BUSY));
+
+    /* Clear trigger */
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_TRIG_1T);
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal);
+
+    /* Set input and output address */
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_MSA, (uint32_t)in);
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_MDA, (uint32_t)out);
+
+    /* Set message length */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_MSG_LEN, len / 16);
+
+    if (aesCtx->mode == SEC_ENG_AES_CTR) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_DEC_KEY_SEL);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_DEC_KEY_SEL);
+    }
+
+    /* Set IV sel:0 for new, 1 for last */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_IV_SEL, aesCtx->aesFeed);
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal);
+
+    /* Trigger AES Engine */
+    tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_TRIG_1T);
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal);
+
+    /* Wait finished */
+    timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT;
+
+    do {
+        tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL);
+        timeoutCnt--;
+
+        if (timeoutCnt == 0) {
+            return TIMEOUT;
+        }
+    } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_BUSY));
+
+    aesCtx->aesFeed = 1;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  AES finish function, clean register
+ *
+ * @param  aesNo: AES ID type
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type Sec_Eng_AES_Finish(SEC_ENG_AES_ID_Type aesNo)
+{
+    uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET;
+    uint32_t tmpVal;
+    uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT;
+
+    /* Wait finished */
+    do {
+        tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL);
+        timeoutCnt--;
+
+        if (timeoutCnt == 0) {
+            return TIMEOUT;
+        }
+    } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_BUSY));
+
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_EN);
+
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_DEC_KEY_SEL);
+
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_IV_SEL);
+
+    BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  TRNG enable TRNG interrupt
+ *
+ * @param  None
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type Sec_Eng_Trng_Enable(void)
+{
+    uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET;
+    uint32_t tmpVal;
+    uint32_t timeoutCnt = SEC_ENG_TRNG_BUSY_TIMEOUT_COUNT;
+
+    tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0);
+
+    /* FIXME:default reseed number is 0x1ff, to verify, use 0xa to speed up */
+    //tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_TRNG_RESEED_N,0x1ff);
+
+    /* No interrupt as default */
+    tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_EN);
+    BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_INT_CLR_1T);
+    BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);
+    /* busy will be set to 1 after trigger, the gap is 1T */
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+
+    do {
+        tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0);
+        timeoutCnt--;
+
+        if (timeoutCnt == 0) {
+            return TIMEOUT;
+        }
+    } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_TRNG_BUSY));
+
+    /* Clear trng interrupt */
+    tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_INT_CLR_1T);
+    BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(SEC_TRNG_IRQn, SEC_TRNG_IRQHandler);
+#endif
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  TRNG enable TRNG interrupt
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_Trng_Int_Enable(void)
+{
+    uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET;
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0);
+
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_INT_MASK);
+
+    BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TRNG disable TRNG interrupt
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_Trng_Int_Disable(void)
+{
+    uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET;
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_INT_MASK);
+
+    BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TRNG get random data out
+ *
+ * @param  data[32]: TRNG output data
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type Sec_Eng_Trng_Read(uint8_t data[32])
+{
+    uint8_t *p = (uint8_t *)data;
+    uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET;
+    uint32_t tmpVal;
+    uint32_t timeoutCnt = SEC_ENG_TRNG_BUSY_TIMEOUT_COUNT;
+
+    tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0);
+
+    /* Trigger */
+    tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_TRIG_1T);
+    BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);
+
+    /* busy will be set to 1 after trigger, the gap is 1T */
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+
+    do {
+        tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0);
+        timeoutCnt--;
+
+        if (timeoutCnt == 0) {
+            return TIMEOUT;
+        }
+    } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_TRNG_BUSY));
+
+    /* copy trng value */
+    BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_0));
+    p += 4;
+    BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_1));
+    p += 4;
+    BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_2));
+    p += 4;
+    BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_3));
+    p += 4;
+    BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_4));
+    p += 4;
+    BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_5));
+    p += 4;
+    BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_6));
+    p += 4;
+    BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_7));
+    p += 4;
+
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_TRIG_1T);
+    BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);
+
+    /* Clear data */
+    tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_DOUT_CLR_1T);
+    BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);
+
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_DOUT_CLR_1T);
+    BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  TRNG get random data out
+ *
+ * @param  data: TRNG output data buffer
+ *
+ * @param  len: total length to get in bytes
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type Sec_Eng_Trng_Get_Random(uint8_t *data, uint32_t len)
+{
+    uint8_t tmpBuf[32];
+    uint32_t readLen = 0;
+    uint32_t i = 0, cnt = 0;
+
+    while (readLen < len) {
+        if (Sec_Eng_Trng_Read(tmpBuf) != SUCCESS) {
+            return -1;
+        }
+
+        cnt = len - readLen;
+
+        if (cnt > sizeof(tmpBuf)) {
+            cnt = sizeof(tmpBuf);
+        }
+
+        for (i = 0; i < cnt; i++) {
+            data[readLen + i] = tmpBuf[i];
+        }
+
+        readLen += cnt;
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  TRNG Interrupt Read Trigger
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_Trng_Int_Read_Trigger(void)
+{
+    uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET;
+    uint32_t tmpVal;
+
+    Sec_Eng_Trng_Int_Enable();
+
+    tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0);
+    /* Trigger */
+    tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_TRIG_1T);
+    BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TRNG get random data out with Interrupt
+ *
+ * @param  data[32]: TRNG output data
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_Trng_Int_Read(uint8_t data[32])
+{
+    uint8_t *p = (uint8_t *)data;
+    uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET;
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0);
+
+    /* copy trng value */
+    BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_0));
+    p += 4;
+    BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_1));
+    p += 4;
+    BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_2));
+    p += 4;
+    BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_3));
+    p += 4;
+    BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_4));
+    p += 4;
+    BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_5));
+    p += 4;
+    BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_6));
+    p += 4;
+    BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_7));
+    p += 4;
+
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_TRIG_1T);
+    BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);
+
+    /* Clear data */
+    tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_DOUT_CLR_1T);
+    BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);
+
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_DOUT_CLR_1T);
+    BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable TRNG
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_Trng_Disable(void)
+{
+    uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET;
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0);
+
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_EN);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_TRNG_RESEED_N);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_INT_CLR_1T);
+
+    BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA Reset
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_Reset(void)
+{
+    uint8_t val;
+
+    //Disable sec engine
+    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, 0);
+
+    //Enable sec engine
+    val = 1 << 3;
+    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, val);
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA Enable big endian
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_BigEndian_Enable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_ENDIAN);
+    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, tmpVal);
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(SEC_PKA_IRQn, SEC_PKA_IRQHandler);
+#endif
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA Enable little endian
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_LittleEndian_Enable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_ENDIAN);
+    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, tmpVal);
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(SEC_PKA_IRQn, SEC_PKA_IRQHandler);
+#endif
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA get status function
+ *
+ * @param  status: Structure pointer of PKA status type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_GetStatus(SEC_Eng_PKA_Status_Type *status)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);
+    *(uint16_t *)status = (uint16_t)BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_PKA_0_STATUS);
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA clear interrupt
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_Clear_Int(void)
+{
+    uint32_t ctrl;
+
+    ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);
+    ctrl = BL_SET_REG_BIT(ctrl, SEC_ENG_SE_PKA_0_INT_CLR_1T);
+
+    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, ctrl);
+
+    ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);
+    ctrl = BL_CLR_REG_BIT(ctrl, SEC_ENG_SE_PKA_0_INT_CLR_1T);
+    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, ctrl);
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA get Register size according to Register type
+ *
+ * @param  reg_type: PKA Register type
+ *
+ * @return Register size
+ *
+*******************************************************************************/
+static uint16_t Sec_Eng_PKA_Get_Reg_Size(SEC_ENG_PKA_REG_SIZE_Type reg_type)
+{
+    switch (reg_type) {
+        case SEC_ENG_PKA_REG_SIZE_8:
+            return 8;
+
+        case SEC_ENG_PKA_REG_SIZE_16:
+            return 16;
+
+        case SEC_ENG_PKA_REG_SIZE_32:
+            return 32;
+
+        case SEC_ENG_PKA_REG_SIZE_64:
+            return 64;
+
+        case SEC_ENG_PKA_REG_SIZE_96:
+            return 96;
+
+        case SEC_ENG_PKA_REG_SIZE_128:
+            return 128;
+
+        case SEC_ENG_PKA_REG_SIZE_192:
+            return 192;
+
+        case SEC_ENG_PKA_REG_SIZE_256:
+            return 256;
+
+        case SEC_ENG_PKA_REG_SIZE_384:
+            return 384;
+
+        case SEC_ENG_PKA_REG_SIZE_512:
+            return 512;
+
+        default:
+            return 0;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA set pre-load register configuration
+ *
+ * @param  size: Data size in word to write
+ * @param  regIndex: Register index
+ * @param  regType: Register type
+ * @param  op: PKA operation
+ * @param  lastOp: Last operation
+ *
+ * @return None
+ *
+*******************************************************************************/
+static void Sec_Eng_PKA_Write_Pld_Cfg(uint16_t size, uint8_t regIndex, SEC_ENG_PKA_REG_SIZE_Type regType, SEC_ENG_PKA_OP_Type op, uint8_t lastOp)
+{
+    struct pka0_pld_cfg cfg;
+
+    cfg.value.BF.size = size;
+    cfg.value.BF.d_reg_index = regIndex;
+    cfg.value.BF.d_reg_type = regType;
+    cfg.value.BF.op = op;
+    cfg.value.BF.last_op = lastOp;
+
+    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA write common operation first configuration
+ *
+ * @param  s0RegIndex: Register index
+ * @param  s0RegType: Register type
+ * @param  dRegIndex: Result Register index
+ * @param  dRegType: Result Register type
+ * @param  op: PKA operation
+ * @param  lastOp: Last operation
+ *
+ * @return None
+ *
+*******************************************************************************/
+static void Sec_Eng_PKA_Write_Common_OP_First_Cfg(uint8_t s0RegIndex, uint8_t s0RegType, uint8_t dRegIndex, uint8_t dRegType,
+                                                  uint8_t op, uint8_t lastOp)
+{
+    struct pka0_common_op_first_cfg cfg;
+
+    cfg.value.BF.s0_reg_idx = s0RegIndex;
+    cfg.value.BF.s0_reg_type = s0RegType;
+
+    if (op != SEC_ENG_PKA_OP_LCMP) {
+        cfg.value.BF.d_reg_idx = dRegIndex;
+        cfg.value.BF.d_reg_type = dRegType;
+    }
+
+    cfg.value.BF.op = op;
+    cfg.value.BF.last_op = lastOp;
+
+    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA write common operation second configuration1
+ *
+ * @param  s1RegIndex: Register index
+ * @param  s1RegType: Register type
+ *
+ * @return None
+ *
+*******************************************************************************/
+static void Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(uint8_t s1RegIndex, uint8_t s1RegType)
+{
+    struct pka0_common_op_snd_cfg_S1_only cfg;
+
+    cfg.value.BF.s1_reg_idx = s1RegIndex;
+    cfg.value.BF.s1_reg_type = s1RegType;
+
+    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA write common operation second configuration2
+ *
+ * @param  s2RegIndex: Register index
+ * @param  s2RegType: Register type
+ *
+ * @return None
+ *
+*******************************************************************************/
+static void Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(uint8_t s2RegIndex, uint8_t s2RegType)
+{
+    struct pka0_common_op_snd_cfg_S2_only cfg;
+
+    cfg.value.BF.s2_reg_idx = s2RegIndex;
+    cfg.value.BF.s2_reg_type = s2RegType;
+
+    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA write common operation second configuration1 and configuration 2
+ *
+ * @param  s1RegIndex: Configuration 1 Register index
+ * @param  s1RegType: Configuration 1 Register type
+ * @param  s2RegIndex: Configuration 2 Register index
+ * @param  s2RegType: Configuration 3 Register type
+ *
+ * @return None
+ *
+*******************************************************************************/
+static void Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(uint8_t s1RegIndex, uint8_t s1RegType, uint8_t s2RegIndex, uint8_t s2RegType)
+{
+    struct pka0_common_op_snd_cfg_S1_S2 cfg;
+
+    cfg.value.BF.s1_reg_idx = s1RegIndex;
+    cfg.value.BF.s1_reg_type = s1RegType;
+    cfg.value.BF.s2_reg_idx = s2RegIndex;
+    cfg.value.BF.s2_reg_type = s2RegType;
+
+    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA wait for complete interrupt
+ *
+ * @param  None
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+static BL_Err_Type Sec_Eng_PKA_Wait_ISR(void)
+{
+    uint32_t pka0_ctrl;
+    uint32_t timeoutCnt = SEC_ENG_PKA_INT_TIMEOUT_COUNT;
+
+    do {
+        pka0_ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);
+        timeoutCnt--;
+
+        if (timeoutCnt == 0) {
+            return TIMEOUT;
+        }
+    } while (!BL_GET_REG_BITS_VAL(pka0_ctrl, SEC_ENG_SE_PKA_0_INT));
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA read block data from register
+ *
+ * @param  dest: Pointer to buffer address
+ * @param  src: Pointer to register address
+ * @param  len: Data len in word
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifdef ARCH_ARM
+#ifndef __GNUC__
+__ASM void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len)
+{
+    PUSH  {R3-R6,LR}
+Start0
+    CMP  R2,#4
+    BLT  Finish0
+    LDR  R3,[R1]
+    LDR  R4,[R1]
+    LDR  R5,[R1]
+    LDR  R6,[R1]
+    STMIA  R0!,{R3-R6}
+    SUBS R2,R2,#4
+    B  Start0
+Finish0
+    POP  {R3-R6,PC}
+}
+#else
+void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len)
+{
+    __asm__ __volatile__("push {r3-r6,lr}\n\t"
+                         "Start0 :"
+                         "cmp   r2,#4\n\t"
+                         "blt   Finish0\n\t"
+                         "ldr   r3,[r1]\n\t"
+                         "ldr   r4,[r1]\n\t"
+                         "ldr   r5,[r1]\n\t"
+                         "ldr   r6,[r1]\n\t"
+                         "stmia r0!,{r3-r6}\n\t"
+                         "sub   r2,r2,#4\n\t"
+                         "b     Start0\n\t"
+                         "Finish0 :"
+                         "pop   {r3-r6,pc}\n\t");
+}
+#endif
+#endif
+#ifdef ARCH_RISCV
+void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len)
+{
+    uint32_t wrLen = len - len % 4;
+    uint32_t i;
+
+    for (i = 0; i < wrLen; i++) {
+        dest[i] = *src;
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  PKA Write block data to register
+ *
+ * @param  dest: Pointer to register address
+ * @param  src: Pointer to buffer address
+ * @param  len: Data len in word
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifdef ARCH_ARM
+#ifndef __GNUC__
+__ASM void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len)
+{
+    PUSH  {R3-R6,LR}
+Start1
+    CMP  R2,#4
+    BLT  Finish1
+    LDMIA  R1!,{R3-R6}    
+    STR  R3,[R0]
+    STR  R4,[R0]
+    STR  R5,[R0]
+    STR  R6,[R0]
+    SUBS R2,R2,#4
+    B  Start1
+Finish1
+    POP  {R3-R6,PC}
+}
+#else
+void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len)
+{
+    __asm__ __volatile__("push {r3-r6,lr}\n\t"
+                         "Start1 :"
+                         "cmp   r2,#4\n\t"
+                         "blt   Finish1\n\t"
+                         "ldmia r1!,{r3-r6}\n\t"
+                         "str   r3,[r0]\n\t"
+                         "str   r4,[r0]\n\t"
+                         "str   r5,[r0]\n\t"
+                         "str   r6,[r0]\n\t"
+                         "sub   r2,r2,#4\n\t"
+                         "b     Start1\n\t"
+                         "Finish1 :"
+                         "pop   {r3-r6,pc}\n\t");
+}
+#endif
+#endif
+#ifdef ARCH_RISCV
+void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len)
+{
+    uint32_t wrLen = len - len % 4;
+    uint32_t i;
+
+    for (i = 0; i < wrLen; i++) {
+        *dest = src[i];
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  PKA get result
+ *
+ * @param  result: Pointer to store result
+ * @param  retSize: Result length in word
+ * @param  regLen: register length in byte
+ *
+ * @return None
+ *
+*******************************************************************************/
+static void Sec_Eng_PKA_Get_Result(uint32_t *result, uint8_t retSize, uint16_t regLen)
+{
+    uint32_t ret_data = 0x00;
+    int index = 0x00;
+
+    /* Wait for the result */
+    Sec_Eng_PKA_Wait_ISR();
+    Sec_Eng_PKA_Clear_Int();
+    Sec_Eng_PKA_Read_Block(result, (uint32_t *)(SEC_ENG_BASE + SEC_ENG_SE_PKA_0_RW_OFFSET), retSize);
+    index = retSize - (retSize % 4);
+
+    while (index < retSize) {
+        ret_data = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW);
+        result[index] = ret_data;
+        index++;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA load data to register
+ *
+ * @param  regType: Register type
+ * @param  regIndex: Register index
+ * @param  data: Data buffer
+ * @param  size: Data length in word
+ * @param  lastOp: Last operation
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, const uint32_t *data, uint16_t size, uint8_t lastOp)
+{
+    int index = 0x00;
+    uint16_t regLen = Sec_Eng_PKA_Get_Reg_Size(regType);
+
+    Sec_Eng_PKA_Write_Pld_Cfg(size, regIndex, regType, SEC_ENG_PKA_OP_CTLIR_PLD, lastOp);
+
+    if (size > regLen / 4) {
+        size = regLen / 4;
+    }
+
+    Sec_Eng_PKA_Write_Block((uint32_t *)(SEC_ENG_BASE + SEC_ENG_SE_PKA_0_RW_OFFSET), data, size);
+    index = size - (size % 4);
+
+    while (index < size) {
+        BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, data[index]);
+        index++;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA read data from register
+ *
+ * @param  regType: Register type
+ * @param  regIdx: Register index
+ * @param  result: Data buffer
+ * @param  retSize: Data length in word
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_Read_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIdx, uint32_t *result, uint8_t retSize)
+{
+    uint16_t regSize;
+    uint32_t dummyData = 0;
+
+    regSize = Sec_Eng_PKA_Get_Reg_Size(regType);
+
+    if (retSize > regSize / 4) {
+        result = NULL;
+        return;
+    }
+
+    Sec_Eng_PKA_Write_Pld_Cfg(retSize, regIdx, regType, SEC_ENG_PKA_OP_CFLIR_BUFFER, 1);
+
+    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData);
+
+    Sec_Eng_PKA_Get_Result(result, retSize, regSize);
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA clear register
+ *
+ * @param  dRegType: Register type
+ * @param  dRegIdx: Register index
+ * @param  size: Data length in word
+ * @param  lastOp: Last operation
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_Type dRegType, uint8_t dRegIdx, uint8_t size, uint8_t lastOp)
+{
+    uint32_t dummyData = 0;
+
+    Sec_Eng_PKA_Write_Pld_Cfg(size, dRegIdx, dRegType, SEC_ENG_PKA_OP_CLIR, lastOp);
+    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData);
+
+    if (lastOp) {
+        Sec_Eng_PKA_Wait_ISR();
+        Sec_Eng_PKA_Clear_Int();
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA load data to register
+ *
+ * @param  regType: regType: Register type
+ * @param  regIndex: regIndex: Register index
+ * @param  data: data: Data buffer
+ * @param  lastOp: size: Data length in word
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_Write_Immediate(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, uint32_t data, uint8_t lastOp)
+{
+    struct pka0_pldi_cfg cfg;
+
+    cfg.value.BF.rsvd = 0;
+    cfg.value.BF.d_reg_index = regIndex;
+    cfg.value.BF.d_reg_type = regType;
+    cfg.value.BF.op = SEC_ENG_PKA_OP_SLIR;
+    cfg.value.BF.last_op = lastOp;
+
+    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);
+    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, data);
+
+    if (lastOp) {
+        Sec_Eng_PKA_Wait_ISR();
+        Sec_Eng_PKA_Clear_Int();
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA negative source data:D = (1 << SIZE{S0})-S0
+ *
+ * @param  dRegType: Destination Register type
+ * @param  dRegIdx: Destination Register index
+ * @param  s0RegType: Source Register type
+ * @param  s0RegIdx: Source Register index
+ * @param  lastOp: Last operation
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_NREG(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp)
+{
+    uint32_t dummyData = 0;
+
+    Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_NLIR, lastOp);
+    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData);
+
+    if (lastOp) {
+        Sec_Eng_PKA_Wait_ISR();
+        Sec_Eng_PKA_Clear_Int();
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA move data:D = S0
+ *
+ * @param  dRegType: Destination Register type
+ * @param  dRegIdx: Destination Register index
+ * @param  s0RegType: Source Register type
+ * @param  s0RegIdx: Source Register index
+ * @param  lastOp: Last operation
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_Move_Data(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp)
+{
+    uint32_t dummyData = 0;
+
+    Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MOVDAT, lastOp);
+    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData);
+
+    if (lastOp) {
+        Sec_Eng_PKA_Wait_ISR();
+        Sec_Eng_PKA_Clear_Int();
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA resize data:D = S0, D.Size = S0.Size
+ *
+ * @param  dRegType: Destination Register type
+ * @param  dRegIdx: Destination Register index
+ * @param  s0RegType: Source Register type
+ * @param  s0RegIdx: Source Register index
+ * @param  lastOp: Last operation
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_RESIZE(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp)
+{
+    uint32_t dummyData = 0;
+
+    Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_RESIZE, lastOp);
+    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData);
+
+    if (lastOp) {
+        Sec_Eng_PKA_Wait_ISR();
+        Sec_Eng_PKA_Clear_Int();
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA mod add:D = (S0 + S1) mod S2
+ *
+ * @param  dRegType: Destination Register type
+ * @param  dRegIdx: Destination Register index
+ * @param  s0RegType: Source 0 Register type
+ * @param  s0RegIdx: Source 0 Register index
+ * @param  s1RegType: Source 1 Register type
+ * @param  s1RegIdx: Source 1 Register index
+ * @param  s2RegType: Source 2 Register type
+ * @param  s2RegIdx: Source 2 Register index
+ * @param  lastOp: Last operation
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_MADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                      uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp)
+{
+    Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MADD, lastOp);
+    Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType);
+
+    if (lastOp) {
+        Sec_Eng_PKA_Wait_ISR();
+        Sec_Eng_PKA_Clear_Int();
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA mod sub:D = (S0 - S1) mod S2
+ *
+ * @param  dRegType: Destination Register type
+ * @param  dRegIdx: Destination Register index
+ * @param  s0RegType: Source 0 Register type
+ * @param  s0RegIdx: Source 0 Register index
+ * @param  s1RegType: Source 1 Register type
+ * @param  s1RegIdx: Source 1 Register index
+ * @param  s2RegType: Source 2 Register type
+ * @param  s2RegIdx: Source 2 Register index
+ * @param  lastOp: Last operation
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_MSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                      uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp)
+{
+    Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MSUB, lastOp);
+    Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType);
+
+    if (lastOp) {
+        Sec_Eng_PKA_Wait_ISR();
+        Sec_Eng_PKA_Clear_Int();
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA mod :D = S0 mod S2
+ *
+ * @param  dRegType: Destination Register type
+ * @param  dRegIdx: Destination Register index
+ * @param  s0RegType: Source 0 Register type
+ * @param  s0RegIdx: Source 0 Register index
+ * @param  s2RegType: Source 2 Register type
+ * @param  s2RegIdx: Source 2 Register index
+ * @param  lastOp: Last operation
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_MREM(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                      uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp)
+{
+    Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MREM, lastOp);
+    Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType);
+
+    if (lastOp) {
+        Sec_Eng_PKA_Wait_ISR();
+        Sec_Eng_PKA_Clear_Int();
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA mod mul:D = (S0 * S1) mod S2
+ *
+ * @param  dRegType: Destination Register type
+ * @param  dRegIdx: Destination Register index
+ * @param  s0RegType: Source 0 Register type
+ * @param  s0RegIdx: Source 0 Register index
+ * @param  s1RegType: Source 1 Register type
+ * @param  s1RegIdx: Source 1 Register index
+ * @param  s2RegType: Source 2 Register type
+ * @param  s2RegIdx: Source 2 Register index
+ * @param  lastOp: Last operation
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_MMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                      uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp)
+{
+    Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MMUL, lastOp);
+    Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType);
+
+    if (lastOp) {
+        Sec_Eng_PKA_Wait_ISR();
+        Sec_Eng_PKA_Clear_Int();
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA mod sqr:D = (S0 ^ 2) mod S2
+ *
+ * @param  dRegType: Destination Register type
+ * @param  dRegIdx: Destination Register index
+ * @param  s0RegType: Source 0 Register type
+ * @param  s0RegIdx: Source 0 Register index
+ * @param  s2RegType: Source 2 Register type
+ * @param  s2RegIdx: Source 2 Register index
+ * @param  lastOp: Last operation
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_MSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                      uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp)
+{
+    Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MSQR, lastOp);
+    Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType);
+
+    if (lastOp) {
+        Sec_Eng_PKA_Wait_ISR();
+        Sec_Eng_PKA_Clear_Int();
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA mod exp:D = (S0 ^ S1) mod S2
+ *
+ * @param  dRegType: Destination Register type
+ * @param  dRegIdx: Destination Register index
+ * @param  s0RegType: Source 0 Register type
+ * @param  s0RegIdx: Source 0 Register index
+ * @param  s1RegType: Source 1 Register type
+ * @param  s1RegIdx: Source 1 Register index
+ * @param  s2RegType: Source 2 Register type
+ * @param  s2RegIdx: Source 2 Register index
+ * @param  lastOp: Last operation
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_MEXP(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                      uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp)
+{
+    Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MEXP, lastOp);
+    Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType);
+
+    if (lastOp) {
+        Sec_Eng_PKA_Wait_ISR();
+        Sec_Eng_PKA_Clear_Int();
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA mod exp:D = (S0 ^ (S2-2) ) mod S2
+ *
+ * @param  dRegType: Destination Register type
+ * @param  dRegIdx: Destination Register index
+ * @param  s0RegType: Source 0 Register type
+ * @param  s0RegIdx: Source 0 Register index
+ * @param  s2RegType: Source 2 Register type
+ * @param  s2RegIdx: Source 2 Register index
+ * @param  lastOp: Last operation
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                      uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp)
+{
+    Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MINV, lastOp);
+    Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType);
+
+    if (lastOp) {
+        Sec_Eng_PKA_Wait_ISR();
+        Sec_Eng_PKA_Clear_Int();
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA Report COUT to 1 when S0 < S1
+ *
+ * @param  cout: Compare result
+ * @param  s0RegType: Source 0 Register type
+ * @param  s0RegIdx: Source 0 Register index
+ * @param  s1RegType: Source 1 Register type
+ * @param  s1RegIdx: Source 1 Register index
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_LCMP(uint8_t *cout, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx)
+{
+    uint32_t pka0_ctrl = 0x00;
+
+    Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, 0, 0, SEC_ENG_PKA_OP_LCMP, 1);
+    Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType);
+
+    Sec_Eng_PKA_Wait_ISR();
+    Sec_Eng_PKA_Clear_Int();
+    pka0_ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);
+
+    *cout = (pka0_ctrl & SEC_ENG_PKA_STATUS_LAST_OPC_MASK) >> SEC_ENG_PKA_STATUS_LAST_OPC_OFFSET;
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA add:D = S0 + S1
+ *
+ * @param  dRegType: Destination Register type
+ * @param  dRegIdx: Destination Register index
+ * @param  s0RegType: Source 0 Register type
+ * @param  s0RegIdx: Source 0 Register index
+ * @param  s1RegType: Source 1 Register type
+ * @param  s1RegIdx: Source 1 Register index
+ * @param  lastOp: Last operation
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_LADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                      uint8_t s1RegType, uint8_t s1RegIdx, uint8_t lastOp)
+{
+    Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LADD, lastOp);
+    Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType);
+
+    if (lastOp) {
+        Sec_Eng_PKA_Wait_ISR();
+        Sec_Eng_PKA_Clear_Int();
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA sub:D = S0 - S1
+ *
+ * @param  dRegType: Destination Register type
+ * @param  dRegIdx: Destination Register index
+ * @param  s0RegType: Source 0 Register type
+ * @param  s0RegIdx: Source 0 Register index
+ * @param  s1RegType: Source 1 Register type
+ * @param  s1RegIdx: Source 1 Register index
+ * @param  lastOp: Last operation
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_LSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                      uint8_t s1RegType, uint8_t s1RegIdx, uint8_t lastOp)
+{
+    Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LSUB, lastOp);
+    Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType);
+
+    if (lastOp) {
+        Sec_Eng_PKA_Wait_ISR();
+        Sec_Eng_PKA_Clear_Int();
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA mul:D = S0 * S1
+ *
+ * @param  dRegType: Destination Register type
+ * @param  dRegIdx: Destination Register index
+ * @param  s0RegType: Source 0 Register type
+ * @param  s0RegIdx: Source 0 Register index
+ * @param  s1RegType: Source 1 Register type
+ * @param  s1RegIdx: Source 1 Register index
+ * @param  lastOp: Last operation
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_LMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                      uint8_t s1RegType, uint8_t s1RegIdx, uint8_t lastOp)
+{
+    Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LMUL, lastOp);
+    Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType);
+
+    if (lastOp) {
+        Sec_Eng_PKA_Wait_ISR();
+        Sec_Eng_PKA_Clear_Int();
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA sqr:D = S0^2
+ *
+ * @param  dRegType: Destination Register type
+ * @param  dRegIdx: Destination Register index
+ * @param  s0RegType: Source 0 Register type
+ * @param  s0RegIdx: Source 0 Register index
+ * @param  lastOp: Last operation
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_LSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp)
+{
+    uint32_t dummyData = 0;
+
+    Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LSQR, lastOp);
+    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData);
+
+    if (lastOp) {
+        Sec_Eng_PKA_Wait_ISR();
+        Sec_Eng_PKA_Clear_Int();
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA div:D = S0 / S2
+ *
+ * @param  dRegType: Destination Register type
+ * @param  dRegIdx: Destination Register index
+ * @param  s0RegType: Source 0 Register type
+ * @param  s0RegIdx: Source 0 Register index
+ * @param  s2RegType: Source 2 Register type
+ * @param  s2RegIdx: Source 2 Register index
+ * @param  lastOp: Last operation
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_LDIV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                      uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp)
+{
+    Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LDIV, lastOp);
+    Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType);
+
+    if (lastOp) {
+        Sec_Eng_PKA_Wait_ISR();
+        Sec_Eng_PKA_Clear_Int();
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA shift:D = S0 << BIT SHIFT
+ *
+ * @param  dRegType: Destination Register type
+ * @param  dRegIdx: Destination Register index
+ * @param  s0RegType: Source 0 Register type
+ * @param  s0RegIdx: Source 0 Register index
+ * @param  bit_shift: Bits to shift
+ * @param  lastOp: Last operation
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_LMUL2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                        uint16_t bit_shift, uint8_t lastOp)
+{
+    struct pka0_bit_shift_op_cfg cfg;
+
+    Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LMUL2N, 0);
+
+    cfg.value.BF.bit_shift = bit_shift;
+    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);
+
+    if (lastOp) {
+        Sec_Eng_PKA_Wait_ISR();
+        Sec_Eng_PKA_Clear_Int();
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA shift:D = S0 >> BIT SHIFT
+ *
+ * @param  dRegType: Destination Register type
+ * @param  dRegIdx: Destination Register index
+ * @param  s0RegType: Source 0 Register type
+ * @param  s0RegIdx: Source 0 Register index
+ * @param  bit_shift: Bits to shift
+ * @param  lastOp: Last operation
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_LDIV2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                        uint16_t bit_shift, uint8_t lastOp)
+{
+    struct pka0_bit_shift_op_cfg cfg;
+
+    Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LDIV2N, 0);
+
+    cfg.value.BF.bit_shift = bit_shift;
+    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);
+
+    if (lastOp) {
+        Sec_Eng_PKA_Wait_ISR();
+        Sec_Eng_PKA_Clear_Int();
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA mod 2N:D = S0 % ((1 << BIT SHIFT)-1)
+ *
+ * @param  dRegType: Destination Register type
+ * @param  dRegIdx: Destination Register index
+ * @param  s0RegType: Source 0 Register type
+ * @param  s0RegIdx: Source 0 Register index
+ * @param  bit_shift: Bits to shift
+ * @param  lastOp: Last operation
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Sec_Eng_PKA_LMOD2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
+                        uint16_t bit_shift, uint8_t lastOp)
+{
+    struct pka0_bit_shift_op_cfg cfg;
+
+    Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MOD2N, lastOp);
+
+    cfg.value.BF.bit_shift = bit_shift;
+    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);
+
+    if (lastOp) {
+        Sec_Eng_PKA_Wait_ISR();
+        Sec_Eng_PKA_Clear_Int();
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  PKA GF to Mont  filed 2N:d = (a<
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_glb.h"
+#include "bl702_sf_cfg.h"
+#include "softcrc.h"
+#include "bl702_xip_sflash.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SF_CFG
+ *  @{
+ */
+
+/** @defgroup  SF_CFG_Private_Macros
+ *  @{
+ */
+#define BFLB_FLASH_CFG_MAGIC "FCFG"
+
+/*@} end of group SF_CFG_Private_Macros */
+
+/** @defgroup  SF_CFG_Private_Types
+ *  @{
+ */
+#ifndef BFLB_USE_ROM_DRIVER
+typedef struct
+{
+    uint32_t jedecID;
+    char *name;
+    const SPI_Flash_Cfg_Type *cfg;
+} Flash_Info_t;
+#endif
+
+/*@} end of group SF_CFG_Private_Types */
+
+/** @defgroup  SF_CFG_Private_Variables
+ *  @{
+ */
+#ifndef BFLB_USE_ROM_DRIVER
+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_80DV = {
+    .resetCreadCmd = 0xff,
+    .resetCreadCmdSize = 3,
+    .mid = 0xef,
+
+    .deBurstWrapCmd = 0x77,
+    .deBurstWrapCmdDmyClk = 0x3,
+    .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .deBurstWrapData = 0xF0,
+
+    /*reg*/
+    .writeEnableCmd = 0x06,
+    .wrEnableIndex = 0x00,
+    .wrEnableBit = 0x01,
+    .wrEnableReadRegLen = 0x01,
+
+    .qeIndex = 1,
+    .qeBit = 0x01,
+    .qeWriteRegLen = 0x02,
+    .qeReadRegLen = 0x1,
+
+    .busyIndex = 0,
+    .busyBit = 0x00,
+    .busyReadRegLen = 0x1,
+    .releasePowerDown = 0xab,
+
+    .readRegCmd[0] = 0x05,
+    .readRegCmd[1] = 0x35,
+    .writeRegCmd[0] = 0x01,
+    .writeRegCmd[1] = 0x01,
+
+    .fastReadQioCmd = 0xeb,
+    .frQioDmyClk = 16 / 8,
+    .cReadSupport = 0,
+    .cReadMode = 0xFF,
+
+    .burstWrapCmd = 0x77,
+    .burstWrapCmdDmyClk = 0x3,
+    .burstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .burstWrapData = 0x40,
+    /*erase*/
+    .chipEraseCmd = 0xc7,
+    .sectorEraseCmd = 0x20,
+    .blk32EraseCmd = 0x52,
+    .blk64EraseCmd = 0xd8,
+    /*write*/
+    .pageProgramCmd = 0x02,
+    .qpageProgramCmd = 0x32,
+    .qppAddrMode = SF_CTRL_ADDR_1_LINE,
+
+    .ioMode = SF_CTRL_QIO_MODE,
+    .clkDelay = 1,
+    .clkInvert = 0x3d,
+
+    .resetEnCmd = 0x66,
+    .resetCmd = 0x99,
+    .cRExit = 0xff,
+    .wrEnableWriteRegLen = 0x00,
+
+    /*id*/
+    .jedecIdCmd = 0x9f,
+    .jedecIdCmdDmyClk = 0,
+    .qpiJedecIdCmd = 0x9f,
+    .qpiJedecIdCmdDmyClk = 0x00,
+    .sectorSize = 4,
+    .pageSize = 256,
+
+    /*read*/
+    .fastReadCmd = 0x0b,
+    .frDmyClk = 8 / 8,
+    .qpiFastReadCmd = 0x0b,
+    .qpiFrDmyClk = 8 / 8,
+    .fastReadDoCmd = 0x3b,
+    .frDoDmyClk = 8 / 8,
+    .fastReadDioCmd = 0xbb,
+    .frDioDmyClk = 0,
+    .fastReadQoCmd = 0x6b,
+    .frQoDmyClk = 8 / 8,
+
+    .qpiFastReadQioCmd = 0xeb,
+    .qpiFrQioDmyClk = 16 / 8,
+    .qpiPageProgramCmd = 0x02,
+    .writeVregEnableCmd = 0x50,
+
+    /* qpi mode */
+    .enterQpi = 0x38,
+    .exitQpi = 0xff,
+
+    /*AC*/
+    .timeEsector = 300,
+    .timeE32k = 1200,
+    .timeE64k = 1200,
+    .timePagePgm = 5,
+    .timeCe = 20 * 1000,
+    .pdDelay = 3,
+    .qeData = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_16DV = {
+    .resetCreadCmd = 0xff,
+    .resetCreadCmdSize = 3,
+    .mid = 0xef,
+
+    .deBurstWrapCmd = 0x77,
+    .deBurstWrapCmdDmyClk = 0x3,
+    .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .deBurstWrapData = 0xF0,
+
+    /*reg*/
+    .writeEnableCmd = 0x06,
+    .wrEnableIndex = 0x00,
+    .wrEnableBit = 0x01,
+    .wrEnableReadRegLen = 0x01,
+
+    .qeIndex = 1,
+    .qeBit = 0x01,
+    .qeWriteRegLen = 0x02, /*Q08BV,Q16DV: 0x02.Q32FW,Q32FV: 0x01 */
+    .qeReadRegLen = 0x1,
+
+    .busyIndex = 0,
+    .busyBit = 0x00,
+    .busyReadRegLen = 0x1,
+    .releasePowerDown = 0xab,
+
+    .readRegCmd[0] = 0x05,
+    .readRegCmd[1] = 0x35,
+    .writeRegCmd[0] = 0x01,
+    .writeRegCmd[1] = 0x01,
+
+    .fastReadQioCmd = 0xeb,
+    .frQioDmyClk = 16 / 8,
+    .cReadSupport = 1,
+    .cReadMode = 0x20,
+
+    .burstWrapCmd = 0x77,
+    .burstWrapCmdDmyClk = 0x3,
+    .burstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .burstWrapData = 0x40,
+    /*erase*/
+    .chipEraseCmd = 0xc7,
+    .sectorEraseCmd = 0x20,
+    .blk32EraseCmd = 0x52,
+    .blk64EraseCmd = 0xd8,
+    /*write*/
+    .pageProgramCmd = 0x02,
+    .qpageProgramCmd = 0x32,
+    .qppAddrMode = SF_CTRL_ADDR_1_LINE,
+
+    .ioMode = SF_CTRL_QIO_MODE,
+    .clkDelay = 1,
+    .clkInvert = 0x3d,
+
+    .resetEnCmd = 0x66,
+    .resetCmd = 0x99,
+    .cRExit = 0xff,
+    .wrEnableWriteRegLen = 0x00,
+
+    /*id*/
+    .jedecIdCmd = 0x9f,
+    .jedecIdCmdDmyClk = 0,
+    .qpiJedecIdCmd = 0x9f,
+    .qpiJedecIdCmdDmyClk = 0x00,
+    .sectorSize = 4,
+    .pageSize = 256,
+
+    /*read*/
+    .fastReadCmd = 0x0b,
+    .frDmyClk = 8 / 8,
+    .qpiFastReadCmd = 0x0b,
+    .qpiFrDmyClk = 8 / 8,
+    .fastReadDoCmd = 0x3b,
+    .frDoDmyClk = 8 / 8,
+    .fastReadDioCmd = 0xbb,
+    .frDioDmyClk = 0,
+    .fastReadQoCmd = 0x6b,
+    .frQoDmyClk = 8 / 8,
+
+    .qpiFastReadQioCmd = 0xeb,
+    .qpiFrQioDmyClk = 16 / 8,
+    .qpiPageProgramCmd = 0x02,
+    .writeVregEnableCmd = 0x50,
+
+    /* qpi mode */
+    .enterQpi = 0x38,
+    .exitQpi = 0xff,
+
+    /*AC*/
+    .timeEsector = 300,
+    .timeE32k = 1200,
+    .timeE64k = 1200,
+    .timePagePgm = 5,
+    .timeCe = 20 * 1000,
+    .pdDelay = 3,
+    .qeData = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_80EW_16FW_32JW_32FW_32FV = {
+    .resetCreadCmd = 0xff,
+    .resetCreadCmdSize = 3,
+    .mid = 0xef,
+
+    .deBurstWrapCmd = 0x77,
+    .deBurstWrapCmdDmyClk = 0x3,
+    .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .deBurstWrapData = 0xF0,
+
+    /*reg*/
+    .writeEnableCmd = 0x06,
+    .wrEnableIndex = 0x00,
+    .wrEnableBit = 0x01,
+    .wrEnableReadRegLen = 0x01,
+
+    .qeIndex = 1,
+    .qeBit = 0x01,
+    .qeWriteRegLen = 0x01,
+    .qeReadRegLen = 0x1,
+
+    .busyIndex = 0,
+    .busyBit = 0x00,
+    .busyReadRegLen = 0x1,
+    .releasePowerDown = 0xab,
+
+    .readRegCmd[0] = 0x05,
+    .readRegCmd[1] = 0x35,
+    .writeRegCmd[0] = 0x01,
+    .writeRegCmd[1] = 0x31,
+
+    .fastReadQioCmd = 0xeb,
+    .frQioDmyClk = 16 / 8,
+    .cReadSupport = 1,
+    .cReadMode = 0x20,
+
+    .burstWrapCmd = 0x77,
+    .burstWrapCmdDmyClk = 0x3,
+    .burstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .burstWrapData = 0x40,
+    /*erase*/
+    .chipEraseCmd = 0xc7,
+    .sectorEraseCmd = 0x20,
+    .blk32EraseCmd = 0x52,
+    .blk64EraseCmd = 0xd8,
+    /*write*/
+    .pageProgramCmd = 0x02,
+    .qpageProgramCmd = 0x32,
+    .qppAddrMode = SF_CTRL_ADDR_1_LINE,
+
+    .ioMode = SF_CTRL_QIO_MODE,
+    .clkDelay = 1,
+    .clkInvert = 0x3f,
+
+    .resetEnCmd = 0x66,
+    .resetCmd = 0x99,
+    .cRExit = 0xff,
+    .wrEnableWriteRegLen = 0x00,
+
+    /*id*/
+    .jedecIdCmd = 0x9f,
+    .jedecIdCmdDmyClk = 0,
+    .qpiJedecIdCmd = 0x9f,
+    .qpiJedecIdCmdDmyClk = 0x00,
+    .sectorSize = 4,
+    .pageSize = 256,
+
+    /*read*/
+    .fastReadCmd = 0x0b,
+    .frDmyClk = 8 / 8,
+    .qpiFastReadCmd = 0x0b,
+    .qpiFrDmyClk = 8 / 8,
+    .fastReadDoCmd = 0x3b,
+    .frDoDmyClk = 8 / 8,
+    .fastReadDioCmd = 0xbb,
+    .frDioDmyClk = 0,
+    .fastReadQoCmd = 0x6b,
+    .frQoDmyClk = 8 / 8,
+
+    .qpiFastReadQioCmd = 0xeb,
+    .qpiFrQioDmyClk = 16 / 8,
+    .qpiPageProgramCmd = 0x02,
+    .writeVregEnableCmd = 0x50,
+
+    /* qpi mode */
+    .enterQpi = 0x38,
+    .exitQpi = 0xff,
+
+    /*AC*/
+    .timeEsector = 400,
+    .timeE32k = 1600,
+    .timeE64k = 2000,
+    .timePagePgm = 5,
+    .timeCe = 20 * 1000,
+    .pdDelay = 3,
+    .qeData = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Issi = {
+    .resetCreadCmd = 0xff,
+    .resetCreadCmdSize = 3,
+    .mid = 0x9d,
+
+    .deBurstWrapCmd = 0xC0,
+    .deBurstWrapCmdDmyClk = 0x00,
+    .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE,
+    .deBurstWrapData = 0x00,
+
+    /*reg*/
+    .writeEnableCmd = 0x06,
+    .wrEnableIndex = 0x00,
+    .wrEnableBit = 0x01,
+    .wrEnableReadRegLen = 0x01,
+
+    .qeIndex = 0,
+    .qeBit = 0x06,
+    .qeWriteRegLen = 0x01,
+    .qeReadRegLen = 0x1,
+
+    .busyIndex = 0,
+    .busyBit = 0x00,
+    .busyReadRegLen = 0x1,
+    .releasePowerDown = 0xab,
+
+    .readRegCmd[0] = 0x05,
+    .readRegCmd[1] = 0x35,
+    .writeRegCmd[0] = 0x01,
+    .writeRegCmd[1] = 0x31,
+
+    .fastReadQioCmd = 0xeb,
+    .frQioDmyClk = 16 / 8,
+    .cReadSupport = 1,
+    .cReadMode = 0xA0,
+
+    .burstWrapCmd = 0xC0,
+    .burstWrapCmdDmyClk = 0x00,
+    .burstWrapDataMode = SF_CTRL_DATA_1_LINE,
+    .burstWrapData = 0x06,
+    /*erase*/
+    .chipEraseCmd = 0xc7,
+    .sectorEraseCmd = 0x20,
+    .blk32EraseCmd = 0x52,
+    .blk64EraseCmd = 0xd8,
+    /*write*/
+    .pageProgramCmd = 0x02,
+    .qpageProgramCmd = 0x32,
+    .qppAddrMode = SF_CTRL_ADDR_1_LINE,
+
+    .ioMode = SF_CTRL_QIO_MODE,
+    .clkDelay = 1,
+    .clkInvert = 0x3f,
+
+    .resetEnCmd = 0x66,
+    .resetCmd = 0x99,
+    .cRExit = 0xff,
+    .wrEnableWriteRegLen = 0x00,
+
+    /*id*/
+    .jedecIdCmd = 0x9f,
+    .jedecIdCmdDmyClk = 0,
+    .qpiJedecIdCmd = 0x9f,
+    .qpiJedecIdCmdDmyClk = 0x00,
+    .sectorSize = 4,
+    .pageSize = 256,
+
+    /*read*/
+    .fastReadCmd = 0x0b,
+    .frDmyClk = 8 / 8,
+    .qpiFastReadCmd = 0x0b,
+    .qpiFrDmyClk = 8 / 8,
+    .fastReadDoCmd = 0x3b,
+    .frDoDmyClk = 8 / 8,
+    .fastReadDioCmd = 0xbb,
+    .frDioDmyClk = 0,
+    .fastReadQoCmd = 0x6b,
+    .frQoDmyClk = 8 / 8,
+
+    .qpiFastReadQioCmd = 0xeb,
+    .qpiFrQioDmyClk = 16 / 8,
+    .qpiPageProgramCmd = 0x02,
+    .writeVregEnableCmd = 0x50,
+
+    /* qpi mode */
+    .enterQpi = 0x38,
+    .exitQpi = 0xff,
+
+    /*AC*/
+    .timeEsector = 300,
+    .timeE32k = 1200,
+    .timeE64k = 1200,
+    .timePagePgm = 5,
+    .timeCe = 20 * 1000,
+    .pdDelay = 5,
+    .qeData = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Md_40D = {
+    .resetCreadCmd = 0xff,
+    .resetCreadCmdSize = 3,
+    .mid = 0x51,
+
+    .deBurstWrapCmd = 0x77,
+    .deBurstWrapCmdDmyClk = 0x3,
+    .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .deBurstWrapData = 0xF0,
+
+    /*reg*/
+    .writeEnableCmd = 0x06,
+    .wrEnableIndex = 0x00,
+    .wrEnableBit = 0x01,
+    .wrEnableReadRegLen = 0x01,
+
+    .qeIndex = 1,
+    .qeBit = 0x01,
+    .qeWriteRegLen = 0x02,
+    .qeReadRegLen = 0x1,
+
+    .busyIndex = 0,
+    .busyBit = 0x00,
+    .busyReadRegLen = 0x1,
+    .releasePowerDown = 0xab,
+
+    .readRegCmd[0] = 0x05,
+    .readRegCmd[1] = 0x35,
+    .writeRegCmd[0] = 0x01,
+    .writeRegCmd[1] = 0x01,
+
+    .fastReadQioCmd = 0xeb,
+    .frQioDmyClk = 16 / 8,
+    .cReadSupport = 0,
+    .cReadMode = 0xA0,
+
+    .burstWrapCmd = 0x77,
+    .burstWrapCmdDmyClk = 0x3,
+    .burstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .burstWrapData = 0x40,
+    /*erase*/
+    .chipEraseCmd = 0xc7,
+    .sectorEraseCmd = 0x20,
+    .blk32EraseCmd = 0x52,
+    .blk64EraseCmd = 0xd8,
+    /*write*/
+    .pageProgramCmd = 0x02,
+    .qpageProgramCmd = 0x32,
+    .qppAddrMode = SF_CTRL_ADDR_1_LINE,
+
+    .ioMode = SF_CTRL_DO_MODE,
+    .clkDelay = 1,
+    .clkInvert = 0x3f,
+
+    .resetEnCmd = 0x66,
+    .resetCmd = 0x99,
+    .cRExit = 0xff,
+    .wrEnableWriteRegLen = 0x00,
+
+    /*id*/
+    .jedecIdCmd = 0x9f,
+    .jedecIdCmdDmyClk = 0,
+    .qpiJedecIdCmd = 0x9f,
+    .qpiJedecIdCmdDmyClk = 0x00,
+    .sectorSize = 4,
+    .pageSize = 256,
+
+    /*read*/
+    .fastReadCmd = 0x0b,
+    .frDmyClk = 8 / 8,
+    .qpiFastReadCmd = 0x0b,
+    .qpiFrDmyClk = 8 / 8,
+    .fastReadDoCmd = 0x3b,
+    .frDoDmyClk = 8 / 8,
+    .fastReadDioCmd = 0xbb,
+    .frDioDmyClk = 0,
+    .fastReadQoCmd = 0x6b,
+    .frQoDmyClk = 8 / 8,
+
+    .qpiFastReadQioCmd = 0xeb,
+    .qpiFrQioDmyClk = 16 / 8,
+    .qpiPageProgramCmd = 0x02,
+    .writeVregEnableCmd = 0x50,
+
+    /* qpi mode */
+    .enterQpi = 0x38,
+    .exitQpi = 0xff,
+
+    /*AC*/
+    .timeEsector = 300,
+    .timeE32k = 1200,
+    .timeE64k = 1200,
+    .timePagePgm = 5,
+    .timeCe = 20 * 1000,
+    .pdDelay = 20,
+    .qeData = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E = {
+    .resetCreadCmd = 0xff,
+    .resetCreadCmdSize = 3,
+    .mid = 0xc8,
+
+    .deBurstWrapCmd = 0x77,
+    .deBurstWrapCmdDmyClk = 0x3,
+    .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .deBurstWrapData = 0xF0,
+
+    /*reg*/
+    .writeEnableCmd = 0x06,
+    .wrEnableIndex = 0x00,
+    .wrEnableBit = 0x01,
+    .wrEnableReadRegLen = 0x01,
+
+    .qeIndex = 1,
+    .qeBit = 0x01,
+    .qeWriteRegLen = 0x02,
+    .qeReadRegLen = 0x1,
+
+    .busyIndex = 0,
+    .busyBit = 0x00,
+    .busyReadRegLen = 0x1,
+    .releasePowerDown = 0xab,
+
+    .readRegCmd[0] = 0x05,
+    .readRegCmd[1] = 0x35,
+    .writeRegCmd[0] = 0x01,
+    .writeRegCmd[1] = 0x01,
+
+    .fastReadQioCmd = 0xeb,
+    .frQioDmyClk = 16 / 8,
+    .cReadSupport = 1,
+    .cReadMode = 0x20,
+
+    .burstWrapCmd = 0x77,
+    .burstWrapCmdDmyClk = 0x3,
+    .burstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .burstWrapData = 0x40,
+    /*erase*/
+    .chipEraseCmd = 0xc7,
+    .sectorEraseCmd = 0x20,
+    .blk32EraseCmd = 0x52,
+    .blk64EraseCmd = 0xd8,
+    /*write*/
+    .pageProgramCmd = 0x02,
+    .qpageProgramCmd = 0x32,
+    .qppAddrMode = SF_CTRL_ADDR_1_LINE,
+
+    .ioMode = SF_CTRL_QIO_MODE,
+    .clkDelay = 1,
+    .clkInvert = 0x3f,
+
+    .resetEnCmd = 0x66,
+    .resetCmd = 0x99,
+    .cRExit = 0xff,
+    .wrEnableWriteRegLen = 0x00,
+
+    /*id*/
+    .jedecIdCmd = 0x9f,
+    .jedecIdCmdDmyClk = 0,
+    .qpiJedecIdCmd = 0x9f,
+    .qpiJedecIdCmdDmyClk = 0x00,
+    .sectorSize = 4,
+    .pageSize = 256,
+
+    /*read*/
+    .fastReadCmd = 0x0b,
+    .frDmyClk = 8 / 8,
+    .qpiFastReadCmd = 0x0b,
+    .qpiFrDmyClk = 8 / 8,
+    .fastReadDoCmd = 0x3b,
+    .frDoDmyClk = 8 / 8,
+    .fastReadDioCmd = 0xbb,
+    .frDioDmyClk = 0,
+    .fastReadQoCmd = 0x6b,
+    .frQoDmyClk = 8 / 8,
+
+    .qpiFastReadQioCmd = 0xeb,
+    .qpiFrQioDmyClk = 16 / 8,
+    .qpiPageProgramCmd = 0x02,
+    .writeVregEnableCmd = 0x50,
+
+    /* qpi mode */
+    .enterQpi = 0x38,
+    .exitQpi = 0xff,
+
+    /*AC*/
+    .timeEsector = 300,
+    .timeE32k = 1200,
+    .timeE64k = 1200,
+    .timePagePgm = 5,
+    .timeCe = 20 * 1000,
+    .pdDelay = 20,
+    .qeData = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q80E_Q16E = {
+    .resetCreadCmd = 0xff,
+    .resetCreadCmdSize = 3,
+    .mid = 0xc8,
+
+    .deBurstWrapCmd = 0x77,
+    .deBurstWrapCmdDmyClk = 0x3,
+    .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .deBurstWrapData = 0xF0,
+
+    /*reg*/
+    .writeEnableCmd = 0x06,
+    .wrEnableIndex = 0x00,
+    .wrEnableBit = 0x01,
+    .wrEnableReadRegLen = 0x01,
+
+    .qeIndex = 1,
+    .qeBit = 0x01,
+    .qeWriteRegLen = 0x02,
+    .qeReadRegLen = 0x1,
+
+    .busyIndex = 0,
+    .busyBit = 0x00,
+    .busyReadRegLen = 0x1,
+    .releasePowerDown = 0xab,
+
+    .readRegCmd[0] = 0x05,
+    .readRegCmd[1] = 0x35,
+    .writeRegCmd[0] = 0x01,
+    .writeRegCmd[1] = 0x01,
+
+    .fastReadQioCmd = 0xeb,
+    .frQioDmyClk = 16 / 8,
+    .cReadSupport = 1,
+    .cReadMode = 0xA0,
+
+    .burstWrapCmd = 0x77,
+    .burstWrapCmdDmyClk = 0x3,
+    .burstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .burstWrapData = 0x40,
+    /*erase*/
+    .chipEraseCmd = 0xc7,
+    .sectorEraseCmd = 0x20,
+    .blk32EraseCmd = 0x52,
+    .blk64EraseCmd = 0xd8,
+    /*write*/
+    .pageProgramCmd = 0x02,
+    .qpageProgramCmd = 0x32,
+    .qppAddrMode = SF_CTRL_ADDR_1_LINE,
+
+    .ioMode = SF_CTRL_QIO_MODE,
+    .clkDelay = 1,
+    .clkInvert = 0x3f,
+
+    .resetEnCmd = 0x66,
+    .resetCmd = 0x99,
+    .cRExit = 0xff,
+    .wrEnableWriteRegLen = 0x00,
+
+    /*id*/
+    .jedecIdCmd = 0x9f,
+    .jedecIdCmdDmyClk = 0,
+    .qpiJedecIdCmd = 0x9f,
+    .qpiJedecIdCmdDmyClk = 0x00,
+    .sectorSize = 4,
+    .pageSize = 256,
+
+    /*read*/
+    .fastReadCmd = 0x0b,
+    .frDmyClk = 8 / 8,
+    .qpiFastReadCmd = 0x0b,
+    .qpiFrDmyClk = 8 / 8,
+    .fastReadDoCmd = 0x3b,
+    .frDoDmyClk = 8 / 8,
+    .fastReadDioCmd = 0xbb,
+    .frDioDmyClk = 0,
+    .fastReadQoCmd = 0x6b,
+    .frQoDmyClk = 8 / 8,
+
+    .qpiFastReadQioCmd = 0xeb,
+    .qpiFrQioDmyClk = 16 / 8,
+    .qpiPageProgramCmd = 0x02,
+    .writeVregEnableCmd = 0x50,
+
+    /* qpi mode */
+    .enterQpi = 0x38,
+    .exitQpi = 0xff,
+
+    /*AC*/
+    .timeEsector = 300,
+    .timeE32k = 1200,
+    .timeE64k = 1200,
+    .timePagePgm = 5,
+    .timeCe = 20 * 1000,
+    .pdDelay = 20,
+    .qeData = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_WQ80E_WQ16E = {
+    .resetCreadCmd = 0xff,
+    .resetCreadCmdSize = 3,
+    .mid = 0xc8,
+
+    .deBurstWrapCmd = 0x77,
+    .deBurstWrapCmdDmyClk = 0x3,
+    .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .deBurstWrapData = 0xF0,
+
+    /*reg*/
+    .writeEnableCmd = 0x06,
+    .wrEnableIndex = 0x00,
+    .wrEnableBit = 0x01,
+    .wrEnableReadRegLen = 0x01,
+
+    .qeIndex = 1,
+    .qeBit = 0x01,
+    .qeWriteRegLen = 0x02,
+    .qeReadRegLen = 0x1,
+
+    .busyIndex = 0,
+    .busyBit = 0x00,
+    .busyReadRegLen = 0x1,
+    .releasePowerDown = 0xab,
+
+    .readRegCmd[0] = 0x05,
+    .readRegCmd[1] = 0x35,
+    .writeRegCmd[0] = 0x01,
+    .writeRegCmd[1] = 0x01,
+
+    .fastReadQioCmd = 0xeb,
+    .frQioDmyClk = 32 / 8,
+    .cReadSupport = 1,
+    .cReadMode = 0xA0,
+
+    .burstWrapCmd = 0x77,
+    .burstWrapCmdDmyClk = 0x3,
+    .burstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .burstWrapData = 0x40,
+    /*erase*/
+    .chipEraseCmd = 0xc7,
+    .sectorEraseCmd = 0x20,
+    .blk32EraseCmd = 0x52,
+    .blk64EraseCmd = 0xd8,
+    /*write*/
+    .pageProgramCmd = 0x02,
+    .qpageProgramCmd = 0x32,
+    .qppAddrMode = SF_CTRL_ADDR_1_LINE,
+
+    .ioMode = SF_CTRL_QIO_MODE,
+    .clkDelay = 1,
+    .clkInvert = 0x3f,
+
+    .resetEnCmd = 0x66,
+    .resetCmd = 0x99,
+    .cRExit = 0xff,
+    .wrEnableWriteRegLen = 0x00,
+
+    /*id*/
+    .jedecIdCmd = 0x9f,
+    .jedecIdCmdDmyClk = 0,
+    .qpiJedecIdCmd = 0x9f,
+    .qpiJedecIdCmdDmyClk = 0x00,
+    .sectorSize = 4,
+    .pageSize = 256,
+
+    /*read*/
+    .fastReadCmd = 0x0b,
+    .frDmyClk = 8 / 8,
+    .qpiFastReadCmd = 0x0b,
+    .qpiFrDmyClk = 8 / 8,
+    .fastReadDoCmd = 0x3b,
+    .frDoDmyClk = 8 / 8,
+    .fastReadDioCmd = 0xbb,
+    .frDioDmyClk = 8 / 8,
+    .fastReadQoCmd = 0x6b,
+    .frQoDmyClk = 8 / 8,
+
+    .qpiFastReadQioCmd = 0xeb,
+    .qpiFrQioDmyClk = 16 / 8,
+    .qpiPageProgramCmd = 0x02,
+    .writeVregEnableCmd = 0x50,
+
+    /* qpi mode */
+    .enterQpi = 0x38,
+    .exitQpi = 0xff,
+
+    /*AC*/
+    .timeEsector = 300,
+    .timeE32k = 1200,
+    .timeE64k = 1200,
+    .timePagePgm = 5,
+    .timeCe = 20 * 1000,
+    .pdDelay = 20,
+    .qeData = 0x12,
+};
+
+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q32C = {
+    .resetCreadCmd = 0xff,
+    .resetCreadCmdSize = 3,
+    .mid = 0xc8,
+
+    .deBurstWrapCmd = 0x77,
+    .deBurstWrapCmdDmyClk = 0x3,
+    .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .deBurstWrapData = 0xF0,
+
+    /*reg*/
+    .writeEnableCmd = 0x06,
+    .wrEnableIndex = 0x00,
+    .wrEnableBit = 0x01,
+    .wrEnableReadRegLen = 0x01,
+
+    .qeIndex = 1,
+    .qeBit = 0x01,
+    .qeWriteRegLen = 0x01,
+    .qeReadRegLen = 0x1,
+
+    .busyIndex = 0,
+    .busyBit = 0x00,
+    .busyReadRegLen = 0x1,
+    .releasePowerDown = 0xab,
+
+    .readRegCmd[0] = 0x05,
+    .readRegCmd[1] = 0x35,
+    .writeRegCmd[0] = 0x01,
+    .writeRegCmd[1] = 0x31,
+
+    .fastReadQioCmd = 0xeb,
+    .frQioDmyClk = 16 / 8,
+    .cReadSupport = 1,
+    .cReadMode = 0x20,
+
+    .burstWrapCmd = 0x77,
+    .burstWrapCmdDmyClk = 0x3,
+    .burstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .burstWrapData = 0x40,
+    /*erase*/
+    .chipEraseCmd = 0xc7,
+    .sectorEraseCmd = 0x20,
+    .blk32EraseCmd = 0x52,
+    .blk64EraseCmd = 0xd8,
+    /*write*/
+    .pageProgramCmd = 0x02,
+    .qpageProgramCmd = 0x32,
+    .qppAddrMode = SF_CTRL_ADDR_1_LINE,
+
+    .ioMode = SF_CTRL_QIO_MODE,
+    .clkDelay = 1,
+    .clkInvert = 0x3f,
+
+    .resetEnCmd = 0x66,
+    .resetCmd = 0x99,
+    .cRExit = 0xff,
+    .wrEnableWriteRegLen = 0x00,
+
+    /*id*/
+    .jedecIdCmd = 0x9f,
+    .jedecIdCmdDmyClk = 0,
+    .qpiJedecIdCmd = 0x9f,
+    .qpiJedecIdCmdDmyClk = 0x00,
+    .sectorSize = 4,
+    .pageSize = 256,
+
+    /*read*/
+    .fastReadCmd = 0x0b,
+    .frDmyClk = 8 / 8,
+    .qpiFastReadCmd = 0x0b,
+    .qpiFrDmyClk = 8 / 8,
+    .fastReadDoCmd = 0x3b,
+    .frDoDmyClk = 8 / 8,
+    .fastReadDioCmd = 0xbb,
+    .frDioDmyClk = 0,
+    .fastReadQoCmd = 0x6b,
+    .frQoDmyClk = 8 / 8,
+
+    .qpiFastReadQioCmd = 0xeb,
+    .qpiFrQioDmyClk = 16 / 8,
+    .qpiPageProgramCmd = 0x02,
+    .writeVregEnableCmd = 0x50,
+
+    /* qpi mode */
+    .enterQpi = 0x38,
+    .exitQpi = 0xff,
+
+    /*AC*/
+    .timeEsector = 300,
+    .timeE32k = 1200,
+    .timeE64k = 1200,
+    .timePagePgm = 5,
+    .timeCe = 20 * 1000,
+    .pdDelay = 20,
+    .qeData = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic = {
+    .resetCreadCmd = 0xff,
+    .resetCreadCmdSize = 3,
+    .mid = 0xC2,
+
+    .deBurstWrapCmd = 0xC0,
+    .deBurstWrapCmdDmyClk = 0x00,
+    .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE,
+    .deBurstWrapData = 0x10,
+
+    /*reg*/
+    .writeEnableCmd = 0x06,
+    .wrEnableIndex = 0x00,
+    .wrEnableBit = 0x01,
+    .wrEnableReadRegLen = 0x01,
+
+    .qeIndex = 0,
+    .qeBit = 0x06,
+    .qeWriteRegLen = 0x02,
+    .qeReadRegLen = 0x1,
+
+    .busyIndex = 0,
+    .busyBit = 0x00,
+    .busyReadRegLen = 0x1,
+    .releasePowerDown = 0xab,
+
+    .readRegCmd[0] = 0x05,
+    .readRegCmd[1] = 0x35,
+    .writeRegCmd[0] = 0x01,
+    .writeRegCmd[1] = 0x01,
+
+    .fastReadQioCmd = 0xeb,
+    .frQioDmyClk = 16 / 8,
+    .cReadSupport = 1,
+    .cReadMode = 0xA5,
+
+    .burstWrapCmd = 0xC0,
+    .burstWrapCmdDmyClk = 0x00,
+    .burstWrapDataMode = SF_CTRL_DATA_1_LINE,
+    .burstWrapData = 0x02,
+    /*erase*/
+    .chipEraseCmd = 0xc7,
+    .sectorEraseCmd = 0x20,
+    .blk32EraseCmd = 0x52,
+    .blk64EraseCmd = 0xd8,
+    /*write*/
+    .pageProgramCmd = 0x02,
+    .qpageProgramCmd = 0x38,
+    .qppAddrMode = SF_CTRL_ADDR_4_LINES,
+
+    .ioMode = SF_CTRL_QIO_MODE,
+    .clkDelay = 1,
+    .clkInvert = 0x3f,
+
+    .resetEnCmd = 0x66,
+    .resetCmd = 0x99,
+    .cRExit = 0xff,
+    .wrEnableWriteRegLen = 0x00,
+
+    /*id*/
+    .jedecIdCmd = 0x9f,
+    .jedecIdCmdDmyClk = 0,
+    .qpiJedecIdCmd = 0x9f,
+    .qpiJedecIdCmdDmyClk = 0x00,
+    .sectorSize = 4,
+    .pageSize = 256,
+
+    /*read*/
+    .fastReadCmd = 0x0b,
+    .frDmyClk = 8 / 8,
+    .qpiFastReadCmd = 0x0b,
+    .qpiFrDmyClk = 8 / 8,
+    .fastReadDoCmd = 0x3b,
+    .frDoDmyClk = 8 / 8,
+    .fastReadDioCmd = 0xbb,
+    .frDioDmyClk = 0,
+    .fastReadQoCmd = 0x6b,
+    .frQoDmyClk = 8 / 8,
+
+    .qpiFastReadQioCmd = 0xeb,
+    .qpiFrQioDmyClk = 16 / 8,
+    .qpiPageProgramCmd = 0x02,
+    .writeVregEnableCmd = 0x50,
+
+    /* qpi mode */
+    .enterQpi = 0x38,
+    .exitQpi = 0xff,
+
+    /*AC*/
+    .timeEsector = 300,
+    .timeE32k = 1200,
+    .timeE64k = 1200,
+    .timePagePgm = 5,
+    .timeCe = 20 * 1000,
+    .pdDelay = 45,
+    .qeData = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic_1635F = {
+    .resetCreadCmd = 0xff,
+    .resetCreadCmdSize = 3,
+    .mid = 0xC2,
+
+    .deBurstWrapCmd = 0xC0,
+    .deBurstWrapCmdDmyClk = 0x00,
+    .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE,
+    .deBurstWrapData = 0x10,
+
+    /*reg*/
+    .writeEnableCmd = 0x06,
+    .wrEnableIndex = 0x00,
+    .wrEnableBit = 0x01,
+    .wrEnableReadRegLen = 0x01,
+
+    .qeIndex = 0,
+    .qeBit = 0x06,
+    .qeWriteRegLen = 0x01,
+    .qeReadRegLen = 0x1,
+
+    .busyIndex = 0,
+    .busyBit = 0x00,
+    .busyReadRegLen = 0x1,
+    .releasePowerDown = 0xab,
+
+    .readRegCmd[0] = 0x05,
+    .readRegCmd[1] = 0x35,
+    .writeRegCmd[0] = 0x01,
+    .writeRegCmd[1] = 0x01,
+
+    .fastReadQioCmd = 0xeb,
+    .frQioDmyClk = 16 / 8,
+    .cReadSupport = 1,
+    .cReadMode = 0xA5,
+
+    .burstWrapCmd = 0xC0,
+    .burstWrapCmdDmyClk = 0x00,
+    .burstWrapDataMode = SF_CTRL_DATA_1_LINE,
+    .burstWrapData = 0x02,
+    /*erase*/
+    .chipEraseCmd = 0xc7,
+    .sectorEraseCmd = 0x20,
+    .blk32EraseCmd = 0x52,
+    .blk64EraseCmd = 0xd8,
+    /*write*/
+    .pageProgramCmd = 0x02,
+    .qpageProgramCmd = 0x38,
+    .qppAddrMode = SF_CTRL_ADDR_4_LINES,
+
+    .ioMode = SF_CTRL_QIO_MODE,
+    .clkDelay = 1,
+    .clkInvert = 0x3f,
+
+    .resetEnCmd = 0x66,
+    .resetCmd = 0x99,
+    .cRExit = 0xff,
+    .wrEnableWriteRegLen = 0x00,
+
+    /*id*/
+    .jedecIdCmd = 0x9f,
+    .jedecIdCmdDmyClk = 0,
+    .qpiJedecIdCmd = 0x9f,
+    .qpiJedecIdCmdDmyClk = 0x00,
+    .sectorSize = 4,
+    .pageSize = 256,
+
+    /*read*/
+    .fastReadCmd = 0x0b,
+    .frDmyClk = 8 / 8,
+    .qpiFastReadCmd = 0x0b,
+    .qpiFrDmyClk = 8 / 8,
+    .fastReadDoCmd = 0x3b,
+    .frDoDmyClk = 8 / 8,
+    .fastReadDioCmd = 0xbb,
+    .frDioDmyClk = 0,
+    .fastReadQoCmd = 0x6b,
+    .frQoDmyClk = 8 / 8,
+
+    .qpiFastReadQioCmd = 0xeb,
+    .qpiFrQioDmyClk = 16 / 8,
+    .qpiPageProgramCmd = 0x02,
+    .writeVregEnableCmd = 0x50,
+
+    /* qpi mode */
+    .enterQpi = 0x38,
+    .exitQpi = 0xff,
+
+    /*AC*/
+    .timeEsector = 300,
+    .timeE32k = 1200,
+    .timeE64k = 1200,
+    .timePagePgm = 5,
+    .timeCe = 20 * 1000,
+    .pdDelay = 45,
+    .qeData = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Xtx40 = {
+    .resetCreadCmd = 0xff,
+    .resetCreadCmdSize = 3,
+    .mid = 0x0B,
+
+    .deBurstWrapCmd = 0x77,
+    .deBurstWrapCmdDmyClk = 0x3,
+    .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .deBurstWrapData = 0xF0,
+
+    /*reg*/
+    .writeEnableCmd = 0x06,
+    .wrEnableIndex = 0x00,
+    .wrEnableBit = 0x01,
+    .wrEnableReadRegLen = 0x01,
+
+    .qeIndex = 0x01,
+    .qeBit = 0x01,
+    .qeWriteRegLen = 0x02,
+    .qeReadRegLen = 0x1,
+
+    .busyIndex = 0,
+    .busyBit = 0x00,
+    .busyReadRegLen = 0x1,
+    .releasePowerDown = 0xab,
+
+    .readRegCmd[0] = 0x05,
+    .readRegCmd[1] = 0x35,
+    .writeRegCmd[0] = 0x01,
+    .writeRegCmd[1] = 0x01,
+
+    .fastReadQioCmd = 0xeb,
+    .frQioDmyClk = 16 / 8,
+    .cReadSupport = 1,
+    .cReadMode = 0x20,
+
+    .burstWrapCmd = 0x77,
+    .burstWrapCmdDmyClk = 0x3,
+    .burstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .burstWrapData = 0x40,
+    /*erase*/
+    .chipEraseCmd = 0xc7,
+    .sectorEraseCmd = 0x20,
+    .blk32EraseCmd = 0x52,
+    .blk64EraseCmd = 0xd8,
+    /*write*/
+    .pageProgramCmd = 0x02,
+    .qpageProgramCmd = 0x32,
+    .qppAddrMode = SF_CTRL_ADDR_1_LINE,
+
+    .ioMode = SF_CTRL_DIO_MODE,
+    .clkDelay = 1,
+    .clkInvert = 0x3f,
+
+    .resetEnCmd = 0x66,
+    .resetCmd = 0x99,
+    .cRExit = 0xff,
+    .wrEnableWriteRegLen = 0x00,
+    /*id*/
+    .jedecIdCmd = 0x9f,
+    .jedecIdCmdDmyClk = 0,
+    .qpiJedecIdCmd = 0x9f,
+    .qpiJedecIdCmdDmyClk = 0x00,
+    .sectorSize = 4,
+    .pageSize = 256,
+
+    /*read*/
+    .fastReadCmd = 0x0b,
+    .frDmyClk = 8 / 8,
+    .qpiFastReadCmd = 0x0b,
+    .qpiFrDmyClk = 8 / 8,
+    .fastReadDoCmd = 0x3b,
+    .frDoDmyClk = 8 / 8,
+    .fastReadDioCmd = 0xbb,
+    .frDioDmyClk = 0,
+    .fastReadQoCmd = 0x6b,
+    .frQoDmyClk = 8 / 8,
+
+    .qpiFastReadQioCmd = 0xeb,
+    .qpiFrQioDmyClk = 16 / 8,
+    .qpiPageProgramCmd = 0x02,
+    .writeVregEnableCmd = 0x50,
+
+    /* qpi mode */
+    .enterQpi = 0x38,
+    .exitQpi = 0xff,
+
+    /*AC*/
+    .timeEsector = 6000,
+    .timeE32k = 1200,
+    .timeE64k = 1200,
+    .timePagePgm = 5,
+    .timeCe = 20 * 1000,
+    .pdDelay = 20,
+    .qeData = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Xtx = {
+    .resetCreadCmd = 0xff,
+    .resetCreadCmdSize = 3,
+    .mid = 0x0B,
+
+    .deBurstWrapCmd = 0x77,
+    .deBurstWrapCmdDmyClk = 0x3,
+    .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .deBurstWrapData = 0xF0,
+
+    /*reg*/
+    .writeEnableCmd = 0x06,
+    .wrEnableIndex = 0x00,
+    .wrEnableBit = 0x01,
+    .wrEnableReadRegLen = 0x01,
+
+    .qeIndex = 0x01,
+    .qeBit = 0x01,
+    .qeWriteRegLen = 0x02,
+    .qeReadRegLen = 0x1,
+
+    .busyIndex = 0,
+    .busyBit = 0x00,
+    .busyReadRegLen = 0x1,
+    .releasePowerDown = 0xab,
+
+    .readRegCmd[0] = 0x05,
+    .readRegCmd[1] = 0x35,
+    .writeRegCmd[0] = 0x01,
+    .writeRegCmd[1] = 0x01,
+
+    .fastReadQioCmd = 0xeb,
+    .frQioDmyClk = 16 / 8,
+    .cReadSupport = 1,
+    .cReadMode = 0x20,
+
+    .burstWrapCmd = 0x77,
+    .burstWrapCmdDmyClk = 0x3,
+    .burstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .burstWrapData = 0x40,
+    /*erase*/
+    .chipEraseCmd = 0xc7,
+    .sectorEraseCmd = 0x20,
+    .blk32EraseCmd = 0x52,
+    .blk64EraseCmd = 0xd8,
+    /*write*/
+    .pageProgramCmd = 0x02,
+    .qpageProgramCmd = 0x32,
+    .qppAddrMode = SF_CTRL_ADDR_1_LINE,
+
+    .ioMode = SF_CTRL_QIO_MODE,
+    .clkDelay = 1,
+    .clkInvert = 0x3f,
+
+    .resetEnCmd = 0x66,
+    .resetCmd = 0x99,
+    .cRExit = 0xff,
+    .wrEnableWriteRegLen = 0x00,
+    /*id*/
+    .jedecIdCmd = 0x9f,
+    .jedecIdCmdDmyClk = 0,
+    .qpiJedecIdCmd = 0x9f,
+    .qpiJedecIdCmdDmyClk = 0x00,
+    .sectorSize = 4,
+    .pageSize = 256,
+
+    /*read*/
+    .fastReadCmd = 0x0b,
+    .frDmyClk = 8 / 8,
+    .qpiFastReadCmd = 0x0b,
+    .qpiFrDmyClk = 8 / 8,
+    .fastReadDoCmd = 0x3b,
+    .frDoDmyClk = 8 / 8,
+    .fastReadDioCmd = 0xbb,
+    .frDioDmyClk = 0,
+    .fastReadQoCmd = 0x6b,
+    .frQoDmyClk = 8 / 8,
+
+    .qpiFastReadQioCmd = 0xeb,
+    .qpiFrQioDmyClk = 16 / 8,
+    .qpiPageProgramCmd = 0x02,
+    .writeVregEnableCmd = 0x50,
+
+    /* qpi mode */
+    .enterQpi = 0x38,
+    .exitQpi = 0xff,
+
+    /*AC*/
+    .timeEsector = 6000,
+    .timeE32k = 1200,
+    .timeE64k = 1200,
+    .timePagePgm = 5,
+    .timeCe = 20 * 1000,
+    .pdDelay = 20,
+    .qeData = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Puya_Q80L_Q80H_Q16H = {
+    .resetCreadCmd = 0xff,
+    .resetCreadCmdSize = 3,
+    .mid = 0x85,
+
+    .deBurstWrapCmd = 0x77,
+    .deBurstWrapCmdDmyClk = 0x3,
+    .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .deBurstWrapData = 0xF0,
+
+    /*reg*/
+    .writeEnableCmd = 0x06,
+    .wrEnableIndex = 0x00,
+    .wrEnableBit = 0x01,
+    .wrEnableReadRegLen = 0x01,
+
+    .qeIndex = 0x01,
+    .qeBit = 0x01,
+    .qeWriteRegLen = 0x02,
+    .qeReadRegLen = 0x1,
+
+    .busyIndex = 0,
+    .busyBit = 0x00,
+    .busyReadRegLen = 0x1,
+    .releasePowerDown = 0xab,
+
+    .readRegCmd[0] = 0x05,
+    .readRegCmd[1] = 0x35,
+    .writeRegCmd[0] = 0x01,
+    .writeRegCmd[1] = 0x01,
+
+    .fastReadQioCmd = 0xeb,
+    .frQioDmyClk = 16 / 8,
+    .cReadSupport = 1,
+    .cReadMode = 0x20,
+
+    .burstWrapCmd = 0x77,
+    .burstWrapCmdDmyClk = 0x3,
+    .burstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .burstWrapData = 0x40,
+    /*erase*/
+    .chipEraseCmd = 0xc7,
+    .sectorEraseCmd = 0x20,
+    .blk32EraseCmd = 0x52,
+    .blk64EraseCmd = 0xd8,
+    /*write*/
+    .pageProgramCmd = 0x02,
+    .qpageProgramCmd = 0x32,
+    .qppAddrMode = SF_CTRL_ADDR_1_LINE,
+
+    .ioMode = SF_CTRL_QIO_MODE,
+    .clkDelay = 1,
+    .clkInvert = 0x3d,
+
+    .resetEnCmd = 0x66,
+    .resetCmd = 0x99,
+    .cRExit = 0xff,
+    .wrEnableWriteRegLen = 0x00,
+    /*id*/
+    .jedecIdCmd = 0x9f,
+    .jedecIdCmdDmyClk = 0,
+    .qpiJedecIdCmd = 0x9f,
+    .qpiJedecIdCmdDmyClk = 0x00,
+    .sectorSize = 4,
+    .pageSize = 256,
+
+    /*read*/
+    .fastReadCmd = 0x0b,
+    .frDmyClk = 8 / 8,
+    .qpiFastReadCmd = 0x0b,
+    .qpiFrDmyClk = 8 / 8,
+    .fastReadDoCmd = 0x3b,
+    .frDoDmyClk = 8 / 8,
+    .fastReadDioCmd = 0xbb,
+    .frDioDmyClk = 0,
+    .fastReadQoCmd = 0x6b,
+    .frQoDmyClk = 8 / 8,
+
+    .qpiFastReadQioCmd = 0xeb,
+    .qpiFrQioDmyClk = 16 / 8,
+    .qpiPageProgramCmd = 0x02,
+    .writeVregEnableCmd = 0x50,
+
+    /* qpi mode */
+    .enterQpi = 0x38,
+    .exitQpi = 0xff,
+
+    /*AC*/
+    .timeEsector = 300,
+    .timeE32k = 1200,
+    .timeE64k = 1200,
+    .timePagePgm = 5,
+    .timeCe = 20 * 1000,
+    .pdDelay = 8,
+    .qeData = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Puya_Q32H = {
+    .resetCreadCmd = 0xff,
+    .resetCreadCmdSize = 3,
+    .mid = 0x85,
+
+    .deBurstWrapCmd = 0x77,
+    .deBurstWrapCmdDmyClk = 0x3,
+    .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .deBurstWrapData = 0xF0,
+
+    /*reg*/
+    .writeEnableCmd = 0x06,
+    .wrEnableIndex = 0x00,
+    .wrEnableBit = 0x01,
+    .wrEnableReadRegLen = 0x01,
+
+    .qeIndex = 0x01,
+    .qeBit = 0x01,
+    .qeWriteRegLen = 0x01,
+    .qeReadRegLen = 0x1,
+
+    .busyIndex = 0,
+    .busyBit = 0x00,
+    .busyReadRegLen = 0x1,
+    .releasePowerDown = 0xab,
+
+    .readRegCmd[0] = 0x05,
+    .readRegCmd[1] = 0x35,
+    .writeRegCmd[0] = 0x01,
+    .writeRegCmd[1] = 0x31,
+
+    .fastReadQioCmd = 0xeb,
+    .frQioDmyClk = 16 / 8,
+    .cReadSupport = 1,
+    .cReadMode = 0x20,
+
+    .burstWrapCmd = 0x77,
+    .burstWrapCmdDmyClk = 0x3,
+    .burstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .burstWrapData = 0x40,
+    /*erase*/
+    .chipEraseCmd = 0xc7,
+    .sectorEraseCmd = 0x20,
+    .blk32EraseCmd = 0x52,
+    .blk64EraseCmd = 0xd8,
+    /*write*/
+    .pageProgramCmd = 0x02,
+    .qpageProgramCmd = 0x32,
+    .qppAddrMode = SF_CTRL_ADDR_1_LINE,
+
+    .ioMode = SF_CTRL_QIO_MODE,
+    .clkDelay = 1,
+    .clkInvert = 0x3f,
+
+    .resetEnCmd = 0x66,
+    .resetCmd = 0x99,
+    .cRExit = 0xff,
+    .wrEnableWriteRegLen = 0x00,
+    /*id*/
+    .jedecIdCmd = 0x9f,
+    .jedecIdCmdDmyClk = 0,
+    .qpiJedecIdCmd = 0x9f,
+    .qpiJedecIdCmdDmyClk = 0x00,
+    .sectorSize = 4,
+    .pageSize = 256,
+
+    /*read*/
+    .fastReadCmd = 0x0b,
+    .frDmyClk = 8 / 8,
+    .qpiFastReadCmd = 0x0b,
+    .qpiFrDmyClk = 8 / 8,
+    .fastReadDoCmd = 0x3b,
+    .frDoDmyClk = 8 / 8,
+    .fastReadDioCmd = 0xbb,
+    .frDioDmyClk = 0,
+    .fastReadQoCmd = 0x6b,
+    .frQoDmyClk = 8 / 8,
+
+    .qpiFastReadQioCmd = 0xeb,
+    .qpiFrQioDmyClk = 16 / 8,
+    .qpiPageProgramCmd = 0x02,
+    .writeVregEnableCmd = 0x50,
+
+    /* qpi mode */
+    .enterQpi = 0x38,
+    .exitQpi = 0xff,
+
+    /*AC*/
+    .timeEsector = 300,
+    .timeE32k = 1200,
+    .timeE64k = 1200,
+    .timePagePgm = 5,
+    .timeCe = 20 * 1000,
+    .pdDelay = 8,
+    .qeData = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Boya40 = {
+    .resetCreadCmd = 0xff,
+    .resetCreadCmdSize = 3,
+    .mid = 0x68,
+
+    .deBurstWrapCmd = 0x77,
+    .deBurstWrapCmdDmyClk = 0x3,
+    .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .deBurstWrapData = 0xF0,
+
+    /*reg*/
+    .writeEnableCmd = 0x06,
+    .wrEnableIndex = 0x00,
+    .wrEnableBit = 0x01,
+    .wrEnableReadRegLen = 0x01,
+
+    .qeIndex = 1,
+    .qeBit = 0x01,
+    .qeWriteRegLen = 0x02,
+    .qeReadRegLen = 0x1,
+
+    .busyIndex = 0,
+    .busyBit = 0x00,
+    .busyReadRegLen = 0x1,
+    .releasePowerDown = 0xab,
+
+    .readRegCmd[0] = 0x05,
+    .readRegCmd[1] = 0x35,
+    .writeRegCmd[0] = 0x01,
+    .writeRegCmd[1] = 0x01,
+
+    .fastReadQioCmd = 0xeb,
+    .frQioDmyClk = 16 / 8,
+    .cReadSupport = 0,
+    .cReadMode = 0xA0,
+
+    .burstWrapCmd = 0x77,
+    .burstWrapCmdDmyClk = 0x3,
+    .burstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .burstWrapData = 0x40,
+    /*erase*/
+    .chipEraseCmd = 0xc7,
+    .sectorEraseCmd = 0x20,
+    .blk32EraseCmd = 0x52,
+    .blk64EraseCmd = 0xd8,
+    /*write*/
+    .pageProgramCmd = 0x02,
+    .qpageProgramCmd = 0x32,
+    .qppAddrMode = SF_CTRL_ADDR_1_LINE,
+
+    .ioMode = SF_CTRL_DO_MODE,
+    .clkDelay = 1,
+    .clkInvert = 0x3f,
+
+    .resetEnCmd = 0x66,
+    .resetCmd = 0x99,
+    .cRExit = 0xff,
+    .wrEnableWriteRegLen = 0x00,
+
+    /*id*/
+    .jedecIdCmd = 0x9f,
+    .jedecIdCmdDmyClk = 0,
+    .qpiJedecIdCmd = 0x9f,
+    .qpiJedecIdCmdDmyClk = 0x00,
+    .sectorSize = 4,
+    .pageSize = 256,
+
+    /*read*/
+    .fastReadCmd = 0x0b,
+    .frDmyClk = 8 / 8,
+    .qpiFastReadCmd = 0x0b,
+    .qpiFrDmyClk = 8 / 8,
+    .fastReadDoCmd = 0x3b,
+    .frDoDmyClk = 8 / 8,
+    .fastReadDioCmd = 0xbb,
+    .frDioDmyClk = 0,
+    .fastReadQoCmd = 0x6b,
+    .frQoDmyClk = 8 / 8,
+
+    .qpiFastReadQioCmd = 0xeb,
+    .qpiFrQioDmyClk = 16 / 8,
+    .qpiPageProgramCmd = 0x02,
+    .writeVregEnableCmd = 0x50,
+
+    /* qpi mode */
+    .enterQpi = 0x38,
+    .exitQpi = 0xff,
+
+    /*AC*/
+    .timeEsector = 300,
+    .timeE32k = 1200,
+    .timeE64k = 1200,
+    .timePagePgm = 5,
+    .timeCe = 20 * 1000,
+    .pdDelay = 20,
+    .qeData = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Boya = {
+    .resetCreadCmd = 0xff,
+    .resetCreadCmdSize = 3,
+    .mid = 0x68,
+
+    .deBurstWrapCmd = 0x77,
+    .deBurstWrapCmdDmyClk = 0x3,
+    .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .deBurstWrapData = 0xF0,
+
+    /*reg*/
+    .writeEnableCmd = 0x06,
+    .wrEnableIndex = 0x00,
+    .wrEnableBit = 0x01,
+    .wrEnableReadRegLen = 0x01,
+
+    .qeIndex = 0x01,
+    .qeBit = 0x01,
+    .qeWriteRegLen = 0x01,
+    .qeReadRegLen = 0x1,
+
+    .busyIndex = 0,
+    .busyBit = 0x00,
+    .busyReadRegLen = 0x1,
+    .releasePowerDown = 0xab,
+
+    .readRegCmd[0] = 0x05,
+    .readRegCmd[1] = 0x35,
+    .writeRegCmd[0] = 0x01,
+    .writeRegCmd[1] = 0x31,
+
+    .fastReadQioCmd = 0xeb,
+    .frQioDmyClk = 16 / 8,
+    .cReadSupport = 1,
+    .cReadMode = 0x20,
+
+    .burstWrapCmd = 0x77,
+    .burstWrapCmdDmyClk = 0x3,
+    .burstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .burstWrapData = 0x40,
+    /*erase*/
+    .chipEraseCmd = 0xc7,
+    .sectorEraseCmd = 0x20,
+    .blk32EraseCmd = 0x52,
+    .blk64EraseCmd = 0xd8,
+    /*write*/
+    .pageProgramCmd = 0x02,
+    .qpageProgramCmd = 0x32,
+    .qppAddrMode = SF_CTRL_ADDR_1_LINE,
+
+    .ioMode = SF_CTRL_QIO_MODE,
+    .clkDelay = 1,
+    .clkInvert = 0x3f,
+
+    .resetEnCmd = 0x66,
+    .resetCmd = 0x99,
+    .cRExit = 0xff,
+    .wrEnableWriteRegLen = 0x00,
+    /*id*/
+    .jedecIdCmd = 0x9f,
+    .jedecIdCmdDmyClk = 0,
+    .qpiJedecIdCmd = 0x9f,
+    .qpiJedecIdCmdDmyClk = 0x00,
+    .sectorSize = 4,
+    .pageSize = 256,
+
+    /*read*/
+    .fastReadCmd = 0x0b,
+    .frDmyClk = 8 / 8,
+    .qpiFastReadCmd = 0x0b,
+    .qpiFrDmyClk = 8 / 8,
+    .fastReadDoCmd = 0x3b,
+    .frDoDmyClk = 8 / 8,
+    .fastReadDioCmd = 0xbb,
+    .frDioDmyClk = 0,
+    .fastReadQoCmd = 0x6b,
+    .frQoDmyClk = 8 / 8,
+
+    .qpiFastReadQioCmd = 0xeb,
+    .qpiFrQioDmyClk = 16 / 8,
+    .qpiPageProgramCmd = 0x02,
+    .writeVregEnableCmd = 0x50,
+
+    /* qpi mode */
+    .enterQpi = 0x38,
+    .exitQpi = 0xff,
+
+    /*AC*/
+    .timeEsector = 300,
+    .timeE32k = 1200,
+    .timeE64k = 1200,
+    .timePagePgm = 5,
+    .timeCe = 20 * 1000,
+    .pdDelay = 20,
+    .qeData = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_FT_VQ80 = {
+    .resetCreadCmd = 0xff,
+    .resetCreadCmdSize = 3,
+    .mid = 0xef,
+
+    .deBurstWrapCmd = 0x77,
+    .deBurstWrapCmdDmyClk = 0x3,
+    .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .deBurstWrapData = 0xF0,
+
+    /*reg*/
+    .writeEnableCmd = 0x06,
+    .wrEnableIndex = 0x00,
+    .wrEnableBit = 0x01,
+    .wrEnableReadRegLen = 0x01,
+
+    .qeIndex = 1,
+    .qeBit = 0x01,
+    .qeWriteRegLen = 0x01,
+    .qeReadRegLen = 0x1,
+
+    .busyIndex = 0,
+    .busyBit = 0x00,
+    .busyReadRegLen = 0x1,
+    .releasePowerDown = 0xab,
+
+    .readRegCmd[0] = 0x05,
+    .readRegCmd[1] = 0x35,
+    .writeRegCmd[0] = 0x01,
+    .writeRegCmd[1] = 0x31,
+
+    .fastReadQioCmd = 0xeb,
+    .frQioDmyClk = 16 / 8,
+    .cReadSupport = 1,
+    .cReadMode = 0x20,
+
+    .burstWrapCmd = 0x77,
+    .burstWrapCmdDmyClk = 0x3,
+    .burstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .burstWrapData = 0x40,
+    /*erase*/
+    .chipEraseCmd = 0xc7,
+    .sectorEraseCmd = 0x20,
+    .blk32EraseCmd = 0x52,
+    .blk64EraseCmd = 0xd8,
+    /*write*/
+    .pageProgramCmd = 0x02,
+    .qpageProgramCmd = 0x32,
+    .qppAddrMode = SF_CTRL_ADDR_1_LINE,
+
+    .ioMode = SF_CTRL_QIO_MODE,
+    .clkDelay = 1,
+    .clkInvert = 0x3f,
+
+    .resetEnCmd = 0x66,
+    .resetCmd = 0x99,
+    .cRExit = 0xff,
+    .wrEnableWriteRegLen = 0x00,
+
+    /*id*/
+    .jedecIdCmd = 0x9f,
+    .jedecIdCmdDmyClk = 0,
+    .qpiJedecIdCmd = 0x9f,
+    .qpiJedecIdCmdDmyClk = 0x00,
+    .sectorSize = 4,
+    .pageSize = 256,
+
+    /*read*/
+    .fastReadCmd = 0x0b,
+    .frDmyClk = 8 / 8,
+    .qpiFastReadCmd = 0x0b,
+    .qpiFrDmyClk = 8 / 8,
+    .fastReadDoCmd = 0x3b,
+    .frDoDmyClk = 8 / 8,
+    .fastReadDioCmd = 0xbb,
+    .frDioDmyClk = 0,
+    .fastReadQoCmd = 0x6b,
+    .frQoDmyClk = 8 / 8,
+
+    .qpiFastReadQioCmd = 0xeb,
+    .qpiFrQioDmyClk = 16 / 8,
+    .qpiPageProgramCmd = 0x02,
+    .writeVregEnableCmd = 0x50,
+
+    /* qpi mode */
+    .enterQpi = 0x38,
+    .exitQpi = 0xff,
+
+    /*AC*/
+    .timeEsector = 300,
+    .timeE32k = 1200,
+    .timeE64k = 1200,
+    .timePagePgm = 5,
+    .timeCe = 20 * 1000,
+    .pdDelay = 8,
+    .qeData = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = {
+    {
+        .jedecID = 0x1440ef,
+        .name = "Winb_80DV_08_33",
+        .cfg = &flashCfg_Winb_80DV,
+    },
+    {
+        .jedecID = 0x1540ef,
+        .name = "Winb_16DV_16_33",
+        .cfg = &flashCfg_Winb_16DV,
+    },
+    {
+        .jedecID = 0x1640ef,
+        .name = "Winb_32FV_32_33",
+        .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV,
+    },
+    {
+        .jedecID = 0x1460ef,
+        .name = "Winb_80EW_08_18",
+        .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV,
+    },
+    {
+        .jedecID = 0x1560ef,
+        .name = "Winb_16FW_16_18",
+        .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV,
+    },
+    {
+        .jedecID = 0x1660ef,
+        .name = "Winb_32FW_32_18",
+        .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV,
+    },
+    {
+        .jedecID = 0x1860ef,
+        .name = "Winb_128FW_128_18",
+        .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV,
+    },
+    {
+        .jedecID = 0x1680ef,
+        .name = "Winb_32JW_32_18",
+        .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV,
+    },
+    {
+        .jedecID = 0x13605e,
+        .name = "Zbit_04_33",
+        .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV,
+    },
+    {
+        .jedecID = 0x14605e,
+        .name = "Zbit_08_33",
+        .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV,
+    },
+    {
+        .jedecID = 0x14609d,
+        .name = "ISSI_08_33",
+        .cfg = &flashCfg_Issi,
+    },
+    {
+        .jedecID = 0x15609d,
+        .name = "ISSI_16_33",
+        .cfg = &flashCfg_Issi,
+    },
+    {
+        .jedecID = 0x16609d,
+        .name = "ISSI_32_33",
+        .cfg = &flashCfg_Issi,
+    },
+    {
+        .jedecID = 0x14709d,
+        .name = "ISSI_08_18",
+        .cfg = &flashCfg_Issi,
+    },
+    {
+        .jedecID = 0x15709d,
+        .name = "ISSI_16_18",
+        .cfg = &flashCfg_Issi,
+    },
+    {
+        .jedecID = 0x16709d,
+        .name = "ISSI_32_18",
+        .cfg = &flashCfg_Issi,
+    },
+    {
+        .jedecID = 0x134051,
+        .name = "GD_MD04D_04_33",
+        .cfg = &flashCfg_Gd_Md_40D,
+    },
+    {
+        .jedecID = 0x1440C8,
+        .name = "GD_Q08E_08_33",
+        .cfg = &flashCfg_Gd_Q80E_Q16E,
+    },
+    {
+        .jedecID = 0x1540C8,
+        .name = "GD_Q16E_16_33",
+        .cfg = &flashCfg_Gd_Q80E_Q16E,
+    },
+    {
+        .jedecID = 0x1640C8,
+        .name = "GD_Q32C_32_33",
+        .cfg = &flashCfg_Gd_Q32C,
+    },
+    {
+        .jedecID = 0x1460C8,
+        .name = "GD_LQ08C_08_18",
+        .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E,
+    },
+    {
+        .jedecID = 0x1560C8,
+        .name = "GD_LE16C_16_18",
+        .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E,
+    },
+    {
+        .jedecID = 0x1660C8,
+        .name = "GD_LQ32D_32_18",
+        .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E,
+    },
+    {
+        .jedecID = 0x1465C8,
+        .name = "GD_WQ80E_80_33",
+        .cfg = &flashCfg_Gd_WQ80E_WQ16E,
+    },
+    {
+        .jedecID = 0x1565C8,
+        .name = "GD_WQ16E_16_33",
+        .cfg = &flashCfg_Gd_WQ80E_WQ16E,
+    },
+    {
+        .jedecID = 0x1665C8,
+        .name = "GD_WQ32E_32_33",
+        .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E,
+    },
+    {
+        .jedecID = 0x3425C2,
+        .name = "MX_25V80_08_18",
+        .cfg = &flashCfg_Mxic,
+    },
+    {
+        .jedecID = 0x3525C2,
+        .name = "MX_25U16_35_18",
+        .cfg = &flashCfg_Mxic_1635F,
+    },
+    {
+        .jedecID = 0x3625C2,
+        .name = "MX_25V32_32_18",
+        .cfg = &flashCfg_Mxic,
+    },
+    {
+        .jedecID = 0x13400B,
+        .name = "XT_25F04D_04_33",
+        .cfg = &flashCfg_Xtx40,
+    },
+    {
+        .jedecID = 0x15400B,
+        .name = "XT_25F16B_16_33",
+        .cfg = &flashCfg_Xtx,
+    },
+    {
+        .jedecID = 0x16400B,
+        .name = "XT_25F32B_32_33",
+        .cfg = &flashCfg_Xtx,
+    },
+    {
+        .jedecID = 0x14600B,
+        .name = "XT_25Q80B_08_18",
+        .cfg = &flashCfg_Xtx,
+    },
+    {
+        .jedecID = 0x16600B,
+        .name = "XT_25Q32B_32_18",
+        .cfg = &flashCfg_Xtx,
+    },
+    {
+        .jedecID = 0x146085,
+        .name = "Puya_Q80L/H_08_18/33",
+        .cfg = &flashCfg_Puya_Q80L_Q80H_Q16H,
+    },
+    {
+        .jedecID = 0x156085,
+        .name = "Puya_Q16H_16_33",
+        .cfg = &flashCfg_Puya_Q80L_Q80H_Q16H,
+    },
+    {
+        .jedecID = 0x166085,
+        .name = "Puya_Q32H_32_33",
+        .cfg = &flashCfg_Puya_Q32H,
+    },
+    {
+        .jedecID = 0x134068,
+        .name = "Boya_Q04B_04_33",
+        .cfg = &flashCfg_Boya40,
+    },
+    {
+        .jedecID = 0x144068,
+        .name = "Boya_Q08B_08_33",
+        .cfg = &flashCfg_Boya,
+    },
+    {
+        .jedecID = 0x154068,
+        .name = "Boya_Q16B_16_33",
+        .cfg = &flashCfg_Boya,
+    },
+    {
+        .jedecID = 0x164068,
+        .name = "Boya_Q32B_32_33",
+        .cfg = &flashCfg_Boya,
+    },
+    {
+        .jedecID = 0x174068,
+        .name = "Boya_Q64A_64_33",
+        .cfg = &flashCfg_Boya,
+    },
+    {
+        .jedecID = 0x184068,
+        .name = "Boya_Q128A_128_33",
+        .cfg = &flashCfg_Boya,
+    },
+    {
+        .jedecID = 0x14605E,
+        .name = "FT_VQ80",
+        .cfg = &flashCfg_FT_VQ80,
+    }
+};
+#endif
+
+/*@} end of group SF_CFG_Private_Variables */
+
+/** @defgroup  SF_CFG_Global_Variables
+ *  @{
+ */
+
+/*@} end of group SF_CFG_Global_Variables */
+
+/** @defgroup  SF_CFG_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group SF_CFG_Private_Fun_Declaration */
+
+/** @defgroup  SF_CFG_Private_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Init external flash GPIO according to flash GPIO config
+ *
+ * @param  extFlashPin: Flash GPIO config
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+/* static */ void ATTR_TCM_SECTION SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin)
+{
+    GLB_GPIO_Cfg_Type cfg;
+    uint8_t gpiopins[6];
+    uint8_t i = 0;
+
+    cfg.gpioMode = GPIO_MODE_AF;
+    cfg.pullType = GPIO_PULL_UP;
+    cfg.drive = 1;
+    cfg.smtCtrl = 1;
+    cfg.gpioFun = GPIO_FUN_FLASH_PSRAM;
+
+    if (extFlashPin == 0) {
+        gpiopins[0] = BFLB_EXTFLASH_CLK0_GPIO;
+        gpiopins[1] = BFLB_EXTFLASH_CS0_GPIO;
+        gpiopins[2] = BFLB_EXTFLASH_DATA00_GPIO;
+        gpiopins[3] = BFLB_EXTFLASH_DATA10_GPIO;
+        gpiopins[4] = BFLB_EXTFLASH_DATA20_GPIO;
+        gpiopins[5] = BFLB_EXTFLASH_DATA30_GPIO;
+    } else if (extFlashPin == 1) {
+        gpiopins[0] = BFLB_EXTFLASH_CLK1_GPIO;
+        gpiopins[1] = BFLB_EXTFLASH_CS1_GPIO;
+        gpiopins[2] = BFLB_EXTFLASH_DATA01_GPIO;
+        gpiopins[3] = BFLB_EXTFLASH_DATA11_GPIO;
+        gpiopins[4] = BFLB_EXTFLASH_DATA21_GPIO;
+        gpiopins[5] = BFLB_EXTFLASH_DATA31_GPIO;
+    } else {
+        gpiopins[0] = BFLB_EXTFLASH_CLK2_GPIO;
+        gpiopins[1] = BFLB_EXTFLASH_CS2_GPIO;
+        gpiopins[2] = BFLB_EXTFLASH_DATA02_GPIO;
+        gpiopins[3] = BFLB_EXTFLASH_DATA12_GPIO;
+        gpiopins[4] = BFLB_EXTFLASH_DATA22_GPIO;
+        gpiopins[5] = BFLB_EXTFLASH_DATA32_GPIO;
+    }
+
+    for (i = 0; i < sizeof(gpiopins); i++) {
+        cfg.gpioPin = gpiopins[i];
+
+        if (i == 0 || i == 1) {
+            /*flash clk and cs is output*/
+            cfg.gpioMode = GPIO_MODE_OUTPUT;
+        } else {
+            /*data are bidir*/
+            cfg.gpioMode = GPIO_MODE_AF;
+        }
+
+        GLB_GPIO_Init(&cfg);
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Deinit external flash GPIO according to flash GPIO config
+ *
+ * @param  extFlashPin: Flash GPIO config
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+/* static */ void ATTR_TCM_SECTION SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin)
+{
+    GLB_GPIO_Cfg_Type cfg;
+    uint8_t gpiopins[6];
+    uint8_t i = 0;
+
+    cfg.gpioMode = GPIO_MODE_INPUT;
+    cfg.pullType = GPIO_PULL_UP;
+    cfg.drive = 1;
+    cfg.smtCtrl = 1;
+    cfg.gpioFun = GPIO_FUN_GPIO;
+
+    if (extFlashPin == 0) {
+        gpiopins[0] = BFLB_EXTFLASH_CLK0_GPIO;
+        gpiopins[1] = BFLB_EXTFLASH_CS0_GPIO;
+        gpiopins[2] = BFLB_EXTFLASH_DATA00_GPIO;
+        gpiopins[3] = BFLB_EXTFLASH_DATA10_GPIO;
+        gpiopins[4] = BFLB_EXTFLASH_DATA20_GPIO;
+        gpiopins[5] = BFLB_EXTFLASH_DATA30_GPIO;
+
+    } else if (extFlashPin == 1) {
+        gpiopins[0] = BFLB_EXTFLASH_CLK1_GPIO;
+        gpiopins[1] = BFLB_EXTFLASH_CS1_GPIO;
+        gpiopins[2] = BFLB_EXTFLASH_DATA01_GPIO;
+        gpiopins[3] = BFLB_EXTFLASH_DATA11_GPIO;
+        gpiopins[4] = BFLB_EXTFLASH_DATA21_GPIO;
+        gpiopins[5] = BFLB_EXTFLASH_DATA31_GPIO;
+    } else {
+        gpiopins[0] = BFLB_EXTFLASH_CLK2_GPIO;
+        gpiopins[1] = BFLB_EXTFLASH_CS2_GPIO;
+        gpiopins[2] = BFLB_EXTFLASH_DATA02_GPIO;
+        gpiopins[3] = BFLB_EXTFLASH_DATA12_GPIO;
+        gpiopins[4] = BFLB_EXTFLASH_DATA22_GPIO;
+        gpiopins[5] = BFLB_EXTFLASH_DATA32_GPIO;
+    }
+
+    for (i = 0; i < sizeof(gpiopins); i++) {
+        cfg.gpioPin = gpiopins[i];
+        GLB_GPIO_Init(&cfg);
+    }
+}
+#endif
+
+/*@} end of group SF_CFG_Private_Functions */
+
+/** @defgroup  SF_CFG_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Get flash config according to flash ID
+ *
+ * @param  flashID: Flash ID
+ * @param  pFlashCfg: Flash config pointer
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg)
+{
+    uint32_t i;
+    uint8_t buf[sizeof(SPI_Flash_Cfg_Type) + 8];
+    uint32_t crc, *pCrc;
+    uint32_t xipOffset;
+
+    if (flashID == 0) {
+        xipOffset = SF_Ctrl_Get_Flash_Image_Offset();
+        SF_Ctrl_Set_Flash_Image_Offset(0);
+        XIP_SFlash_Read_Via_Cache_Need_Lock(8 + BL702_FLASH_XIP_BASE, buf, sizeof(SPI_Flash_Cfg_Type) + 8);
+        SF_Ctrl_Set_Flash_Image_Offset(xipOffset);
+
+        if (BL702_MemCmp(buf, BFLB_FLASH_CFG_MAGIC, 4) == 0) {
+            crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type));
+            pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type));
+
+            if (*pCrc == crc) {
+                BL702_MemCpy_Fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type));
+                return SUCCESS;
+            }
+        }
+    } else {
+        for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) {
+            if (flashInfos[i].jedecID == flashID) {
+                BL702_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));
+                return SUCCESS;
+            }
+        }
+    }
+
+    return ERROR;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Init flash GPIO according to flash Pin config
+ *
+ * @param  flashPinCfg: Specify flash Pin config
+ * @param  restoreDefault: Wether to restore default setting
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg, uint8_t restoreDefault)
+{
+    uint8_t flashCfg;
+    uint8_t swapCfg;
+    uint32_t tmpVal;
+
+    flashCfg = (flashPinCfg >> 2) & 0x03;
+    swapCfg = flashPinCfg & 0x03;
+
+    if (restoreDefault) {
+        /* Set Default first */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO);
+
+        if (BL_GET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO) == 0x00) {
+            SF_Cfg_Init_Ext_Flash_Gpio(1);
+        }
+
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3);
+        BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+        SF_Ctrl_Select_Pad(SF_CTRL_PAD_SEL_SF2);
+
+        /* Default is set, so return */
+        if (flashCfg == BFLB_FLASH_CFG_SF2_EXT_23_28 && swapCfg == BFLB_SF2_SWAP_NONE) {
+            return;
+        }
+    }
+
+    if (flashCfg == BFLB_FLASH_CFG_SF1_EXT_17_22) {
+        SF_Cfg_Init_Ext_Flash_Gpio(0);
+        SF_Ctrl_Select_Pad(SF_CTRL_PAD_SEL_SF1);
+    } else {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO);
+
+        if (BL_GET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO) == 0x00) {
+            SF_Cfg_Init_Ext_Flash_Gpio(1);
+        }
+
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+
+        if (swapCfg == BFLB_SF2_SWAP_NONE) {
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3);
+        } else if (swapCfg == BFLB_SF2_SWAP_CS_IO2) {
+            tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3);
+        } else if (swapCfg == BFLB_SF2_SWAP_IO0_IO3) {
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2);
+            tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3);
+        } else {
+            tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2);
+            tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3);
+        }
+
+        BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+        SF_Ctrl_Select_Pad(SF_CTRL_PAD_SEL_SF2);
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Identify one flash
+ *
+ * @param  callFromFlash: code run at flash or ram
+ * @param  autoScan: Auto scan all GPIO pin
+ * @param  flashPinCfg: Specify flash GPIO config, not auto scan
+ * @param  restoreDefault: Wether restore default flash GPIO config
+ * @param  pFlashCfg: Flash config pointer
+ *
+ * @return Flash ID
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify(uint8_t callFromFlash,
+                                                uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg)
+{
+    uint32_t jdecId = 0;
+    uint32_t i = 0;
+    uint32_t offset;
+    BL_Err_Type stat;
+
+    BL702_MemCpy_Fast(pFlashCfg, &flashCfg_Gd_Q80E_Q16E, sizeof(SPI_Flash_Cfg_Type));
+
+    if (callFromFlash == 1) {
+        stat = XIP_SFlash_State_Save(pFlashCfg, &offset);
+
+        if (stat != SUCCESS) {
+            SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB);
+            return 0;
+        }
+    }
+
+    if (autoScan) {
+        flashPinCfg = 0;
+
+        do {
+            if (flashPinCfg > 0x0f) {
+                jdecId = 0;
+                break;
+            }
+
+            SF_Cfg_Init_Flash_Gpio(flashPinCfg, restoreDefault);
+            SFlash_Releae_Powerdown(pFlashCfg);
+            SFlash_Reset_Continue_Read(pFlashCfg);
+            SFlash_DisableBurstWrap(pFlashCfg);
+            jdecId = 0;
+            SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId);
+            SFlash_DisableBurstWrap(pFlashCfg);
+            jdecId = jdecId & 0xffffff;
+            flashPinCfg++;
+        } while ((jdecId & 0x00ffff) == 0 || (jdecId & 0xffff00) == 0 || (jdecId & 0x00ffff) == 0xffff || (jdecId & 0xffff00) == 0xffff00);
+    } else {
+        /* select media gpio */
+        SF_Cfg_Init_Flash_Gpio(flashPinCfg, restoreDefault);
+        SFlash_Releae_Powerdown(pFlashCfg);
+        SFlash_Reset_Continue_Read(pFlashCfg);
+        SFlash_DisableBurstWrap(pFlashCfg);
+        SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId);
+        SFlash_DisableBurstWrap(pFlashCfg);
+        jdecId = jdecId & 0xffffff;
+    }
+
+    for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) {
+        if (flashInfos[i].jedecID == jdecId) {
+            BL702_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));
+            break;
+        }
+    }
+
+    if (i == sizeof(flashInfos) / sizeof(flashInfos[0])) {
+        if (callFromFlash == 1) {
+            XIP_SFlash_State_Restore(pFlashCfg, pFlashCfg->ioMode, offset);
+        }
+
+        return jdecId;
+    } else {
+        if (callFromFlash == 1) {
+            XIP_SFlash_State_Restore(pFlashCfg, pFlashCfg->ioMode, offset);
+        }
+
+        return (jdecId | BFLB_FLASH_ID_VALID_FLAG);
+    }
+}
+#endif
+
+/*@} end of group SF_CFG_Public_Functions */
+
+/*@} end of group SF_CFG */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sf_cfg_ext.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sf_cfg_ext.c
new file mode 100644
index 00000000..d90928c8
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sf_cfg_ext.c
@@ -0,0 +1,705 @@
+/**
+  ******************************************************************************
+  * @file    bl702_sf_cfg_ext.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_glb.h"
+#include "bl702_sf_cfg.h"
+#include "bl702_sf_cfg_ext.h"
+#include "bl702_xip_sflash.h"
+#include "bl702_romdriver.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SF_CFG_EXT
+ *  @{
+ */
+
+/** @defgroup  SF_CFG_EXT_Private_Macros
+ *  @{
+ */
+#define BFLB_FLASH_CFG_MAGIC "FCFG"
+
+/*@} end of group SF_CFG_EXT_Private_Macros */
+
+/** @defgroup  SF_CFG_EXT_Private_Types
+ *  @{
+ */
+typedef struct
+{
+    uint32_t jedecID;
+    char *name;
+    const SPI_Flash_Cfg_Type *cfg;
+} Flash_Info_t;
+
+/*@} end of group SF_CFG_EXT_Private_Types */
+
+/** @defgroup  SF_CFG_EXT_Private_Variables
+ *  @{
+ */
+
+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Md_40D={
+    .resetCreadCmd = 0xff,
+    .resetCreadCmdSize = 3,
+    .mid = 0x51,
+
+    .deBurstWrapCmd = 0x77,
+    .deBurstWrapCmdDmyClk = 0x3,
+    .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .deBurstWrapData = 0xF0,
+
+    /*reg*/
+    .writeEnableCmd = 0x06,
+    .wrEnableIndex = 0x00,
+    .wrEnableBit = 0x01,
+    .wrEnableReadRegLen = 0x01,
+
+    .qeIndex = 1,
+    .qeBit = 0x01,
+    .qeWriteRegLen = 0x02,
+    .qeReadRegLen = 0x1,
+
+    .busyIndex = 0,
+    .busyBit = 0x00,
+    .busyReadRegLen = 0x1,
+    .releasePowerDown = 0xab,
+
+    .readRegCmd[0] = 0x05,
+    .readRegCmd[1] = 0x35,
+    .writeRegCmd[0] = 0x01,
+    .writeRegCmd[1] = 0x01,
+
+    .fastReadQioCmd = 0xeb,
+    .frQioDmyClk = 16/8,
+    .cReadSupport = 0,
+    .cReadMode = 0xA0,
+
+    .burstWrapCmd = 0x77,
+    .burstWrapCmdDmyClk = 0x3,
+    .burstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .burstWrapData = 0x40,
+     /*erase*/
+    .chipEraseCmd = 0xc7,
+    .sectorEraseCmd = 0x20,
+    .blk32EraseCmd = 0x52,
+    .blk64EraseCmd = 0xd8,
+    /*write*/
+    .pageProgramCmd = 0x02,
+    .qpageProgramCmd = 0x32,
+    .qppAddrMode = SF_CTRL_ADDR_1_LINE,
+
+    .ioMode = 0x11,
+    .clkDelay = 1,
+    .clkInvert = 0x3f,
+
+    .resetEnCmd = 0x66,
+    .resetCmd = 0x99,
+    .cRExit = 0xff,
+    .wrEnableWriteRegLen = 0x00,
+
+    /*id*/
+    .jedecIdCmd = 0x9f,
+    .jedecIdCmdDmyClk = 0,
+    .qpiJedecIdCmd = 0x9f,
+    .qpiJedecIdCmdDmyClk = 0x00,
+    .sectorSize = 4,
+    .pageSize = 256,
+
+    /*read*/
+    .fastReadCmd = 0x0b,
+    .frDmyClk = 8/8,
+    .qpiFastReadCmd = 0x0b,
+    .qpiFrDmyClk = 8/8,
+    .fastReadDoCmd = 0x3b,
+    .frDoDmyClk = 8/8,
+    .fastReadDioCmd = 0xbb,
+    .frDioDmyClk = 0,
+    .fastReadQoCmd = 0x6b,
+    .frQoDmyClk = 8/8,
+
+    .qpiFastReadQioCmd = 0xeb,
+    .qpiFrQioDmyClk = 16/8,
+    .qpiPageProgramCmd = 0x02,
+    .writeVregEnableCmd = 0x50,
+
+    /* qpi mode */
+    .enterQpi = 0x38,
+    .exitQpi = 0xff,
+
+     /*AC*/
+    .timeEsector = 300,
+    .timeE32k = 1200,
+    .timeE64k = 1200,
+    .timePagePgm = 5,
+    .timeCe = 20*1000,
+    .pdDelay = 20,
+    .qeData = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_MX_KH25 = {
+    .resetCreadCmd = 0xff,
+    .resetCreadCmdSize = 3,
+    .mid = 0xc2,
+
+    .deBurstWrapCmd = 0x77,
+    .deBurstWrapCmdDmyClk = 0x3,
+    .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .deBurstWrapData = 0xF0,
+
+    /*reg*/
+    .writeEnableCmd = 0x06,
+    .wrEnableIndex = 0x00,
+    .wrEnableBit = 0x01,
+    .wrEnableReadRegLen = 0x01,
+
+    .qeIndex = 1,
+    .qeBit = 0x01,
+    .qeWriteRegLen = 0x01,
+    .qeReadRegLen = 0x1,
+
+    .busyIndex = 0,
+    .busyBit = 0x00,
+    .busyReadRegLen = 0x1,
+    .releasePowerDown = 0xab,
+
+    .readRegCmd[0] = 0x05,
+    .readRegCmd[1] = 0x00,
+    .writeRegCmd[0] = 0x01,
+    .writeRegCmd[1] = 0x00,
+
+    .fastReadQioCmd = 0xeb,
+    .frQioDmyClk = 16 / 8,
+    .cReadSupport = 0,
+    .cReadMode = 0x20,
+
+    .burstWrapCmd = 0x77,
+    .burstWrapCmdDmyClk = 0x3,
+    .burstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .burstWrapData = 0x40,
+    /*erase*/
+    .chipEraseCmd = 0xc7,
+    .sectorEraseCmd = 0x20,
+    .blk32EraseCmd = 0x52,
+    .blk64EraseCmd = 0xd8,
+    /*write*/
+    .pageProgramCmd = 0x02,
+    .qpageProgramCmd = 0x32,
+    .qppAddrMode = SF_CTRL_ADDR_1_LINE,
+
+    .ioMode = 0x11,
+    .clkDelay = 1,
+    .clkInvert = 0x01,
+
+    .resetEnCmd = 0x66,
+    .resetCmd = 0x99,
+    .cRExit = 0xff,
+    .wrEnableWriteRegLen = 0x00,
+
+    /*id*/
+    .jedecIdCmd = 0x9f,
+    .jedecIdCmdDmyClk = 0,
+    .qpiJedecIdCmd = 0x9f,
+    .qpiJedecIdCmdDmyClk = 0x00,
+    .sectorSize = 4,
+    .pageSize = 256,
+
+    /*read*/
+    .fastReadCmd = 0x0b,
+    .frDmyClk = 8 / 8,
+    .qpiFastReadCmd = 0x0b,
+    .qpiFrDmyClk = 8 / 8,
+    .fastReadDoCmd = 0x3b,
+    .frDoDmyClk = 8 / 8,
+    .fastReadDioCmd = 0xbb,
+    .frDioDmyClk = 0,
+    .fastReadQoCmd = 0x6b,
+    .frQoDmyClk = 8 / 8,
+
+    .qpiFastReadQioCmd = 0xeb,
+    .qpiFrQioDmyClk = 16 / 8,
+    .qpiPageProgramCmd = 0x02,
+    .writeVregEnableCmd = 0x50,
+
+    /* qpi mode */
+    .enterQpi = 0x38,
+    .exitQpi = 0xff,
+
+    /*AC*/
+    .timeEsector = 300,
+    .timeE32k = 1200,
+    .timeE64k = 1200,
+    .timePagePgm = 5,
+    .timeCe = 33000,
+    .pdDelay = 20,
+    .qeData = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_FM_Q80 = {
+    .resetCreadCmd = 0xff,
+    .resetCreadCmdSize = 3,
+    .mid = 0xc8,
+
+    .deBurstWrapCmd = 0x77,
+    .deBurstWrapCmdDmyClk = 0x3,
+    .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .deBurstWrapData = 0xF0,
+
+    /*reg*/
+    .writeEnableCmd = 0x06,
+    .wrEnableIndex = 0x00,
+    .wrEnableBit = 0x01,
+    .wrEnableReadRegLen = 0x01,
+
+    .qeIndex = 1,
+    .qeBit = 0x01,
+    .qeWriteRegLen = 0x02,
+    .qeReadRegLen = 0x1,
+
+    .busyIndex = 0,
+    .busyBit = 0x00,
+    .busyReadRegLen = 0x1,
+    .releasePowerDown = 0xab,
+
+    .readRegCmd[0] = 0x05,
+    .readRegCmd[1] = 0x35,
+    .writeRegCmd[0] = 0x01,
+    .writeRegCmd[1] = 0x01,
+
+    .fastReadQioCmd = 0xeb,
+    .frQioDmyClk = 16 / 8,
+    .cReadSupport = 1,
+    .cReadMode = 0xA0,
+
+    .burstWrapCmd = 0x77,
+    .burstWrapCmdDmyClk = 0x3,
+    .burstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .burstWrapData = 0x40,
+    /*erase*/
+    .chipEraseCmd = 0xc7,
+    .sectorEraseCmd = 0x20,
+    .blk32EraseCmd = 0x52,
+    .blk64EraseCmd = 0xd8,
+    /*write*/
+    .pageProgramCmd = 0x02,
+    .qpageProgramCmd = 0x32,
+    .qppAddrMode = SF_CTRL_ADDR_1_LINE,
+
+    .ioMode = SF_CTRL_QIO_MODE,
+    .clkDelay = 1,
+    .clkInvert = 0x01,
+
+    .resetEnCmd = 0x66,
+    .resetCmd = 0x99,
+    .cRExit = 0xff,
+    .wrEnableWriteRegLen = 0x00,
+
+    /*id*/
+    .jedecIdCmd = 0x9f,
+    .jedecIdCmdDmyClk = 0,
+    .qpiJedecIdCmd = 0x9f,
+    .qpiJedecIdCmdDmyClk = 0x00,
+    .sectorSize = 4,
+    .pageSize = 256,
+
+    /*read*/
+    .fastReadCmd = 0x0b,
+    .frDmyClk = 8 / 8,
+    .qpiFastReadCmd = 0x0b,
+    .qpiFrDmyClk = 8 / 8,
+    .fastReadDoCmd = 0x3b,
+    .frDoDmyClk = 8 / 8,
+    .fastReadDioCmd = 0xbb,
+    .frDioDmyClk = 0,
+    .fastReadQoCmd = 0x6b,
+    .frQoDmyClk = 8 / 8,
+
+    .qpiFastReadQioCmd = 0xeb,
+    .qpiFrQioDmyClk = 16 / 8,
+    .qpiPageProgramCmd = 0x02,
+    .writeVregEnableCmd = 0x50,
+
+    /* qpi mode */
+    .enterQpi = 0x38,
+    .exitQpi = 0xff,
+
+    /*AC*/
+    .timeEsector = 300,
+    .timeE32k = 1200,
+    .timeE64k = 1200,
+    .timePagePgm = 5,
+    .timeCe = 33000,
+    .pdDelay = 20,
+    .qeData = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_16JV = {
+    .resetCreadCmd = 0xff,
+    .resetCreadCmdSize = 3,
+    .mid = 0xef,
+
+    .deBurstWrapCmd = 0x77,
+    .deBurstWrapCmdDmyClk = 0x3,
+    .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .deBurstWrapData = 0xF0,
+
+    /*reg*/
+    .writeEnableCmd = 0x06,
+    .wrEnableIndex = 0x00,
+    .wrEnableBit = 0x01,
+    .wrEnableReadRegLen = 0x01,
+
+    .qeIndex = 1,
+    .qeBit = 0x01,
+    .qeWriteRegLen = 0x01,
+    .qeReadRegLen = 0x1,
+
+    .busyIndex = 0,
+    .busyBit = 0x00,
+    .busyReadRegLen = 0x1,
+    .releasePowerDown = 0xab,
+
+    .readRegCmd[0] = 0x05,
+    .readRegCmd[1] = 0x35,
+    .writeRegCmd[0] = 0x01,
+    .writeRegCmd[1] = 0x31,
+
+    .fastReadQioCmd = 0xeb,
+    .frQioDmyClk = 16 / 8,
+    .cReadSupport = 1,
+    .cReadMode = 0x20,
+
+    .burstWrapCmd = 0x77,
+    .burstWrapCmdDmyClk = 0x3,
+    .burstWrapDataMode = SF_CTRL_DATA_4_LINES,
+    .burstWrapData = 0x40,
+    /*erase*/
+    .chipEraseCmd = 0xc7,
+    .sectorEraseCmd = 0x20,
+    .blk32EraseCmd = 0x52,
+    .blk64EraseCmd = 0xd8,
+    /*write*/
+    .pageProgramCmd = 0x02,
+    .qpageProgramCmd = 0x32,
+    .qppAddrMode = SF_CTRL_ADDR_1_LINE,
+
+    .ioMode = SF_CTRL_QIO_MODE,
+    .clkDelay = 1,
+    .clkInvert = 0x01,
+
+    .resetEnCmd = 0x66,
+    .resetCmd = 0x99,
+    .cRExit = 0xff,
+    .wrEnableWriteRegLen = 0x00,
+
+    /*id*/
+    .jedecIdCmd = 0x9f,
+    .jedecIdCmdDmyClk = 0,
+    .qpiJedecIdCmd = 0x9f,
+    .qpiJedecIdCmdDmyClk = 0x00,
+    .sectorSize = 4,
+    .pageSize = 256,
+
+    /*read*/
+    .fastReadCmd = 0x0b,
+    .frDmyClk = 8 / 8,
+    .qpiFastReadCmd = 0x0b,
+    .qpiFrDmyClk = 8 / 8,
+    .fastReadDoCmd = 0x3b,
+    .frDoDmyClk = 8 / 8,
+    .fastReadDioCmd = 0xbb,
+    .frDioDmyClk = 0,
+    .fastReadQoCmd = 0x6b,
+    .frQoDmyClk = 8 / 8,
+
+    .qpiFastReadQioCmd = 0xeb,
+    .qpiFrQioDmyClk = 16 / 8,
+    .qpiPageProgramCmd = 0x02,
+    .writeVregEnableCmd = 0x50,
+
+    /* qpi mode */
+    .enterQpi = 0x38,
+    .exitQpi = 0xff,
+
+    /*AC*/
+    .timeEsector = 400,
+    .timeE32k = 1600,
+    .timeE64k = 2000,
+    .timePagePgm = 5,
+    .timeCe = 33000,
+    .pdDelay = 3,
+    .qeData = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = {
+    {
+        .jedecID = 0x134051,
+        .name = "GD_MD04D_04_33",
+        .cfg = &flashCfg_Gd_Md_40D,
+    },
+    {
+        .jedecID = 0x1320c2,
+        .name = "MX_KH40_04_33",
+        .cfg = &flashCfg_MX_KH25,
+    },
+    {
+        .jedecID = 0x1420c2,
+        .name = "MX_KH80_08_33",
+        .cfg = &flashCfg_MX_KH25,
+    },
+    {
+        .jedecID = 0x1520c2,
+        .name = "MX_KH16_16_33",
+        .cfg = &flashCfg_MX_KH25,
+    },
+    {
+        .jedecID = 0x1440A1,
+        .name = "FM_25Q80_80_33",
+        .cfg = &flashCfg_FM_Q80,
+    },
+    {
+        .jedecID = 0x1570EF,
+        .name = "Winb_16JV_16_33",
+        .cfg = &flashCfg_Winb_16JV,
+    },
+    {
+        .jedecID = 0x1870EF,
+        .name = "Winb_128JV_128_33",
+        .cfg = &flashCfg_Winb_16JV,
+    },
+    {
+        .jedecID = 0x15605E,
+        .name = "ZB_VQ16_16_33",
+        .cfg = &flashCfg_Winb_16JV,
+    },
+    {
+        .jedecID = 0x144020,
+        .name = "XM_25QH80_80_33",
+        .cfg = &flashCfg_Winb_16JV,
+    },
+    {
+        .jedecID = 0x154020,
+        .name = "XM_25QH16_16_33",
+        .cfg = &flashCfg_Winb_16JV,
+    },
+    {
+        .jedecID = 0x164020,
+        .name = "XM_25QH32_32_33",
+        .cfg = &flashCfg_Winb_16JV,
+    },
+    {
+        .jedecID = 0x174020,
+        .name = "XM_25QH64_64_33",
+        .cfg = &flashCfg_Winb_16JV,
+    },
+    {
+        .jedecID = 0x13325E,
+        .name = "ZB_D40B_80_33",
+        .cfg = &flashCfg_MX_KH25,
+    },
+    {
+        .jedecID = 0x14325E,
+        .name = "ZB_D80B_80_33",
+        .cfg = &flashCfg_MX_KH25,
+    },
+    {
+        .jedecID = 0x15405E,
+        .name = "ZB_25Q16B_15_33",
+        .cfg = &flashCfg_Winb_16JV,
+    },
+    {
+        .jedecID = 0x16405E,
+        .name = "ZB_25Q32B_16_33",
+        .cfg = &flashCfg_Winb_16JV,
+    },
+    {
+        .jedecID = 0x1560EB,
+        .name = "TH_25Q16HB_16_33",
+        .cfg = &flashCfg_FM_Q80,
+    },
+    {
+        .jedecID = 0x15345E,
+        .name = "ZB_25Q16A_15_33",
+        .cfg = &flashCfg_Winb_16JV,
+    },
+};
+
+/*@} end of group SF_CFG_EXT_Private_Variables */
+
+/** @defgroup  SF_CFG_EXT_Global_Variables
+ *  @{
+ */
+
+/*@} end of group SF_CFG_EXT_Global_Variables */
+
+/** @defgroup  SF_CFG_EXT_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group SF_CFG_EXT_Private_Fun_Declaration */
+
+/** @defgroup  SF_CFG_EXT_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Init internal flash GPIO
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION SF_Cfg_Init_Internal_Flash_Gpio(void)
+{
+    GLB_GPIO_Cfg_Type gpioCfg = {
+        .gpioPin = GLB_GPIO_PIN_0,
+        .gpioFun = GPIO_FUN_GPIO,
+        .gpioMode = GPIO_MODE_INPUT,
+        .pullType = GPIO_PULL_NONE,
+        .drive = 0,
+        .smtCtrl = 1,
+    };
+
+    /* Turn on Flash pad, GPIO23 - GPIO28 */
+    for (uint32_t pin = 23; pin < 29; pin++) {
+        gpioCfg.gpioPin = pin;
+
+        if (pin == 25) {
+            gpioCfg.pullType = GPIO_PULL_DOWN;
+        } else {
+            gpioCfg.pullType = GPIO_PULL_NONE;
+        }
+
+        GLB_GPIO_Init(&gpioCfg);
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Get flash config according to flash ID
+ *
+ * @param  flashID: Flash ID
+ * @param  pFlashCfg: Flash config pointer
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg)
+{
+    uint32_t i;
+    uint8_t buf[sizeof(SPI_Flash_Cfg_Type) + 8];
+    uint32_t crc, *pCrc;
+    char flashCfgMagic[] = "FCFG";
+
+    if (flashID == 0) {
+        XIP_SFlash_Read_Via_Cache_Need_Lock(8 + BL702_FLASH_XIP_BASE, buf, sizeof(SPI_Flash_Cfg_Type) + 8);
+
+        if (BL702_MemCmp(buf, flashCfgMagic, 4) == 0) {
+            crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type));
+            pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type));
+
+            if (*pCrc == crc) {
+                BL702_MemCpy_Fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type));
+                return SUCCESS;
+            }
+        }
+    } else {
+        if (SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg) == SUCCESS) {
+            /* 0x134051 flash cfg is wrong in rom, find again */
+            if ((flashID&0xFFFFFF) != 0x134051) {
+                return SUCCESS;
+            }
+        }
+
+        for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) {
+            if (flashInfos[i].jedecID == flashID) {
+                BL702_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));
+                return SUCCESS;
+            }
+        }
+    }
+
+    return ERROR;
+}
+
+/****************************************************************************/ /**
+ * @brief  Identify one flash
+ *
+ * @param  callFromFlash: code run at flash or ram
+ * @param  autoScan: Auto scan all GPIO pin
+ * @param  flashPinCfg: Specify flash GPIO config, not auto scan
+ * @param  restoreDefault: Wether restore default flash GPIO config
+ * @param  pFlashCfg: Flash config pointer
+ *
+ * @return Flash ID
+ *
+*******************************************************************************/
+uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash,
+                                                    uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg)
+{
+    uint32_t jdecId = 0;
+    uint32_t i = 0;
+    uint32_t ret = 0;
+
+    ret = SF_Cfg_Flash_Identify(callFromFlash, autoScan, flashPinCfg, restoreDefault, pFlashCfg);
+
+    if ((ret & BFLB_FLASH_ID_VALID_FLAG) != 0) {
+        /* 0x134051 flash cfg is wrong in rom, find again */
+        if ((ret&0xFFFFFF) != 0x134051) {
+            return ret;
+        }
+    }
+
+    jdecId = (ret & 0xffffff);
+
+    for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) {
+        if (flashInfos[i].jedecID == jdecId) {
+            BL702_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));
+            break;
+        }
+    }
+
+    if (i == sizeof(flashInfos) / sizeof(flashInfos[0])) {
+        return jdecId;
+    } else {
+        return (jdecId | BFLB_FLASH_ID_VALID_FLAG);
+    }
+}
+
+/*@} end of group SF_CFG_EXT_Public_Functions */
+
+/*@} end of group SF_CFG_EXT */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sf_ctrl.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sf_ctrl.c
new file mode 100644
index 00000000..a67e0e98
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sf_ctrl.c
@@ -0,0 +1,1449 @@
+/**
+  ******************************************************************************
+  * @file    bl702_sf_ctrl.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_sf_ctrl.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SF_CTRL
+ *  @{
+ */
+
+/** @defgroup  SF_CTRL_Private_Macros
+ *  @{
+ */
+
+/*@} end of group SF_CTRL_Private_Macros */
+
+/** @defgroup  SF_CTRL_Private_Types
+ *  @{
+ */
+
+/*@} end of group SF_CTRL_Private_Types */
+
+/** @defgroup  SF_CTRL_Private_Variables
+ *  @{
+ */
+#define SF_CTRL_BUSY_STATE_TIMEOUT      (5 * 160 * 1000)
+#define SF_Ctrl_Get_AES_Region(addr, r) (addr + SF_CTRL_AES_REGION_OFFSET + (r)*0x100)
+
+/*@} end of group SF_CTRL_Private_Variables */
+
+/** @defgroup  SF_CTRL_Global_Variables
+ *  @{
+ */
+
+/*@} end of group SF_CTRL_Global_Variables */
+
+/** @defgroup  SF_CTRL_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group SF_CTRL_Private_Fun_Declaration */
+
+/** @defgroup  SF_CTRL_Private_Functions
+ *  @{
+ */
+
+/*@} end of group SF_CTRL_Private_Functions */
+
+/** @defgroup  SF_CTRL_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Enable serail flash controller
+ *
+ * @param  cfg: serial flash controller config
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg)
+{
+    uint32_t tmpVal = 0;
+    uint32_t timeOut = 0;
+
+    if (cfg == NULL) {
+        return;
+    }
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SF_CTRL_OWNER_TYPE(cfg->owner));
+
+    timeOut = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+    while (SET == SF_Ctrl_GetBusyState()) {
+        timeOut--;
+
+        if (timeOut == 0) {
+            return;
+        }
+    }
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0);
+
+    if (cfg->clkDelay > 0) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N, cfg->clkDelay - 1);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN);
+    }
+
+    /* Serail out inverted, so sf ctrl send on negative edge */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_OUT_INV_SEL, cfg->clkInvert);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_SF_RX_INV_SEL, cfg->rxClkInvert);
+
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal);
+
+    /* Set do di and oe delay */
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_0_DO_DLY_SEL, cfg->doDelay);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_0_DI_DLY_SEL, cfg->diDelay);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_0_OE_DLY_SEL, cfg->oeDelay);
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_1, tmpVal);
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_1_DO_DLY_SEL, cfg->doDelay);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_1_DI_DLY_SEL, cfg->diDelay);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_1_OE_DLY_SEL, cfg->oeDelay);
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_2, tmpVal);
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_2_DO_DLY_SEL, cfg->doDelay);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_2_DI_DLY_SEL, cfg->diDelay);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_2_OE_DLY_SEL, cfg->oeDelay);
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_3, tmpVal);
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_4);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_3_DO_DLY_SEL, cfg->doDelay);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_3_DI_DLY_SEL, cfg->diDelay);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_3_OE_DLY_SEL, cfg->oeDelay);
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_4, tmpVal);
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_0_DO_DLY_SEL, cfg->doDelay);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_0_DI_DLY_SEL, cfg->diDelay);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_0_OE_DLY_SEL, cfg->oeDelay);
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_1, tmpVal);
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_1_DO_DLY_SEL, cfg->doDelay);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_1_DI_DLY_SEL, cfg->diDelay);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_1_OE_DLY_SEL, cfg->oeDelay);
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_2, tmpVal);
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_2_DO_DLY_SEL, cfg->doDelay);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_2_DI_DLY_SEL, cfg->diDelay);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_2_OE_DLY_SEL, cfg->oeDelay);
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_3, tmpVal);
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_4);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_3_DO_DLY_SEL, cfg->doDelay);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_3_DI_DLY_SEL, cfg->diDelay);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_3_OE_DLY_SEL, cfg->oeDelay);
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_4, tmpVal);
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_0_DO_DLY_SEL, cfg->doDelay);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_0_DI_DLY_SEL, cfg->diDelay);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_0_OE_DLY_SEL, cfg->oeDelay);
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_1, tmpVal);
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_1_DO_DLY_SEL, cfg->doDelay);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_1_DI_DLY_SEL, cfg->diDelay);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_1_OE_DLY_SEL, cfg->oeDelay);
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_2, tmpVal);
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_2_DO_DLY_SEL, cfg->doDelay);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_2_DI_DLY_SEL, cfg->diDelay);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_2_OE_DLY_SEL, cfg->oeDelay);
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_3, tmpVal);
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_4);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_3_DO_DLY_SEL, cfg->doDelay);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_3_DI_DLY_SEL, cfg->diDelay);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_3_OE_DLY_SEL, cfg->oeDelay);
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_4, tmpVal);
+
+    /* Enable AHB access sram buffer and enable sf interface */
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SRAM_EN);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN);
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal);
+
+    SF_Ctrl_Set_Owner(cfg->owner);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Enable serail psram controller
+ *
+ * @param  sfCtrlPsramCfg: serial psram controller config
+ *
+ * @return None
+ *
+*******************************************************************************/
+//#ifndef BFLB_USE_ROM_DRIVER
+//__WEAK
+void ATTR_TCM_SECTION SF_Ctrl_Psram_Init(SF_Ctrl_Psram_Cfg *sfCtrlPsramCfg)
+{
+    uint32_t tmpVal = 0;
+
+    SF_Ctrl_Select_Pad(sfCtrlPsramCfg->padSel);
+    SF_Ctrl_Select_Bank(sfCtrlPsramCfg->bankSel);
+
+    /* Select psram clock delay */
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_12);
+
+    if (sfCtrlPsramCfg->psramRxClkInvertSrc) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SRC);
+
+        if (sfCtrlPsramCfg->psramRxClkInvertSel) {
+            tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SEL);
+        } else {
+            tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SEL);
+        }
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SRC);
+    }
+
+    if (sfCtrlPsramCfg->psramDelaySrc) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_SRC);
+
+        if (sfCtrlPsramCfg->psramClkDelay > 0) {
+            tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_EN);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IF_READ_DLY_N, sfCtrlPsramCfg->psramClkDelay - 1);
+        } else {
+            tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_EN);
+        }
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_SRC);
+    }
+
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_12, tmpVal);
+
+    /* Enable AHB access sram buffer and enable sf interface */
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SRAM_EN);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN);
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal);
+
+    SF_Ctrl_Set_Owner(sfCtrlPsramCfg->owner);
+}
+//#endif
+
+/****************************************************************************/ /**
+ * @brief  Get flash controller clock delay value
+ *
+ * @param  None
+ *
+ * @return Clock delay value
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+uint8_t ATTR_TCM_SECTION SF_Ctrl_Get_Clock_Delay(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0);
+
+    if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN) == 0) {
+        return 0;
+    } else {
+        return BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N) + 1;
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set flash controller clock delay value
+ *
+ * @param  delay: Clock delay value
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SF_Ctrl_Set_Clock_Delay(uint8_t delay)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0);
+
+    if (delay > 0) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N, delay - 1);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN);
+    }
+
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  SF Ctrl set cmds config
+ *
+ * @param  cmdsCfg: SF Ctrl cmds config
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SF_CTRL_WRAP_LEN_TYPE(cmdsCfg->wrapLen));
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_3);
+
+    if (cmdsCfg->cmdsEn) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_EN);
+    }
+
+    if (cmdsCfg->burstToggleEn) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_BT_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_BT_EN);
+    }
+
+    if (cmdsCfg->wrapModeEn) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_WRAP_MODE);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_WRAP_MODE);
+    }
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_WRAP_LEN, cmdsCfg->wrapLen);
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_3, tmpVal);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  SF Ctrl pad select
+ *
+ * @param  sel: pad select type
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Select sel)
+{
+    /* TODO: sf_if_bk_swap */
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SF_CTRL_PAD_SELECT(sel));
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2);
+
+    if (sel <= SF_CTRL_PAD_SEL_SF3) {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, sel);
+    } else if (sel >= SF_CTRL_PAD_SEL_DUAL_BANK_SF1_SF2 && sel <= SF_CTRL_PAD_SEL_DUAL_BANK_SF3_SF1) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN);
+        tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_MODE);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, sel - SF_CTRL_PAD_SEL_DUAL_BANK_SF1_SF2);
+    } else if (sel == SF_CTRL_PAD_SEL_DUAL_CS_SF2) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_MODE);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, 1);
+    } else if (sel == SF_CTRL_PAD_SEL_DUAL_CS_SF3) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_MODE);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, 2);
+    }
+
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  SF Ctrl bank select
+ *
+ * @param  sel: bank select type
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SF_Ctrl_Select_Bank(SF_Ctrl_Select sel)
+{
+    /* TODO: sf_if_bk_swap */
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SF_CTRL_SELECT(sel));
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2);
+
+    if (sel == SF_CTRL_SEL_FLASH) {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_BK_SEL);
+    } else {
+        tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_BK_SEL);
+    }
+
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set flash controller owner:I/D AHB or system AHB
+ *
+ * @param  owner: owner type
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner)
+{
+    uint32_t tmpVal = 0;
+    uint32_t timeOut = 0;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SF_CTRL_OWNER_TYPE(owner));
+
+    timeOut = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+    while (SET == SF_Ctrl_GetBusyState()) {
+        timeOut--;
+
+        if (timeOut == 0) {
+            return;
+        }
+    }
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1);
+
+    /* Set owner */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL, owner);
+
+    /* Set iahb to flash interface */
+    if (owner == SF_CTRL_OWNER_IAHB) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_EN);
+    }
+
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Disable flash controller
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SF_Ctrl_Disable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1);
+
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN);
+
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Enable flash controller AES with big indian
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_BE(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_KEY_ENDIAN);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_IV_ENDIAN);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_DOUT_ENDIAN);
+
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Enable flash controller AES with little indian
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_LE(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0);
+
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_KEY_ENDIAN);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_IV_ENDIAN);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_DOUT_ENDIAN);
+
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Serial flash controller set AES region
+ *
+ * @param  region: region number
+ * @param  enable: enable or not
+ * @param  hwKey: hardware key or software key
+ * @param  startAddr: region start address
+ * @param  endAddr: region end address
+ * @param  locked: lock this region or not
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable,
+                                             uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked)
+{
+    /* Do flash key eco*/
+    uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region);
+    uint32_t tmpVal;
+
+    if (!hwKey) {
+        regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region);
+    }
+
+    tmpVal = BL_RD_REG(regionRegBase, SF_CTRL_SF_AES_CFG);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_HW_KEY_EN, hwKey);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_START, startAddr / 1024);
+    /* sf_aes_end =1 means 1,11,1111,1111 */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_END, endAddr / 1024);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_EN, enable);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_LOCK, locked);
+
+    BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_CFG, tmpVal);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Serial flash controller set AES key
+ *
+ * @param  region: region number
+ * @param  key: key data pointer
+ * @param  keyType: flash controller AES key type:128 bits,192 bits or 256 bits
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType)
+{
+    /* Do flash key eco*/
+    uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region);
+    uint32_t tmpVal, i = 0;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType));
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType);
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal);
+
+    if (NULL != key) {
+        if (keyType == SF_CTRL_AES_128BITS) {
+            i = 4;
+            /*
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key)));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key)));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key)));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key)));
+            key+=4;
+            */
+        } else if (keyType == SF_CTRL_AES_256BITS) {
+            i = 8;
+            /*
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key)));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key)));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key)));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key)));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key)));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key)));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,__REV(BL_RDWD_FRM_BYTEP(key)));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,__REV(BL_RDWD_FRM_BYTEP(key)));
+            key+=4;
+            */
+        } else if (keyType == SF_CTRL_AES_192BITS) {
+            i = 6;
+            /*
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key)));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key)));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key)));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key)));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key)));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key)));
+            key+=4;
+            */
+        }
+
+        tmpVal = SF_CTRL_SF_AES_KEY_7_OFFSET;
+
+        while (i--) {
+            BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(key)));
+            key += 4;
+            tmpVal -= 4;
+        }
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Serial flash controller set AES key with big endian
+ *
+ * @param  region: region number
+ * @param  key: key data pointer
+ * @param  keyType: flash controller AES key type:128 bits,192 bits or 256 bits
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType)
+{
+    /* Do flash key eco*/
+    uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region);
+    uint32_t tmpVal, i = 0;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType));
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType);
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal);
+
+    if (NULL != key) {
+        if (keyType == SF_CTRL_AES_128BITS) {
+            i = 4;
+            /*
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key));
+            key+=4;
+            */
+        } else if (keyType == SF_CTRL_AES_256BITS) {
+            i = 8;
+            /*
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,BL_RDWD_FRM_BYTEP(key));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,BL_RDWD_FRM_BYTEP(key));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,BL_RDWD_FRM_BYTEP(key));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,BL_RDWD_FRM_BYTEP(key));
+            key+=4;
+            */
+        } else if (keyType == SF_CTRL_AES_192BITS) {
+            i = 6;
+            /*
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,BL_RDWD_FRM_BYTEP(key));
+            key+=4;
+            BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,BL_RDWD_FRM_BYTEP(key));
+            */
+        }
+
+        tmpVal = SF_CTRL_SF_AES_KEY_0_OFFSET;
+
+        while (i--) {
+            BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(key));
+            key += 4;
+            tmpVal += 4;
+        }
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Serial flash controller set AES iv
+ *
+ * @param  region: region number
+ * @param  iv: iv data pointer
+ * @param  addrOffset: flash address offset
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset)
+{
+    /* Do flash key eco*/
+    uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region);
+    uint32_t tmpVal, i = 3;
+
+    if (iv != NULL) {
+        tmpVal = SF_CTRL_SF_AES_IV_W3_OFFSET;
+
+        while (i--) {
+            BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(iv)));
+            iv += 4;
+            tmpVal -= 4;
+        }
+
+        /*
+        BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W3,__REV(BL_RDWD_FRM_BYTEP(iv)));
+        iv+=4;
+        BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W2,__REV(BL_RDWD_FRM_BYTEP(iv)));
+        iv+=4;
+        BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W1,__REV(BL_RDWD_FRM_BYTEP(iv)));
+        iv+=4;
+        */
+        BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W0, addrOffset);
+        iv += 4;
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Serial flash controller set AES iv with big endian
+ *
+ * @param  region: region number
+ * @param  iv: iv data pointer
+ * @param  addrOffset: flash address offset
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset)
+{
+    /* Do flash key eco*/
+    uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region);
+    uint32_t tmpVal, i = 3;
+
+    if (iv != NULL) {
+        tmpVal = SF_CTRL_SF_AES_IV_W0_OFFSET;
+
+        while (i--) {
+            BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(iv));
+            iv += 4;
+            tmpVal += 4;
+        }
+
+        /*
+        BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W0,BL_RDWD_FRM_BYTEP(iv));
+        iv+=4;
+        BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W1,BL_RDWD_FRM_BYTEP(iv));
+        iv+=4;
+        BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W2,BL_RDWD_FRM_BYTEP(iv));
+        iv+=4;
+        */
+        BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W3, __REV(addrOffset));
+        iv += 4;
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Enable serial flash controller AES
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SF_Ctrl_AES_Enable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_EN);
+
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Disable serial flash controller AES
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SF_Ctrl_AES_Disable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_EN);
+
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Check is serial flash controller AES enable
+ *
+ * @param  None
+ *
+ * @return Wether AES is enable
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+uint8_t ATTR_TCM_SECTION SF_Ctrl_Is_AES_Enable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES);
+    return BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_AES_EN);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set flash image offset
+ *
+ * @param  addrOffset: Address offset value
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset)
+{
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET, addrOffset);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Get flash image offset
+ *
+ * @param  None
+ *
+ * @return :Address offset value
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+uint32_t ATTR_TCM_SECTION SF_Ctrl_Get_Flash_Image_Offset(void)
+{
+    return BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  SF controller send one command
+ *
+ * @param  sahbType: Serial flash controller clock sahb sram select
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0);
+
+    if (sahbType == SF_CTRL_SAHB_CLOCK) {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CLK_SAHB_SRAM_SEL);
+    } else if (sahbType == SF_CTRL_FLASH_CLOCK) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CLK_SAHB_SRAM_SEL);
+    }
+
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  SF controller send one command
+ *
+ * @param  cfg: Serial flash controller command configuration pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg)
+{
+    uint32_t tmpVal = 0;
+    uint32_t timeOut = 0;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode));
+    CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode));
+    CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode));
+    CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode));
+
+    timeOut = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+    while (SET == SF_Ctrl_GetBusyState()) {
+        timeOut--;
+
+        if (timeOut == 0) {
+            return;
+        }
+    }
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1);
+
+    if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_SAHB) {
+        return;
+    }
+
+    /* Clear trigger */
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_TRIG);
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0, tmpVal);
+
+    /* Copy command buffer */
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_1, cfg->cmdBuf[0]);
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_2, cfg->cmdBuf[1]);
+
+    /* Configure SPI and IO mode*/
+    if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_QPI_MODE_EN, SF_CTRL_SPI_MODE);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_QPI_MODE_EN, SF_CTRL_QPI_MODE);
+    }
+
+    if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) {
+        if (SF_CTRL_DATA_1_LINE == cfg->dataMode) {
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_NIO_MODE);
+        } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) {
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_DO_MODE);
+        } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) {
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_QO_MODE);
+        }
+    } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_DIO_MODE);
+    } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_QIO_MODE);
+    }
+
+    /* Configure cmd */
+    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_CMD_EN);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_CMD_BYTE, 0);
+
+    /* Configure address */
+    if (cfg->addrSize != 0) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_ADR_EN);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_ADR_BYTE, cfg->addrSize - 1);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_ADR_EN);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_ADR_BYTE, 0);
+    }
+
+    /* Configure dummy */
+    if (cfg->dummyClks != 0) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_DMY_EN);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DMY_BYTE, cfg->dummyClks - 1);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_DMY_EN);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DMY_BYTE, 0);
+    }
+
+    /* Configure data */
+    if (cfg->nbData != 0) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_DAT_EN);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DAT_BYTE, cfg->nbData - 1);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_DAT_EN);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DAT_BYTE, 0);
+    }
+
+    /* Set read write flag */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DAT_RW, cfg->rwFlag);
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0, tmpVal);
+
+    //switch sf_clk_sahb_sram_sel = 1
+    SF_Ctrl_Select_Clock(SF_CTRL_FLASH_CLOCK);
+    /* Trigger */
+    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_TRIG);
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0, tmpVal);
+
+    timeOut = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+    while (SET == SF_Ctrl_GetBusyState()) {
+        timeOut--;
+
+        if (timeOut == 0) {
+            SF_Ctrl_Select_Clock(SF_CTRL_SAHB_CLOCK);
+            return;
+        }
+    }
+
+    //switch sf_clk_sahb_sram_sel = 0
+    SF_Ctrl_Select_Clock(SF_CTRL_SAHB_CLOCK);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Config SF controller for flash I/D cache read
+ *
+ * @param  cfg: Serial flash controller command configuration pointer
+ * @param  cmdValid: command valid or not, for continous read, cache may need no command
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid)
+{
+    uint32_t tmpVal = 0;
+    uint32_t timeOut = 0;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode));
+    CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode));
+    CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode));
+    CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode));
+
+    timeOut = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+    while (SET == SF_Ctrl_GetBusyState()) {
+        timeOut--;
+
+        if (timeOut == 0) {
+            return;
+        }
+    }
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1);
+
+    if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) {
+        return;
+    }
+
+    /* Copy command buffer */
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_1, cfg->cmdBuf[0]);
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_2, cfg->cmdBuf[1]);
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_0);
+
+    /* Configure SPI and IO mode*/
+    if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_SPI_MODE);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_QPI_MODE);
+    }
+
+    if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) {
+        if (SF_CTRL_DATA_1_LINE == cfg->dataMode) {
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_NIO_MODE);
+        } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) {
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DO_MODE);
+        } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) {
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QO_MODE);
+        }
+    } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DIO_MODE);
+    } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QIO_MODE);
+    }
+
+    if (cmdValid) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 1);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0);
+    }
+
+    /* Configure address */
+    if (cfg->addrSize != 0) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 1);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, cfg->addrSize - 1);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, 0);
+    }
+
+    /* configure dummy */
+    if (cfg->dummyClks != 0) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 1);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, cfg->dummyClks - 1);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, 0);
+    }
+
+    /* Configure data */
+    if (cfg->nbData != 0) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 1);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 0);
+    }
+
+    /* Set read write flag */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_RW, cfg->rwFlag);
+
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_0, tmpVal);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Config psram controller for psram I/D cache write
+ *
+ * @param  cfg: Serial flash controller command configuration pointer
+ * @param  cmdValid: command valid or not, cache may need no command
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SF_Ctrl_Psram_Write_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid)
+{
+    uint32_t tmpVal = 0;
+    uint32_t timeOut = 0;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode));
+    CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode));
+    CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode));
+    CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode));
+
+    timeOut = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+    while (SET == SF_Ctrl_GetBusyState()) {
+        timeOut--;
+
+        if (timeOut == 0) {
+            return;
+        }
+    }
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1);
+
+    if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) {
+        return;
+    }
+
+    /* Copy command buffer */
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_4, cfg->cmdBuf[0]);
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_5, cfg->cmdBuf[1]);
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_3);
+
+    /* Configure SPI and IO mode*/
+    if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_QPI_MODE_EN, SF_CTRL_SPI_MODE);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_QPI_MODE_EN, SF_CTRL_QPI_MODE);
+    }
+
+    if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) {
+        if (SF_CTRL_DATA_1_LINE == cfg->dataMode) {
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_NIO_MODE);
+        } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) {
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_DO_MODE);
+        } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) {
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_QO_MODE);
+        }
+    } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_DIO_MODE);
+    } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_QIO_MODE);
+    }
+
+    if (cmdValid) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_CMD_EN, 1);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_CMD_BYTE, 0);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_CMD_EN, 0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_CMD_BYTE, 0);
+    }
+
+    /* Configure address */
+    if (cfg->addrSize != 0) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_ADR_EN, 1);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_ADR_BYTE, cfg->addrSize - 1);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_ADR_EN, 0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_ADR_BYTE, 0);
+    }
+
+    /* configure dummy */
+    if (cfg->dummyClks != 0) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DMY_EN, 1);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DMY_BYTE, cfg->dummyClks - 1);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DMY_EN, 0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DMY_BYTE, 0);
+    }
+
+    /* Configure data */
+    if (cfg->nbData != 0) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DAT_EN, 1);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DAT_EN, 0);
+    }
+
+    /* Set read write flag */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DAT_RW, cfg->rwFlag);
+
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_3, tmpVal);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Config psram controller for psram I/D cache read
+ *
+ * @param  cfg: Serial flash controller command configuration pointer
+ * @param  cmdValid: command valid or not, for continous read, cache may need no command
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SF_Ctrl_Psram_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid)
+{
+    uint32_t tmpVal = 0;
+    uint32_t timeOut = 0;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode));
+    CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode));
+    CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode));
+    CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode));
+
+    timeOut = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+    while (SET == SF_Ctrl_GetBusyState()) {
+        timeOut--;
+
+        if (timeOut == 0) {
+            return;
+        }
+    }
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1);
+
+    if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) {
+        return;
+    }
+
+    /* Copy command buffer */
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_10, cfg->cmdBuf[0]);
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_11, cfg->cmdBuf[1]);
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_9);
+
+    /* Configure SPI and IO mode*/
+    if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_SPI_MODE);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_QPI_MODE);
+    }
+
+    if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) {
+        if (SF_CTRL_DATA_1_LINE == cfg->dataMode) {
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_NIO_MODE);
+        } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) {
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DO_MODE);
+        } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) {
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QO_MODE);
+        }
+    } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DIO_MODE);
+    } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QIO_MODE);
+    }
+
+    if (cmdValid) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 1);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0);
+    }
+
+    /* Configure address */
+    if (cfg->addrSize != 0) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 1);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, cfg->addrSize - 1);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, 0);
+    }
+
+    /* configure dummy */
+    if (cfg->dummyClks != 0) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 1);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, cfg->dummyClks - 1);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, 0);
+    }
+
+    /* Configure data */
+    if (cfg->nbData != 0) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 1);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 0);
+    }
+
+    /* Set read write flag */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_RW, cfg->rwFlag);
+
+    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_9, tmpVal);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Get SF Ctrl busy state
+ *
+ * @param  None
+ *
+ * @return SET  for SF ctrl busy or RESET for SF ctrl not busy
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_GetBusyState(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0);
+
+    if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_IF_BUSY)) {
+        return SET;
+    } else {
+        return RESET;
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  SF Controller interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void SF_Ctrl_IRQHandler(void)
+{
+    /* TODO: Not implemented */
+}
+#endif
+
+/*@} end of group SF_CTRL_Public_Functions */
+
+/*@} end of group SF_CTRL */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sflash.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sflash.c
new file mode 100644
index 00000000..81ec04b3
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sflash.c
@@ -0,0 +1,1489 @@
+/**
+ ******************************************************************************
+ * @file    bl702_sflash.c
+ * @version V1.0
+ * @date
+ * @brief   This file is the standard driver c file
+ ******************************************************************************
+ * @attention
+ *
+ * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#include "bl702_sflash.h"
+#include "bl702_l1c.h"
+#include "bl702_sf_ctrl.h"
+#include "string.h"
+
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SFLASH
+ *  @{
+ */
+
+/** @defgroup  SFLASH_Private_Macros
+ *  @{
+ */
+
+/*@} end of group SFLASH_Private_Macros */
+
+/** @defgroup  SFLASH_Private_Types
+ *  @{
+ */
+
+/*@} end of group SFLASH_Private_Types */
+
+/** @defgroup  SFLASH_Private_Variables
+ *  @{
+ */
+#define SFCTRL_BUSY_STATE_TIMEOUT (5 * 160 * 1000)
+
+/*@} end of group SFLASH_Private_Variables */
+
+/** @defgroup  SFLASH_Global_Variables
+ *  @{
+ */
+
+/*@} end of group SFLASH_Global_Variables */
+
+/** @defgroup  SFLASH_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group SFLASH_Private_Fun_Declaration */
+
+/** @defgroup  SFLASH_Private_Functions
+ *  @{
+ */
+
+/*@} end of group SFLASH_Private_Functions */
+
+/** @defgroup  SFLASH_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+                                                                                * @brief  Init serial flash control interface
+                                                                                *
+                                                                                * @param  pSfCtrlCfg: Serial flash controller configuration pointer
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg) { SF_Ctrl_Enable(pSfCtrlCfg); }
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Set serial flash control interface SPI or QPI mode
+                                                                                *
+                                                                                * @param  mode: Serial flash interface mode
+                                                                                *
+                                                                                * @return BFLB_RET:SUCCESS or ERROR
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode) {
+  BL_Err_Type stat = SUCCESS;
+
+  /* Check the parameters */
+  CHECK_PARAM(IS_SF_CTRL_MODE_TYPE(mode));
+
+  return stat;
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Read flash register
+                                                                                *
+                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
+                                                                                * @param  regIndex: register index
+                                                                                * @param  regValue: register value pointer to store data
+                                                                                * @param  regLen: register value length
+                                                                                *
+                                                                                * @return SUCCESS or ERROR
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) {
+  uint8_t *const       flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
+  SF_Ctrl_Cmd_Cfg_Type flashCmd;
+  uint32_t             cnt = 0;
+
+  if (((uint32_t)&flashCmd) % 4 == 0) {
+    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
+  } else {
+    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
+  }
+
+  flashCmd.cmdBuf[0] = (flashCfg->readRegCmd[regIndex]) << 24;
+  flashCmd.rwFlag    = SF_CTRL_READ;
+  flashCmd.nbData    = regLen;
+
+  SF_Ctrl_SendCmd(&flashCmd);
+
+  while (SET == SF_Ctrl_GetBusyState()) {
+    BL702_Delay_US(1);
+    cnt++;
+
+    if (cnt > 1000) {
+      return ERROR;
+    }
+  }
+
+  BL702_MemCpy(regValue, flashCtrlBuf, regLen);
+  return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Write flash register
+                                                                                *
+                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
+                                                                                * @param  regIndex: register index
+                                                                                * @param  regValue: register value pointer storing data
+                                                                                * @param  regLen: register value length
+                                                                                *
+                                                                                * @return SUCCESS or ERROR
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) {
+  uint8_t *const       flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
+  uint32_t             cnt          = 0;
+  SF_Ctrl_Cmd_Cfg_Type flashCmd;
+
+  if (((uint32_t)&flashCmd) % 4 == 0) {
+    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
+  } else {
+    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
+  }
+
+  BL702_MemCpy(flashCtrlBuf, regValue, regLen);
+
+  flashCmd.cmdBuf[0] = (flashCfg->writeRegCmd[regIndex]) << 24;
+  flashCmd.rwFlag    = SF_CTRL_WRITE;
+  flashCmd.nbData    = regLen;
+
+  SF_Ctrl_SendCmd(&flashCmd);
+
+  /* take 40ms for tw(write status register) as default */
+  while (SET == SFlash_Busy(flashCfg)) {
+    BL702_Delay_US(100);
+    cnt++;
+
+    if (cnt > 400) {
+      return ERROR;
+    }
+  }
+
+  return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Read flash register with read command
+                                                                                *
+                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
+                                                                                * @param  readRegCmd: read command
+                                                                                * @param  regValue: register value pointer to store data
+                                                                                * @param  regLen: register value length
+                                                                                *
+                                                                                * @return SUCCESS or ERROR
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen) {
+  uint8_t *const       flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
+  SF_Ctrl_Cmd_Cfg_Type flashCmd;
+  uint32_t             cnt = 0;
+
+  if (((uint32_t)&flashCmd) % 4 == 0) {
+    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
+  } else {
+    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
+  }
+
+  flashCmd.cmdBuf[0] = readRegCmd << 24;
+  flashCmd.rwFlag    = SF_CTRL_READ;
+  flashCmd.nbData    = regLen;
+
+  SF_Ctrl_SendCmd(&flashCmd);
+
+  while (SET == SF_Ctrl_GetBusyState()) {
+    BL702_Delay_US(1);
+    cnt++;
+
+    if (cnt > 1000) {
+      return ERROR;
+    }
+  }
+
+  BL702_MemCpy(regValue, flashCtrlBuf, regLen);
+  return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Write flash register with write command
+                                                                                *
+                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
+                                                                                * @param  writeRegCmd: write command
+                                                                                * @param  regValue: register value pointer storing data
+                                                                                * @param  regLen: register value length
+                                                                                *
+                                                                                * @return SUCCESS or ERROR
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen) {
+  uint8_t *const       flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
+  uint32_t             cnt          = 0;
+  SF_Ctrl_Cmd_Cfg_Type flashCmd;
+
+  if (((uint32_t)&flashCmd) % 4 == 0) {
+    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
+  } else {
+    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
+  }
+
+  BL702_MemCpy(flashCtrlBuf, regValue, regLen);
+
+  flashCmd.cmdBuf[0] = writeRegCmd << 24;
+  flashCmd.rwFlag    = SF_CTRL_WRITE;
+  flashCmd.nbData    = regLen;
+
+  SF_Ctrl_SendCmd(&flashCmd);
+
+  /* take 40ms for tw(write status register) as default */
+  while (SET == SFlash_Busy(flashCfg)) {
+    BL702_Delay_US(100);
+    cnt++;
+
+    if (cnt > 400) {
+      return ERROR;
+    }
+  }
+
+  return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Check flash busy status
+                                                                                *
+                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
+                                                                                *
+                                                                                * @return SET for busy or RESET for not busy
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Sts_Type ATTR_TCM_SECTION SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg) {
+  uint32_t stat = 0;
+  SFlash_Read_Reg(flashCfg, flashCfg->busyIndex, (uint8_t *)&stat, flashCfg->busyReadRegLen);
+
+  if ((stat & (1 << flashCfg->busyBit)) == 0) {
+    return RESET;
+  }
+
+  return SET;
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Enable flash write function
+                                                                                *
+                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
+                                                                                *
+                                                                                * @return SUCCESS or ERROR
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) {
+  uint32_t             stat = 0;
+  SF_Ctrl_Cmd_Cfg_Type flashCmd;
+
+  if (((uint32_t)&flashCmd) % 4 == 0) {
+    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
+  } else {
+    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
+  }
+
+  /* Write enable*/
+  flashCmd.cmdBuf[0] = (flashCfg->writeEnableCmd) << 24;
+  /* rwFlag don't care */
+  flashCmd.rwFlag = SF_CTRL_READ;
+  SF_Ctrl_SendCmd(&flashCmd);
+
+  SFlash_Read_Reg(flashCfg, flashCfg->wrEnableIndex, (uint8_t *)&stat, flashCfg->wrEnableReadRegLen);
+
+  if ((stat & (1 << flashCfg->wrEnableBit)) != 0) {
+    return SUCCESS;
+  }
+
+  return ERROR;
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Enable flash flash controller QSPI interface
+                                                                                *
+                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
+                                                                                *
+                                                                                * @return SUCCESS or ERROR
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg) {
+  uint32_t stat = 0, ret;
+
+  if (flashCfg->qeReadRegLen == 0) {
+    ret = SFlash_Write_Enable(flashCfg);
+
+    if (SUCCESS != ret) {
+      return ERROR;
+    }
+
+    SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen);
+    return SUCCESS;
+  }
+
+  SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen);
+
+  if (flashCfg->qeData == 0) {
+    if ((stat & (1 << flashCfg->qeBit)) != 0) {
+      return SUCCESS;
+    }
+  } else {
+    if (((stat >> (flashCfg->qeBit & 0x08)) & 0xff) == flashCfg->qeData) {
+      return SUCCESS;
+    }
+  }
+
+  if (flashCfg->qeWriteRegLen != 1) {
+    /* This is  read r0,read r1 write r0,r1 case*/
+    SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&stat, 1);
+    SFlash_Read_Reg(flashCfg, 1, ((uint8_t *)&stat) + 1, 1);
+
+    if (flashCfg->qeData == 0) {
+      stat |= (1 << (flashCfg->qeBit + 8 * flashCfg->qeIndex));
+    } else {
+      stat = stat & (~(0xff << (8 * flashCfg->qeIndex)));
+      stat |= (flashCfg->qeData << (8 * flashCfg->qeIndex));
+    }
+  } else {
+    if (flashCfg->qeData == 0) {
+      stat |= (1 << (flashCfg->qeBit % 8));
+    } else {
+      stat = flashCfg->qeData;
+    }
+  }
+
+  ret = SFlash_Write_Enable(flashCfg);
+
+  if (SUCCESS != ret) {
+    return ERROR;
+  }
+
+  SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen);
+  SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen);
+
+  if (flashCfg->qeData == 0) {
+    if ((stat & (1 << flashCfg->qeBit)) != 0) {
+      return SUCCESS;
+    }
+  } else {
+    if (((stat >> (flashCfg->qeBit & 0x08)) & 0xff) == flashCfg->qeData) {
+      return SUCCESS;
+    }
+  }
+
+  return ERROR;
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Enable flash volatile register write enable
+                                                                                *
+                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) {
+  SF_Ctrl_Cmd_Cfg_Type flashCmd;
+
+  if (((uint32_t)&flashCmd) % 4 == 0) {
+    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
+  } else {
+    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
+  }
+
+  flashCmd.cmdBuf[0] = (flashCfg->writeVregEnableCmd) << 24;
+  flashCmd.rwFlag    = SF_CTRL_WRITE;
+
+  SF_Ctrl_SendCmd(&flashCmd);
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Erase flash whole chip
+                                                                                *
+                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
+                                                                                *
+                                                                                * @return SUCCESS or ERROR
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg) {
+  SF_Ctrl_Cmd_Cfg_Type flashCmd;
+  uint32_t             cnt  = 0;
+  BL_Err_Type          stat = SFlash_Write_Enable(flashCfg);
+
+  if (stat != SUCCESS) {
+    return stat;
+  }
+
+  if (((uint32_t)&flashCmd) % 4 == 0) {
+    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
+  } else {
+    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
+  }
+
+  flashCmd.cmdBuf[0] = (flashCfg->chipEraseCmd) << 24;
+  /* rwFlag don't care */
+  flashCmd.rwFlag = SF_CTRL_READ;
+
+  SF_Ctrl_SendCmd(&flashCmd);
+
+  while (SET == SFlash_Busy(flashCfg)) {
+    BL702_Delay_US(500);
+    cnt++;
+
+    if (cnt > flashCfg->timeCe * 3) {
+      return ERROR;
+    }
+  }
+
+  return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Erase flash one sector
+                                                                                *
+                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
+                                                                                * @param  secNum: flash sector number
+                                                                                *
+                                                                                * @return SUCCESS or ERROR
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum) {
+  uint32_t             cnt = 0;
+  SF_Ctrl_Cmd_Cfg_Type flashCmd;
+
+  BL_Err_Type stat = SFlash_Write_Enable(flashCfg);
+
+  if (stat != SUCCESS) {
+    return stat;
+  }
+
+  if (((uint32_t)&flashCmd) % 4 == 0) {
+    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
+  } else {
+    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
+  }
+
+  flashCmd.cmdBuf[0] = (flashCfg->sectorEraseCmd << 24) | (flashCfg->sectorSize * 1024 * secNum);
+  /* rwFlag don't care */
+  flashCmd.rwFlag   = SF_CTRL_READ;
+  flashCmd.addrSize = 3;
+
+  SF_Ctrl_SendCmd(&flashCmd);
+
+  while (SET == SFlash_Busy(flashCfg)) {
+    BL702_Delay_US(500);
+    cnt++;
+
+    if (cnt > flashCfg->timeEsector * 3) {
+      return ERROR;
+    }
+  }
+
+  return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Erase flash one 32K block
+                                                                                *
+                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
+                                                                                * @param  blkNum: flash 32K block number
+                                                                                *
+                                                                                * @return SUCCESS or ERROR
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) {
+  uint32_t             cnt = 0;
+  SF_Ctrl_Cmd_Cfg_Type flashCmd;
+  BL_Err_Type          stat = SFlash_Write_Enable(flashCfg);
+
+  if (stat != SUCCESS) {
+    return stat;
+  }
+
+  if (((uint32_t)&flashCmd) % 4 == 0) {
+    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
+  } else {
+    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
+  }
+
+  flashCmd.cmdBuf[0] = (flashCfg->blk32EraseCmd << 24) | (BFLB_SPIFLASH_BLK32K_SIZE * blkNum);
+  /* rwFlag don't care */
+  flashCmd.rwFlag   = SF_CTRL_READ;
+  flashCmd.addrSize = 3;
+
+  SF_Ctrl_SendCmd(&flashCmd);
+
+  while (SET == SFlash_Busy(flashCfg)) {
+    BL702_Delay_US(500);
+    cnt++;
+
+    if (cnt > flashCfg->timeE32k * 3) {
+      return ERROR;
+    }
+  }
+
+  return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Erase flash one 64K block
+                                                                                *
+                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
+                                                                                * @param  blkNum: flash 64K block number
+                                                                                *
+                                                                                * @return SUCCESS or ERROR
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) {
+  SF_Ctrl_Cmd_Cfg_Type flashCmd;
+  uint32_t             cnt  = 0;
+  BL_Err_Type          stat = SFlash_Write_Enable(flashCfg);
+
+  if (stat != SUCCESS) {
+    return stat;
+  }
+
+  if (((uint32_t)&flashCmd) % 4 == 0) {
+    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
+  } else {
+    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
+  }
+
+  flashCmd.cmdBuf[0] = (flashCfg->blk64EraseCmd << 24) | (BFLB_SPIFLASH_BLK64K_SIZE * blkNum);
+  /* rwFlag don't care */
+  flashCmd.rwFlag   = SF_CTRL_READ;
+  flashCmd.addrSize = 3;
+
+  SF_Ctrl_SendCmd(&flashCmd);
+
+  while (SET == SFlash_Busy(flashCfg)) {
+    BL702_Delay_US(500);
+    cnt++;
+
+    if (cnt > flashCfg->timeE64k * 3) {
+      return ERROR;
+    }
+  }
+
+  return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Erase flash one region
+                                                                                *
+                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
+                                                                                * @param  startaddr: start address to erase
+                                                                                * @param  endaddr: end address(include this address) to erase
+                                                                                *
+                                                                                * @return SUCCESS or ERROR
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr) {
+  uint32_t    len      = 0;
+  uint32_t    eraseLen = 0;
+  BL_Err_Type ret      = SUCCESS;
+
+  while (startaddr <= endaddr) {
+    len = endaddr - startaddr + 1;
+
+    if (flashCfg->blk64EraseCmd != BFLB_SPIFLASH_CMD_INVALID && (startaddr & (BFLB_SPIFLASH_BLK64K_SIZE - 1)) == 0 && len > (uint32_t)(BFLB_SPIFLASH_BLK64K_SIZE - flashCfg->sectorSize * 1024)) {
+      /* 64K margin address,and length > 64K-sector size, erase one first */
+      ret      = SFlash_Blk64_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK64K_SIZE);
+      eraseLen = BFLB_SPIFLASH_BLK64K_SIZE;
+    } else if (flashCfg->blk32EraseCmd != BFLB_SPIFLASH_CMD_INVALID && (startaddr & (BFLB_SPIFLASH_BLK32K_SIZE - 1)) == 0
+               && len > (uint32_t)(BFLB_SPIFLASH_BLK32K_SIZE - flashCfg->sectorSize * 1024)) {
+      /* 32K margin address,and length > 32K-sector size, erase one first */
+      ret      = SFlash_Blk32_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK32K_SIZE);
+      eraseLen = BFLB_SPIFLASH_BLK32K_SIZE;
+    } else {
+      /* Sector erase */
+      startaddr = ((startaddr) & (~(flashCfg->sectorSize * 1024 - 1)));
+      ret       = SFlash_Sector_Erase(flashCfg, startaddr / flashCfg->sectorSize / 1024);
+      eraseLen  = flashCfg->sectorSize * 1024;
+    }
+
+    startaddr += eraseLen;
+
+    if (ret != SUCCESS) {
+      return ERROR;
+    }
+  }
+
+  return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Program flash one region
+                                                                                *
+                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
+                                                                                * @param  ioMode: progran mode:SPI mode or QPI mode
+                                                                                * @param  addr: start address to be programed
+                                                                                * @param  data: data pointer to be programed
+                                                                                * @param  len: data length to be programed
+                                                                                *
+                                                                                * @return SUCCESS or ERROR
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) {
+  uint8_t *const       flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
+  uint32_t             i = 0, curLen = 0;
+  uint32_t             cnt = 0;
+  BL_Err_Type          stat;
+  uint8_t              cmd;
+  SF_Ctrl_Cmd_Cfg_Type flashCmd;
+
+  if (((uint32_t)&flashCmd) % 4 == 0) {
+    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
+  } else {
+    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
+  }
+
+  if (SF_CTRL_NIO_MODE == ioMode || SF_CTRL_DO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) {
+    cmd = flashCfg->pageProgramCmd;
+  } else if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_QO_MODE == ioMode) {
+    flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->qppAddrMode;
+    flashCmd.dataMode = SF_CTRL_DATA_4_LINES;
+    cmd               = flashCfg->qpageProgramCmd;
+  } else {
+    return ERROR;
+  }
+
+  /* Prepare command */
+  flashCmd.rwFlag   = SF_CTRL_WRITE;
+  flashCmd.addrSize = 3;
+
+  for (i = 0; i < len;) {
+    /* Write enable is needed for every program */
+    stat = SFlash_Write_Enable(flashCfg);
+
+    if (stat != SUCCESS) {
+      return stat;
+    }
+
+    /* Get current programmed length within page size */
+    curLen = flashCfg->pageSize - addr % flashCfg->pageSize;
+
+    if (curLen > len - i) {
+      curLen = len - i;
+    }
+
+    /* Prepare command */
+    BL702_MemCpy_Fast(flashCtrlBuf, data, curLen);
+    flashCmd.cmdBuf[0] = (cmd << 24) | (addr);
+    flashCmd.nbData    = curLen;
+
+    SF_Ctrl_SendCmd(&flashCmd);
+
+    /* Adjust address and programmed length */
+    addr += curLen;
+    i += curLen;
+    data += curLen;
+
+    /* Wait for write done */
+    cnt = 0;
+
+    while (SET == SFlash_Busy(flashCfg)) {
+      BL702_Delay_US(100);
+      cnt++;
+
+      if (cnt > flashCfg->timePagePgm * 20) {
+        return ERROR;
+      }
+    }
+  }
+
+  return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Get flash unique ID
+                                                                                *
+                                                                                * @param  data: data pointer to store read data
+                                                                                * @param  idLen: unique ID len
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SFlash_GetUniqueId(uint8_t *data, uint8_t idLen) {
+  uint8_t *const       flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
+  uint8_t              cmd, dummyClks;
+  uint32_t             timeOut = 0;
+  SF_Ctrl_Cmd_Cfg_Type flashCmd;
+
+  if (((uint32_t)&flashCmd) % 4 == 0) {
+    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
+  } else {
+    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
+  }
+
+  dummyClks          = 4;
+  cmd                = 0x4B;
+  flashCmd.cmdBuf[0] = (cmd << 24);
+  flashCmd.rwFlag    = SF_CTRL_READ;
+  flashCmd.dummyClks = dummyClks;
+  flashCmd.nbData    = idLen;
+
+  SF_Ctrl_SendCmd(&flashCmd);
+
+  timeOut = SFCTRL_BUSY_STATE_TIMEOUT;
+
+  while (SET == SF_Ctrl_GetBusyState()) {
+    timeOut--;
+
+    if (timeOut == 0) {
+      return;
+    }
+  }
+
+  BL702_MemCpy(data, flashCtrlBuf, idLen);
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Get flash jedec ID
+                                                                                *
+                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
+                                                                                * @param  data: data pointer to store read data
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data) {
+  uint8_t *const       flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
+  uint8_t              cmd, dummyClks;
+  uint32_t             timeOut = 0;
+  SF_Ctrl_Cmd_Cfg_Type flashCmd;
+
+  if (((uint32_t)&flashCmd) % 4 == 0) {
+    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
+  } else {
+    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
+  }
+
+  dummyClks          = flashCfg->jedecIdCmdDmyClk;
+  cmd                = flashCfg->jedecIdCmd;
+  flashCmd.cmdBuf[0] = (cmd << 24);
+  flashCmd.rwFlag    = SF_CTRL_READ;
+  flashCmd.dummyClks = dummyClks;
+  flashCmd.nbData    = 3;
+
+  SF_Ctrl_SendCmd(&flashCmd);
+
+  timeOut = SFCTRL_BUSY_STATE_TIMEOUT;
+
+  while (SET == SF_Ctrl_GetBusyState()) {
+    timeOut--;
+
+    if (timeOut == 0) {
+      return;
+    }
+  }
+
+  BL702_MemCpy(data, flashCtrlBuf, 3);
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Get flash device ID
+                                                                                *
+                                                                                * @param  data: data pointer to store read data
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SFlash_GetDeviceId(uint8_t *data) {
+  uint8_t *const       flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
+  uint8_t              cmd, dummyClks;
+  uint32_t             timeOut = 0;
+  SF_Ctrl_Cmd_Cfg_Type flashCmd;
+  uint32_t             addr     = 0x00000001;
+  uint8_t              readMode = 0xFF;
+
+  if (((uint32_t)&flashCmd) % 4 == 0) {
+    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
+  } else {
+    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
+  }
+
+  flashCmd.addrMode  = SF_CTRL_ADDR_4_LINES;
+  flashCmd.dataMode  = SF_CTRL_DATA_4_LINES;
+  dummyClks          = 2;
+  cmd                = 0x94;
+  flashCmd.cmdBuf[0] = (cmd << 24) | (addr);
+  flashCmd.cmdBuf[1] = (readMode << 24);
+  flashCmd.rwFlag    = SF_CTRL_READ;
+  flashCmd.addrSize  = 4;
+  flashCmd.dummyClks = dummyClks;
+  flashCmd.nbData    = 2;
+
+  SF_Ctrl_SendCmd(&flashCmd);
+
+  timeOut = SFCTRL_BUSY_STATE_TIMEOUT;
+
+  while (SET == SF_Ctrl_GetBusyState()) {
+    timeOut--;
+
+    if (timeOut == 0) {
+      return;
+    }
+  }
+
+  BL702_MemCpy(data, flashCtrlBuf, 2);
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Set flash power down
+                                                                                *
+                                                                                * @param  None
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SFlash_Powerdown(void) {
+  SF_Ctrl_Cmd_Cfg_Type flashCmd;
+  uint8_t              cmd     = 0;
+  uint32_t             timeOut = 0;
+
+  if (((uint32_t)&flashCmd) % 4 == 0) {
+    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
+  } else {
+    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
+  }
+
+  cmd                = 0xB9;
+  flashCmd.cmdBuf[0] = (cmd << 24);
+  flashCmd.rwFlag    = SF_CTRL_WRITE;
+
+  SF_Ctrl_SendCmd(&flashCmd);
+
+  timeOut = SFCTRL_BUSY_STATE_TIMEOUT;
+
+  while (SET == SF_Ctrl_GetBusyState()) {
+    timeOut--;
+
+    if (timeOut == 0) {
+      return;
+    }
+  }
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Release flash power down for wake up
+                                                                                *
+                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg) {
+  uint8_t  cmd;
+  uint32_t timeOut = 0;
+
+  SF_Ctrl_Cmd_Cfg_Type flashCmd;
+
+  if (((uint32_t)&flashCmd) % 4 == 0) {
+    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
+  } else {
+    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
+  }
+
+  cmd                = flashCfg->releasePowerDown;
+  flashCmd.cmdBuf[0] = (cmd << 24);
+  flashCmd.rwFlag    = SF_CTRL_WRITE;
+
+  SF_Ctrl_SendCmd(&flashCmd);
+
+  timeOut = SFCTRL_BUSY_STATE_TIMEOUT;
+
+  while (SET == SF_Ctrl_GetBusyState()) {
+    timeOut--;
+
+    if (timeOut == 0) {
+      return;
+    }
+  }
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Sflash restore from power down
+                                                                                *
+                                                                                * @param  pFlashCfg: Flash configuration pointer
+                                                                                * @param  flashContRead: Whether enable continuous read
+                                                                                *
+                                                                                * @return SUCCESS or ERROR
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead) {
+  BL_Err_Type stat   = SUCCESS;
+  uint32_t    jdecId = 0;
+  uint8_t     tmp[8];
+  uint8_t     ioMode = pFlashCfg->ioMode & 0xf;
+
+  /* Wake flash up from power down */
+  SFlash_Releae_Powerdown(pFlashCfg);
+  BL702_Delay_US(120);
+
+  SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId);
+
+  if (SF_CTRL_QO_MODE == ioMode || SF_CTRL_QIO_MODE == ioMode) {
+    SFlash_Qspi_Enable(pFlashCfg);
+  }
+
+  if (((pFlashCfg->ioMode >> 4) & 0x01) == 1) {
+    /* unwrap */
+    L1C_Set_Wrap(DISABLE);
+  } else {
+    /* burst wrap */
+    L1C_Set_Wrap(ENABLE);
+    /* For command that is setting register instead of send command, we need write enable */
+    SFlash_Write_Enable(pFlashCfg);
+    SFlash_SetBurstWrap(pFlashCfg);
+  }
+
+  if (flashContRead) {
+    stat = SFlash_Read(pFlashCfg, ioMode, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp));
+    SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB);
+  } else {
+    stat = SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 0, 0, 32);
+  }
+
+  return stat;
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Set flash burst wrap config
+                                                                                *
+                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg) {
+  uint8_t *const       flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
+  uint8_t              cmd, dummyClks;
+  uint32_t             wrapData;
+  SF_Ctrl_Cmd_Cfg_Type flashCmd;
+
+  if (((flashCfg->ioMode >> 4) & 0x01) == 1) {
+    /* Disable burst wrap ,just return */
+    return;
+  }
+
+  if (((uint32_t)&flashCmd) % 4 == 0) {
+    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
+  } else {
+    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
+  }
+
+  flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->burstWrapDataMode;
+  flashCmd.dataMode = (SF_Ctrl_Data_Mode_Type)flashCfg->burstWrapDataMode;
+  dummyClks         = flashCfg->burstWrapCmdDmyClk;
+  cmd               = flashCfg->burstWrapCmd;
+  wrapData          = flashCfg->burstWrapData;
+  BL702_MemCpy4((uint32_t *)flashCtrlBuf, &wrapData, 4);
+  flashCmd.cmdBuf[0] = (cmd << 24);
+  flashCmd.rwFlag    = SF_CTRL_WRITE;
+  flashCmd.dummyClks = dummyClks;
+  flashCmd.nbData    = 1;
+
+  SF_Ctrl_SendCmd(&flashCmd);
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Disable flash burst wrap config
+                                                                                *
+                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg) {
+  uint8_t *const       flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
+  uint8_t              cmd, dummyClks;
+  uint32_t             wrapData;
+  SF_Ctrl_Cmd_Cfg_Type flashCmd;
+
+  if (((uint32_t)&flashCmd) % 4 == 0) {
+    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
+  } else {
+    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
+  }
+
+  flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->deBurstWrapDataMode;
+  flashCmd.dataMode = (SF_Ctrl_Data_Mode_Type)flashCfg->deBurstWrapDataMode;
+  dummyClks         = flashCfg->deBurstWrapCmdDmyClk;
+  cmd               = flashCfg->deBurstWrapCmd;
+  wrapData          = flashCfg->deBurstWrapData;
+  BL702_MemCpy4((uint32_t *)flashCtrlBuf, &wrapData, 4);
+  flashCmd.cmdBuf[0] = (cmd << 24);
+  flashCmd.rwFlag    = SF_CTRL_WRITE;
+  flashCmd.dummyClks = dummyClks;
+  flashCmd.nbData    = 1;
+
+  SF_Ctrl_SendCmd(&flashCmd);
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Software reset flash
+                                                                                *
+                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
+                                                                                *
+                                                                                * @return SUCCESS or ERROR
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg) {
+  uint16_t             cnt = 0;
+  SF_Ctrl_Cmd_Cfg_Type flashCmd;
+
+  if (((uint32_t)&flashCmd) % 4 == 0) {
+    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
+  } else {
+    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
+  }
+
+  /* Reset enable */
+  flashCmd.cmdBuf[0] = (flashCfg->resetEnCmd) << 24;
+  /* rwFlag don't care */
+  flashCmd.rwFlag = SF_CTRL_READ;
+
+  /* Wait for write done */
+  while (SET == SFlash_Busy(flashCfg)) {
+    BL702_Delay_US(100);
+    cnt++;
+
+    if (cnt > 20) {
+      return ERROR;
+    }
+  }
+
+  SF_Ctrl_SendCmd(&flashCmd);
+
+  /* Reset */
+  flashCmd.cmdBuf[0] = (flashCfg->resetCmd) << 24;
+  /* rwFlag don't care */
+  flashCmd.rwFlag = SF_CTRL_READ;
+  SF_Ctrl_SendCmd(&flashCmd);
+
+  BL702_Delay_US(50);
+
+  return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Reset flash continous read mode
+                                                                                *
+                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg) {
+  SF_Ctrl_Cmd_Cfg_Type flashCmd;
+
+  if (((uint32_t)&flashCmd) % 4 == 0) {
+    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
+  } else {
+    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
+  }
+
+  /* Reset continous read */
+  BL702_MemSet(&flashCmd.cmdBuf[0], flashCfg->resetCreadCmd, 4);
+  /* rwFlag don't care */
+  flashCmd.rwFlag   = SF_CTRL_READ;
+  flashCmd.addrSize = flashCfg->resetCreadCmdSize;
+  SF_Ctrl_SendCmd(&flashCmd);
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Set I/D bus read flash configuration in flash controller
+                                                                                *
+                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
+                                                                                * @param  ioMode: flash controller interface mode
+                                                                                * @param  contRead: Wether enable cont read mode
+                                                                                * @param  addr: address to read/write
+                                                                                * @param  len: data length to read/write
+                                                                                *
+                                                                                * @return SUCCESS or ERROR
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len) {
+  uint8_t              cmd, dummyClks;
+  SF_Ctrl_Cmd_Cfg_Type flashCmd;
+  uint8_t              cmdValid      = 1;
+  uint8_t              noReadModeCfg = 0;
+  uint8_t              cReadSupport  = 0;
+
+  if (((uint32_t)&flashCmd) % 4 == 0) {
+    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
+  } else {
+    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
+  }
+
+  SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB);
+
+  if (SF_CTRL_NIO_MODE == ioMode) {
+    cmd       = flashCfg->fastReadCmd;
+    dummyClks = flashCfg->frDmyClk;
+  } else if (SF_CTRL_DO_MODE == ioMode) {
+    flashCmd.dataMode = SF_CTRL_DATA_2_LINES;
+    cmd               = flashCfg->fastReadDoCmd;
+    dummyClks         = flashCfg->frDoDmyClk;
+  } else if (SF_CTRL_DIO_MODE == ioMode) {
+    flashCmd.addrMode = SF_CTRL_ADDR_2_LINES;
+    flashCmd.dataMode = SF_CTRL_DATA_2_LINES;
+    cmd               = flashCfg->fastReadDioCmd;
+    dummyClks         = flashCfg->frDioDmyClk;
+  } else if (SF_CTRL_QO_MODE == ioMode) {
+    flashCmd.dataMode = SF_CTRL_DATA_4_LINES;
+    cmd               = flashCfg->fastReadQoCmd;
+    dummyClks         = flashCfg->frQoDmyClk;
+  } else if (SF_CTRL_QIO_MODE == ioMode) {
+    flashCmd.addrMode = SF_CTRL_ADDR_4_LINES;
+    flashCmd.dataMode = SF_CTRL_DATA_4_LINES;
+    cmd               = flashCfg->fastReadQioCmd;
+    dummyClks         = flashCfg->frQioDmyClk;
+  } else {
+    return ERROR;
+  }
+
+  /*prepare command**/
+  flashCmd.rwFlag    = SF_CTRL_READ;
+  flashCmd.addrSize  = 3;
+  flashCmd.cmdBuf[0] = (cmd << 24) | addr;
+
+  if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) {
+    noReadModeCfg = flashCfg->cReadSupport & 0x02;
+    cReadSupport  = flashCfg->cReadSupport & 0x01;
+
+    if (noReadModeCfg == 0) {
+      /* Read mode must be set*/
+      if (cReadSupport == 0) {
+        /* Not support cont read,but we still need set read mode(winbond 80dv)*/
+        flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24);
+      } else {
+        /* Flash support cont read, setting depend on user parameter */
+        if (contRead) {
+          flashCmd.cmdBuf[0] = (addr << 8) | flashCfg->cReadMode;
+          cmdValid           = 0;
+        } else {
+          flashCmd.cmdBuf[1] = ((!flashCfg->cReadMode) << 24);
+        }
+      }
+
+      flashCmd.addrSize++;
+    }
+  }
+
+  flashCmd.dummyClks = dummyClks;
+  flashCmd.nbData    = len;
+  SF_Ctrl_Flash_Read_Icache_Set(&flashCmd, cmdValid);
+
+  return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Enable I/D bus read from flash
+                                                                                *
+                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
+                                                                                * @param  ioMode: flash controller interface mode
+                                                                                * @param  contRead: Wether enable cont read mode
+                                                                                *
+                                                                                * @return SUCCESS or ERROR
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead) {
+  BL_Err_Type stat;
+
+  stat = SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, 0, 4);
+
+  if (SUCCESS != stat) {
+    return stat;
+  }
+
+  return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Enable cache read from flash with cache
+                                                                                *
+                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
+                                                                                * @param  ioMode: flash controller interface mode
+                                                                                * @param  contRead: Wether enable cont read mode
+                                                                                * @param  wayDisable: cache way disable config
+                                                                                *
+                                                                                * @return SUCCESS or ERROR
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint8_t wayDisable) {
+  BL_Err_Type stat;
+
+  /* Cache now only support 32 bytes read */
+  stat = SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, 0, 32);
+
+  if (SUCCESS != stat) {
+    return stat;
+  }
+
+  return L1C_Cache_Enable_Set(wayDisable);
+}
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Disable read from flash with cache
+                                                                                *
+                                                                                * @param  None
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION SFlash_Cache_Read_Disable(void) { L1C_Cache_Read_Disable(); }
+#endif
+
+/****************************************************************************/ /**
+                                                                                * @brief  Read data from flash
+                                                                                *
+                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
+                                                                                * @param  ioMode: flash controller interface mode
+                                                                                * @param  contRead: Wether enable cont read mode
+                                                                                * @param  addr: flash read start address
+                                                                                * @param  data: data pointer to store data read from flash
+                                                                                * @param  len: data length to read
+                                                                                *
+                                                                                * @return None
+                                                                                *
+                                                                                *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len) {
+  uint8_t *const       flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
+  uint32_t             curLen, i;
+  uint8_t              cmd, dummyClks;
+  uint32_t             timeOut = 0;
+  SF_Ctrl_Cmd_Cfg_Type flashCmd;
+  uint8_t              noReadModeCfg = 0;
+  uint8_t              cReadSupport  = 0;
+
+  if (((uint32_t)&flashCmd) % 4 == 0) {
+    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
+  } else {
+    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
+  }
+
+  if (SF_CTRL_NIO_MODE == ioMode) {
+    cmd       = flashCfg->fastReadCmd;
+    dummyClks = flashCfg->frDmyClk;
+  } else if (SF_CTRL_DO_MODE == ioMode) {
+    flashCmd.dataMode = SF_CTRL_DATA_2_LINES;
+    cmd               = flashCfg->fastReadDoCmd;
+    dummyClks         = flashCfg->frDoDmyClk;
+  } else if (SF_CTRL_DIO_MODE == ioMode) {
+    flashCmd.addrMode = SF_CTRL_ADDR_2_LINES;
+    flashCmd.dataMode = SF_CTRL_DATA_2_LINES;
+    cmd               = flashCfg->fastReadDioCmd;
+    dummyClks         = flashCfg->frDioDmyClk;
+  } else if (SF_CTRL_QO_MODE == ioMode) {
+    flashCmd.dataMode = SF_CTRL_DATA_4_LINES;
+    cmd               = flashCfg->fastReadQoCmd;
+    dummyClks         = flashCfg->frQoDmyClk;
+  } else if (SF_CTRL_QIO_MODE == ioMode) {
+    flashCmd.addrMode = SF_CTRL_ADDR_4_LINES;
+    flashCmd.dataMode = SF_CTRL_DATA_4_LINES;
+    cmd               = flashCfg->fastReadQioCmd;
+    dummyClks         = flashCfg->frQioDmyClk;
+  } else {
+    return ERROR;
+  }
+
+  /* Prepare command */
+  flashCmd.rwFlag   = SF_CTRL_READ;
+  flashCmd.addrSize = 3;
+
+  if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) {
+    noReadModeCfg = flashCfg->cReadSupport & 0x02;
+    cReadSupport  = flashCfg->cReadSupport & 0x01;
+
+    if (noReadModeCfg == 0) {
+      /* Read mode must be set*/
+      if (cReadSupport == 0) {
+        /* Not support cont read,but we still need set read mode(winbond 80dv)*/
+        flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24);
+      } else {
+        /* Flash support cont read, setting depend on user parameter */
+        if (contRead) {
+          flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24);
+        } else {
+          flashCmd.cmdBuf[1] = ((!flashCfg->cReadMode) << 24);
+        }
+      }
+
+      flashCmd.addrSize++;
+    }
+  }
+
+  flashCmd.dummyClks = dummyClks;
+
+  /* Read data */
+  for (i = 0; i < len;) {
+    /* Prepare command */
+    flashCmd.cmdBuf[0] = (cmd << 24) | (addr);
+    curLen             = len - i;
+
+    if (curLen >= FLASH_CTRL_BUF_SIZE) {
+      curLen          = FLASH_CTRL_BUF_SIZE;
+      flashCmd.nbData = curLen;
+    } else {
+      /* Make sf_ctrl word read */
+      flashCmd.nbData = ((curLen + 3) >> 2) << 2;
+    }
+
+    SF_Ctrl_SendCmd(&flashCmd);
+
+    timeOut = SFCTRL_BUSY_STATE_TIMEOUT;
+
+    while (SET == SF_Ctrl_GetBusyState()) {
+      timeOut--;
+
+      if (timeOut == 0) {
+        return TIMEOUT;
+      }
+    }
+
+    BL702_MemCpy_Fast(data, flashCtrlBuf, curLen);
+
+    addr += curLen;
+    i += curLen;
+    data += curLen;
+  }
+
+  return SUCCESS;
+}
+#endif
+
+/*@} end of group SFLASH_Public_Functions */
+
+/*@} end of group SFLASH */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sflash_ext.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sflash_ext.c
new file mode 100644
index 00000000..fba50951
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sflash_ext.c
@@ -0,0 +1,274 @@
+/**
+  ******************************************************************************
+  * @file    bl702_sflash_ext.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_sflash_ext.h"
+#include "bl702_sf_ctrl.h"
+#include "l1c_reg.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SFLASH_EXT
+ *  @{
+ */
+
+/** @defgroup  SFLASH_EXT_Private_Macros
+ *  @{
+ */
+
+/*@} end of group SFLASH_EXT_Private_Macros */
+
+/** @defgroup  SFLASH_EXT_Private_Types
+ *  @{
+ */
+
+/*@} end of group SFLASH_EXT_Private_Types */
+
+/** @defgroup  SFLASH_EXT_Private_Variables
+ *  @{
+ */
+
+/*@} end of group SFLASH_EXT_Private_Variables */
+
+/** @defgroup  SFLASH_EXT_Global_Variables
+ *  @{
+ */
+
+/*@} end of group SFLASH_EXT_Global_Variables */
+
+/** @defgroup  SFLASH_EXT_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group SFLASH_EXT_Private_Fun_Declaration */
+
+/** @defgroup  SFLASH_EXT_Private_Functions
+ *  @{
+ */
+
+/*@} end of group SFLASH_EXT_Private_Functions */
+
+/** @defgroup  SFLASH_EXT_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  KH25V40 flash write protect set
+ *
+ * @param  flashCfg: Serial flash parameter configuration pointer
+ * @param  protect: protect area
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION SFlash_KH25V40_Write_Protect(SPI_Flash_Cfg_Type *flashCfg, SFlash_Protect_Kh25v40_Type protect)
+{
+    uint32_t stat = 0, ret;
+
+    SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&stat, 1);
+    if (((stat >> 2) & 0xf) == protect) {
+        return SUCCESS;
+    }
+
+    stat |= ((protect << 2) & 0xff);
+
+    ret = SFlash_Write_Enable(flashCfg);
+    if (SUCCESS != ret) {
+        return ERROR;
+    }
+
+    SFlash_Write_Reg(flashCfg, 0, (uint8_t *)&stat, 1);
+    SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&stat, 1);
+    if (((stat >> 2) & 0xf) == protect) {
+        return SUCCESS;
+    }
+
+    return ERROR;
+}
+
+/****************************************************************************/ /**
+ * @brief  Read flash register with read command
+ *
+ * @param  flashCfg: Serial flash parameter configuration pointer
+ * @param  readRegCmd: read command
+ * @param  regValue: register value pointer to store data
+ * @param  regLen: register value length
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen)
+{
+    uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
+    SF_Ctrl_Cmd_Cfg_Type flashCmd;
+    uint32_t cnt = 0;
+
+    if (((uint32_t)&flashCmd) % 4 == 0) {
+        BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
+    } else {
+        BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
+    }
+
+    flashCmd.cmdBuf[0] = readRegCmd << 24;
+    flashCmd.rwFlag = SF_CTRL_READ;
+    flashCmd.nbData = regLen;
+
+    SF_Ctrl_SendCmd(&flashCmd);
+
+    while (SET == SF_Ctrl_GetBusyState()) {
+        BL702_Delay_US(1);
+        cnt++;
+
+        if (cnt > 1000) {
+            return ERROR;
+        }
+    }
+
+    BL702_MemCpy(regValue, flashCtrlBuf, regLen);
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Write flash register with write command
+ *
+ * @param  flashCfg: Serial flash parameter configuration pointer
+ * @param  writeRegCmd: write command
+ * @param  regValue: register value pointer storing data
+ * @param  regLen: register value length
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen)
+{
+    uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
+    uint32_t cnt = 0;
+    SF_Ctrl_Cmd_Cfg_Type flashCmd;
+
+    if (((uint32_t)&flashCmd) % 4 == 0) {
+        BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
+    } else {
+        BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
+    }
+
+    BL702_MemCpy(flashCtrlBuf, regValue, regLen);
+
+    flashCmd.cmdBuf[0] = writeRegCmd << 24;
+    flashCmd.rwFlag = SF_CTRL_WRITE;
+    flashCmd.nbData = regLen;
+
+    SF_Ctrl_SendCmd(&flashCmd);
+
+    /* take 40ms for tw(write status register) as default */
+    while (SET == SFlash_Busy(flashCfg)) {
+        BL702_Delay_US(100);
+        cnt++;
+
+        if (cnt > 400) {
+            return ERROR;
+        }
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************//**
+ * @brief  Clear flash status register
+ *
+ * @param  pFlashCfg: Flash configuration pointer
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION SFlash_Clear_Status_Register(SPI_Flash_Cfg_Type *pFlashCfg)
+{
+    uint32_t ret = 0;
+    uint32_t qeValue = 0;
+    uint32_t regValue = 0;
+    uint32_t readValue = 0;
+    uint8_t readRegValue0 = 0;
+    uint8_t readRegValue1 = 0;
+
+    if((pFlashCfg->ioMode&0xf)==SF_CTRL_QO_MODE || (pFlashCfg->ioMode&0xf)==SF_CTRL_QIO_MODE){
+        qeValue = 1;
+    }
+
+    SFlash_Read_Reg(pFlashCfg, 0, (uint8_t *)&readRegValue0, 1);
+    SFlash_Read_Reg(pFlashCfg, 1, (uint8_t *)&readRegValue1, 1);
+    readValue = (readRegValue0|(readRegValue1<<8));
+    if ((readValue & (~((1<<(pFlashCfg->qeIndex*8+pFlashCfg->qeBit)) |
+                        (1<<(pFlashCfg->busyIndex*8+pFlashCfg->busyBit)) |
+                        (1<<(pFlashCfg->wrEnableIndex*8+pFlashCfg->wrEnableBit))))) == 0){
+        return SUCCESS;
+    }
+
+    ret = SFlash_Write_Enable(pFlashCfg);
+    if (SUCCESS != ret) {
+        return ERROR;
+    }
+    if (pFlashCfg->qeWriteRegLen == 2) {
+        regValue = (qeValue<<(pFlashCfg->qeIndex*8+pFlashCfg->qeBit));
+        SFlash_Write_Reg(pFlashCfg, 0, (uint8_t *)®Value, 2);
+    } else {
+        if (pFlashCfg->qeIndex == 0) {
+            regValue = (qeValue<qeBit);
+        } else {
+            regValue = 0;
+        }
+        SFlash_Write_Reg(pFlashCfg, 0, (uint8_t *)®Value, 1);
+        ret = SFlash_Write_Enable(pFlashCfg);
+        if (SUCCESS != ret) {
+            return ERROR;
+        }
+        if (pFlashCfg->qeIndex == 1) {
+            regValue = (qeValue<qeBit);
+        } else {
+            regValue = 0;
+        }
+        SFlash_Write_Reg(pFlashCfg, 1, (uint8_t *)®Value, 1);
+    }
+    return SUCCESS;
+}
+
+/*@} end of group SFLASH_EXT_Public_Functions */
+
+/*@} end of group SFLASH_EXT */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_spi.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_spi.c
new file mode 100644
index 00000000..f831aaed
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_spi.c
@@ -0,0 +1,1811 @@
+/**
+  ******************************************************************************
+  * @file    bl702_spi.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_spi.h"
+#include "bl702_glb.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SPI
+ *  @{
+ */
+
+/** @defgroup  SPI_Private_Macros
+ *  @{
+ */
+#define SPI_TX_TIMEOUT_COUNT (160 * 1000)
+#define SPI_RX_TIMEOUT_COUNT (160 * 1000)
+
+/*@} end of group SPI_Private_Macros */
+
+/** @defgroup  SPI_Private_Types
+ *  @{
+ */
+
+/*@} end of group SPI_Private_Types */
+
+/** @defgroup  SPI_Private_Variables
+ *  @{
+ */
+static const uint32_t spiAddr[SPI_ID_MAX] = { SPI_BASE };
+static intCallback_Type *spiIntCbfArra[SPI_ID_MAX][SPI_INT_ALL] = {
+    { NULL }
+};
+
+/*@} end of group SPI_Private_Variables */
+
+/** @defgroup  SPI_Global_Variables
+ *  @{
+ */
+
+/*@} end of group SPI_Global_Variables */
+
+/** @defgroup  SPI_Private_Fun_Declaration
+ *  @{
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+static void SPI_IntHandler(SPI_ID_Type spiNo);
+#endif
+
+/*@} end of group SPI_Private_Fun_Declaration */
+
+/** @defgroup  SPI_Private_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  SPI interrupt common handler function
+ *
+ * @param  spiNo: SPI ID type
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+static void SPI_IntHandler(SPI_ID_Type spiNo)
+{
+    uint32_t tmpVal;
+    uint32_t SPIx = spiAddr[spiNo];
+
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+
+    tmpVal = BL_RD_REG(SPIx, SPI_INT_STS);
+
+    /* Transfer end interrupt,shared by both master and slave mode */
+    if (BL_IS_REG_BIT_SET(tmpVal, SPI_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_END_MASK)) {
+        BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_END_CLR));
+
+        if (spiIntCbfArra[spiNo][SPI_INT_END] != NULL) {
+            spiIntCbfArra[spiNo][SPI_INT_END]();
+        }
+    }
+
+    /* TX fifo ready interrupt(fifo count > fifo threshold) */
+    if (BL_IS_REG_BIT_SET(tmpVal, SPI_TXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_TXF_MASK)) {
+        if (spiIntCbfArra[spiNo][SPI_INT_TX_FIFO_REQ] != NULL) {
+            spiIntCbfArra[spiNo][SPI_INT_TX_FIFO_REQ]();
+        }
+    }
+
+    /*  RX fifo ready interrupt(fifo count > fifo threshold) */
+    if (BL_IS_REG_BIT_SET(tmpVal, SPI_RXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_RXF_MASK)) {
+        if (spiIntCbfArra[spiNo][SPI_INT_RX_FIFO_REQ] != NULL) {
+            spiIntCbfArra[spiNo][SPI_INT_RX_FIFO_REQ]();
+        }
+    }
+
+    /* Slave mode transfer time-out interrupt,triggered when bus is idle for the given value */
+    if (BL_IS_REG_BIT_SET(tmpVal, SPI_STO_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_STO_MASK)) {
+        BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_STO_CLR));
+
+        if (spiIntCbfArra[spiNo][SPI_INT_SLAVE_TIMEOUT] != NULL) {
+            spiIntCbfArra[spiNo][SPI_INT_SLAVE_TIMEOUT]();
+        }
+    }
+
+    /* Slave mode tx underrun error interrupt,trigged when tx is not ready during transfer */
+    if (BL_IS_REG_BIT_SET(tmpVal, SPI_TXU_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_TXU_MASK)) {
+        BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_TXU_CLR));
+
+        if (spiIntCbfArra[spiNo][SPI_INT_SLAVE_UNDERRUN] != NULL) {
+            spiIntCbfArra[spiNo][SPI_INT_SLAVE_UNDERRUN]();
+        }
+    }
+
+    /* TX/RX fifo overflow/underflow interrupt */
+    if (BL_IS_REG_BIT_SET(tmpVal, SPI_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_FER_MASK)) {
+        if (spiIntCbfArra[spiNo][SPI_INT_FIFO_ERROR] != NULL) {
+            spiIntCbfArra[spiNo][SPI_INT_FIFO_ERROR]();
+        }
+    }
+}
+#endif
+
+/*@} end of group SPI_Private_Functions */
+
+/** @defgroup  SPI_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  SPI initialization function
+ *
+ * @param  spiNo: SPI ID type
+ * @param  spiCfg: SPI configuration structure pointer
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_Init(SPI_ID_Type spiNo, SPI_CFG_Type *spiCfg)
+{
+    uint32_t tmpVal;
+    uint32_t SPIx = spiAddr[spiNo];
+
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+    CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(spiCfg->mod));
+    CHECK_PARAM(IS_SPI_BYTE_INVERSE_TYPE(spiCfg->byteSequence));
+    CHECK_PARAM(IS_SPI_BIT_INVERSE_TYPE(spiCfg->bitSequence));
+    CHECK_PARAM(IS_SPI_CLK_PHASE_INVERSE_TYPE(spiCfg->clkPhaseInv));
+    CHECK_PARAM(IS_SPI_CLK_POLARITY_TYPE(spiCfg->clkPolarity));
+
+    /* Disable clock gate */
+    GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_SPI);
+
+    /* spi config */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_DEG_EN, spiCfg->deglitchEnable);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_M_CONT_EN, spiCfg->continuousEnable);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_BYTE_INV, spiCfg->byteSequence);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_BIT_INV, spiCfg->bitSequence);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_SCLK_PH, (spiCfg->clkPhaseInv + 1) & 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_SCLK_POL, spiCfg->clkPolarity);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, spiCfg->frameSize);
+    BL_WR_REG(SPIx, SPI_CONFIG, tmpVal);
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(SPI_IRQn, SPI_IRQHandler);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SPI set default value of all registers function
+ *
+ * @param  spiNo: SPI ID type
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_DeInit(SPI_ID_Type spiNo)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+
+    if (SPI_ID_0 == spiNo) {
+        GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_SPI);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Length of data phase1/0,start/stop condition and interval between frame initialization
+ *         function
+ *
+ * @param  spiNo: SPI ID type
+ * @param  clockCfg: Clock configuration structure pointer
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_ClockConfig(SPI_ID_Type spiNo, SPI_ClockCfg_Type *clockCfg)
+{
+    uint32_t tmpVal;
+    uint32_t SPIx = spiAddr[spiNo];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+
+    /* Configure length of data phase1/0 and start/stop condition */
+    tmpVal = BL_RD_REG(SPIx, SPI_PRD_0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_S, clockCfg->startLen - 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_P, clockCfg->stopLen - 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_0, clockCfg->dataPhase0Len - 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_1, clockCfg->dataPhase1Len - 1);
+    BL_WR_REG(SPIx, SPI_PRD_0, tmpVal);
+
+    /* Configure length of interval between frame */
+    tmpVal = BL_RD_REG(SPIx, SPI_PRD_1);
+    BL_WR_REG(SPIx, SPI_PRD_1, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_I, clockCfg->intervalLen - 1));
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SPI configure fifo function
+ *
+ * @param  spiNo: SPI ID type
+ * @param  fifoCfg: FIFO configuration structure pointer
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_FifoConfig(SPI_ID_Type spiNo, SPI_FifoCfg_Type *fifoCfg)
+{
+    uint32_t tmpVal;
+    uint32_t SPIx = spiAddr[spiNo];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+
+    /* Set fifo threshold value */
+    tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_TX_FIFO_TH, fifoCfg->txFifoThreshold);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_RX_FIFO_TH, fifoCfg->rxFifoThreshold);
+    BL_WR_REG(SPIx, SPI_FIFO_CONFIG_1, tmpVal);
+
+    /* Enable or disable dma function */
+    tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_DMA_TX_EN, fifoCfg->txFifoDmaEnable);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_DMA_RX_EN, fifoCfg->rxFifoDmaEnable);
+    BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set SPI SCK Clcok
+ *
+ * @param  spiNo: SPI ID type
+ * @param  clk: Clk
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_SetClock(SPI_ID_Type spiNo, uint32_t clk)
+{
+    uint32_t glb_div = 1, spi_div = 1;
+    uint32_t tmpVal;
+    uint32_t SPIx = spiAddr[spiNo];
+
+    if(clk > 36000000) {
+        clk = 36000000;
+        glb_div = 1;
+        spi_div = 1;
+    } else if(clk > 140625) {
+        glb_div = 1;
+        spi_div = 36000000 / clk;
+    } else if(clk > 70312) {
+        glb_div = 2;
+        spi_div = 18000000 / clk;
+    } else if(clk > 35156) {
+        glb_div = 4;
+        spi_div = 9000000 / clk;
+    } else if(clk > 4394) {
+        glb_div = 32;
+        spi_div = 1125000 / clk;
+    } else {
+        glb_div = 32;
+        spi_div = 256;
+    }
+
+    /* Configure length of data phase1/0 and start/stop condition */
+    tmpVal = BL_RD_REG(SPIx, SPI_PRD_0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_S, spi_div - 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_P, spi_div - 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_0, spi_div - 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_1, spi_div - 1);
+    BL_WR_REG(SPIx, SPI_PRD_0, tmpVal);
+
+    tmpVal = BL_RD_REG(SPIx, SPI_PRD_1);
+    BL_WR_REG(SPIx, SPI_PRD_1, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_I, spi_div - 1));
+
+    GLB_Set_SPI_CLK(ENABLE, glb_div - 1);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable spi transfer
+ *
+ * @param  spiNo: SPI ID type
+ * @param  modeType: Master or slave mode select
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_Enable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType)
+{
+    uint32_t tmpVal;
+    uint32_t SPIx = spiAddr[spiNo];
+
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+    CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(modeType));
+
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+
+    if (modeType != SPI_WORK_MODE_SLAVE) {
+        /* master mode */
+        tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_S_EN);
+        tmpVal = BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_M_EN);
+    } else {
+        /* slave mode */
+        tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_M_EN);
+        tmpVal = BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_S_EN);
+    }
+
+    BL_WR_REG(SPIx, SPI_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable spi transfer
+ *
+ * @param  spiNo: SPI ID type
+ * @param  modeType: Master or slave mode select
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_Disable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType)
+{
+    uint32_t tmpVal;
+    uint32_t SPIx = spiAddr[spiNo];
+
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+    CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(modeType));
+
+    /* close master and slave */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_M_EN);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_S_EN);
+    BL_WR_REG(SPIx, SPI_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set time-out value to trigger interrupt when spi bus is idle for the given value
+ *
+ * @param  spiNo: SPI ID type
+ * @param  value: Time value
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_SetTimeOutValue(SPI_ID_Type spiNo, uint16_t value)
+{
+    uint32_t tmpVal;
+    uint32_t SPIx = spiAddr[spiNo];
+
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+
+    /* Set time-out value */
+    tmpVal = BL_RD_REG(SPIx, SPI_STO_VALUE);
+    BL_WR_REG(SPIx, SPI_STO_VALUE, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_STO_VALUE, value - 1));
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set de-glitch function cycle count value
+ *
+ * @param  spiNo: SPI ID type
+ * @param  cnt: De-glitch function cycle count
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_SetDeglitchCount(SPI_ID_Type spiNo, uint8_t cnt)
+{
+    uint32_t tmpVal;
+    uint32_t SPIx = spiAddr[spiNo];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+
+    /* Set count value */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_DEG_CNT, cnt);
+    BL_WR_REG(SPIx, SPI_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable rx data ignore function and set start/stop point
+ *
+ * @param  spiNo: SPI ID type
+ * @param  startPoint: Start point
+ * @param  stopPoint: Stop point
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_RxIgnoreEnable(SPI_ID_Type spiNo, uint8_t startPoint, uint8_t stopPoint)
+{
+    uint32_t tmpVal;
+    uint32_t SPIx = spiAddr[spiNo];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+
+    /* Enable rx ignore function */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));
+
+    /* Set start and stop point */
+    tmpVal = startPoint << SPI_CR_SPI_RXD_IGNR_S_POS | stopPoint;
+    BL_WR_REG(SPIx, SPI_RXD_IGNR, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable rx data ignore function
+ *
+ * @param  spiNo: SPI ID type
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_RxIgnoreDisable(SPI_ID_Type spiNo)
+{
+    uint32_t tmpVal;
+    uint32_t SPIx = spiAddr[spiNo];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+
+    /* Disable rx ignore function */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Clear tx fifo and tx fifo overflow/underflow status
+ *
+ * @param  spiNo: SPI ID type
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_ClrTxFifo(SPI_ID_Type spiNo)
+{
+    uint32_t tmpVal;
+    uint32_t SPIx = spiAddr[spiNo];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+
+    /* Clear tx fifo */
+    tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
+    BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR));
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Clear rx fifo and rx fifo overflow/underflow status
+ *
+ * @param  spiNo: SPI ID type
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_ClrRxFifo(SPI_ID_Type spiNo)
+{
+    uint32_t tmpVal;
+    uint32_t SPIx = spiAddr[spiNo];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+
+    /* Clear rx fifo */
+    tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
+    BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR));
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Clear spi interrupt status
+ *
+ * @param  spiNo: SPI ID type
+ * @param  intType: SPI interrupt type
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_ClrIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType)
+{
+    uint32_t tmpVal;
+    uint32_t SPIx = spiAddr[spiNo];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+
+    /* Clear certain or all interrupt */
+    tmpVal = BL_RD_REG(SPIx, SPI_INT_STS);
+
+    if (SPI_INT_ALL == intType) {
+        tmpVal |= 0x1f << SPI_CR_SPI_END_CLR_POS;
+    } else {
+        tmpVal |= 1 << (intType + SPI_CR_SPI_END_CLR_POS);
+    }
+
+    BL_WR_REG(SPIx, SPI_INT_STS, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SPI mask or unmask certain or all interrupt
+ *
+ * @param  spiNo: SPI ID type
+ * @param  intType: SPI interrupt type
+ * @param  intMask: SPI interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt )
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_IntMask(SPI_ID_Type spiNo, SPI_INT_Type intType, BL_Mask_Type intMask)
+{
+    uint32_t tmpVal;
+    uint32_t SPIx = spiAddr[spiNo];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+    CHECK_PARAM(IS_SPI_INT_TYPE(intType));
+    CHECK_PARAM(IS_BL_MASK_TYPE(intMask));
+
+    tmpVal = BL_RD_REG(SPIx, SPI_INT_STS);
+
+    /* Mask or unmask certain or all interrupt */
+    if (SPI_INT_ALL == intType) {
+        if (MASK == intMask) {
+            tmpVal |= 0x3f << SPI_CR_SPI_END_MASK_POS;
+        } else {
+            tmpVal &= ~(0x3f << SPI_CR_SPI_END_MASK_POS);
+        }
+    } else {
+        if (MASK == intMask) {
+            tmpVal |= 1 << (intType + SPI_CR_SPI_END_MASK_POS);
+        } else {
+            tmpVal &= ~(1 << (intType + SPI_CR_SPI_END_MASK_POS));
+        }
+    }
+
+    /* Write back */
+    BL_WR_REG(SPIx, SPI_INT_STS, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Install spi interrupt callback function
+ *
+ * @param  spiNo: SPI ID type
+ * @param  intType: SPI interrupt type
+ * @param  cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_Int_Callback_Install(SPI_ID_Type spiNo, SPI_INT_Type intType, intCallback_Type *cbFun)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+    CHECK_PARAM(IS_SPI_INT_TYPE(intType));
+
+    spiIntCbfArra[spiNo][intType] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SPI write data to tx fifo
+ *
+ * @param  spiNo: SPI ID type
+ * @param  data: Data to write
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_SendData(SPI_ID_Type spiNo, uint32_t data)
+{
+    uint32_t SPIx = spiAddr[spiNo];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+
+    /* Write tx fifo */
+    BL_WR_REG(SPIx, SPI_FIFO_WDATA, data);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SPI send 8-bit datas
+ *
+ * @param  spiNo: SPI ID type
+ * @param  buff: Buffer of datas
+ * @param  length: Length of buffer
+ * @param  timeoutType: Enable or disable timeout judgment
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_Send_8bits(SPI_ID_Type spiNo, uint8_t *buff, uint32_t length, SPI_Timeout_Type timeoutType)
+{
+    uint32_t tmpVal;
+    uint32_t txLen = 0;
+    uint32_t rData;
+    uint32_t SPIx = spiAddr[spiNo];
+    uint32_t timeoutCnt = SPI_TX_TIMEOUT_COUNT;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+    CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));
+
+    /* Set valid width for each fifo entry */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 0));
+
+    /* Disable rx ignore */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));
+
+    /* Clear tx and rx fifo */
+    tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR);
+    BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);
+
+    /* Fill tx fifo */
+    tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;
+
+    for (txLen = 0; txLen < tmpVal; txLen++) {
+        BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)buff[txLen]);
+    }
+
+    /* Wait receive data and send the rest of the data */
+    for (; txLen < length; txLen++) {
+        timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+        while (SPI_GetRxFifoCount(spiNo) == 0) {
+            if (timeoutType) {
+                timeoutCnt--;
+
+                if (timeoutCnt == 0) {
+                    return TIMEOUT;
+                }
+            }
+        }
+
+        rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA);
+        BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)buff[txLen]);
+    }
+
+    /* Wait receive the rest of the data */
+    for (txLen = 0; txLen < tmpVal; txLen++) {
+        timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+        while (SPI_GetRxFifoCount(spiNo) == 0) {
+            if (timeoutType) {
+                timeoutCnt--;
+
+                if (timeoutCnt == 0) {
+                    return TIMEOUT;
+                }
+            }
+        }
+
+        rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SPI send 16-bit datas
+ *
+ * @param  spiNo: SPI ID type
+ * @param  buff: Buffer of datas
+ * @param  length: Length of buffer
+ * @param  timeoutType: Enable or disable timeout judgment
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_Send_16bits(SPI_ID_Type spiNo, uint16_t *buff, uint32_t length, SPI_Timeout_Type timeoutType)
+{
+    uint32_t tmpVal;
+    uint32_t txLen = 0;
+    uint32_t rData;
+    uint32_t SPIx = spiAddr[spiNo];
+    uint32_t timeoutCnt = SPI_TX_TIMEOUT_COUNT;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+    CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));
+
+    /* Set valid width for each fifo entry */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 1));
+
+    /* Disable rx ignore */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));
+
+    /* Clear tx and rx fifo */
+    tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR);
+    BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);
+
+    /* Fill tx fifo */
+    tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;
+
+    for (txLen = 0; txLen < tmpVal; txLen++) {
+        BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)buff[txLen]);
+    }
+
+    /* Wait receive data and send the rest of the data */
+    for (; txLen < length; txLen++) {
+        timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+        while (SPI_GetRxFifoCount(spiNo) == 0) {
+            if (timeoutType) {
+                timeoutCnt--;
+
+                if (timeoutCnt == 0) {
+                    return TIMEOUT;
+                }
+            }
+        }
+
+        rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA);
+        BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)buff[txLen]);
+    }
+
+    /* Wait receive the rest of the data */
+    for (txLen = 0; txLen < tmpVal; txLen++) {
+        timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+        while (SPI_GetRxFifoCount(spiNo) == 0) {
+            if (timeoutType) {
+                timeoutCnt--;
+
+                if (timeoutCnt == 0) {
+                    return TIMEOUT;
+                }
+            }
+        }
+
+        rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SPI send 24-bit datas
+ *
+ * @param  spiNo: SPI ID type
+ * @param  buff: Buffer of datas
+ * @param  length: Length of buffer
+ * @param  timeoutType: Enable or disable timeout judgment
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_Send_24bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType)
+{
+    uint32_t tmpVal;
+    uint32_t txLen = 0;
+    uint32_t rData;
+    uint32_t SPIx = spiAddr[spiNo];
+    uint32_t timeoutCnt = SPI_TX_TIMEOUT_COUNT;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+    CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));
+
+    /* Set valid width for each fifo entry */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 2));
+
+    /* Disable rx ignore */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));
+
+    /* Clear tx and rx fifo */
+    tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR);
+    BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);
+
+    /* Fill tx fifo */
+    tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;
+
+    for (txLen = 0; txLen < tmpVal; txLen++) {
+        BL_WR_REG(SPIx, SPI_FIFO_WDATA, buff[txLen]);
+    }
+
+    /* Wait receive data and send the rest of the data */
+    for (; txLen < length; txLen++) {
+        timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+        while (SPI_GetRxFifoCount(spiNo) == 0) {
+            if (timeoutType) {
+                timeoutCnt--;
+
+                if (timeoutCnt == 0) {
+                    return TIMEOUT;
+                }
+            }
+        }
+
+        rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA);
+        BL_WR_REG(SPIx, SPI_FIFO_WDATA, buff[txLen]);
+    }
+
+    /* Wait receive the rest of the data */
+    for (txLen = 0; txLen < tmpVal; txLen++) {
+        timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+        while (SPI_GetRxFifoCount(spiNo) == 0) {
+            if (timeoutType) {
+                timeoutCnt--;
+
+                if (timeoutCnt == 0) {
+                    return TIMEOUT;
+                }
+            }
+        }
+
+        rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SPI send 32-bit datas
+ *
+ * @param  spiNo: SPI ID type
+ * @param  buff: Buffer of datas
+ * @param  length: Length of buffer
+ * @param  timeoutType: Enable or disable timeout judgment
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_Send_32bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType)
+{
+    uint32_t tmpVal;
+    uint32_t txLen = 0;
+    uint32_t rData;
+    uint32_t SPIx = spiAddr[spiNo];
+    uint32_t timeoutCnt = SPI_TX_TIMEOUT_COUNT;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+    CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));
+
+    /* Set valid width for each fifo entry */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 3));
+
+    /* Disable rx ignore */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));
+
+    /* Clear tx and rx fifo */
+    tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR);
+    BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);
+
+    /* Fill tx fifo */
+    tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;
+
+    for (txLen = 0; txLen < tmpVal; txLen++) {
+        BL_WR_REG(SPIx, SPI_FIFO_WDATA, buff[txLen]);
+    }
+
+    /* Wait receive data and send the rest of the data */
+    for (; txLen < length; txLen++) {
+        timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+        while (SPI_GetRxFifoCount(spiNo) == 0) {
+            if (timeoutType) {
+                timeoutCnt--;
+
+                if (timeoutCnt == 0) {
+                    return TIMEOUT;
+                }
+            }
+        }
+
+        rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA);
+        BL_WR_REG(SPIx, SPI_FIFO_WDATA, buff[txLen]);
+    }
+
+    /* Wait receive the rest of the data */
+    for (txLen = 0; txLen < tmpVal; txLen++) {
+        timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+        while (SPI_GetRxFifoCount(spiNo) == 0) {
+            if (timeoutType) {
+                timeoutCnt--;
+
+                if (timeoutCnt == 0) {
+                    return TIMEOUT;
+                }
+            }
+        }
+
+        rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SPI receive 8-bit datas
+ *
+ * @param  spiNo: SPI ID type
+ * @param  buff: Buffer of datas
+ * @param  length: Length of buffer
+ * @param  timeoutType: Enable or disable timeout judgment
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_Recv_8bits(SPI_ID_Type spiNo, uint8_t *buff, uint32_t length, SPI_Timeout_Type timeoutType)
+{
+    uint32_t tmpVal;
+    uint32_t rxLen = 0;
+    uint32_t SPIx = spiAddr[spiNo];
+    uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+    CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));
+
+    /* Set valid width for each fifo entry */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 0));
+
+    /* Disable rx ignore */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));
+
+    /* Clear tx and rx fifo */
+    tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR);
+    BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);
+
+    /* Fill tx fifo with 0 */
+    tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;
+
+    for (rxLen = 0; rxLen < tmpVal; rxLen++) {
+        BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0);
+    }
+
+    /* Wait receive data and send the rest of the data 0 */
+    for (rxLen = 0; rxLen < length - tmpVal; rxLen++) {
+        timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+        while (SPI_GetRxFifoCount(spiNo) == 0) {
+            if (timeoutType) {
+                timeoutCnt--;
+
+                if (timeoutCnt == 0) {
+                    return TIMEOUT;
+                }
+            }
+        }
+
+        buff[rxLen] = (uint8_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xff);
+        BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0);
+    }
+
+    /* Wait receive the rest of the data */
+    for (; rxLen < length; rxLen++) {
+        timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+        while (SPI_GetRxFifoCount(spiNo) == 0) {
+            if (timeoutType) {
+                timeoutCnt--;
+
+                if (timeoutCnt == 0) {
+                    return TIMEOUT;
+                }
+            }
+        }
+
+        buff[rxLen] = (uint8_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xff);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SPI receive 16-bit datas
+ *
+ * @param  spiNo: SPI ID type
+ * @param  buff: Buffer of datas
+ * @param  length: Length of buffer
+ * @param  timeoutType: Enable or disable timeout judgment
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_Recv_16bits(SPI_ID_Type spiNo, uint16_t *buff, uint32_t length, SPI_Timeout_Type timeoutType)
+{
+    uint32_t tmpVal;
+    uint32_t rxLen = 0;
+    uint32_t SPIx = spiAddr[spiNo];
+    uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+    CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));
+
+    /* Set valid width for each fifo entry */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 1));
+
+    /* Disable rx ignore */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));
+
+    /* Clear tx and rx fifo */
+    tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR);
+    BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);
+
+    /* Fill tx fifo with 0 */
+    tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;
+
+    for (rxLen = 0; rxLen < tmpVal; rxLen++) {
+        BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0);
+    }
+
+    /* Wait receive data and send the rest of the data 0 */
+    for (rxLen = 0; rxLen < length - tmpVal; rxLen++) {
+        timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+        while (SPI_GetRxFifoCount(spiNo) == 0) {
+            if (timeoutType) {
+                timeoutCnt--;
+
+                if (timeoutCnt == 0) {
+                    return TIMEOUT;
+                }
+            }
+        }
+
+        buff[rxLen++] = (uint16_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffff);
+        BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0);
+    }
+
+    /* Wait receive the rest of the data */
+    for (; rxLen < length; rxLen++) {
+        timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+        while (SPI_GetRxFifoCount(spiNo) == 0) {
+            if (timeoutType) {
+                timeoutCnt--;
+
+                if (timeoutCnt == 0) {
+                    return TIMEOUT;
+                }
+            }
+        }
+
+        buff[rxLen++] = (uint16_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffff);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SPI receive 24-bit datas
+ *
+ * @param  spiNo: SPI ID type
+ * @param  buff: Buffer of datas
+ * @param  length: Length of buffer
+ * @param  timeoutType: Enable or disable timeout judgment
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_Recv_24bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType)
+{
+    uint32_t tmpVal;
+    uint32_t rxLen = 0;
+    uint32_t SPIx = spiAddr[spiNo];
+    uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+    CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));
+
+    /* Set valid width for each fifo entry */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 2));
+
+    /* Disable rx ignore */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));
+
+    /* Clear tx and rx fifo */
+    tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR);
+    BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);
+
+    /* Fill tx fifo with 0 */
+    tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;
+
+    for (rxLen = 0; rxLen < tmpVal; rxLen++) {
+        BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0);
+    }
+
+    /* Wait receive data and send the rest of the data 0 */
+    for (rxLen = 0; rxLen < length - tmpVal; rxLen++) {
+        timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+        while (SPI_GetRxFifoCount(spiNo) == 0) {
+            if (timeoutType) {
+                timeoutCnt--;
+
+                if (timeoutCnt == 0) {
+                    return TIMEOUT;
+                }
+            }
+        }
+
+        buff[rxLen++] = BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffffff;
+        BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0);
+    }
+
+    /* Wait receive the rest of the data */
+    for (; rxLen < length; rxLen++) {
+        timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+        while (SPI_GetRxFifoCount(spiNo) == 0) {
+            if (timeoutType) {
+                timeoutCnt--;
+
+                if (timeoutCnt == 0) {
+                    return TIMEOUT;
+                }
+            }
+        }
+
+        buff[rxLen++] = BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffffff;
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SPI receive 32-bit datas
+ *
+ * @param  spiNo: SPI ID type
+ * @param  buff: Buffer of datas
+ * @param  length: Length of buffer
+ * @param  timeoutType: Enable or disable timeout judgment
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_Recv_32bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType)
+{
+    uint32_t tmpVal;
+    uint32_t rxLen = 0;
+    uint32_t SPIx = spiAddr[spiNo];
+    uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+    CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));
+
+    /* Set valid width for each fifo entry */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 3));
+
+    /* Disable rx ignore */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));
+
+    /* Clear tx and rx fifo */
+    tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR);
+    BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);
+
+    /* Fill tx fifo with 0 */
+    tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;
+
+    for (rxLen = 0; rxLen < tmpVal; rxLen++) {
+        BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0);
+    }
+
+    /* Wait receive data and send the rest of the data 0 */
+    for (rxLen = 0; rxLen < length - tmpVal; rxLen++) {
+        timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+        while (SPI_GetRxFifoCount(spiNo) == 0) {
+            if (timeoutType) {
+                timeoutCnt--;
+
+                if (timeoutCnt == 0) {
+                    return TIMEOUT;
+                }
+            }
+        }
+
+        buff[rxLen++] = BL_RD_REG(SPIx, SPI_FIFO_RDATA);
+        BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0);
+    }
+
+    /* Wait receive the rest of the data */
+    for (; rxLen < length; rxLen++) {
+        timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+        while (SPI_GetRxFifoCount(spiNo) == 0) {
+            if (timeoutType) {
+                timeoutCnt--;
+
+                if (timeoutCnt == 0) {
+                    return TIMEOUT;
+                }
+            }
+        }
+
+        buff[rxLen++] = BL_RD_REG(SPIx, SPI_FIFO_RDATA);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SPI send and receive 8-bit datas at the same time
+ *
+ * @param  spiNo: SPI ID type
+ * @param  sendBuff: Buffer of datas to send
+ * @param  recvBuff: Buffer of datas received
+ * @param  length: Length of buffer
+ * @param  timeoutType: Enable or disable timeout judgment
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_SendRecv_8bits(SPI_ID_Type spiNo, uint8_t *sendBuff, uint8_t *recvBuff, uint32_t length, SPI_Timeout_Type timeoutType)
+{
+    uint32_t tmpVal;
+    uint32_t txLen = 0;
+    uint32_t SPIx = spiAddr[spiNo];
+    uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+    CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));
+
+    /* Set valid width for each fifo entry */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 0));
+
+    /* Disable rx ignore */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));
+
+    /* Clear tx and rx fifo */
+    tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR);
+    BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);
+
+    /* Fill tx fifo */
+    tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;
+
+    for (txLen = 0; txLen < tmpVal; txLen++) {
+        BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)sendBuff[txLen]);
+    }
+
+    /* Wait receive data and send the rest of the data */
+    for (; txLen < length; txLen++) {
+        timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+        while (SPI_GetRxFifoCount(spiNo) == 0) {
+            if (timeoutType) {
+                timeoutCnt--;
+
+                if (timeoutCnt == 0) {
+                    return TIMEOUT;
+                }
+            }
+        }
+
+        recvBuff[txLen - tmpVal] = (uint8_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xff);
+        BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)sendBuff[txLen]);
+    }
+
+    /* Wait receive the rest of the data */
+    for (txLen = 0; txLen < tmpVal; txLen++) {
+        timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+        while (SPI_GetRxFifoCount(spiNo) == 0) {
+            if (timeoutType) {
+                timeoutCnt--;
+
+                if (timeoutCnt == 0) {
+                    return TIMEOUT;
+                }
+            }
+        }
+
+        recvBuff[length - tmpVal + txLen] = (uint8_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xff);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SPI send and receive 16-bit datas at the same time
+ *
+ * @param  spiNo: SPI ID type
+ * @param  sendBuff: Buffer of datas to send
+ * @param  recvBuff: Buffer of datas received
+ * @param  length: Length of buffer
+ * @param  timeoutType: Enable or disable timeout judgment
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_SendRecv_16bits(SPI_ID_Type spiNo, uint16_t *sendBuff, uint16_t *recvBuff, uint32_t length, SPI_Timeout_Type timeoutType)
+{
+    uint32_t tmpVal;
+    uint32_t txLen = 0;
+    uint32_t SPIx = spiAddr[spiNo];
+    uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+    CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));
+
+    /* Set valid width for each fifo entry */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 1));
+
+    /* Disable rx ignore */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));
+
+    /* Clear tx and rx fifo */
+    tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR);
+    BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);
+
+    /* Fill tx fifo */
+    tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;
+
+    for (txLen = 0; txLen < tmpVal; txLen++) {
+        BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)sendBuff[txLen]);
+    }
+
+    /* Wait receive data and send the rest of the data */
+    for (; txLen < length; txLen++) {
+        timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+        while (SPI_GetRxFifoCount(spiNo) == 0) {
+            if (timeoutType) {
+                timeoutCnt--;
+
+                if (timeoutCnt == 0) {
+                    return TIMEOUT;
+                }
+            }
+        }
+
+        recvBuff[txLen - tmpVal] = (uint16_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffff);
+        BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)sendBuff[txLen]);
+    }
+
+    /* Wait receive the rest of the data */
+    for (txLen = 0; txLen < tmpVal; txLen++) {
+        timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+        while (SPI_GetRxFifoCount(spiNo) == 0) {
+            if (timeoutType) {
+                timeoutCnt--;
+
+                if (timeoutCnt == 0) {
+                    return TIMEOUT;
+                }
+            }
+        }
+
+        recvBuff[length - tmpVal + txLen] = (uint16_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffff);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SPI send and receive 24-bit datas at the same time
+ *
+ * @param  spiNo: SPI ID type
+ * @param  sendBuff: Buffer of datas to send
+ * @param  recvBuff: Buffer of datas received
+ * @param  length: Length of buffer
+ * @param  timeoutType: Enable or disable timeout judgment
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_SendRecv_24bits(SPI_ID_Type spiNo, uint32_t *sendBuff, uint32_t *recvBuff, uint32_t length, SPI_Timeout_Type timeoutType)
+{
+    uint32_t tmpVal;
+    uint32_t txLen = 0;
+    uint32_t SPIx = spiAddr[spiNo];
+    uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+    CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));
+
+    /* Set valid width for each fifo entry */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 2));
+
+    /* Disable rx ignore */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));
+
+    /* Clear tx and rx fifo */
+    tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR);
+    BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);
+
+    /* Fill tx fifo */
+    tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;
+
+    for (txLen = 0; txLen < tmpVal; txLen++) {
+        BL_WR_REG(SPIx, SPI_FIFO_WDATA, sendBuff[txLen]);
+    }
+
+    /* Wait receive data and send the rest of the data */
+    for (; txLen < length; txLen++) {
+        timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+        while (SPI_GetRxFifoCount(spiNo) == 0) {
+            if (timeoutType) {
+                timeoutCnt--;
+
+                if (timeoutCnt == 0) {
+                    return TIMEOUT;
+                }
+            }
+        }
+
+        recvBuff[txLen - tmpVal] = BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffffff;
+        BL_WR_REG(SPIx, SPI_FIFO_WDATA, sendBuff[txLen]);
+    }
+
+    /* Wait receive the rest of the data */
+    for (txLen = 0; txLen < tmpVal; txLen++) {
+        timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+        while (SPI_GetRxFifoCount(spiNo) == 0) {
+            if (timeoutType) {
+                timeoutCnt--;
+
+                if (timeoutCnt == 0) {
+                    return TIMEOUT;
+                }
+            }
+        }
+
+        recvBuff[length - tmpVal + txLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffffff;
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SPI send and receive 32-bit datas at the same time
+ *
+ * @param  spiNo: SPI ID type
+ * @param  sendBuff: Buffer of datas to send
+ * @param  recvBuff: Buffer of datas received
+ * @param  length: Length of buffer
+ * @param  timeoutType: Enable or disable timeout judgment
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type SPI_SendRecv_32bits(SPI_ID_Type spiNo, uint32_t *sendBuff, uint32_t *recvBuff, uint32_t length, SPI_Timeout_Type timeoutType)
+{
+    uint32_t tmpVal;
+    uint32_t txLen = 0;
+    uint32_t SPIx = spiAddr[spiNo];
+    uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+    CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));
+
+    /* Set valid width for each fifo entry */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 3));
+
+    /* Disable rx ignore */
+    tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
+    BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));
+
+    /* Clear tx and rx fifo */
+    tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR);
+    BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);
+
+    /* Fill tx fifo */
+    tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;
+
+    for (txLen = 0; txLen < tmpVal; txLen++) {
+        BL_WR_REG(SPIx, SPI_FIFO_WDATA, sendBuff[txLen]);
+    }
+
+    /* Wait receive data and send the rest of the data */
+    for (; txLen < length; txLen++) {
+        timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+        while (SPI_GetRxFifoCount(spiNo) == 0) {
+            if (timeoutType) {
+                timeoutCnt--;
+
+                if (timeoutCnt == 0) {
+                    return TIMEOUT;
+                }
+            }
+        }
+
+        recvBuff[txLen - tmpVal] = BL_RD_REG(SPIx, SPI_FIFO_RDATA);
+        BL_WR_REG(SPIx, SPI_FIFO_WDATA, sendBuff[txLen]);
+    }
+
+    /* Wait receive the rest of the data */
+    for (txLen = 0; txLen < tmpVal; txLen++) {
+        timeoutCnt = SPI_RX_TIMEOUT_COUNT;
+
+        while (SPI_GetRxFifoCount(spiNo) == 0) {
+            if (timeoutType) {
+                timeoutCnt--;
+
+                if (timeoutCnt == 0) {
+                    return TIMEOUT;
+                }
+            }
+        }
+
+        recvBuff[length - tmpVal + txLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SPI read data from rx fifo
+ *
+ * @param  spiNo: SPI ID type
+ *
+ * @return Data readed
+ *
+*******************************************************************************/
+uint32_t SPI_ReceiveData(SPI_ID_Type spiNo)
+{
+    uint32_t SPIx = spiAddr[spiNo];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+
+    return BL_RD_REG(SPIx, SPI_FIFO_RDATA);
+}
+
+/****************************************************************************/ /**
+ * @brief  Get tx fifo available count value function
+ *
+ * @param  spiNo: SPI ID type
+ *
+ * @return Count value
+ *
+*******************************************************************************/
+uint8_t SPI_GetTxFifoCount(SPI_ID_Type spiNo)
+{
+    uint32_t SPIx = spiAddr[spiNo];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+
+    /* Get count value */
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_TX_FIFO_CNT);
+}
+
+/****************************************************************************/ /**
+ * @brief  Get rx fifo available count value function
+ *
+ * @param  spiNo: SPI ID type
+ *
+ * @return Count value
+ *
+*******************************************************************************/
+uint8_t SPI_GetRxFifoCount(SPI_ID_Type spiNo)
+{
+    uint32_t SPIx = spiAddr[spiNo];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+
+    /* Get count value */
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT);
+}
+
+/****************************************************************************/ /**
+ * @brief  Get spi interrupt status
+ *
+ * @param  spiNo: SPI ID type
+ * @param  intType: SPI interrupt type
+ *
+ * @return Status of interrupt
+ *
+*******************************************************************************/
+BL_Sts_Type SPI_GetIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType)
+{
+    uint32_t tmpVal;
+    uint32_t SPIx = spiAddr[spiNo];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+    CHECK_PARAM(IS_SPI_INT_TYPE(intType));
+
+    /* Get certain or all interrupt status */
+    tmpVal = BL_RD_REG(SPIx, SPI_INT_STS);
+
+    if (SPI_INT_ALL == intType) {
+        if ((tmpVal & 0x3f) != 0) {
+            return SET;
+        } else {
+            return RESET;
+        }
+    } else {
+        if ((tmpVal & (1U << intType)) != 0) {
+            return SET;
+        } else {
+            return RESET;
+        }
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Get indicator of spi bus busy
+ *
+ * @param  spiNo: SPI ID type
+ *
+ * @return Status of spi bus
+ *
+*******************************************************************************/
+BL_Sts_Type SPI_GetBusyStatus(SPI_ID_Type spiNo)
+{
+    uint32_t tmpVal;
+    uint32_t SPIx = spiAddr[spiNo];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+
+    /* Get bus busy status */
+    tmpVal = BL_RD_REG(SPIx, SPI_BUS_BUSY);
+
+    if (BL_IS_REG_BIT_SET(tmpVal, SPI_STS_SPI_BUS_BUSY)) {
+        return SET;
+    } else {
+        return RESET;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Get tx/rx fifo overflow or underflow status
+ *
+ * @param  spiNo: SPI ID type
+ * @param  fifoSts: Select tx/rx overflow or underflow
+ *
+ * @return Status of tx/rx fifo
+ *
+*******************************************************************************/
+BL_Sts_Type SPI_GetFifoStatus(SPI_ID_Type spiNo, SPI_FifoStatus_Type fifoSts)
+{
+    uint32_t tmpVal;
+    uint32_t SPIx = spiAddr[spiNo];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
+    CHECK_PARAM(IS_SPI_FIFOSTATUS_TYPE(fifoSts));
+
+    /* Get tx/rx fifo overflow or underflow status */
+    tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
+
+    if ((tmpVal & (1U << (fifoSts + SPI_TX_FIFO_OVERFLOW_POS))) != 0) {
+        return SET;
+    } else {
+        return RESET;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  SPI interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void SPI_IRQHandler(void)
+{
+    SPI_IntHandler(SPI_ID_0);
+}
+#endif
+
+/*@} end of group SPI_Public_Functions */
+
+/*@} end of group SPI */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_timer.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_timer.c
new file mode 100644
index 00000000..0dec73f1
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_timer.c
@@ -0,0 +1,894 @@
+/**
+  ******************************************************************************
+  * @file    bl702_timer.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_timer.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  TIMER
+ *  @{
+ */
+
+/** @defgroup  TIMER_Private_Macros
+ *  @{
+ */
+#define TIMER_MAX_MATCH 3
+
+/*@} end of group TIMER_Private_Macros */
+
+/** @defgroup  TIMER_Private_Types
+ *  @{
+ */
+
+/*@} end of group TIMER_Private_Types */
+
+/** @defgroup  TIMER_Private_Variables
+ *  @{
+ */
+intCallback_Type *timerIntCbfArra[3][TIMER_INT_ALL] = {
+    { NULL, NULL, NULL },
+    { NULL, NULL, NULL },
+    { NULL, NULL, NULL }
+};
+
+/*@} end of group TIMER_Private_Variables */
+
+/** @defgroup  TIMER_Global_Variables
+ *  @{
+ */
+
+/*@} end of group TIMER_Global_Variables */
+
+/** @defgroup  TIMER_Private_Fun_Declaration
+ *  @{
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+static void TIMER_IntHandler(IRQn_Type irqNo, TIMER_Chan_Type timerCh);
+#endif
+
+/*@} end of group TIMER_Private_Fun_Declaration */
+
+/** @defgroup  TIMER_Private_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  TIMER interrupt common handler function
+ *
+ * @param  irqNo: Interrupt ID type
+ * @param  timerCh: TIMER channel type
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void TIMER_IntHandler(IRQn_Type irqNo, TIMER_Chan_Type timerCh)
+{
+    uint32_t intId;
+    uint32_t tmpVal;
+    uint32_t tmpAddr;
+
+    intId = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * timerCh);
+    tmpAddr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * timerCh;
+    tmpVal = BL_RD_WORD(tmpAddr);
+
+    /* Comparator 0 match interrupt */
+    if (BL_IS_REG_BIT_SET(intId, TIMER_TMSR_0)) {
+        BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TCLR_0));
+
+        if (timerIntCbfArra[irqNo - TIMER_CH0_IRQn][TIMER_INT_COMP_0] != NULL) {
+            /* Call the callback function */
+            timerIntCbfArra[irqNo - TIMER_CH0_IRQn][TIMER_INT_COMP_0]();
+        }
+    }
+
+    /* Comparator 1 match interrupt */
+    if (BL_IS_REG_BIT_SET(intId, TIMER_TMSR_1)) {
+        BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TCLR_1));
+
+        if (timerIntCbfArra[irqNo - TIMER_CH0_IRQn][TIMER_INT_COMP_1] != NULL) {
+            /* Call the callback function */
+            timerIntCbfArra[irqNo - TIMER_CH0_IRQn][TIMER_INT_COMP_1]();
+        }
+    }
+
+    /* Comparator 2 match interrupt */
+    if (BL_IS_REG_BIT_SET(intId, TIMER_TMSR_2)) {
+        BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TCLR_2));
+
+        if (timerIntCbfArra[irqNo - TIMER_CH0_IRQn][TIMER_INT_COMP_2] != NULL) {
+            /* Call the callback function */
+            timerIntCbfArra[irqNo - TIMER_CH0_IRQn][TIMER_INT_COMP_2]();
+        }
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Get the specified channel and match comparator value
+ *
+ * @param  timerCh: TIMER channel type
+ * @param  cmpNo: TIMER comparator ID type
+ *
+ * @return Match comapre register value
+ *
+*******************************************************************************/
+uint32_t TIMER_GetCompValue(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));
+    CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo));
+
+    tmpVal = BL_RD_WORD(TIMER_BASE + TIMER_TMR2_0_OFFSET + 4 * (TIMER_MAX_MATCH * timerCh + cmpNo));
+    return tmpVal;
+}
+
+/****************************************************************************/ /**
+ * @brief  TIMER set specified channel and comparator compare value
+ *
+ * @param  timerCh: TIMER channel type
+ * @param  cmpNo: TIMER comparator ID type
+ * @param  val: TIMER match comapre register value
+ *
+ * @return None
+ *
+*******************************************************************************/
+void TIMER_SetCompValue(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo, uint32_t val)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));
+    CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo));
+
+    BL_WR_WORD(TIMER_BASE + TIMER_TMR2_0_OFFSET + 4 * (TIMER_MAX_MATCH * timerCh + cmpNo), val);
+}
+
+/****************************************************************************/ /**
+ * @brief  TIMER get the specified channel count value
+ *
+ * @param  timerCh: TIMER channel type
+ *
+ * @return TIMER count register value
+ *
+*******************************************************************************/
+uint32_t TIMER_GetCounterValue(TIMER_Chan_Type timerCh)
+{
+    uint32_t tmpVal;
+    uint32_t tmpAddr;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));
+
+    /* TO avoid risk of reading, don't read TCVWR directly*/
+    /* request for read*/
+    tmpAddr = TIMER_BASE + TIMER_TCVWR2_OFFSET + 4 * timerCh;
+    BL_WR_WORD(tmpAddr, 1);
+
+    /* Need wait */
+    tmpVal = BL_RD_WORD(tmpAddr);
+    tmpVal = BL_RD_WORD(tmpAddr);
+    tmpVal = BL_RD_WORD(tmpAddr);
+
+    return tmpVal;
+}
+
+/****************************************************************************/ /**
+ * @brief  TIMER get specified channel and comparator match status
+ *
+ * @param  timerCh: TIMER channel type
+ * @param  cmpNo: TIMER comparator ID type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type TIMER_GetMatchStatus(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo)
+{
+    uint32_t tmpVal;
+    BL_Sts_Type bitStatus = RESET;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));
+    CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo));
+
+    tmpVal = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * timerCh);
+
+    switch (cmpNo) {
+        case TIMER_COMP_ID_0:
+            bitStatus = BL_IS_REG_BIT_SET(tmpVal, TIMER_TMSR_0) ? SET : RESET;
+            break;
+
+        case TIMER_COMP_ID_1:
+            bitStatus = BL_IS_REG_BIT_SET(tmpVal, TIMER_TMSR_1) ? SET : RESET;
+            break;
+
+        case TIMER_COMP_ID_2:
+            bitStatus = BL_IS_REG_BIT_SET(tmpVal, TIMER_TMSR_2) ? SET : RESET;
+            break;
+
+        default:
+            break;
+    }
+
+    return bitStatus;
+}
+
+/****************************************************************************/ /**
+ * @brief  TIMER get specified channel preload value
+ *
+ * @param  timerCh: TIMER channel type
+ *
+ * @return Preload register value
+ *
+*******************************************************************************/
+uint32_t TIMER_GetPreloadValue(TIMER_Chan_Type timerCh)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));
+
+    return BL_RD_WORD(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timerCh);
+}
+
+/****************************************************************************/ /**
+ * @brief  TIMER set preload register low 32bits value
+ *
+ * @param  timerCh: TIMER channel type
+ * @param  val: Preload register low 32bits value
+ *
+ * @return None
+ *
+*******************************************************************************/
+void TIMER_SetPreloadValue(TIMER_Chan_Type timerCh, uint32_t val)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));
+
+    BL_WR_WORD(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timerCh, val);
+}
+
+/****************************************************************************/ /**
+ * @brief  TIMER set preload trigger source,COMP0,COMP1,COMP2 or None
+ *
+ * @param  timerCh: TIMER channel type
+ * @param  plSrc: TIMER preload source type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void TIMER_SetPreloadTrigSrc(TIMER_Chan_Type timerCh, TIMER_PreLoad_Trig_Type plSrc)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));
+    CHECK_PARAM(IS_TIMER_PRELOAD_TRIG_TYPE(plSrc));
+
+    BL_WR_WORD(TIMER_BASE + TIMER_TPLCR2_OFFSET + 4 * timerCh, plSrc);
+}
+
+/****************************************************************************/ /**
+ * @brief  TIMER set count mode:preload or free run
+ *
+ * @param  timerCh: TIMER channel type
+ * @param  countMode: TIMER count mode: TIMER_COUNT_PRELOAD or TIMER_COUNT_FREERUN
+ *
+ * @return None
+ *
+*******************************************************************************/
+void TIMER_SetCountMode(TIMER_Chan_Type timerCh, TIMER_CountMode_Type countMode)
+{
+    uint32_t tmpval;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));
+    CHECK_PARAM(IS_TIMER_COUNTMODE_TYPE(countMode));
+
+    tmpval = BL_RD_WORD(TIMER_BASE + TIMER_TCMR_OFFSET);
+    tmpval &= (~(1 << (timerCh + 1)));
+    tmpval |= (countMode << (timerCh + 1));
+
+    BL_WR_WORD(TIMER_BASE + TIMER_TCMR_OFFSET, tmpval);
+}
+
+/****************************************************************************/ /**
+ * @brief  TIMER clear interrupt status
+ *
+ * @param  timerCh: TIMER channel type
+ * @param  cmpNo: TIMER macth comparator ID type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void TIMER_ClearIntStatus(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo)
+{
+    uint32_t tmpAddr;
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));
+    CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo));
+
+    tmpAddr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * timerCh;
+
+    tmpVal = BL_RD_WORD(tmpAddr);
+    tmpVal |= (1 << cmpNo);
+
+    BL_WR_WORD(tmpAddr, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TIMER initialization function
+ *
+ * @param  timerCfg: TIMER configuration structure pointer
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type TIMER_Init(TIMER_CFG_Type *timerCfg)
+{
+    TIMER_Chan_Type timerCh = timerCfg->timerCh;
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_TIMER_CLKSRC_TYPE(timerCfg->clkSrc));
+    CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCfg->timerCh));
+    CHECK_PARAM(IS_TIMER_PRELOAD_TRIG_TYPE(timerCfg->plTrigSrc));
+    CHECK_PARAM(IS_TIMER_COUNTMODE_TYPE(timerCfg->countMode));
+
+    /* Configure timer clock source */
+    tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
+
+    if (timerCh == TIMER_CH0) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_CS_1, timerCfg->clkSrc);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_CS_2, timerCfg->clkSrc);
+    }
+
+    BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpVal);
+
+    /* Configure timer clock division */
+    tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
+
+    if (timerCh == TIMER_CH0) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_TCDR2, timerCfg->clockDivision);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_TCDR3, timerCfg->clockDivision);
+    }
+
+    BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpVal);
+
+    /* Configure timer count mode: preload or free run */
+    TIMER_SetCountMode(timerCh, timerCfg->countMode);
+
+    /* Configure timer preload trigger src */
+    TIMER_SetPreloadTrigSrc(timerCh, timerCfg->plTrigSrc);
+
+    if (timerCfg->countMode == TIMER_COUNT_PRELOAD) {
+        /* Configure timer preload value */
+        TIMER_SetPreloadValue(timerCh, timerCfg->preLoadVal);
+
+        /* Configure match compare values */
+        if (timerCfg->matchVal0 > 1 + timerCfg->preLoadVal) {
+            TIMER_SetCompValue(timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0 - 2);
+        } else {
+            TIMER_SetCompValue(timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0);
+        }
+
+        if (timerCfg->matchVal1 > 1 + timerCfg->preLoadVal) {
+            TIMER_SetCompValue(timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1 - 2);
+        } else {
+            TIMER_SetCompValue(timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1);
+        }
+
+        if (timerCfg->matchVal2 > 1 + timerCfg->preLoadVal) {
+            TIMER_SetCompValue(timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2 - 2);
+        } else {
+            TIMER_SetCompValue(timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2);
+        }
+    } else {
+        /* Configure match compare values */
+        if (timerCfg->matchVal0 > 1) {
+            TIMER_SetCompValue(timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0 - 2);
+        } else {
+            TIMER_SetCompValue(timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0);
+        }
+
+        if (timerCfg->matchVal1 > 1) {
+            TIMER_SetCompValue(timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1 - 2);
+        } else {
+            TIMER_SetCompValue(timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1);
+        }
+
+        if (timerCfg->matchVal2 > 1) {
+            TIMER_SetCompValue(timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2 - 2);
+        } else {
+            TIMER_SetCompValue(timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2);
+        }
+    }
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(TIMER_CH0_IRQn, TIMER_CH0_IRQHandler);
+    Interrupt_Handler_Register(TIMER_CH1_IRQn, TIMER_CH1_IRQHandler);
+#endif
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  TIMER enable one channel function
+ *
+ * @param  timerCh: TIMER channel type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void TIMER_Enable(TIMER_Chan_Type timerCh)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));
+
+    tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCER);
+    tmpVal |= (1 << (timerCh + 1));
+
+    BL_WR_REG(TIMER_BASE, TIMER_TCER, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TIMER disable one channel function
+ *
+ * @param  timerCh: TIMER channel type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void TIMER_Disable(TIMER_Chan_Type timerCh)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));
+
+    tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCER);
+    tmpVal &= (~(1 << (timerCh + 1)));
+
+    BL_WR_REG(TIMER_BASE, TIMER_TCER, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TIMER mask or unmask certain or all interrupt
+ *
+ * @param  timerCh: TIMER channel type
+ * @param  intType: TIMER interrupt type
+ * @param  intMask: TIMER interrupt mask value:MASK:disbale interrupt.UNMASK:enable interrupt
+ *
+ * @return None
+ *
+*******************************************************************************/
+void TIMER_IntMask(TIMER_Chan_Type timerCh, TIMER_INT_Type intType, BL_Mask_Type intMask)
+{
+    uint32_t tmpAddr;
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));
+    CHECK_PARAM(IS_TIMER_INT_TYPE(intType));
+    CHECK_PARAM(IS_BL_MASK_TYPE(intMask));
+
+    tmpAddr = TIMER_BASE + TIMER_TIER2_OFFSET + 4 * timerCh;
+    tmpVal = BL_RD_WORD(tmpAddr);
+
+    switch (intType) {
+        case TIMER_INT_COMP_0:
+            if (intMask == UNMASK) {
+                /* Enable this interrupt */
+                BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER_0));
+            } else {
+                /* Disable this interrupt */
+                BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER_0));
+            }
+
+            break;
+
+        case TIMER_INT_COMP_1:
+            if (intMask == UNMASK) {
+                /* Enable this interrupt */
+                BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER_1));
+            } else {
+                /* Disable this interrupt */
+                BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER_1));
+            }
+
+            break;
+
+        case TIMER_INT_COMP_2:
+            if (intMask == UNMASK) {
+                /* Enable this interrupt */
+                BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER_2));
+            } else {
+                /* Disable this interrupt */
+                BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER_2));
+            }
+
+            break;
+
+        case TIMER_INT_ALL:
+            if (intMask == UNMASK) {
+                /* Enable this interrupt */
+                BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER_0));
+                BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER_1));
+                BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER_2));
+            } else {
+                /* Disable this interrupt */
+                BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER_0));
+                BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER_1));
+                BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER_2));
+            }
+
+            break;
+
+        default:
+            break;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  TIMER set watchdog clock source and clock division
+ *
+ * @param  clkSrc: Watchdog timer clock source type
+ * @param  div: Watchdog timer clock division value
+ *
+ * @return None
+ *
+*******************************************************************************/
+void WDT_Set_Clock(TIMER_ClkSrc_Type clkSrc, uint8_t div)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_TIMER_CLKSRC_TYPE(clkSrc));
+
+    /* Configure watchdog timer clock source */
+    tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_CS_WDT, clkSrc);
+    BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpVal);
+
+    /* Configure watchdog timer clock divison */
+    tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_WCDR, div);
+    BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TIMER get watchdog match compare value
+ *
+ * @param  None
+ *
+ * @return Watchdog match comapre register value
+ *
+*******************************************************************************/
+uint16_t WDT_GetMatchValue(void)
+{
+    uint32_t tmpVal;
+
+    WDT_ENABLE_ACCESS();
+
+    /* Get watchdog timer match register value */
+    tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WMR);
+
+    return tmpVal;
+}
+
+/****************************************************************************/ /**
+ * @brief  TIMER set watchdog match compare value
+ *
+ * @param  val: Watchdog match compare value
+ *
+ * @return None
+ *
+*******************************************************************************/
+void WDT_SetCompValue(uint16_t val)
+{
+    WDT_ENABLE_ACCESS();
+
+    /* Set watchdog timer match register value */
+    BL_WR_REG(TIMER_BASE, TIMER_WMR, val);
+}
+
+/****************************************************************************/ /**
+ * @brief  TIMER get watchdog count register value
+ *
+ * @param  None
+ *
+ * @return Watchdog count register value
+ *
+*******************************************************************************/
+uint16_t WDT_GetCounterValue(void)
+{
+    uint32_t tmpVal;
+
+    WDT_ENABLE_ACCESS();
+
+    /* Get watchdog timer count register value */
+    tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WVR);
+
+    return tmpVal;
+}
+
+/****************************************************************************/ /**
+ * @brief  TIMER reset watchdog count register value
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void WDT_ResetCounterValue(void)
+{
+    uint32_t tmpVal;
+
+    /* Reset watchdog timer count register value */
+    WDT_ENABLE_ACCESS();
+
+    tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WCR);
+
+    /* Set watchdog counter reset register bit0 to 1 */
+    BL_WR_REG(TIMER_BASE, TIMER_WCR, BL_SET_REG_BIT(tmpVal, TIMER_WCR));
+}
+
+/****************************************************************************/ /**
+ * @brief  TIMER get watchdog reset status
+ *
+ * @param  None
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type WDT_GetResetStatus(void)
+{
+    uint32_t tmpVal;
+
+    WDT_ENABLE_ACCESS();
+
+    /* Get watchdog status register */
+    tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WSR);
+
+    return (BL_IS_REG_BIT_SET(tmpVal, TIMER_WTS)) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  TIMER clear watchdog reset status
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void WDT_ClearResetStatus(void)
+{
+    uint32_t tmpVal;
+
+    WDT_ENABLE_ACCESS();
+
+    tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WSR);
+
+    /* Set watchdog status register */
+    BL_WR_REG(TIMER_BASE, TIMER_WSR, BL_CLR_REG_BIT(tmpVal, TIMER_WTS));
+}
+
+/****************************************************************************/ /**
+ * @brief  TIMER enable watchdog function
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void WDT_Enable(void)
+{
+    uint32_t tmpVal;
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(TIMER_WDT_IRQn, TIMER_WDT_IRQHandler);
+#endif
+
+    WDT_ENABLE_ACCESS();
+
+    tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WMER);
+
+    BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_SET_REG_BIT(tmpVal, TIMER_WE));
+}
+
+/****************************************************************************/ /**
+ * @brief  Watchdog timer disable function
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void WDT_Disable(void)
+{
+    uint32_t tmpVal;
+
+    WDT_ENABLE_ACCESS();
+
+    tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WMER);
+
+    BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_CLR_REG_BIT(tmpVal, TIMER_WE));
+}
+
+/****************************************************************************/ /**
+ * @brief  Watchdog timer mask or unmask certain or all interrupt
+ *
+ * @param  intType: Watchdog interrupt type
+ * @param  intMask: Watchdog interrupt mask value:MASK:disbale interrupt.UNMASK:enable interrupt
+ *
+ * @return None
+ *
+*******************************************************************************/
+void WDT_IntMask(WDT_INT_Type intType, BL_Mask_Type intMask)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_WDT_INT_TYPE(intType));
+    CHECK_PARAM(IS_BL_MASK_TYPE(intMask));
+
+    WDT_ENABLE_ACCESS();
+
+    /* Deal with watchdog match/interrupt enable register,
+      WRIE:watchdog reset/interrupt enable */
+    tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WMER);
+
+    switch (intType) {
+        case WDT_INT:
+            if (intMask == UNMASK) {
+                /* Enable this interrupt */
+                /* 0 means generates a watchdog interrupt,
+                   a watchdog timer reset is not generated*/
+                BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_CLR_REG_BIT(tmpVal, TIMER_WRIE));
+            } else {
+                /* Disable this interrupt */
+                /* 1 means generates a watchdog timer reset,
+                   a watchdog  interrupt is not generated*/
+                BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_SET_REG_BIT(tmpVal, TIMER_WRIE));
+            }
+
+            break;
+
+        default:
+            break;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  TIMER channel 0 interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void TIMER_CH0_IRQHandler(void)
+{
+    TIMER_IntHandler(TIMER_CH0_IRQn, TIMER_CH0);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  TIMER channel 1 interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void TIMER_CH1_IRQHandler(void)
+{
+    TIMER_IntHandler(TIMER_CH1_IRQn, TIMER_CH1);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  TIMER watchdog interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void TIMER_WDT_IRQHandler(void)
+{
+    uint32_t tmpVal;
+
+    WDT_ENABLE_ACCESS();
+
+    tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WICR);
+    BL_WR_REG(TIMER_BASE, TIMER_WICR, BL_SET_REG_BIT(tmpVal, TIMER_WICLR));
+
+    if (timerIntCbfArra[TIMER_WDT_IRQn - TIMER_CH0_IRQn][WDT_INT] != NULL) {
+        /* Call the callback function */
+        timerIntCbfArra[TIMER_WDT_IRQn - TIMER_CH0_IRQn][WDT_INT]();
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  TIMER install interrupt callback
+ *
+ * @param  timerChan: TIMER channel type
+ * @param  intType: TIMER interrupt type
+ * @param  cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Timer_Int_Callback_Install(TIMER_Chan_Type timerChan, TIMER_INT_Type intType, intCallback_Type *cbFun)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerChan));
+    CHECK_PARAM(IS_TIMER_INT_TYPE(intType));
+
+    timerIntCbfArra[timerChan][intType] = cbFun;
+}
+
+/****************************************************************************/ /**
+ * @brief  Watchdog install interrupt callback
+ *
+ * @param  wdtInt: Watchdog interrupt type
+ * @param  cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
+ *
+ * @return None
+ *
+*******************************************************************************/
+void WDT_Int_Callback_Install(WDT_INT_Type wdtInt, intCallback_Type *cbFun)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_WDT_INT_TYPE(wdtInt));
+
+    timerIntCbfArra[2][wdtInt] = cbFun;
+}
+
+/*@} end of group TIMER_Private_Functions */
+
+/*@} end of group TIMER */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_uart.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_uart.c
new file mode 100644
index 00000000..6b8ce8f2
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_uart.c
@@ -0,0 +1,1226 @@
+/**
+  ******************************************************************************
+  * @file    bl702_uart.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_uart.h"
+#include "bl702_glb.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  UART
+ *  @{
+ */
+
+/** @defgroup  UART_Private_Macros
+ *  @{
+ */
+#define UART_TX_TIMEOUT_COUNT (160 * 1000)
+
+/*@} end of group UART_Private_Macros */
+
+/** @defgroup  UART_Private_Types
+ *  @{
+ */
+
+/*@} end of group UART_Private_Types */
+
+/** @defgroup  UART_Private_Variables
+ *  @{
+ */
+static const uint32_t uartAddr[2] = { UART0_BASE, UART1_BASE };
+static intCallback_Type *uartIntCbfArra[2][UART_INT_ALL] = {
+    { NULL },
+    { NULL }
+};
+
+/*@} end of group UART_Private_Variables */
+
+/** @defgroup  UART_Global_Variables
+ *  @{
+ */
+
+/*@} end of group UART_Global_Variables */
+
+/** @defgroup  UART_Private_Fun_Declaration
+ *  @{
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+static void UART_IntHandler(UART_ID_Type uartId);
+#endif
+
+/*@} end of group UART_Private_Fun_Declaration */
+
+/** @defgroup  UART_Private_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  UART interrupt common handler function
+ *
+ * @param  uartId: UART ID type
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+static void UART_IntHandler(UART_ID_Type uartId)
+{
+    uint32_t tmpVal = 0;
+    uint32_t maskVal = 0;
+    uint32_t UARTx = uartAddr[uartId];
+
+    tmpVal = BL_RD_REG(UARTx, UART_INT_STS);
+    maskVal = BL_RD_REG(UARTx, UART_INT_MASK);
+
+    /* Length of uart tx data transfer arrived interrupt */
+    if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_END_MASK)) {
+        BL_WR_REG(UARTx, UART_INT_CLEAR, 0x1);
+
+        if (uartIntCbfArra[uartId][UART_INT_TX_END] != NULL) {
+            uartIntCbfArra[uartId][UART_INT_TX_END]();
+        }
+    }
+
+    /* Length of uart rx data transfer arrived interrupt */
+    if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_END_MASK)) {
+        BL_WR_REG(UARTx, UART_INT_CLEAR, 0x2);
+
+        if (uartIntCbfArra[uartId][UART_INT_RX_END] != NULL) {
+            uartIntCbfArra[uartId][UART_INT_RX_END]();
+        }
+    }
+
+    /* Tx fifo ready interrupt,auto-cleared when data is pushed */
+    if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FIFO_MASK)) {
+        if (uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ] != NULL) {
+            uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ]();
+        }
+    }
+
+    /* Rx fifo ready interrupt,auto-cleared when data is popped */
+    if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FIFO_MASK)) {
+        if (uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ] != NULL) {
+            uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ]();
+        }
+    }
+
+    /* Rx time-out interrupt */
+    if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_RTO_MASK)) {
+        BL_WR_REG(UARTx, UART_INT_CLEAR, 0x10);
+
+        if (uartIntCbfArra[uartId][UART_INT_RTO] != NULL) {
+            uartIntCbfArra[uartId][UART_INT_RTO]();
+        }
+    }
+
+    /* Rx parity check error interrupt */
+    if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_PCE_MASK)) {
+        BL_WR_REG(UARTx, UART_INT_CLEAR, 0x20);
+
+        if (uartIntCbfArra[uartId][UART_INT_PCE] != NULL) {
+            uartIntCbfArra[uartId][UART_INT_PCE]();
+        }
+    }
+
+    /* Tx fifo overflow/underflow error interrupt */
+    if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FER_MASK)) {
+        if (uartIntCbfArra[uartId][UART_INT_TX_FER] != NULL) {
+            uartIntCbfArra[uartId][UART_INT_TX_FER]();
+        }
+    }
+
+    /* Rx fifo overflow/underflow error interrupt */
+    if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FER_MASK)) {
+        if (uartIntCbfArra[uartId][UART_INT_RX_FER] != NULL) {
+            uartIntCbfArra[uartId][UART_INT_RX_FER]();
+        }
+    }
+
+    /* Rx lin mode sync field error interrupt */
+    if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_LSE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_LSE_MASK)) {
+        BL_WR_REG(UARTx, UART_INT_CLEAR, 0x100);
+
+        if (uartIntCbfArra[uartId][UART_INT_LSE] != NULL) {
+            uartIntCbfArra[uartId][UART_INT_LSE]();
+        }
+    }
+}
+#endif
+
+/*@} end of group UART_Private_Functions */
+
+/** @defgroup  UART_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  UART initialization function
+ *
+ * @param  uartId: UART ID type
+ * @param  uartCfg: UART configuration structure pointer
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type UART_Init(UART_ID_Type uartId, UART_CFG_Type *uartCfg)
+{
+    uint32_t tmpValTxCfg = 0;
+    uint32_t tmpValRxCfg = 0;
+    uint32_t fraction = 0;
+    uint32_t baudRateDivisor = 0;
+    uint32_t UARTx = uartAddr[uartId];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+    CHECK_PARAM(IS_UART_PARITY_TYPE(uartCfg->parity));
+    CHECK_PARAM(IS_UART_DATABITS_TYPE(uartCfg->dataBits));
+    CHECK_PARAM(IS_UART_STOPBITS_TYPE(uartCfg->stopBits));
+    CHECK_PARAM(IS_UART_BYTEBITINVERSE_TYPE(uartCfg->byteBitInverse));
+
+    /* Cal the baud rate divisor */
+    fraction = uartCfg->uartClk * 10 / uartCfg->baudRate % 10;
+    baudRateDivisor = uartCfg->uartClk / uartCfg->baudRate;
+
+    if (fraction >= 5) {
+        ++baudRateDivisor;
+    }
+
+    /* Set the baud rate register value */
+    BL_WR_REG(UARTx, UART_BIT_PRD, ((baudRateDivisor - 1) << 0x10) | ((baudRateDivisor - 1) & 0xFFFF));
+
+    /* Configure parity type */
+    tmpValTxCfg = BL_RD_REG(UARTx, UART_UTX_CONFIG);
+    tmpValRxCfg = BL_RD_REG(UARTx, UART_URX_CONFIG);
+
+    switch (uartCfg->parity) {
+        case UART_PARITY_NONE:
+            tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_EN);
+            tmpValRxCfg = BL_CLR_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_EN);
+            break;
+
+        case UART_PARITY_ODD:
+            tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_EN);
+            tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_SEL);
+            tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_EN);
+            tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_SEL);
+            break;
+
+        case UART_PARITY_EVEN:
+            tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_EN);
+            tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_SEL);
+            tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_EN);
+            tmpValRxCfg = BL_CLR_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_SEL);
+            break;
+
+        default:
+            break;
+    }
+
+    /* Configure data bits */
+    tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_BIT_CNT_D, (uartCfg->dataBits + 4));
+    tmpValRxCfg = BL_SET_REG_BITS_VAL(tmpValRxCfg, UART_CR_URX_BIT_CNT_D, (uartCfg->dataBits + 4));
+
+    /* Configure tx stop bits */
+    tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_BIT_CNT_P, uartCfg->stopBits);
+
+    /* Configure tx cts flow control function */
+    tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_CTS_EN, uartCfg->ctsFlowControl);
+
+    /* Configure rx input de-glitch function */
+    tmpValRxCfg = BL_SET_REG_BITS_VAL(tmpValRxCfg, UART_CR_URX_DEG_EN, uartCfg->rxDeglitch);
+
+    /* Configure tx lin mode function */
+    tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_LIN_EN, uartCfg->txLinMode);
+
+    /* Configure rx lin mode function */
+    tmpValRxCfg = BL_SET_REG_BITS_VAL(tmpValRxCfg, UART_CR_URX_LIN_EN, uartCfg->rxLinMode);
+
+    /* Set tx break bit count for lin protocol */
+    tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_BIT_CNT_B, uartCfg->txBreakBitCnt);
+
+    /* Write back */
+    BL_WR_REG(UARTx, UART_UTX_CONFIG, tmpValTxCfg);
+    BL_WR_REG(UARTx, UART_URX_CONFIG, tmpValRxCfg);
+
+    /* Configure LSB-first or MSB-first */
+    tmpValTxCfg = BL_RD_REG(UARTx, UART_DATA_CONFIG);
+
+    if (UART_MSB_FIRST == uartCfg->byteBitInverse) {
+        tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UART_BIT_INV);
+    } else {
+        tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg, UART_CR_UART_BIT_INV);
+    }
+
+    BL_WR_REG(UARTx, UART_DATA_CONFIG, tmpValTxCfg);
+
+    tmpValTxCfg = BL_RD_REG(UARTx, UART_SW_MODE);
+    /* Configure rx rts output SW control mode */
+    tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_URX_RTS_SW_MODE, uartCfg->rtsSoftwareControl);
+    /* Configure tx output SW control mode */
+    tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_TXD_SW_MODE, uartCfg->txSoftwareControl);
+    BL_WR_REG(UARTx, UART_SW_MODE, tmpValTxCfg);
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(UART0_IRQn, UART0_IRQHandler);
+    Interrupt_Handler_Register(UART1_IRQn, UART1_IRQHandler);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  UART set default value of all registers function
+ *
+ * @param  uartId: UART ID type
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type UART_DeInit(UART_ID_Type uartId)
+{
+    if (UART0_ID == uartId) {
+        GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART0);
+    } else if (UART1_ID == uartId) {
+        GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART1);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  UART configure fifo function
+ *
+ * @param  uartId: UART ID type
+ * @param  fifoCfg: FIFO configuration structure pointer
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type UART_FifoConfig(UART_ID_Type uartId, UART_FifoCfg_Type *fifoCfg)
+{
+    uint32_t tmpVal = 0;
+    uint32_t UARTx = uartAddr[uartId];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+
+    /* Deal with uart fifo configure register */
+    tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_1);
+    /* Configure dma tx fifo threshold */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_TX_FIFO_TH, fifoCfg->txFifoDmaThreshold);
+    /* Configure dma rx fifo threshold */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_RX_FIFO_TH, fifoCfg->rxFifoDmaThreshold);
+    /* Write back */
+    BL_WR_REG(UARTx, UART_FIFO_CONFIG_1, tmpVal);
+
+    /* Enable or disable uart fifo dma function */
+    tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0);
+
+    if (ENABLE == fifoCfg->txFifoDmaEnable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_TX_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_TX_EN);
+    }
+
+    if (ENABLE == fifoCfg->rxFifoDmaEnable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_RX_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_RX_EN);
+    }
+
+    BL_WR_REG(UARTx, UART_FIFO_CONFIG_0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  UART configure infra function
+ *
+ * @param  uartId: UART ID type
+ * @param  irCfg: IR configuration structure pointer
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type UART_IrConfig(UART_ID_Type uartId, UART_IrCfg_Type *irCfg)
+{
+    uint32_t tmpVal = 0;
+    uint32_t UARTx = uartAddr[uartId];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+
+    /* Configure tx ir mode */
+    tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG);
+
+    if (ENABLE == irCfg->txIrEnable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_UTX_IR_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_IR_EN);
+    }
+
+    if (ENABLE == irCfg->txIrInverse) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_UTX_IR_INV);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_IR_INV);
+    }
+
+    BL_WR_REG(UARTx, UART_UTX_CONFIG, tmpVal);
+
+    /* Configure rx ir mode */
+    tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG);
+
+    if (ENABLE == irCfg->rxIrEnable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_URX_IR_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_URX_IR_EN);
+    }
+
+    if (ENABLE == irCfg->rxIrInverse) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_URX_IR_INV);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_URX_IR_INV);
+    }
+
+    BL_WR_REG(UARTx, UART_URX_CONFIG, tmpVal);
+
+    /* Configure tx ir pulse start and stop position */
+    BL_WR_REG(UARTx, UART_UTX_IR_POSITION, irCfg->txIrPulseStop << 0x10 | irCfg->txIrPulseStart);
+
+    /* Configure rx ir pulse start position */
+    BL_WR_REG(UARTx, UART_URX_IR_POSITION, irCfg->rxIrPulseStart);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable UART
+ *
+ * @param  uartId: UART ID type
+ * @param  direct: UART direction type
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type UART_Enable(UART_ID_Type uartId, UART_Direction_Type direct)
+{
+    uint32_t tmpVal = 0;
+    uint32_t UARTx = uartAddr[uartId];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+    CHECK_PARAM(IS_UART_DIRECTION_TYPE(direct));
+
+    if (direct == UART_TX || direct == UART_TXRX) {
+        /* Enable UART tx unit */
+        tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG);
+        BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_UTX_EN));
+    }
+
+    if (direct == UART_RX || direct == UART_TXRX) {
+        /* Enable UART rx unit */
+        tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG);
+        BL_WR_REG(UARTx, UART_URX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_URX_EN));
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable UART
+ *
+ * @param  uartId: UART ID type
+ * @param  direct: UART direction type
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type UART_Disable(UART_ID_Type uartId, UART_Direction_Type direct)
+{
+    uint32_t tmpVal = 0;
+    uint32_t UARTx = uartAddr[uartId];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+    CHECK_PARAM(IS_UART_DIRECTION_TYPE(direct));
+
+    if (direct == UART_TX || direct == UART_TXRX) {
+        /* Disable UART tx unit */
+        tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG);
+        BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_EN));
+    }
+
+    if (direct == UART_RX || direct == UART_TXRX) {
+        /* Disable UART rx unit */
+        tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG);
+        BL_WR_REG(UARTx, UART_URX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_URX_EN));
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  UART set length of tx data transfer,tx end interrupt will assert when this length is
+ *         reached
+ *
+ * @param  uartId: UART ID type
+ * @param  length: Length of data (unit:character/byte)
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type UART_SetTxDataLength(UART_ID_Type uartId, uint16_t length)
+{
+    uint32_t tmpVal = 0;
+    uint32_t UARTx = uartAddr[uartId];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+
+    /* Set length */
+    tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG);
+    BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, UART_CR_UTX_LEN, length - 1));
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  UART set length of rx data transfer,rx end interrupt will assert when this length is
+ *         reached
+ *
+ * @param  uartId: UART ID type
+ * @param  length: Length of data (unit:character/byte)
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type UART_SetRxDataLength(UART_ID_Type uartId, uint16_t length)
+{
+    uint32_t tmpVal = 0;
+    uint32_t UARTx = uartAddr[uartId];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+
+    /* Set length */
+    tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG);
+    BL_WR_REG(UARTx, UART_URX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_LEN, length - 1));
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  UART set rx time-out value for triggering RTO interrupt
+ *
+ * @param  uartId: UART ID type
+ * @param  time: Time-out value (unit:bit time)
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type UART_SetRxTimeoutValue(UART_ID_Type uartId, uint8_t time)
+{
+    uint32_t UARTx = uartAddr[uartId];
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+
+    /* Set time-out value */
+    tmpVal = BL_RD_REG(UARTx, UART_URX_RTO_TIMER);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_RTO_VALUE, time - 1);
+    BL_WR_REG(UARTx, UART_URX_RTO_TIMER, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  UART set de-glitch function cycle count value
+ *
+ * @param  uartId: UART ID type
+ * @param  deglitchCnt: De-glitch function cycle count
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId, uint8_t deglitchCnt)
+{
+    uint32_t UARTx = uartAddr[uartId];
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+
+    /* Set count value */
+    tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_DEG_CNT, deglitchCnt);
+    BL_WR_REG(UARTx, UART_URX_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  UART set tx and rx baudrate according to auto baudrate detection value
+ *
+ * @param  uartId: UART ID type
+ * @param  autoBaudDet: Choose detection value using codeword 0x55 or start bit
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type UART_ApplyAbrResult(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet)
+{
+    uint32_t UARTx = uartAddr[uartId];
+    uint16_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+
+    /* Get detection value */
+    tmpVal = UART_GetAutoBaudCount(uartId, autoBaudDet);
+
+    /* Set tx baudrate */
+    BL_WR_REG(UARTx, UART_BIT_PRD, tmpVal << 0x10 | tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  UART set rx rts output software control value
+ *
+ * @param  uartId: UART ID type
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type UART_SetRtsValue(UART_ID_Type uartId)
+{
+    uint32_t UARTx = uartAddr[uartId];
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+
+    /* Rts set 1*/
+    tmpVal = BL_RD_REG(UARTx, UART_SW_MODE);
+    BL_WR_REG(UARTx, UART_SW_MODE, BL_SET_REG_BIT(tmpVal, UART_CR_URX_RTS_SW_VAL));
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  UART clear rx rts output software control value
+ *
+ * @param  uartId: UART ID type
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type UART_ClrRtsValue(UART_ID_Type uartId)
+{
+    uint32_t UARTx = uartAddr[uartId];
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+
+    /* Rts clear 0 */
+    tmpVal = BL_RD_REG(UARTx, UART_SW_MODE);
+    BL_WR_REG(UARTx, UART_SW_MODE, BL_CLR_REG_BIT(tmpVal, UART_CR_URX_RTS_SW_VAL));
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  UART set tx output software control value
+ *
+ * @param  uartId: UART ID type
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type UART_SetTxValue(UART_ID_Type uartId)
+{
+    uint32_t UARTx = uartAddr[uartId];
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+
+    /* Tx set 1*/
+    tmpVal = BL_RD_REG(UARTx, UART_SW_MODE);
+    BL_WR_REG(UARTx, UART_SW_MODE, BL_SET_REG_BIT(tmpVal, UART_CR_UTX_TXD_SW_VAL));
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  UART clear tx output software control value
+ *
+ * @param  uartId: UART ID type
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type UART_ClrTxValue(UART_ID_Type uartId)
+{
+    uint32_t UARTx = uartAddr[uartId];
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+
+    /* Rts clear 0 */
+    tmpVal = BL_RD_REG(UARTx, UART_SW_MODE);
+    BL_WR_REG(UARTx, UART_SW_MODE, BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_TXD_SW_VAL));
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  UART configure tx free run mode function
+ *
+ * @param  uartId: UART ID type
+ * @param  txFreeRun: Enable or disable tx free run mode
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type UART_TxFreeRun(UART_ID_Type uartId, BL_Fun_Type txFreeRun)
+{
+    uint32_t tmpVal = 0;
+    uint32_t UARTx = uartAddr[uartId];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+
+    /* Enable or disable tx free run mode */
+    tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG);
+
+    if (ENABLE == txFreeRun) {
+        BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_UTX_FRM_EN));
+    } else {
+        BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_FRM_EN));
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  UART configure auto baud rate detection function
+ *
+ * @param  uartId: UART ID type
+ * @param  autoBaud: Enable or disable auto function
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type UART_AutoBaudDetection(UART_ID_Type uartId, BL_Fun_Type autoBaud)
+{
+    uint32_t tmpVal = 0;
+    uint32_t UARTx = uartAddr[uartId];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+
+    /* Enable or disable auto baud rate detection function */
+    tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG);
+
+    if (ENABLE == autoBaud) {
+        BL_WR_REG(UARTx, UART_URX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_URX_ABR_EN));
+    } else {
+        BL_WR_REG(UARTx, UART_URX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_URX_ABR_EN));
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  UART tx fifo clear
+ *
+ * @param  uartId: UART ID type
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type UART_TxFifoClear(UART_ID_Type uartId)
+{
+    uint32_t tmpVal = 0;
+    uint32_t UARTx = uartAddr[uartId];
+
+    /* Check the parameter */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+
+    /* Clear tx fifo */
+    tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0);
+    BL_WR_REG(UARTx, UART_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, UART_TX_FIFO_CLR));
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  UART rx fifo clear
+ *
+ * @param  uartId: UART ID type
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type UART_RxFifoClear(UART_ID_Type uartId)
+{
+    uint32_t tmpVal = 0;
+    uint32_t UARTx = uartAddr[uartId];
+
+    /* Check the parameter */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+
+    /* Clear rx fifo */
+    tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0);
+    BL_WR_REG(UARTx, UART_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, UART_RX_FIFO_CLR));
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  UART mask or unmask certain or all interrupt
+ *
+ * @param  uartId: UART ID type
+ * @param  intType: UART interrupt type
+ * @param  intMask: UART interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt )
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type UART_IntMask(UART_ID_Type uartId, UART_INT_Type intType, BL_Mask_Type intMask)
+{
+    uint32_t tmpVal;
+    uint32_t UARTx = uartAddr[uartId];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+    CHECK_PARAM(IS_UART_INT_TYPE(intType));
+    CHECK_PARAM(IS_BL_MASK_TYPE(intMask));
+
+    tmpVal = BL_RD_REG(UARTx, UART_INT_MASK);
+
+    /* Mask or unmask certain or all interrupt */
+    if (UART_INT_ALL == intType) {
+        if (MASK == intMask) {
+            tmpVal |= 0x1ff;
+        } else {
+            tmpVal &= 0;
+        }
+    } else {
+        if (MASK == intMask) {
+            tmpVal |= 1 << intType;
+        } else {
+            tmpVal &= ~(1 << intType);
+        }
+    }
+
+    /* Write back */
+    BL_WR_REG(UARTx, UART_INT_MASK, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  UART clear certain or all interrupt
+ *
+ * @param  uartId: UART ID type
+ * @param  intType: UART interrupt type
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type UART_IntClear(UART_ID_Type uartId, UART_INT_Type intType)
+{
+    uint32_t tmpVal;
+    uint32_t UARTx = uartAddr[uartId];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+    CHECK_PARAM(IS_UART_INT_TYPE(intType));
+
+    tmpVal = BL_RD_REG(UARTx, UART_INT_CLEAR);
+
+    /* Clear certain or all interrupt */
+    if (UART_INT_ALL == intType) {
+        tmpVal |= 0x1ff;
+    } else {
+        tmpVal |= 1 << intType;
+    }
+
+    /* Write back */
+    BL_WR_REG(UARTx, UART_INT_CLEAR, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Install uart interrupt callback function
+ *
+ * @param  uartId: UART ID type
+ * @param  intType: UART interrupt type
+ * @param  cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type UART_Int_Callback_Install(UART_ID_Type uartId, UART_INT_Type intType, intCallback_Type *cbFun)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+    CHECK_PARAM(IS_UART_INT_TYPE(intType));
+
+    uartIntCbfArra[uartId][intType] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  UART send data to tx fifo
+ *
+ * @param  uartId: UART ID type
+ * @param  data: The data to be send
+ * @param  len: The length of the send buffer
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type UART_SendData(UART_ID_Type uartId, uint8_t *data, uint32_t len)
+{
+    uint32_t txLen = 0;
+    uint32_t UARTx = uartAddr[uartId];
+    uint32_t timeoutCnt = UART_TX_TIMEOUT_COUNT;
+
+    /* Check the parameter */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+
+    /* Send data */
+    while (txLen < len) {
+        if (UART_GetTxFifoCount(uartId) > 0) {
+            BL_WR_BYTE(UARTx + UART_FIFO_WDATA_OFFSET, data[txLen++]);
+            timeoutCnt = UART_TX_TIMEOUT_COUNT;
+        } else {
+            timeoutCnt--;
+
+            if (timeoutCnt == 0) {
+                return TIMEOUT;
+            }
+        }
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  UART send data to tx fifo in block mode
+ *
+ * @param  uartId: UART ID type
+ * @param  data: The data to be send
+ * @param  len: The length of the send buffer
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type UART_SendDataBlock(UART_ID_Type uartId, uint8_t *data, uint32_t len)
+{
+    uint32_t txLen = 0;
+    uint32_t UARTx = uartAddr[uartId];
+    uint32_t timeoutCnt = UART_TX_TIMEOUT_COUNT;
+
+    /* Check the parameter */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+
+    /* Send data */
+    while (txLen < len) {
+        if (UART_GetTxFifoCount(uartId) > 0) {
+            BL_WR_BYTE(UARTx + UART_FIFO_WDATA_OFFSET, data[txLen++]);
+            timeoutCnt = UART_TX_TIMEOUT_COUNT;
+        } else {
+            timeoutCnt--;
+
+            if (timeoutCnt == 0) {
+                return TIMEOUT;
+            }
+        }
+    }
+
+    while (UART_GetTxBusBusyStatus(uartId) == SET) {
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  UART receive data from rx fifo
+ *
+ * @param  uartId: UART ID type
+ * @param  data: The receive data buffer
+ * @param  maxLen: The max length of the buffer
+ *
+ * @return The length of the received buffer
+ *
+*******************************************************************************/
+uint32_t UART_ReceiveData(UART_ID_Type uartId, uint8_t *data, uint32_t maxLen)
+{
+    uint32_t rxLen = 0;
+    uint32_t UARTx = uartAddr[uartId];
+
+    /* Check the parameter */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+
+    /* Receive data */
+    while (rxLen < maxLen && UART_GetRxFifoCount(uartId) > 0) {
+        data[rxLen++] = BL_RD_BYTE(UARTx + UART_FIFO_RDATA_OFFSET);
+    }
+
+    return rxLen;
+}
+
+/****************************************************************************/ /**
+ * @brief  UART get auto baud count value
+ *
+ * @param  uartId: UART ID type
+ * @param  autoBaudDet: Detection using codeword 0x55 or start bit
+ *
+ * @return Bit period of auto baudrate detection
+ *
+*******************************************************************************/
+uint16_t UART_GetAutoBaudCount(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet)
+{
+    uint32_t UARTx = uartAddr[uartId];
+
+    /* Check the parameter */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+    CHECK_PARAM(IS_UART_AUTOBAUDDETECTION_TYPE(autoBaudDet));
+
+    /* Select 0x55 or start bit detection value */
+    if (UART_AUTOBAUD_0X55 == autoBaudDet) {
+        return BL_RD_REG(UARTx, UART_STS_URX_ABR_PRD) >> 0x10 & 0xffff;
+    } else {
+        return BL_RD_REG(UARTx, UART_STS_URX_ABR_PRD) & 0xffff;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  UART get tx fifo unoccupied count value
+ *
+ * @param  uartId: UART ID type
+ *
+ * @return Tx fifo unoccupied count value
+ *
+*******************************************************************************/
+uint8_t UART_GetTxFifoCount(UART_ID_Type uartId)
+{
+    uint32_t UARTx = uartAddr[uartId];
+
+    /* Check the parameter */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(UARTx, UART_FIFO_CONFIG_1), UART_TX_FIFO_CNT);
+}
+
+/****************************************************************************/ /**
+ * @brief  UART get rx fifo occupied count value
+ *
+ * @param  uartId: UART ID type
+ *
+ * @return Rx fifo occupied count value
+ *
+*******************************************************************************/
+uint8_t UART_GetRxFifoCount(UART_ID_Type uartId)
+{
+    uint32_t UARTx = uartAddr[uartId];
+
+    /* Check the parameter */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(UARTx, UART_FIFO_CONFIG_1), UART_RX_FIFO_CNT);
+}
+
+/****************************************************************************/ /**
+ * @brief  Get uart interrupt status
+ *
+ * @param  uartId: UART ID type
+ * @param  intType: UART interrupt type
+ *
+ * @return Status of interrupt
+ *
+*******************************************************************************/
+BL_Sts_Type UART_GetIntStatus(UART_ID_Type uartId, UART_INT_Type intType)
+{
+    uint32_t tmpVal;
+    uint32_t UARTx = uartAddr[uartId];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+    CHECK_PARAM(IS_UART_INT_TYPE(intType));
+
+    /* Get certain or all interrupt status */
+    tmpVal = BL_RD_REG(UARTx, UART_INT_STS);
+
+    if (UART_INT_ALL == intType) {
+        if ((tmpVal & 0x1ff) != 0) {
+            return SET;
+        } else {
+            return RESET;
+        }
+    } else {
+        if ((tmpVal & (1U << intType)) != 0) {
+            return SET;
+        } else {
+            return RESET;
+        }
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Get indicator of uart tx bus busy
+ *
+ * @param  uartId: UART ID type
+ *
+ * @return Status of tx bus
+ *
+*******************************************************************************/
+BL_Sts_Type UART_GetTxBusBusyStatus(UART_ID_Type uartId)
+{
+    uint32_t tmpVal;
+    uint32_t UARTx = uartAddr[uartId];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+
+    /* Get tx bus busy status */
+    tmpVal = BL_RD_REG(UARTx, UART_STATUS);
+
+    if (BL_IS_REG_BIT_SET(tmpVal, UART_STS_UTX_BUS_BUSY)) {
+        return SET;
+    } else {
+        return RESET;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Get indicator of uart rx bus busy
+ *
+ * @param  uartId: UART ID type
+ *
+ * @return Status of rx bus
+ *
+*******************************************************************************/
+BL_Sts_Type UART_GetRxBusBusyStatus(UART_ID_Type uartId)
+{
+    uint32_t tmpVal;
+    uint32_t UARTx = uartAddr[uartId];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+
+    /* Get rx bus busy status */
+    tmpVal = BL_RD_REG(UARTx, UART_STATUS);
+
+    if (BL_IS_REG_BIT_SET(tmpVal, UART_STS_URX_BUS_BUSY)) {
+        return SET;
+    } else {
+        return RESET;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Get tx/rx fifo overflow or underflow status
+ *
+ * @param  uartId: UART ID type
+ * @param  overflow: Select tx/rx overflow or underflow
+ *
+ * @return Status of tx/rx fifo
+ *
+*******************************************************************************/
+BL_Sts_Type UART_GetOverflowStatus(UART_ID_Type uartId, UART_Overflow_Type overflow)
+{
+    uint32_t tmpVal;
+    uint32_t UARTx = uartAddr[uartId];
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_UART_ID_TYPE(uartId));
+    CHECK_PARAM(IS_UART_OVERFLOW_TYPE(overflow));
+
+    /* Get tx/rx fifo overflow or underflow status */
+    tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0);
+
+    if ((tmpVal & (1U << (overflow + 4))) != 0) {
+        return SET;
+    } else {
+        return RESET;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  UART0 interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void UART0_IRQHandler(void)
+{
+    UART_IntHandler(UART0_ID);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  UART1 interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void UART1_IRQHandler(void)
+{
+    UART_IntHandler(UART1_ID);
+}
+#endif
+
+/*@} end of group UART_Public_Functions */
+
+/*@} end of group UART */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_usb.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_usb.c
new file mode 100644
index 00000000..64766265
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_usb.c
@@ -0,0 +1,2491 @@
+/**
+  ******************************************************************************
+  * @file    bl70x_usb.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_usb.h"
+#include "bl702_glb.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL70X_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  USB
+ *  @{
+ */
+
+/** @defgroup  USB_Private_Macros
+ *  @{
+ */
+
+/*@} end of group USB_Private_Macros */
+
+/** @defgroup  USB_Private_Types
+ *  @{
+ */
+
+/*@} end of group USB_Private_Types */
+
+/** @defgroup  USB_Private_Variables
+ *  @{
+ */
+
+/*@} end of group USB_Private_Variables */
+
+/** @defgroup  USB_Global_Variables
+ *  @{
+ */
+
+/*@} end of group USB_Global_Variables */
+
+/** @defgroup  USB_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group USB_Private_Fun_Declaration */
+
+/** @defgroup  USB_Private_Functions
+ *  @{
+ */
+
+/*@} end of group USB_Private_Functions */
+
+/** @defgroup  USB_Public_Functions
+ *  @{
+ */
+
+BL_Err_Type USB_Enable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
+    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EN);
+    BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_Disable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EN);
+    BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_Set_Config(BL_Fun_Type enable, USB_Config_Type *usbCfg)
+{
+    uint32_t tmpVal = 0;
+
+    /* disable USB first */
+    tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EN);
+    BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
+
+    /* USB config */
+    tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
+
+    if (usbCfg->SoftwareCtrl == ENABLE) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_CTRL);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_EP0_SW_ADDR, usbCfg->DeviceAddress);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_EP0_SW_SIZE, usbCfg->EnumMaxPacketSize);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_EP0_SW_NACK_IN, usbCfg->EnumInEn);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_EP0_SW_NACK_OUT, usbCfg->EnumOutEn);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_ROM_DCT_EN, usbCfg->RomBaseDescriptorUsed);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_CTRL);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_ROM_DCT_EN, usbCfg->RomBaseDescriptorUsed);
+    }
+
+    BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
+
+    /* enable/disable USB */
+    tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
+
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EN);
+    }
+
+    BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_Set_Device_Addr(uint8_t addr)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_EP0_SW_ADDR, addr);
+    BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+
+uint8_t USB_Get_Device_Addr(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, USB_CR_USB_EP0_SW_ADDR);
+}
+
+BL_Err_Type USB_Set_EPx_Xfer_Size(USB_EP_ID epId, uint8_t size)
+{
+    uint32_t tmpVal = 0;
+
+    if (epId == EP_ID0) {
+        tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_EP0_SW_SIZE, size);
+        BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
+    } else {
+        switch (epId) {
+            case EP_ID1:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
+                tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP1_SIZE, size);
+                BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
+                break;
+
+            case EP_ID2:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
+                tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP2_SIZE, size);
+                BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
+                break;
+
+            case EP_ID3:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
+                tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP3_SIZE, size);
+                BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
+                break;
+
+            case EP_ID4:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
+                tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP4_SIZE, size);
+                BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
+                break;
+
+            case EP_ID5:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
+                tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP5_SIZE, size);
+                BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
+                break;
+
+            case EP_ID6:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
+                tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP6_SIZE, size);
+                BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
+                break;
+
+            case EP_ID7:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
+                tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP7_SIZE, size);
+                BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
+                break;
+
+            default:
+                break;
+        }
+    }
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_Set_EPx_IN_Busy(USB_EP_ID epId)
+{
+    uint32_t tmpVal = 0;
+
+    if (epId == EP_ID0) {
+        tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
+        tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_IN);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_STALL);
+        BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
+    } else {
+        switch (epId) {
+            case EP_ID1:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP1_STALL);
+                BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
+                break;
+
+            case EP_ID2:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP2_STALL);
+                BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
+                break;
+
+            case EP_ID3:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP3_STALL);
+                BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
+                break;
+
+            case EP_ID4:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP4_STALL);
+                BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
+                break;
+
+            case EP_ID5:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP5_STALL);
+                BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
+                break;
+
+            case EP_ID6:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP6_STALL);
+                BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
+                break;
+
+            case EP_ID7:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP7_STALL);
+                BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
+                break;
+
+            default:
+                break;
+        }
+    }
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_Set_EPx_IN_Stall(USB_EP_ID epId)
+{
+    uint32_t tmpVal = 0;
+
+    if (epId == EP_ID0) {
+        tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_OUT);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_IN);
+        tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_STALL);
+        BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
+    } else {
+        switch (epId) {
+            case EP_ID1:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP1_NACK);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_STALL);
+                BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
+                break;
+
+            case EP_ID2:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP2_NACK);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_STALL);
+                BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
+                break;
+
+            case EP_ID3:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP3_NACK);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_STALL);
+                BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
+                break;
+
+            case EP_ID4:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP4_NACK);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_STALL);
+                BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
+                break;
+
+            case EP_ID5:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP5_NACK);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_STALL);
+                BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
+                break;
+
+            case EP_ID6:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP6_NACK);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_STALL);
+                BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
+                break;
+
+            case EP_ID7:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP7_NACK);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_STALL);
+                BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
+                break;
+
+            default:
+                break;
+        }
+    }
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_Set_EPx_OUT_Busy(USB_EP_ID epId)
+{
+    uint32_t tmpVal = 0;
+
+    if (epId == EP_ID0) {
+        tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
+        tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_OUT);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_STALL);
+        BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
+    } else {
+        switch (epId) {
+            case EP_ID1:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP1_STALL);
+                BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
+                break;
+
+            case EP_ID2:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP2_STALL);
+                BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
+                break;
+
+            case EP_ID3:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP3_STALL);
+                BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
+                break;
+
+            case EP_ID4:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP4_STALL);
+                BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
+                break;
+
+            case EP_ID5:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP5_STALL);
+                BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
+                break;
+
+            case EP_ID6:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP6_STALL);
+                BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
+                break;
+
+            case EP_ID7:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP7_STALL);
+                BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
+                break;
+
+            default:
+                break;
+        }
+    }
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_Set_EPx_OUT_Stall(USB_EP_ID epId)
+{
+    uint32_t tmpVal = 0;
+
+    if (epId == EP_ID0) {
+        tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_OUT);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_IN);
+        tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_STALL);
+        BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
+    } else {
+        switch (epId) {
+            case EP_ID1:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP1_NACK);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_STALL);
+                BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
+                break;
+
+            case EP_ID2:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP2_NACK);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_STALL);
+                BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
+                break;
+
+            case EP_ID3:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP3_NACK);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_STALL);
+                BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
+                break;
+
+            case EP_ID4:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP4_NACK);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_STALL);
+                BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
+                break;
+
+            case EP_ID5:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP5_NACK);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_STALL);
+                BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
+                break;
+
+            case EP_ID6:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP6_NACK);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_STALL);
+                BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
+                break;
+
+            case EP_ID7:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP7_NACK);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_STALL);
+                BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
+                break;
+
+            default:
+                break;
+        }
+    }
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_Set_EPx_Rdy(USB_EP_ID epId)
+{
+    uint32_t tmpVal = 0;
+
+    if (epId == EP_ID0) {
+        tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
+        tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_RDY);
+        tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_OUT);
+        tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_IN);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_STALL);
+        BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
+    } else {
+        switch (epId) {
+            case EP_ID1:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_RDY);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP1_STALL);
+                BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
+                break;
+
+            case EP_ID2:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_RDY);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP2_STALL);
+                BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
+                break;
+
+            case EP_ID3:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_RDY);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP3_STALL);
+                BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
+                break;
+
+            case EP_ID4:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_RDY);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP4_STALL);
+                BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
+                break;
+
+            case EP_ID5:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_RDY);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP5_STALL);
+                BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
+                break;
+
+            case EP_ID6:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_RDY);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP6_STALL);
+                BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
+                break;
+
+            case EP_ID7:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_RDY);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP7_STALL);
+                BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
+                break;
+
+            default:
+                break;
+        }
+    }
+
+    return SUCCESS;
+}
+
+BL_Sts_Type USB_Is_EPx_RDY_Free(USB_EP_ID epId)
+{
+    uint32_t tmpVal = 0;
+
+    if (epId == EP_ID0) {
+        tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
+        tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_STS_USB_EP0_SW_RDY);
+    } else {
+        switch (epId) {
+            case EP_ID1:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_STS_EP1_RDY);
+                break;
+
+            case EP_ID2:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_STS_EP2_RDY);
+                break;
+
+            case EP_ID3:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_STS_EP3_RDY);
+                break;
+
+            case EP_ID4:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_STS_EP4_RDY);
+                break;
+
+            case EP_ID5:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_STS_EP5_RDY);
+                break;
+
+            case EP_ID6:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_STS_EP6_RDY);
+                break;
+
+            case EP_ID7:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_STS_EP7_RDY);
+                break;
+
+            default:
+                break;
+        }
+    }
+
+    return tmpVal ? RESET : SET;
+}
+
+BL_Err_Type USB_Set_EPx_STALL(USB_EP_ID epId)
+{
+    uint32_t tmpVal = 0;
+
+    if (epId == EP_ID0) {
+        tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
+        tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_STALL);
+        BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
+    } else {
+        switch (epId) {
+            case EP_ID1:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_STALL);
+                BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
+                break;
+
+            case EP_ID2:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_STALL);
+                BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
+                break;
+
+            case EP_ID3:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_STALL);
+                BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
+                break;
+
+            case EP_ID4:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_STALL);
+                BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
+                break;
+
+            case EP_ID5:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_STALL);
+                BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
+                break;
+
+            case EP_ID6:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_STALL);
+                BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
+                break;
+
+            case EP_ID7:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_STALL);
+                BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
+                break;
+
+            default:
+                break;
+        }
+    }
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_Clr_EPx_STALL(USB_EP_ID epId)
+{
+    uint32_t tmpVal = 0;
+
+    if (epId == EP_ID0) {
+        return SUCCESS;
+    } else {
+        switch (epId) {
+            case EP_ID1:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP1_STALL);
+                BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
+                break;
+
+            case EP_ID2:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP2_STALL);
+                BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
+                break;
+
+            case EP_ID3:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP3_STALL);
+                BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
+                break;
+
+            case EP_ID4:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP4_STALL);
+                BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
+                break;
+
+            case EP_ID5:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP5_STALL);
+                BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
+                break;
+
+            case EP_ID6:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP6_STALL);
+                BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
+                break;
+
+            case EP_ID7:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP7_STALL);
+                BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
+                break;
+
+            default:
+                break;
+        }
+    }
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_Set_EPx_Busy(USB_EP_ID epId)
+{
+    uint32_t tmpVal = 0;
+
+    if (epId == EP_ID0) {
+        tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
+        tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_IN);
+        tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_OUT);
+        BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
+    } else {
+        switch (epId) {
+            case EP_ID1:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP1_STALL);
+                BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
+                break;
+
+            case EP_ID2:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP2_STALL);
+                BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
+                break;
+
+            case EP_ID3:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP3_STALL);
+                BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
+                break;
+
+            case EP_ID4:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP4_STALL);
+                BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
+                break;
+
+            case EP_ID5:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP5_STALL);
+                BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
+                break;
+
+            case EP_ID6:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP6_STALL);
+                BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
+                break;
+
+            case EP_ID7:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_NACK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP7_STALL);
+                BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
+                break;
+
+            default:
+                break;
+        }
+    }
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_Set_EPx_Status(USB_EP_ID epId, USB_EP_STATUS_Type sts)
+{
+    switch (sts) {
+        case USB_EP_STATUS_ACK:
+            USB_Set_EPx_Rdy(epId);
+            break;
+
+        case USB_EP_STATUS_NACK:
+            USB_Set_EPx_Busy(epId);
+            break;
+
+        case USB_EP_STATUS_STALL:
+            USB_Set_EPx_STALL(epId);
+            break;
+
+        case USB_EP_STATUS_NSTALL:
+            USB_Clr_EPx_STALL(epId);
+            break;
+
+        default:
+            break;
+    }
+
+    return SUCCESS;
+}
+
+USB_EP_STATUS_Type USB_Get_EPx_Status(USB_EP_ID epId)
+{
+    uint32_t tmpVal = 0;
+
+    if (epId == EP_ID0) {
+        tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
+
+        switch ((tmpVal >> 24) & 0x7) {
+            case 0:
+                return USB_EP_STATUS_ACK;
+
+            case 1:
+                return USB_EP_STATUS_STALL;
+
+            case 2:
+            case 4:
+            case 6:
+                return USB_EP_STATUS_NACK;
+
+            default:
+                break;
+        }
+    } else {
+        switch (epId) {
+            case EP_ID1:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
+                break;
+
+            case EP_ID2:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
+                break;
+
+            case EP_ID3:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
+                break;
+
+            case EP_ID4:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
+                break;
+
+            case EP_ID5:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
+                break;
+
+            case EP_ID6:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
+                break;
+
+            case EP_ID7:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
+                break;
+
+            default:
+                tmpVal = 0;
+                break;
+        }
+
+        switch ((tmpVal >> 14) & 0x3) {
+            case 0:
+                return USB_EP_STATUS_ACK;
+
+            case 1:
+                return USB_EP_STATUS_STALL;
+
+            case 2:
+                return USB_EP_STATUS_NACK;
+
+            case 3:
+            default:
+                break;
+        }
+    }
+
+    return USB_EP_STATUS_NSTALL;
+}
+
+BL_Err_Type USB_IntEn(USB_INT_Type intType, uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    if (USB_INT_ALL == intType) {
+        if (enable) {
+            BL_WR_REG(USB_BASE, USB_INT_EN, USB_INT_TYPE_ALL);
+        } else {
+            BL_WR_REG(USB_BASE, USB_INT_EN, ~USB_INT_TYPE_ALL);
+        }
+
+        return SUCCESS;
+    }
+
+    tmpVal = BL_RD_REG(USB_BASE, USB_INT_EN);
+
+    if (enable) {
+        tmpVal |= (1 << intType);
+    } else {
+        tmpVal &= ~(1 << intType);
+    }
+
+    BL_WR_REG(USB_BASE, USB_INT_EN, tmpVal);
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_IntMask(USB_INT_Type intType, BL_Mask_Type intMask)
+{
+    uint32_t tmpVal = 0;
+
+    if (USB_INT_ALL == intType) {
+        if (intMask != UNMASK) {
+            BL_WR_REG(USB_BASE, USB_INT_MASK, USB_INT_TYPE_ALL);
+        } else {
+            BL_WR_REG(USB_BASE, USB_INT_MASK, ~USB_INT_TYPE_ALL);
+        }
+
+        return SUCCESS;
+    }
+
+    tmpVal = BL_RD_REG(USB_BASE, USB_INT_MASK);
+
+    if (intMask != UNMASK) {
+        tmpVal |= (1 << intType);
+    } else {
+        tmpVal &= ~(1 << intType);
+    }
+
+    BL_WR_REG(USB_BASE, USB_INT_MASK, tmpVal);
+
+    return SUCCESS;
+}
+
+BL_Sts_Type USB_Get_IntStatus(USB_INT_Type intType)
+{
+    if (USB_INT_ALL == intType) {
+        return BL_RD_REG(USB_BASE, USB_INT_STS) ? SET : RESET;
+    }
+
+    return ((BL_RD_REG(USB_BASE, USB_INT_STS) & (1 << intType))) ? SET : RESET;
+}
+
+BL_Err_Type USB_Clr_IntStatus(USB_INT_Type intType)
+{
+    uint32_t tmpVal = 0;
+
+    if (USB_INT_ALL == intType) {
+        BL_WR_REG(USB_BASE, USB_INT_CLEAR, USB_INT_TYPE_ALL);
+
+        return SUCCESS;
+    }
+
+    tmpVal = BL_RD_REG(USB_BASE, USB_INT_CLEAR);
+    tmpVal |= (1 << intType);
+    BL_WR_REG(USB_BASE, USB_INT_CLEAR, tmpVal);
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_Clr_EPx_IntStatus(USB_EP_ID epId)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(USB_BASE, USB_INT_CLEAR);
+
+    if (epId == EP_ID0) {
+        tmpVal |= (0x3F << 4);
+    } else {
+        tmpVal |= (0x3 << (epId * 2 + 8));
+    }
+
+    BL_WR_REG(USB_BASE, USB_INT_CLEAR, tmpVal);
+
+    return SUCCESS;
+}
+
+uint16_t USB_Get_Frame_Num(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(USB_BASE, USB_FRAME_NO);
+
+    return tmpVal & 0x7ff;
+}
+
+BL_Err_Type USB_Set_EPx_Config(USB_EP_ID epId, EP_Config_Type *epCfg)
+{
+    uint32_t tmpVal = 0;
+
+    if (epId == EP_ID0) {
+        return ERROR;
+    }
+
+    switch (epId) {
+        case EP_ID1:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP1_TYPE, epCfg->type);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP1_DIR, epCfg->dir);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP1_SIZE, epCfg->EPMaxPacketSize);
+            BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
+            break;
+
+        case EP_ID2:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP2_TYPE, epCfg->type);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP2_DIR, epCfg->dir);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP2_SIZE, epCfg->EPMaxPacketSize);
+            BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
+            break;
+
+        case EP_ID3:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP3_TYPE, epCfg->type);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP3_DIR, epCfg->dir);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP3_SIZE, epCfg->EPMaxPacketSize);
+            BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
+            break;
+
+        case EP_ID4:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP4_TYPE, epCfg->type);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP4_DIR, epCfg->dir);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP4_SIZE, epCfg->EPMaxPacketSize);
+            BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
+            break;
+
+        case EP_ID5:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP5_TYPE, epCfg->type);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP5_DIR, epCfg->dir);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP5_SIZE, epCfg->EPMaxPacketSize);
+            BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
+            break;
+
+        case EP_ID6:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP6_TYPE, epCfg->type);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP6_DIR, epCfg->dir);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP6_SIZE, epCfg->EPMaxPacketSize);
+            BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
+            break;
+
+        case EP_ID7:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP7_TYPE, epCfg->type);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP7_DIR, epCfg->dir);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP7_SIZE, epCfg->EPMaxPacketSize);
+            BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
+            break;
+
+        default:
+            break;
+    }
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_Set_EPx_Type(USB_EP_ID epId, EP_XFER_Type type)
+{
+    uint32_t tmpVal = 0;
+
+    if (epId == EP_ID0) {
+        return ERROR;
+    }
+
+    switch (epId) {
+        case EP_ID1:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP1_TYPE, type);
+            BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
+            break;
+
+        case EP_ID2:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP2_TYPE, type);
+            BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
+            break;
+
+        case EP_ID3:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP3_TYPE, type);
+            BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
+            break;
+
+        case EP_ID4:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP4_TYPE, type);
+            BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
+            break;
+
+        case EP_ID5:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP5_TYPE, type);
+            BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
+            break;
+
+        case EP_ID6:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP6_TYPE, type);
+            BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
+            break;
+
+        case EP_ID7:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP7_TYPE, type);
+            BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
+            break;
+
+        default:
+            break;
+    }
+
+    return SUCCESS;
+}
+
+EP_XFER_Type USB_Get_EPx_Type(USB_EP_ID epId)
+{
+    uint32_t tmpVal = 0;
+
+    if (epId == EP_ID0) {
+        return EP_CTRL;
+    }
+
+    switch (epId) {
+        case EP_ID1:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP1_TYPE);
+            break;
+
+        case EP_ID2:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP2_TYPE);
+            break;
+
+        case EP_ID3:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP3_TYPE);
+            break;
+
+        case EP_ID4:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP4_TYPE);
+            break;
+
+        case EP_ID5:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP5_TYPE);
+            break;
+
+        case EP_ID6:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP6_TYPE);
+            break;
+
+        case EP_ID7:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP7_TYPE);
+            break;
+
+        default:
+            break;
+    }
+
+    return (EP_XFER_Type)tmpVal;
+}
+
+BL_Err_Type USB_Set_EPx_Dir(USB_EP_ID epId, EP_XFER_DIR dir)
+{
+    uint32_t tmpVal = 0;
+
+    if (epId == EP_ID0) {
+        return ERROR;
+    }
+
+    switch (epId) {
+        case EP_ID1:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP1_DIR, dir);
+            BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
+            break;
+
+        case EP_ID2:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP2_DIR, dir);
+            BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
+            break;
+
+        case EP_ID3:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP3_DIR, dir);
+            BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
+            break;
+
+        case EP_ID4:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP4_DIR, dir);
+            BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
+            break;
+
+        case EP_ID5:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP5_DIR, dir);
+            BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
+            break;
+
+        case EP_ID6:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP6_DIR, dir);
+            BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
+            break;
+
+        case EP_ID7:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP7_DIR, dir);
+            BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
+            break;
+
+        default:
+            break;
+    }
+
+    return SUCCESS;
+}
+
+EP_XFER_DIR USB_Get_EPx_Dir(USB_EP_ID epId)
+{
+    uint32_t tmpVal = 0;
+
+    if (epId == EP_ID0) {
+        return EP_DISABLED;
+    }
+
+    switch (epId) {
+        case EP_ID1:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP1_DIR);
+            break;
+
+        case EP_ID2:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP2_DIR);
+            break;
+
+        case EP_ID3:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP3_DIR);
+            break;
+
+        case EP_ID4:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP4_DIR);
+            break;
+
+        case EP_ID5:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP5_DIR);
+            break;
+
+        case EP_ID6:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP6_DIR);
+            break;
+
+        case EP_ID7:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP7_DIR);
+            break;
+
+        default:
+            break;
+    }
+
+    return (EP_XFER_DIR)tmpVal;
+}
+
+BL_Err_Type USB_Set_EPx_Size(USB_EP_ID epId, uint32_t size)
+{
+    uint32_t tmpVal = 0;
+
+    switch (epId) {
+        case EP_ID0:
+            tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_EP0_SW_SIZE, size);
+            BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
+            break;
+
+        case EP_ID1:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP1_SIZE, size);
+            BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
+            break;
+
+        case EP_ID2:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP2_SIZE, size);
+            BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
+            break;
+
+        case EP_ID3:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP3_SIZE, size);
+            BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
+            break;
+
+        case EP_ID4:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP4_SIZE, size);
+            BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
+            break;
+
+        case EP_ID5:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP5_SIZE, size);
+            BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
+            break;
+
+        case EP_ID6:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP6_SIZE, size);
+            BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
+            break;
+
+        case EP_ID7:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP7_SIZE, size);
+            BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
+            break;
+
+        default:
+            break;
+    }
+
+    return SUCCESS;
+}
+
+BL_Sts_Type USB_Get_EPx_TX_FIFO_Errors(USB_EP_ID epId, USB_FIFO_ERROR_FLAG_Type errFlag)
+{
+    uint32_t tmpVal = 0;
+
+    if (errFlag == USB_FIFO_ERROR_OVERFLOW) {
+        switch (epId) {
+            case EP_ID0:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_TX_FIFO_OVERFLOW);
+                break;
+
+            case EP_ID1:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_TX_FIFO_OVERFLOW);
+                break;
+
+            case EP_ID2:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_TX_FIFO_OVERFLOW);
+                break;
+
+            case EP_ID3:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_TX_FIFO_OVERFLOW);
+                break;
+
+            case EP_ID4:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_TX_FIFO_OVERFLOW);
+                break;
+
+            case EP_ID5:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_TX_FIFO_OVERFLOW);
+                break;
+
+            case EP_ID6:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_TX_FIFO_OVERFLOW);
+                break;
+
+            case EP_ID7:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_TX_FIFO_OVERFLOW);
+                break;
+
+            default:
+                tmpVal = 0;
+                break;
+        }
+    } else {
+        switch (epId) {
+            case EP_ID0:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_TX_FIFO_UNDERFLOW);
+                break;
+
+            case EP_ID1:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_TX_FIFO_UNDERFLOW);
+                break;
+
+            case EP_ID2:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_TX_FIFO_UNDERFLOW);
+                break;
+
+            case EP_ID3:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_TX_FIFO_UNDERFLOW);
+                break;
+
+            case EP_ID4:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_TX_FIFO_UNDERFLOW);
+                break;
+
+            case EP_ID5:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_TX_FIFO_UNDERFLOW);
+                break;
+
+            case EP_ID6:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_TX_FIFO_UNDERFLOW);
+                break;
+
+            case EP_ID7:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_TX_FIFO_UNDERFLOW);
+                break;
+
+            default:
+                tmpVal = 0;
+                break;
+        }
+    }
+
+    return tmpVal ? SET : RESET;
+}
+
+BL_Sts_Type USB_Get_EPx_RX_FIFO_Errors(USB_EP_ID epId, USB_FIFO_ERROR_FLAG_Type errFlag)
+{
+    uint32_t tmpVal = 0;
+
+    if (errFlag == USB_FIFO_ERROR_OVERFLOW) {
+        switch (epId) {
+            case EP_ID0:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_RX_FIFO_OVERFLOW);
+                break;
+
+            case EP_ID1:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_RX_FIFO_OVERFLOW);
+                break;
+
+            case EP_ID2:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_RX_FIFO_OVERFLOW);
+                break;
+
+            case EP_ID3:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_RX_FIFO_OVERFLOW);
+                break;
+
+            case EP_ID4:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_RX_FIFO_OVERFLOW);
+                break;
+
+            case EP_ID5:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_RX_FIFO_OVERFLOW);
+                break;
+
+            case EP_ID6:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_RX_FIFO_OVERFLOW);
+                break;
+
+            case EP_ID7:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_RX_FIFO_OVERFLOW);
+                break;
+
+            default:
+                tmpVal = 0;
+                break;
+        }
+    } else {
+        switch (epId) {
+            case EP_ID0:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_RX_FIFO_UNDERFLOW);
+                break;
+
+            case EP_ID1:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_RX_FIFO_UNDERFLOW);
+                break;
+
+            case EP_ID2:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_RX_FIFO_UNDERFLOW);
+                break;
+
+            case EP_ID3:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_RX_FIFO_UNDERFLOW);
+                break;
+
+            case EP_ID4:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_RX_FIFO_UNDERFLOW);
+                break;
+
+            case EP_ID5:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_RX_FIFO_UNDERFLOW);
+                break;
+
+            case EP_ID6:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_RX_FIFO_UNDERFLOW);
+                break;
+
+            case EP_ID7:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_RX_FIFO_UNDERFLOW);
+                break;
+
+            default:
+                tmpVal = 0;
+                break;
+        }
+    }
+
+    return tmpVal ? SET : RESET;
+}
+
+BL_Err_Type USB_Clr_EPx_TX_FIFO_Errors(USB_EP_ID epId)
+{
+    uint32_t tmpVal = 0;
+
+    switch (epId) {
+        case EP_ID0:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP0_TX_FIFO_CLR);
+            BL_WR_REG(USB_BASE, USB_EP0_FIFO_CONFIG, tmpVal);
+            break;
+
+        case EP_ID1:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP1_TX_FIFO_CLR);
+            BL_WR_REG(USB_BASE, USB_EP1_FIFO_CONFIG, tmpVal);
+            break;
+
+        case EP_ID2:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP2_TX_FIFO_CLR);
+            BL_WR_REG(USB_BASE, USB_EP2_FIFO_CONFIG, tmpVal);
+            break;
+
+        case EP_ID3:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP3_TX_FIFO_CLR);
+            BL_WR_REG(USB_BASE, USB_EP3_FIFO_CONFIG, tmpVal);
+            break;
+
+        case EP_ID4:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP4_TX_FIFO_CLR);
+            BL_WR_REG(USB_BASE, USB_EP4_FIFO_CONFIG, tmpVal);
+            break;
+
+        case EP_ID5:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP5_TX_FIFO_CLR);
+            BL_WR_REG(USB_BASE, USB_EP5_FIFO_CONFIG, tmpVal);
+            break;
+
+        case EP_ID6:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP6_TX_FIFO_CLR);
+            BL_WR_REG(USB_BASE, USB_EP6_FIFO_CONFIG, tmpVal);
+            break;
+
+        case EP_ID7:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP7_TX_FIFO_CLR);
+            BL_WR_REG(USB_BASE, USB_EP7_FIFO_CONFIG, tmpVal);
+            break;
+
+        default:
+            break;
+    }
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_Clr_EPx_RX_FIFO_Errors(USB_EP_ID epId)
+{
+    uint32_t tmpVal = 0;
+
+    switch (epId) {
+        case EP_ID0:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP0_RX_FIFO_CLR);
+            BL_WR_REG(USB_BASE, USB_EP0_FIFO_CONFIG, tmpVal);
+            break;
+
+        case EP_ID1:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP1_RX_FIFO_CLR);
+            BL_WR_REG(USB_BASE, USB_EP1_FIFO_CONFIG, tmpVal);
+            break;
+
+        case EP_ID2:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP2_RX_FIFO_CLR);
+            BL_WR_REG(USB_BASE, USB_EP2_FIFO_CONFIG, tmpVal);
+            break;
+
+        case EP_ID3:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP3_RX_FIFO_CLR);
+            BL_WR_REG(USB_BASE, USB_EP3_FIFO_CONFIG, tmpVal);
+            break;
+
+        case EP_ID4:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP4_RX_FIFO_CLR);
+            BL_WR_REG(USB_BASE, USB_EP4_FIFO_CONFIG, tmpVal);
+            break;
+
+        case EP_ID5:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP5_RX_FIFO_CLR);
+            BL_WR_REG(USB_BASE, USB_EP5_FIFO_CONFIG, tmpVal);
+            break;
+
+        case EP_ID6:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP6_RX_FIFO_CLR);
+            BL_WR_REG(USB_BASE, USB_EP6_FIFO_CONFIG, tmpVal);
+            break;
+
+        case EP_ID7:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG);
+            tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP7_RX_FIFO_CLR);
+            BL_WR_REG(USB_BASE, USB_EP7_FIFO_CONFIG, tmpVal);
+            break;
+
+        default:
+            break;
+    }
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_EPx_Write_Data_To_FIFO(USB_EP_ID epId, uint8_t *pData, uint16_t len)
+{
+    uint32_t timeout = 0x00FFFFFF;
+
+    while ((!USB_Is_EPx_RDY_Free(epId)) && timeout) {
+        timeout--;
+    }
+
+    if (!timeout) {
+        return ERROR;
+    }
+
+    if (len == 1) {
+        USB_Set_EPx_Xfer_Size(EP_ID0, 1);
+    } else {
+        USB_Set_EPx_Xfer_Size(EP_ID0, 64);
+    }
+
+    for (uint16_t i = 0; i < len; i++) {
+        switch (epId) {
+            case EP_ID0:
+                BL_WR_REG(USB_BASE, USB_EP0_TX_FIFO_WDATA, pData[i]);
+                break;
+
+            case EP_ID1:
+                BL_WR_REG(USB_BASE, USB_EP1_TX_FIFO_WDATA, pData[i]);
+                break;
+
+            case EP_ID2:
+                BL_WR_REG(USB_BASE, USB_EP2_TX_FIFO_WDATA, pData[i]);
+                break;
+
+            case EP_ID3:
+                BL_WR_REG(USB_BASE, USB_EP3_TX_FIFO_WDATA, pData[i]);
+                break;
+
+            case EP_ID4:
+                BL_WR_REG(USB_BASE, USB_EP4_TX_FIFO_WDATA, pData[i]);
+                break;
+
+            case EP_ID5:
+                BL_WR_REG(USB_BASE, USB_EP5_TX_FIFO_WDATA, pData[i]);
+                break;
+
+            case EP_ID6:
+                BL_WR_REG(USB_BASE, USB_EP6_TX_FIFO_WDATA, pData[i]);
+                break;
+
+            case EP_ID7:
+                BL_WR_REG(USB_BASE, USB_EP7_TX_FIFO_WDATA, pData[i]);
+                break;
+
+            default:
+                break;
+        }
+    }
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_EPx_Read_Data_From_FIFO(USB_EP_ID epId, uint8_t *pBuff, uint16_t len)
+{
+    for (uint16_t i = 0; i < len; i++) {
+        switch (epId) {
+            case EP_ID0:
+                pBuff[i] = (uint8_t)BL_RD_REG(USB_BASE, USB_EP0_RX_FIFO_RDATA);
+                break;
+
+            case EP_ID1:
+                pBuff[i] = (uint8_t)BL_RD_REG(USB_BASE, USB_EP1_RX_FIFO_RDATA);
+                break;
+
+            case EP_ID2:
+                pBuff[i] = (uint8_t)BL_RD_REG(USB_BASE, USB_EP2_RX_FIFO_RDATA);
+                break;
+
+            case EP_ID3:
+                pBuff[i] = (uint8_t)BL_RD_REG(USB_BASE, USB_EP3_RX_FIFO_RDATA);
+                break;
+
+            case EP_ID4:
+                pBuff[i] = (uint8_t)BL_RD_REG(USB_BASE, USB_EP4_RX_FIFO_RDATA);
+                break;
+
+            case EP_ID5:
+                pBuff[i] = (uint8_t)BL_RD_REG(USB_BASE, USB_EP5_RX_FIFO_RDATA);
+                break;
+
+            case EP_ID6:
+                pBuff[i] = (uint8_t)BL_RD_REG(USB_BASE, USB_EP6_RX_FIFO_RDATA);
+                break;
+
+            case EP_ID7:
+                pBuff[i] = (uint8_t)BL_RD_REG(USB_BASE, USB_EP7_RX_FIFO_RDATA);
+                break;
+
+            default:
+                break;
+        }
+    }
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_Set_EPx_TX_DMA_Interface_Config(USB_EP_ID epId, BL_Fun_Type newState)
+{
+    uint32_t tmpVal = 0;
+
+    if (newState == ENABLE) {
+        switch (epId) {
+            case EP_ID0:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP0_DMA_TX_EN);
+                BL_WR_REG(USB_BASE, USB_EP0_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID1:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP1_DMA_TX_EN);
+                BL_WR_REG(USB_BASE, USB_EP1_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID2:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP2_DMA_TX_EN);
+                BL_WR_REG(USB_BASE, USB_EP2_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID3:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP3_DMA_TX_EN);
+                BL_WR_REG(USB_BASE, USB_EP3_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID4:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP4_DMA_TX_EN);
+                BL_WR_REG(USB_BASE, USB_EP4_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID5:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP5_DMA_TX_EN);
+                BL_WR_REG(USB_BASE, USB_EP5_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID6:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP6_DMA_TX_EN);
+                BL_WR_REG(USB_BASE, USB_EP6_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID7:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP7_DMA_TX_EN);
+                BL_WR_REG(USB_BASE, USB_EP7_FIFO_CONFIG, tmpVal);
+                break;
+
+            default:
+                break;
+        }
+    } else {
+        switch (epId) {
+            case EP_ID0:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP0_DMA_TX_EN);
+                BL_WR_REG(USB_BASE, USB_EP0_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID1:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP1_DMA_TX_EN);
+                BL_WR_REG(USB_BASE, USB_EP1_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID2:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP2_DMA_TX_EN);
+                BL_WR_REG(USB_BASE, USB_EP2_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID3:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP3_DMA_TX_EN);
+                BL_WR_REG(USB_BASE, USB_EP3_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID4:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP4_DMA_TX_EN);
+                BL_WR_REG(USB_BASE, USB_EP4_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID5:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP5_DMA_TX_EN);
+                BL_WR_REG(USB_BASE, USB_EP5_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID6:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP6_DMA_TX_EN);
+                BL_WR_REG(USB_BASE, USB_EP6_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID7:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP7_DMA_TX_EN);
+                BL_WR_REG(USB_BASE, USB_EP7_FIFO_CONFIG, tmpVal);
+                break;
+
+            default:
+                break;
+        }
+    }
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_Set_EPx_RX_DMA_Interface_Config(USB_EP_ID epId, BL_Fun_Type newState)
+{
+    uint32_t tmpVal = 0;
+
+    if (newState == ENABLE) {
+        switch (epId) {
+            case EP_ID0:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP0_DMA_RX_EN);
+                BL_WR_REG(USB_BASE, USB_EP0_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID1:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP1_DMA_RX_EN);
+                BL_WR_REG(USB_BASE, USB_EP1_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID2:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP2_DMA_RX_EN);
+                BL_WR_REG(USB_BASE, USB_EP2_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID3:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP3_DMA_RX_EN);
+                BL_WR_REG(USB_BASE, USB_EP3_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID4:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP4_DMA_RX_EN);
+                BL_WR_REG(USB_BASE, USB_EP4_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID5:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP5_DMA_RX_EN);
+                BL_WR_REG(USB_BASE, USB_EP5_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID6:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP6_DMA_RX_EN);
+                BL_WR_REG(USB_BASE, USB_EP6_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID7:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG);
+                tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP7_DMA_RX_EN);
+                BL_WR_REG(USB_BASE, USB_EP7_FIFO_CONFIG, tmpVal);
+                break;
+
+            default:
+                break;
+        }
+    } else {
+        switch (epId) {
+            case EP_ID0:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP0_DMA_RX_EN);
+                BL_WR_REG(USB_BASE, USB_EP0_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID1:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP1_DMA_RX_EN);
+                BL_WR_REG(USB_BASE, USB_EP1_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID2:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP2_DMA_RX_EN);
+                BL_WR_REG(USB_BASE, USB_EP2_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID3:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP3_DMA_RX_EN);
+                BL_WR_REG(USB_BASE, USB_EP3_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID4:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP4_DMA_RX_EN);
+                BL_WR_REG(USB_BASE, USB_EP4_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID5:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP5_DMA_RX_EN);
+                BL_WR_REG(USB_BASE, USB_EP5_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID6:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP6_DMA_RX_EN);
+                BL_WR_REG(USB_BASE, USB_EP6_FIFO_CONFIG, tmpVal);
+                break;
+
+            case EP_ID7:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP7_DMA_RX_EN);
+                BL_WR_REG(USB_BASE, USB_EP7_FIFO_CONFIG, tmpVal);
+                break;
+
+            default:
+                break;
+        }
+    }
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_EPx_Write_Data_To_FIFO_DMA(USB_EP_ID epId, uint8_t *pData, uint16_t len)
+{
+    /* not yet implemented */
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_EPx_Read_Data_From_FIFO_DMA(USB_EP_ID epId, uint8_t *pBuff, uint16_t len)
+{
+    /* not yet implemented */
+
+    return SUCCESS;
+}
+
+uint16_t USB_Get_EPx_TX_FIFO_CNT(USB_EP_ID epId)
+{
+    uint32_t tmpVal = 0;
+
+    switch (epId) {
+        case EP_ID0:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_STATUS);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_TX_FIFO_CNT);
+            break;
+
+        case EP_ID1:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_STATUS);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_TX_FIFO_CNT);
+            break;
+
+        case EP_ID2:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_STATUS);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_TX_FIFO_CNT);
+            break;
+
+        case EP_ID3:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_STATUS);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_TX_FIFO_CNT);
+            break;
+
+        case EP_ID4:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_STATUS);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_TX_FIFO_CNT);
+            break;
+
+        case EP_ID5:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_STATUS);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_TX_FIFO_CNT);
+            break;
+
+        case EP_ID6:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_STATUS);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_TX_FIFO_CNT);
+            break;
+
+        case EP_ID7:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_STATUS);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_TX_FIFO_CNT);
+            break;
+
+        default:
+            tmpVal = 0;
+            break;
+    }
+
+    return tmpVal;
+}
+
+uint16_t USB_Get_EPx_RX_FIFO_CNT(USB_EP_ID epId)
+{
+    uint32_t tmpVal = 0;
+
+    switch (epId) {
+        case EP_ID0:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_STATUS);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_RX_FIFO_CNT);
+            break;
+
+        case EP_ID1:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_STATUS);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_RX_FIFO_CNT);
+            break;
+
+        case EP_ID2:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_STATUS);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_RX_FIFO_CNT);
+            break;
+
+        case EP_ID3:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_STATUS);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_RX_FIFO_CNT);
+            break;
+
+        case EP_ID4:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_STATUS);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_RX_FIFO_CNT);
+            break;
+
+        case EP_ID5:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_STATUS);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_RX_FIFO_CNT);
+            break;
+
+        case EP_ID6:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_STATUS);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_RX_FIFO_CNT);
+            break;
+
+        case EP_ID7:
+            tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_STATUS);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_RX_FIFO_CNT);
+            break;
+
+        default:
+            tmpVal = 0;
+            break;
+    }
+
+    return tmpVal;
+}
+
+BL_Sts_Type USB_Get_EPx_TX_FIFO_Status(USB_EP_ID epId, USB_FIFO_STATUS_Type sts)
+{
+    uint32_t tmpVal = 0;
+
+    if (sts == USB_FIFO_EMPTY) {
+        switch (epId) {
+            case EP_ID0:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_TX_FIFO_EMPTY);
+                break;
+
+            case EP_ID1:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_TX_FIFO_EMPTY);
+                break;
+
+            case EP_ID2:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_TX_FIFO_EMPTY);
+                break;
+
+            case EP_ID3:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_TX_FIFO_EMPTY);
+                break;
+
+            case EP_ID4:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_TX_FIFO_EMPTY);
+                break;
+
+            case EP_ID5:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_TX_FIFO_EMPTY);
+                break;
+
+            case EP_ID6:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_TX_FIFO_EMPTY);
+                break;
+
+            case EP_ID7:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_TX_FIFO_EMPTY);
+                break;
+
+            default:
+                tmpVal = 0;
+                break;
+        }
+    } else {
+        switch (epId) {
+            case EP_ID0:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_TX_FIFO_FULL);
+                break;
+
+            case EP_ID1:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_TX_FIFO_FULL);
+                break;
+
+            case EP_ID2:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_TX_FIFO_FULL);
+                break;
+
+            case EP_ID3:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_TX_FIFO_FULL);
+                break;
+
+            case EP_ID4:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_TX_FIFO_FULL);
+                break;
+
+            case EP_ID5:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_TX_FIFO_FULL);
+                break;
+
+            case EP_ID6:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_TX_FIFO_FULL);
+                break;
+
+            case EP_ID7:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_TX_FIFO_FULL);
+                break;
+
+            default:
+                tmpVal = 0;
+                break;
+        }
+    }
+
+    return tmpVal ? SET : RESET;
+}
+
+BL_Sts_Type USB_Get_EPx_RX_FIFO_Status(USB_EP_ID epId, USB_FIFO_STATUS_Type sts)
+{
+    uint32_t tmpVal = 0;
+
+    if (sts == USB_FIFO_EMPTY) {
+        switch (epId) {
+            case EP_ID0:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_RX_FIFO_EMPTY);
+                break;
+
+            case EP_ID1:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_RX_FIFO_EMPTY);
+                break;
+
+            case EP_ID2:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_RX_FIFO_EMPTY);
+                break;
+
+            case EP_ID3:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_RX_FIFO_EMPTY);
+                break;
+
+            case EP_ID4:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_RX_FIFO_EMPTY);
+                break;
+
+            case EP_ID5:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_RX_FIFO_EMPTY);
+                break;
+
+            case EP_ID6:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_RX_FIFO_EMPTY);
+                break;
+
+            case EP_ID7:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_RX_FIFO_EMPTY);
+                break;
+
+            default:
+                tmpVal = 0;
+                break;
+        }
+    } else {
+        switch (epId) {
+            case EP_ID0:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_RX_FIFO_FULL);
+                break;
+
+            case EP_ID1:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_RX_FIFO_FULL);
+                break;
+
+            case EP_ID2:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_RX_FIFO_FULL);
+                break;
+
+            case EP_ID3:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_RX_FIFO_FULL);
+                break;
+
+            case EP_ID4:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_RX_FIFO_FULL);
+                break;
+
+            case EP_ID5:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_RX_FIFO_FULL);
+                break;
+
+            case EP_ID6:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_RX_FIFO_FULL);
+                break;
+
+            case EP_ID7:
+                tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_STATUS);
+                tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_RX_FIFO_FULL);
+                break;
+
+            default:
+                tmpVal = 0;
+                break;
+        }
+    }
+
+    return tmpVal ? SET : RESET;
+}
+
+BL_Err_Type USB_Set_Internal_PullUp_Config(BL_Fun_Type newState)
+{
+    uint32_t tmpVal = 0;
+
+    /* recommended: fclk<=160MHz, bclk<=80MHz */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ENUM, newState);
+    BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal);
+
+    return SUCCESS;
+}
+
+BL_Sts_Type USB_Get_LPM_Status(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(USB_BASE, USB_LPM_CONFIG);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, USB_STS_LPM) ? SET : RESET;
+}
+
+uint16_t USB_Get_LPM_Packet_Attr(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(USB_BASE, USB_LPM_CONFIG);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, USB_STS_LPM_ATTR);
+}
+
+BL_Err_Type USB_Set_LPM_Default_Response(USB_LPM_DEFAULT_RESP_Type defaultResp)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(USB_BASE, USB_LPM_CONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_LPM_RESP, defaultResp);
+    BL_WR_REG(USB_BASE, USB_LPM_CONFIG, tmpVal);
+
+    tmpVal = BL_RD_REG(USB_BASE, USB_LPM_CONFIG);
+    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_LPM_RESP_UPD);
+    BL_WR_REG(USB_BASE, USB_LPM_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_LPM_Enable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(USB_BASE, USB_LPM_CONFIG);
+    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_LPM_EN);
+    BL_WR_REG(USB_BASE, USB_LPM_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_LPM_Disable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(USB_BASE, USB_LPM_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_LPM_EN);
+    BL_WR_REG(USB_BASE, USB_LPM_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_Device_Output_K_State(uint16_t stateWidth)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((stateWidth <= 0x7FF));
+
+    tmpVal = BL_RD_REG(USB_BASE, USB_RESUME_CONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_RES_WIDTH, stateWidth);
+    BL_WR_REG(USB_BASE, USB_RESUME_CONFIG, tmpVal);
+
+    tmpVal = BL_RD_REG(USB_BASE, USB_RESUME_CONFIG);
+    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_RES_TRIG);
+    BL_WR_REG(USB_BASE, USB_RESUME_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+
+uint8_t USB_Get_Current_Packet_PID(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(USB_BASE, USB_FRAME_NO);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, USB_STS_PID);
+}
+
+uint8_t USB_Get_Current_Packet_EP(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(USB_BASE, USB_FRAME_NO);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, USB_STS_EP_NO);
+}
+
+BL_Sts_Type USB_Get_Error_Status(USB_ERROR_Type err)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(USB_BASE, USB_ERROR);
+
+    return tmpVal & (1 << err) ? SET : RESET;
+}
+
+BL_Err_Type USB_Clr_Error_Status(USB_ERROR_Type err)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(USB_BASE, USB_INT_CLEAR);
+    tmpVal |= (1 << USB_INT_ERROR);
+    BL_WR_REG(USB_BASE, USB_INT_CLEAR, tmpVal);
+
+    return SUCCESS;
+}
+
+BL_Err_Type USB_Clr_RstEndIntStatus(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(USB_BASE, USB_INT_CLEAR);
+    tmpVal |= (1 << 27);
+    BL_WR_REG(USB_BASE, USB_INT_CLEAR, tmpVal);
+
+    return SUCCESS;
+}
+
+/*@} end of group USB_Public_Functions */
+
+/*@} end of group USB */
+
+/*@} end of group BL70X_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_xip_sflash.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_xip_sflash.c
new file mode 100644
index 00000000..23c28a63
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_xip_sflash.c
@@ -0,0 +1,404 @@
+/**
+  ******************************************************************************
+  * @file    bl702_xip_sflash.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "string.h"
+#include "bl702_xip_sflash.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  XIP_SFLASH
+ *  @{
+ */
+
+/** @defgroup  XIP_SFLASH_Private_Macros
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_Private_Macros */
+
+/** @defgroup  XIP_SFLASH_Private_Types
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_Private_Types */
+
+/** @defgroup  XIP_SFLASH_Private_Variables
+ *  @{
+ */
+static uint8_t aesEnable;
+
+/*@} end of group XIP_SFLASH_Private_Variables */
+
+/** @defgroup  XIP_SFLASH_Global_Variables
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_Global_Variables */
+
+/** @defgroup  XIP_SFLASH_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_Private_Fun_Declaration */
+
+/** @defgroup  XIP_SFLASH_Private_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  XIP SFlash option save
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION XIP_SFlash_Opt_Enter(void)
+{
+    aesEnable = SF_Ctrl_Is_AES_Enable();
+
+    if (aesEnable) {
+        SF_Ctrl_AES_Disable();
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  XIP SFlash option restore
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION XIP_SFlash_Opt_Exit(void)
+{
+    if (aesEnable) {
+        SF_Ctrl_AES_Enable();
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Save flash controller state
+ *
+ * @param  pFlashCfg: Flash config pointer
+ * @param  offset: CPU XIP flash offset pointer
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset)
+{
+    /* XIP_SFlash_Delay */
+    volatile uint32_t i = 32 * 2;
+
+    while (i--)
+        ;
+
+    SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
+    /* Exit form continous read for accepting command */
+    SFlash_Reset_Continue_Read(pFlashCfg);
+    /* Send software reset command(80bv has no this command)to deburst wrap for ISSI like */
+    SFlash_Software_Reset(pFlashCfg);
+    /* For disable command that is setting register instaed of send command, we need write enable */
+    SFlash_DisableBurstWrap(pFlashCfg);
+    /* Enable QE again in case reset command make it reset */
+    SFlash_Qspi_Enable(pFlashCfg);
+    /* Deburst again to make sure */
+    SFlash_DisableBurstWrap(pFlashCfg);
+
+    /* Clear offset setting*/
+    *offset = SF_Ctrl_Get_Flash_Image_Offset();
+    SF_Ctrl_Set_Flash_Image_Offset(0);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Restore flash controller state
+ *
+ * @param  pFlashCfg: Flash config pointer
+ * @param  ioMode: flash controller interface mode
+ * @param  offset: CPU XIP flash offset
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t offset)
+{
+    uint32_t tmp[1];
+
+    SF_Ctrl_Set_Flash_Image_Offset(offset);
+
+    SFlash_SetBurstWrap(pFlashCfg);
+    SFlash_Read(pFlashCfg, ioMode, 1, 0x0, (uint8_t *)tmp, sizeof(tmp));
+    SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
+
+    return SUCCESS;
+}
+#endif
+
+/*@} end of group XIP_SFLASH_Private_Functions */
+
+/** @defgroup  XIP_SFLASH_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Erase flash one region
+ *
+ * @param  pFlashCfg: Flash config pointer
+ * @param  ioMode: flash controller interface mode
+ * @param  startaddr: start address to erase
+ * @param  endaddr: end address(include this address) to erase
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t startaddr, uint32_t endaddr)
+{
+    BL_Err_Type stat;
+    uint32_t offset;
+
+    stat = XIP_SFlash_State_Save(pFlashCfg, &offset);
+
+    if (stat != SUCCESS) {
+        SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
+    } else {
+        stat = SFlash_Erase(pFlashCfg, startaddr, endaddr);
+        XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset);
+    }
+
+    return stat;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Program flash one region
+ *
+ * @param  pFlashCfg: Flash config pointer
+ * @param  ioMode: flash controller interface mode
+ * @param  addr: start address to be programed
+ * @param  data: data pointer to be programed
+ * @param  len: data length to be programed
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len)
+{
+    BL_Err_Type stat;
+    uint32_t offset;
+
+    stat = XIP_SFlash_State_Save(pFlashCfg, &offset);
+
+    if (stat != SUCCESS) {
+        SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
+    } else {
+        stat = SFlash_Program(pFlashCfg, ioMode, addr, data, len);
+        XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset);
+    }
+
+    return stat;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Read data from flash
+ *
+ * @param  pFlashCfg: Flash config pointer
+ * @param  ioMode: flash controller interface mode
+ * @param  addr: flash read start address
+ * @param  data: data pointer to store data read from flash
+ * @param  len: data length to read
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len)
+{
+    BL_Err_Type stat;
+    uint32_t offset;
+
+    stat = XIP_SFlash_State_Save(pFlashCfg, &offset);
+
+    if (stat != SUCCESS) {
+        SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
+    } else {
+        stat = SFlash_Read(pFlashCfg, ioMode, 0, addr, data, len);
+        XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset);
+    }
+
+    return stat;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Get Flash Jedec ID
+ *
+ * @param  pFlashCfg: Flash config pointer
+ * @param  ioMode: flash controller interface mode
+ * @param  data: data pointer to store Jedec ID Read from flash
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t *data)
+{
+    BL_Err_Type stat;
+    uint32_t offset;
+
+    stat = XIP_SFlash_State_Save(pFlashCfg, &offset);
+
+    if (stat != SUCCESS) {
+        SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
+    } else {
+        SFlash_GetJedecId(pFlashCfg, data);
+        XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset);
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Get Flash Device ID
+ *
+ * @param  pFlashCfg: Flash config pointer
+ * @param  ioMode: flash controller interface mode
+ * @param  data: data pointer to store Device ID Read from flash
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t *data)
+{
+    BL_Err_Type stat;
+    uint32_t offset;
+
+    stat = XIP_SFlash_State_Save(pFlashCfg, &offset);
+
+    if (stat != SUCCESS) {
+        SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
+    } else {
+        SFlash_GetDeviceId(data);
+        XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset);
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Get Flash Unique ID
+ *
+ * @param  pFlashCfg: Flash config pointer
+ * @param  ioMode: flash controller interface mode
+ * @param  data: data pointer to store Device ID Read from flash
+ * @param  idLen: Unique id len
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t *data, uint8_t idLen)
+{
+    BL_Err_Type stat;
+    uint32_t offset;
+
+    stat = XIP_SFlash_State_Save(pFlashCfg, &offset);
+
+    if (stat != SUCCESS) {
+        SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
+    } else {
+        SFlash_GetUniqueId(data, idLen);
+        XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset);
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Read data from flash via XIP
+ *
+ * @param  addr: flash read start address
+ * @param  data: data pointer to store data read from flash
+ * @param  len: data length to read
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len)
+{
+    uint32_t offset;
+
+    if (addr >= BL702_FLASH_XIP_BASE && addr < BL702_FLASH_XIP_END) {
+        offset = SF_Ctrl_Get_Flash_Image_Offset();
+        SF_Ctrl_Set_Flash_Image_Offset(0);
+        /* Flash read */
+        BL702_MemCpy_Fast(data, (void *)(addr - SF_Ctrl_Get_Flash_Image_Offset()), len);
+        SF_Ctrl_Set_Flash_Image_Offset(offset);
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/*@} end of group XIP_SFLASH_Public_Functions */
+
+/*@} end of group XIP_SFLASH */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_xip_sflash_ext.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_xip_sflash_ext.c
new file mode 100644
index 00000000..2f75785d
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_xip_sflash_ext.c
@@ -0,0 +1,139 @@
+/**
+  ******************************************************************************
+  * @file    bl702_xip_sflash_ext.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "string.h"
+#include "bl702_xip_sflash_ext.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  XIP_SFLASH
+ *  @{
+ */
+
+/** @defgroup  XIP_SFLASH_EXT_Private_Macros
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_EXT_Private_Macros */
+
+/** @defgroup  XIP_SFLASH_EXT_Private_Types
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_EXT_Private_Types */
+
+/** @defgroup  XIP_SFLASH_EXT_Private_Variables
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_EXT_Private_Variables */
+
+/** @defgroup  XIP_SFLASH_EXT_Global_Variables
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_EXT_Global_Variables */
+
+/** @defgroup  XIP_SFLASH_EXT_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_EXT_Private_Fun_Declaration */
+
+/** @defgroup  XIP_SFLASH_EXT_Private_Functions
+ *  @{
+ */
+
+/****************************************************************************//**
+ * @brief  XIP KH25V40 flash write protect set
+ *
+ * @param  pFlashCfg: Flash config pointer
+ * @param  protect: protect area
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_KH25V40_Write_Protect_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Protect_Kh25v40_Type protect)
+{
+    BL_Err_Type stat;
+    uint32_t offset;
+    SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf;
+
+    stat = XIP_SFlash_State_Save(pFlashCfg, &offset);
+    if (stat != SUCCESS) {
+        SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
+    } else {
+        stat = SFlash_KH25V40_Write_Protect(pFlashCfg, protect);
+        XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset);
+    }
+
+    return stat;
+}
+
+/****************************************************************************//**
+ * @brief  Clear flash status register need lock
+ *
+ * @param  pFlashCfg: Flash config pointer
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Clear_Status_Register_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg)
+{
+    BL_Err_Type stat;
+    uint32_t offset;
+    SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf;
+
+    stat=XIP_SFlash_State_Save(pFlashCfg, &offset);
+    if (stat != SUCCESS) {
+        SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
+    } else {
+        stat=SFlash_Clear_Status_Register(pFlashCfg);
+        XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset);
+    }
+
+    return stat;
+}
+
+/*@} end of group XIP_SFLASH_EXT_Public_Functions */
+
+/*@} end of group XIP_SFLASH_EXT */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/source/Core/BSP/Pinecilv2/board.c b/source/Core/BSP/Pinecilv2/board.c
new file mode 100644
index 00000000..a1ef0288
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/board.c
@@ -0,0 +1,261 @@
+/**
+ * @file board.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+
+#include "bflb_platform.h"
+#include "bl702_config.h"
+#include "bl702_glb.h"
+#include "hal_gpio.h"
+
+struct pin_mux_cfg {
+  uint8_t  pin;
+  uint16_t func;
+};
+
+static const struct pin_mux_cfg af_pin_table[] = {
+#ifdef CONFIG_GPIO0_FUNC
+    {.pin = GPIO_PIN_0, .func = CONFIG_GPIO0_FUNC},
+#endif
+#ifdef CONFIG_GPIO1_FUNC
+    {.pin = GPIO_PIN_1, .func = CONFIG_GPIO1_FUNC},
+#endif
+#ifdef CONFIG_GPIO2_FUNC
+    {.pin = GPIO_PIN_2, .func = CONFIG_GPIO2_FUNC},
+#endif
+#ifdef CONFIG_GPIO3_FUNC
+    {.pin = GPIO_PIN_3, .func = CONFIG_GPIO3_FUNC},
+#endif
+#ifdef CONFIG_GPIO4_FUNC
+    {.pin = GPIO_PIN_4, .func = CONFIG_GPIO4_FUNC},
+#endif
+#ifdef CONFIG_GPIO5_FUNC
+    {.pin = GPIO_PIN_5, .func = CONFIG_GPIO5_FUNC},
+#endif
+#ifdef CONFIG_GPIO6_FUNC
+    {.pin = GPIO_PIN_6, .func = CONFIG_GPIO6_FUNC},
+#endif
+#ifdef CONFIG_GPIO7_FUNC
+    {.pin = GPIO_PIN_7, .func = CONFIG_GPIO7_FUNC},
+#endif
+#ifdef CONFIG_GPIO8_FUNC
+    {.pin = GPIO_PIN_8, .func = CONFIG_GPIO8_FUNC},
+#endif
+#ifdef CONFIG_GPIO9_FUNC
+    {.pin = GPIO_PIN_9, .func = CONFIG_GPIO9_FUNC},
+#endif
+#ifdef CONFIG_GPIO10_FUNC
+    {.pin = GPIO_PIN_10, .func = CONFIG_GPIO10_FUNC},
+#endif
+#ifdef CONFIG_GPIO11_FUNC
+    {.pin = GPIO_PIN_11, .func = CONFIG_GPIO11_FUNC},
+#endif
+#ifdef CONFIG_GPIO12_FUNC
+    {.pin = GPIO_PIN_12, .func = CONFIG_GPIO12_FUNC},
+#endif
+#ifdef CONFIG_GPIO13_FUNC
+    {.pin = GPIO_PIN_13, .func = CONFIG_GPIO13_FUNC},
+#endif
+#ifdef CONFIG_GPIO14_FUNC
+    {.pin = GPIO_PIN_14, .func = CONFIG_GPIO14_FUNC},
+#endif
+#ifdef CONFIG_GPIO15_FUNC
+    {.pin = GPIO_PIN_15, .func = CONFIG_GPIO15_FUNC},
+#endif
+#ifdef CONFIG_GPIO16_FUNC
+    {.pin = GPIO_PIN_16, .func = CONFIG_GPIO16_FUNC},
+#endif
+#ifdef CONFIG_GPIO17_FUNC
+    {.pin = GPIO_PIN_17, .func = CONFIG_GPIO17_FUNC},
+#endif
+#ifdef CONFIG_GPIO18_FUNC
+    {.pin = GPIO_PIN_18, .func = CONFIG_GPIO18_FUNC},
+#endif
+#ifdef CONFIG_GPIO19_FUNC
+    {.pin = GPIO_PIN_19, .func = CONFIG_GPIO19_FUNC},
+#endif
+#ifdef CONFIG_GPIO20_FUNC
+    {.pin = GPIO_PIN_20, .func = CONFIG_GPIO20_FUNC},
+#endif
+#ifdef CONFIG_GPIO21_FUNC
+    {.pin = GPIO_PIN_21, .func = CONFIG_GPIO21_FUNC},
+#endif
+#ifdef CONFIG_GPIO22_FUNC
+    {.pin = GPIO_PIN_22, .func = CONFIG_GPIO22_FUNC},
+#endif
+#ifdef CONFIG_GPIO23_FUNC
+    {.pin = GPIO_PIN_23, .func = CONFIG_GPIO23_FUNC},
+#endif
+#ifdef CONFIG_GPIO24_FUNC
+    {.pin = GPIO_PIN_24, .func = CONFIG_GPIO24_FUNC},
+#endif
+#ifdef CONFIG_GPIO25_FUNC
+    {.pin = GPIO_PIN_25, .func = CONFIG_GPIO25_FUNC},
+#endif
+#ifdef CONFIG_GPIO26_FUNC
+    {.pin = GPIO_PIN_26, .func = CONFIG_GPIO26_FUNC},
+#endif
+#ifdef CONFIG_GPIO27_FUNC
+    {.pin = GPIO_PIN_27, .func = CONFIG_GPIO27_FUNC},
+#endif
+#ifdef CONFIG_GPIO28_FUNC
+    {.pin = GPIO_PIN_28, .func = CONFIG_GPIO28_FUNC},
+#endif
+#ifdef CONFIG_GPIO29_FUNC
+    {.pin = GPIO_PIN_29, .func = CONFIG_GPIO29_FUNC},
+#endif
+#ifdef CONFIG_GPIO30_FUNC
+    {.pin = GPIO_PIN_30, .func = CONFIG_GPIO30_FUNC},
+#endif
+#ifdef CONFIG_GPIO31_FUNC
+    {.pin = GPIO_PIN_31, .func = CONFIG_GPIO31_FUNC},
+#endif
+};
+
+static void board_pin_mux_init(void) {
+  GLB_GPIO_Cfg_Type gpio_cfg;
+  uint32_t          tmpVal;
+  gpio_cfg.drive        = 3;
+  gpio_cfg.smtCtrl      = 1;
+  uint8_t hbn_gpio_mask = 0x1f;
+  uint8_t hbn_aon_ie    = 0;
+
+  for (uint32_t i = 0; i < sizeof(af_pin_table) / sizeof(af_pin_table[0]); i++) {
+    gpio_cfg.gpioMode = GPIO_MODE_AF;
+    gpio_cfg.pullType = GPIO_PULL_UP;
+    gpio_cfg.gpioPin  = af_pin_table[i].pin;
+    gpio_cfg.gpioFun  = af_pin_table[i].func;
+
+    /*if using gpio9-gpio12 and func is not analog and output ,should set reg_aon_pad_ie_smt corresponding bit = 1*/
+    if ((af_pin_table[i].pin > GPIO_PIN_8) && (af_pin_table[i].pin < GPIO_PIN_13)) {
+      if ((af_pin_table[i].func != 10) && ((af_pin_table[i].func < GPIO_FUN_GPIO_OUTPUT_UP) || (af_pin_table[i].func > GPIO_FUN_GPIO_OUTPUT_NONE)))
+        hbn_aon_ie |= (1 << (af_pin_table[i].pin - 9));
+    }
+
+    /*if reset state*/
+    if (af_pin_table[i].func == GPIO_FUN_UNUSED) {
+      continue;
+    } else if (af_pin_table[i].func == GPIO_FUN_WAKEUP) {
+      /*if hbn or pds gpio wakeup func*/
+      if (af_pin_table[i].pin < GPIO_PIN_8) {
+        /*enable pds gpio wakeup and irq unmask*/
+        tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_INT_SELECT, af_pin_table[i].pin);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_INT_MODE, PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_INT_MASK);
+        BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
+      } else if ((af_pin_table[i].pin > GPIO_PIN_8) && (af_pin_table[i].pin < GPIO_PIN_13)) {
+        hbn_gpio_mask &= ~(1 << (af_pin_table[i].pin - 9));
+      }
+      continue;
+    } else if ((af_pin_table[i].func == GPIO_FUN_USB) || (af_pin_table[i].func == GPIO_FUN_DAC) || (af_pin_table[i].func == GPIO_FUN_ADC)) {
+      /*if analog func , for usb、adc、dac*/
+      gpio_cfg.gpioFun  = GPIO_FUN_ANALOG;
+      gpio_cfg.gpioMode = GPIO_MODE_ANALOG;
+      gpio_cfg.pullType = GPIO_PULL_NONE;
+    } else if ((af_pin_table[i].func & 0xF0) == 0xF0) {
+      /*if uart func*/
+      gpio_cfg.gpioFun  = GPIO_FUN_UART;
+      uint8_t uart_func = af_pin_table[i].func & 0x07;
+      uint8_t uart_sig  = gpio_cfg.gpioPin % 8;
+      /*link to one uart sig*/
+      GLB_UART_Fun_Sel((GLB_UART_SIG_Type)uart_sig, (GLB_UART_SIG_FUN_Type)uart_func);
+      GLB_UART_Fun_Sel((GLB_UART_SIG_Type)uart_func, (GLB_UART_SIG_FUN_Type)uart_sig);
+    } else if (af_pin_table[i].func == GPIO_FUN_PWM) {
+      /*if pwm func*/
+      gpio_cfg.pullType = GPIO_PULL_DOWN;
+    } else if (af_pin_table[i].func == GPIO_FUN_QDEC) {
+      /* if qdec a/b */
+      gpio_cfg.pullType = GPIO_PULL_NONE;
+      gpio_cfg.gpioMode = GPIO_MODE_INPUT;
+      gpio_cfg.gpioFun  = GPIO_FUN_QDEC;
+    } else if (af_pin_table[i].func == GPIO_FUN_QDEC_LED) {
+      /* if qdec led */
+      gpio_cfg.pullType = GPIO_PULL_NONE;
+      gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
+      gpio_cfg.gpioFun  = GPIO_FUN_QDEC;
+    } else if (af_pin_table[i].func == GPIO_FUN_CLK_OUT) {
+      if (af_pin_table[i].pin % 2) {
+        /*odd gpio output clock*/
+        GLB_Set_Chip_Out_1_CLK_Sel(GLB_CHIP_CLK_OUT_I2S_REF_CLK);
+      } else {
+        /*even gpio output clock*/
+        GLB_Set_Chip_Out_0_CLK_Sel(GLB_CHIP_CLK_OUT_I2S_REF_CLK);
+      }
+    } else if ((af_pin_table[i].func == GPIO_FUN_GPIO_INPUT_UP) || (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_FALLING_EDGE) || (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_LOW_LEVEL)) {
+      /*if common gpio func,include input、output and exti*/
+      gpio_cfg.gpioFun  = GPIO_FUN_GPIO;
+      gpio_cfg.gpioMode = GPIO_MODE_INPUT;
+      gpio_cfg.pullType = GPIO_PULL_UP;
+
+      if (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_FALLING_EDGE) {
+        GLB_Set_GPIO_IntMod(af_pin_table[i].pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_NEG_PULSE);
+      } else if (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_LOW_LEVEL) {
+        GLB_Set_GPIO_IntMod(af_pin_table[i].pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_NEG_LEVEL);
+      }
+    } else if ((af_pin_table[i].func == GPIO_FUN_GPIO_INPUT_DOWN) || (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_RISING_EDGE) || (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_HIGH_LEVEL)) {
+      gpio_cfg.gpioFun  = GPIO_FUN_GPIO;
+      gpio_cfg.gpioMode = GPIO_MODE_INPUT;
+      gpio_cfg.pullType = GPIO_PULL_DOWN;
+
+      if (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_RISING_EDGE) {
+        GLB_Set_GPIO_IntMod(af_pin_table[i].pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_POS_PULSE);
+      } else if (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_HIGH_LEVEL) {
+        GLB_Set_GPIO_IntMod(af_pin_table[i].pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_POS_LEVEL);
+      }
+    } else if (af_pin_table[i].func == GPIO_FUN_GPIO_INPUT_NONE) {
+      gpio_cfg.gpioFun  = GPIO_FUN_GPIO;
+      gpio_cfg.gpioMode = GPIO_MODE_INPUT;
+      gpio_cfg.pullType = GPIO_PULL_NONE;
+    } else if (af_pin_table[i].func == GPIO_FUN_GPIO_OUTPUT_UP) {
+      gpio_cfg.gpioFun  = GPIO_FUN_GPIO;
+      gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
+      gpio_cfg.pullType = GPIO_PULL_UP;
+    } else if (af_pin_table[i].func == GPIO_FUN_GPIO_OUTPUT_DOWN) {
+      gpio_cfg.gpioFun  = GPIO_FUN_GPIO;
+      gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
+      gpio_cfg.pullType = GPIO_PULL_DOWN;
+    } else if (af_pin_table[i].func == GPIO_FUN_GPIO_OUTPUT_NONE) {
+      gpio_cfg.gpioFun  = GPIO_FUN_GPIO;
+      gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
+      gpio_cfg.pullType = GPIO_PULL_NONE;
+    }
+    GLB_GPIO_Init(&gpio_cfg);
+  }
+
+  /*disable unused reg_aon_pad_ie_smt bits and hbn_pin_wakeup_mask bits*/
+  tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, hbn_gpio_mask);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, hbn_aon_ie);
+  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
+  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MODE, HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE);
+  BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+}
+
+static void board_clock_init(void) {
+  system_clock_init();
+  peripheral_clock_init();
+}
+
+void board_init(void) {
+  board_clock_init();
+  board_pin_mux_init();
+}
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/clock_config.h b/source/Core/BSP/Pinecilv2/clock_config.h
new file mode 100644
index 00000000..4e2d4f2a
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/clock_config.h
@@ -0,0 +1,64 @@
+/**
+ * @file clock_config.h
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+
+#ifndef _CLOCK_CONFIG_H
+#define _CLOCK_CONFIG_H
+
+#define XTAL_TYPE                  EXTERNAL_XTAL_32M
+#define XTAL_32K_TYPE              INTERNAL_RC_32K
+#define BSP_ROOT_CLOCK_SOURCE      ROOT_CLOCK_SOURCE_PLL_144M
+#define BSP_AUDIO_PLL_CLOCK_SOURCE ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ
+
+#define BSP_FCLK_DIV 0
+#define BSP_BCLK_DIV 1
+
+#define BSP_UART_CLOCK_SOURCE   ROOT_CLOCK_SOURCE_PLL_96M
+#define BSP_UART_CLOCK_DIV      0
+#define BSP_I2C_CLOCK_SOURCE    ROOT_CLOCK_SOURCE_BCLK
+#define BSP_I2C_CLOCK_DIV       0
+#define BSP_SPI_CLOCK_SOURCE    ROOT_CLOCK_SOURCE_BCLK
+#define BSP_SPI_CLOCK_DIV       0
+#define BSP_TIMER0_CLOCK_SOURCE ROOT_CLOCK_SOURCE_32K_CLK
+#define BSP_TIMER0_CLOCK_DIV    22
+#define BSP_TIMER1_CLOCK_SOURCE ROOT_CLOCK_SOURCE_32K_CLK
+#define BSP_TIMER1_CLOCK_DIV    31
+#define BSP_WDT_CLOCK_SOURCE    ROOT_CLOCK_SOURCE_32K_CLK
+#define BSP_WDT_CLOCK_DIV       32
+#define BSP_PWM_CLOCK_SOURCE    ROOT_CLOCK_SOURCE_XCLK
+#define BSP_PWM_CLOCK_DIV       22
+#define BSP_IR_CLOCK_SOURCE     ROOT_CLOCK_SOURCE_XCLK
+#define BSP_IR_CLOCK_DIV        0
+
+#define BSP_ADC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_XCLK
+#define BSP_ADC_CLOCK_DIV    16
+
+#define BSP_DAC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ
+#define BSP_DAC_CLOCK_DIV    2
+
+#define BSP_CAM_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_96M
+#define BSP_CAM_CLOCK_DIV    3
+
+#define BSP_QDEC_KEYSCAN_CLOCK_SOURCE ROOT_CLOCK_SOURCE_XCLK
+#define BSP_QDEC_KEYSCAN_CLOCK_DIV    31
+
+#endif
\ No newline at end of file
diff --git a/source/Core/BSP/Pinecilv2/configuration.h b/source/Core/BSP/Pinecilv2/configuration.h
new file mode 100644
index 00000000..06871af8
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/configuration.h
@@ -0,0 +1,161 @@
+#ifndef CONFIGURATION_H_
+#define CONFIGURATION_H_
+#include "Settings.h"
+#include 
+/**
+ * Configuration.h
+ * Define here your default pre settings for Pinecil
+ *
+ */
+
+//===========================================================================
+//============================= Default Settings ============================
+//===========================================================================
+/**
+ * Default soldering temp is 320.0 C
+ * Temperature the iron sleeps at - default 150.0 C
+ */
+
+#define SLEEP_TEMP         150 // Default sleep temperature
+#define BOOST_TEMP         420 // Default boost temp.
+#define BOOST_MODE_ENABLED 1   // 0: Disable 1: Enable
+
+/**
+ * Blink the temperature on the cooling screen when its > 50C
+ */
+#define COOLING_TEMP_BLINK 0 // 0: Disable 1: Enable
+
+/**
+ * How many seconds/minutes we wait until going to sleep/shutdown.
+ * Values -> SLEEP_TIME * 10; i.e. 5*10 = 50 Seconds!
+ */
+#define SLEEP_TIME    5  // x10 Seconds
+#define SHUTDOWN_TIME 10 // Minutes
+
+/**
+ * Auto start off for safety.
+ * Pissible values are:
+ *  0 - none
+ *  1 - Soldering Temperature
+ *  2 - Sleep Temperature
+ *  3 - Sleep Off Temperature
+ */
+#define AUTO_START_MODE 0 // Default to none
+
+/**
+ * Locking Mode
+ * When in soldering mode a long press on both keys toggle the lock of the buttons
+ * Possible values are:
+ *  0 - Desactivated
+ *  1 - Lock except boost
+ *  2 - Full lock
+ */
+#define LOCKING_MODE 0 // Default to desactivated for safety
+
+/**
+ * OLED Orientation
+ *
+ */
+#define ORIENTATION_MODE           2 // 0: Right 1:Left 2:Automatic - Default Automatic
+#define REVERSE_BUTTON_TEMP_CHANGE 0 // 0:Default 1:Reverse - Reverse the plus and minus button assigment for temperature change
+
+/**
+ * Temp change settings
+ */
+#define TEMP_CHANGE_SHORT_STEP     1  // Default temp change short step +1
+#define TEMP_CHANGE_LONG_STEP      10 // Default temp change long step +10
+#define TEMP_CHANGE_SHORT_STEP_MAX 50 // Temp change short step MAX value
+#define TEMP_CHANGE_LONG_STEP_MAX  90 // Temp change long step MAX value
+
+/* Power pulse for keeping power banks awake*/
+
+#define POWER_PULSE_INCREMENT    1
+#define POWER_PULSE_MAX          100 // x10 max watts
+#define POWER_PULSE_WAIT_MAX     9   // 9*2.5s = 22.5 seconds
+#define POWER_PULSE_DURATION_MAX 9   // 9*250ms = 2.25 seconds
+
+#ifdef MODEL_Pinecil
+#define POWER_PULSE_DEFAULT 0
+#else
+#define POWER_PULSE_DEFAULT 5
+#endif
+#define POWER_PULSE_WAIT_DEFAULT     4 // Default rate of the power pulse: 4*2500 = 10000 ms = 10 s
+#define POWER_PULSE_DURATION_DEFAULT 1 // Default duration of the power pulse: 1*250 = 250 ms
+
+/**
+ * OLED Orientation Sensitivity on Automatic mode!
+ * Motion Sensitivity <0=Off 1=Least Sensitive 9=Most Sensitive>
+ */
+#define SENSITIVITY 7 // Default 7
+
+/**
+ * Detailed soldering screen
+ * Detailed idle screen (off for first time users)
+ */
+#define DETAILED_SOLDERING 0 // 0: Disable 1: Enable - Default 0
+#define DETAILED_IDLE      0 // 0: Disable 1: Enable - Default 0
+
+#define THERMAL_RUNAWAY_TIME_SEC 20
+#define THERMAL_RUNAWAY_TEMP_C   20
+
+#define CUT_OUT_SETTING          0  // default to no cut-off voltage
+#define RECOM_VOL_CELL           33 // Minimum voltage per cell (Recommended 3.3V (33))
+#define TEMPERATURE_INF          0  // default to 0
+#define DESCRIPTION_SCROLL_SPEED 0  // 0: Slow 1: Fast - default to slow
+#define ANIMATION_LOOP           1  // 0: off 1: on
+#define ANIMATION_SPEED          settingOffSpeed_t::MEDIUM
+
+#define OP_AMP_Rf_Pinecil  680 * 1000 // 700  Kilo-ohms -> From schematic, R1
+#define OP_AMP_Rin_Pinecil 2370       // 2.37 Kilo-ohms -> From schematic, R2
+
+#define OP_AMP_GAIN_STAGE_PINECIL (1 + (OP_AMP_Rf_Pinecil / OP_AMP_Rin_Pinecil))
+
+#if defined(MODEL_Pinecilv2) == 0
+#error "No model defined!"
+#endif
+
+#ifdef MODEL_Pinecilv2
+#define ADC_VDD_MV                 3300                      // ADC max reading millivolts
+#define ADC_MAX_READING            (62000 >> 1)              // Maximum reading of the adc
+#define SOLDERING_TEMP             320                       // Default soldering temp is 320.0 °C
+#define VOLTAGE_DIV                600                       // 600 - Default divider from schematic
+#define CALIBRATION_OFFSET         900                       // 900 - Default adc offset in uV
+#define MIN_CALIBRATION_OFFSET     100                       // Min value for calibration
+#define PID_POWER_LIMIT            220                       // Sets the max pwm power limit
+#define POWER_LIMIT                0                         // 0 watts default limit
+#define MAX_POWER_LIMIT            220                       //
+#define POWER_LIMIT_STEPS          5                         //
+#define OP_AMP_GAIN_STAGE          OP_AMP_GAIN_STAGE_PINECIL // Uses TS100 resistors
+#define TEMP_uV_LOOKUP_HAKKO                                 // Use Hakko lookup table
+#define USB_PD_VMAX                28                        // Maximum voltage for PD to negotiate
+#define PID_TIM_HZ                 (10)                      // Tick rate of the PID loop
+#define MAX_TEMP_C                 450                       // Max soldering temp selectable °C
+#define MAX_TEMP_F                 850                       // Max soldering temp selectable °F
+#define MIN_TEMP_C                 10                        // Min soldering temp selectable °C
+#define MIN_TEMP_F                 60                        // Min soldering temp selectable °F
+#define MIN_BOOST_TEMP_C           250                       // The min settable temp for boost mode °C
+#define MIN_BOOST_TEMP_F           480                       // The min settable temp for boost mode °F
+#define DEVICE_HAS_VALIDATION_CODE                           // We have 2 digit validations
+#define POW_PD                     1                         // Supported features
+#define POW_QC                     1                         // Supported features
+#define POW_DC                     1                         // Supported features
+#define POW_QC_20V                 1                         // Supported features
+#define POW_EPR                    1
+#define ENABLE_QC2                 1
+#define DEVICE_HAS_VALIDATION_SUPPORT
+#define TEMP_NTC
+#define ACCEL_BMA
+#define ACCEL_SC7
+#define HALL_SENSOR
+#define HALL_SI7210
+#define DEBUG_UART_OUTPUT
+#define HAS_POWER_DEBUG_MENU
+#define HARDWARE_MAX_WATTAGE_X10 750
+#define TIP_THERMAL_MASS         65 // X10 watts to raise 1 deg C in 1 second
+
+#define NEEDS_VBUS_PROBE 0
+
+#endif
+#endif
+
+#define FLASH_LOGOADDR (0x23000000 + (1022 * 1024))
diff --git a/source/Core/BSP/Pinecilv2/crc32.h b/source/Core/BSP/Pinecilv2/crc32.h
new file mode 100644
index 00000000..c8bc9c09
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/crc32.h
@@ -0,0 +1,29 @@
+#pragma once
+
+#include 
+
+#define DEFAULT_POLY 0x973afb51
+
+template  struct CRC32Table {
+  constexpr CRC32Table() : table() {
+    for (uint32_t i = 0; i < 256; i++) {
+      uint32_t c = i;
+      for (auto j = 0; j < 8; j++) {
+        if (c & 1) {
+          c = polynomial ^ (c >> 1);
+        } else {
+          c >>= 1;
+        }
+      }
+      table[i] = c;
+    }
+  }
+  uint32_t table[256];
+  uint32_t computeCRC32(uint32_t initial, const uint8_t *buf, int len) {
+    uint32_t c = initial ^ 0xFFFFFFFF;
+    for (auto i = 0; i < len; ++i) {
+      c = table[(c ^ buf[i]) & 0xFF] ^ (c >> 8);
+    }
+    return c ^ 0xFFFFFFFF;
+  }
+};
diff --git a/source/Core/BSP/Pinecilv2/flash.c b/source/Core/BSP/Pinecilv2/flash.c
new file mode 100644
index 00000000..38337001
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/flash.c
@@ -0,0 +1,23 @@
+/*
+ * flash.c
+ *
+ *  Created on: 29 May 2020
+ *      Author: Ralim
+ */
+
+#include "BSP.h"
+#include "BSP_Flash.h"
+#include "hal_flash.h"
+#include "string.h"
+
+#define FLASH_PAGE_SIZE (1024)
+
+#define SETTINGS_START_PAGE (1023 * FLASH_PAGE_SIZE) // Hal auto offsets base addr
+
+uint8_t flash_save_buffer(const uint8_t *buffer, const uint16_t length) {
+  BL_Err_Type err = flash_erase(SETTINGS_START_PAGE, FLASH_PAGE_SIZE);
+  err             = flash_write(SETTINGS_START_PAGE, buffer, length);
+  return err != SUCCESS;
+}
+
+void flash_read_buffer(uint8_t *buffer, const uint16_t length) { flash_read(SETTINGS_START_PAGE, buffer, length); }
diff --git a/source/Core/BSP/Pinecilv2/fusb_user.cpp b/source/Core/BSP/Pinecilv2/fusb_user.cpp
new file mode 100644
index 00000000..0e06e943
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/fusb_user.cpp
@@ -0,0 +1,27 @@
+#include "configuration.h"
+#if POW_PD
+#include "BSP.h"
+#include "I2C_Wrapper.hpp"
+#include "Setup.h"
+
+/*
+ * Read multiple bytes from the FUSB302B
+ *
+ * cfg: The FUSB302B to communicate with
+ * addr: The memory address from which to read
+ * size: The number of bytes to read
+ * buf: The buffer into which data will be read
+ */
+bool fusb_read_buf(const uint8_t deviceAddr, const uint8_t registerAdd, const uint8_t size, uint8_t *buf) { return FRToSI2C::Mem_Read(deviceAddr, registerAdd, buf, size); }
+
+/*
+ * Write multiple bytes to the FUSB302B
+ *
+ * cfg: The FUSB302B to communicate with
+ * addr: The memory address to which we will write
+ * size: The number of bytes to write
+ * buf: The buffer to write
+ */
+bool fusb_write_buf(const uint8_t deviceAddr, const uint8_t registerAdd, const uint8_t size, uint8_t *buf) { return FRToSI2C::Mem_Write(deviceAddr, registerAdd, (uint8_t *)buf, size); }
+
+#endif
diff --git a/source/Core/BSP/Pinecilv2/peripheral_config.h b/source/Core/BSP/Pinecilv2/peripheral_config.h
new file mode 100644
index 00000000..21b56915
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/peripheral_config.h
@@ -0,0 +1,266 @@
+/**
+ * @file peripheral_config.h
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+
+#ifndef _PERIPHERAL_CONFIG_H_
+#define _PERIPHERAL_CONFIG_H_
+
+/* PERIPHERAL USING LIST */
+#define BSP_USING_ADC0
+// #define BSP_USING_DAC0
+#define BSP_USING_UART0
+// #define BSP_USING_UART1
+// #define BSP_USING_SPI0
+#define BSP_USING_I2C0
+// #define BSP_USING_I2S0
+// #define BSP_USING_PWM_CH0
+#define BSP_USING_PWM_CH1
+// #define BSP_USING_PWM_CH2
+// #define BSP_USING_PWM_CH3
+// #define BSP_USING_PWM_CH4
+#define BSP_USING_TIMER0
+#define BSP_USING_TIMER1
+#define BSP_USING_WDT
+// #define BSP_USING_KEYSCAN
+// #define BSP_USING_QDEC0
+// #define BSP_USING_QDEC1
+// #define BSP_USING_QDEC2
+// #define BSP_USING_USB
+/* ----------------------*/
+
+/* PERIPHERAL With DMA LIST */
+
+#define BSP_USING_DMA0_CH0
+#define BSP_USING_DMA0_CH1
+#define BSP_USING_DMA0_CH2
+#define BSP_USING_DMA0_CH3
+#define BSP_USING_DMA0_CH4
+#define BSP_USING_DMA0_CH5
+#define BSP_USING_DMA0_CH6
+#define BSP_USING_DMA0_CH7
+
+/* PERIPHERAL CONFIG */
+#if defined(BSP_USING_ADC0)
+#ifndef ADC0_CONFIG
+#define ADC0_CONFIG                                                                                                                                                      \
+  {                                                                                                                                                                      \
+    .clk_div = ADC_CLOCK_DIV_32, .vref = ADC_VREF_3V2, .continuous_conv_mode = DISABLE, .differential_mode = DISABLE, .data_width = ADC_DATA_WIDTH_16B_WITH_256_AVERAGE, \
+    .fifo_threshold = ADC_FIFO_THRESHOLD_8BYTE, .gain = ADC_GAIN_1                                                                                                       \
+  }
+#endif
+#endif
+
+#if defined(BSP_USING_DAC0)
+#ifndef DAC_CONFIG
+#define DAC_CONFIG \
+  { .channels = DAC_CHANNEL_0, .sample_freq = DAC_SAMPLE_FREQ_500KHZ, .vref = DAC_VREF_INTERNAL, }
+#endif
+#endif
+
+#if defined(BSP_USING_UART0)
+#ifndef UART0_CONFIG
+#define UART0_CONFIG \
+  { .id = 0, .baudrate = 2000000, .databits = UART_DATA_LEN_8, .stopbits = UART_STOP_ONE, .parity = UART_PAR_NONE, .fifo_threshold = 0, }
+#endif
+#endif
+
+#if defined(BSP_USING_PWM_CH0)
+#ifndef PWM_CH0_CONFIG
+#define PWM_CH0_CONFIG \
+  { .ch = 0, .polarity_invert_mode = DISABLE, .period = 0, .threshold_low = 0, .threshold_high = 0, .it_pulse_count = 0, }
+#endif
+#endif
+
+#if defined(BSP_USING_PWM_CH1)
+#ifndef PWM_CH1_CONFIG
+#define PWM_CH1_CONFIG \
+  { .ch = 1, .polarity_invert_mode = DISABLE, .period = 100, .threshold_low = 0, .threshold_high = 0, .it_pulse_count = 0, }
+#endif
+#endif
+
+#if defined(BSP_USING_PWM_CH2)
+#ifndef PWM_CH2_CONFIG
+#define PWM_CH2_CONFIG \
+  { .ch = 2, .polarity_invert_mode = DISABLE, .period = 0, .threshold_low = 0, .threshold_high = 0, .it_pulse_count = 0, }
+#endif
+#endif
+
+#if defined(BSP_USING_PWM_CH3)
+#ifndef PWM_CH3_CONFIG
+#define PWM_CH3_CONFIG \
+  { .ch = 3, .polarity_invert_mode = DISABLE, .period = 0, .threshold_low = 0, .threshold_high = 0, .it_pulse_count = 0, }
+#endif
+#endif
+
+#if defined(BSP_USING_PWM_CH4)
+#ifndef PWM_CH4_CONFIG
+#define PWM_CH4_CONFIG \
+  { .ch = 4, .polarity_invert_mode = DISABLE, .period = 0, .threshold_low = 0, .threshold_high = 0, .it_pulse_count = 0, }
+#endif
+#endif
+
+#if defined(BSP_USING_DMA0_CH0)
+#ifndef DMA0_CH0_CONFIG
+#define DMA0_CH0_CONFIG                                                                                                                                                                            \
+  {                                                                                                                                                                                                \
+    .id = 0, .ch = 0, .direction = DMA_MEMORY_TO_MEMORY, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_NONE, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE,  \
+    .dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_4BYTE, .dst_burst_size = DMA_BURST_4BYTE, .src_width = DMA_TRANSFER_WIDTH_32BIT, .dst_width = DMA_TRANSFER_WIDTH_32BIT, \
+  }
+#endif
+#endif
+
+#if defined(BSP_USING_DMA0_CH1)
+#ifndef DMA0_CH1_CONFIG
+#define DMA0_CH1_CONFIG                                                                                                                                                                            \
+  {                                                                                                                                                                                                \
+    .id = 0, .ch = 1, .direction = DMA_MEMORY_TO_MEMORY, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_NONE, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE,  \
+    .dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_4BYTE, .dst_burst_size = DMA_BURST_4BYTE, .src_width = DMA_TRANSFER_WIDTH_16BIT, .dst_width = DMA_TRANSFER_WIDTH_16BIT, \
+  }
+#endif
+#endif
+
+#if defined(BSP_USING_DMA0_CH2)
+#ifndef DMA0_CH2_CONFIG
+#define DMA0_CH2_CONFIG                                                                                                                                                                               \
+  {                                                                                                                                                                                                   \
+    .id = 0, .ch = 2, .direction = DMA_MEMORY_TO_PERIPH, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_UART1_TX, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
+    .dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_8BIT, .dst_width = DMA_TRANSFER_WIDTH_8BIT,     \
+  }
+#endif
+#endif
+
+#if defined(BSP_USING_DMA0_CH3)
+#ifndef DMA0_CH3_CONFIG
+#define DMA0_CH3_CONFIG                                                                                                                                                                              \
+  {                                                                                                                                                                                                  \
+    .id = 0, .ch = 3, .direction = DMA_MEMORY_TO_PERIPH, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_SPI0_TX, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
+    .dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_8BIT, .dst_width = DMA_TRANSFER_WIDTH_8BIT,    \
+  }
+#endif
+#endif
+
+#if defined(BSP_USING_DMA0_CH4)
+#ifndef DMA0_CH4_CONFIG
+#define DMA0_CH4_CONFIG                                                                                                                                                                               \
+  {                                                                                                                                                                                                   \
+    .id = 0, .ch = 4, .direction = DMA_PERIPH_TO_MEMORY, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_SPI0_RX, .dst_req = DMA_REQUEST_NONE, .src_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
+    .dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_8BIT, .dst_width = DMA_TRANSFER_WIDTH_8BIT,      \
+  }
+#endif
+#endif
+
+#if defined(BSP_USING_DMA0_CH5)
+#ifndef DMA0_CH5_CONFIG
+#define DMA0_CH5_CONFIG                                                                                                                                                                              \
+  {                                                                                                                                                                                                  \
+    .id = 0, .ch = 5, .direction = DMA_MEMORY_TO_PERIPH, .transfer_mode = DMA_LLI_CYCLE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_I2S_TX, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
+    .dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_16BIT, .dst_width = DMA_TRANSFER_WIDTH_16BIT,  \
+  }
+#endif
+#endif
+
+#if defined(BSP_USING_DMA0_CH6)
+#ifndef DMA0_CH6_CONFIG
+#define DMA0_CH6_CONFIG                                                                                                                                                                              \
+  {                                                                                                                                                                                                  \
+    .id = 0, .ch = 6, .direction = DMA_MEMORY_TO_PERIPH, .transfer_mode = DMA_LLI_CYCLE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_I2S_TX, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
+    .dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_16BIT, .dst_width = DMA_TRANSFER_WIDTH_16BIT,  \
+  }
+#endif
+#endif
+
+#if defined(BSP_USING_DMA0_CH7)
+#ifndef DMA0_CH7_CONFIG
+#define DMA0_CH7_CONFIG                                                                                                                                                                            \
+  {                                                                                                                                                                                                \
+    .id = 0, .ch = 7, .direction = DMA_MEMORY_TO_MEMORY, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_NONE, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE,  \
+    .dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_32BIT, .dst_width = DMA_TRANSFER_WIDTH_32BIT, \
+  }
+#endif
+#endif
+
+#if defined(BSP_USING_I2C0)
+#ifndef I2C0_CONFIG
+#define I2C0_CONFIG \
+  { .id = 0, .mode = I2C_HW_MODE, .phase = 15, }
+#endif
+#endif
+
+#if defined(BSP_USING_TIMER0)
+#ifndef TIMER0_CONFIG
+#define TIMER0_CONFIG \
+  { .id = 0, .cnt_mode = TIMER_CNT_PRELOAD, .trigger = TIMER_PRELOAD_TRIGGER_COMP2, .reload = 0, .timeout1 = 1000000, .timeout2 = 2000000, .timeout3 = 3000000, }
+#endif
+#endif
+
+#if defined(BSP_USING_TIMER1)
+#ifndef TIMER1_CONFIG
+#define TIMER1_CONFIG \
+  { .id = 1, .cnt_mode = TIMER_CNT_PRELOAD, .trigger = TIMER_PRELOAD_TRIGGER_COMP0, .reload = 0, .timeout1 = 1000000, .timeout2 = 2000000, .timeout3 = 3000000, }
+#endif
+#endif
+
+#if defined(BSP_USING_WDT)
+#ifndef WDT_CONFIG
+#define WDT_CONFIG \
+  { .id = 0, .wdt_timeout = 6000, }
+#endif
+#endif
+
+#if defined(BSP_USING_KEYSCAN)
+#ifndef KEYSCAN_CONFIG
+#define KEYSCAN_CONFIG \
+  { .col_num = COL_NUM_4, .row_num = ROW_NUM_4, .deglitch_count = 0, }
+#endif
+#endif
+
+#if defined(BSP_USING_QDEC0)
+#ifndef QDEC0_CONFIG
+#define QDEC0_CONFIG                                                                                                                                                                                 \
+  {                                                                                                                                                                                                  \
+    .id = 0, .acc_mode = QDEC_ACC_CONTINUE_ACCUMULATE, .sample_mode = QDEC_SAMPLE_SINGLE_MOD, .sample_period = QDEC_SAMPLE_PERIOD_256US, .report_mode = QDEC_REPORT_TIME_MOD, .report_period = 2000, \
+    .led_en = ENABLE, .led_swap = DISABLE, .led_period = 7, .deglitch_en = DISABLE, .deglitch_strength = 0x0,                                                                                        \
+  }
+#endif
+#endif
+
+#if defined(BSP_USING_QDEC1)
+#ifndef QDEC1_CONFIG
+#define QDEC1_CONFIG                                                                                                                                                                                 \
+  {                                                                                                                                                                                                  \
+    .id = 1, .acc_mode = QDEC_ACC_CONTINUE_ACCUMULATE, .sample_mode = QDEC_SAMPLE_SINGLE_MOD, .sample_period = QDEC_SAMPLE_PERIOD_256US, .report_mode = QDEC_REPORT_TIME_MOD, .report_period = 2000, \
+    .led_en = ENABLE, .led_swap = DISABLE, .led_period = 7, .deglitch_en = DISABLE, .deglitch_strength = 0x0,                                                                                        \
+  }
+#endif
+#endif
+
+#if defined(BSP_USING_QDEC2)
+#ifndef QDEC2_CONFIG
+#define QDEC2_CONFIG                                                                                                                                                                                 \
+  {                                                                                                                                                                                                  \
+    .id = 2, .acc_mode = QDEC_ACC_CONTINUE_ACCUMULATE, .sample_mode = QDEC_SAMPLE_SINGLE_MOD, .sample_period = QDEC_SAMPLE_PERIOD_256US, .report_mode = QDEC_REPORT_TIME_MOD, .report_period = 2000, \
+    .led_en = ENABLE, .led_swap = DISABLE, .led_period = 7, .deglitch_en = DISABLE, .deglitch_strength = 0x0,                                                                                        \
+  }
+#endif
+#endif
+
+#endif
diff --git a/source/Core/BSP/Pinecilv2/pinmux_config.h b/source/Core/BSP/Pinecilv2/pinmux_config.h
new file mode 100644
index 00000000..9fa10ec0
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/pinmux_config.h
@@ -0,0 +1,178 @@
+/**
+ * @file pinmux_config.h
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef _PINMUX_CONFIG_H
+#define _PINMUX_CONFIG_H
+
+//  GPIO0 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio0 function
+#define CONFIG_GPIO0_FUNC GPIO_FUN_E21_JTAG
+
+//  GPIO1 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_CTS//GPIO_FUN_UART1_CTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio1 function
+#define CONFIG_GPIO1_FUNC GPIO_FUN_E21_JTAG
+
+//  GPIO2 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_TX//GPIO_FUN_UART1_TX//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio2 function
+#define CONFIG_GPIO2_FUNC GPIO_FUN_E21_JTAG
+
+//  GPIO3 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RX//GPIO_FUN_UART1_RX//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio3 function
+#define CONFIG_GPIO3_FUNC GPIO_FUN_GPIO_OUTPUT_NONE
+
+//  GPIO4 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio4 function
+#define CONFIG_GPIO4_FUNC GPIO_FUN_GPIO_INPUT_NONE
+
+//  GPIO5 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_CTS//GPIO_FUN_UART1_CTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio5 function
+#define CONFIG_GPIO5_FUNC GPIO_FUN_GPIO_INPUT_NONE
+
+//  GPIO6 <2> [GPIO_FUN_UNUSED//GPIO_FUN_CLK_OUT//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_TX//GPIO_FUN_UART1_TX//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio6 function
+#define CONFIG_GPIO6_FUNC GPIO_FUN_GPIO_INPUT_NONE
+
+//  GPIO7 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RX//GPIO_FUN_UART1_RX//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio7 function
+#define CONFIG_GPIO7_FUNC GPIO_FUN_USB
+
+//  GPIO8 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio8 function
+#define CONFIG_GPIO8_FUNC GPIO_FUN_USB
+
+//  GPIO9 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio9 function
+#define CONFIG_GPIO9_FUNC GPIO_FUN_E21_JTAG
+
+//  GPIO10 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio10 function
+#define CONFIG_GPIO10_FUNC GPIO_FUN_I2C
+
+//  GPIO11 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio11 function
+#define CONFIG_GPIO11_FUNC GPIO_FUN_I2C
+
+//  GPIO12 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio12 function
+#define CONFIG_GPIO12_FUNC GPIO_FUN_GPIO_INPUT_NONE
+
+//  GPIO13 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio13 function
+#define CONFIG_GPIO13_FUNC GPIO_FUN_UNUSED
+
+//  GPIO14 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio14 function
+#define CONFIG_GPIO14_FUNC GPIO_FUN_GPIO_INPUT_NONE
+
+//  GPIO15 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio15 function
+#define CONFIG_GPIO15_FUNC GPIO_FUN_SPI
+
+//  GPIO16 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio16 function
+#define CONFIG_GPIO16_FUNC GPIO_FUN_GPIO_EXTI_LOW_LEVEL
+
+//  GPIO17 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio17 function
+#define CONFIG_GPIO17_FUNC GPIO_FUN_ADC
+
+//  GPIO18 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio18 function
+#define CONFIG_GPIO18_FUNC GPIO_FUN_ADC
+
+//  GPIO19 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio19 function
+#define CONFIG_GPIO19_FUNC GPIO_FUN_ADC
+
+//  GPIO20 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio20 function
+#define CONFIG_GPIO20_FUNC GPIO_FUN_ADC
+
+//  GPIO21 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio21 function
+#define CONFIG_GPIO21_FUNC GPIO21_FUN_PWM_CH1
+
+//  GPIO22 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio22 function
+#define CONFIG_GPIO22_FUNC GPIO_FUN_UART0_TX
+
+//  GPIO23 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio23 function
+#define CONFIG_GPIO23_FUNC GPIO_FUN_UART0_RX
+
+//  GPIO24 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio24 function
+#define CONFIG_GPIO24_FUNC GPIO_FUN_GPIO_INPUT_NONE
+
+//  GPIO25 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio25 function
+#define CONFIG_GPIO25_FUNC GPIO_FUN_GPIO_INPUT_NONE
+
+//  GPIO26 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio26 function
+#define CONFIG_GPIO26_FUNC GPIO_FUN_GPIO_INPUT_NONE
+
+//  GPIO27 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio27 function
+#define CONFIG_GPIO27_FUNC GPIO_FUN_GPIO_INPUT_NONE
+
+//  GPIO28 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio28 function
+#define CONFIG_GPIO28_FUNC GPIO_FUN_GPIO_INPUT_NONE
+
+//  GPIO29 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio29 function
+#define CONFIG_GPIO29_FUNC GPIO_FUN_GPIO_EXTI_LOW_LEVEL
+
+//  GPIO30 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio30 function
+#define CONFIG_GPIO30_FUNC GPIO_FUN_GPIO_EXTI_LOW_LEVEL
+
+//  GPIO31 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio31 function
+#define CONFIG_GPIO31_FUNC GPIO_FUN_GPIO_EXTI_LOW_LEVEL
+
+//  GPIO32 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio32 function
+#define CONFIG_GPIO32_FUNC GPIO_FUN_UNUSED
+
+//  GPIO33 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio33 function
+#define CONFIG_GPIO33_FUNC GPIO_FUN_UNUSED
+
+//  GPIO34 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio34 function
+#define CONFIG_GPIO34_FUNC GPIO_FUN_UNUSED
+
+//  GPIO35 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio35 function
+#define CONFIG_GPIO35_FUNC GPIO_FUN_UNUSED
+
+//  GPIO36 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio36 function
+#define CONFIG_GPIO36_FUNC GPIO_FUN_UNUSED
+
+//  GPIO37 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+//  config gpio37 function
+#define CONFIG_GPIO37_FUNC GPIO_FUN_UNUSED
+
+#endif
diff --git a/source/Core/BSP/Pinecilv2/postRTOS.cpp b/source/Core/BSP/Pinecilv2/postRTOS.cpp
new file mode 100644
index 00000000..7e10c24e
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/postRTOS.cpp
@@ -0,0 +1,29 @@
+#include "BSP.h"
+#include "FreeRTOS.h"
+#include "I2C_Wrapper.hpp"
+#include "QC3.h"
+#include "Settings.h"
+#include "Si7210.h"
+#include "cmsis_os.h"
+#include "main.hpp"
+#include "power.hpp"
+#include "stdlib.h"
+#include "task.h"
+
+bool hall_effect_present = false;
+void postRToSInit() {
+  // Any after RTos setup
+#ifdef HALL_SI7210
+  if (Si7210::detect()) {
+    hall_effect_present = Si7210::init();
+  }
+#endif
+}
+int16_t getRawHallEffect() {
+  if (hall_effect_present) {
+    return Si7210::read();
+  }
+  return 0;
+}
+
+bool getHallSensorFitted() { return hall_effect_present; }
diff --git a/source/Core/BSP/Pinecilv2/preRTOS.cpp b/source/Core/BSP/Pinecilv2/preRTOS.cpp
new file mode 100644
index 00000000..1a949881
--- /dev/null
+++ b/source/Core/BSP/Pinecilv2/preRTOS.cpp
@@ -0,0 +1,24 @@
+/*
+ * preRTOS.c
+ *
+ *  Created on: 29 May 2020
+ *      Author: Ralim
+ */
+
+#include "BSP.h"
+#include "Pins.h"
+#include "Setup.h"
+#include "bflb_platform.h"
+#include "hal_gpio.h"
+#include 
+
+void preRToSInit() {
+  // Normal system bringup -- GPIO etc
+  bflb_platform_init(0);
+
+  hardware_init();
+  gpio_write(OLED_RESET_Pin, 0);
+  delay_ms(10);
+  gpio_write(OLED_RESET_Pin, 1);
+  FRToSI2C::FRToSInit();
+}
diff --git a/source/Core/Drivers/Font.h b/source/Core/Drivers/Font.h
index d3fc1723..d098f6f8 100644
--- a/source/Core/Drivers/Font.h
+++ b/source/Core/Drivers/Font.h
@@ -87,37 +87,6 @@ const uint8_t ExtraFontChars[] = {
      */
 };
 
-const uint8_t FontSymbols[] = {
-    0x00, 0x00, 0x00, 0xFC, 0xF8, 0xF0, 0xE0, 0xC0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x0F, 0x07, 0x03, 0x01, 0x00, 0x00, 0x00,
-    0x00, // Right block
-    0x00, 0x00, 0x00, 0x80, 0xC0, 0xE0, 0xF0, 0xF8, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x07, 0x0F, 0x1F, 0x00, 0x00,
-    0x00, // left block
-    0x00, 0x00, 0x00, 0x10, 0x18, 0x1C, 0xFE, 0x1C, 0x18, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x0C, 0x1C, 0x3F, 0x1C, 0x0C, 0x04, 0x00,
-    0x00, // UD arrow
-    0x00, 0x00, 0x00, 0xFE, 0xFE, 0x00, 0x00, 0xFE, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00,
-    0x00, // !!
-    0x00, 0x38, 0x7C, 0xC6, 0x82, 0xFE, 0xFE, 0x02, 0xFE, 0xFE, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x3F, 0x00, 0x3F, 0x3F, 0x00,
-    0x00, // paragraph
-    0x00, 0x00, 0xDC, 0xFE, 0x22, 0x22, 0x22, 0x22, 0xE6, 0xC4, 0x00, 0x00, 0x00, 0x00, 0x08, 0x19, 0x11, 0x11, 0x11, 0x11, 0x1F, 0x0E, 0x00,
-    0x00, // section
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38,
-    0x00, // cursor
-    0x00, 0x00, 0x00, 0x08, 0x0C, 0x0E, 0xFF, 0x0E, 0x0C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x4C, 0x5C, 0x7F, 0x5C, 0x4C, 0x44, 0x00,
-    0x00, // UD arrow
-    0x00, 0x00, 0x00, 0x10, 0x18, 0x1C, 0xFE, 0x1C, 0x18, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00,
-    0x00, // UP arrow
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x0C, 0x1C, 0x3F, 0x1C, 0x0C, 0x04, 0x00,
-    0x00, // Down arrow
-    0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0xF0, 0xE0, 0xC0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x03, 0x01, 0x00,
-    0x00, // right arrow
-    0x00, 0x00, 0x80, 0xC0, 0xE0, 0xF0, 0x80, 0x80, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, // left arrow
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00,
-    0x00, 0x80, 0xC0, 0xE0, 0xF0, 0x80, 0x80, 0x80, 0xF0, 0xE0, 0xC0, 0x80, 0x00, 0x00, 0x01, 0x03, 0x07, 0x00, 0x00, 0x00, 0x07, 0x03, 0x01, 0x00, // LR arrow
-    0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0xE0, 0xC0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x04, 0x06, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x06, 0x04, // UP block
-    0x00, 0x20, 0x60, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0x60, 0x20, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x07, 0x03, 0x01, 0x00, 0x00, 0x00  // Down block
-};
-
 const uint8_t WarningBlock24[] = {
     // width = 24
     // height = 16
@@ -140,6 +109,22 @@ const uint8_t disconnectedTip[] = {
     0x04, 0x31, 0x38, 0x1c, 0x0e, 0x04, 0x01, 0x03, 0x07, 0x0e, 0x1c, 0x39, 0x30, 0x01, 0x03, 0x00, 0x02, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02, 0x01, 0x04, 0x09, 0x0f, 0x00};
 #endif
 
+#if defined(MODEL_Pinecilv2) >= 1
+const uint8_t buttonA[] = {
+    // width = 42
+    // height = 16
+    0x00, 0x00, 0x00, 0x00, 0xe0, 0x18, 0x04, 0x02, 0x02, 0x01, 0x81, 0x49, 0x31, 0x01, 0xc1, 0x25, 0x19, 0x01, 0xc1, 0x25, 0x19, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+    0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x02, 0x04, 0x18, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x18, 0x20, 0x40, 0x40, 0x80, 0x89, 0x8a, 0x88, 0x94,
+    0x8c, 0x94, 0xae, 0x80, 0xbe, 0x8e, 0xa6, 0x8e, 0xa6, 0x8e, 0xa6, 0x8e, 0xa6, 0x8a, 0xa6, 0x8a, 0xa6, 0x8a, 0xa6, 0x8a, 0x46, 0x4a, 0x22, 0x18, 0x07, 0x00, 0x00, 0x00};
+
+const uint8_t disconnectedTip[] = {
+    // width = 42
+    // height = 16
+    0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0xc0, 0x00, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xcc, 0x9c, 0x38, 0x70, 0xe0, 0xc0, 0x80, 0x20, 0x70, 0x38, 0x1c, 0xcc, 0x40,
+    0x80, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0xc0, 0x60, 0xe0, 0x00, 0x01, 0x01, 0x01, 0x02, 0x01, 0x02, 0x05, 0x00, 0x07, 0x01, 0x04, 0x01, 0x04, 0x01,
+    0x04, 0x31, 0x38, 0x1c, 0x0e, 0x04, 0x01, 0x03, 0x07, 0x0e, 0x1c, 0x39, 0x30, 0x01, 0x03, 0x00, 0x02, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02, 0x01, 0x04, 0x09, 0x0f, 0x00};
+#endif
+
 #if defined(MODEL_TS80) + defined(MODEL_TS80P) > 0
 const uint8_t buttonA[] = {
     // width = 42
@@ -179,16 +164,16 @@ const uint8_t buttonB[] = {
     0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x02, 0x04, 0x18, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x18, 0x20, 0x40, 0x40, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
     0x80, 0x80, 0xbf, 0x80, 0x80, 0x8e, 0xaa, 0x8e, 0x80, 0x83, 0xba, 0x83, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x40, 0x40, 0x20, 0x18, 0x07, 0x00, 0x00, 0x00, 0x00};
 
-const uint8_t brightnessIcon[] = {
-    // width = 16
-    // height = 16
-    0x80, 0x86, 0x8E, 0x9C, 0x18, 0xC0, 0xE0, 0xEF, 0xEF, 0xE0, 0xC0, 0x18, 0x9C, 0x8E, 0x86, 0x80, 0x01, 0x61, 0x71, 0x39, 0x18, 0x03, 0x07, 0xF7, 0xF7, 0x07, 0x03, 0x18, 0x39, 0x71, 0x61, 0x01};
+// const uint8_t brightnessIcon[] = {
+//     // width = 16
+//     // height = 16
+//     0x80, 0x86, 0x8E, 0x9C, 0x18, 0xC0, 0xE0, 0xEF, 0xEF, 0xE0, 0xC0, 0x18, 0x9C, 0x8E, 0x86, 0x80, 0x01, 0x61, 0x71, 0x39, 0x18, 0x03, 0x07, 0xF7, 0xF7, 0x07, 0x03, 0x18, 0x39, 0x71, 0x61, 0x01};
 
-const uint8_t invertDisplayIcon[] = {
-    // width = 24
-    // height = 16
-    0xFE, 0x01, 0x79, 0x25, 0x79, 0x01, 0xFE, 0x00, 0x20, 0x20, 0x20, 0x20, 0xDF, 0x07, 0x8F, 0xDF, 0xFF, 0x01, 0xFE, 0x86, 0xDA, 0x86, 0xFE, 0x01,
-    0x7F, 0x80, 0xA4, 0xBE, 0xA0, 0x80, 0x7F, 0x00, 0x04, 0x0E, 0x1F, 0x04, 0xFB, 0xFB, 0xFB, 0xFB, 0xFF, 0x80, 0x7F, 0x5B, 0x41, 0x5F, 0x7F, 0x80};
+// const uint8_t invertDisplayIcon[] = {
+//     // width = 24
+//     // height = 16
+//     0xFE, 0x01, 0x79, 0x25, 0x79, 0x01, 0xFE, 0x00, 0x20, 0x20, 0x20, 0x20, 0xDF, 0x07, 0x8F, 0xDF, 0xFF, 0x01, 0xFE, 0x86, 0xDA, 0x86, 0xFE, 0x01,
+//     0x7F, 0x80, 0xA4, 0xBE, 0xA0, 0x80, 0x7F, 0x00, 0x04, 0x0E, 0x1F, 0x04, 0xFB, 0xFB, 0xFB, 0xFB, 0xFF, 0x80, 0x7F, 0x5B, 0x41, 0x5F, 0x7F, 0x80};
 
 const uint8_t infinityIcon[] = {
     // width = 24
diff --git a/source/Core/Drivers/OLED.cpp b/source/Core/Drivers/OLED.cpp
index 60bad499..6ca691db 100644
--- a/source/Core/Drivers/OLED.cpp
+++ b/source/Core/Drivers/OLED.cpp
@@ -222,7 +222,7 @@ void OLED::maskScrollIndicatorOnOLED() {
   // it from the screen buffer which is updated by `OLED::setRotation`.
   uint8_t rightmostColumn = screenBuffer[7];
   uint8_t maskCommands[]  = {
-       // Set column address:
+      // Set column address:
       //  A[6:0] - Column start address = rightmost column
       //  B[6:0] - Column end address = rightmost column
       0x80,
@@ -431,9 +431,9 @@ inline void stripLeaderZeros(char *buffer, uint8_t places) {
     }
   }
 }
-void OLED::drawHex(uint32_t x, FontStyle fontStyle) {
+void OLED::drawHex(uint32_t x, FontStyle fontStyle, uint8_t digits) {
   // print number to hex
-  for (uint_fast8_t i = 0; i < 8; i++) {
+  for (uint_fast8_t i = 0; i < digits; i++) {
     uint16_t value = (x >> (4 * (7 - i))) & 0b1111;
     drawChar(value + 2, fontStyle);
   }
diff --git a/source/Core/Drivers/OLED.hpp b/source/Core/Drivers/OLED.hpp
index 0d6f790c..f088f91a 100644
--- a/source/Core/Drivers/OLED.hpp
+++ b/source/Core/Drivers/OLED.hpp
@@ -89,7 +89,7 @@ public:
   // Draws a checkbox
   static void drawCheckbox(bool state) { drawSymbol((state) ? 16 : 17); }
   static void debugNumber(int32_t val, FontStyle fontStyle);
-  static void drawHex(uint32_t x, FontStyle fontStyle);
+  static void drawHex(uint32_t x, FontStyle fontStyle, uint8_t digits);
   static void drawSymbol(uint8_t symbolID);                                                           // Used for drawing symbols of a predictable width
   static void drawArea(int16_t x, int8_t y, uint8_t wide, uint8_t height, const uint8_t *ptr);        // Draw an area, but y must be aligned on 0/8 offset
   static void drawAreaSwapped(int16_t x, int8_t y, uint8_t wide, uint8_t height, const uint8_t *ptr); // Draw an area, but y must be aligned on 0/8 offset
diff --git a/source/Core/Drivers/TipThermoModel.cpp b/source/Core/Drivers/TipThermoModel.cpp
index 4e708d54..c71f2332 100644
--- a/source/Core/Drivers/TipThermoModel.cpp
+++ b/source/Core/Drivers/TipThermoModel.cpp
@@ -9,6 +9,7 @@
 #include "BSP.h"
 #include "Settings.h"
 #include "Utils.h"
+#include "configuration.h"
 #include "main.hpp"
 #include "power.hpp"
 /*
@@ -32,10 +33,10 @@ uint32_t          TipThermoModel::convertTipRawADCTouV(uint16_t rawADC, bool ski
   // This takes the raw ADC samples, converts these to uV
   // Then divides this down by the gain to convert to the uV on the input to the op-amp (A+B terminals)
   // Then remove the calibration value that is stored as a tip offset
-  uint32_t vddRailmVX10 = 33000; // The vreg is +-2%, but we have no higher accuracy available
+  uint32_t vddRailmVX10 = ADC_VDD_MV * 10; // The vreg is +-2%, but we have no higher accuracy available
   // 4096 * 8 readings for full scale
   // Convert the input ADC reading back into mV times 10 format.
-  uint32_t rawInputmVX10 = (rawADC * vddRailmVX10) / (4096 * 8);
+  uint32_t rawInputmVX10 = (rawADC * vddRailmVX10) / (ADC_MAX_READING);
 
   uint32_t valueuV = rawInputmVX10 * 100; // shift into uV
   // Now to divide this down by the gain
@@ -89,7 +90,7 @@ uint32_t TipThermoModel::getTipInF(bool sampleNow) {
 }
 
 uint32_t TipThermoModel::getTipMaxInC() {
-  uint32_t maximumTipTemp = TipThermoModel::convertTipRawADCToDegC(0x7FFF - (21 * 3)); // back off approx 5 deg c from ADC max
-  maximumTipTemp += getHandleTemperature(0) / 10;                                      // Add handle offset
+  uint32_t maximumTipTemp = TipThermoModel::convertTipRawADCToDegC(ADC_MAX_READING - 1);
+  maximumTipTemp += getHandleTemperature(0) / 10; // Add handle offset
   return maximumTipTemp - 1;
 }
diff --git a/source/Core/Drivers/USBPD.cpp b/source/Core/Drivers/USBPD.cpp
index 2111bf32..f7d9020c 100644
--- a/source/Core/Drivers/USBPD.cpp
+++ b/source/Core/Drivers/USBPD.cpp
@@ -66,6 +66,7 @@ bool USBPowerDelivery::fusbPresent() {
 }
 
 bool USBPowerDelivery::isVBUSConnected() {
+#if NEEDS_VBUS_PROBE == 1
   static uint8_t state = 0;
   if (state) {
     return state == 1;
@@ -81,6 +82,9 @@ bool USBPowerDelivery::isVBUSConnected() {
     state = 2;
     return false;
   }
+#else
+  return false;
+#endif
 }
 uint32_t  lastCapabilities[11];
 uint32_t *USBPowerDelivery::getLastSeenCapabilities() { return lastCapabilities; }
diff --git a/source/Core/Drivers/Utils.cpp b/source/Core/Drivers/Utils.cpp
index 9d85ef38..2f0587b5 100644
--- a/source/Core/Drivers/Utils.cpp
+++ b/source/Core/Drivers/Utils.cpp
@@ -7,7 +7,7 @@
 
 #include 
 
-int32_t Utils::InterpolateLookupTable(const uint16_t *lookupTable, const int noItems, const uint16_t value) {
+int32_t Utils::InterpolateLookupTable(const int32_t *lookupTable, const int noItems, const int32_t value) {
   if (value) {
     for (int i = 1; i < (noItems - 1); i++) {
       // If current tip temp is less than current lookup, then this current lookup is the higher point to interpolate
diff --git a/source/Core/Drivers/Utils.h b/source/Core/Drivers/Utils.h
index a4e2b07c..040de2c6 100644
--- a/source/Core/Drivers/Utils.h
+++ b/source/Core/Drivers/Utils.h
@@ -10,7 +10,7 @@
 #include 
 class Utils {
 public:
-  static int32_t InterpolateLookupTable(const uint16_t *lookupTable, const int noItems, const uint16_t value);
+  static int32_t InterpolateLookupTable(const int32_t *lookupTable, const int noItems, const int32_t value);
   static int32_t LinearInterpolate(int32_t x1, int32_t y1, int32_t x2, int32_t y2, int32_t x);
 };
 
diff --git a/source/Core/Inc/Translation.h b/source/Core/Inc/Translation.h
index cf90ead3..124c1b99 100644
--- a/source/Core/Inc/Translation.h
+++ b/source/Core/Inc/Translation.h
@@ -83,6 +83,7 @@ struct TranslationIndexTable {
   uint16_t SleepingAdvancedString;
   uint16_t SleepingTipAdvancedString;
   uint16_t OffString;
+  uint16_t DeviceFailedValidationWarning;
 
   uint16_t SettingsResetMessage;
   uint16_t NoAccelerometerMessage;
diff --git a/source/Core/Inc/expMovingAverage.h b/source/Core/Inc/expMovingAverage.h
index af88ba95..b3bba9c9 100644
--- a/source/Core/Inc/expMovingAverage.h
+++ b/source/Core/Inc/expMovingAverage.h
@@ -8,7 +8,6 @@
 #ifndef INC_EXPMOVINGAVERAGE_H_
 #define INC_EXPMOVINGAVERAGE_H_
 
-// max size = 127
 template  struct expMovingAverage {
   int32_t sum;
   void    update(T const val) { sum = ((val * weighting) + (sum * (256 - weighting))) / 256; }
diff --git a/source/Core/Inc/history.hpp b/source/Core/Inc/history.hpp
index 6718e3c6..6ab51b21 100644
--- a/source/Core/Inc/history.hpp
+++ b/source/Core/Inc/history.hpp
@@ -14,7 +14,7 @@
 template  struct history {
   static const uint8_t size = SIZE;
   T                    buf[size];
-  int32_t              sum;
+  uint32_t             sum;
   uint8_t              loc;
 
   void update(T const val) {
diff --git a/source/Core/Inc/main.hpp b/source/Core/Inc/main.hpp
index c2216408..a3bc02b6 100644
--- a/source/Core/Inc/main.hpp
+++ b/source/Core/Inc/main.hpp
@@ -1,6 +1,6 @@
 #ifndef __MAIN_H
 #define __MAIN_H
-
+#include 
 #include "OLED.hpp"
 #include "Setup.h"
 extern volatile uint32_t currentTempTargetDegC;
diff --git a/source/Core/Inc/settingsGUI.hpp b/source/Core/Inc/settingsGUI.hpp
index 9905973f..b64e14ea 100644
--- a/source/Core/Inc/settingsGUI.hpp
+++ b/source/Core/Inc/settingsGUI.hpp
@@ -29,7 +29,9 @@ typedef struct {
   void (*const draw)(void);
   bool (*const isVisible)(void);
   // If this is set, we will automatically use the settings increment handler instead, set >= num settings to disable
-  SettingsOptions autoSettingOption;
+  SettingsOptions   autoSettingOption;
+  SettingsItemIndex shortDescriptionIndex;
+  uint8_t           shortDescriptionSize;
 } menuitem;
 
 void                  enterSettingsMenu();
diff --git a/source/Core/Src/FreeRTOSHooks.c b/source/Core/Src/FreeRTOSHooks.c
index d795f04b..a4fec381 100644
--- a/source/Core/Src/FreeRTOSHooks.c
+++ b/source/Core/Src/FreeRTOSHooks.c
@@ -20,7 +20,7 @@ void vApplicationGetIdleTaskMemory(StaticTask_t **ppxIdleTaskTCBBuffer, StackTyp
   /* place for user code */
 }
 
-void vApplicationStackOverflowHook(TaskHandle_t *pxTask, signed portCHAR *pcTaskName) {
+void vApplicationStackOverflowHook(TaskHandle_t *pxTask, signed char *pcTaskName) {
   (void)pxTask;
   (void)pcTaskName;
 
diff --git a/source/Core/Src/main.cpp b/source/Core/Src/main.cpp
index a7317d61..7b92316b 100644
--- a/source/Core/Src/main.cpp
+++ b/source/Core/Src/main.cpp
@@ -14,22 +14,22 @@ bool      settingsWereReset            = false;
 // FreeRTOS variables
 
 osThreadId          GUITaskHandle;
-static const size_t GUITaskStackSize = 1024 / 4;
+static const size_t GUITaskStackSize = 1024 / 2;
 uint32_t            GUITaskBuffer[GUITaskStackSize];
 osStaticThreadDef_t GUITaskControlBlock;
 
 osThreadId          PIDTaskHandle;
-static const size_t PIDTaskStackSize = 1024 / 4;
+static const size_t PIDTaskStackSize = 1024 / 2;
 uint32_t            PIDTaskBuffer[PIDTaskStackSize];
 osStaticThreadDef_t PIDTaskControlBlock;
 
 osThreadId          MOVTaskHandle;
-static const size_t MOVTaskStackSize = 1024 / 4;
+static const size_t MOVTaskStackSize = 1024 / 2;
 uint32_t            MOVTaskBuffer[MOVTaskStackSize];
 osStaticThreadDef_t MOVTaskControlBlock;
 
 osThreadId          POWTaskHandle;
-static const size_t POWTaskStackSize = 512 / 4;
+static const size_t POWTaskStackSize = 512 / 2;
 uint32_t            POWTaskBuffer[POWTaskStackSize];
 osStaticThreadDef_t POWTaskControlBlock;
 
@@ -37,10 +37,13 @@ osStaticThreadDef_t POWTaskControlBlock;
 // Main sets up the hardware then hands over to the FreeRTOS kernel
 int main(void) {
   preRToSInit();
-  setTipX10Watts(0); // force tip off
+
   resetWatchdog();
   // Testing for which accelerometer is mounted
   settingsWereReset = loadSettings(); // load the settings from flash
+
+  setTipX10Watts(0); // force tip off
+
   resetWatchdog();
   /* Create the thread(s) */
 
diff --git a/source/Core/Src/power.cpp b/source/Core/Src/power.cpp
index 593c4945..88d0509b 100644
--- a/source/Core/Src/power.cpp
+++ b/source/Core/Src/power.cpp
@@ -48,8 +48,12 @@ uint32_t availableW10(uint8_t sample) {
   // P = V^2 / R, v*v = v^2 * 100
   //				R = R*10
   // P therefore is in V^2*100/R*10 = W*10.
-  uint32_t v                 = getInputVoltageX10(getSettingValue(SettingsOptions::VoltageDiv), sample); // 100 = 10v
-  uint32_t availableWattsX10 = (v * v) / getTipResistanceX10();
+  uint32_t v             = getInputVoltageX10(getSettingValue(SettingsOptions::VoltageDiv), sample); // 100 = 10v
+  uint32_t tipResistance = getTipResistanceX10();
+  if (tipResistance == 0) {
+    return 100; // say 100 watt to force scale down
+  }
+  uint32_t availableWattsX10 = (v * v) / tipResistance;
   // However, 100% duty cycle is not possible as there is a dead time while the ADC takes a reading
   // Therefore need to scale available milliwats by this
 
diff --git a/source/Core/Src/settingsGUI.cpp b/source/Core/Src/settingsGUI.cpp
index 0f44e6ee..7d2c2061 100644
--- a/source/Core/Src/settingsGUI.cpp
+++ b/source/Core/Src/settingsGUI.cpp
@@ -17,78 +17,78 @@
 void gui_Menu(const menuitem *menu);
 
 #ifdef POW_DC
-static void settings_displayInputVRange(void);
-static bool settings_showInputVOptions(void);
-static void settings_displayInputMinVRange(void);
+static void displayInputVRange(void);
+static bool showInputVOptions(void);
+static void displayInputMinVRange(void);
 #endif
 #ifdef POW_QC
-static void settings_displayQCInputV(void);
+static void displayQCInputV(void);
 #endif
 #if POW_PD
-static void settings_displayPDNegTimeout(void);
+static void displayPDNegTimeout(void);
 #endif
-static void settings_displaySensitivity(void);
-static void settings_displayShutdownTime(void);
-static bool settings_showSleepOptions(void);
+static void displaySensitivity(void);
+static void displayShutdownTime(void);
+static bool showSleepOptions(void);
 #ifndef NO_SLEEP_MODE
-static bool settings_setSleepTemp(void);
-static void settings_displaySleepTemp(void);
-static void settings_displaySleepTime(void);
+static bool setSleepTemp(void);
+static void displaySleepTemp(void);
+static void displaySleepTime(void);
 #endif
-static bool settings_setTempF(void);
-static void settings_displayTempF(void);
-static void settings_displayAdvancedSolderingScreens(void);
-static void settings_displayAdvancedIDLEScreens(void);
-static void settings_displayScrollSpeed(void);
-static void settings_displayPowerLimit(void);
+static bool setTempF(void);
+static void displayTempF(void);
+static void displayAdvancedSolderingScreens(void);
+static void displayAdvancedIDLEScreens(void);
+static void displayScrollSpeed(void);
+static void displayPowerLimit(void);
 #ifndef NO_DISPLAY_ROTATE
-static bool settings_setDisplayRotation(void);
-static void settings_displayDisplayRotation(void);
+static bool setDisplayRotation(void);
+static void displayDisplayRotation(void);
 #endif
 
-static bool settings_setBoostTemp(void);
-static void settings_displayBoostTemp(void);
-static void settings_displayAutomaticStartMode(void);
-static void settings_displayLockingMode(void);
-static void settings_displayCoolingBlinkEnabled(void);
-static bool settings_setResetSettings(void);
-static void settings_displayResetSettings(void);
-static bool settings_setCalibrate(void);
-static void settings_displayCalibrate(void);
-static bool settings_setCalibrateVIN(void);
-static void settings_displayCalibrateVIN(void);
-static void settings_displayReverseButtonTempChangeEnabled(void);
-static void settings_displayTempChangeShortStep(void);
-static void settings_displayTempChangeLongStep(void);
-static void settings_displayPowerPulse(void);
-static bool settings_displayAnimationOptions(void);
-static void settings_displayAnimationSpeed(void);
-static void settings_displayAnimationLoop(void);
-static void settings_displayPowerPulseWait(void);
-static bool settings_showPowerPulseOptions(void);
-static void settings_displayPowerPulseDuration(void);
-static void settings_displayBrightnessLevel(void);
-static void settings_displayInvertColor(void);
-static void settings_displayLogoTime(void);
+static bool setBoostTemp(void);
+static void displayBoostTemp(void);
+static void displayAutomaticStartMode(void);
+static void displayLockingMode(void);
+static void displayCoolingBlinkEnabled(void);
+static bool setResetSettings(void);
+static void displayResetSettings(void);
+static bool setCalibrate(void);
+static void displayCalibrate(void);
+static bool setCalibrateVIN(void);
+static void displayCalibrateVIN(void);
+static void displayReverseButtonTempChangeEnabled(void);
+static void displayTempChangeShortStep(void);
+static void displayTempChangeLongStep(void);
+static void displayPowerPulse(void);
+static bool displayAnimationOptions(void);
+static void displayAnimationSpeed(void);
+static void displayAnimationLoop(void);
+static void displayPowerPulseWait(void);
+static bool showPowerPulseOptions(void);
+static void displayPowerPulseDuration(void);
+static void displayBrightnessLevel(void);
+static void displayInvertColor(void);
+static void displayLogoTime(void);
 
 #ifdef HALL_SENSOR
-static void settings_displayHallEffect(void);
-static bool settings_showHallEffect(void);
+static void displayHallEffect(void);
+static bool showHallEffect(void);
 #endif
 // Menu functions
 
 #if defined(POW_DC) || defined(POW_QC)
-static void settings_displayPowerMenu(void);
-static bool settings_enterPowerMenu(void);
+static void displayPowerMenu(void);
+static bool enterPowerMenu(void);
 #endif
-static void settings_displaySolderingMenu(void);
-static bool settings_enterSolderingMenu(void);
-static void settings_displayPowerSavingMenu(void);
-static bool settings_enterPowerSavingMenu(void);
-static void settings_displayUIMenu(void);
-static bool settings_enterUIMenu(void);
-static void settings_displayAdvancedMenu(void);
-static bool settings_enterAdvancedMenu(void);
+static void displaySolderingMenu(void);
+static bool enterSolderingMenu(void);
+static void displayPowerSavingMenu(void);
+static bool enterPowerSavingMenu(void);
+static void displayUIMenu(void);
+static bool enterUIMenu(void);
+static void displayAdvancedMenu(void);
+static bool enterAdvancedMenu(void);
 /*
  * Root Settings Menu
  *
@@ -146,15 +146,15 @@ const menuitem rootSettingsMenu[] {
    */
 
 #if defined(POW_DC) || defined(POW_QC)
-  {0, settings_enterPowerMenu, settings_displayPowerMenu, nullptr, SettingsOptions::SettingsOptionsLength}, /*Power*/
+  {0, enterPowerMenu, displayPowerMenu, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::NUM_ITEMS, 0}, /*Power*/
 #endif
-      {0, settings_enterSolderingMenu, settings_displaySolderingMenu, nullptr, SettingsOptions::SettingsOptionsLength},                     /*Soldering*/
-      {0, settings_enterPowerSavingMenu, settings_displayPowerSavingMenu, nullptr, SettingsOptions::SettingsOptionsLength},                 /*Sleep Options Menu*/
-      {0, settings_enterUIMenu, settings_displayUIMenu, nullptr, SettingsOptions::SettingsOptionsLength},                                   /*UI Menu*/
-      {0, settings_enterAdvancedMenu, settings_displayAdvancedMenu, nullptr, SettingsOptions::SettingsOptionsLength},                       /*Advanced Menu*/
-      {0, settings_setLanguageSwitch, settings_displayLanguageSwitch, settings_showLanguageSwitch, SettingsOptions::SettingsOptionsLength}, /*Language Switch*/
+      {0, enterSolderingMenu, displaySolderingMenu, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::NUM_ITEMS, 0},                                       /*Soldering*/
+      {0, enterPowerSavingMenu, displayPowerSavingMenu, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::NUM_ITEMS, 0},                                   /*Sleep Options Menu*/
+      {0, enterUIMenu, displayUIMenu, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::NUM_ITEMS, 0},                                                     /*UI Menu*/
+      {0, enterAdvancedMenu, displayAdvancedMenu, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::NUM_ITEMS, 0},                                         /*Advanced Menu*/
+      {0, settings_setLanguageSwitch, settings_displayLanguageSwitch, settings_showLanguageSwitch, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::NUM_ITEMS, 0}, /*Language Switch*/
   {
-    0, nullptr, nullptr, nullptr, SettingsOptions::SettingsOptionsLength
+    0, nullptr, nullptr, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::NUM_ITEMS, 0
   } // end of menu marker. DO NOT REMOVE
 };
 
@@ -167,16 +167,16 @@ const menuitem powerMenu[] = {
  *  PD Timeout
  */
 #ifdef POW_DC
-    {SETTINGS_DESC(SettingsItemIndex::DCInCutoff), nullptr, settings_displayInputVRange, nullptr, SettingsOptions::MinDCVoltageCells},                     /*Voltage input*/
-    {SETTINGS_DESC(SettingsItemIndex::MinVolCell), nullptr, settings_displayInputMinVRange, settings_showInputVOptions, SettingsOptions::MinVoltageCells}, /*Minimum voltage input*/
+    {SETTINGS_DESC(SettingsItemIndex::DCInCutoff), nullptr, displayInputVRange, nullptr, SettingsOptions::MinDCVoltageCells, SettingsItemIndex::DCInCutoff, 6},            /*Voltage input*/
+    {SETTINGS_DESC(SettingsItemIndex::MinVolCell), nullptr, displayInputMinVRange, showInputVOptions, SettingsOptions::MinVoltageCells, SettingsItemIndex::MinVolCell, 5}, /*Minimum voltage input*/
 #endif
 #ifdef POW_QC
-    {SETTINGS_DESC(SettingsItemIndex::QCMaxVoltage), nullptr, settings_displayQCInputV, nullptr, SettingsOptions::QCIdealVoltage}, /*Voltage input*/
+    {SETTINGS_DESC(SettingsItemIndex::QCMaxVoltage), nullptr, displayQCInputV, nullptr, SettingsOptions::QCIdealVoltage, SettingsItemIndex::QCMaxVoltage, 4}, /*Voltage input*/
 #endif
 #if POW_PD
-    {SETTINGS_DESC(SettingsItemIndex::PDNegTimeout), nullptr, settings_displayPDNegTimeout, nullptr, SettingsOptions::PDNegTimeout}, /*PD timeout setup*/
+    {SETTINGS_DESC(SettingsItemIndex::PDNegTimeout), nullptr, displayPDNegTimeout, nullptr, SettingsOptions::PDNegTimeout, SettingsItemIndex::PDNegTimeout, 5}, /*PD timeout setup*/
 #endif
-    {0, nullptr, nullptr, nullptr, SettingsOptions::SettingsOptionsLength} // end of menu marker. DO NOT REMOVE
+    {0, nullptr, nullptr, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::NUM_ITEMS, 0} // end of menu marker. DO NOT REMOVE
 };
 #endif
 const menuitem solderingMenu[] = {
@@ -187,12 +187,14 @@ const menuitem solderingMenu[] = {
      *  Temp change long step
      *	Locking Mode
      */
-    {SETTINGS_DESC(SettingsItemIndex::BoostTemperature), settings_setBoostTemp, settings_displayBoostTemp, nullptr, SettingsOptions::SettingsOptionsLength}, /*Boost Temp*/
-    {SETTINGS_DESC(SettingsItemIndex::AutoStart), nullptr, settings_displayAutomaticStartMode, nullptr, SettingsOptions::AutoStartMode},                     /*Auto start*/
-    {SETTINGS_DESC(SettingsItemIndex::TempChangeShortStep), nullptr, settings_displayTempChangeShortStep, nullptr, SettingsOptions::TempChangeShortStep},    /*Temp change short step*/
-    {SETTINGS_DESC(SettingsItemIndex::TempChangeLongStep), nullptr, settings_displayTempChangeLongStep, nullptr, SettingsOptions::TempChangeLongStep},       /*Temp change long step*/
-    {SETTINGS_DESC(SettingsItemIndex::LockingMode), nullptr, settings_displayLockingMode, nullptr, SettingsOptions::LockingMode},                            /*Locking Mode*/
-    {0, nullptr, nullptr, nullptr, SettingsOptions::SettingsOptionsLength}                                                                                   // end of menu marker. DO NOT REMOVE
+    {SETTINGS_DESC(SettingsItemIndex::BoostTemperature), setBoostTemp, displayBoostTemp, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::BoostTemperature, 5}, /*Boost Temp*/
+    {SETTINGS_DESC(SettingsItemIndex::AutoStart), nullptr, displayAutomaticStartMode, nullptr, SettingsOptions::AutoStartMode, SettingsItemIndex::AutoStart, 7},                   /*Auto start*/
+    {SETTINGS_DESC(SettingsItemIndex::TempChangeShortStep), nullptr, displayTempChangeShortStep, nullptr, SettingsOptions::TempChangeShortStep, SettingsItemIndex::TempChangeShortStep,
+     6}, /*Temp change short step*/
+    {SETTINGS_DESC(SettingsItemIndex::TempChangeLongStep), nullptr, displayTempChangeLongStep, nullptr, SettingsOptions::TempChangeLongStep, SettingsItemIndex::TempChangeLongStep,
+     6},                                                                                                                                                    /*Temp change long step*/
+    {SETTINGS_DESC(SettingsItemIndex::LockingMode), nullptr, displayLockingMode, nullptr, SettingsOptions::LockingMode, SettingsItemIndex::LockingMode, 7}, /*Locking Mode*/
+    {0, nullptr, nullptr, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::NUM_ITEMS, 0}                                                 // end of menu marker. DO NOT REMOVE
 };
 const menuitem PowerSavingMenu[] = {
     /*
@@ -201,16 +203,18 @@ const menuitem PowerSavingMenu[] = {
      * 	-Sleep Time
      * 	-Shutdown Time
      */
-    {SETTINGS_DESC(SettingsItemIndex::MotionSensitivity), nullptr, settings_displaySensitivity, nullptr, SettingsOptions::Sensitivity}, /* Motion Sensitivity*/
+    {SETTINGS_DESC(SettingsItemIndex::MotionSensitivity), nullptr, displaySensitivity, nullptr, SettingsOptions::Sensitivity, SettingsItemIndex::MotionSensitivity, 7}, /* Motion Sensitivity*/
 #ifndef NO_SLEEP_MODE
-    {SETTINGS_DESC(SettingsItemIndex::SleepTemperature), settings_setSleepTemp, settings_displaySleepTemp, settings_showSleepOptions, SettingsOptions::SettingsOptionsLength}, /*Sleep Temp*/
-    {SETTINGS_DESC(SettingsItemIndex::SleepTimeout), nullptr, settings_displaySleepTime, settings_showSleepOptions, SettingsOptions::SleepTime},                               /*Sleep Time*/
+    {SETTINGS_DESC(SettingsItemIndex::SleepTemperature), setSleepTemp, displaySleepTemp, showSleepOptions, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::SleepTemperature,
+     5},                                                                                                                                                           /*Sleep Temp*/
+    {SETTINGS_DESC(SettingsItemIndex::SleepTimeout), nullptr, displaySleepTime, showSleepOptions, SettingsOptions::SleepTime, SettingsItemIndex::SleepTimeout, 5}, /*Sleep Time*/
 #endif
-    {SETTINGS_DESC(SettingsItemIndex::ShutdownTimeout), nullptr, settings_displayShutdownTime, settings_showSleepOptions, SettingsOptions::ShutdownTime}, /*Shutdown Time*/
+    {SETTINGS_DESC(SettingsItemIndex::ShutdownTimeout), nullptr, displayShutdownTime, showSleepOptions, SettingsOptions::ShutdownTime, SettingsItemIndex::ShutdownTimeout, 5}, /*Shutdown Time*/
 #ifdef HALL_SENSOR
-    {SETTINGS_DESC(SettingsItemIndex::HallEffSensitivity), nullptr, settings_displayHallEffect, settings_showHallEffect, SettingsOptions::HallEffectSensitivity}, /* HallEffect Sensitivity*/
+    {SETTINGS_DESC(SettingsItemIndex::HallEffSensitivity), nullptr, displayHallEffect, showHallEffect, SettingsOptions::HallEffectSensitivity, SettingsItemIndex::HallEffSensitivity,
+     7}, /* HallEffect Sensitivity*/
 #endif
-    {0, nullptr, nullptr, nullptr, SettingsOptions::SettingsOptionsLength} // end of menu marker. DO NOT REMOVE
+    {0, nullptr, nullptr, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::NUM_ITEMS, 0} // end of menu marker. DO NOT REMOVE
 };
 const menuitem UIMenu[] = {
     /*
@@ -228,23 +232,26 @@ const menuitem UIMenu[] = {
      *  Detailed IDLE
      *  Detailed Soldering
      */
-    {SETTINGS_DESC(SettingsItemIndex::TemperatureUnit), settings_setTempF, settings_displayTempF, nullptr,
-     SettingsOptions::SettingsOptionsLength}, /* Temperature units, this has to be the first element in the array to work with the logic in settings_enterUIMenu() */
+    {SETTINGS_DESC(SettingsItemIndex::TemperatureUnit), setTempF, displayTempF, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::TemperatureUnit,
+     7}, /* Temperature units, this has to be the first element in the array to work with the logic in enterUIMenu() */
 #ifndef NO_DISPLAY_ROTATE
-    {SETTINGS_DESC(SettingsItemIndex::DisplayRotation), settings_setDisplayRotation, settings_displayDisplayRotation, nullptr, SettingsOptions::SettingsOptionsLength}, /*Display Rotation*/
+    {SETTINGS_DESC(SettingsItemIndex::DisplayRotation), setDisplayRotation, displayDisplayRotation, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::DisplayRotation,
+     7}, /*Display Rotation*/
 #endif
-    {SETTINGS_DESC(SettingsItemIndex::CooldownBlink), nullptr, settings_displayCoolingBlinkEnabled, nullptr, SettingsOptions::CoolingTempBlink}, /*Cooling blink warning*/
-    {SETTINGS_DESC(SettingsItemIndex::ScrollingSpeed), nullptr, settings_displayScrollSpeed, nullptr, SettingsOptions::DescriptionScrollSpeed},  /*Scroll Speed for descriptions*/
-    {SETTINGS_DESC(SettingsItemIndex::ReverseButtonTempChange), nullptr, settings_displayReverseButtonTempChangeEnabled, nullptr,
-     SettingsOptions::ReverseButtonTempChangeEnabled},                                                                                                      /*Reverse Temp change buttons + - */
-    {SETTINGS_DESC(SettingsItemIndex::AnimSpeed), nullptr, settings_displayAnimationSpeed, nullptr, SettingsOptions::AnimationSpeed},                       /*Animation Speed adjustment */
-    {SETTINGS_DESC(SettingsItemIndex::AnimLoop), nullptr, settings_displayAnimationLoop, settings_displayAnimationOptions, SettingsOptions::AnimationLoop}, /*Animation Loop switch */
-    {SETTINGS_DESC(SettingsItemIndex::Brightness), nullptr, settings_displayBrightnessLevel, nullptr, SettingsOptions::OLEDBrightness},                     /*Brightness Level*/
-    {SETTINGS_DESC(SettingsItemIndex::ColourInversion), nullptr, settings_displayInvertColor, nullptr, SettingsOptions::OLEDInversion},                     /*Invert screen colour*/
-    {SETTINGS_DESC(SettingsItemIndex::LOGOTime), nullptr, settings_displayLogoTime, nullptr, SettingsOptions::LOGOTime},                                    /*Set logo duration*/
-    {SETTINGS_DESC(SettingsItemIndex::AdvancedIdle), nullptr, settings_displayAdvancedIDLEScreens, nullptr, SettingsOptions::DetailedIDLE},                 /*Advanced idle screen*/
-    {SETTINGS_DESC(SettingsItemIndex::AdvancedSoldering), nullptr, settings_displayAdvancedSolderingScreens, nullptr, SettingsOptions::DetailedSoldering},  /*Advanced soldering screen*/
-    {0, nullptr, nullptr, nullptr, SettingsOptions::SettingsOptionsLength}                                                                                  // end of menu marker. DO NOT REMOVE
+    {SETTINGS_DESC(SettingsItemIndex::CooldownBlink), nullptr, displayCoolingBlinkEnabled, nullptr, SettingsOptions::CoolingTempBlink, SettingsItemIndex::CooldownBlink, 7}, /*Cooling blink warning*/
+    {SETTINGS_DESC(SettingsItemIndex::ScrollingSpeed), nullptr, displayScrollSpeed, nullptr, SettingsOptions::DescriptionScrollSpeed, SettingsItemIndex::ScrollingSpeed,
+     7}, /*Scroll Speed for descriptions*/
+    {SETTINGS_DESC(SettingsItemIndex::ReverseButtonTempChange), nullptr, displayReverseButtonTempChangeEnabled, nullptr, SettingsOptions::ReverseButtonTempChangeEnabled,
+     SettingsItemIndex::ReverseButtonTempChange, 7},                                                                                                          /*Reverse Temp change buttons + - */
+    {SETTINGS_DESC(SettingsItemIndex::AnimSpeed), nullptr, displayAnimationSpeed, nullptr, SettingsOptions::AnimationSpeed, SettingsItemIndex::AnimSpeed, 7}, /*Animation Speed adjustment */
+    {SETTINGS_DESC(SettingsItemIndex::AnimLoop), nullptr, displayAnimationLoop, displayAnimationOptions, SettingsOptions::AnimationLoop, SettingsItemIndex::AnimLoop, 7}, /*Animation Loop switch */
+    {SETTINGS_DESC(SettingsItemIndex::Brightness), nullptr, displayBrightnessLevel, nullptr, SettingsOptions::OLEDBrightness, SettingsItemIndex::Brightness, 6},          /*Brightness Level*/
+    {SETTINGS_DESC(SettingsItemIndex::ColourInversion), nullptr, displayInvertColor, nullptr, SettingsOptions::OLEDInversion, SettingsItemIndex::ColourInversion, 7},     /*Invert screen colour*/
+    {SETTINGS_DESC(SettingsItemIndex::LOGOTime), nullptr, displayLogoTime, nullptr, SettingsOptions::LOGOTime, SettingsItemIndex::LOGOTime, 5},                           /*Set logo duration*/
+    {SETTINGS_DESC(SettingsItemIndex::AdvancedIdle), nullptr, displayAdvancedIDLEScreens, nullptr, SettingsOptions::DetailedIDLE, SettingsItemIndex::AdvancedIdle, 7},    /*Advanced idle screen*/
+    {SETTINGS_DESC(SettingsItemIndex::AdvancedSoldering), nullptr, displayAdvancedSolderingScreens, nullptr, SettingsOptions::DetailedSoldering, SettingsItemIndex::AdvancedSoldering,
+     7},                                                                                                    /*Advanced soldering screen*/
+    {0, nullptr, nullptr, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::NUM_ITEMS, 0} // end of menu marker. DO NOT REMOVE
 };
 const menuitem advancedMenu[] = {
 
@@ -257,15 +264,18 @@ const menuitem advancedMenu[] = {
      *  -Power Pulse Delay
      *  -Power Pulse duration
      */
-    {SETTINGS_DESC(SettingsItemIndex::PowerLimit), nullptr, settings_displayPowerLimit, nullptr, SettingsOptions::PowerLimit},                                        /*Power limit*/
-    {SETTINGS_DESC(SettingsItemIndex::SettingsReset), settings_setResetSettings, settings_displayResetSettings, nullptr, SettingsOptions::SettingsOptionsLength},     /*Resets settings*/
-    {SETTINGS_DESC(SettingsItemIndex::TemperatureCalibration), settings_setCalibrate, settings_displayCalibrate, nullptr, SettingsOptions::SettingsOptionsLength},    /*Calibrate tip*/
-    {SETTINGS_DESC(SettingsItemIndex::VoltageCalibration), settings_setCalibrateVIN, settings_displayCalibrateVIN, nullptr, SettingsOptions::SettingsOptionsLength},  /*Voltage input cal*/
-    {SETTINGS_DESC(SettingsItemIndex::PowerPulsePower), nullptr, settings_displayPowerPulse, nullptr, SettingsOptions::KeepAwakePulse},                               /*Power Pulse adjustment */
-    {SETTINGS_DESC(SettingsItemIndex::PowerPulseWait), nullptr, settings_displayPowerPulseWait, settings_showPowerPulseOptions, SettingsOptions::KeepAwakePulseWait}, /*Power Pulse Wait adjustment*/
-    {SETTINGS_DESC(SettingsItemIndex::PowerPulseDuration), nullptr, settings_displayPowerPulseDuration, settings_showPowerPulseOptions,
-     SettingsOptions::KeepAwakePulseDuration},                             /*Power Pulse Duration adjustment*/
-    {0, nullptr, nullptr, nullptr, SettingsOptions::SettingsOptionsLength} // end of menu marker. DO NOT REMOVE
+    {SETTINGS_DESC(SettingsItemIndex::PowerLimit), nullptr, displayPowerLimit, nullptr, SettingsOptions::PowerLimit, SettingsItemIndex::PowerLimit, 5},                              /*Power limit*/
+    {SETTINGS_DESC(SettingsItemIndex::SettingsReset), setResetSettings, displayResetSettings, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::SettingsReset, 7}, /*Resets settings*/
+    {SETTINGS_DESC(SettingsItemIndex::TemperatureCalibration), setCalibrate, displayCalibrate, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::TemperatureCalibration,
+     5}, /*Calibrate tip*/
+    {SETTINGS_DESC(SettingsItemIndex::VoltageCalibration), setCalibrateVIN, displayCalibrateVIN, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::VoltageCalibration,
+     5},                                                                                                                                                              /*Voltage input cal*/
+    {SETTINGS_DESC(SettingsItemIndex::PowerPulsePower), nullptr, displayPowerPulse, nullptr, SettingsOptions::KeepAwakePulse, SettingsItemIndex::PowerPulsePower, 5}, /*Power Pulse adjustment */
+    {SETTINGS_DESC(SettingsItemIndex::PowerPulseWait), nullptr, displayPowerPulseWait, showPowerPulseOptions, SettingsOptions::KeepAwakePulseWait, SettingsItemIndex::PowerPulseWait,
+     7}, /*Power Pulse Wait adjustment*/
+    {SETTINGS_DESC(SettingsItemIndex::PowerPulseDuration), nullptr, displayPowerPulseDuration, showPowerPulseOptions, SettingsOptions::KeepAwakePulseDuration, SettingsItemIndex::PowerPulseDuration,
+     7},                                                                                                    /*Power Pulse Duration adjustment*/
+    {0, nullptr, nullptr, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::NUM_ITEMS, 0} // end of menu marker. DO NOT REMOVE
 };
 
 /**
@@ -316,8 +326,7 @@ static int userConfirmation(const char *message) {
 }
 #ifdef POW_DC
 
-static void settings_displayInputVRange(void) {
-  printShortDescription(SettingsItemIndex::DCInCutoff, 6);
+static void displayInputVRange(void) {
 
   if (getSettingValue(SettingsOptions::MinDCVoltageCells)) {
     OLED::printNumber(2 + getSettingValue(SettingsOptions::MinDCVoltageCells), 1, FontStyle::LARGE);
@@ -327,9 +336,9 @@ static void settings_displayInputVRange(void) {
   }
 }
 
-static bool settings_showInputVOptions(void) { return getSettingValue(SettingsOptions::MinDCVoltageCells) > 0; }
-static void settings_displayInputMinVRange(void) {
-  printShortDescription(SettingsItemIndex::MinVolCell, 5);
+static bool showInputVOptions(void) { return getSettingValue(SettingsOptions::MinDCVoltageCells) > 0; }
+static void displayInputMinVRange(void) {
+
   OLED::printNumber(getSettingValue(SettingsOptions::MinVoltageCells) / 10, 1, FontStyle::LARGE);
   OLED::print(SymbolDot, FontStyle::LARGE);
   OLED::printNumber(getSettingValue(SettingsOptions::MinVoltageCells) % 10, 1, FontStyle::LARGE);
@@ -337,8 +346,8 @@ static void settings_displayInputMinVRange(void) {
 #endif
 #ifdef POW_QC
 
-static void settings_displayQCInputV(void) {
-  printShortDescription(SettingsItemIndex::QCMaxVoltage, 4);
+static void displayQCInputV(void) {
+
   // These are only used in QC modes
   // Allows setting the voltage negotiated for QC
   auto voltage = getSettingValue(SettingsOptions::QCIdealVoltage);
@@ -351,8 +360,8 @@ static void settings_displayQCInputV(void) {
 
 #if POW_PD
 
-static void settings_displayPDNegTimeout(void) {
-  printShortDescription(SettingsItemIndex::PDNegTimeout, 5);
+static void displayPDNegTimeout(void) {
+
   auto value = getSettingValue(SettingsOptions::PDNegTimeout);
   if (value == 0) {
     OLED::print(translatedString(Tr->OffString), FontStyle::LARGE);
@@ -362,8 +371,8 @@ static void settings_displayPDNegTimeout(void) {
 }
 #endif
 
-static void settings_displayShutdownTime(void) {
-  printShortDescription(SettingsItemIndex::ShutdownTimeout, 5);
+static void displayShutdownTime(void) {
+
   if (getSettingValue(SettingsOptions::ShutdownTime) == 0) {
     OLED::print(translatedString(Tr->OffString), FontStyle::LARGE);
   } else {
@@ -372,15 +381,12 @@ static void settings_displayShutdownTime(void) {
   }
 }
 
-static void settings_displaySensitivity(void) {
-  printShortDescription(SettingsItemIndex::MotionSensitivity, 7);
-  OLED::printNumber(getSettingValue(SettingsOptions::Sensitivity), 1, FontStyle::LARGE, false);
-}
-static bool settings_showSleepOptions(void) { return getSettingValue(SettingsOptions::Sensitivity) > 0; }
+static void displaySensitivity(void) { OLED::printNumber(getSettingValue(SettingsOptions::Sensitivity), 1, FontStyle::LARGE, false); }
+static bool showSleepOptions(void) { return getSettingValue(SettingsOptions::Sensitivity) > 0; }
 
 #ifndef NO_SLEEP_MODE
 
-static bool settings_setSleepTemp(void) {
+static bool setSleepTemp(void) {
   // If in C, 10 deg, if in F 20 deg
   uint16_t temp = getSettingValue(SettingsOptions::SleepTemp);
   if (getSettingValue(SettingsOptions::TemperatureInF)) {
@@ -398,13 +404,10 @@ static bool settings_setSleepTemp(void) {
   }
 }
 
-static void settings_displaySleepTemp(void) {
-  printShortDescription(SettingsItemIndex::SleepTemperature, 5);
-  OLED::printNumber(getSettingValue(SettingsOptions::SleepTemp), 3, FontStyle::LARGE);
-}
+static void displaySleepTemp(void) { OLED::printNumber(getSettingValue(SettingsOptions::SleepTemp), 3, FontStyle::LARGE); }
+
+static void displaySleepTime(void) {
 
-static void settings_displaySleepTime(void) {
-  printShortDescription(SettingsItemIndex::SleepTimeout, 5);
   if (getSettingValue(SettingsOptions::SleepTime) == 0) {
     OLED::print(translatedString(Tr->OffString), FontStyle::LARGE);
   } else if (getSettingValue(SettingsOptions::SleepTime) < 6) {
@@ -417,7 +420,7 @@ static void settings_displaySleepTime(void) {
 }
 #endif
 
-static bool settings_setTempF(void) {
+static bool setTempF(void) {
   bool     res           = nextSettingValue(SettingsOptions::TemperatureInF);
   uint16_t BoostTemp     = getSettingValue(SettingsOptions::BoostTemp);
   uint16_t SolderingTemp = getSettingValue(SettingsOptions::SolderingTemp);
@@ -450,23 +453,14 @@ static bool settings_setTempF(void) {
   return res;
 }
 
-static void settings_displayTempF(void) {
-  printShortDescription(SettingsItemIndex::TemperatureUnit, 7);
-  OLED::print((getSettingValue(SettingsOptions::TemperatureInF)) ? SymbolDegF : SymbolDegC, FontStyle::LARGE);
-}
+static void displayTempF(void) { OLED::print((getSettingValue(SettingsOptions::TemperatureInF)) ? SymbolDegF : SymbolDegC, FontStyle::LARGE); }
 
-static void settings_displayAdvancedSolderingScreens(void) {
-  printShortDescription(SettingsItemIndex::AdvancedSoldering, 7);
-  OLED::drawCheckbox(getSettingValue(SettingsOptions::DetailedSoldering));
-}
+static void displayAdvancedSolderingScreens(void) { OLED::drawCheckbox(getSettingValue(SettingsOptions::DetailedSoldering)); }
 
-static void settings_displayAdvancedIDLEScreens(void) {
-  printShortDescription(SettingsItemIndex::AdvancedIdle, 7);
-  OLED::drawCheckbox(getSettingValue(SettingsOptions::DetailedIDLE));
-}
+static void displayAdvancedIDLEScreens(void) { OLED::drawCheckbox(getSettingValue(SettingsOptions::DetailedIDLE)); }
+
+static void displayPowerLimit(void) {
 
-static void settings_displayPowerLimit(void) {
-  printShortDescription(SettingsItemIndex::PowerLimit, 5);
   if (getSettingValue(SettingsOptions::PowerLimit) == 0) {
     OLED::print(translatedString(Tr->OffString), FontStyle::LARGE);
   } else {
@@ -475,13 +469,10 @@ static void settings_displayPowerLimit(void) {
   }
 }
 
-static void settings_displayScrollSpeed(void) {
-  printShortDescription(SettingsItemIndex::ScrollingSpeed, 7);
-  OLED::print(translatedString((getSettingValue(SettingsOptions::DescriptionScrollSpeed)) ? Tr->SettingFastChar : Tr->SettingSlowChar), FontStyle::LARGE);
-}
+static void displayScrollSpeed(void) { OLED::print(translatedString((getSettingValue(SettingsOptions::DescriptionScrollSpeed)) ? Tr->SettingFastChar : Tr->SettingSlowChar), FontStyle::LARGE); }
 
 #ifndef NO_DISPLAY_ROTATE
-static bool settings_setDisplayRotation(void) {
+static bool setDisplayRotation(void) {
   bool res = nextSettingValue(SettingsOptions::OrientationMode);
   switch (getSettingValue(SettingsOptions::OrientationMode)) {
   case 0:
@@ -499,8 +490,7 @@ static bool settings_setDisplayRotation(void) {
   return res;
 }
 
-static void settings_displayDisplayRotation(void) {
-  printShortDescription(SettingsItemIndex::DisplayRotation, 7);
+static void displayDisplayRotation(void) {
 
   switch (getSettingValue(SettingsOptions::OrientationMode)) {
   case 0:
@@ -518,7 +508,7 @@ static void settings_displayDisplayRotation(void) {
   }
 }
 #endif
-static bool settings_setBoostTemp(void) {
+static bool setBoostTemp(void) {
   uint16_t value = getSettingValue(SettingsOptions::BoostTemp);
   if (getSettingValue(SettingsOptions::TemperatureInF)) {
     if (value == 0) {
@@ -545,8 +535,8 @@ static bool settings_setBoostTemp(void) {
   return value >= MAX_TEMP_C;
 }
 
-static void settings_displayBoostTemp(void) {
-  printShortDescription(SettingsItemIndex::BoostTemperature, 5);
+static void displayBoostTemp(void) {
+
   if (getSettingValue(SettingsOptions::BoostTemp)) {
     OLED::printNumber(getSettingValue(SettingsOptions::BoostTemp), 3, FontStyle::LARGE);
   } else {
@@ -554,8 +544,7 @@ static void settings_displayBoostTemp(void) {
   }
 }
 
-static void settings_displayAutomaticStartMode(void) {
-  printShortDescription(SettingsItemIndex::AutoStart, 7);
+static void displayAutomaticStartMode(void) {
 
   switch (getSettingValue(SettingsOptions::AutoStartMode)) {
   case 0:
@@ -576,8 +565,7 @@ static void settings_displayAutomaticStartMode(void) {
   }
 }
 
-static void settings_displayLockingMode(void) {
-  printShortDescription(SettingsItemIndex::LockingMode, 7);
+static void displayLockingMode(void) {
 
   switch (getSettingValue(SettingsOptions::LockingMode)) {
   case 0:
@@ -595,12 +583,9 @@ static void settings_displayLockingMode(void) {
   }
 }
 
-static void settings_displayCoolingBlinkEnabled(void) {
-  printShortDescription(SettingsItemIndex::CooldownBlink, 7);
-  OLED::drawCheckbox(getSettingValue(SettingsOptions::CoolingTempBlink));
-}
+static void displayCoolingBlinkEnabled(void) { OLED::drawCheckbox(getSettingValue(SettingsOptions::CoolingTempBlink)); }
 
-static bool settings_setResetSettings(void) {
+static bool setResetSettings(void) {
   if (userConfirmation(translatedString(Tr->SettingsResetWarning))) {
     resetSettings();
     warnUser(translatedString(Tr->SettingsResetMessage), 10 * TICKS_SECOND);
@@ -608,7 +593,7 @@ static bool settings_setResetSettings(void) {
   return false;
 }
 
-static void settings_displayResetSettings(void) { printShortDescription(SettingsItemIndex::SettingsReset, 7); }
+static void displayResetSettings(void) {}
 
 static void setTipOffset() {
   uint16_t setoffset = 0;
@@ -642,7 +627,7 @@ static void setTipOffset() {
 
 // Provide the user the option to tune their own tip if custom is selected
 // If not only do single point tuning as per usual
-static bool settings_setCalibrate(void) {
+static bool setCalibrate(void) {
 
   if (userConfirmation(translatedString(Tr->SettingsCalibrationWarning))) {
     // User confirmed
@@ -652,9 +637,9 @@ static bool settings_setCalibrate(void) {
   return false;
 }
 
-static void settings_displayCalibrate(void) { printShortDescription(SettingsItemIndex::TemperatureCalibration, 5); }
+static void displayCalibrate(void) {}
 
-static bool settings_setCalibrateVIN(void) {
+static bool setCalibrateVIN(void) {
   // Jump to the voltage calibration subscreen
   OLED::clearScreen();
 
@@ -693,23 +678,14 @@ static bool settings_setCalibrateVIN(void) {
   return false;
 }
 
-static void settings_displayReverseButtonTempChangeEnabled(void) {
-  printShortDescription(SettingsItemIndex::ReverseButtonTempChange, 7);
-  OLED::drawCheckbox(getSettingValue(SettingsOptions::ReverseButtonTempChangeEnabled));
-}
+static void displayReverseButtonTempChangeEnabled(void) { OLED::drawCheckbox(getSettingValue(SettingsOptions::ReverseButtonTempChangeEnabled)); }
 
-static void settings_displayTempChangeShortStep(void) {
-  printShortDescription(SettingsItemIndex::TempChangeShortStep, 6);
-  OLED::printNumber(getSettingValue(SettingsOptions::TempChangeShortStep), 2, FontStyle::LARGE);
-}
+static void displayTempChangeShortStep(void) { OLED::printNumber(getSettingValue(SettingsOptions::TempChangeShortStep), 2, FontStyle::LARGE); }
 
-static void settings_displayTempChangeLongStep(void) {
-  printShortDescription(SettingsItemIndex::TempChangeLongStep, 6);
-  OLED::printNumber(getSettingValue(SettingsOptions::TempChangeLongStep), 2, FontStyle::LARGE);
-}
+static void displayTempChangeLongStep(void) { OLED::printNumber(getSettingValue(SettingsOptions::TempChangeLongStep), 2, FontStyle::LARGE); }
+
+static void displayPowerPulse(void) {
 
-static void settings_displayPowerPulse(void) {
-  printShortDescription(SettingsItemIndex::PowerPulsePower, 5);
   if (getSettingValue(SettingsOptions::KeepAwakePulse)) {
     OLED::printNumber(getSettingValue(SettingsOptions::KeepAwakePulse) / 10, 1, FontStyle::LARGE);
     OLED::print(SymbolDot, FontStyle::LARGE);
@@ -719,14 +695,11 @@ static void settings_displayPowerPulse(void) {
   }
 }
 
-static bool settings_displayAnimationOptions(void) { return getSettingValue(SettingsOptions::AnimationSpeed) > 0; }
-static void settings_displayAnimationLoop(void) {
-  printShortDescription(SettingsItemIndex::AnimLoop, 7);
-  OLED::drawCheckbox(getSettingValue(SettingsOptions::AnimationLoop));
-}
+static bool displayAnimationOptions(void) { return getSettingValue(SettingsOptions::AnimationSpeed) > 0; }
+static void displayAnimationLoop(void) { OLED::drawCheckbox(getSettingValue(SettingsOptions::AnimationLoop)); }
+
+static void displayAnimationSpeed(void) {
 
-static void settings_displayAnimationSpeed(void) {
-  printShortDescription(SettingsItemIndex::AnimSpeed, 7);
   switch (getSettingValue(SettingsOptions::AnimationSpeed)) {
   case settingOffSpeed_t::SLOW:
     OLED::print(translatedString(Tr->SettingSlowChar), FontStyle::LARGE);
@@ -743,37 +716,27 @@ static void settings_displayAnimationSpeed(void) {
   }
 }
 
-static bool settings_showPowerPulseOptions(void) { return getSettingValue(SettingsOptions::KeepAwakePulse) > 0; }
-static void settings_displayPowerPulseWait(void) {
-  printShortDescription(SettingsItemIndex::PowerPulseWait, 7);
-  OLED::printNumber(getSettingValue(SettingsOptions::KeepAwakePulseWait), 1, FontStyle::LARGE);
-}
+static bool showPowerPulseOptions(void) { return getSettingValue(SettingsOptions::KeepAwakePulse) > 0; }
+static void displayPowerPulseWait(void) { OLED::printNumber(getSettingValue(SettingsOptions::KeepAwakePulseWait), 1, FontStyle::LARGE); }
 
-static void settings_displayPowerPulseDuration(void) {
-  printShortDescription(SettingsItemIndex::PowerPulseDuration, 7);
-  OLED::printNumber(getSettingValue(SettingsOptions::KeepAwakePulseDuration), 1, FontStyle::LARGE);
-}
+static void displayPowerPulseDuration(void) { OLED::printNumber(getSettingValue(SettingsOptions::KeepAwakePulseDuration), 1, FontStyle::LARGE); }
+
+static void displayBrightnessLevel(void) {
 
-static void settings_displayBrightnessLevel(void) {
-  OLED::drawArea(0, 0, 16, 16, brightnessIcon);
-  OLED::setCursor(6 * FONT_12_WIDTH - 2, 0);
-  // printShortDescription(SettingsItemIndex::Brightness, 7);
   OLED::printNumber((getSettingValue(SettingsOptions::OLEDBrightness) / 11 + 1), 2, FontStyle::LARGE);
   // While not optimal to apply this here, it is _very_ convienient
   OLED::setBrightness(getSettingValue(SettingsOptions::OLEDBrightness));
 }
 
-static void settings_displayInvertColor(void) {
-  OLED::drawArea(0, 0, 24, 16, invertDisplayIcon);
-  OLED::setCursor(7 * FONT_12_WIDTH - 2, 0);
-  // printShortDescription(SettingsItemIndex::ColourInversion, 7);
+static void displayInvertColor(void) {
+
   OLED::drawCheckbox(getSettingValue(SettingsOptions::OLEDInversion));
   // While not optimal to apply this here, it is _very_ convienient
   OLED::setInverseDisplay(getSettingValue(SettingsOptions::OLEDInversion));
 }
 
-static void settings_displayLogoTime(void) {
-  printShortDescription(SettingsItemIndex::LOGOTime, 5);
+static void displayLogoTime(void) {
+
   if (getSettingValue(SettingsOptions::LOGOTime) == 0) {
     OLED::print(translatedString(Tr->OffString), FontStyle::LARGE);
   } else if (getSettingValue(SettingsOptions::LOGOTime) == 5) {
@@ -785,11 +748,8 @@ static void settings_displayLogoTime(void) {
 }
 
 #ifdef HALL_SENSOR
-static void settings_displayHallEffect(void) {
-  printShortDescription(SettingsItemIndex::HallEffSensitivity, 7);
-  OLED::printNumber(getSettingValue(SettingsOptions::HallEffectSensitivity), 1, FontStyle::LARGE, false);
-}
-static bool settings_showHallEffect(void) { return getHallSensorFitted(); }
+static void displayHallEffect(void) { OLED::printNumber(getSettingValue(SettingsOptions::HallEffectSensitivity), 1, FontStyle::LARGE, false); }
+static bool showHallEffect(void) { return getHallSensorFitted(); }
 #endif
 
 // Indicates whether a menu transition is in progress, so that the menu icon
@@ -837,32 +797,32 @@ static void displayMenu(size_t index) {
   OLED::drawArea(OLED_WIDTH - 16 - 2, 0, 16, 16, (&SettingsMenuIcons[index][(16 * 2) * currentFrame]));
 }
 
-static void settings_displayCalibrateVIN(void) { printShortDescription(SettingsItemIndex::VoltageCalibration, 5); }
+static void displayCalibrateVIN(void) {}
 
 #if defined(POW_DC) || defined(POW_QC)
-static void settings_displayPowerMenu(void) { displayMenu(0); }
-static bool settings_enterPowerMenu(void) {
+static void displayPowerMenu(void) { displayMenu(0); }
+static bool enterPowerMenu(void) {
   gui_Menu(powerMenu);
   return false;
 }
 #endif
-static void settings_displaySolderingMenu(void) { displayMenu(1); }
-static bool settings_enterSolderingMenu(void) {
+static void displaySolderingMenu(void) { displayMenu(1); }
+static bool enterSolderingMenu(void) {
   gui_Menu(solderingMenu);
   return false;
 }
-static void settings_displayPowerSavingMenu(void) { displayMenu(2); }
-static bool settings_enterPowerSavingMenu(void) {
+static void displayPowerSavingMenu(void) { displayMenu(2); }
+static bool enterPowerSavingMenu(void) {
   gui_Menu(PowerSavingMenu);
   return false;
 }
-static void settings_displayUIMenu(void) { displayMenu(3); }
-static bool settings_enterUIMenu(void) {
+static void displayUIMenu(void) { displayMenu(3); }
+static bool enterUIMenu(void) {
   gui_Menu(HasFahrenheit ? UIMenu : UIMenu + 1);
   return false;
 }
-static void settings_displayAdvancedMenu(void) { displayMenu(4); }
-static bool settings_enterAdvancedMenu(void) {
+static void displayAdvancedMenu(void) { displayMenu(4); }
+static bool enterAdvancedMenu(void) {
   gui_Menu(advancedMenu);
   return false;
 }
@@ -934,6 +894,9 @@ void gui_Menu(const menuitem *menu) {
       }
       OLED::setCursor(0, 0);
       OLED::clearScreen();
+      if (menu[currentScreen].shortDescriptionSize > 0) {
+        printShortDescription(menu[currentScreen].shortDescriptionIndex, menu[currentScreen].shortDescriptionSize);
+      }
       menu[currentScreen].draw();
       if (navState == NavState::ScrollingDown) {
         // Play the scroll down animation.
@@ -957,6 +920,9 @@ void gui_Menu(const menuitem *menu) {
       lcdRefresh = true;
       OLED::setCursor(0, 0);
       OLED::clearScreen();
+      if (menu[currentScreen].shortDescriptionSize > 0) {
+        printShortDescription(menu[currentScreen].shortDescriptionIndex, menu[currentScreen].shortDescriptionSize);
+      }
       menu[currentScreen].draw();
       uint8_t indicatorHeight = OLED_HEIGHT / scrollContentSize;
       uint8_t position        = OLED_HEIGHT * (currentScreen - screensSkipped) / scrollContentSize;
diff --git a/source/Core/Threads/GUIThread.cpp b/source/Core/Threads/GUIThread.cpp
index 71762ac4..dd322d55 100644
--- a/source/Core/Threads/GUIThread.cpp
+++ b/source/Core/Threads/GUIThread.cpp
@@ -42,7 +42,7 @@ void              showWarnings();
 #define BUTTON_INACTIVITY_TIME   (60 * configTICK_RATE_HZ)
 static TickType_t lastHallEffectSleepStart = 0;
 static uint16_t   min(uint16_t a, uint16_t b) {
-    if (a > b)
+  if (a > b)
     return b;
   else
     return a;
@@ -132,14 +132,14 @@ static bool checkVoltageForExit() {
 static void gui_drawBatteryIcon() {
 #if defined(POW_PD) || defined(POW_QC)
   if (!getIsPoweredByDCIN()) {
-    // On TS80 we replace this symbol with the voltage we are operating on
+    // On non-DC inputs we replace this symbol with the voltage we are operating on
     // If <9V then show single digit, if not show dual small ones vertically stacked
-    uint8_t V = getInputVoltageX10(getSettingValue(SettingsOptions::VoltageDiv), 0);
+    uint16_t V = getInputVoltageX10(getSettingValue(SettingsOptions::VoltageDiv), 0);
     if (V % 10 >= 5)
-      V = V / 10 + 1; // round up
+      V = (V / 10) + 1; // round up
     else
       V = V / 10;
-    if (V >= 10) {
+    if (V > 9) {
       int16_t xPos = OLED::getCursorX();
       OLED::printNumber(V / 10, 1, FontStyle::SMALL);
       OLED::setCursor(xPos, 8);
@@ -758,8 +758,16 @@ void showDebugMenu(void) {
       // Print device ID Numbers
       {
         uint64_t id = getDeviceID();
-        OLED::drawHex((uint32_t)(id >> 32), FontStyle::SMALL);
-        OLED::drawHex((uint32_t)(id & 0xFFFFFFFF), FontStyle::SMALL);
+#ifdef DEVICE_HAS_VALIDATION_CODE
+        // If device has validation code; then we want to take over both lines of the screen
+        OLED::clearScreen();   // Ensure the buffer starts clean
+        OLED::setCursor(0, 0); // Position the cursor at the 0,0 (top left)
+        OLED::print(DebugMenu[screen], FontStyle::SMALL);
+        OLED::drawHex(getDeviceValidation(), FontStyle::SMALL, 8);
+        OLED::setCursor(0, 8); // second line
+#endif
+        OLED::drawHex((uint32_t)(id >> 32), FontStyle::SMALL, 8);
+        OLED::drawHex((uint32_t)(id & 0xFFFFFFFF), FontStyle::SMALL, 8);
       }
       break;
     case 10:
@@ -767,19 +775,26 @@ void showDebugMenu(void) {
       OLED::printNumber(TipThermoModel::getTipMaxInC(), 3, FontStyle::SMALL);
       break;
     case 11:
+      // Tip resistance
+      OLED::printNumber(getTipResistanceX10() / 10, 4, FontStyle::SMALL); // large to pad over so that we cover ID left overs
+      OLED::print(SymbolDot, FontStyle::SMALL);
+      OLED::printNumber(getTipResistanceX10() % 10, 1, FontStyle::SMALL);
+      break;
+    case 12:
       // High water mark for GUI
       OLED::printNumber(uxTaskGetStackHighWaterMark(GUITaskHandle), 5, FontStyle::SMALL);
       break;
-    case 12:
+    case 13:
       // High water mark for the Movement task
       OLED::printNumber(uxTaskGetStackHighWaterMark(MOVTaskHandle), 5, FontStyle::SMALL);
       break;
-    case 13:
+    case 14:
       // High water mark for the PID task
       OLED::printNumber(uxTaskGetStackHighWaterMark(PIDTaskHandle), 5, FontStyle::SMALL);
       break;
+      break;
 #ifdef HALL_SENSOR
-    case 14:
+    case 15:
       // Print raw hall effect value if availabe, none if hall effect disabled.
       {
         int16_t hallEffectStrength = getRawHallEffect();
@@ -801,9 +816,9 @@ void showDebugMenu(void) {
     else if (b == BUTTON_F_SHORT) {
       screen++;
 #ifdef HALL_SENSOR
-      screen = screen % 15;
+      screen = screen % 16;
 #else
-      screen = screen % 14;
+      screen = screen % 15;
 #endif
     }
     GUIDelay();
@@ -906,6 +921,12 @@ void showWarnings() {
   if (settingsWereReset) {
     warnUser(translatedString(Tr->SettingsResetMessage), 10 * TICKS_SECOND);
   }
+#ifdef DEVICE_HAS_VALIDATION_SUPPORT
+  if (getDeviceValidationStatus()) {
+    // Warn user this device might be counterfeit
+    warnUser(translatedString(Tr->DeviceFailedValidationWarning), 10 * TICKS_SECOND);
+  }
+#endif
 #ifndef NO_WARN_MISSING
   // We also want to alert if accel or pd is not detected / not responding
   // In this case though, we dont want to nag the user _too_ much
@@ -951,6 +972,7 @@ void startGUITask(void const *argument) {
   bool    tempOnDisplay          = false;
   bool    tipDisconnectedDisplay = false;
   bool    showExitMenuTransition = false;
+
   {
     // Generate the flipped screen into ram for later use
     // flipped is generated by flipping each row
@@ -962,7 +984,9 @@ void startGUITask(void const *argument) {
       }
     }
   }
+
   getTipRawTemp(1); // reset filter
+
   OLED::setRotation(getSettingValue(SettingsOptions::OrientationMode) & 1);
   // If the front button is held down, on supported devices, show PD debugging metrics
 #if POW_PD
@@ -973,10 +997,8 @@ void startGUITask(void const *argument) {
 #endif
 #endif
   // If the boot logo is enabled (but it times out) and the autostart mode is enabled (but not set to sleep w/o heat), start heating during boot logo
-  if (getSettingValue(SettingsOptions::LOGOTime) > 0 &&
-      getSettingValue(SettingsOptions::LOGOTime) < 5 &&
-      getSettingValue(SettingsOptions::AutoStartMode) > 0 &&
-      getSettingValue(SettingsOptions::AutoStartMode) < 3) {
+  if (getSettingValue(SettingsOptions::LOGOTime) > 0 && getSettingValue(SettingsOptions::LOGOTime) < 5 && getSettingValue(SettingsOptions::AutoStartMode) > 0
+      && getSettingValue(SettingsOptions::AutoStartMode) < 3) {
     uint16_t sleepTempDegC;
     if (getSettingValue(SettingsOptions::TemperatureInF)) {
       sleepTempDegC = TipThermoModel::convertFtoC(getSettingValue(SettingsOptions::SleepTemp));
@@ -987,11 +1009,9 @@ void startGUITask(void const *argument) {
     currentTempTargetDegC = min(sleepTempDegC, 75);
   }
 
-
   BootLogo::handleShowingLogo((uint8_t *)FLASH_LOGOADDR);
 
   showWarnings();
-
   if (getSettingValue(SettingsOptions::AutoStartMode)) {
     // jump directly to the autostart mode
     gui_solderingMode(getSettingValue(SettingsOptions::AutoStartMode) - 1);
diff --git a/source/Core/Threads/PIDThread.cpp b/source/Core/Threads/PIDThread.cpp
index 4b3c9704..9423e57a 100644
--- a/source/Core/Threads/PIDThread.cpp
+++ b/source/Core/Threads/PIDThread.cpp
@@ -14,6 +14,7 @@
 #include "main.hpp"
 #include "power.hpp"
 #include "task.h"
+
 static TickType_t powerPulseWaitUnit      = 25 * TICKS_100MS;      // 2.5 s
 static TickType_t powerPulseDurationUnit  = (5 * TICKS_100MS) / 2; // 250 ms
 TaskHandle_t      pidTaskNotification     = NULL;
@@ -45,7 +46,8 @@ void startPIDTask(void const *argument __unused) {
     getInputVoltageX10(getSettingValue(SettingsOptions::VoltageDiv), 1);
   }
 
-  while (preStartChecks() != 0) {
+  while (preStartChecks() == 0) {
+    resetWatchdog();
     ulTaskNotifyTake(pdTRUE, 2000);
   }
 
@@ -141,7 +143,7 @@ int32_t getPIDResultX10Watts(int32_t setpointDelta) {
   // TIM3->CTR1 is configured with a duty cycle of 50% so, in real, we get only 50% of the presumed power output
   // so we basically double the need (gain = 2) to get what we want.
   return powerStore.update(TIP_THERMAL_MASS * setpointDelta, // the required power
-                           TIP_THERMAL_MASS,                 // Inertia, smaller numbers increase dominance of the previous value
+                           getTipThermalMass(),              // Inertia, smaller numbers increase dominance of the previous value
                            2,                                // gain
                            rate,                             // PID cycle frequency
                            getX10WattageLimits());
diff --git a/source/Core/Threads/POWThread.cpp b/source/Core/Threads/POWThread.cpp
index d604742d..079507a1 100644
--- a/source/Core/Threads/POWThread.cpp
+++ b/source/Core/Threads/POWThread.cpp
@@ -21,9 +21,11 @@
 void startPOWTask(void const *argument __unused) {
   // Init any other misc sensors
   postRToSInit();
+  while (preStartChecksDone() == 0) {
+    osDelay(3);
+  }
   // You have to run this once we are willing to answer PD messages
   // Setting up too early can mean that we miss the ~20ms window to respond on some chargers
-
 #if POW_PD
   USBPowerDelivery::start();
   // Crank the handle at boot until we are stable and waiting for IRQ
@@ -41,16 +43,16 @@ void startPOWTask(void const *argument __unused) {
      * Then we would sleep as nothing to do, but 100ms> 20ms power supply typical timeout
      */
     if (!getFUS302IRQLow()) {
-      res = xTaskNotifyWait(0x0, 0xFFFFFF, NULL, TICKS_100MS);
+      res = xTaskNotifyWait(0x0, 0xFFFFFF, NULL, TICKS_100MS / 2);
     }
 
 #if POW_PD
-
     if (res != pdFALSE || getFUS302IRQLow()) {
       USBPowerDelivery::IRQOccured();
     }
-    USBPowerDelivery::step();
     USBPowerDelivery::PPSTimerCallback();
+    USBPowerDelivery::step();
+
 #else
     (void)res;
 #endif
diff --git a/source/Makefile b/source/Makefile
index 0d7a78a4..8aec2e7d 100644
--- a/source/Makefile
+++ b/source/Makefile
@@ -3,9 +3,10 @@ model:=Pinecil
 endif
 
 ALL_MINIWARE_MODELS=TS100 TS80 TS80P
-ALL_PINE_MODELS=Pinecil
+ALL_PINECIL_MODELS=Pinecil
+ALL_PINECIL_V2_MODELS=Pinecilv2
 ALL_MHP30_MODELS=MHP30
-ALL_MODELS=$(ALL_MINIWARE_MODELS) $(ALL_PINE_MODELS) $(ALL_MHP30_MODELS)
+ALL_MODELS=$(ALL_MINIWARE_MODELS) $(ALL_PINECIL_MODELS) $(ALL_MHP30_MODELS) $(ALL_PINECIL_V2_MODELS)
 ifneq ($(model),$(filter $(model),$(ALL_MODELS)))
 $(error Invalid model '$(model)', valid options are: $(ALL_MODELS))
 endif
@@ -64,11 +65,58 @@ MHP30_STARTUP_DIR = ./Startup
 MHP30_INC_DIR = ./Core/BSP/MHP30
 MHP30_LD_FILE = ./Core/BSP/MHP30/stm32f103.ld
 
-PINE_INC_DIR = ./Core/BSP/Pine64
-PINE_VENDOR_INC_DIR = ./Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include
-PINE_VENDOR_USB_INC_DIR = ./Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb
-PINE_NMSIS_INC_DIR = ./Core/BSP/Pine64/Vendor/NMSIS/Core/Include
-PINE_FREERTOS_PORT_INC_DIR = ./Core/BSP/Pine64/Vendor/OS/FreeRTOS/Source/portable/GCC
+PINE_INC_DIR = ./Core/BSP/Pinecil
+PINE_VENDOR_INC_DIR = ./Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include
+PINE_VENDOR_USB_INC_DIR = ./Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb
+PINE_NMSIS_INC_DIR = ./Core/BSP/Pinecil/Vendor/NMSIS/Core/Include
+PINE_FREERTOS_PORT_INC_DIR = ./Core/BSP/Pinecil/Vendor/OS/FreeRTOS/Source/portable/GCC
+
+PINECILV2_DIR = ./Core/BSP/Pinecilv2
+PINECILV2_SDK_DIR = $(PINECILV2_DIR)/bl_mcu_sdk
+
+PINECILV2_VENDOR_BSP_DIR = $(PINECILV2_SDK_DIR)/bsp
+PINECILV2_VENDOR_BSP_COMMON_DIR = $(PINECILV2_VENDOR_BSP_DIR)/bsp_common
+PINECILV2_VENDOR_BSP_BOARD_DIR = $(PINECILV2_VENDOR_BSP_DIR)/board
+PINECILV2_VENDOR_BSP_PLATFORM_DIR = $(PINECILV2_VENDOR_BSP_COMMON_DIR)/platform
+PINECILV2_VENDOR_BSP_USB_DIR = $(PINECILV2_VENDOR_BSP_COMMON_DIR)/usb
+
+
+PINECILV2_COMMON_DIR = $(PINECILV2_SDK_DIR)/common
+PINECILV2_COMMON_BL_MATH_DIR = $(PINECILV2_COMMON_DIR)/bl_math
+PINECILV2_COMMON_DEVICE_DIR = $(PINECILV2_COMMON_DIR)/device
+PINECILV2_COMMON_LIST_DIR = $(PINECILV2_COMMON_DIR)/list
+PINECILV2_COMMON_MISC_DIR = $(PINECILV2_COMMON_DIR)/misc
+PINECILV2_COMMON_PARTITION_DIR = $(PINECILV2_COMMON_DIR)/partition
+PINECILV2_COMMON_PID_DIR = $(PINECILV2_COMMON_DIR)/pid
+PINECILV2_COMMON_RING_BUFFERDIR = $(PINECILV2_COMMON_DIR)/ring_buffer
+PINECILV2_COMMON_SOFT_CRC_DIR = $(PINECILV2_COMMON_DIR)/soft_crc
+PINECILV2_COMMON_TIMESTAMP_DIR = $(PINECILV2_COMMON_DIR)/timestamp
+PINECILV2_COMPONENTS_DIR = $(PINECILV2_SDK_DIR)/components
+
+
+PINECILV2_COMPONENTS_FREERTOS_DIR = $(PINECILV2_COMPONENTS_DIR)/freertos
+PINECILV2_COMPONENTS_FREERTOS_BL602_DIR = $(PINECILV2_COMPONENTS_FREERTOS_DIR)/portable/gcc/risc-v/bl702
+
+
+PINECILV2_COMPONENTS_NMSIS_DIR = $(PINECILV2_COMPONENTS_DIR)/nmsis
+PINECILV2_COMPONENTS_NMSIS_CORE_INC_DIR = $(PINECILV2_COMPONENTS_NMSIS_DIR)/core/inc
+
+PINECILV2_COMPONENTS_USB_STACK_DIR = $(PINECILV2_COMPONENTS_DIR)/usb_stack
+PINECILV2_COMPONENTS_USB_STACK_COMMON_DIR = $(PINECILV2_COMPONENTS_USB_STACK_DIR)/common
+PINECILV2_COMPONENTS_USB_STACK_CORE_DIR = $(PINECILV2_COMPONENTS_USB_STACK_DIR)/core
+PINECILV2_COMPONENTS_USB_STACK_CDC_DIR = $(PINECILV2_COMPONENTS_USB_STACK_DIR)/class/cdc
+PINECILV2_COMPONENTS_USB_STACK_WINUSB_DIR = $(PINECILV2_COMPONENTS_USB_STACK_DIR)/class/winusb
+
+PINECILV2_DRIVERS_DIR = $(PINECILV2_SDK_DIR)/drivers/bl702_driver
+PINECILV2_DRIVERS_HAL_DRV_INC_DIR = $(PINECILV2_DRIVERS_DIR)/hal_drv/inc
+PINECILV2_DRIVERS_HAL_DRV_DEF_DIR = $(PINECILV2_DRIVERS_DIR)/hal_drv/default_config
+PINECILV2_DRIVERS_REGS_DIR = $(PINECILV2_DRIVERS_DIR)/regs
+PINECILV2_DRIVERS_RISCV_DIR = $(PINECILV2_DRIVERS_DIR)/risc-v
+PINECILV2_DRIVERS_STARTUP_DIR = $(PINECILV2_DRIVERS_DIR)/startup
+PINECILV2_DRIVERS_STD_DRV_DIR = $(PINECILV2_DRIVERS_DIR)/std_drv/inc
+
+
+
 
 SOURCE_MIDDLEWARES_DIR = ./Middlewares
 FRTOS_CMIS_INC_DIR = ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS
@@ -84,10 +132,12 @@ SOURCE_DRIVERS_DIR = ./Core/Drivers
 INC_PD_DRIVERS_DIR = ./Core/Drivers/usb-pd/include
 PD_DRIVER_TESTS_DIR = ./Core/Drivers/usb-pd/tests
 PD_DRIVER_DIR = ./Core/Drivers/usb-pd
-# Find-all's used for formatting
 
-ALL_INCLUDES = $(shell find ./Core -type d \( -path $(BRIEFLZ_INC_DIR) -o -path $(PD_DRIVER_DIR) \)  -prune -false -o \( -type f \( -name '*.h' -o -name '*.hpp' \) \) )
-ALL_SOURCE = $(shell find ./Core -type d  \( -path $(SOURCE_BRIEFLZ_DIR) -o -path $(PD_DRIVER_DIR) \) -prune -false -o \( -type f \( -name '*.c' -o -name '*.cpp' \) \) )
+
+# Find-all's used for formatting; have to exclude external modules
+
+ALL_INCLUDES = $(shell find ./Core -type d \( -path $(BRIEFLZ_INC_DIR) -o -path $(PD_DRIVER_DIR) -o -path $(PINECILV2_SDK_DIR) \)  -prune -false -o \( -type f \( -name '*.h' -o -name '*.hpp' \) \) )
+ALL_SOURCE = $(shell find ./Core -type d  \( -path $(SOURCE_BRIEFLZ_DIR) -o -path $(PD_DRIVER_DIR) -o -path $(PINECILV2_SDK_DIR)  \) -prune -false -o \( -type f \( -name '*.c' -o -name '*.cpp' \) \) )
 
 # Device dependent settings
 ifeq ($(model),$(filter $(model),$(ALL_MINIWARE_MODELS)))
@@ -105,11 +155,11 @@ DEV_GLOBAL_DEFS= -D STM32F103T8Ux -D STM32F1 -D STM32 -D USE_HAL_DRIVER -D STM32
 		-D STM32F10X_MD 
 DEV_LDFLAGS= 
 DEV_AFLAGS=
-DEV_CFLAGS= 
+DEV_CFLAGS=  -D VECT_TAB_OFFSET=$(bootldr_size)U
 DEV_CXXFLAGS= 
 CPUFLAGS= -mcpu=cortex-m3     \
-		  -mthumb 			\
-		  -mfloat-abi=soft
+		-mthumb 			\
+		-mfloat-abi=soft
 flash_size=64k
 bootldr_size=0x4000
 DEVICE_DFU_ADDRESS=0x08004000
@@ -131,11 +181,11 @@ DEV_GLOBAL_DEFS= -D STM32F103T8Ux -D STM32F1 -D STM32 -D USE_HAL_DRIVER -D STM32
 		-D STM32F10X_MD 
 DEV_LDFLAGS= 
 DEV_AFLAGS=
-DEV_CFLAGS= 
+DEV_CFLAGS=  -D VECT_TAB_OFFSET=$(bootldr_size)U
 DEV_CXXFLAGS= 
 CPUFLAGS= -mcpu=cortex-m3     \
-		  -mthumb 			\
-		  -mfloat-abi=soft
+		-mthumb 			\
+		-mfloat-abi=soft
 flash_size=128k
 bootldr_size=32k
 DEVICE_DFU_ADDRESS=0x08008000
@@ -143,18 +193,18 @@ DEVICE_DFU_VID_PID=0x1209:0xDB42
 endif
 
 
-ifeq ($(model),$(ALL_PINE_MODELS))
-$(info Building for Pine64 )
+ifeq ($(model),$(ALL_PINECIL_MODELS))
+$(info Building for Pine64 Pinecilv1)
 DEVICE_INCLUDES = -I$(PINE_INC_DIR) \
 -I$(PINE_VENDOR_INC_DIR) \
 -I$(PINE_VENDOR_USB_INC_DIR) \
 -I$(PINE_NMSIS_INC_DIR) \
 -I$(PINE_FREERTOS_PORT_INC_DIR) 
 	
-DEVICE_BSP_DIR = ./Core/BSP/Pine64
+DEVICE_BSP_DIR = ./Core/BSP/Pinecil
 S_SRCS := $(shell find $(PINE_INC_DIR) -type f -name '*.S') $(info $(S_SRCS) )
 ASM_INC = -I$(PINE_RISCV_INC_DIR)
-LDSCRIPT=./Core/BSP/Pine64/Vendor/SoC/gd32vf103/Board/pinecil/Source/GCC/gcc_gd32vf103_flashxip.ld
+LDSCRIPT=./Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Board/pinecil/Source/GCC/gcc_gd32vf103_flashxip.ld
 flash_size=128k
 bootldr_size=0x0
 # Flags
@@ -164,10 +214,74 @@ CPUFLAGS= -march=rv32imac \
 DEV_LDFLAGS=-nostartfiles 
 DEV_AFLAGS=  
 DEV_GLOBAL_DEFS= -DRTOS_FREERTOS -DDOWNLOAD_MODE=DOWNLOAD_MODE_FLASHXIP
-DEV_CFLAGS=
+DEV_CFLAGS= -D VECT_TAB_OFFSET=$(bootldr_size)U
 DEV_CXXFLAGS=
 endif
 
+
+
+
+ifeq ($(model),$(ALL_PINECIL_V2_MODELS))
+$(info Building for Pine64 Pinecilv2 )
+
+
+
+DEVICE_INCLUDES = -I$(PINECILV2_DIR) \
+	-I$(PINECILV2_SDK_DIR) \
+	-I$(PINECILV2_VENDOR_BSP_COMMON_DIR) \
+	-I$(PINECILV2_VENDOR_BSP_PLATFORM_DIR) \
+	-I$(PINECILV2_COMMON_DIR) \
+	-I$(PINECILV2_COMMON_BL_MATH_DIR) \
+	-I$(PINECILV2_COMMON_DEVICE_DIR) \
+	-I$(PINECILV2_COMMON_LIST_DIR) \
+	-I$(PINECILV2_COMMON_MISC_DIR) \
+	-I$(PINECILV2_COMMON_PARTITION_DIR) \
+	-I$(PINECILV2_COMMON_PID_DIR) \
+	-I$(PINECILV2_COMMON_RING_BUFFERDIR) \
+	-I$(PINECILV2_COMMON_SOFT_CRC_DIR) \
+	-I$(PINECILV2_COMMON_TIMESTAMP_DIR) \
+	-I$(PINECILV2_COMPONENTS_DIR) \
+	-I$(PINECILV2_COMPONENTS_FREERTOS_DIR) \
+	-I$(PINECILV2_COMPONENTS_FREERTOS_BL602_DIR) \
+	-I$(PINECILV2_COMPONENTS_NMSIS_DIR) \
+	-I$(PINECILV2_COMPONENTS_USB_STACK_DIR) \
+	-I$(PINECILV2_DRIVERS_DIR) \
+	-I$(PINECILV2_DRIVERS_HAL_DRV_INC_DIR) \
+	-I$(PINECILV2_DRIVERS_HAL_DRV_DEF_DIR) \
+	-I$(PINECILV2_DRIVERS_REGS_DIR) \
+	-I$(PINECILV2_DRIVERS_RISCV_DIR) \
+	-I$(PINECILV2_DRIVERS_STARTUP_DIR) \
+	-I$(PINECILV2_DRIVERS_STD_DRV_DIR) \
+	-I$(PINECILV2_VENDOR_BSP_PLATFORM_DIR) \
+	-I$(PINECILV2_VENDOR_BSP_USB_DIR) \
+	-I$(PINECILV2_COMPONENTS_USB_STACK_COMMON_DIR) \
+	-I$(PINECILV2_COMPONENTS_USB_STACK_CORE_DIR) \
+	-I$(PINECILV2_COMPONENTS_USB_STACK_CDC_DIR) \
+	-I$(PINECILV2_COMPONENTS_USB_STACK_WINUSB_DIR) \
+	-I$(PINECILV2_COMPONENTS_NMSIS_CORE_INC_DIR) 
+
+DEVICE_BSP_DIR = ./Core/BSP/Pinecilv2
+S_SRCS := $(shell find $(PINECILV2_DIR) -type d  \(  -path $(PINECILV2_VENDOR_BSP_COMMON_DIR) \) -prune -false -o  -type f -name '*.S') $(info $(S_SRCS) )
+ASM_INC = $(DEVICE_INCLUDES)
+LDSCRIPT=./Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/bl702_flash.ld
+
+# Flags
+CPUFLAGS= -march=rv32imafc \
+			-mabi=ilp32f \
+			-mcmodel=medany -fsigned-char -fno-builtin -nostartfiles \
+			-DportasmHANDLE_INTERRUPT=FreeRTOS_Interrupt_Handler -DARCH_RISCV -D__RISCV_FEATURE_MVE=0 -DportUSING_MPU_WRAPPERS=0
+# -DBFLB_USE_ROM_DRIVER=1
+DEV_LDFLAGS=-nostartfiles  -DDEBUG
+DEV_AFLAGS=  
+DEV_GLOBAL_DEFS= 
+#Required to be turned off due to their drivers tripping warnings
+DEV_CFLAGS= -Wno-error=enum-conversion -Wno-type-limits -Wno-implicit-fallthrough
+DEV_CXXFLAGS= $(DEV_CFLAGS)
+flash_size=128k
+bootldr_size=0x0
+
+endif
+
 INCLUDES = -I$(APP_INC_DIR)	\
 	-I$(BRIEFLZ_INC_DIR) \
 	-I$(FRTOS_CMIS_INC_DIR)	\
@@ -176,19 +290,26 @@ INCLUDES = -I$(APP_INC_DIR)	\
 	-I$(BSP_INC_DIR) \
 	-I$(THREADS_INC_DIR) \
 	-I$(INC_PD_DRIVERS_DIR) \
-	  $(DEVICE_INCLUDES) 
+	$(DEVICE_INCLUDES) 
+
+EXCLUDED_DIRS := -path  $(PINECILV2_VENDOR_BSP_ES8388_DIR) \
+-o -path  $(PINECILV2_VENDOR_BSP_IMAGE_SENSOR_DIR) \
+-o -path  $(PINECILV2_VENDOR_BSP_LVGL_DIR) \
+-o -path  $(PINECILV2_VENDOR_BSP_MCU_LCD_DIR) \
+-o -path  $(PINECILV2_VENDOR_BSP_BOARD_DIR) \
+-o -path $(PINECILV2_VENDOR_BSP_USB_DIR) \
 
 SOURCE := $(shell find $(SOURCE_THREADS_DIR) -type f -name '*.c') \
 $(shell find $(SOURCE_CORE_DIR) -type f -name '*.c') \
 $(shell find $(SOURCE_DRIVERS_DIR) -type f -name '*.c') \
-$(shell find $(DEVICE_BSP_DIR) -type f -name '*.c') \
+$(shell find $(DEVICE_BSP_DIR) -type d  \( $(EXCLUDED_DIRS)  \) -prune -false -o -type f -name '*.c')\
 $(shell find $(SOURCE_MIDDLEWARES_DIR) -type f -name '*.c') \
 $(SOURCE_BRIEFLZ_DIR)/depack.c
 # We exclude the USB-PD stack tests $(PD_DRIVER_TESTS_DIR)
 SOURCE_CPP := $(shell find $(SOURCE_THREADS_DIR) -type f -name '*.cpp') \
 $(shell find $(SOURCE_CORE_DIR) -type f -name '*.cpp') \
 $(shell find $(SOURCE_DRIVERS_DIR) -path $(PD_DRIVER_TESTS_DIR) -prune -false -o -type f -name '*.cpp') \
-$(shell find $(DEVICE_BSP_DIR) -type f -name '*.cpp') \
+$(shell find $(DEVICE_BSP_DIR) -type d  \( $(EXCLUDED_DIRS) \) -prune -false -o -type f -name '*.cpp')  \
 $(shell find $(SOURCE_MIDDLEWARES_DIR) -type f -name '*.cpp')
 
 # code optimisation ------------------------------------------------------------
@@ -215,7 +336,7 @@ COMPILER=gcc
 ifeq ($(model),$(filter $(model),$(ALL_MINIWARE_MODELS) $(ALL_MHP30_MODELS)))
 COMPILER_PREFIX=arm-none-eabi
 endif
-ifeq ($(model),$(ALL_PINE_MODELS))
+ifeq ($(model),$(filter $(model),$(ALL_PINECIL_MODELS) $(ALL_PINECIL_V2_MODELS)))
 COMPILER_PREFIX=riscv-none-elf
 endif
 # programs ---------------------------------------------------------------------
@@ -223,7 +344,6 @@ CC=$(COMPILER_PREFIX)-gcc
 CPP=$(COMPILER_PREFIX)-g++
 OBJCOPY=$(COMPILER_PREFIX)-objcopy
 OBJDUMP=$(COMPILER_PREFIX)-objdump
-SIZE=$(COMPILER_PREFIX)-size
 # use gcc in assembler mode so we can use defines etc in assembly
 AS=$(COMPILER_PREFIX)-gcc -x assembler-with-cpp
 
@@ -236,7 +356,6 @@ LINKER_FLAGS=   -Wl,--gc-sections 		                      \
 			    -Wl,--defsym=__FLASH_SIZE__=$(flash_size)     \
 			    -Wl,--defsym=__BOOTLDR_SIZE__=$(bootldr_size) \
 				-Wl,--print-memory-usage 					  \
-				-flto 										  \
 				--specs=nosys.specs 						  \
 			    --specs=nano.specs						      \
 				$(DEV_LDFLAGS)
@@ -270,8 +389,8 @@ CHECKOPTIONS=		-Wall 				\
 			-Winline			\
 			-Wshadow			\
 			-Wno-unused-parameter \
-			-Wdouble-promotion \
-			-Werror 
+			-Wdouble-promotion 
+			
 			
 
 
@@ -349,7 +468,6 @@ firmware-%: $(HEXFILE_DIR)/$(model)_%.hex $(HEXFILE_DIR)/$(model)_%.bin $(HEXFIL
 	$(OBJCOPY) $< -O ihex $@
 
 %.bin : %.elf Makefile
-	$(SIZE)  --format=berkeley  $<
 	$(OBJCOPY) $< -O binary $@
 
 %.dfu : %.bin Makefile
diff --git a/source/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h b/source/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h
deleted file mode 100644
index 79a185b4..00000000
--- a/source/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
- * When the MPU is used the standard (non MPU) API functions are mapped to
- * equivalents that start "MPU_", the prototypes for which are defined in this
- * header files.  This will cause the application code to call the MPU_ version
- * which wraps the non-MPU version with privilege promoting then demoting code,
- * so the kernel code always runs will full privileges.
- */
-
-
-#ifndef MPU_PROTOTYPES_H
-#define MPU_PROTOTYPES_H
-
-/* MPU versions of tasks.h API functions. */
-BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;
-TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) FREERTOS_SYSTEM_CALL;
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
-uint32_t MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-uint32_t MPU_ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) FREERTOS_SYSTEM_CALL;
-
-/* MPU versions of queue.h API functions. */
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) FREERTOS_SYSTEM_CALL;
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
-QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;
-void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-
-/* MPU versions of timers.h API functions. */
-TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL;
-TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) FREERTOS_SYSTEM_CALL;
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-
-/* MPU versions of event_group.h API functions. */
-EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL;
-EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup ) FREERTOS_SYSTEM_CALL;
-
-/* MPU versions of message/stream_buffer.h API functions. */
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
-StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL;
-StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL;
-
-
-
-#endif /* MPU_PROTOTYPES_H */
-
diff --git a/source/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h b/source/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h
deleted file mode 100644
index 87a2f2c3..00000000
--- a/source/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef MPU_WRAPPERS_H
-#define MPU_WRAPPERS_H
-
-/* This file redefines API functions to be called through a wrapper macro, but
-only for ports that are using the MPU. */
-#ifdef portUSING_MPU_WRAPPERS
-
-	/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
-	included from queue.c or task.c to prevent it from having an effect within
-	those files. */
-	#ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-		/*
-		 * Map standard (non MPU) API functions to equivalents that start
-		 * "MPU_".  This will cause the application code to call the MPU_
-		 * version, which wraps the non-MPU version with privilege promoting
-		 * then demoting code, so the kernel code always runs will full
-		 * privileges.
-		 */
-
-		/* Map standard tasks.h API functions to the MPU equivalents. */
-		#define xTaskCreate								MPU_xTaskCreate
-		#define xTaskCreateStatic						MPU_xTaskCreateStatic
-		#define xTaskCreateRestricted					MPU_xTaskCreateRestricted
-		#define vTaskAllocateMPURegions					MPU_vTaskAllocateMPURegions
-		#define vTaskDelete								MPU_vTaskDelete
-		#define vTaskDelay								MPU_vTaskDelay
-		#define vTaskDelayUntil							MPU_vTaskDelayUntil
-		#define xTaskAbortDelay							MPU_xTaskAbortDelay
-		#define uxTaskPriorityGet						MPU_uxTaskPriorityGet
-		#define eTaskGetState							MPU_eTaskGetState
-		#define vTaskGetInfo							MPU_vTaskGetInfo
-		#define vTaskPrioritySet						MPU_vTaskPrioritySet
-		#define vTaskSuspend							MPU_vTaskSuspend
-		#define vTaskResume								MPU_vTaskResume
-		#define vTaskSuspendAll							MPU_vTaskSuspendAll
-		#define xTaskResumeAll							MPU_xTaskResumeAll
-		#define xTaskGetTickCount						MPU_xTaskGetTickCount
-		#define uxTaskGetNumberOfTasks					MPU_uxTaskGetNumberOfTasks
-		#define pcTaskGetName							MPU_pcTaskGetName
-		#define xTaskGetHandle							MPU_xTaskGetHandle
-		#define uxTaskGetStackHighWaterMark				MPU_uxTaskGetStackHighWaterMark
-		#define uxTaskGetStackHighWaterMark2			MPU_uxTaskGetStackHighWaterMark2
-		#define vTaskSetApplicationTaskTag				MPU_vTaskSetApplicationTaskTag
-		#define xTaskGetApplicationTaskTag				MPU_xTaskGetApplicationTaskTag
-		#define vTaskSetThreadLocalStoragePointer		MPU_vTaskSetThreadLocalStoragePointer
-		#define pvTaskGetThreadLocalStoragePointer		MPU_pvTaskGetThreadLocalStoragePointer
-		#define xTaskCallApplicationTaskHook			MPU_xTaskCallApplicationTaskHook
-		#define xTaskGetIdleTaskHandle					MPU_xTaskGetIdleTaskHandle
-		#define uxTaskGetSystemState					MPU_uxTaskGetSystemState
-		#define vTaskList								MPU_vTaskList
-		#define vTaskGetRunTimeStats					MPU_vTaskGetRunTimeStats
-		#define ulTaskGetIdleRunTimeCounter				MPU_ulTaskGetIdleRunTimeCounter
-		#define xTaskGenericNotify						MPU_xTaskGenericNotify
-		#define xTaskNotifyWait							MPU_xTaskNotifyWait
-		#define ulTaskNotifyTake						MPU_ulTaskNotifyTake
-		#define xTaskNotifyStateClear					MPU_xTaskNotifyStateClear
-		#define ulTaskNotifyValueClear					MPU_ulTaskNotifyValueClear
-		#define xTaskCatchUpTicks						MPU_xTaskCatchUpTicks
-
-		#define xTaskGetCurrentTaskHandle				MPU_xTaskGetCurrentTaskHandle
-		#define vTaskSetTimeOutState					MPU_vTaskSetTimeOutState
-		#define xTaskCheckForTimeOut					MPU_xTaskCheckForTimeOut
-		#define xTaskGetSchedulerState					MPU_xTaskGetSchedulerState
-
-		/* Map standard queue.h API functions to the MPU equivalents. */
-		#define xQueueGenericSend						MPU_xQueueGenericSend
-		#define xQueueReceive							MPU_xQueueReceive
-		#define xQueuePeek								MPU_xQueuePeek
-		#define xQueueSemaphoreTake						MPU_xQueueSemaphoreTake
-		#define uxQueueMessagesWaiting					MPU_uxQueueMessagesWaiting
-		#define uxQueueSpacesAvailable					MPU_uxQueueSpacesAvailable
-		#define vQueueDelete							MPU_vQueueDelete
-		#define xQueueCreateMutex						MPU_xQueueCreateMutex
-		#define xQueueCreateMutexStatic					MPU_xQueueCreateMutexStatic
-		#define xQueueCreateCountingSemaphore			MPU_xQueueCreateCountingSemaphore
-		#define xQueueCreateCountingSemaphoreStatic		MPU_xQueueCreateCountingSemaphoreStatic
-		#define xQueueGetMutexHolder					MPU_xQueueGetMutexHolder
-		#define xQueueTakeMutexRecursive				MPU_xQueueTakeMutexRecursive
-		#define xQueueGiveMutexRecursive				MPU_xQueueGiveMutexRecursive
-		#define xQueueGenericCreate						MPU_xQueueGenericCreate
-		#define xQueueGenericCreateStatic				MPU_xQueueGenericCreateStatic
-		#define xQueueCreateSet							MPU_xQueueCreateSet
-		#define xQueueAddToSet							MPU_xQueueAddToSet
-		#define xQueueRemoveFromSet						MPU_xQueueRemoveFromSet
-		#define xQueueSelectFromSet						MPU_xQueueSelectFromSet
-		#define xQueueGenericReset						MPU_xQueueGenericReset
-
-		#if( configQUEUE_REGISTRY_SIZE > 0 )
-			#define vQueueAddToRegistry						MPU_vQueueAddToRegistry
-			#define vQueueUnregisterQueue					MPU_vQueueUnregisterQueue
-			#define pcQueueGetName							MPU_pcQueueGetName
-		#endif
-
-		/* Map standard timer.h API functions to the MPU equivalents. */
-		#define xTimerCreate							MPU_xTimerCreate
-		#define xTimerCreateStatic						MPU_xTimerCreateStatic
-		#define pvTimerGetTimerID						MPU_pvTimerGetTimerID
-		#define vTimerSetTimerID						MPU_vTimerSetTimerID
-		#define xTimerIsTimerActive						MPU_xTimerIsTimerActive
-		#define xTimerGetTimerDaemonTaskHandle			MPU_xTimerGetTimerDaemonTaskHandle
-		#define xTimerPendFunctionCall					MPU_xTimerPendFunctionCall
-		#define pcTimerGetName							MPU_pcTimerGetName
-		#define vTimerSetReloadMode						MPU_vTimerSetReloadMode
-		#define uxTimerGetReloadMode					MPU_uxTimerGetReloadMode
-		#define xTimerGetPeriod							MPU_xTimerGetPeriod
-		#define xTimerGetExpiryTime						MPU_xTimerGetExpiryTime
-		#define xTimerGenericCommand					MPU_xTimerGenericCommand
-
-		/* Map standard event_group.h API functions to the MPU equivalents. */
-		#define xEventGroupCreate						MPU_xEventGroupCreate
-		#define xEventGroupCreateStatic					MPU_xEventGroupCreateStatic
-		#define xEventGroupWaitBits						MPU_xEventGroupWaitBits
-		#define xEventGroupClearBits					MPU_xEventGroupClearBits
-		#define xEventGroupSetBits						MPU_xEventGroupSetBits
-		#define xEventGroupSync							MPU_xEventGroupSync
-		#define vEventGroupDelete						MPU_vEventGroupDelete
-
-		/* Map standard message/stream_buffer.h API functions to the MPU
-		equivalents. */
-		#define xStreamBufferSend						MPU_xStreamBufferSend
-		#define xStreamBufferReceive					MPU_xStreamBufferReceive
-		#define xStreamBufferNextMessageLengthBytes		MPU_xStreamBufferNextMessageLengthBytes
-		#define vStreamBufferDelete						MPU_vStreamBufferDelete
-		#define xStreamBufferIsFull						MPU_xStreamBufferIsFull
-		#define xStreamBufferIsEmpty					MPU_xStreamBufferIsEmpty
-		#define xStreamBufferReset						MPU_xStreamBufferReset
-		#define xStreamBufferSpacesAvailable			MPU_xStreamBufferSpacesAvailable
-		#define xStreamBufferBytesAvailable				MPU_xStreamBufferBytesAvailable
-		#define xStreamBufferSetTriggerLevel			MPU_xStreamBufferSetTriggerLevel
-		#define xStreamBufferGenericCreate				MPU_xStreamBufferGenericCreate
-		#define xStreamBufferGenericCreateStatic		MPU_xStreamBufferGenericCreateStatic
-
-
-		/* Remove the privileged function macro, but keep the PRIVILEGED_DATA
-		macro so applications can place data in privileged access sections
-		(useful when using statically allocated objects). */
-		#define PRIVILEGED_FUNCTION
-		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
-		#define FREERTOS_SYSTEM_CALL
-
-	#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
-
-		/* Ensure API functions go in the privileged execution section. */
-		#define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))
-		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
-		#define FREERTOS_SYSTEM_CALL __attribute__((section( "freertos_system_calls")))
-
-	#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
-
-#else /* portUSING_MPU_WRAPPERS */
-
-	#define PRIVILEGED_FUNCTION
-	#define PRIVILEGED_DATA
-	#define FREERTOS_SYSTEM_CALL
-	#define portUSING_MPU_WRAPPERS 0
-
-#endif /* portUSING_MPU_WRAPPERS */
-
-
-#endif /* MPU_WRAPPERS_H */
-
diff --git a/source/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h b/source/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h
index ac644e45..d5b449a4 100644
--- a/source/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h
+++ b/source/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h
@@ -92,11 +92,14 @@ must be set in the compiler's include path. */
 #endif
 
 #ifdef __cplusplus
-extern "C"
-{
+extern "C" {
 #endif
 
-#include "mpu_wrappers.h"
+#define PRIVILEGED_FUNCTION
+#define PRIVILEGED_DATA
+#define FREERTOS_SYSTEM_CALL
+#define portUSING_MPU_WRAPPERS 0
+// #include "mpu_wrappers.h"
 
 /*
  * Setup the stack of a new task so it is ready to be placed under the
@@ -106,9 +109,9 @@ extern "C"
  */
 #if (portUSING_MPU_WRAPPERS == 1)
 #if (portHAS_STACK_OVERFLOW_CHECKING == 1)
-	StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged) PRIVILEGED_FUNCTION;
+StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged) PRIVILEGED_FUNCTION;
 #else
-	StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged) PRIVILEGED_FUNCTION;
+StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged) PRIVILEGED_FUNCTION;
 #endif
 #else
 #if (portHAS_STACK_OVERFLOW_CHECKING == 1)
@@ -118,27 +121,25 @@ StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxC
 #endif
 #endif
 
-	/* Used by heap_5.c to define the start address and size of each memory region
+/* Used by heap_5.c to define the start address and size of each memory region
 that together comprise the total FreeRTOS heap space. */
-	typedef struct HeapRegion
-	{
-		uint8_t *pucStartAddress;
-		size_t xSizeInBytes;
-	} HeapRegion_t;
+typedef struct HeapRegion {
+  uint8_t *pucStartAddress;
+  size_t   xSizeInBytes;
+} HeapRegion_t;
 
-	/* Used to pass information about the heap out of vPortGetHeapStats(). */
-	typedef struct xHeapStats
-	{
-		size_t xAvailableHeapSpaceInBytes;		/* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */
-		size_t xSizeOfLargestFreeBlockInBytes;	/* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
-		size_t xSizeOfSmallestFreeBlockInBytes; /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
-		size_t xNumberOfFreeBlocks;				/* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */
-		size_t xMinimumEverFreeBytesRemaining;	/* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */
-		size_t xNumberOfSuccessfulAllocations;	/* The number of calls to pvPortMalloc() that have returned a valid memory block. */
-		size_t xNumberOfSuccessfulFrees;		/* The number of calls to vPortFree() that has successfully freed a block of memory. */
-	} HeapStats_t;
+/* Used to pass information about the heap out of vPortGetHeapStats(). */
+typedef struct xHeapStats {
+  size_t xAvailableHeapSpaceInBytes;      /* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */
+  size_t xSizeOfLargestFreeBlockInBytes;  /* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
+  size_t xSizeOfSmallestFreeBlockInBytes; /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
+  size_t xNumberOfFreeBlocks;             /* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */
+  size_t xMinimumEverFreeBytesRemaining;  /* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */
+  size_t xNumberOfSuccessfulAllocations;  /* The number of calls to pvPortMalloc() that have returned a valid memory block. */
+  size_t xNumberOfSuccessfulFrees;        /* The number of calls to vPortFree() that has successfully freed a block of memory. */
+} HeapStats_t;
 
-	/*
+/*
  * Used to define multiple heap regions for use by heap_5.c.  This function
  * must be called before any calls to pvPortMalloc() - not creating a task,
  * queue, semaphore, mutex, software timer, event group, etc. will result in
@@ -149,35 +150,35 @@ that together comprise the total FreeRTOS heap space. */
  * terminated by a HeapRegions_t structure that has a size of 0.  The region
  * with the lowest start address must appear first in the array.
  */
-	void vPortDefineHeapRegions(const HeapRegion_t *const pxHeapRegions) PRIVILEGED_FUNCTION;
+void vPortDefineHeapRegions(const HeapRegion_t *const pxHeapRegions) PRIVILEGED_FUNCTION;
 
-	/*
+/*
  * Returns a HeapStats_t structure filled with information about the current
  * heap state.
  */
-	void vPortGetHeapStats(HeapStats_t *pxHeapStats);
+void vPortGetHeapStats(HeapStats_t *pxHeapStats);
 
-	/*
+/*
  * Map to the memory management routines required for the port.
  */
-	void *pvPortMalloc(size_t xSize) PRIVILEGED_FUNCTION;
-	void vPortFree(void *pv) PRIVILEGED_FUNCTION;
-	void vPortInitialiseBlocks(void) PRIVILEGED_FUNCTION;
-	size_t xPortGetFreeHeapSize(void) PRIVILEGED_FUNCTION;
-	size_t xPortGetMinimumEverFreeHeapSize(void) PRIVILEGED_FUNCTION;
+void  *pvPortMalloc(size_t xSize) PRIVILEGED_FUNCTION;
+void   vPortFree(void *pv) PRIVILEGED_FUNCTION;
+void   vPortInitialiseBlocks(void) PRIVILEGED_FUNCTION;
+size_t xPortGetFreeHeapSize(void) PRIVILEGED_FUNCTION;
+size_t xPortGetMinimumEverFreeHeapSize(void) PRIVILEGED_FUNCTION;
 
-	/*
+/*
  * Setup the hardware ready for the scheduler to take control.  This generally
  * sets up a tick interrupt and sets timers for the correct tick frequency.
  */
-	BaseType_t xPortStartScheduler(void) PRIVILEGED_FUNCTION;
+BaseType_t xPortStartScheduler(void) PRIVILEGED_FUNCTION;
 
-	/*
+/*
  * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
  * the hardware is left in its original condition after the scheduler stops
  * executing.
  */
-	void vPortEndScheduler(void) PRIVILEGED_FUNCTION;
+void vPortEndScheduler(void) PRIVILEGED_FUNCTION;
 
 /*
  * The structures and methods of manipulating the MPU are contained within the
@@ -187,8 +188,8 @@ that together comprise the total FreeRTOS heap space. */
  * contained in xRegions.
  */
 #if (portUSING_MPU_WRAPPERS == 1)
-	struct xMEMORY_REGION;
-	void vPortStoreTaskMPUSettings(xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION *const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth) PRIVILEGED_FUNCTION;
+struct xMEMORY_REGION;
+void vPortStoreTaskMPUSettings(xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION *const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth) PRIVILEGED_FUNCTION;
 #endif
 
 #ifdef __cplusplus
diff --git a/source/build.sh b/source/build.sh
index 643af510..ce75418e 100755
--- a/source/build.sh
+++ b/source/build.sh
@@ -7,7 +7,7 @@ TRANSLATION_SCRIPT="make_translation.py"
 # AVAILABLE_LANGUAGES will be calculating according to json files in $TRANSLATION_DIR
 AVAILABLE_LANGUAGES=()
 BUILD_LANGUAGES=()
-AVAILABLE_MODELS=("TS100" "TS80" "TS80P" "Pinecil" "MHP30")
+AVAILABLE_MODELS=("TS100" "TS80" "TS80P" "Pinecil" "MHP30" "Pinecilv2")
 BUILD_MODELS=()
 
 usage() {