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Merge Dev into mainline (#1)
* Removing USB Need to refine the drive to the iron tip * Update README.md * * Rewrite all code from scratch * Only kept settings * New font * New PID * New Menus * Use Hardware I2C * Faster System * Better Heating Time * No USB * Full Menu System
This commit is contained in:
Ben V. Brown
GitHub
@@ -1,19 +1,91 @@
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/********************* (C) COPYRIGHT 2015 e-Design Co.,Ltd. **********************
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File Name : MMA8652FC.h
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Version : S100 APP Ver 2.11
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Description:
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Author : Celery
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Data: 2015/07/07
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History:
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2015/07/07 ͳһ<CDB3><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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*******************************************************************************/
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/*
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* MMA8652FC.*
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* Files for the built in accelerometer from NXP.
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* This sets the unit up in motion detection mode with an interrupt on movement
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* This interrupt is fed to PB5 which catches it via EXTI5
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*
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* http://cache.freescale.com/files/sensors/doc/data_sheet/MMA8652FC.pdf
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*
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* EXTI Motion config setup values lifted from AN4070 from NXP
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* #defines also taken from ^
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*
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* Ben V. Brown - <ralim@ralimtek.com>
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*/
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#ifndef __MMA8652FC__H
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#define __MMA8652FC__H
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void StartUp_Accelerometer(void);//This is the only function we expose
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//--------------MMA8652 Device ID----------------------------------------------//
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#define DEVICE_ADDR 0X1D
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//--------------MMA8652 Registers-------------------------------------------//
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#define STATUS_REG 0x00 // STATUS Register
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#define OUT_X_MSB_REG 0x01 // [7:0] are 8 MSBs of the 14-bit X-axis sample
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#define OUT_X_LSB_REG 0x02 // [7:2] are the 6 LSB of 14-bit X-axis sample
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#define OUT_Y_MSB_REG 0x03 // [7:0] are 8 MSBs of the 14-bit Y-axis sample
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#define OUT_Y_LSB_REG 0x04 // [7:2] are the 6 LSB of 14-bit Y-axis sample
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#define OUT_Z_MSB_REG 0x05 // [7:0] are 8 MSBs of the 14-bit Z-axis sample
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#define OUT_Z_LSB_REG 0x06 // [7:2] are the 6 LSB of 14-bit Z-axis sample
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#define F_SETUP_REG 0x09 // F_SETUP FIFO Setup Register
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#define TRIG_CFG_REG 0x0A // TRIG_CFG Map of FIFO data capture events
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#define SYSMOD_REG 0x0B // SYSMOD System Mode Register
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#define INT_SOURCE_REG 0x0C // INT_SOURCE System Interrupt Status Register
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#define WHO_AM_I_REG 0x0D // WHO_AM_I Device ID Register
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#define XYZ_DATA_CFG_REG 0x0E // XYZ_DATA_CFG Sensor Data Configuration Register
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#define HP_FILTER_CUTOFF_REG 0x0F // HP_FILTER_CUTOFF High Pass Filter Register
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#define PL_STATUS_REG 0x10 // PL_STATUS Portrait/Landscape Status Register
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#define PL_CFG_REG 0x11 // PL_CFG Portrait/Landscape Configuration Register
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#define PL_COUNT_REG 0x12 // PL_COUNT Portrait/Landscape Debounce Register
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#define PL_BF_ZCOMP_REG 0x13 // PL_BF_ZCOMP Back/Front and Z Compensation Register
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#define P_L_THS_REG 0x14 // P_L_THS Portrait to Landscape Threshold Register
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#define FF_MT_CFG_REG 0x15 // FF_MT_CFG Freefall and Motion Configuration Register
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#define FF_MT_SRC_REG 0x16 // FF_MT_SRC Freefall and Motion Source Register
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#define FF_MT_THS_REG 0x17 // FF_MT_THS Freefall and Motion Threshold Register
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#define FF_MT_COUNT_REG 0x18 // FF_MT_COUNT Freefall Motion Count Register
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#define TRANSIENT_CFG_REG 0x1D // TRANSIENT_CFG Transient Configuration Register
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#define TRANSIENT_SRC_REG 0x1E // TRANSIENT_SRC Transient Source Register
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#define TRANSIENT_THS_REG 0x1F // TRANSIENT_THS Transient Threshold Register
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#define TRANSIENT_COUNT_REG 0x20 // TRANSIENT_COUNT Transient Debounce Counter Register
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#define PULSE_CFG_REG 0x21 // PULSE_CFG Pulse Configuration Register
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#define PULSE_SRC_REG 0x22 // PULSE_SRC Pulse Source Register
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#define PULSE_THSX_REG 0x23 // PULSE_THS XYZ Pulse Threshold Registers
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#define PULSE_THSY_REG 0x24
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#define PULSE_THSZ_REG 0x25
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#define PULSE_TMLT_REG 0x26 // PULSE_TMLT Pulse Time Window Register
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#define PULSE_LTCY_REG 0x27 // PULSE_LTCY Pulse Latency Timer Register
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#define PULSE_WIND_REG 0x28 // PULSE_WIND Second Pulse Time Window Register
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#define ASLP_COUNT_REG 0x29 // ASLP_COUNT Auto Sleep Inactivity Timer Register
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#define CTRL_REG1 0x2A // CTRL_REG1 System Control 1 Register
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#define CTRL_REG2 0x2B // CTRL_REG2 System Control 2 Register
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#define CTRL_REG3 0x2C // CTRL_REG3 Interrupt Control Register
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#define CTRL_REG4 0x2D // CTRL_REG4 Interrupt Enable Register
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#define CTRL_REG5 0x2E // CTRL_REG5 Interrupt Configuration Register
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#define OFF_X_REG 0x2F // XYZ Offset Correction Registers
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#define OFF_Y_REG 0x30
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#define OFF_Z_REG 0x31
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//MMA8652FC 7-bit I2C address
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#define MMA8652FC_I2C_ADDRESS 0x1D // MMA865xFC 7-bit I2C address is fixed
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//MMA8652FC Sensitivity
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#define SENSITIVITY_2G 1024
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#define SENSITIVITY_4G 512
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#define SENSITIVITY_8G 256
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#define STATUS_REG 0x00
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#define X_MSB_REG 0X01
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#define X_LSB_REG 0X02
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@@ -27,15 +99,8 @@ History:
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#define INT_SOURCE 0X0C
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#define DEVICE_ID 0X0D
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#define XYZ_DATA_CFG_REG 0X0E
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#define CTRL_REG1 0X2A //
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#define CTRL_REG2 0X2B //System Control 2 register
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#define CTRL_REG3 0X2C //
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#define CTRL_REG4 0X2D //Interrupt Enable register
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#define CTRL_REG5 0X2E //
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//-----STATUS_REG(0X00)-----Bit Define----------------------------------------//
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#define ZYXDR_BIT 0X08
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//----XYZ_DATA_CFG_REG(0xE)-Bit Define----------------------------------------//
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@@ -54,7 +119,7 @@ History:
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#define FHZ2 0x5 //12.5hz
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#define FHZ1 0x6 //6.25hz
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#define FHZ0 0x7 //1.563hz
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#define DataRateValue FHZ100
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//---------CTRL_REG2(0X2B)Bit Define------------------------------------------//
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#define MODS_MASK 0x03 //Oversampling Mode 4
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#define Normal_Mode 0x0 //Normal=0,Low Noise Low Power MODS=1,
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@@ -70,16 +135,5 @@ History:
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#define INT_EN_FF_MT 1<<2 //Freefall/Motion Interrupt Enable
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#define INT_EN_DRDY 1<<0 //Data Ready Interrupt Enable
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u16 Get_MmaShift(void);
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void Set_MmaShift(u16 shift);
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u16 Get_MmaActive(void);
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void MMA865x_Standby(void);
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void MMA865x_Active(void);
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u16 Cheak_XYData(u16 x0,u16 y0,u16 x1,u16 y1);
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u16 Update_X(void);
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u16 Update_Y(void);
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u16 Update_Z(void);
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void Check_Accelerated(void);
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void StartUp_Accelerated(void);
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#endif
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/******************************** END OF FILE *********************************/
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